PSMN165-200K,118 [NXP]

N-channel TrenchMOS SiliconMAX standard level FET SOIC 8-Pin;
PSMN165-200K,118
型号: PSMN165-200K,118
厂家: NXP    NXP
描述:

N-channel TrenchMOS SiliconMAX standard level FET SOIC 8-Pin

文件: 总12页 (文件大小:213K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
PSMN165-200K  
N-channel TrenchMOS SiliconMAX standard level FET  
Rev. 02 — 3 December 2009  
Product data sheet  
1. Product profile  
1.1 General description  
SiliconMAX standard level N-channel enhancement mode Field-Effect Transistor (FET) in  
a plastic package using TrenchMOS technology. This product is designed and qualified for  
use in computing, communications, consumer and industrial applications only.  
1.2 Features and benefits  
„ Low conduction losses due to low  
„ Suitable for high frequency  
applications due to fast switching  
characteristics  
on-state resistance  
1.3 Applications  
„ Computer motherboards  
„ DC-to-DC convertors  
„ Switched-mode power supplies  
1.4 Quick reference data  
Table 1.  
Quick reference  
Symbol Parameter  
Conditions  
drain-source voltage Tj 25 °C; Tj 150 °C  
Min  
Typ  
Max Unit  
VDS  
ID  
-
-
-
-
200  
2.9  
V
A
drain current  
Tsp = 80 °C;  
see Figure 1 and 3  
Ptot  
total power  
dissipation  
Tsp = 80 °C;  
see Figure 2  
-
-
-
3.5  
W
Dynamic characteristics  
QGD gate-drain charge  
VGS = 10 V; ID = 3 A;  
VDS = 100 V; Tj = 25 °C;  
see Figure 11  
12  
16.5 nC  
Static characteristics  
RDSon  
drain-source  
on-state resistance  
VGS = 10 V; ID = 2.5 A;  
Tj = 25 °C;  
-
130  
165  
mΩ  
see Figure 9 and 10  
 
 
 
 
 
PSMN165-200K  
NXP Semiconductors  
N-channel TrenchMOS SiliconMAX standard level FET  
2. Pinning information  
Table 2.  
Pinning information  
Pin  
1
Symbol Description  
Simplified outline  
Graphic symbol  
S
S
S
G
D
D
D
D
source  
source  
source  
gate  
8
5
4
D
2
3
G
4
mbb076  
S
5
drain  
1
6
drain  
SOT96-1 (SO8)  
7
drain  
8
drain  
3. Ordering information  
Table 3.  
Ordering information  
Type number  
Package  
Name  
SO8  
Description  
plastic small outline package; 8 leads; body width 3.9 mm  
Version  
PSMN165-200K  
SOT96-1  
4. Limiting values  
Table 4.  
Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134).  
Symbol  
VDS  
VGS  
ID  
Parameter  
Conditions  
Min  
-
Max  
200  
Unit  
drain-source voltage  
gate-source voltage  
drain current  
Tj 25 °C; Tj 150 °C  
V
-20  
-
20  
V
Tsp = 80 °C; see Figure 1 and 3  
2.9  
20  
A
IDM  
peak drain current  
Tsp = 25 °C; tp 10 µs; pulsed  
-
A
Ptot  
Tstg  
Tj  
total power dissipation Tsp = 80 °C; see Figure 2  
storage temperature  
-
3.5  
150  
150  
W
°C  
°C  
-55  
-55  
junction temperature  
Source-drain diode  
IS  
source current  
peak source current  
Tsp = 80 °C  
-
-
3.1  
20  
A
A
ISM  
Tsp = 25 °C; tp 10 µs; pulsed  
PSMN165-200K_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 3 December 2009  
2 of 12  
 
 
 
PSMN165-200K  
NXP Semiconductors  
N-channel TrenchMOS SiliconMAX standard level FET  
03aa25  
03aa17  
120  
120  
I
P
der  
der  
(%)  
(%)  
80  
80  
40  
40  
0
0
0
50  
100  
150  
200  
0
50  
100  
150  
200  
T
sp  
(°C)  
T
sp  
(°C)  
Fig 1. Normalized continuous drain current as a  
function of solder point temperature  
Fig 2. Normalized total power dissipation as a  
function of solder point temperature  
03ae06  
2
10  
R
DSon  
= V /I  
DS D  
I
D
(A)  
10  
t
p
= 10 µs  
100  
µs  
1 ms  
1
10 ms  
t
p
D.C.  
P
δ =  
T
100 ms  
1  
10  
t
t
p
T
2  
10  
2
3
1
10  
10  
10  
V
DS  
(V)  
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage  
PSMN165-200K_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 3 December 2009  
3 of 12  
PSMN165-200K  
NXP Semiconductors  
N-channel TrenchMOS SiliconMAX standard level FET  
5. Thermal characteristics  
Table 5.  
Symbol  
Rth(j-sp)  
Thermal characteristics  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
thermal resistance from mounted on a metal clad substrate;  
junction to solder point see Figure 4  
-
-
20  
K/W  
03ae05  
2
10  
Z
th(j-sp)  
(K/W)  
δ = 0.5  
10  
0.2  
0.1  
0.05  
1
0.02  
t
p
P
δ =  
T
1  
10  
single pulse  
t
t
p
T
2  
10  
10  
4  
3  
2  
1  
2
10  
10  
10  
1
10  
10  
t
p
(s)  
Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration  
PSMN165-200K_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 3 December 2009  
4 of 12  
 
 
PSMN165-200K  
NXP Semiconductors  
N-channel TrenchMOS SiliconMAX standard level FET  
6. Characteristics  
Table 6.  
Symbol  
Characteristics  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
Static characteristics  
V(BR)DSS  
drain-source  
breakdown voltage  
ID = 250 µA; VGS = 0 V; Tj = 25 °C  
200  
1.2  
-
240  
-
V
V
V
V
VGS(th)  
gate-source threshold ID = 1 mA; VDS= VGS; Tj = 150 °C;  
voltage  
-
-
-
-
see Figure 8  
ID = 1 mA; VDS= VGS; Tj = -55 °C;  
see Figure 8  
6
4
ID = 1 mA; VDS= VGS; Tj = 25 °C;  
see Figure 8  
2
IDSS  
drain leakage current  
gate leakage current  
VDS = 160 V; VGS = 0 V; Tj = 25 °C  
VDS = 200 V; VGS = 0 V; Tj = 150 °C  
VGS = 20 V; VDS = 0 V; Tj = 25 °C  
VGS = -20 V; VDS = 0 V; Tj = 25 °C  
-
-
-
-
-
-
1
µA  
mA  
nA  
-
0.5  
100  
100  
413  
IGSS  
-
-
nA  
RDSon  
drain-source on-state  
resistance  
VGS = 10 V; ID = 2.5 A; Tj = 150 °C;  
see Figure 9 and 10  
325  
mΩ  
VGS = 10 V; ID = 2.5 A; Tj = 25 °C;  
-
130  
165  
mΩ  
see Figure 9 and 10  
Dynamic characteristics  
QG(tot)  
QGS  
QGD  
Ciss  
total gate charge  
gate-source charge  
gate-drain charge  
input capacitance  
output capacitance  
ID = 3 A; VDS = 100 V; VGS = 10 V;  
Tj = 25 °C; see Figure 11  
-
-
-
-
-
-
40  
-
nC  
nC  
nC  
pF  
pF  
pF  
4.5  
12  
-
16.5  
VDS = 25 V; VGS = 0 V; f = 1 MHz;  
Tj = 25 °C; see Figure 12  
1330  
140  
70  
-
-
-
Coss  
Crss  
reverse transfer  
capacitance  
td(on)  
tr  
td(off)  
tf  
turn-on delay time  
rise time  
VDS = 100 V; RL = 100 ; VGS = 10 V;  
RG(ext) = 6 ; Tj = 25 °C  
-
-
-
-
-
12  
11  
50  
25  
10  
25  
25  
80  
40  
-
ns  
ns  
ns  
ns  
S
turn-off delay time  
fall time  
gfs  
transfer conductance  
VDS = 15 V; ID = 2.9 A; Tj = 25 °C;  
see Figure 13  
Source-drain diode  
VSD  
source-drain voltage  
IS = 2.3 A; VGS = 0 V; Tj = 25 °C;  
see Figure 14  
-
0.7  
1.1  
V
trr  
reverse recovery time  
recovered charge  
IS = 2.9 A; dIS/dt = -100 A/µs; VGS = 0 V;  
VDS = 25 V; Tj = 25 °C  
-
-
105  
-
-
ns  
Qr  
0.45  
µC  
PSMN165-200K_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 3 December 2009  
5 of 12  
 
PSMN165-200K  
NXP Semiconductors  
N-channel TrenchMOS SiliconMAX standard level FET  
03ae07  
03ae09  
20  
20  
V
= 10 V  
5 V  
GS  
V
> I X R  
D
DS  
DSon  
I
D
I
D
(A)  
(A)  
15  
15  
4.5 V  
10  
5
10  
5
4 V  
T = 150 °C  
25 °C  
j
3.5 V  
0
0
0
1
2
3
4
5
0
1
2
3
4
5
V
(V)  
GS  
V
(V)  
DS  
Fig 5. Output characteristics: drain current as a  
function of drain-source voltage; typical values  
Fig 6. Transfer characteristics: drain current as a  
function of gate-source voltage; typical values  
03aa35  
03aa32  
1  
10  
5
I
V
D
GS(th)  
(V)  
(A)  
min  
typ  
max  
2  
3  
4  
5  
6  
10  
10  
10  
10  
10  
4
max  
3
typ  
2
min  
1
0
0
2
4
6
60  
0
60  
120  
180  
V
GS  
(V)  
T (°C)  
j
Fig 7. Sub-threshold drain current as a function of  
gate-source voltage  
Fig 8. Gate-source threshold voltage as a function of  
junction temperature  
PSMN165-200K_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 3 December 2009  
6 of 12  
PSMN165-200K  
NXP Semiconductors  
N-channel TrenchMOS SiliconMAX standard level FET  
03aa31  
03ae08  
3
0.3  
V
= 4 V  
4.5 V  
T = 25 °C  
j
GS  
R
DSon  
a
2
(Ω)  
0.25  
0.2  
0.15  
0.1  
5 V  
10 V  
1
0
-60  
0
60  
120  
180  
0
5
10  
15  
20  
I
(A)  
D
T ( C)  
°
j
Fig 9. Drain-source on-state resistance as a function  
of drain current; typical values  
Fig 10. Normalized drain-source on-state resistance  
factor as a function of junction temperature  
03ae12  
03ae13  
4
10  
10  
I
= 3 A  
D
V
GS  
C
,
iss  
C
,
oss  
(V)  
T = 25 °C  
j
C
rss  
8
6
4
2
0
(pF)  
V
= 40 V 100 V 160 V  
DD  
C
iss  
3
10  
10  
C
C
oss  
rss  
2
10  
1  
2
0
15  
30  
45  
10  
1
10  
10  
Q
(nC)  
G
V
(V)  
DS  
Fig 11. Gate-source voltage as a function of gate  
charge; typical values  
Fig 12. Input, output and reverse transfer capacitances  
as a function of drain-source voltage; typical  
values  
PSMN165-200K_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 3 December 2009  
7 of 12  
PSMN165-200K  
NXP Semiconductors  
N-channel TrenchMOS SiliconMAX standard level FET  
03ae10  
03ae11  
30  
fs  
(S)  
25  
20  
g
V
> I X R  
D
V
= 0 V  
DS  
DSon  
GS  
I
S
(A)  
T = 25 °C  
j
15  
20  
15  
10  
5
150 °C  
10  
5
T = 150 °C  
25 °C  
j
0
0
0
5
10  
15  
20  
0
0.2  
0.4  
0.6  
0.8  
1
I
(A)  
V
(V)  
D
SD  
Fig 13. Forward transconductance as a function of  
drain current; typical values  
Fig 14. Source current as a function of source-drain  
voltage; typical values  
PSMN165-200K_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 3 December 2009  
8 of 12  
PSMN165-200K  
NXP Semiconductors  
N-channel TrenchMOS SiliconMAX standard level FET  
7. Package outline  
SO8: plastic small outline package; 8 leads; body width 3.9 mm  
SOT96-1  
D
E
A
X
v
c
y
H
M
A
E
Z
5
8
Q
A
2
A
(A )  
3
A
1
pin 1 index  
θ
L
p
L
1
4
e
w
M
detail X  
b
p
0
2.5  
5 mm  
scale  
DIMENSIONS (inch dimensions are derived from the original mm dimensions)  
A
(1)  
(1)  
(2)  
UNIT  
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.  
0.25  
0.10  
1.45  
1.25  
0.49  
0.36  
0.25  
0.19  
5.0  
4.8  
4.0  
3.8  
6.2  
5.8  
1.0  
0.4  
0.7  
0.6  
0.7  
0.3  
mm  
1.27  
0.05  
1.05  
0.041  
1.75  
0.25  
0.01  
0.25  
0.01  
0.25  
0.1  
8o  
0o  
0.010 0.057  
0.004 0.049  
0.019 0.0100 0.20  
0.014 0.0075 0.19  
0.16  
0.15  
0.244  
0.228  
0.039 0.028  
0.016 0.024  
0.028  
0.012  
inches 0.069  
0.01 0.004  
Notes  
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.  
2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
99-12-27  
03-02-18  
SOT96-1  
076E03  
MS-012  
Fig 15. Package outline SOT96-1 (SO8)  
PSMN165-200K_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 3 December 2009  
9 of 12  
 
PSMN165-200K  
NXP Semiconductors  
N-channel TrenchMOS SiliconMAX standard level FET  
8. Revision history  
Table 7.  
Revision history  
Document ID  
Release date  
Data sheet status  
Change notice  
Supersedes  
PSMN165-200K_2  
Modifications:  
20091203  
Product data sheet  
-
PSMN165-200K-01  
The format of this data sheet has been redesigned to comply with the new identity  
guidelines of NXP Semiconductors.  
Legal texts have been adapted to the new company name where appropriate.  
PSMN165-200K-01  
20010116  
Product specification  
-
-
PSMN165-200K_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 3 December 2009  
10 of 12  
 
PSMN165-200K  
NXP Semiconductors  
N-channel TrenchMOS SiliconMAX standard level FET  
9. Legal information  
9.1 Data sheet status  
Document status[1][2]  
Product status[3]  
Development  
Definition  
Objective [short] data sheet  
This document contains data from the objective specification for product development.  
This document contains data from the preliminary specification.  
This document contains the product specification.  
Preliminary [short] data sheet Qualification  
Product [short] data sheet Production  
[1]  
[2]  
[3]  
Please consult the most recently issued document before initiating or completing a design.  
The term 'short data sheet' is explained in section "Definitions".  
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product  
status information is available on the Internet at URLhttp://www.nxp.com.  
Applications— Applications that are described herein for any of these  
9.2 Definitions  
products are for illustrative purposes only. NXP Semiconductors makes no  
representation or warranty that such applications will be suitable for the  
specified use without further testing or modification.  
Draft— The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. NXP Semiconductors does not give any  
representations or warranties as to the accuracy or completeness of  
information included herein and shall have no liability for the consequences of  
use of such information.  
Quick reference data— The Quick reference data is an extract of the  
product data given in the Limiting values and Characteristics sections of this  
document, and as such is not complete, exhaustive or legally binding.  
Limiting values— Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) may cause permanent  
damage to the device. Limiting values are stress ratings only and operation of  
the device at these or any other conditions above those given in the  
Characteristics sections of this document is not implied. Exposure to limiting  
values for extended periods may affect device reliability.  
Short data sheet— A short data sheet is an extract from a full data sheet with  
the same product type number(s) and title. A short data sheet is intended for  
quick reference only and should not be relied upon to contain detailed and full  
information. For detailed and full information see the relevant full data sheet,  
which is available on request via the local NXP Semiconductors sales office.  
In case of any inconsistency or conflict with the short data sheet, the full data  
sheet shall prevail.  
Terms and conditions of sale— NXP Semiconductors products are sold  
subject to the general terms and conditions of commercial sale, as published  
athttp://www.nxp.com/profile/terms, including those pertaining to warranty,  
intellectual property rights infringement and limitation of liability, unless  
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of  
any inconsistency or conflict between information in this document and such  
terms and conditions, the latter will prevail.  
9.3 Disclaimers  
General— Information in this document is believed to be accurate and  
reliable. However, NXP Semiconductors does not give any representations or  
warranties, expressed or implied, as to the accuracy or completeness of such  
information and shall have no liability for the consequences of use of such  
information.  
No offer to sell or license— Nothing in this document may be interpreted or  
construed as an offer to sell products that is open for acceptance or the grant,  
conveyance or implication of any license under any copyrights, patents or  
other industrial or intellectual property rights.  
Right to make changes— NXP Semiconductors reserves the right to make  
changes to information published in this document, including without  
limitation specifications and product descriptions, at any time and without  
notice. This document supersedes and replaces all information supplied prior  
to the publication hereof.  
Export control— This document as well as the item(s) described herein may  
be subject to export control regulations. Export might require a prior  
authorization from national authorities.  
Suitability for use— NXP Semiconductors products are not designed,  
authorized or warranted to be suitable for use in medical, military, aircraft,  
space or life support equipment, nor in applications where failure or  
malfunction of an NXP Semiconductors product can reasonably be expected  
to result in personal injury, death or severe property or environmental  
damage. NXP Semiconductors accepts no liability for inclusion and/or use of  
NXP Semiconductors products in such equipment or applications and  
therefore such inclusion and/or use is at the customer’s own risk.  
9.4 Trademarks  
Notice: All referenced brands, product names, service names and trademarks  
are the property of their respective owners.  
TrenchMOS— is a trademark of NXP B.V.  
10. Contact information  
For more information, please visit:http://www.nxp.com  
For sales office addresses, please send an email to:salesaddresses@nxp.com  
PSMN165-200K_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 3 December 2009  
11 of 12  
 
 
 
 
 
 
 
 
 
PSMN165-200K  
NXP Semiconductors  
N-channel TrenchMOS SiliconMAX standard level FET  
11. Contents  
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1  
1.1  
1.2  
1.3  
1.4  
General description . . . . . . . . . . . . . . . . . . . . . .1  
Features and benefits. . . . . . . . . . . . . . . . . . . . .1  
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1  
Quick reference data . . . . . . . . . . . . . . . . . . . . .1  
2
3
4
5
6
7
8
Pinning information. . . . . . . . . . . . . . . . . . . . . . .2  
Ordering information. . . . . . . . . . . . . . . . . . . . . .2  
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2  
Thermal characteristics . . . . . . . . . . . . . . . . . . .4  
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .5  
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9  
Revision history. . . . . . . . . . . . . . . . . . . . . . . . .10  
9
Legal information. . . . . . . . . . . . . . . . . . . . . . . .11  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . .11  
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .11  
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .11  
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .11  
9.1  
9.2  
9.3  
9.4  
10  
Contact information. . . . . . . . . . . . . . . . . . . . . .11  
Please be aware that important notices concerning this document and the product(s)  
described herein, have been included in section ‘Legal information’.  
© NXP B.V. 2009.  
All rights reserved.  
For more information, please visit: http://www.nxp.com  
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Date of release: 3 December 2009  
Document identifier: PSMN165-200K_2  

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