PSMN5R0-80BS [NXP]
N-channel 80 V, 5.1 mΩ standard level MOSFET in D2PAK; 在D2PAK N沟道80 V, 5.1英里©标准级MOSFET型号: | PSMN5R0-80BS |
厂家: | NXP |
描述: | N-channel 80 V, 5.1 mΩ standard level MOSFET in D2PAK |
文件: | 总15页 (文件大小:220K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PSMN5R0-80BS
AK
D2P
N-channel 80 V, 5.1 mΩ standard level MOSFET in D2PAK
Rev. 1 — 20 March 2012
Product data sheet
1. Product profile
1.1 General description
Standard level N-channel MOSFET in SOT404 package qualified to 175 °C. This product
is designed and qualified for use in a wide range of industrial, communications and
domestic equipment.
1.2 Features and benefits
High efficiency due to low switching
Suitable for standard level gate drive
and conduction losses
sources
1.3 Applications
DC-to-DC converters
Load switching
Motor control
Server power supplies
1.4 Quick reference data
Table 1.
Symbol
VDS
Quick reference data
Parameter
Conditions
Min
Typ
Max
80
Unit
V
drain-source voltage
drain current
Tj ≥ 25 °C; Tj ≤ 175 °C
-
-
-
-
[1]
ID
Tmb = 25 °C; VGS = 10 V;
see Figure 1
100
A
Ptot
Tj
total power dissipation
junction temperature
Tmb = 25 °C; see Figure 2
-
-
-
270
175
W
-55
°C
Static characteristics
RDSon
drain-source on-state resistance VGS = 10 V; ID = 25 A; Tj = 100 °C;
see Figure 13; see Figure 12
-
-
7.19
4.36
8.5
5.1
mΩ
mΩ
VGS = 10 V; ID = 25 A; Tj = 25 °C;
see Figure 12
Dynamic characteristics
QGD
gate-drain charge
total gate charge
VGS = 10 V; ID = 25 A; VDS = 40 V;
see Figure 14; see Figure 15
-
-
21
-
-
nC
nC
QG(tot)
101
Avalanche ruggedness
EDS(AL)S non-repetitive drain-source
avalanche energy
VGS = 10 V; Tj(init) = 25 °C;
ID = 100 A; Vsup ≤ 80 V; RGS = 50 Ω;
unclamped
-
-
396
mJ
[1] Continuous current is limited by package
PSMN5R0-80BS
NXP Semiconductors
N-channel 80 V, 5.1 mΩ standard level MOSFET in D2PAK
2. Pinning information
Table 2.
Pinning information
Symbol Description
Pin
1
Simplified outline
Graphic symbol
G
D
S
D
gate
drain[1]
mb
D
S
2
3
source
G
mb
mounting base; connected to drain
mbb076
2
1
3
SOT404 (D2PAK)
[1] It is not possible to make connection to pin 2
3. Ordering information
Table 3.
Ordering information
Type number
Package
Name
Description
Version
PSMN5R0-80BS
D2PAK
plastic single-ended surface-mounted package (D2PAK); 3 leads SOT404
(one lead cropped)
4. Marking
Table 4.
Marking codes
Type number
PSMN5R0-80BS
Marking code
PSMN5R0-80BS
PSMN5R0-80BS
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 20 March 2012
2 of 15
PSMN5R0-80BS
NXP Semiconductors
N-channel 80 V, 5.1 mΩ standard level MOSFET in D2PAK
5. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDS
Parameter
Conditions
Min
Max
80
Unit
V
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
Tj ≥ 25 °C; Tj ≤ 175 °C
Tj ≥ 25 °C; Tj ≤ 175 °C; RGS = 20 kΩ
-
VDGR
VGS
-
80
V
-20
20
V
[1]
[1]
ID
VGS = 10 V; Tmb = 100 °C; see Figure 1
VGS = 10 V; Tmb = 25 °C; see Figure 1
pulsed; tp ≤ 10 µs; Tmb = 25 °C; see Figure 3
Tmb = 25 °C; see Figure 2
-
100
100
598
270
175
175
260
A
-
A
IDM
peak drain current
-
A
Ptot
Tstg
Tj
total power dissipation
storage temperature
junction temperature
peak soldering temperature
-
W
°C
°C
°C
-55
-55
-
Tsld(M)
Source-drain diode
[1]
IS
source current
peak source current
Tmb = 25 °C
-
-
100
598
A
A
ISM
pulsed; tp ≤ 10 µs; Tmb = 25 °C
Avalanche ruggedness
EDS(AL)S non-repetitive drain-source
avalanche energy
VGS = 10 V; Tj(init) = 25 °C; ID = 100 A;
Vsup ≤ 80 V; RGS = 50 Ω; unclamped
-
396
mJ
[1] Continuous current is limited by package
003aad078
03aa16
120
150
ID
P
(%)
der
(A)
80
100
(1)
50
40
0
0
0
50
100
150
200
0
50
100
150
200
Tmb (°C)
T
(°C)
mb
Fig 1. Continuous drain current as a function of
mounting base temperature
Fig 2. Normalized total power dissipation as a
function of mounting base temperature
PSMN5R0-80BS
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 20 March 2012
3 of 15
PSMN5R0-80BS
NXP Semiconductors
N-channel 80 V, 5.1 mΩ standard level MOSFET in D2PAK
003aad299
103
Limit RDSon = VDS / ID
ID
(A)
t = 10
s
μ
p
102
10
100 μs
(1)
DC
1 ms
10 ms
1
100 ms
10-1
10-1
1
10
102
103
VDS (V)
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PSMN5R0-80BS
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 20 March 2012
4 of 15
PSMN5R0-80BS
NXP Semiconductors
N-channel 80 V, 5.1 mΩ standard level MOSFET in D2PAK
6. Thermal characteristics
Table 6.
Symbol
Rth(j-mb)
Thermal characteristics
Parameter
Conditions
Min
Typ
Max
Unit
thermal resistance from junction to
mounting base
see Figure 4
-
0.3
0.56
K/W
Rth(j-a)
thermal resistance from junction to
ambient
Minimum footprint; mounted on a
printed circuit board
-
50
-
K/W
003aad080
1
Zth(j-mb)
(K/W)
δ = 0.5
10-1
0.2
0.1
0.05
0.02
10-2
10-3
10-4
tp
δ =
P
T
single shot
t
tp
T
10-6
10-5
10-4
10-3
10-2
10-1
tp (s)
1
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration; typical
values
PSMN5R0-80BS
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 20 March 2012
5 of 15
PSMN5R0-80BS
NXP Semiconductors
N-channel 80 V, 5.1 mΩ standard level MOSFET in D2PAK
7. Characteristics
Table 7.
Tested to JEDEC standards where applicable.
Symbol Parameter Conditions
Static characteristics
V(BR)DSS
Characteristics
Min
Typ
Max
Unit
drain-source breakdown voltage ID = 250 µA; VGS = 0 V; Tj = -55 °C
ID = 250 µA; VGS = 0 V; Tj = 25 °C
73
80
1
-
-
-
-
-
-
V
V
V
VGS(th)
gate-source threshold voltage
ID = 1 mA; VDS = VGS; Tj = 175 °C;
see Figure 10
ID = 1 mA; VDS = VGS; Tj = -55 °C;
see Figure 10
-
-
4.6
4
V
V
ID = 1 mA; VDS = VGS; Tj = 25 °C;
see Figure 11; see Figure 10
2
3
IDSS
drain leakage current
gate leakage current
VDS = 80 V; VGS = 0 V; Tj = 25 °C
VDS = 80 V; VGS = 0 V; Tj = 125 °C
VGS = -20 V; VDS = 0 V; Tj = 25 °C
VGS = 20 V; VDS = 0 V; Tj = 25 °C
-
-
-
-
-
0.02
-
8
µA
µA
nA
nA
Ω
150
100
100
IGSS
10
10
RDSon
drain-source on-state resistance VGS = 10 V; ID = 25 A; Tj = 175 °C;
see Figure 12; see Figure 13
10.46 12.3
VGS = 10 V; ID = 25 A; Tj = 100 °C;
see Figure 13; see Figure 12
-
-
-
7.19
4.36
0.95
8.5
5.1
-
mΩ
mΩ
Ω
V
GS = 10 V; ID = 25 A; Tj = 25 °C;
see Figure 12
RG
internal gate resistance (AC)
f = 1 MHz
Dynamic characteristics
QG(tot)
total gate charge
ID = 0 A; VDS = 0 V; VGS = 10 V
-
-
-
-
87
-
-
-
-
nC
nC
nC
nC
ID = 25 A; VDS = 40 V; VGS = 10 V;
see Figure 14; see Figure 15
101
26
QGS
gate-source charge
QGS(th)
pre-threshold gate-source
charge
18
QGS(th-pl)
post-threshold gate-source
charge
-
8
-
nC
QGD
gate-drain charge
-
-
21
-
-
nC
V
VGS(pl)
gate-source plateau voltage
ID = 25 A; VDS = 40 V; see Figure 14;
see Figure 15
4.2
Ciss
Coss
Crss
td(on)
tr
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
VDS = 40 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; see Figure 16
-
-
-
-
-
-
-
6793
913
350
33
-
-
-
-
-
-
-
pF
pF
pF
ns
ns
ns
ns
VDS = 40 V; RL = 0.5 Ω; VGS = 10 V;
RG(ext) = 4.7 Ω
21
td(off)
tf
turn-off delay time
fall time
73
14
PSMN5R0-80BS
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 20 March 2012
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PSMN5R0-80BS
NXP Semiconductors
N-channel 80 V, 5.1 mΩ standard level MOSFET in D2PAK
Table 7.
Characteristics …continued
Tested to JEDEC standards where applicable.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Source-drain diode
VSD
source-drain voltage
IS = 25 A; VGS = 0 V; Tj = 25 °C;
see Figure 17
-
0.8
1.2
V
trr
reverse recovery time
recovered charge
IS = 25 A; dIS/dt = 100 A/µs;
VGS = 0 V; VDS = 40 V
-
-
56
-
-
ns
Qr
116
nC
003aad081
003aad083
100
250
ID
10
5.5
6
20
ID
(A)
(A)
80
200
150
100
50
5
60
40
20
0
4.5
Tj = 175 °C
25 °C
VGS (V) = 4
0
0
1
2
3
4
0
1
2
3
4
5
V
DS (V)
V
GS (V)
Fig 5. Output characteristics: drain current as a
function of drain-source voltage; typical values
Fig 6. Transfer characteristics: drain current as a
function of gate-source voltage; typical values
003aad087
003aad088
10000
C
140
gfs
(pF)
9000
Ciss
(S)
120
8000
7000
6000
5000
4000
3000
100
80
60
40
20
0
Crss
0
20
40
60
80
100
120
D (A)
2
4
6
8
10
V
GS (V)
I
Fig 7. Input and reverse transfer capacitances as a
function of gate-source voltage; typical values
Fig 8. Forward transconductance as a function of
drain current; typical values
PSMN5R0-80BS
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 20 March 2012
7 of 15
PSMN5R0-80BS
NXP Semiconductors
N-channel 80 V, 5.1 mΩ standard level MOSFET in D2PAK
003aad089
003aad280
5
40
V
GS(th)
(V)
RDSon
(mΩ)
4
3
2
1
0
max
30
20
10
0
typ
min
0
5
10
15
20
−60
0
60
120
180
VGS (V)
T (°C)
j
Fig 9. Drain-source on-state resistance as a function
of gate-source voltage; typical values
Fig 10. Gate-source threshold voltage as a function of
junction temperature
03aa35
003aad082
−1
10
10
I
D
RDSon
(A)
(mΩ)
min
typ
max
−2
−3
−4
−5
−6
VGS (V) = 5
10
8
5.5
10
10
10
10
6
6
4
2
10
20
0
50
100
150
200
250
0
2
4
6
ID (A)
V
(V)
GS
Fig 11. Sub-threshold drain current as a function of
gate-source voltage
Fig 12. Drain-source on-state resistance as a function
of drain current; typical values
PSMN5R0-80BS
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 20 March 2012
8 of 15
PSMN5R0-80BS
NXP Semiconductors
N-channel 80 V, 5.1 mΩ standard level MOSFET in D2PAK
003aad045
2.5
V
DS
a
I
D
2.0
V
GS(pl)
1.5
1.0
0.5
0.0
V
GS(th)
GS
V
Q
Q
GS1
GS2
Q
Q
GD
GS
Q
G(tot)
003aaa508
-60 -30
0
30
60
90 120 150 180
Tj (°C)
Fig 13. Normalized drain-source on-state resistance
factor as a function of junction temperature
Fig 14. Gate charge waveform definitions
003aad085
003aad086
10
104
VGS
(V)
Ciss
8
C
(pF)
6
VDS = 40 V
103
Coss
4
2
0
Crss
102
10-1
0
20
40
60
80
100
120
1
10
102
VDS (V)
Q
G (nC)
Fig 15. Gate-source voltage as a function of gate
charge; typical values
Fig 16. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
PSMN5R0-80BS
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 20 March 2012
9 of 15
PSMN5R0-80BS
NXP Semiconductors
N-channel 80 V, 5.1 mΩ standard level MOSFET in D2PAK
003aad084
100
IS
(A)
80
60
40
20
0
175 °C
Tj = 25 °C
0
0.2
0.4
0.6
0.8
1
1.2
SD (V)
V
Fig 17. Source current as a function of source-drain voltage; typical values
PSMN5R0-80BS
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 20 March 2012
10 of 15
PSMN5R0-80BS
NXP Semiconductors
N-channel 80 V, 5.1 mΩ standard level MOSFET in D2PAK
8. Package outline
Plastic single-ended surface-mounted package (D2PAK); 3 leads (one lead cropped)
SOT404
A
A
E
1
mounting
base
D
1
D
H
D
2
L
p
1
3
c
b
e
e
Q
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
D
E
A
A
b
UNIT
c
D
e
L
H
Q
1
1
p
D
max.
4.50
4.10
1.40
1.27
0.85
0.60
0.64
0.46
1.60
1.20
10.30
9.70
2.90 15.80 2.60
2.10 14.80 2.20
mm
11
2.54
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
05-02-11
06-03-16
SOT404
Fig 18. Package outline SOT404 (D2PAK)
PSMN5R0-80BS
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 20 March 2012
11 of 15
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NXP Semiconductors
N-channel 80 V, 5.1 mΩ standard level MOSFET in D2PAK
9. Revision history
Table 8.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PSMN5R0-80BS v.1
20120320
Product data sheet
-
-
PSMN5R0-80BS
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 20 March 2012
12 of 15
PSMN5R0-80BS
NXP Semiconductors
N-channel 80 V, 5.1 mΩ standard level MOSFET in D2PAK
10. Legal information
10.1 Data sheet status
Document status[1] [2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product
status information is available on the Internet at URLhttp://www.nxp.com.
Right to make changes — NXP Semiconductors reserves the right to make
10.2 Definitions
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Preview — The document is a preview version only. The document is still
subject to formal approval, which may result in modifications or additions.
NXP Semiconductors does not give any representations or warranties as to
the accuracy or completeness of information included herein and shall have
no liability for the consequences of use of such information.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
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applications and therefore such inclusion and/or use is at the customer’s own
risk.
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modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
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full data sheet shall prevail.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Applications — Applications that are described herein for any of these
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representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
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customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
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applications and products.
10.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
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damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
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punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with theTerms and conditions of commercial sale of NXP Semiconductors.
PSMN5R0-80BS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 20 March 2012
13 of 15
PSMN5R0-80BS
NXP Semiconductors
N-channel 80 V, 5.1 mΩ standard level MOSFET in D2PAK
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published athttp://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
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applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
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liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
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Translations — A non-English (translated) version of a document is for
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conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
10.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Export control — This document as well as the item(s) described herein may
be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Adelante,Bitport,Bitsound,CoolFlux,CoReUse,DESFire,EZ-HV,FabKey,G
reenChip,HiPerSmart,HITAG,I²C-bus
logo,ICODE,I-CODE,ITEC,Labelution,MIFARE,MIFARE Plus,MIFARE
Ultralight,MoReUse,QLPAK,Silicon
Tuner,SiliconMAX,SmartXA,STARplug,TOPFET,TrenchMOS,TriMedia
andUCODE — are trademarks of NXP B.V.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
HD Radio andHD Radio logo — are trademarks of iBiquity Digital
Corporation.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
11. Contact information
For more information, please visit:http://www.nxp.com
For sales office addresses, please send an email to:salesaddresses@nxp.com
PSMN5R0-80BS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 20 March 2012
14 of 15
PSMN5R0-80BS
NXP Semiconductors
N-channel 80 V, 5.1 mΩ standard level MOSFET in D2PAK
12. Contents
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General description . . . . . . . . . . . . . . . . . . . . . .1
Features and benefits. . . . . . . . . . . . . . . . . . . . .1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Quick reference data . . . . . . . . . . . . . . . . . . . . .1
1.1
1.2
1.3
1.4
2
3
4
5
6
7
8
9
Pinning information. . . . . . . . . . . . . . . . . . . . . . .2
Ordering information. . . . . . . . . . . . . . . . . . . . . .2
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3
Thermal characteristics . . . . . . . . . . . . . . . . . . .5
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .6
Package outline . . . . . . . . . . . . . . . . . . . . . . . . .11
Revision history. . . . . . . . . . . . . . . . . . . . . . . . .12
10
Legal information. . . . . . . . . . . . . . . . . . . . . . . .13
Data sheet status . . . . . . . . . . . . . . . . . . . . . . .13
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .14
10.1
10.2
10.3
10.4
11
Contact information. . . . . . . . . . . . . . . . . . . . . .14
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 20 March 2012
Document identifier: PSMN5R0-80BS
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