PTN3393BS_技术文档

PTN3393

2-lane DisplayPort to VGA adapter test IC

Rev. 2 — 27 July 2012

Objective product brief

1. General description

The PTN3393 is a DisplayPort to VGA adapter IC designed to connect a DisplayPort

source to a VGA sink. The PTN3393 integrates a DisplayPort receiver and a high-speed

triple video digital-to-analog converter that supports display resolutions from VGA to

WUXGA. The PTN3393 supports either one or two DisplayPort v1.1a lanes operating at

either 2.7 Gbit/s or 1.62 Gbit/s per lane. The PTN3393 supports ‘Flash-over-AUX’

capability enabling simple firmware upgradability in the field.

The PTN3393 supports I²C-bus over AUX per DisplayPort v1.1a specification, and

bridges the VESA DDC channel to the DisplayPort Interface.

The PTN3393 is designed for single supply and minimizes application costs. It can be

powered directly from the DisplayPort source side 3.3 V supply without a need for

additional core voltage regulator. The VGA output is powered down when there is no valid

DisplayPort source data being transmitted. The PTN3393 also aids in monitor detection

by performing load sensing and reporting sink connection status to the source.

2. Functional diagram

PTN3393

RX PHY

VIDEO DAC SUBSYSTEM

DAC

RX PHY DIGITAL

ISOCHRONOUS LINK

MAIN

TIME

CONV.

ANALOG

R[7:0]

G[7:0]

B[7:0]

SUBSYSTEM

R

G

B

VGA

DAC

STREAM

DIFF CDR,

RCV S2P

OUTPUT

lane 0

lane 1

H, V

sync

HSYNC

VSYNC

TIMING RECOVERY

V

bias

DIFF CDR,

RCV S2P

CONTROL

FLASH MCU

DPCD

REGISTERS

V

bias

2

SCL

SDA

I C-BUS

RCV

MASTER

MANCHESTER

CODEC

AUX COMMAND

LEVEL MODULE

AUX

DRV

RX ACLI

RX DIGITAL SUBSYSTEM

V

bias

002aah229

Fig 1. Functional diagram of PTN3393

PTN3393

NXP Semiconductors

2-lane DisplayPort to VGA adapter test IC

3. Pinning information

3.1 Pinning

terminal 1

index area

1

2

3

4

5

6

7

8

9

30

29

VDDA22_AUX

LDOCPA_AUX

AUX_P

RSET

n.c.

28 GRN

AUX_N

27 VDDA33_DAC

26 BLU

RRX

PTN3393BS

ML0_P

25 HSYNC

24 VSYNC

23 n.c.

ML0_N

n.c.

ML1_P

22 SDA

ML1_N 10

21 VDDD33_IO

002aah226

Transparent top view

Fig 2. Pin configuration for HVQFN40

3.2 Pin description

Table 1.

Symbol

Power

Pin description

Type

Description

VDDD33_CORE 36

power

Digital core 3.3 V supply voltage

VDDA33_AUX

VDDA33_DP

VDDD33_IO

VDDA33_DAC

LDOCAP_AUX

LDOCAP_DIG

DisplayPort

ML0_P

1

Analog AUX, bias and PLL 3.3 V supply voltage

Analog 3.3 V supply for DisplayPort receiver module

I/O 3.3 V supply voltage

14

21

27

2

Analog 3.3 V supply for DAC

1.8 V AUX supply decoupling

35

1.8 V digital core supply decoupling

6

self-biasing

differential input

DisplayPort main lane signal lane 0, positive

DisplayPort main lane signal lane 0, negative

DisplayPort main lane signal lane 1, positive

DisplayPort main lane signal lane 1, negative

ML0_N

ML1_P

ML1_N

AUX_P

AUX_N

7

self-biasing

differential input

9

self-biasing

differential input

10

3

self-biasing

differential input

self-biasing differential DisplayPort auxiliary channel signal, positive

input/output

4

self-biasing differential DisplayPort auxiliary channel signal, negative

input/output

PTN3393

All information provided in this document is subject to legal disclaimers.

Objective product brief

Rev. 2 — 27 July 2012

2 of 5

PTN3393

NXP Semiconductors

2-lane DisplayPort to VGA adapter test IC

Table 1.

Symbol

HPD

Pin description …continued

Type

Description

13

3.3 V TTL

Hot Plug Detect

single-ended output

RGB DAC outputs

BLU

26

analog output

‘blue’ current analog output

‘green’ current analog output

‘red’ current analog output

GRN

RED

RSET

28

31

30

analog output

analog input/output

DAC full-scale current control resistor. Pull down to ground by an

external 1.2 kΩ 1 % resistor.

DDC

SCL

20

22

single-ended 5 V

open-drain DDC I/O

5 V sink-side DDC clock I/O. Pulled up by external resistor to 5 V.

5 V sink-side DDC data I/O. Pulled up by external resistor to 5 V.

SDA

single-ended 5 V

open-drain DDC I/O

Monitor-side sync

HSYNC

25

single-ended 3.3 V

TTL output

horizontal sync signal to monitor

vertical sync signal to monitor

VSYNC

24

single-ended 3.3 V

TTL output

JTAG

TCK

15

16

17

18

19

input

output

input

JTAG clock input

TDO

JTAG data output

TMS

JTAG mode select input

JTAG reset (active LOW) input

JTAG data input

TRST

TDI

Miscellaneous

S0

37

input

Open (internal pull-down) = logic 0

Implement VGA-side monitor detect according to VESA DisplayPort

Standard v1.1a, sections 7 and 8.

HIGH (external pull-up) = logic 1

Set HPD HIGH upon VGA monitor detection; set HPD LOW upon VGA

monitor detachment.

S1

S2

38

39

input

reserved; leave open-circuit (default internal pull-down)

Open (internal pull-down) = logic 0 to set default I²C-bus speed to

50 kbit/s.

HIGH (external pull-up) = logic 1, to set default I²C-bus speed to 10

kbit/s.

This pin may be left open-circuit (internal pull-down) or tied to V_DD

according to the desired default I²C-bus speed. See more explanation

about S2 pin setting and DPCD register 00109h.

S3

40

11

input

reserved; leave open-circuit (default internal pull-down)

RESET

Hardware reset input (active LOW); internal pull-up. A capacitor must be

connected between this pin and ground. A 1 μF capacitor is

recommended.

CLK_O

12

33

output

input

DisplayPort receiver test clock output

crystal oscillator input

OSC_IN

PTN3393

All information provided in this document is subject to legal disclaimers.

Objective product brief

Rev. 2 — 27 July 2012

3 of 5

PTN3393

NXP Semiconductors

2-lane DisplayPort to VGA adapter test IC

Table 1.

Symbol

OSC_OUT

RRX

Pin description …continued

34

5

Type

output

input

Description

crystal oscillator output

Receiver termination resistance control. A 12 kΩ resistor must be

connected between this pin and LDOCAP_AUX (pin 2).

n.c.

8, 23,

-

not connected

29, 32

4. Display resolution

Table 2 lists some example display resolutions and clock rates that PTN3393 supports.

Display resolution and pixel clock rate

Table 2.

Display

type

Active video

Total frame

Bits per Frame rate

Pixel clock Data rate

pixel

(Hz)

(MHz)

(Gbit/s)

Horizontal Vertical

VGA

640

480

800

525

24

18

24

18

24

59.94

60.32

60

25.175

0.8

SVGA

XGA

800

600

1056

1344

1520

1664

1848

1520

1792

1688

1728

1864

2112

2240

2160

1760

2160

2200

2592

2080

2144

2720

2208

628

40.002

1.2

1024

1152

1280

1400

1152

1366

1280

1400

1600

1680

1600

1920

2048

768

806

64.996

1.9

XGA+

WXGA

WXGA+

XGA+

864

806

60

81.806

2.45

2.39

3.11

2.45

2.57

3.2

768

897

60

79.672

900

934

60

103.562

81.806

864

806

60

768

798

60

85.801

SXGA

SXGA+

1024

1050

900

1066

1072

1089

934

60.02

85

108.000

157.455

121.794

118.356

146.362

162.000

164.076

229.500

148.500

193.251

154.000

164.249

161.500

156.751

4.72

3.65

3.55

4.39

3.9

60

WSXGA+

UXGA

1050

1200

1080

1200

1536

1152

1089

1250

1243

1250

1125

1245

1235

1555

1188

1185

60

UXGA

75

4.92

5.16

4.46

4.35

4.62

4.9

UXGA

85

FHD

60

WUXGA

QXGA

59.885

59.95

49.266

49.979

59.909

QWXGA

4.84

4.7

The available bandwidth over a 2-lane HBR DisplayPort 1.1a link limits pixel clock rate

support to:

• 240 MHz at 6 bpc

• 180 MHz at 8 bpc

PTN3393

All information provided in this document is subject to legal disclaimers.

Objective product brief

Rev. 2 — 27 July 2012

4 of 5

PTN3393

NXP Semiconductors

2-lane DisplayPort to VGA adapter test IC

5. Package outline

HVQFN40: plastic thermal enhanced very thin quad flat package; no leads;

40 terminals; body 6 x 6 x 0.85 mm

SOT618-1

D

B

A

terminal 1

index area

A

E

1

c

detail X

C

e

1

y

1

y

1/2 e

e

v

M

C

b

C

A

B

11

20

w

L

21

10

e

E

h

2

1/2 e

1

30

terminal 1

index area

40

31

D

X

h

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

A

(1)

UNIT

A

b

c

E

e

1

e

2

y

D

E

L

v

w

y

1

h

max.

0.05 0.30

0.00 0.18

6.1

5.9

4.25

3.95

6.1

5.9

4.25

3.95

0.5

0.3

mm

0.05 0.1

1

0.2

0.5

4.5

0.1

0.05

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

01-08-08

02-10-22

SOT618-1

- - -

MO-220

- - -

Fig 3. Package outline SOT618-1 (HVQFN40)

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 27 July 2012

Document identifier: PTN3393

PTN3393

All information provided in this document is subject to legal disclaimers.

Objective product brief

Rev. 2 — 27 July 2012

5 of 5


型号：	PTN3393BS
厂家：	NXP
描述：	IC SPECIALTY ANALOG CIRCUIT, Analog IC:Other
文件：	总5页 (文件大小：175K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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