PUMD2,125 [NXP]
PEMD2; PIMD2; PUMD2 - NPN/PNP resistor-equipped transistors; R1 = 22 kΩ, R2 = 22 kΩ TSSOP 6-Pin;
| 型号： | PUMD2,125 |
| 厂家： | 
NXP |
| 描述： | PEMD2; PIMD2; PUMD2 - NPN/PNP resistor-equipped transistors; R1 = 22 kΩ, R2 = 22 kΩ TSSOP 6-Pin 开关 光电二极管 晶体管 |
| 文件： | 总16页 (文件大小：88K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PEMD2; PIMD2; PUMD2
NPN/PNP resistor-equipped transistors;
R1 = 22 kΩ, R2 = 22 kΩ
Rev. 07 — 24 September 2008
Product data sheet
1. Product profile
1.1 General description
NPN/PNP Resistor-Equipped Transistors (RET).
Table 1.
Product overview
Type number
Package
NXP
PNP/PNP
complement
NPN/NPN
complement
JEITA
-
PEMD2
PIMD2
PUMD2
SOT666
SOT457
SOT363
PEMB1
-
PEMH1
-
SC-74
SC-88
PUMB1
PUMH1
1.2 Features
I Built-in bias resistors
I Simplifies circuit design
I Reduces component count
I Reduces pick and place costs
1.3 Applications
I Low current peripheral driver
I Control of IC inputs
I Replaces general-purpose transistors in digital applications
1.4 Quick reference data
Table 2.
Symbol
VCEO
IO
Quick reference data
Parameter
Conditions
Min
-
Typ
Max
50
Unit
V
collector-emitter voltage
output current
open base
-
-
-
100
28.6
1.2
mA
kΩ
R1
bias resistor 1 (input)
bias resistor ratio
15.4
0.8
22
1
R2/R1
PEMD2; PIMD2; PUMD2
NXP Semiconductors
NPN/PNP resistor-equipped transistors; R1 = 22 kΩ, R2 = 22 kΩ
2. Pinning information
Table 3.
Pin
Pinning
Description
Simplified outline
Graphic symbol
PEMD2; PUMD2
1
2
3
4
5
6
GND (emitter) TR1
6
5
4
6
1
5
2
4
input (base) TR1
output (collector) TR2
GND (emitter) TR2
input (base) TR2
R1
R2
TR2
TR1
3
output (collector) TR1
001aab555
R2
R1
1
2
3
006aaa143
PIMD2
1
2
3
4
5
6
GND (emitter) TR2
input (base) TR2
6
5
4
6
1
5
2
4
3
output (collector) TR1
GND (emitter) TR1
input (base) TR1
R1
R2
TR1
TR2
R2
R1
output (collector) TR2
1
2
3
006aab235
3. Ordering information
Table 4.
Ordering information
Type number
Package
Name
-
Description
plastic surface-mounted package; 6 leads
Version
SOT666
SOT457
SOT363
PEMD2
PIMD2
PUMD2
SC-74
SC-88
plastic surface-mounted package (TSOP6); 6 leads
plastic surface-mounted package; 6 leads
PEMD2_PIMD2_PUMD2_7
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 24 September 2008
2 of 16
PEMD2; PIMD2; PUMD2
NXP Semiconductors
NPN/PNP resistor-equipped transistors; R1 = 22 kΩ, R2 = 22 kΩ
4. Marking
Table 5.
Marking codes
Type number
PEMD2
Marking code[1]
D4
PIMD2
M5
D*2
PUMD2
[1] * = -: made in Hong Kong
* = p: made in Hong Kong
* = t: made in Malaysia
* = W: made in China
5. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
Per transistor; for the PNP transistor with negative polarity
VCBO
VCEO
VEBO
VI
collector-base voltage
collector-emitter voltage
emitter-base voltage
input voltage TR1
positive
open emitter
open base
-
-
-
50
50
10
V
V
V
open collector
-
-
+40
V
V
negative
−10
input voltage TR2
positive
-
-
-
-
+10
−40
100
100
V
negative
V
IO
output current
mA
mA
ICM
peak collector current
single pulse;
tp ≤ 1 ms
[1]
[2]
Ptot
total power dissipation
PEMD2 (SOT666)
PIMD2 (SOT457)
Tamb ≤ 25 °C
-
200
mW
mW
mW
°C
-
300
PUMD2 (SOT363)
junction temperature
ambient temperature
storage temperature
-
200
Tj
-
150
Tamb
Tstg
−65
−65
+150
+150
°C
°C
PEMD2_PIMD2_PUMD2_7
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 24 September 2008
3 of 16
PEMD2; PIMD2; PUMD2
NXP Semiconductors
NPN/PNP resistor-equipped transistors; R1 = 22 kΩ, R2 = 22 kΩ
Table 6.
Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Per device
Ptot
Parameter
Conditions
Min
Max
Unit
[1]
[2]
total power dissipation
PEMD2 (SOT666)
PIMD2 (SOT457)
PUMD2 (SOT363)
Tamb ≤ 25 °C
-
-
-
300
600
300
mW
mW
mW
[1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard
footprint.
[2] Reflow soldering is the only recommended soldering method.
6. Thermal characteristics
Table 7.
Symbol
Per transistor
Thermal characteristics
Parameter
Conditions
Min
Typ
Max
Unit
[1]
[2]
Rth(j-a)
thermal resistance from
in free air
junction to ambient
PEMD2 (SOT666)
PIMD2 (SOT457)
PUMD2 (SOT363)
-
-
-
-
-
-
625
417
625
K/W
K/W
K/W
Per device
[1]
[2]
Rth(j-a)
thermal resistance from
junction to ambient
in free air
PEMD2 (SOT666)
PIMD2 (SOT457)
PUMD2 (SOT363)
-
-
-
-
-
-
416
208
416
K/W
K/W
K/W
[1] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint.
[2] Reflow soldering is the only recommended soldering method.
PEMD2_PIMD2_PUMD2_7
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 24 September 2008
4 of 16
PEMD2; PIMD2; PUMD2
NXP Semiconductors
NPN/PNP resistor-equipped transistors; R1 = 22 kΩ, R2 = 22 kΩ
7. Characteristics
Table 8.
Characteristics
Tamb = 25 °C unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Per transistor; for the PNP transistor with negative polarity
ICBO
collector-basecut-off VCB = 50 V; IE = 0 A
current
-
-
100
nA
ICEO
collector-emitter
cut-off current
VCE = 30 V; IB = 0 A
-
-
-
-
1
µA
µA
VCE = 30 V; IB = 0 A;
50
Tj = 150 °C
IEBO
emitter-base cut-off VEB = 5 V; IC = 0 A
current
-
-
180
µA
hFE
DC current gain
VCE = 5 V; IC = 5 mA
60
-
-
-
-
VCEsat
collector-emitter
IC = 10 mA; IB = 0.5 mA
150
mV
V
saturation voltage
VI(off)
VI(on)
off-state input
voltage
VCE = 5 V; IC = 100 µA
-
1.1
1.7
0.8
-
on-state input
voltage
VCE = 0.3 V; IC = 5 mA
2.5
V
R1
bias resistor 1 (input)
bias resistor ratio
15.4
0.8
22
1
28.6
1.2
kΩ
R2/R1
Cc
collector capacitance VCB = 10 V; IE = ie = 0 A;
f = 1 MHz
TR1 (NPN)
TR2 (PNP)
-
-
-
-
2.5
3
pF
pF
PEMD2_PIMD2_PUMD2_7
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 24 September 2008
5 of 16
PEMD2; PIMD2; PUMD2
NXP Semiconductors
NPN/PNP resistor-equipped transistors; R1 = 22 kΩ, R2 = 22 kΩ
006aaa038
006aaa039
3
−1
10
10
h
FE
(1)
(2)
(1)
(2)
(3)
V
CEsat
(V)
2
10
(3)
10
−2
1
10
10
−1
2
2
1
10
10
1
10
10
I
(mA)
I (mA)
C
C
VCE = 5 V
IC/IB = 20
(1) Tamb = 150 °C
(2) Tamb = 25 °C
(3) Tamb = −40 °C
(1) Tamb = 100 °C
(2) Tamb = 25 °C
(3) Tamb = −40 °C
Fig 1. TR1 (NPN): DC current gain as a function of
collector current; typical values
Fig 2. TR1 (NPN): Collector-emitter saturation
voltage as a function of collector current;
typical values
006aaa040
006aaa041
10
10
V
I(on)
V
I(off)
(V)
(V)
(1)
(2)
(1)
(2)
(3)
1
1
(3)
−1
−1
10
10
−1
2
−2
−1
1
10
1
10
10
10
10
1
10
I
(mA)
I (mA)
C
C
VCE = 0.3 V
VCE = 5 V
(1) Tamb = −40 °C
(2) Tamb = 25 °C
(3) Tamb = 100 °C
(1) Tamb = −40 °C
(2) Tamb = 25 °C
(3) Tamb = 100 °C
Fig 3. TR1 (NPN): On-state input voltage as a
function of collector current; typical values
Fig 4. TR1 (NPN): Off-state input voltage as a
function of collector current; typical values
PEMD2_PIMD2_PUMD2_7
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 24 September 2008
6 of 16
PEMD2; PIMD2; PUMD2
NXP Semiconductors
NPN/PNP resistor-equipped transistors; R1 = 22 kΩ, R2 = 22 kΩ
006aab351
3
10
R
CEsat
(Ω)
2
10
(1)
(2)
(3)
10
1
10
−1
2
1
10
10
I
(mA)
C
IC/IB = 20
(1) Tamb = 100 °C
(2) Tamb = 25 °C
(3) Tamb = −40 °C
Fig 5. TR1 (NPN): Collector-emitter saturation resistance as a function of collector
current; typical values
PEMD2_PIMD2_PUMD2_7
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 24 September 2008
7 of 16
PEMD2; PIMD2; PUMD2
NXP Semiconductors
NPN/PNP resistor-equipped transistors; R1 = 22 kΩ, R2 = 22 kΩ
006aab197
006aab198
3
10
−1
h
FE
(1)
(2)
(3)
V
CEsat
(V)
2
10
−1
(1)
(2)
(3)
−10
10
−
2
1
−10
−10
−1
2
2
−1
−10
−10
−1
−10
−10
I
(mA)
I (mA)
C
C
VCE = −5 V
IC/IB = 20
(1) Tamb = 150 °C
(2) Tamb = 25 °C
(3) Tamb = −40 °C
(1) Tamb = 100 °C
(2) Tamb = 25 °C
(3) Tamb = −40 °C
Fig 6. TR2 (PNP): DC current gain as a function of
collector current; typical values
Fig 7. TR2 (PNP): Collector-emitter saturation
voltage as a function of collector current;
typical values
006aab199
006aab200
−10
−10
V
I(on)
V
I(off)
(V)
(V)
(1)
(2)
(1)
(2)
−1
−1
(3)
(3)
−1
−1
−10
−10
−1
2
−2
−1
−10
−1
−10
−10
−10
−10
−1
−10
I
(mA)
I (mA)
C
C
VCE = −0.3 V
VCE = −5 V
(1) Tamb = −40 °C
(2) Tamb = 25 °C
(3) Tamb = 100 °C
(1) Tamb = −40 °C
(2) Tamb = 25 °C
(3) Tamb = 100 °C
Fig 8. TR2 (PNP): On-state input voltage as a
function of collector current; typical values
Fig 9. TR2 (PNP): Off-state input voltage as a
function of collector current; typical values
PEMD2_PIMD2_PUMD2_7
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 24 September 2008
8 of 16
PEMD2; PIMD2; PUMD2
NXP Semiconductors
NPN/PNP resistor-equipped transistors; R1 = 22 kΩ, R2 = 22 kΩ
006aab352
3
10
R
CEsat
(Ω)
2
10
(1)
(2)
(3)
10
1
−10
−1
2
−1
−10
−10
I
(mA)
C
IC/IB = 20
(1) Tamb = 100 °C
(2) Tamb = 25 °C
(3) Tamb = −40 °C
Fig 10. TR2 (PNP): Collector-emitter saturation resistance as a function of collector
current; typical values
PEMD2_PIMD2_PUMD2_7
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 24 September 2008
9 of 16
PEMD2; PIMD2; PUMD2
NXP Semiconductors
NPN/PNP resistor-equipped transistors; R1 = 22 kΩ, R2 = 22 kΩ
8. Package outline
3.1
2.7
1.1
0.9
1.7
1.5
0.6
0.5
6
5
4
6
5
4
0.6
0.2
0.3
0.1
3.0 1.7
2.5 1.3
1.7 1.3
1.5 1.1
pin 1 index
pin 1 index
1
2
3
1
2
3
0.26
0.10
0.18
0.08
0.40
0.25
0.27
0.17
0.95
0.5
1
1.9
Dimensions in mm
04-11-08
Dimensions in mm
04-11-08
Fig 11. Package outline PEMD2 (SOT666)
Fig 12. Package outline PIMD2 (SOT457/SC-74)
2.2
1.8
1.1
0.8
0.45
0.15
6
5
4
2.2 1.35
2.0 1.15
pin 1
index
1
2
3
0.25
0.10
0.3
0.2
0.65
1.3
Dimensions in mm
06-03-16
Fig 13. Package outline PUMD2 (SOT363/SC-88)
PEMD2_PIMD2_PUMD2_7
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 24 September 2008
10 of 16
PEMD2; PIMD2; PUMD2
NXP Semiconductors
NPN/PNP resistor-equipped transistors; R1 = 22 kΩ, R2 = 22 kΩ
9. Packing information
Table 9.
Packing methods
The indicated -xxx are the last three digits of the 12NC ordering code.[1]
Type number Package Description
Packing quantity
3000 4000 8000 10000
PEMD2
PIMD2
PUMD2
SOT666 2 mm pitch, 8 mm tape and reel
4 mm pitch, 8 mm tape and reel
-
-
-315
-
-
-115
-
-
-
-
-
-
[2]
[3]
[2]
[3]
SOT457 4 mm pitch, 8 mm tape and reel; T1
4 mm pitch, 8 mm tape and reel; T2
-115
-125
-115
-125
-
-
-
-
-135
-165
-135
-165
SOT363 4 mm pitch, 8 mm tape and reel; T1
4 mm pitch, 8 mm tape and reel; T2
[1] For further information and the availability of packing methods, see Section 13.
[2] T1: normal taping
[3] T2: reverse taping
10. Soldering
2.75
2.45
2.1
1.6
solder lands
0.4
(6×)
0.3
(2×)
0.25
(2×)
placement area
0.538
0.55
(2×)
1.075
1.7
2
solder paste
occupied area
0.325 0.375
(4×) (4×)
Dimensions in mm
1.7
0.45
0.6
(4×)
(2×)
0.5
0.65
(4×)
(2×)
sot666_fr
Reflow soldering is the only recommended soldering method.
Fig 14. Reflow soldering footprint PEMD2 (SOT666)
PEMD2_PIMD2_PUMD2_7
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 24 September 2008
11 of 16
PEMD2; PIMD2; PUMD2
NXP Semiconductors
NPN/PNP resistor-equipped transistors; R1 = 22 kΩ, R2 = 22 kΩ
3.45
1.95
0.55
(6×)
solder lands
solder resist
0.45
(6×)
0.95
0.95
3.3 2.825
solder paste
occupied area
0.7
Dimensions in mm
(6×)
0.8
(6×)
2.4
sot457_fr
Fig 15. Reflow soldering footprint PIMD2 (SOT457/SC-74)
5.3
1.5
(4×)
solder lands
solder resist
occupied area
1.475
0.45
(2×)
5.05
1.475
Dimensions in mm
preferred transport
direction during soldering
1.45
(6×)
2.85
sot457_fw
Fig 16. Wave soldering footprint PIMD2 (SOT457/SC-74)
PEMD2_PIMD2_PUMD2_7
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 24 September 2008
12 of 16
PEMD2; PIMD2; PUMD2
NXP Semiconductors
NPN/PNP resistor-equipped transistors; R1 = 22 kΩ, R2 = 22 kΩ
2.65
solder lands
0.4 (2×)
1.5
2.35
0.6
(4×)
0.5
(4×)
solder resist
solder paste
0.5
(4×)
0.6
(2×)
occupied area
0.6
(4×)
Dimensions in mm
1.8
sot363_fr
Fig 17. Reflow soldering footprint PUMD2 (SOT363/SC-88)
1.5
solder lands
solder resist
occupied area
2.5
0.3
4.5
1.5
Dimensions in mm
preferred transport
direction during soldering
1.3
1.3
2.45
5.3
sot363_fw
Fig 18. Wave soldering footprint PUMD2 (SOT363/SC-88)
PEMD2_PIMD2_PUMD2_7
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 24 September 2008
13 of 16
PEMD2; PIMD2; PUMD2
NXP Semiconductors
NPN/PNP resistor-equipped transistors; R1 = 22 kΩ, R2 = 22 kΩ
11. Revision history
Table 10. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PEMD2_PIMD2_PUMD2_7 20080924
Product data sheet
-
PEMD2_PIMD2_PUMD2_6
Modifications:
• The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Table 8 “Characteristics”: VCEsat unit corrected
• Figure 1, 2, 3, 4, 5, 6, 7, 8, 9 and 10: added
• Section 12 “Legal information”: updated
PEMD2_PIMD2_PUMD2_6 20040421
Product specification
-
PEMD2_PIMD2_PUMD2_5
PEMD2_PIMD2_PUMD2_7
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 24 September 2008
14 of 16
PEMD2; PIMD2; PUMD2
NXP Semiconductors
NPN/PNP resistor-equipped transistors; R1 = 22 kΩ, R2 = 22 kΩ
12. Legal information
12.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
12.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
12.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
12.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
13. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
PEMD2_PIMD2_PUMD2_7
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 24 September 2008
15 of 16
PEMD2; PIMD2; PUMD2
NXP Semiconductors
NPN/PNP resistor-equipped transistors; R1 = 22 kΩ, R2 = 22 kΩ
14. Contents
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data. . . . . . . . . . . . . . . . . . . . . 1
1.1
1.2
1.3
1.4
2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Thermal characteristics. . . . . . . . . . . . . . . . . . . 4
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
Packing information. . . . . . . . . . . . . . . . . . . . . 11
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14
3
4
5
6
7
8
9
10
11
12
Legal information. . . . . . . . . . . . . . . . . . . . . . . 15
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
12.1
12.2
12.3
12.4
13
14
Contact information. . . . . . . . . . . . . . . . . . . . . 15
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 24 September 2008
Document identifier: PEMD2_PIMD2_PUMD2_7
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