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PZ3032-10BC-T [NXP]

EE PLD, 17ns, PQFP44;
PZ3032-10BC-T
型号： PZ3032-10BC-T
厂家： NXP    NXP
描述：

EE PLD, 17ns, PQFP44
文件： 总14页 (文件大小：116K)
中文：  中文翻译
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INTEGRATED CIRCUITS  
PZ3032  
32 macrocell CPLD  
Product specification  
IC27 Data Handbook  
1997 Feb 20  
Philips  
Semiconductors  
Philips Semiconductors  
Product specification  
32 macrocell CPLD  
PZ3032  
FEATURES  
DESCRIPTION  
The PZ3032 CPLD (Complex Programmable Logic Device) is the  
first in a family of Fast Zero Power (FZP ) CPLDs from Philips  
Semiconductors. These devices combine high speed and zero  
power in a 32 macrocell CPLD. With the FZP design technique,  
the PZ3032 offers true pin-to-pin speeds of 8ns, while  
• Industry’s first TotalCMOS PLD – both CMOS design and  
process technologies  
• Fast Zero Power (FZP ) design technique provides ultra-low  
power and very high speed  
• High speed pin-to-pin delays of 8ns  
• Ultra-low static power of less than 35µA  
simultaneously delivering power that is less than 35µA at standby  
without the need for ‘turbo bits’ or other power down schemes. By  
replacing conventional sense amplifier methods for implementing  
product terms (a technique that has been used in PLDs since the  
bipolar era) with a cascaded chain of pure CMOS gates, the  
dynamic power is also substantially lower than any competing CPLD  
– 70% lower at 50MHz. These devices are the first TotalCMOS  
PLDs, as they use both a CMOS process technology and the  
patented full CMOS FZP design technique. For 5V applications,  
Philips also offers the high speed PZ5032 CPLD that offers  
pin-to-pin speeds of 6ns.  
• Dynamic power that is 70% lower at 50MHz than competing  
devices  
• 100% routable with 100% utilization while all pins and all  
macrocells are fixed  
• Deterministic timing model that is extremely simple to use  
• 2 clocks with programmable polarity at every macrocell  
• Support for complex asynchronous clocking  
The Philips FZP CPLDs introduce the new patent-pending XPLA  
(eXtended Programmable Logic Array) architecture. The XPLA  
architecture combines the best features of both PLA and PAL type  
structures to deliver high speed and flexible logic allocation that  
results in superior ability to make design changes with fixed pinouts.  
The XPLA structure in each logic block provides a fast 8ns PAL  
path with 5 dedicated product terms per output. This PAL path is  
joined by an additional PLA structure that deploys a pool of 32  
product terms to a fully programmable OR array that can allocate  
the PLA product terms to any output in the logic block. This  
• Innovative XPLA architecture combines high speed with  
extreme flexibility  
• 1000 erase/program cycles guaranteed  
• 20 years data retention guaranteed  
• Logic expandable to 37 product terms  
• PCI compliant  
2
• Advanced 0.5µ E CMOS process  
combination allows logic to be allocated efficiently throughout the  
logic block and supports as many as 37 product terms on an output.  
The speed with which logic is allocated from the PLA array to an  
output is only 2.5ns, regardless of the number of PLA product terms  
• Security bit prevents unauthorized access  
• Design entry and verification using industry standard and Philips  
CAE tools  
used, which results in worst case t ’s of only 10.5ns from any pin  
PD  
• Reprogrammable using industry standard device programmers  
to any other pin. In addition, logic that is common to multiple outputs  
can be placed on a single PLA product term and shared across  
multiple outputs via the OR array, effectively increasing design  
density.  
• Innovative Control Term structure provides either sum terms or  
product terms in each logic block for:  
– Programmable 3-State buffer  
– Asynchronous macrocell register preset/reset  
The PZ3032 CPLDs are supported by industry standard CAE tools  
(Cadence, Mentor, Synopsys, Synario, Viewlogic, OrCAD), using  
text (Abel, VHDL, Verilog) and/or schematic entry. Design  
verification uses industry standard simulators for functional and  
timing simulation. Development is supported on personal computer,  
Sparc, and HP platforms. Device fitting uses either Minc or Philips  
Semiconductors-developed tools.  
• Programmable global 3-State pin facilitates ‘bed of nails’ testing  
without using logic resources  
• Available in both PLCC and TQFP packages  
Table 1. PZ3032 Features  
PZ3032  
The PZ3032 CPLD is reprogrammable using industry standard  
device programmers from vendors such as Data I/O, BP  
Microsystems, SMS, and others.  
Usable gates  
1000  
Maximum inputs  
Maximum I/Os  
36  
32  
Number of macrocells  
I/O macrocells  
32  
32  
Buried macrocells  
Propagation delay (ns)  
Packages  
0
8.0  
44-pin PLCC, 44-pin TQFP  
PAL is a registered trademark of Advanced Micro Devices, Inc.  
2
1997 Feb 20  
853–1852 17780  
Philips Semiconductors  
Product specification  
32 macrocell CPLD  
PZ3032  
ORDERING INFORMATION  
ORDER CODE  
PZ3032–8A44  
PZ3032–10A44  
PZ3032–12A44  
PZ3032I10A44  
PZ3032I12A44  
PZ3032–8BC  
PZ3032–10BC  
PZ3032–12BC  
PZ3032I10BC  
PZ3032I12BC  
DESCRIPTION  
44-pin PLCC, 8ns t  
DESCRIPTION  
DRAWING NUMBER  
SOT187-2  
SOT187-2  
SOT187-2  
SOT187-2  
SOT187-2  
SOT376-1  
SOT376-1  
SOT376-1  
SOT376-1  
SOT376-1  
Commercial temp range, 3.3 volt power supply, ± 10%  
Commercial temp range, 3.3 volt power supply, ± 10%  
Commercial temp range, 3.3 volt power supply, ± 10%  
Industrial temp range, 3.3 volt power supply, ± 10%  
Industrial temp range, 3.3 volt power supply, ± 10%  
Commercial temp range, 3.3 volt power supply, ± 10%  
Commercial temp range, 3.3 volt power supply, ± 10%  
Commercial temp range, 3.3 volt power supply, ± 10%  
Industrial temp range, 3.3 volt power supply, ± 10%  
Industrial temp range, 3.3 volt power supply, ± 10%  
PD  
44-pin PLCC, 10ns t  
44-pin PLCC, 12ns t  
PD  
PD  
44-pin PLCC, 10ns t  
PD  
PD  
44-pin PLCC, 12ns t  
44-pin TQFP, 8ns t  
,
PD  
44-pin TQFP, 10ns t  
44-pin TQFP, 12ns t  
PD  
PD  
44-pin TQFP, 10ns t  
PD  
PD  
44-pin TQFP, 12ns t  
PRODUCT terms, and are used to control the preset/reset and  
output enables of the 16 macrocells’ flip-flops. The PAL array  
consists of a programmable AND array with a fixed OR array, while  
the PLA array consists of a programmable AND array with a  
programmable OR array. The PAL array provides a high speed path  
through the array, while the PLA array provides increased product  
term density.  
XPLA ARCHITECTURE  
Figure 1 shows a high level block diagram of a 64 macrocell device  
implementing the XPLA architecture. The XPLA architecture  
consists of logic blocks that are interconnected by a Zero-power  
Interconnect Array (ZIA). The ZIA is a virtual crosspoint switch. Each  
logic block is essentially a 36V16 device with 36 inputs from the ZIA  
and 16 macrocells. Each logic block also provides 32 ZIA feedback  
paths from the macrocells and I/O pins.  
Each macrocell has 5 dedicated product terms from the PAL array.  
The pin-to-pin t of the PZ3032 device through the PAL array is  
PD  
From this point of view, this architecture looks like many other CPLD  
architectures. What makes the CoolRunner family unique is what  
is inside each logic block and the design technique used to  
implement these logic blocks. The contents of the logic block will be  
described next.  
8ns. This performance is the fastest 3 volt CPLD available today. If a  
macrocell needs more than 5 product terms, it simply gets the  
additional product terms from the PLA array. The PLA array consists  
of 32 product terms, which are available for use by all 16  
macrocells. The additional propagation delay incurred by a  
macrocell using 1 or all 32 PLA product terms is just 2.5ns. So the  
Logic Block Architecture  
total pin-to-pin t for the PZ3032 using 6 to 37 product terms is  
Figure 2 illustrates the logic block architecture. Each logic block  
contains control terms, a PAL array, a PLA array, and 16 macrocells.  
The 6 control terms can individually be configured as either SUM or  
PD  
10.5ns (8ns for the PAL + 2.5ns for the PLA).  
MC0  
MC0  
MC1  
MC1  
36  
36  
LOGIC  
BLOCK  
LOGIC  
BLOCK  
I/O  
I/O  
MC15  
MC15  
16  
16  
16  
16  
ZIA  
MC0  
MC1  
MC0  
MC1  
36  
36  
LOGIC  
BLOCK  
LOGIC  
BLOCK  
I/O  
I/O  
MC15  
MC15  
16  
16  
16  
16  
SP00439  
Figure 1. Philips XPLA CPLD Architecture  
3
1997 Feb 20  
Philips Semiconductors  
Product specification  
32 macrocell CPLD  
PZ3032  
36 ZIA INPUTS  
CONTROL  
6
5
PAL  
ARRAY  
PLA  
ARRAY  
(32)  
SP00435  
Figure 2. Philips Logic Block Architecture  
4
1997 Feb 20  
Philips Semiconductors  
Product specification  
32 macrocell CPLD  
PZ3032  
to control the Output Enable of the macrocell’s output buffers. The  
reason there are as many control terms dedicated for the Output  
Enable of the macrocell is to insure that all CoolRunner devices  
are PCI compliant. The macrocell’s output buffers can also be  
always enabled or disabled. All CoolRunner devices also provide a  
Global Tri-State (GTS) pin, which, when pulled Low, will 3-State all  
the outputs of the device. This pin is provided to support “In-Circuit  
Testing” or “Bed-of-Nails Testing”.  
Macrocell Architecture  
Figure 3 shows the architecture of the macrocell used in the  
CoolRunner family. The macrocell consists of a flip-flop that can be  
configured as either a D or T type. A D-type flip-flop is generally  
more useful for implementing state machines and data buffering. A  
T-type flip-flop is generally more useful in implementing counters. All  
CoolRunner family members provide both synchronous and  
asynchronous clocking and provide the ability to clock off either the  
falling or rising edges of these clocks. These devices are designed  
such that the skew between the rising and falling edges of a clock  
are minimized for clocking integrity. There are 2 clocks (CLK0 and  
CLK1) available on the PZ3032 device. Clock 0 (CLK0) is  
designated as the “synchronous” clock and must be driven by an  
external source. Clock 1 (CLK1) can either be used as a  
synchronous clock (driven by an external source) or as an  
asynchronous clock (driven by a macrocell equation).  
There are two feedback paths to the ZIA: one from the macrocell,  
and one from the I/O pin. The ZIA feedback path before the output  
buffer is the macrocell feedback path, while the ZIA feedback path  
after the output buffer is the I/O pin ZIA path. When the macrocell is  
used as an output, the output buffer is enabled, and the macrocell  
feedback path can be used to feedback the logic implemented in the  
macrocell. When the I/O pin is used as an input, the output buffer  
will be 3-Stated and the input signal will be fed into the ZIA via the  
I/O feedback path, and the logic implemented in the buried  
macrocell can be fed back to the ZIA via the macrocell feedback  
path. It should be noted that unused inputs or I/Os should be  
properly terminated.  
Two of the control terms (CT0 and CT1) are used to control the  
Preset/Reset of the macrocell’s flip-flop. The Preset/Reset feature  
for each macrocell can also be disabled. Note that the Power-on  
Reset leaves all macrocells in the “zero” state when power is  
properly applied. The other 4 control terms (CT2–CT5) can be used  
TO ZIA  
D/T  
Q
INIT  
(P or R)  
GTS  
CLK0  
CLK0  
CLK1  
CLK1  
GND  
CT0  
CT1  
CT2  
CT3  
CT4  
CT5  
GND  
V
CC  
GND  
SP00440  
Figure 3. PZ3032 Macrocell Architecture  
5
1997 Feb 20  
Philips Semiconductors  
Product specification  
32 macrocell CPLD  
PZ3032  
product terms or less, the t = 8ns, the t = 6.5ns, and the  
Simple Timing Model  
Figure 4 shows the CoolRunner Timing Model. The CoolRunner  
timing model looks very much like a 22V10 timing model in that  
PD  
SU  
t
= 7.5ns. If an output is using 6 to 37 product terms, an additional  
CO  
2.5ns must be added to the t and t timing parameters to  
PD  
SU  
account for the time to propagate through the PLA array.  
there are three main timing parameters, including t , t , and t  
.
PD SU  
CO  
In other competing architectures, the user may be able to fit the  
design into the CPLD, but is not sure whether system timing  
requirements can be met until after the design has been fit into the  
device. This is because the timing models of competing  
architectures are very complex and include such things as timing  
dependencies on the number of parallel expanders borrowed,  
sharable expanders, varying number of X and Y routing channels  
used, etc. In the XPLA architecture, the user knows up front  
whether the design will meet system timing requirements. This is  
due to the simplicity of the timing model. For example, in the  
TotalCMOS Design Technique  
for Fast Zero Power  
Philips is the first to offer a TotalCMOS CPLD, both in process  
technology and design technique. Philips employs a cascade of  
CMOS gates to implement its Sum of Products instead of the  
traditional sense amp approach. This CMOS gate implementation  
allows Philips to offer CPLDs which are both high performance and  
low power, breaking the paradigm that to have low power, you must  
have low performance. Refer to Figure 5 and Table 2 showing the I  
DD  
vs. Frequency of our PZ3032 TotalCMOS CPLD.  
PZ3032 device, the user knows up front that if a given output uses 5  
t
= COMBINATORIAL PAL ONLY  
= COMBINATORIAL PAL + PLA  
PD_PAL  
t
PD_PLA  
INPUT PIN  
INPUT PIN  
OUTPUT PIN  
OUTPUT PIN  
REGISTERED  
= PAL ONLY  
t
t
REGISTERED  
SU_PAL  
= PAL + PLA  
t
SU_PLA  
CO  
D
Q
CLOCK  
SP00441  
Figure 4. CoolRunner Timing Model  
30  
25  
20  
15  
10  
5
TYPICAL  
I
DD  
(mA)  
0
0
10  
20  
30  
40  
50  
60  
70  
80  
90  
100  
110  
120  
130  
FREQUENCY (MHz)  
SP00443  
Figure 5.  
I vs. Frequency @ V = 3.3V  
DD DD  
Table 2. I vs Frequency  
DD  
V
DD  
= 3.3V  
FREQ  
(MHz)  
0
10  
20  
4.65  
30  
40  
50  
11.1  
60  
70  
80  
90  
100  
22.1  
110  
120  
130  
Typical  
(mA)  
0.01  
2.37  
6.80  
9.06  
13.5  
15.5  
17.4  
20.0  
24.4  
26.6  
28.5  
I
DD  
6
1997 Feb 20  
Philips Semiconductors  
Product specification  
32 macrocell CPLD  
PZ3032  
1
ABSOLUTE MAXIMUM RATINGS  
SYMBOL  
PARAMETER  
MIN.  
–0.5  
–1.2  
–0.5  
–30  
MAX.  
7.0  
UNIT  
V
V
V
V
Supply voltage  
Input voltage  
Output voltage  
Input current  
Output current  
DD  
I
V
DD  
V
DD  
+0.5  
V
+0.5  
V
OUT  
I
I
30  
mA  
mA  
°C  
°C  
IN  
OUT  
–100  
–40  
100  
150  
150  
T
J
Maximum junction temperature  
Storage temperature  
T
str  
–65  
NOTES:  
1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at  
these or any other condition above those indicated in the operational and programming specification is not implied.  
OPERATING RANGE  
PRODUCT GRADE  
Commercial  
TEMPERATURE  
0 to +70°C  
VOLTAGE  
3.3 ±10% V  
3.3 ±10% V  
Industrial  
–40 to +85°C  
7
1997 Feb 20  
Philips Semiconductors  
Product specification  
32 macrocell CPLD  
PZ3032  
DC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL GRADE DEVICES  
Commercial: 0°C ≤ T  
≤ +70°C; 3.0V ≤ V ≤ 3.6V  
amb  
DD  
SYMBOL  
PARAMETER  
TEST CONDITIONS  
MIN.  
MAX.  
UNIT  
V
V
V
V
V
V
Input voltage low  
V
DD  
V
DD  
= 3.0V  
= 3.6V  
0.8  
IL  
Input voltage high  
2.0  
V
IH  
I
Input clamp voltage  
V
= 3.0V, I = –18mA  
–1.2  
0.5  
V
DD  
IN  
Output voltage low  
V
DD  
= 3.0V, I = 8mA  
V
OL  
OH  
OL  
Output voltage high  
V
= 3.0V, I = –8mA  
2.4  
–10  
–10  
–10  
–10  
–10  
V
DD  
OH  
I
I
I
I
I
I
Input leakage current low  
Input leakage current high  
Clock input leakage current  
3-Stated output leakage current low  
3-Stated output leakage current high  
Standby current  
V
= 3.6V (except CKO), V = 0V  
10  
10  
µA  
µA  
µA  
µA  
µA  
µA  
mA  
mA  
mA  
pF  
pF  
pF  
IL  
DD  
IN  
V
V
V
V
= 3.6V, V = 3.0V  
IN  
IH  
DD  
DD  
DD  
DD  
DD  
= 3.6V, V = 0.4V  
10  
IL  
IN  
= 3.6V, V = 0.4V  
10  
OZL  
OZH  
DDQ  
IN  
= 3.6V, V = 3.0V  
10  
IN  
V
= 3.6V, T  
= 0°C  
35  
amb  
V
= 3.6V, T  
= 0°C @ 1MHz  
= 0°C @ 50MHz  
0.5  
18  
DD  
amb  
1
I
Dynamic current  
DDD  
V
= 3.6V, T  
amb  
DD  
I
Short circuit output current  
Input pin capacitance  
Clock input capacitance  
I/O pin capacitance  
1 pin at a time for no longer than 1 second  
–5  
5
–100  
8
OS  
C
C
C
T
= 25°C, f = 1MHz  
= 25°C, f = 1MHz  
= 25°C, f = 1MHz  
IN  
amb  
T
amb  
12  
CLK  
I/O  
T
amb  
10  
NOTE:  
1. This parameter measured with a 16–bit, loadable up/down counter loaded into every logic block, with all outputs enabled and unloaded.  
Inputs are tied to V or ground. This parameter guaranteed by design and characterization, not testing.  
DD  
1
AC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL GRADE DEVICES  
Commercial: 0°C ≤ T  
≤ +70°C; 3.0V ≤ V ≤ 3.6V  
amb  
DD  
–8  
–10  
–12  
SYMBOL  
PARAMETER  
UNIT  
MIN. MAX. MIN. MAX. MIN. MAX.  
t
t
t
t
t
t
t
t
t
t
f
f
f
t
t
t
t
t
t
t
t
t
Propagation delay time, input (or feedback node) to output through PAL  
2
3
8
10.5  
7
2
3
10  
13  
9
2
3
12  
15  
11  
ns  
ns  
PD_PAL  
PD_PLA  
CO  
Propagation delay time, input (or feedback node) to output through PAL & PLA  
Clock to out delay time  
2
2
2
ns  
Setup time (from input or feedback node) through PAL  
6.5  
9
8.5  
11.5  
10.5  
13.5  
ns  
SU_PAL  
SU_PLA  
H
Setup time (from input or feedback node) through PAL + PLA  
ns  
Hold time  
0
0
0
ns  
Clock High time  
Clock Low time  
Input rise time  
3
3
4
4
5
5
ns  
CH  
ns  
CL  
20  
20  
20  
20  
20  
20  
ns  
R
Input fall time  
ns  
F
2
Maximum FF toggle rate  
Maximum internal frequency  
Maximum external frequency  
Output buffer delay time  
(1/t + t )  
167  
83  
125  
63  
100  
50  
MHz  
MHz  
MHz  
ns  
MAX1  
MAX2  
MAX3  
BUF  
CH  
CL  
2
(1/t  
+ t  
)
SUPAL  
CF  
2
(1/t  
+ t  
)
74  
57  
47  
SUPAL  
CO  
1.5  
6.5  
9
1.5  
8.5  
11.5  
7.5  
50  
1.5  
10.5  
13.5  
9.5  
50  
Input (or feedback node) to internal feedback node delay time through PAL  
Input (or feedback node) to internal feedback node delay time through PAL + PLA  
Clock to internal feedback node delay time  
ns  
PDF_PAL  
PDF_PLA  
CF  
ns  
5.5  
50  
15  
15  
16  
19  
ns  
Delay from valid V to valid reset  
µs  
INIT  
DD  
3
Input to output disable  
17  
19  
ns  
ER  
Input to output valid  
Input to register preset  
Input to register reset  
17  
19  
ns  
EA  
18  
20  
ns  
RP  
21  
23  
ns  
RR  
NOTES:  
1. Specifications measured with one output switching. See Figure 6 and Table 3 for derating.  
2. This parameter guaranteed by design and characterization, not by test.  
3. Output C = 5pF.  
L
8
1997 Feb 20  
Philips Semiconductors  
Product specification  
32 macrocell CPLD  
PZ3032  
DC ELECTRICAL CHARACTERISTICS FOR INDUSTRIAL GRADE DEVICES  
Industrial:  
–40°C ≤ T  
≤ +85°C; 3.0V ≤ V ≤ 3.6V  
amb  
DD  
SYMBOL  
PARAMETER  
TEST CONDITIONS  
MIN.  
MAX.  
UNIT  
V
V
V
V
V
V
Input voltage low  
V
DD  
V
DD  
= 3.0V  
= 3.6V  
0.8  
IL  
Input voltage high  
2.0  
V
IH  
I
Input clamp voltage  
V
= 3.0V, I = –18mA  
–1.2  
0.5  
V
DD  
IN  
Output voltage low  
V
DD  
= 3.0V, I = 8mA  
V
OL  
OH  
OL  
Output voltage high  
V
= 3.0V, I = –8mA  
2.4  
–10  
–10  
–10  
–10  
–10  
V
DD  
OH  
I
I
I
I
I
I
Input leakage current low  
Input leakage current high  
Clock input leakage current  
3-Stated output leakage current low  
3-Stated output leakage current high  
Standby current  
V
= 3.6V (except CKO), V = 0.4V  
10  
10  
µA  
µA  
µA  
µA  
µA  
µA  
mA  
mA  
mA  
pF  
pF  
pF  
IL  
DD  
IN  
V
DD  
V
DD  
V
DD  
V
DD  
= 3.6V, V = 3.0V  
IN  
IH  
= 3.6V, V = 0.4V  
10  
IL  
IN  
= 3.6V, V = 0.4V  
10  
OZL  
OZH  
DDQ  
IN  
= 3.6V, V = 3.0V  
10  
IN  
V
= 3.6V, T  
= –40°C  
45  
DD  
amb  
V
= 3.6V, T  
= –40°C @ 1MHz  
= –40°C @ 50MHz  
0.5  
18  
DD  
amb  
1
I
Dynamic current  
DDD  
V
= 3.6V, T  
amb  
DD  
I
Short circuit output current  
Input pin capacitance  
Clock input capacitance  
I/O pin capacitance  
1 pin at a time for no longer than 1 second  
–5  
5
–120  
8
OS  
C
C
C
T
= 25°C, f = 1MHz  
= 25°C, f = 1MHz  
= 25°C, f = 1MHz  
IN  
amb  
T
amb  
12  
CLK  
I/O  
T
amb  
10  
NOTE:  
1. This parameter measured with a 16–bit, loadable up/down counter loaded into every logic block, with all outputs enabled and unloaded.  
Inputs are tied to V or ground. This parameter guaranteed by design and characterization, not testing.  
DD  
1
AC ELECTRICAL CHARACTERISTICS FOR INDUSTRIAL GRADE DEVICES  
Industrial:  
–40°C ≤ T ≤ +85°C; 3.0V ≤ V ≤ 3.6V  
amb DD  
I10  
I12  
SYMBOL  
PARAMETER  
UNIT  
MIN. MAX. MIN. MAX.  
t
t
t
t
t
t
t
t
t
t
f
f
f
t
t
t
t
t
t
t
t
t
Propagation delay time, input (or feedback node) to output through PAL  
2
3
10  
12.5  
9
2
3
12  
15  
11  
ns  
ns  
PD_PAL  
PD_PLA  
CO  
Propagation delay time, input (or feedback node) to output through PAL & PLA  
Clock to out delay time  
2
2
ns  
Setup time (from input or feedback node) through PAL  
8
10.5  
13.5  
ns  
SU_PAL  
SU_PLA  
H
Setup time (from input or feedback node) through PAL + PLA  
10.5  
ns  
Hold time  
0
0
ns  
Clock High time  
Clock Low time  
Input rise time  
4
4
5
5
ns  
CH  
ns  
CL  
20  
20  
20  
20  
ns  
R
Input fall time  
ns  
F
2
Maximum FF toggle rate  
Maximum internal frequency  
Maximum external frequency  
Output buffer delay time  
(1/t + t )  
125  
64.5  
58.8  
100  
50  
MHz  
MHz  
MHz  
ns  
MAX1  
MAX2  
MAX3  
BUF  
CH  
CL  
2
(1/t  
+ t  
)
SUPAL  
CF  
2
(1/t  
+ t  
)
47  
SUPAL  
CO  
1.5  
8
1.5  
10.5  
13.5  
9.5  
50  
Input (or feedback node) to internal feedback node delay time through PAL  
Input (or feedback node) to internal feedback node delay time through PAL + PLA  
Clock to internal feedback delay time  
ns  
PDF_PAL  
PDF_PLA  
CF  
10.5  
7.5  
50  
ns  
ns  
Delay from valid V to valid reset  
µs  
INIT  
DD  
3
Input to output disable  
16  
19  
ns  
ER  
Input to output valid  
Input to register preset  
Input to register reset  
16  
19  
ns  
EA  
17  
20  
ns  
RP  
20  
23  
ns  
RR  
NOTES:  
1. Specifications measured with one output switching. See Figure 6 and Table 3 for derating.  
2. This parameter guaranteed by design and characterization, not by test.  
3. Output C = 5pF.  
L
9
1997 Feb 20  
Philips Semiconductors  
Product specification  
32 macrocell CPLD  
PZ3032  
SWITCHING CHARACTERISTICS  
The test load circuit and load values for the AC Electrical Characteristics are illustrated below.  
V
DD  
COMPONENT  
VALUES  
390Ω  
S1  
R1  
R2  
C1  
390Ω  
R1  
R2  
35pF  
V
IN  
V
OUT  
MEASUREMENT  
S1  
S2  
C1  
t
Open  
Closed  
Closed  
Closed  
PZH  
t
Closed  
Closed  
PZL  
t
P
S2  
NOTE: For t  
and t  
C = 5pF, and 3-State levels are  
PHZ  
PLZ  
measured 0.5V from steady-state active level.  
SP00477  
VOLTAGE WAVEFORM  
V
= 3.3V, 25°C  
nS  
9.50  
CC  
+3.0V  
90%  
8.50  
7.50  
6.50  
5.50  
4.50  
10%  
0V  
t
t
F
R
1.5ns  
1.5ns  
TYPICAL  
MEASUREMENTS:  
All circuit delays are measured at the +1.5V level of  
inputs and outputs, unless otherwise specified.  
Input Pulses  
SP00368  
16  
1
2
4
8
12  
SP00449A  
Figure 6.  
PD_PAL  
t
vs. Outputs switching  
PD_PAL  
Table 3. t  
DD  
vs. # of Outputs switching  
V
= 3.30V  
# of  
Outputs  
1
2
4
8
12  
16  
Typical  
(ns)  
6.2  
6.4  
6.6  
6.9  
7.2  
7.5  
10  
1997 Feb 20  
Philips Semiconductors  
Product specification  
32 macrocell CPLD  
PZ3032  
PIN DESCRIPTIONS  
Package Thermal Characteristics  
Philips Semiconductors uses the Temperature Sensitive Parameter  
(TSP) method to test thermal resistance. This method meets  
Mil-Std-883C Method 1012.1 and is described in Philips 1995 IC  
Package Databook. Thermal resistance varies slightly as a function  
of input power. As input power increases, thermal resistance  
changes approximately 5% for a 100% change in power.  
PZ3032 – 44-Pin Plastic Leaded Chip Carrier  
6
1
40  
7
39  
Figure 7 is a derating curve for the change in Θ with airflow based  
JA  
PLCC  
on wind tunnel measurements. It should be noted that the wind flow  
dynamics are more complex and turbulent in actual applications  
than in a wind tunnel. Also, the test boards used in the wind tunnel  
contribute significantly to forced convection heat transfer, and may  
not be similar to the actual circuit board, especially in size.  
17  
29  
18  
28  
Pin  
1
Function  
IN1  
Pin  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
Function  
I/O–A10  
I/O–A11  
I/O–A12  
I/O–A13  
I/O–A14  
I/O–A15  
Pin  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
Function  
I/O–B9  
I/O–B8  
I/O–B7  
I/O–B6  
2
IN3  
3
V
Package  
44-pin PLCC  
Θ
JA  
DD  
4
I/O–A0–CK1  
I/O–A1  
I/O–A2  
I/O–A3  
I/O–A4  
I/O–A5  
GND  
49.8°C/W  
66.3°C/W  
5
V
DD  
6
I/O–B5  
I/O–B4  
I/O–B3  
I/O–B2  
I/O–B1  
I/O–B0  
GND  
44-pin TQFP  
7
GND  
8
V
DD  
9
I/O–B15  
I/O–B14  
I/O–B13  
I/O–B12  
I/O–B11  
I/O–B10  
GND  
10  
11  
12  
13  
14  
15  
I/O–A6  
I/O–A7  
I/O–A8  
I/O–A9  
0
10  
20  
30  
40  
50  
PERCENTAGE  
REDUCTION IN  
IN0–CK0  
IN2–gtsn  
Θ
(%)  
JA  
V
DD  
SP00420  
PZ3032 – 44-Pin Thin Quad Flat Package  
44  
34  
1
33  
PLCC/  
QFP  
TQFP  
11  
23  
0
1
2
3
4
5
AIR FLOW (m/s)  
12  
22  
SP00419A  
Pin  
1
Function  
I/O–A3  
I/O–A4  
I/O–A5  
GND  
Pin  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
Function  
Pin  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
Function  
GND  
I/O–B4  
I/O–B3  
I/O–B2  
I/O–B1  
I/O–B0  
GND  
Figure 7. Average Effect of Airflow on Θ  
JA  
2
V
DD  
3
I/O–B15  
I/O–B14  
I/O–B13  
I/O–B12  
I/O–B11  
I/O–B10  
GND  
4
5
I/O–A6  
I/O–A7  
I/O–A8  
I/O–A9  
6
7
IN0/CK0  
IN2–gtsn  
IN1  
8
9
V
DD  
10  
11  
12  
13  
14  
15  
I/O–A10  
I/O–A11  
I/O–A12  
I/O–A13  
I/O–A14  
I/O–A15  
I/O–B9  
I/O–B8  
I/O–B7  
I/O–B6  
IN3  
V
DD  
I/O–A0–CK1  
I/O–A1  
V
I/O–A2  
DD  
I/O–B5  
SP00433  
11  
1997 Feb 20  
Philips Semiconductors  
Product specification  
32 macrocell CPLD  
PZ3032  
PLCC44: plastic leaded chip carrier; 44 leads  
SOT187-2  
12  
1997 Feb 20  
Philips Semiconductors  
Product specification  
32 macrocell CPLD  
PZ3032  
TQFP44: plastic thin quad flat package; 44 leads; body 10 x 10 x 1.0 mm  
SOT376-1  
13  
1997 Feb 20  
Philips Semiconductors  
Product specification  
32 macrocell CPLD  
PZ3032  
DEFINITIONS  
Data Sheet Identification  
Product Status  
Definition  
This data sheet contains the design target or goal specifications for product development. Specifications  
may change in any manner without notice.  
Objective Specification  
Formative or in Design  
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips  
Semiconductors reserves the right to make changes at any time without notice in order to improve design  
and supply the best possible product.  
Preliminary Specification  
Product Specification  
Preproduction Product  
Full Production  
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes  
at any time without notice, in order to improve design and supply the best possible product.  
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,  
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips  
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,  
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask  
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes  
only. PhilipsSemiconductorsmakesnorepresentationorwarrantythatsuchapplicationswillbesuitableforthespecifiedusewithoutfurthertesting  
or modification.  
LIFE SUPPORT APPLICATIONS  
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,  
orsystemswheremalfunctionofaPhilipsSemiconductorsandPhilipsElectronicsNorthAmericaCorporationProductcanreasonablybeexpected  
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips  
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully  
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.  
Philips Semiconductors  
811 East Arques Avenue  
P.O. Box 3409  
Copyright Philips Electronics North America Corporation 1997  
All rights reserved. Printed in U.S.A.  
Sunnyvale, California 94088–3409  
Telephone 800-234-7381  
Philips  
Semiconductors  

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