S9S08SC4E0CTGR_技术文档

Freescale Semiconductor

Data Sheet: Technical Data

Document Number: MC9S08SC4

Rev. 4, 6/2010

MC9S08SC4 8-Bit

Microcontroller Data Sheet

MC9S08SC4

948F-01

•

Breakpoint capability to allow single breakpoint setting

during in-circuit debugging

8-Bit HCS08 Central Processor Unit (CPU)

•

Up to 40 MHz HCS08 CPU (central processor unit); up

to 20 MHz bus frequency

Peripherals

•

HC08 instruction set with added BGND instruction

•

SCI — Serial Communication Interface

— Full-duplex non-return to zero (NRZ)

— LIN master extended break generation

— LIN slave extended break detection

— Wake-up on active edge

On-Chip Memory

•

4 KB of FLASH with read/program/erase over full

operating voltage and temperature

•

256 bytes of Random-access memory (RAM)

•

TPMx — Two 2-channel Timer/PWM modules (TPM1

and TPM2)

Power-Saving Modes

•

Two very low power stop modes

— 16-bit modulus or up/down counters

•

Reduced power wait mode

— Input capture, output compare, buffered

edge-aligned or center-aligned PWM

Clock Source Options

•

Oscillator (XOSC) — Loop-control Pierce oscillator;

Crystal or ceramic resonator range of 32 kHz to 38.4 kHz

or 1 MHz to 16 MHz

ADC — Analog to Digital Converter

— 8-channel, 10-bit resolution

— 2.5 μs conversion time

— Automatic compare function

— Temperature sensor

•

Internal Clock Source (ICS) — Internal clock source

module containing a frequency-locked loop (FLL)

controlled by internal or external reference; precision

trimming of internal reference allows 0.2 % resolution

and 2.0 % deviation over temperature and voltage;

supports bus frequencies from 2 MHz to 20 MHz.

— Internal bandgap reference channel

Input/Output

•

12 general purpose I/O pins (GPIOs)

System Protection

8 interrupt pins with selectable polarity

•

Watchdog computer operating properly (COP) reset with

option to run from dedicated 1 kHz internal clock source

or bus clock

Hysteresis and configurable pull-up device on all input

pins; Configurable slew rate and drive strength on all

output pins.

•

Low-voltage detection with reset or interrupt; selectable

trip points

Package Options

•

16-TSSOP

•

Illegal opcode detection with reset

Illegal address detection with reset

FLASH block protect

Operating Parameters

•

4.5-5.5 V operation

Reset on loss of clock

•

C,V, M temperature ranges available, covering -40 -

125 °C operation

Development Support

•

Single-wire background debug interface

Freescale reserves the right to change the detail specifications as may be required to permit

improvements in the design of its products.

Table of Contents

Chapter 1

Device Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

1.1 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

Chapter 2

Pins and Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

2.1 Device Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . .5

Chapter 3

3.9 Internal Clock Source (ICS) Characteristics . . . . . . . . 18

3.10 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.11 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.11.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.11.2 TPM Module Timing. . . . . . . . . . . . . . . . . . . . . 22

3.12 Flash Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.13 EMC Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.13.1 Radiated Emissions . . . . . . . . . . . . . . . . . . . . . 24

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

3.2 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . .7

3.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . .7

3.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .8

3.5 ESD Protection and Latch-Up Immunity . . . . . . . . . . . . .9

3.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

3.7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .13

3.8 External Oscillator (XOSC) Characteristics . . . . . . . . .16

Chapter 4

Ordering Information and Mechanical Drawings . . . . . . . . . . 25

4.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.1.1 Device Numbering Scheme . . . . . . . . . . . . . . . 25

4.2 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.3 Mechanical Drawings. . . . . . . . . . . . . . . . . . . . . . . . . . 25

Chapter 5

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

MC9S08SC4 MCU Series Data Sheet, Rev. 4

2

Freescale Semiconductor

Chapter 1

Device Overview

The MC9S08SC4 is a member of the low-cost, high-performance HCS08 Family of 8-bit microcontroller units (MCUs). The

MC9S08SC4 uses the enhanced HCS08 core.

1.1

MCU Block Diagram

The block diagram in Figure 1-1 shows the structure of the MC9S08SC4 MCU.

PTA3/PIA3/ADP3

PTA2/PIA2/ADP2

HCS08 CORE

BKGD/MS

PTA1/PIA1/TPM2CH0/ADP1

PTA0/PIA0/TPM1CH0/TCLK/ADP0

BDC

CPU

RESET

TCLK

HCS08 SYSTEM CONTROL

TPM1CH0

16-BIT TIMER/PWM

MODULE (TPM1)

TPM1CH1

RESETS AND INTERRUPTS

MODES OF OPERATION

POWER MANAGEMENT

PTB7/EXTAL

PTB6/XTAL

TCLK

16-BIT TIMER/PWM

MODULE (TPM2)

TPM2CH0

PTB5/TPM1CH1

PTB4/TPM2CH1

PTB3/PIB3/ADP7

COP

LVD

TPM2CH1

RxD

TxD

PTB2/PIB2/ADP6

SERIAL COMMUNICATIONS

INTERFACE MODULE (SCI)

USER FLASH

PTB1/PIB1/TxD/ADP5

PTB0/PIB0/RxD/ADP4

(MC9S08SC4 = 4096 BYTES)

USER RAM

(MC9S08SC4 = 256 BYTES)

SEE NOTE 1

V_DD

VOLTAGE

REGULATOR

40-MHz INTERNAL CLOCK

SOURCE (ICS)

V_SS

ADP7-ADP0

10-BIT

ANALOG-TO-DIGITAL

CONVERTER (ADC)

LOW-POWER OSCILLATOR

32 kHz to 38.4 kHz

1 MHz to 16 MHz

EXTAL

XTAL

V_DDA

V_SSA

V_REFH

V_REFL

NOTES

V_DDA/V_REFHand V_SSA/V_REFL, are derived from V_DDand V_SSrespectively.

1:

Figure 1-1. MC9S08SC4 Block Diagram

MC9S08SC4 MCU Series Data Sheet, Rev. 4

Freescale Semiconductor

3

Chapter 1 Device Overview

MC9S08SC4 MCU Series Data Sheet, Rev. 4

4

Freescale Semiconductor

Chapter 2

Pins and Connections

This section describes signals that connect to package pins. It includes pinout diagrams, recommended system connections, and

detailed discussions of signals.

2.1

Device Pin Assignment

The following figure shows the pin assignments for the MC9S08SC4 device.

PTA0/PIA0/TPM1CH0/TCLK/ADP0

PTA1/PIA1/TPM2CH0/ADP1

PTA2/PIA2/ADP2

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

RESET

BKGD/MS

V_DD

V_SS

PTB7/EXTAL

PTB6/XTAL

PTA3/PIA3/ADP3

PTB0/PIB0/RxD/ADP4

PTB1/PIB1/TxD/ADP5

PTB2/PIB2/ADP6

PTB5/TPM1CH1

PTB4/TPM2CH1

PTB3/PIB3/ADP7

Table 2-1. Pin Function Priority

Priority

Lowest

Highest

Number

16-pin

Port Pin

Alt 1

Alt 2

Alt 3

Alt 4

1

2

RESET

MS

BKGD

3

V

DD

SS

4

5

PTB7

PTB6

PTB5

PTB4

PTB3

PTB2

PTB1

EXTAL

6

XTAL

7

TPM1CH1

TPM2CH1

PIB3

8

9

ADP7

ADP6

ADP5

10

11

PIB2

PIB1

TxD

MC9S08SC4 MCU Series Data Sheet, Rev. 4

Freescale Semiconductor

5

Chapter 2 Pins and Connections

Table 2-1. Pin Function Priority (continued)

Priority

Lowest

Highest

Number

16-pin

Port Pin

Alt 1

PIB0

Alt 2

RxD

Alt 3

Alt 4

12

13

14

15

16

PTB0

PTA3

PTA2

PTA1

PTA0

ADP4

ADP3

ADP2

ADP1

ADP0

PIA3

PIA2

PIA1

PIA0

TPM2CH0

TPM1CH0

TCLK

MC9S08SC4 MCU Series Data Sheet, Rev. 4

6

Freescale Semiconductor

Chapter 3

Electrical Characteristics

3.1

Introduction

This section contains electrical and timing specifications for the MC9S08SC4 Series of microcontrollers available at the time

of publication.

3.2

Parameter Classification

The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better

understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate:

Table 3-1. Parameter Classifications

Those parameters are guaranteed during production testing on each individual device.

P

C

Those parameters are achieved by the design characterization by measuring a statistically relevant

sample size across process variations.

Those parameters are achieved by design characterization on a small sample size from typical devices

under typical conditions unless otherwise noted. All values shown in the typical column are within this

category.

T

Those parameters are derived mainly from simulations.

D

NOTE

The classification is shown in the column labeled “C” in the parameter tables where

appropriate.

3.3

Absolute Maximum Ratings

Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the

limits specified in Table 3-2 may affect device reliability or cause permanent damage to the device. For functional operating

conditions, refer to the remaining tables in this section.

This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised

that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this

high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for

instance, either V or V ) or the programmable pull-up resistor associated with the pin is enabled.

SS

DD

MC9S08SC4 MCU Series Data Sheet, Rev. 4

Freescale Semiconductor

7

Chapter 3 Electrical Characteristics

Table 3-2. Absolute Maximum Ratings

Rating

Symbol

Value

Unit

Supply voltage

V_DD

I_DD

V_In

I_D

–0.3 to +5.8

120

V

mA

V

Maximum current into V_DD

Digital input voltage

–0.3 to V_DD+ 0.3

± 25

Instantaneous maximum current

mA

Single pin limit (applies to all port pins)^{1, 2, 3}

Storage temperature range

T_stg

–55 to 150

°C

1

Input must be current limited to the value specified. To determine the value of the required

current-limiting resistor, calculate resistance values for positive (V_DD) and negative (V_SS) clamp

voltages, then use the larger of the two resistance values.

2

3

All functional non-supply pins are internally clamped to V_SSand V_DD

.

Power supply must maintain regulation within operating V_DDrange during instantaneous and

operating maximum current conditions. If positive injection current (V_In> V_DD) is greater than

I_DD, the injection current may flow out of V_DDand could result in external power supply going

out of regulation. Ensure external V_DDload will shunt current greater than maximum injection

current. This will be the greatest risk when the MCU is not consuming power. Examples are: if

no system clock is present, or if the clock rate is very low (which would reduce overall power

consumption).

3.4

Thermal Characteristics

This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power

dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and

it is user-determined rather than being controlled by the MCU design. To take P into account in power calculations, determine

I/O

the difference between actual pin voltage and V or V and multiply by the pin current for each I/O pin. Except in cases of

SS

DD

unusually high pin current (heavy loads), the difference between pin voltage and V or V will be very small.

SS

DD

Table 3-3. Thermal Characteristics

Num

C

Rating

Symbol

Value

Unit

1

—

Operating temperature range (packaged)

T_Lto T_H

–40 to 85

–40 to 105

–40 to 125

—

C

T_A

°C

V

M

Maximum junction temperature

2

D

C

V

T_JM

95

°C

115

M

135

Thermal resistance ^1,2

Single-layer board

3

4

D

16-pin TSSOP

θ_JA

130

87

°C/W

Thermal resistance^1,2

Four-layer board

16-pin TSSOP

θ_JA

MC9S08SC4 MCU Series Data Sheet, Rev. 4

8

Freescale Semiconductor

Chapter 3 Electrical Characteristics

1

2

Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting

site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board,

and board thermal resistance.

Junction to Ambient Natural Convection

The average chip-junction temperature (T ) in °C can be obtained from:

J

T = T + (P × θ )

JA

Eqn. 3-1

J

A

D

where:

T = Ambient temperature, °C

A

θ

= Package thermal resistance, junction-to-ambient, °C/W

JA

P = P + P

D

int

I/O

P = I × V , Watts — chip internal power

int

DD

P

= Power dissipation on input and output pins — user determined

I/O

For most applications, P << P and can be neglected. An approximate relationship between P and T (if P is neglected)

I/O

int

D

J

I/O

is:

P = K ÷ (T + 273°C)

Eqn. 3-2

D

J

Solving Equation 3-1 and Equation 3-2 for K gives:

2

K = P × (T + 273°C) + θ × (P )

Eqn. 3-3

D

A

JA

D

where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring P (at equilibrium)

D

for a known T . Using this value of K, the values of P and T can be obtained by solving Equation 3-1 and Equation 3-2

A

D

J

iteratively for any value of T

A

3.5

ESD Protection and Latch-Up Immunity

Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits,

normal handling precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure

that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.

All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During

the device qualification ESD stresses were performed for the human body model (HBM) and the charge device model (CDM).

A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete

DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot

temperature, unless specified otherwise in the device specification.

Table 3-4. ESD and Latch-up Test Conditions

Model

Description

Series resistance

Symbol

Value

Unit

Human

Body

R1

1500

Ω

pF

—

V

Storage capacitance

C

100

3

Number of pulses per pin

—

Latch-up Minimum input voltage limit

Maximum input voltage limit

–2.5

7.5

V

MC9S08SC4 MCU Series Data Sheet, Rev. 4

Freescale Semiconductor

9

Chapter 3 Electrical Characteristics

Table 3-5. ESD and Latch-Up Protection Characteristics

1

No.

1

Symbol

V_HBM

V_CDM

I_LAT

Min

± 2000

± 500

± 100

Max

—

Unit

V

Rating

Human body model (HBM)

Charge device model (CDM)

Latch-up current at T_A= 125°C

2

—

V

3

—

mA

1

Parameter is achieved by design characterization on a small sample size from typical devices

under typical conditions unless otherwise noted.

3.6

DC Characteristics

This section includes information about power supply requirements and I/O pin characteristics.

Table 3-6. DC Characteristics

Num

C

Characteristic

Symbol

Condition

Min

Typ¹

Max

Unit

4

— Operating voltage

V_DD

—

4.5

—

5.5

—

V

C

All I/O pins,

low-drive strength

All I/O pins,

5 V, I_Load= –4 mA

5 V, I_Load= –2 mA

5 V, I_Load= –20 mA

5 V, I_Load= –10 mA

V_OUT< V_DD

V_DD– 1.5

V_DD– 0.8

V_DD– 1.5

V_DD– 0.8

P Output high

C voltage

P

V_OH

V

5

6

7

high-drive strength

Output high

current

Max total I_OHfor

all ports

C

I_OHT

0

—

–100

mA

C

All I/O pins

low-drive strength

All I/O pins

5 V, I_Load= 4 mA

5 V, I_Load= 2 mA

5 V, I_Load= 20 mA

5 V, I_Load= 10 mA

V_OUT> V_SS

—

1.5

0.8

1.5

0.8

P Output low

C voltage

P

V_OL

V

high-drive strength

Output low

current

Max total I_OLfor all ports

8

9

C

I_OLT

0

—

100

mA

P Input high voltage; all digital inputs

V_IH

V_IL

5V

0.65 x V_DD

—

V

10 P Input low voltage; all digital inputs

11 C Input hysteresis

5V

—

0.06 x V_DD

—

0.35 x V_DD

V_hys

|I_In|

—

1

V

12 P Input leakage current (per pin)

V_In= V_DDor V_SS

0.1

μA

P

Hi-Z (off-state) leakage current (per pin)

13

14

input/output port pins |I_OZ|

V_In= V_DDor V_SS

,

—

0.1

0.2

1

2

μA

PTB6/XTAL,RESET

V_In= V_DDor V_SS

Pull-up or Pull-down²resistors; when

enabled

P

C

I/O pins R_PU,R_PD

RESET³

R_PU

—

17

37

52

kΩ

MC9S08SC4 MCU Series Data Sheet, Rev. 4

10

Freescale Semiconductor

Chapter 3 Electrical Characteristics

Table 3-6. DC Characteristics (continued)

Num

C

Characteristic

D DC injection current ^{4, 5, 6, 7}

Single pin limit

Symbol

Condition

Min

Typ¹

Max

Unit

V_IN> V_DD

0

—

2

–0.2

25

–5

8

mA

pF

V

15

I_IC

V_IN< V_SS

,

Total MCU limit, includes

sum of all stressed pins

V_IN> V_DD

0

—

V_IN< V_SS

,

0

—

16 D Input Capacitance, all pins

17 D RAM retention voltage

18 D POR re-arm voltage⁸

19 D POR re-arm time⁹

C_In

—

0.9

10

—

V_RAM

V_POR

t_POR

0.6

1.4

—

1.0

2.0

—

V

μs

P Low-voltage detection threshold —

high range

V_LVD1

V_LVW3

V_LVW2

20

V_DDfalling

_DDrising

3.85

3.95

4.0

4.1

4.15

4.25

V

Low-voltage warning threshold —

P high range 1

—

21

22

V_DDfalling

V_DDrising

4.45

4.55

4.6

4.7

4.75

4.85

Low-voltage warning threshold —

P high range 0

V_DDfalling

V_DDrising

4.15

4.25

4.3

4.4

4.45

4.55

T

P

Low-voltage inhibit reset/recover

hysteresis

Bandgap Voltage Reference¹⁰

V_hys

V_BG

23

24

—

100

—

mV

V

1.17

1.20

1.22

1

2

3

Typical values are measured at 25°C. Characterized, not tested.

When a pin interrupt is configured to detect rising edges, pull-down resistors are used in place of pull-up resistors.

The specified resistor value is the actual value internal to the device. The pull-up value may measure higher when measured

externally on the pin.

4

Power supply must maintain regulation within operating V_DDrange during instantaneous and operating maximum current

conditions. If positive injection current (V_In> V_DD) is greater than I_DD, the injection current may flow out of V_DDand could result

in external power supply going out of regulation. Ensure external V_DDload will shunt current greater than maximum injection

current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if

clock rate is very low (which would reduce overall power consumption).

5

6

All functional non-supply pins are internally clamped to V_SSand V_DD

.

Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate

resistance values for positive and negative clamp voltages, then use the larger of the two values.

7

8

9

The RESET pin does not have a clamp diode to V_DD. Do not drive this pin above V_DD

.

Maximum is highest voltage that POR will occur.

Simulated, not tested

¹⁰Factory trimmed at V_DD= 5.0 V, Temp = 25°C

MC9S08SC4 MCU Series Data Sheet, Rev. 4

Freescale Semiconductor

11

Chapter 3 Electrical Characteristics

2

1.5

1

125°C

25°C

–40°C

Max 1.5V@20mA

0.5

0

5

10

15

(mA)

20

25

I

OL

a) V = 5V, High Drive

DD

Figure 3-1. Typical V vs I , High Drive Strength

OL

2

1.5

1

125°C

25°C

–40°C

Max 1.5V@4mA

0.5

0

1

2

3

4

5

I

(mA)

OL

a) V = 5V, Low Drive

DD

Figure 3-2. Typical V vs I , Low Drive Strength

OL

MC9S08SC4 MCU Series Data Sheet, Rev. 4

12

Freescale Semiconductor

Chapter 3 Electrical Characteristics

2

1.5

1

125°C

25°C

–40°C

Max 1.5V@ –20mA

0.5

0

–5

–10

–15

(mA)

–20

–25

I

OH

a) V = 5V, High Drive

DD

Figure 3-3. Typical V – V vs I , High Drive Strength

DD

OH

2

1.5

1

125°C

25°C

–40°C

Max 1.5V@ –4mA

0.5

0

–1

–2

–3

(mA)

–4

–5

I

OH

a) V = 5V, Low Drive

DD

Figure 3-4. Typical V – V vs I , Low Drive Strength

DD

OH

3.7

Supply Current Characteristics

This section includes information about power supply current in various operating modes.

MC9S08SC4 MCU Series Data Sheet, Rev. 4

Freescale Semiconductor

13

Chapter 3 Electrical Characteristics

Table 3-7. Supply Current Characteristics

V_DD

Num

C

Parameter

Symbol

Typ¹

Max²

Unit

(V)

1

C

Run supply current³measured at

(CPU clock = 4 MHz, f_Bus= 2 MHz)

RI_DD

5

1.9

2.4

mA

2

3

P

C

Run supply current³measured at

(CPU clock = 16 MHz, f_Bus= 8 MHz)

Run supply current⁴measured at

(CPU clock = 32 MHz, f_Bus= 16 MHz)

RI_DD

5

4.6

7.8

5.6

8.9

C

P

C⁵

P⁵

C

–40 °C (C & M suffix)

0.71

0.93

4

—

11

30

60

—

8

Stop3 mode

25 °C (All parts)

85 °C (C suffix only)

105 °C (V suffix only)

125 °C (M suffix only)

–40 °C (C & M suffix)

25 °C (All parts)

4

5

supply current

S3I_DD

5

μA

9

28

0.70

0.89

3

P

Stop2 mode

C⁵

P⁵

C

supply current

85 °C (C suffix only)

105 °C (V suffix only)

125 °C (M suffix only)

S2I_DD

6

22

41

165

8

17

110

5

6

7

LVD adder to stop3 (LVDE = LVDSE = 1)

Adder to stop3 for oscillator enabled⁶

(EREFSTEN =1)

S3I_DDLVD

S3I_DDOSC

5

μA

C

1

Typical values are based on characterization data at 25 °C. See Figure 3-5 through Figure 3-7 for typical curves

across voltage/temperature.

2

3

4

5

Max values in this column apply for the full operating temperature range of the device unless otherwise noted.

All modules except ADC active, ICS configured for FBE, and does not include any dc loads on port pins.

All modules except ADC active, ICS configured for FEI, and does not include any dc loads on port pins.

Stop currents are tested in production for 25 °C on all parts. Tests at other temperatures depend upon the part

number suffix and maturity of the product. Freescale may eliminate a test insertion at a particular temperature

from the production test flow once sufficient data has been collected and is approved.

6

Values given under the following conditions: low range operation (RANGE = 0) with a 32.768 kHz crystal and low

power mode (HGO = 0).

MC9S08SC4 MCU Series Data Sheet, Rev. 4

14

Freescale Semiconductor

Chapter 3 Electrical Characteristics

10

8

FEI

FBELP

6

4

2

0

20

0 1

2

4

8

16

f

(MHz)

bus

Figure 3-5. Typical Run I vs. Bus Frequency (V = 5V)

DD

5

4

3

2

1

0

125

–40

0

25

Temperature (°C

85

105

)

Note: ICS is configured to FEI.

Figure 3-6. Typical Run I vs. Temperature (V = 5V; f = 8MHz)

DD

bus

MC9S08SC4 MCU Series Data Sheet, Rev. 4

Freescale Semiconductor

15

Chapter 3 Electrical Characteristics

50

STOP2

STOP3

40

30

20

10

0

125

–40

0

25

85

105

Temperature (°C

)

Figure 3-7. Typical Stop I vs. Temperature (V = 5V)

DD

3.8

External Oscillator (XOSC) Characteristics

NOTE

The MC9S08SC4 series supports a narrower low frequency external reference range than

the standard ICS specification. All references to range "31.25 kHz to 39.0625 kHz" in this

section should be limited to " 32.0 kHz to 38.4 kHz".

MC9S08SC4 MCU Series Data Sheet, Rev. 4

16

Freescale Semiconductor

Chapter 3 Electrical Characteristics

Table 3-8. Oscillator Electrical Specifications (Temperature Range = –40 to 125°C Ambient)

Num

C

Rating

Symbol

Min

Typ¹

Max

Unit

Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1)

Low range (RANGE = 0)

f_lo

f_hi

32

1

—

38.4

5

kHz

MHz

High range (RANGE = 1) FEE or FBE mode ²

High range (RANGE = 1, HGO = 1) FBELP mode

High range (RANGE = 1, HGO = 0) FBELP mode

Load capacitors

1

C

f_hi-hgo

f_hi-lp

1

16

8

1

See crystal or resonator

manufacturer’s recommendation

C

_1,C₂

2

3

—

Feedback resistor

R_F

Low range (32 kHz to 100 kHz)

High range (1 MHz to 16 MHz)

Series resistor

—

10

1

—

MΩ

Low range, low gain (RANGE = 0, HGO = 0)

Low range, high gain (RANGE = 0, HGO = 1)

High range, low gain (RANGE = 1, HGO = 0)

High range, high gain (RANGE = 1, HGO = 1)

≥ 8 MHz

—

0

100

0

—

R_S

4

—

kΩ

—

0

4 MHz

10

20

1 MHz

Crystal start-up time ³

t

Low range, low gain (RANGE = 0, HGO = 0)

—

200

400

5

—

CSTL-LP

t

Low range, high gain (RANGE = 0, HGO = 1)

High range, low gain (RANGE = 1, HGO = 0)⁴

High range, high gain (RANGE = 1, HGO = 1)⁴

5

6

T

ms

CSTL-HGO

t

CSTH-LP

t

15

CSTH-HGO

Square wave input clock frequency (EREFS = 0, ERCLKEN = 1)

FEE or FBE mode ²

0.03125

0

—

5

MHz

f_extal

FBELP mode

40

1

2

3

Typical data was characterized at 5.0 V, 25°C or is recommended value.

The input clock source must be divided using RDIV to within the range of 31.25 kHz to 39.0625 kHz.

This parameter is characterized and not tested on each device. Proper PC board layout procedures must be followed to achieve

specifications. This data will vary based upon the crystal manufacturer and board design. The crystal should be characterized

by the crystal manufacturer.

4

4 MHz crystal.

MC9S08SC4 MCU Series Data Sheet, Rev. 4

Freescale Semiconductor

17

Chapter 3 Electrical Characteristics

MCU

EXTAL

XTAL

R_S

R_F

C₁

Crystal or Resonator

C₂

3.9

Internal Clock Source (ICS) Characteristics

Table 3-9. ICS Frequency Specifications (Temperature Range = –40 to 125°C Ambient)

Num

C

P

T

Rating

Symbol

Min

Typical

Max

Unit

Internal reference frequency - factory trimmed

at V_DD= 5 V and temperature = 25°C

f_{int_ft}

1

—

31.25

—

kHz

Internal reference frequency - untrimmed¹

f_{int_ut}

f_{int_t}

2

3

4

25

31.25

—

36

—

41.66

39.0625

6

kHz

μs

P Internal reference frequency - user trimmed

t_irefst

T Internal reference startup time

DCO output frequency range - untrimmed¹

— value provided for reference assumes:

fdco_ut = 1024 x f_{int_ut}

f_{dco_ut}

5

25.6

36.86

42.66

MHz

f_{dco_t}

6

7

D DCO output frequency range - trimmed

32

—

40

MHz

Resolution of trimmed DCO output frequency at fixed

Δf_{dco_res_t}

%f_dco

D

± 0.1

± 0.2

voltage and temperature (using FTRIM)

Resolution of trimmed DCO output frequency at fixed

voltage and temperature (not using FTRIM)

Δf_{dco_res_t}

Δf_{dco_t}

%f_dco

8

9

D

—

± 0.2

± 0.4

± 2.0

± 1

Total deviation from actual trimmed DCO output

frequency over voltage and temperature

+ 0.5

– 1.0

D

Total deviation of trimmed DCO output frequency over

fixed voltage and temperature range of 0°C to 70 °C

Δf_{dco_t}

10

D

± 0.5

FLL acquisition time ²

t_acquire

C_Jitter

11

12

D

—

1

ms

DCO output clock long term jitter (over 2mS interval) ³

D

%f_dco

0.02

0.2

1

2

TRIM register at default value (0x80) and FTRIM control bit at default value (0x0).

This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing

from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference,

this specification assumes it is already running.

3

Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f_BUS

.

Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected

into the FLL circuitry via V_DDand V_SSand variation in crystal oscillator frequency increase the C_Jitterpercentage for a given

interval.

MC9S08SC4 MCU Series Data Sheet, Rev. 4

18

Freescale Semiconductor

Chapter 3 Electrical Characteristics

3.10 ADC Characteristics

Table 3-10. ADC Operating Conditions

Characteristic

Conditions

Symb

Min

Typ¹

Max

Unit

Comment

2

Supply voltage

Input Voltage

Absolute

V_DDA

2.7

V_REFL

—

5.5

V_REFH

5.5

V

—

2

—

V_ADIN

C_ADIN

Input

4.5

pF

Capacitance

Input

Resistance

—

R_ADIN

—

3

5

kΩ

—

Analog Source

Resistance

10 bit mode

_ADCK> 4MHz

R_AS

External to MCU

f

—

5

10

f_ADCK< 4MHz

8 bit mode (all valid f_ADCK

High Speed (ADLPC=0)

Low Power (ADLPC=1)

)

—

10

8.0

4.0

ADC

Conversion

Clock

f_ADCK

0.4

MHz

—

Frequency

1

2

Typical values assume VDDA = 5.0 V, Temp = 25°C, fADCK=1.0 MHz unless otherwise stated. Typical values are for

reference only and are not tested in production.

V_DDA/V_REFHand V_SSA/V_REFL, are derived from V_DDand V_SSrespectively.

SIMPLIFIED

INPUT PIN EQUIVALENT

Z_ADIN

CIRCUIT

SIMPLIFIED

CHANNEL SELECT

CIRCUIT

Pad

Z_AS

leakage

due to

ADC SAR

ENGINE

input

protection

R_AS

R_ADIN

+

V_ADIN

–

C_AS

V_AS

+

–

R_ADIN

INPUT PIN

C_ADIN

Figure 3-8. ADC Input Impedance Equivalency Diagram

MC9S08SC4 MCU Series Data Sheet, Rev. 4

Freescale Semiconductor

19

Chapter 3 Electrical Characteristics

Table 3-11. ADC Characteristics

Characteristic

Conditions

C

Symb

Min

Typ¹

Max

Unit

Comment

Supply Current

ADLPC=1

ADLSMP=1

ADCO=1

—

T

I_DDA

—

133

—

μA

—

Supply Current

ADLPC=1

ADLSMP=0

ADCO=1

T

I_DDA

—

218

327

—

1

μA

—

Supply Current

ADLPC=0

ADLSMP=1

ADCO=1

Supply Current

ADLPC=0

ADLSMP=0

ADCO=1

0.582

mA

MHz

ADC

Asynchronous

Clock Source

High Speed (ADLPC=0)

Low Power (ADLPC=1)

f_ADACK

2

3.3

2

5

t_ADACK=

1/f_ADACK

P

1.25

3.3

Conversion

Time

(Including

sample time)

Short Sample

(ADLSMP=0)

P

t_ADC

—

20

40

—

ADCK

cycles

See ADC

chapter in

MC9S08SC4

Reference

Manual for

conversion

time

Long Sample

(ADLSMP=1)

Sample Time

Short Sample

(ADLSMP=0)

P

t_ADS

3.5

23.5

ADCK

cycles

variances

Long Sample

(ADLSMP=1)

Total

Unadjusted

Error

10 bit mode

8 bit mode

P

E_TUE

DNL

—

±1.5

±0.7

±3.5

±1.5

LSB

Includes

quantization

Differential

Non-Linearity

10 bit mode

8 bit mode

—

±0.5

±0.3

±1.0

±0.5

Monotonicity and No-Missing-Codes guaranteed

Integral

Non-Linearity

10 bit mode

8 bit mode

10 bit mode

8 bit mode

10 bit mode

8 bit mode

C

INL

E_ZS

E_FS

—

±0.5

±0.3

±1.5

±0.5

±1

±1.0

±0.5

±2.5

±0.7

±1.5

±0.5

LSB

Zero-Scale

Error

P

V_ADIN= V_SSA

Full-Scale

Error

V_ADIN= V_DDA

P

±0.5

MC9S08SC4 MCU Series Data Sheet, Rev. 4

20

Freescale Semiconductor

Chapter 3 Electrical Characteristics

Table 3-11. ADC Characteristics

Characteristic

Conditions

10 bit mode

C

Symb

Min

Typ¹

Max

Unit

Comment

Quantization

Error

D

E_Q

—

±0.5

±2.5

±1

LSB

—

8 bit mode

10 bit mode

8 bit mode

−40°C– 25°C

—

Input Leakage

Error

D

E_IL

m

±0.2

±0.1

3.266

LSB

Pad leakage²

* R_AS

Temp Sensor

Slope

—

mV/°C

—

25°C– 125°C

25°C

—

3.638

1.396

Temp Sensor

Voltage

D

V_TEMP2

V

—

5

1

2

Typical values assume V_DDA= 5.0V, Temp = 25C, f_ADCK=1.0MHz unless otherwise stated. Typical values are for reference only

and are not tested in production.

Based on input pad leakage current. Refer to pad electricals.

3.11 AC Characteristics

This section describes AC timing characteristics for each peripheral system.

3.11.1 Control Timing

Table 3-12. Control Timing

Num

C

D

P

D

Rating

Symbol

f_Bus

Min

dc

Typ¹

—

Max

20

Unit

MHz

μs

Bus frequency (t_cyc= 1/f_Bus

)

Internal low power oscillator period

External reset pulse width²

Reset low drive³

1

2

3

4

t_LPO

700

975

—

1500

—

t_extrst

t_rstdrv

100

ns

66 x t_cyc

—

ns

Pin interrupt pulse width

Asynchronous path²

Synchronous path⁴

5

D

t_{ILIH, IHIL}

t

100

1.5 x t_cyc

—

ns

Port rise and fall time —

Low output drive (PTxDS = 0) (load = 50 pF)⁵

Slew rate control disabled (PTxSE = 0)

Slew rate control enabled (PTxSE = 1)

t_Rise, t_Fall

—

40

75

—

6

C

Port rise and fall time —

High output drive (PTxDS = 1) (load = 50 pF)⁶

Slew rate control disabled (PTxSE = 0)

Slew rate control enabled (PTxSE = 1)

t_Rise, t_Fall

ns

—

11

35

—

1

Typical values are based on characterization data at V_DD= 5.0V, 25°C unless otherwise stated.

MC9S08SC4 MCU Series Data Sheet, Rev. 4

Freescale Semiconductor

21

Chapter 3 Electrical Characteristics

2

This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to

override reset requests from internal sources. Refer to Figure 3-9.

3

When any reset is initiated, internal circuitry drives the reset pin low for about 66 cycles of t_cyc. After POR reset the bus clock

frequency changes to the untrimmed DCO frequency (f_reset= (f_{dco_ut})/4) because TRIM is reset to 0x80 and FTRIM is reset

to 0, and there is an extra divide-by-two because BDIV is reset to 0:1. After other resets trim stays at the pre-reset value.

4

This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or

may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.

5

Timing is shown with respect to 20% V_DDand 80% V_DDlevels. Temperature range –40°C to 125°C.

t_extrst

RESET PIN

Figure 3-9. Reset Timing

3.11.2 TPM Module Timing

Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the

optional external source to the timer counter. These synchronizers operate from the current bus rate clock.

Table 3-13. TPM Input Timing

Num

C

Rating

Symbol

Min

Max

Unit

1

2

3

4

5

—

External clock frequency

External clock period

f_TEXT

t_TEXT

dc

4

1/4 f_op

—

MHz

t_CYC

External clock high time

External clock low time

Input capture pulse width

t_TCLKH

t_TCLKL

f_ICPW

1.5

—

MC9S08SC4 MCU Series Data Sheet, Rev. 4

22

Freescale Semiconductor

Chapter 3 Electrical Characteristics

t_CYC

ipg_clk

t_TEXT

EXTERNAL

CLOCK

t_TCLKL

t_TCLKH

t_ICPW

INPUT

CAPTURE

3.12 Flash Specifications

This section provides details about program/erase times and program-erase endurance for the FLASH memory.

Program and erase operations do not require any special power sources other than the normal V supply. For more detailed

DD

information about program/erase operations, see the Memory section.

Table 3-14. FLASH Characteristics

Num

C

Characteristic

Symbol

Min

Typical

Max

Unit

1

2

3

4

5

6

7

8

—

Supply voltage for program/erase

Supply voltage for read operation

Internal FCLK frequency¹

V_prog/erase

V_Read

f_FCLK

t_Fcyc

4.5

150

5

—

5.5

V

—

200

6.67

kHz

μs

Internal FCLK period (1/f_FCLK

)

—

Byte program time (random location)²

Byte program time (burst mode)²

Page erase time²

t_prog

9

t_Fcyc

t_Burst

4

t_Page

4000

20,000

Mass erase time²

t_Mass

Program/erase endurance³

T_Lto T_H= –40°C to +125°C

T = 25°C

n_FLPE

9

C

10,000

—

100,000

—

cycles

years

10

C

Data retention⁴

t_{D_ret}

15

100

—

1

2

The frequency of this clock is controlled by a software setting.

These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for

calculating approximate time to program and erase.

3

4

Typical endurance for FLASH is based on the intrinsic bit cell performance. For additional information on how Freescale

defines typical endurance, please refer to Engineering Bulletin EB619/D, Typical Endurance for Nonvolatile Memory.

Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated

to 25°C using the Arrhenius equation. For additional information on how Freescale defines typical data retention, please refer

to Engineering Bulletin EB618/D, Typical Data Retention for Nonvolatile Memory.

MC9S08SC4 MCU Series Data Sheet, Rev. 4

Freescale Semiconductor

23

Chapter 3 Electrical Characteristics

3.13 EMC Performance

Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board

design and layout, circuit topology choices, location and characteristics of external components as well as MCU software

operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such

as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC

performance.

3.13.1 Radiated Emissions

Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell method in accordance

with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed with the microcontroller installed on a

custom EMC evaluation board while running specialized EMC test software. The radiated emissions from the microcontroller

are measured in a TEM cell in two package orientations (North and East).

The maximum radiated RF emissions of the tested configuration in all orientations are less than or equal to the reported

emissions levels.

Table 3-15. Radiated Emissions, Electric Field

Level¹

Parameter

Symbol

Conditions

Frequency

f_OSC/f_BUS

Unit

(Max)

V_{RE_TEM}

V_DD= 5 V

T_A= +25^oC

package type

16-TSSOP

0.15 – 50 MHz

50 – 150 MHz

150 – 500 MHz

500 – 1000 MHz

IEC Level

4 MHz crystal

8 MHz bus

–7

–11

–10

N

dBμV

Radiated emissions,

electric field

—

SAE Level

1

Data based on qualification test results.

MC9S08SC4 MCU Series Data Sheet, Rev. 4

24

Freescale Semiconductor

Chapter 4 Ordering Information and Mechanical Drawings

Chapter 4

Ordering Information and Mechanical Drawings

4.1

Ordering Information

This section contains ordering information for MC9S08SC4 device.

Table 4-1. Device Numbering System

Memory

Available

Device Number¹

Packages²

FLASH

RAM

S9S08SC4E0MTG

4K

256

16 TSSOP

1

2

See MC9S08SC4 Reference Manual for a complete description of modules.

included on each device.

See Table 4-2 for package information.

4.1.1

Device Numbering Scheme

S 9 S08 SC 4 E0 M TG R

Status

- S = Auto Qualified

Tape and Reel Suffix (optional)

Package Designator

Two letter descriptor

(refer to Table 4-2).

Main Memory Type

- 9 = Flash-based

Temperature Option

- C = –40 to 85 °C

- V = –40 to 105 °C

- M = –40 to 125 °C

Core

S Family

Memory Size

- 4 Kbytes

Mask Set Identifier

- Identifies mask.

4.2

4.3

Package Information

Table 4-2. Package Information

Pin Count

Type

Designator

Case Number

Document No.

98ASH70247A

16

TSSOP

TG

948F-01

Mechanical Drawings

The following pages are mechanical drawings for the package described in Table 4-2.

MC9S08SC4 MCU Series Data Sheet, Rev. 4

Freescale Semiconductor

25

Chapter 4 Ordering Information and Mechanical Drawings

MC9S08SC4 MCU Series Data Sheet, Rev. 4

26

Freescale Semiconductor

Chapter 4 Ordering Information and Mechanical Drawings

MC9S08SC4 MCU Series Data Sheet, Rev. 4

Freescale Semiconductor

27

Chapter 4 Ordering Information and Mechanical Drawings

MC9S08SC4 MCU Series Data Sheet, Rev. 4

28

Freescale Semiconductor

Chapter 5 Revision History

Chapter 5

Revision History

To provide the most up-to-date information, the version of our documents on the World Wide Web will be the most current.

Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:

http://freescale.com/

The following revision history table summarizes changes contained in this document.

Revision

Number

Revision

Date

Description of Changes

1

2

9/2008

7/2009

• Initial Release.

• Incorporated editing updates.

• Added C and V temperature ranges at page 1.

• Updated Section 3.10, “ADC Characteristics”.

• Updated Table 3-3, Table 3-6, Table 3-7, Table 3-9, Table 3-12, Table 3-15 and Section

4.1.1, “Device Numbering Scheme”.

• Added actual package mechanical drawings.

• Updated Figure 3-5, Figure 3-6.

• Removed Transient Susceptibilty Section.

• Updated disclaimer page.

3

4

3/2010

6/2010

• Updated TSSOP-16 package diagram, clarified ICS deviation, SCI LIN features at page

1.

• Updated Table 3-6, Table 3-7, Table 3-9, Table 3-12, Table 4-1.

• Updated Figure 3-5 and Figure 3-7.

• Document changed from Advance Information to Technical Data

• Updated footnotes in Table 3-7

• Updated Figure 3-5

MC9S08SC4 MCU Series Data Sheet, Rev. 4

Freescale Semiconductor

29

Chapter 5 Revision History

MC9S08SC4 MCU Series Data Sheet, Rev. 4

30

Freescale Semiconductor

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MC9S08SC4

Rev.4

6/2010


型号：	S9S08SC4E0CTGR
厂家：	NXP
描述：	MC9S08SC4 8-Bit Microcontroller Data Sheet 微控制器
文件：	总31页 (文件大小：746K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

S9S08SC4E0CTGR [NXP]

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SI9130DB

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SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E