SA1620 [NXP]
Low voltage GSM front-end transceiver; 低压GSM前端收发器
| 型号： | SA1620 |
| 厂家： | 
NXP |
| 描述： | Low voltage GSM front-end transceiver |
| 文件： | 总26页 (文件大小：206K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
SA1620
Low voltage GSM front-end transceiver
Product specification
1997 May 22
Supersedes data of 1996 Oct 08
IC17 Data Handbook
Philips
Semiconductors
Philips Semiconductors
Product specification
Low voltage GSM front-end transceiver
SA1620
DESCRIPTION
• Feedthrough attenuation LNA1 to Rx mixer ≥ 35dB
The SA1620 is a combined receive (Rx) and transmit (Tx) front-end
for GSM cellular telephones. The receive path contains two low
noise amplifiers (LNA1 and LNA2) with four switchable attenuation
steps. A Gilbert Cell mixer in the receive path down-converts the
RF signal to a first IF of 70 to 500 MHz. A second Gilbert Cell in the
transmit path transposes a GMSK or phase modulated IF to RF by
image reject mixing and has a fixed IF of 400 MHz. A buffered LO
signal is fed to Rx and Tx mixers. Rx or Tx path or the entire circuit
may be powered-down.
• Tx power adjustable from -3 to +12dBm by external resistor
• Direct supply: 2.7V to 5.5V
• Battery supply voltage V
= 3.3V to 7.5V or direct supply
BATT
• Two DC regulators programmable for 3.0V, 3.4V, 3.7V or 5.1V
• Low current consumption: 28mA for Rx or 59mA for Tx
• Fully compatible with SA1638 GSM IF Digital I/Q circuit
FEATURES
APPLICATIONS
• Excellent noise figure: <2dB for the LNAs at 950MHz
• 900MHz front end for GSM hand-held units
• LNAs matched to 50Ω with external matching components
• LNAs with gain control, 59dB dynamic range in four discrete steps
• LNA gain stability ±0.5dB within -40 to 85°C
• Portable radio, TDMA systems
PIN CONFIGURATION
LQFP Package
48 47 46 45 44 43 42 41 40 39 38 37
36
35
V
BATT
PON
1
2
V
CCL2
IN2
34 GNDREG1
VREG1
32 VREGF2
3
GNDL2
GNDL2A
OUT2
33
4
5
31
30
29
28
27
26
25
VREG2
GNDREG2
CON1
6
B
A
48–PIN LQFP
7
INM
8
LO INX
LO IN
9
INMX
COMP2
COMP1
10
11
12
CON2
GNDTx2
V
BM
CC
13 14 15 16 17 18 19 20 21 22 23 24
SR00127
Figure 1. Pin Configuration
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
ORDER CODE
DWG #
-40 to +85°C
48-Pin Thin Quad Flat Pack (TQFP)
SA1620BE
SOT313-2
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
RATING
UNITS
V
Supply voltages
2.7 to 5.5
3.3 to 7.5
-40 to +85
V
V
CCXX
V
Battery voltage
BATT
T
A
Operating ambient temperature range
°C
2
1997 May 22
853-1784 18066
Philips Semiconductors
Product specification
Low voltage GSM front-end transceiver
SA1620
BLOCK DIAGRAM
PDTx
VREG2
PONRx
BANDGAP
VREG2F2
GNDREG2
BIAS SUPPLIES
VOLTAGE REGULATORS
PONBUF
GNDREG1
VREG1
V
V
Tx1
Tx2
CC
CC
TxO
TxIF
SINGLE
SIDEBAND
MIXER
LINEAR
IF LEVEL
CONTROL
TxOX
TxIFX
RETx
TLO
LO IN
LO INPUT
BUFFER
LO INX
BUFFER
A
B
TLOX
ATTENUATION
CONTROL LOGIC
BUFFER
V
L1
L2
CC
CC
V
RxIF
IN1
LNA2
LNA1
RxIFX
SR00129
Figure 2. Block Diagram
3
1997 May 22
Philips Semiconductors
Product specification
Low voltage GSM front-end transceiver
SA1620
PIN DESCRIPTIONS
Pin No. Pin Name
DC Regulators
Description
Pin No. Pin Name
Description
13
14
GNDBM
PONRx
RxIF
Ground for Rx Bias and Rx mixer
Power on input for Rx bias supply
IF output, open collector
Inverse IF output, open collector
Input to LNA1
15
18
21
26
GND1
GND2
GND3
CON2
Ground of regulator supply
Ground of regulator supply
Ground of regulator supply
16
17
RxIFX
IN1
Control 2, voltage select for regulator 1
and 2
44
45
GNDL1
GNDL1A
OUT1
Ground L1 for LNA1
29
CON1
Control 1, voltage select for regulator 1
and 2
46
Ground L1A for LNA1
47
Output LNA1
30
GNDREG2 Ground of regulator 2
48
V
L1
Positive supply for LNA1
CC
31
VREG2
Output of regulator 2
Feedback of regulator 2
Output of regulator 1
Tx Path
19
32
VREG2F2
VREG1
TxIF
IF input for Tx
33
20
TxIFX
Inverse IF input for Tx
34
GNDREG1 Ground of regulator 1
22
V
Tx1
Positive supply for Tx input
Ground for Tx input
CC
35
PON
Power-on input of regulators
Input of regulator 1 and 2
23
GNDTx1
Tx2
36
V
BATT
24
V
CC
Positive supply for LO and Tx input
Ground for LO and Tx input
Power down Tx input
Rx Path
25
GNDTx2
PDTx
1
2
3
4
5
6
7
8
9
V
CC
L2
Positive supply for LNA2
Input LNA2
38
IN2
39
GNDTx4
TxOX
Ground for Tx output
GNDL2
GNDL2A
OUT2
B
Ground L2 for LNA2
40
Inverse Tx output, open collector
Tx output, open collector
Ground 1 for Tx output side
Reference resistor for Tx output current
Ground L2A for LNA2
41
TxO
Output LNA2
42
GNDTx3
RETx
Attenuation select B for LNA1 and LNA2
Attenuation select A for LNA1 and LNA2
RF input for Rx mixer, open emitter
43
A
Elements for Tx and Rx Path
INM
27
28
37
LO IN
Input for Local Oscillator signal
Inverse input for LO or AC ground
INMX
Inverse RF input for Rx mixer, open
emitter
LO INX
PONBUF
10
11
12
COMP2
COMP1
Capacitor for bias stabilization
Capacitor for bias stabilization
Power on first stage LO input buffer and
bias
V
CC
BM
V
CC
for Rx Bias and Rx mixer
NOTES:
1. Device is ESD sensitive. There are no ESD protection diodes at Pins 16, 17, 40 and 41. Thus, open-collector outputs may have increased
DC voltage or higher AC peak voltage.
2. Pins 15, 18 and 21 are connected to each other and to a separate ground in REG1 and REG2.
3. Pins 23, 25, 42 and 39 are connected to each other and to the Tx path, LO buffer and associated bias supplies.
4. Pins 22 and 24 are connected to each other providing a sense input. They are also connected to the Tx path, LO buffer and associated bias
supplies.
5. Pins 30 and 34 are not internally connected. They must be connected to external grounds.
6. Pins 48, 1, and 12 are not internally connected and have no ESD protection diodes between them. Power may be saved by connecting
V
CC
L1 and IN1 or V L2 and IN2 to ground if LNA1 or LNA2 is not needed.
CC
4
1997 May 22
Philips Semiconductors
Product specification
Low voltage GSM front-end transceiver
SA1620
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
-0.3 to +6.0
-0.3 to +8.0
UNITS
V
V
CCXX
Supply voltages
Battery voltage
V
BATT
V
V
Voltage applied to any other pin
Tx1,2 pins to V BM
-0.3 to (V
+0.3)
V
IN
CCXX
∆V
V
-0.3 to +1
V
CC
CC
∆VG
Any GND pin to any other GND pin
0
V
P
Power dissipation, T = 25°C (still air)
800
mW
°C
dBm
°C
V
D
A
T
Maximum operating junction temperature
Maximum power input/output
150
JMAX
P
MAX
+20
T
STG
Storage temperature range
–65 to +150
V
, V
Positive RF peak voltage at Tx outputs
Positive IF peak voltage at Rx mixer outputs
6
6
TXO TXOX
V
, V
V
RXIF RXIFX
NOTE:
1. Maximum junction temperature is determined by the power dissipation is determined by the operating ambient temperature and the thermal
resistance, θ . 48-pin TQFP: θ = 67°C/W.
JA
JA
DC REGULATORS
Table 1. DC Reg Output Voltage Control Pins
Two low drop regulators (REG1 and REG2) are included on the chip
and may be used to deliver the supply voltage of the main circuitry
CON1
CON2
VREG1
3 ± 5%
VREG2
3 ± 5%
UNITS
L
L
L
H
L
V
V
V
V
(e.g., 3V) out of the battery (at V
Figure 4 and in Table 1.
= 3.3 to 7.5V) as shown in
BATT
3.4 ± 5%
3.7 ± 5%
5.1 ± 5%
3.4 ± 5%
3.7 ± 5%
5.1 ± 10%
REG1 is intended to supply, at least, the internal functions of the
SA1620. Both regulators may also be used for external circuitry.
For this application, different voltages may be programmed as
shown in Table 1.
H
H
H
NOTES:
1. Logic levels at CON1 and CON2:
The transmitter supply pins (V Tx1,2) also operate as a sensor
H – Open circuit. Pin must not be connected externally.
Logic high level supplied on chip.
L – Connected to ground.
CC
connection in the feedback loop of REG1 and must be externally
connected to pin VREG1. For REG2, the sensor pin VREGF2 must
be connected to VREG2.
2. Currents at CON1 and CON2:
H – 0µA
All ground pins are internally bonded to the header except for pins
GNDL1, GNDREG1 and GNDREG2.
L (PON = H) – 50µA
L (PON = L) – <1µA
When both regulators are not used, connect pins V
, PON,
BATT
CON1, CON2, VREG1, VREG2 and VREG2F2 to ground.
5
1997 May 22
Philips Semiconductors
Product specification
Low voltage GSM front-end transceiver
SA1620
Table 2. DC Regulators
LIMITS
TYP
TEST
CONDITIONS
SYMBOL
PARAMETER
UNITS
MAX
MIN
V
Common positive input voltage at both regulators
Output voltages of regulators 1 and 2
VREG1+0.3
V
BATT
VREG1,
VREG2
V
BATT
= 3.3V
2.85
3
3.15
V
I
Internal current of REG1 in power-on mode
Internal current of REG2 in power-on mode
Internal current in power-down mode
Max output current at VREG1
4 + I
/10
mA
mA
µA
INT1
INT2
VREG1
I
2.5 + I
/10
VREG2
I
, I
<15
INT01 INT02
5
I
100
30
mA
mA
VREG1MAX
VREG2MAX
5
I
Max output current at VREG2
V
BATT
V
BATT
V
BATT
= 3.3V, I
= 3.3V, I
= 7.5V, I
= 0.1mA
= 100mA
= 100mA
0.03
60
REG1
REG1
REG1
6
BW
kHz
80
≤100kHz
10MHz
≤–61
≤–32
≤–37
≤–48
7
F
REG
f
dB
100MHz
400MHz
NOTES:
1. Power-on pin of Regulator 1 and 2: PON
2. Input currents at PON: <1µA. There are no pull-up or pull-down resistors.
3. Feedthrough attenuation from the logic input PON to the outputs VREG1 and VREG2: ≥40dB.
4. Recommended load capacitors: C529 = C530 = 1µF to ground with series resistance ≤0.1Ω. See Figure 4. Additional optional capacitor
≤1000µF with series resistance ≤5Ω.
5. At T ≥ 150°C a thermal switch reduces the output current.
j
6. Typical open loop bandwidths of regulator 1 at V
= 3V and C529 = 1µF.
REG1
7. Feedthrough attenuation (at the indicated frequency f) from the input V
(CON1=CON2=L)
to the outputs V
and V
at V
= 3.3V,
BATT
BATT
REG1
REG2
6
1997 May 22
Philips Semiconductors
Product specification
Low voltage GSM front-end transceiver
SA1620
DC ELECTRICAL CHARACTERISTICS
V
CCxxx
= +3V, T = 25°C; unless otherwise stated.
A
LIMITS
TYP
SYMBOL
PARAMETER
TEST CONDITIONS
UNITS
MAX
MIN
Transmitter
Transmit mode
I
Total supply current
59
90
mA
VCC
R
= 240Ω
546
1
R1
External resistor
240
0.43
0.45
1.7
Ω
V
V
Tx1,2 = 2.7V
Tx1,2 = 5.5V
CC
V
R1
Internal supply at pin RETx
Current at pin RETx
V
CC
R546 = 240Ω, V Tx1,2 = 2.7V
CC
I
R1
mA
R546 = 240Ω, V Tx1,2 = 5.5V
1.8
CC
Low noise amplifiers
I
I
L1
L2
Current at pin V L1
G1hi mode
G2hi mode
2.5
2.5
3.5
3.5
5
5
mA
mA
VCC
VCC
CC
Current at pin V L2
CC
Receiver
Receive mode
I
Total supply current
28
39
mA
VCC
R
= 240Ω
546
Regulators
Vreg1
Voltage @ 100mA load
Con1
Con2
L
L
L
H
2.85
3.23
3.0
3.4
3.7
5.1
3.15
3.57
V
V
V
V
H
L
3.515
4.61
3.885
5.61
H
H
Vreg2
Voltage @ 30mA load
Con1
L
Con2
L
2.85
3.23
3.0
3.4
3.7
5.1
3.15
3.57
V
V
V
V
L
H
H
L
3.515
4.61
3.885
5.61
H
H
2
Logic levels
3
V
V
Logic 1 level
P
ON
BUF, PDTx, P Rx, A, B
2.0
2.0
0
V
CCBM
V
V
IH
IH
ON
Logic 1 level
P
ON
V
BATT
V
Logic 0 level
0.8
V
IL
I
Input logic current
Input logic capacitance
1
µA
pF
I
C
1.7
Ia
NOTES:
1. The output current I
+ I
is adjustable by the external resistor R546. I
+ I
= 10 * I
, I
= V /R546,
TXO
TXOX
TXO
TXOX
R546 R546 R1
2. Thresholds are independent of supply voltages. Thus the SA1620 is compatible with SA1638 and with the power down inputs of usual
external voltage regulators.
3. P logic 1 max is V
.
ON
BATT
7
1997 May 22
Philips Semiconductors
Product specification
Low voltage GSM front-end transceiver
SA1620
AC ELECTRICAL CHARACTERISTICS
V
CCXX
= +3V, T = 25°C; RF = 940MHZ; IF=400MHz, f =RF + IF; LO = –15dBm; unless otherwise stated.
A LO
1
LIMITS
TYP
SYMBOL
PARAMETER
TEST CONDITIONS
UNITS
1
1
MIN
-3σ
9.4
–13
3σ
MAX
2
Low Noise Amplifier LNA1
G1hi mode
G1hi mode, RF = 1800MHz
G1lo mode
10
–2.5
–12
28
10.6
–11
Gain
S
21
dB
IP3
G1lo mode
G1hi mode
0.003
∆S /∆T
Gain temperature sensitivity
dB/°C
21
G1lo mode
0.0140
∆S
/
21
Gain/voltage sensitivity
0.1
dB/V
∆V
CCL1
∆S /∆f
Gain frequency variation
Reverse isolation
0.01
–19
–11
–14
–14
–4
dB/MHz
dB
21
S
12
G1hi mode
50Ω
3
S
Input match
dB
11
22
3
S
Output match
50Ω
dB
P
-1dB
Input 1dB gain compression
Input third order intercept
Input third order intercept
Noise figure
G1hi mode
–15.5
–5.5
–12.5
–2.5
dBm
dBm
dB/°C
dB
IIP3
IIP3/∆t
NF
0.011
1.9
t
Turn-on time
7
µs
ON
t
Turn-off time
0.5
µs
OFF
2
Low Noise Amplifier LNA2
G2hi mode
G2hi mode, RF = 1800MHz
G2lo1 mode
9
10
–1.5
–7.5
–21.5
–28.5
18
11
dB
dB
Gain
–8.5
–22.5
–30
–6.5
–20.5
–27
G2lo2 mode
S
21
G2lo3 mode
dB
G2lo1 mode
IP3
G2lo2 mode
20
G2lo3 mode
25
G2hi mode
0.003
0.014
∆S /∆T
Gain temperature sensitivity
Gain/voltage sensitivity
dB/°C
21
G2lo1,2,3 modes
∆S
/
21
0.1
dB/V
∆V
CCL2
∆S /∆f
Gain frequency variation
Reverse isolation
0.01
–24
–13
–15
–16
–6
dB/MHz
dB
21
S
12
G2hi mode
50Ω
3
S
Input match
dB
11
22
3
S
Output match
50Ω
dB
P
-1dB
Input 1dB gain compression
Input third order intercept
Input third order intercept
Noise figure
G2hi mode
–18
–8
–14
–4
dBm
dBm
dB/°C
dB
IIP3
IIP3/∆t
NF
0.019
2
t
Turn-on time
7
µs
ON
t
Turn-off time
0.5
µs
OFF
8
1997 May 22
Philips Semiconductors
Product specification
Low voltage GSM front-end transceiver
SA1620
AC ELECTRICAL CHARACTERISTICS (continued)
1
LIMITS
TYP
SYMBOL
Rx Mixer
PARAMETER
TEST CONDITIONS
UNITS
1
1
MIN
-3σ
3σ
MAX
7.5
+8.5
–4
9.5
5
PG
Power conversion gain
dB
dB
C
RF = 1800MHz
Mixer input match at ports INM
S
11
–13
4
and INMX
NF
SSB combined noise figure
Input 1dB compression
Input third order intercept
Input third order intercept
Input second order intercept
RF feedthrough
10
–7.3
2
dB
dBm
dBm
dB/°C
dBm
dB
M
P
-1dB
IIP3
IIP3/∆t
IIP2
0
4
0.005
19
G
400MHz
400MHz
1.3GHz
1.3GHz
–26
–30
–16
–50
RFM-IF
G
LO floor feedthrough
dB
LOfloor
G
LO feedthrough to IF
dB
LO-IF
G
LO to mixer input feedthrough
dBm
LO-RFM
LO to RF LNA1 input
feedthrough
G
1.3GHz
–65
dBm
dB
LO-RF1
LNA1 output to LNA2 input
feedthrough
400MHz
1290-1760MHz
–41
–26
G
LNA1-2
LNA2-M
LNA1-M
LNA2 output to mixer input
feedthrough
G
G
1290-1760MHz
–23
dB
LNA1 output to mixer input
feedthrough
400MHz
1290-1760MHz
–50
–35
dB
6
Receiver
Cascaded gain
A,B Logic Level
H,H
H,L
L,H
L,L
23.5
6
26.5
9
28.5
11
30.5
13
33.5
16
dB
dB
–8
–5
–3
–1
+2
dB
–41
–36
–20
–32
–18
+28
–16
–23
dB
Input IP3 @ RFin=–40dBm
H,H
dBm
LO input
Input impedance
(each single-ended input)
Z
P
1.3GHz
400MHz
35-j97
–15
Ω
IN
IN
7
Input power
–25
dBm
mV
Transistor saturation limit,
max input amplitude
A
SAT
500
Tx IF input
|Z
P
|
Input impedance
Input power
2
kΩ
IN
–20
dBm
IN
Tx RF output
R546 = 240Ω,
P
OUT
5
7.5
8.5
9.5
dBm
V
CC
Tx1,2 = 3V
NOTES:
1. Due to our automatic test equipment accuracy and repeatability test limits may not reflect the ultimate device performance. Standard
deviations are calculated from characterization data.
2. If the LNA1 is not needed, connect pin V L1 and IN1 to GND. If the LNA2 is not needed, connect pin V L2 and IN2 to GND.
CC
CC
3. Simple L/C elements are needed to achieve specified return loss.
4. The mixer RF inputs (emitters of a Gilbert Cell) may be driven by a symmetrical matching network.
5. Input symmetry suppression is such that the product 6*RF–4*LO is to be suppressed by at least 66dB relative to the wanted IF output when
the input to the mixer is at –32dBm.
6. LNA1, LNA2, and the mixer are cascaded. 0 db insertion loss between LNA1 out to LNA2 in and LNA2 out to mixer in.
7. Lowering the LO input power (P ) from TYP to MIN will lower the mixer gain (PG ) by 1 dB.
IN
C
9
1997 May 22
Philips Semiconductors
Product specification
Low voltage GSM front-end transceiver
SA1620
Table 3. Power-Down and Tx/Rx Control Logic
No. PONBUF
PDTX
PONRX
MODE
Standby
RESULT
LO buffer active, Tx and Rx path inactive
1
2
3
4
H
H
H
H
L
H
L
H
L
x
L
L
Transmit
Receive
LO buffer active, Tx path active, Rx path inactive (LNAs + mixer)
Tx path inactive, LO buffer and Rx path active (LNAs + mixer)
Tx path and Rx LNAs inactive, LO buffer and Rx mixer active
Tx- and Rx-path, LO buffers and Bias inactive
H
H
x
Calibrate
Power-Down
5
NOTES:
1. Logic levels of PONBUF, PDTx and PONRx: TTL, see DC Electrical Characteristics.
2. Logic levels / polarities are compatible with Philips Semiconductors Power Amp Controller PCA5075 and synthesizers UMA1019 or SA8025.
3. First stage of LO buffer and parts of bias supply are powered on by PONBUF.
4. Tx- or Rx-paths may be activated for special timeslots. Lines 1 and 4 show options to support DC offset calibrations at baseband mixers,
following in the receiver chain (SA1638).
Table 4. Gain Control Logic for LNA1 and LNA2
INPUT
GAIN
POWER CONSUMPTION
ATTENUATION
STEP
a
b
H
L
LNA1
G1hi
G1hi
G1hi
G1lo
LNA2
G2hi
LNA1
on
LNA2
on
H
H
L
0
1
2
3
G2lo1
G2lo2
G2lo3
on
off
H
L
on
off
L
off
off
NOTES:
1. Logic levels of a and b: TTL
2. For values of G1hi and G1lo, G2hi, G2lo1, G2lo2 and G2lo3 see LNA1 and LNA2 AC Electrical Characteristics.
10
1997 May 22
Philips Semiconductors
Product specification
Low voltage GSM front-end transceiver
SA1620
SR00130
Figure 3.
11
1997 May 22
Philips Semiconductors
Product specification
Low voltage GSM front-end transceiver
SA1620
Overview of Dual GSM/PCN Architecture
The SA1620 RF front-end and SA1638 IF transceivers form a dual
conversion architecture which uses a common IF and standard I/Q
baseband interface for both transmit and receive paths. This
approach avoids the screening difficulties of direct modulation in the
transmit direction and the mass production and practical
performance issues related to direct conversion in the receive
direction. The time division multiplex nature of the GSM system
permits integration of the transmit and receive functions together on
the one RF and one IF chips. This simplifies the distribution of local
oscillator signals, maximizes circuitry commonality, and reduces
power consumption.
Receive Path
Multiple LNAs allow the flexibility to exploit the best choice of
currently available filters (on performance, size, or cost grounds).
This approach is preferable to a single high-gain stage as the stray
cross-coupling effects between pins remain manageable. In a single
stage amplifier this would limit the amount of rejection of out-of-band
signals that could be achieved, and would also limit the amount of
AGC attenuation that could be practically implemented.
The LNAs are powered up only when PONBUF, PDTx and PONRx
are high, to allow a high degree of battery economy. If greater
sensitivity is required for an application, an external preamplifier
circuit can be used instead of LNA1, and LNA1 left unconnected.
The SA1620 and SA1638 allow considerable flexibility to optimize
the transceiver design for particular price/size/performance
requirements, through choice of appropriate RF and IF filters. The
receive IF may be chosen freely in the range 70–500MHz, while the
transmit IF is fixed to 400 MHz. The comparison frequency of the
SA1638 PLL is high in order to provide fast switching time.
A special mode is provided with just the IF output related circuitry
active in order to allow calibration of the DC offset at the SA1638
baseband receive outputs. This offset contains a contribution due to
coupling effects between the second local oscillator and the IF
circuitry, and therefore the receiver is set up in the receive state (but
with incoming signals excluded) to allow accurate offset calibration.
With suitable choice of the IF, an identical SA1638 IF receiver
design can be used for both 900MHz GSM and 1800MHz PCN
(DCS1800) equipment.
Gain Control
Gain control is implemented in the SA1620 RF front-end. This
avoids the disruption of the DC offset at the baseband IQ outputs
that is typically caused by changes in the AGC. The SA1620 and
SA1638 are designed so that the GSM dynamic range requirements
can be met with the AGC remaining on the maximum gain setting.
General Benefits/Advantages
• 2.7V operation. Compatible with 3V digital technology and
portable applications. (Higher voltage operation also possible, if
desired.)
These gain steps scale the dynamic range of the received signal
(e.g., 90dB for GSM) into the dynamic range of the baseband
processing device.
• Excellent dynamic range. The availability of two LNAs allows
flexibility in receiver dynamic design for portable and mobile GSM
spec. applications with appropriate filters. If for a particular
application a GaAs or discrete front-end is desired, one of the
LNAs can be left unpowered. The placing of the AGC gains
switches at the front means that for most of the time some
attenuation will be inserted, further increasing typical dynamic
performance beyond that specified by GSM.
The absolute gain tolerances may be measured together with the
attenuation tolerances of external filters during production of the
receiver equipment. After software calibration switching from one
dynamic range to another will cause only minor errors.
Tx Path
TXIF and TXIFX are differential IF inputs for phase modulated
signals (e.g., GMSK). There is an IF level control loop which
provides a constant amplitude to an image reject up mixer. Thus,
this mixer operates linearly in the IF path, independent of IF level
tolerances.
• High power transmit output driver, delivering +8.5dBm output.
This is sufficient to drive a filter and power amplifier input, without
a driver amplifier. To avoid unnecessary current consumption the
output power can be reduced, if not required, by appropriate
choice of an external resistor.
The single sideband up mixer is sufficient in quadrature to achieve
the typical performance indicated in Table 6 over an IF range of 250
to 500MHz. The mixer is operating in switching mode by well
matched 0° and 90° LO signals, optimized for 1.1 to 1.5GHz.
• DC offsets generated in the receive channel are independent of
the AGC setting, and correctable by software to prevent erosion of
signal handling dynamic range by DC offsets. Independence of
DC from AGC setting is achieved by putting the gain switches in
the RF front-end.
The Tx output stage operates in switching mode. Thus, parasitic
AM at the IF is not transferred. The outputs TXO and TXOX may be
used symmetrically or single-ended. Some spurious emissions will
be very low when a symmetrical output signal is used.
• Minimal high-quality filter requirements. As a result of the
integration in the SA1638 of high quality channel selectivity filters,
only sufficient filtering is needed in the receive path to provide
blocking protection for the second mixers. This reduces receiver
cost and size.
2
ƪ
ƫ
P
OUT
= Re 6.25V @ (ZPin 40 ) ZPin 41) @ (IR546
)
V
• Operation at a high IF allows RF image reject filters to be relaxed.
For example, at a 400MHz IF, the natural gain roll-off in the LNAs
and mixer suppresses the image signal in the 1800MHz band by
typically 28dB below the desired 900MHz band signal.
R546 according to DC Electrical
I
+
according to Figure 4 and
R546
R546
Characteristics. P
is adjustable with R546 and is accurate to
within ±1dB over the full voltage range 2.7 to 5.5V, and ±0.5dB from
OUT
a given supply voltage. The absolute limit of the negative peak
voltage swing at pins TxO and TxOX is V
= V Tx1,2 – 1V. The
CC
SAT
absolute limit of the positive peak voltage is +6V.
12
1997 May 22
Philips Semiconductors
Product specification
Low voltage GSM front-end transceiver
SA1620
V c c / G n d
P O N B U F
V c c T x 2
G N D T x 1
V c c T x 1
P D T x
V c c / G n d
G N D T x 4
3 3 5
G D N 3
T x I F X
T x O X
6 9 0
3 3 5
T x O
3 5 0
3 5 0
G N D T x 3
T x I F
R E T x
I N 1
G N D 2
9 4 0
R x I F X
R x I F
3 5 0
3 5 0
G N D L 1
G N D L 1 A
G N D 1
6 0 5
P O N R x
G N D B M
O U T 1
V c c L 1
V c c / G n d
1 8 0
4 2 0
SR01332
Figure 4. Application Circuit
13
1997 May 22
Philips Semiconductors
Product specification
Low voltage GSM front-end transceiver
SA1620
recommended to be the receiver band plus 400MHz. Additionally,
the LO leakage at the input of LNA1 is extremely low, which can
greatly alleviate the LO re–radiation problem.
APPLICATION CIRCUIT
LNA
Impedance Match: Intrinsic return losses at the input and output
ports are 7dB and 11dB, respectively. However, since long and
narrow traces are always needed to fan out the pins, the user can
adjust the traces’ dimensions so that only one shunt capacitor at the
input is required to achieve excellent impedance match for both
ports. If the user wants to skip the input matching network for
simplicity, then roughly 0.7dB gain would be lost, although it benefits
the system IP3.
Outband Blocking: For optimum performance, passive R/C network
is added at each input of the mixer. The resistors degenerate the
noise conversion gain, while the capacitors preserve the gain and
noise figure at RF frequencies.
Noise Figure and IP3: The resonant balun is superior to the
conventional balun in terms of insertion loss, size and cost. As a
result, the user can expect excellent SSB noise figure and gain
which is 10dB and 8.5dB, respectively, at 400MHz IF. And the
associated input IP3 is 2dBm typically. In the meantime, due to the
internal LO buffer, the noise figure and IP3 are not sensitive to the
LO levels. As discussed in the LNA Impedance Match session, a
better system IP3 can be achieved (if necessary) through LNAs’
gain reduction.
Noise Match: The LNA1 and LNA2 can achieve 1.9dB and 2.0dB
noise figure, respectively, when S11 = –11dB. Further improvement
in S will slightly decrease NF and increase S
.
11
21
Gain Control: The LNA1 can be switched to the attenuation mode,
while LNA2 has three attenuation modes to choose from. When
gain and loss modes from two LNAs are combined, there will be a
total dynamic range of 59dB in the RF block; 3.0V operation is
preferred to achieve better IP3 for both LNA1 and LNA2.
Transmitter
The resonant balun is applied again to maximize the gain and output
power, for a given bias current. Typical output power is 8.5dBm
when the input level exceeds –25dBm.
Temperature Compensation: Both LNAs have a built–in temperature
compensation scheme to reduce the gain drift rate to 0.003dB/°C
from –40°C to +85°C.
LO Input
The LO input is used in Tx- and in Rx-mode.
Supply Voltage Compensation: Unique circuitry provides gain
stabilization over wide supply voltage range. The gain changes no
Only one synthesizer PLL is necessary to supply the LO input with
different frequencies in Tx and Rx timeslots.
more than 0.5dB when V increases from 2.7V to 5.5V.
CC
The LO input buffer should only be set in power-down mode
together with the PLL. As further buffering is included on chip there
will be no influence on the PLL in active mode when the SA1620 Rx-
or Tx-path is power On or Off. Current consumption can thus be
saved by powering on the Rx- and Tx-circuitry just before it is
required, without disruption of the LO circuitry. LO input pins LO IN
and LO INX may be used single-ended or symmetrically.
Mixer
Mixer Input Match: The mixer is configured for best gain, noise
figure and spurious response. The user must supply an external,
patented resonant balun to provide the differential drive as well as
the impedance match (embedded in). Because the mixer consists
of two single–balance mixers, whose inputs are connected in
parallel instead of in series, the differential and common–mode
impedances are equal.
Table 5. GSM/DSC1800 Frequency Specification
(GSM 05.05, Version 4.2.0, April 1992) Mobile Stations Frequency
Bands
Output Match: The mixer output circuit also features an external,
patented resonant balun to optimize the conversion gain and noise
figure. The principal IF operating frequency is 400 MHz.
GSM
EGSM
DCS1800
1710 to 1785
1805 to 1880
Unit
MHz
MHz
LO Drive: The internal buffer only requires –15dBm from an external
source. Furthermore, the transmitter incorporates an integrated
SSB upconverter that consists of narrowband phase shifters at
1300MHz (LO side) and 400MHz (IF side), so the LO frequency is
Tx
Rx
890 to 915
935 to 960
880.2 to 915
925.2 to 960
14
1997 May 22
Philips Semiconductors
Product specification
Low voltage GSM front-end transceiver
SA1620
Table 6. Measured Tx Output Frequency and Tx Mixer Products
IF=400MHz, symmetrical load at pins TxO, TxOX.
SPECTRAL LINE f=n*IF+m*LO MHz
RELATIVE POWER OF SPECTRAL
LINE
No.
REMARKS
Order
LO =
LO =
LO =
1280MHz
1300MHz
1315MHz
n
–3
–6
4
m
1
min dBc
typ dBc
–70
–76
–60
–46
–31
–62
–56
–37
0
max dBc
1
80
100
200
115
230
2
160
2
3
320
300
285
–1
0
4
400
400
400
1
IF
5
480
500
515
–2
–5
5
1
6
560
600
630
2
7
720
700
685
–1
0
8
800
800
800
2
Note 2
Note 1
Note 3
9
880
900
915
–1
–4
6
1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
960
1000
1100
1200
1300
1400
1500
1600
1700
1800
1900
2000
2100
2200
2300
2400
2500
2600
1030
1185
1200
1315
1430
1545
1600
1715
1830
1945
2000
2115
2230
2345
2400
2515
2630
2
–46
–63
–60
–32
–46
–64
–75
–50
–34
–68
–77
–74
–67
–59
–75
–76
–70
1020
1200
1280
1360
1440
1600
1680
1760
1840
2000
2080
2160
2240
2400
2480
2560
–1
0
3
0
1
LO
–3
–6
4
2
3
0
1
1
Notes 4 and 5
Note 3
–2
–5
5
2
3
Note 3
0
2
1
–1
–4
6
2
3
0
3
1
26
0
2
2LO
NOTES:
1. Desired Tx output frequency LO–IF corresponding to EGSM Tx band in Table 5.
2. (LO+IF)–(LO–IF) = 2 * IF
3. See Rx bands in Table 5.
4. LO+IF = mixer image frequency
5. See Tx bands in Table 5.
15
1997 May 22
Philips Semiconductors
Product specification
Low voltage GSM front-end transceiver
SA1620
Table 7. Measured Tx Output Noise Floor
dBc/Hz
TYP
Frequency MHz
MIN
REMARKS
MAX
< 860
860 to 880
–135
–134
–133
–133
–133
–134
–135
–135
–135
–146
–145
–144
–147
–130
880.2 to 890
890 to 915
EGSM TX extension
GSM TX
915 to 925
925.2 to 935
935 to 960
EGSM RX extension
GSM RX
960 to 1000
1000 to 1710
1710 to 1785
1785 to 1805
1805 to 1880
1880 to 12750
Adjacent Channel
DCS1800 TX
DCS1800 RX
16
1997 May 22
Philips Semiconductors
Product specification
Low voltage GSM front-end transceiver
SA1620
40
35
30
25
20
15
5
4.5
4
3V
3V
4V
3.5
4V
5V
5V
3
2.5
2
-40°
25°
85°
-40°
25°
85°
Temp (°C)
Temp (°C)
SR01334
SR01333
Figure 8. Receive ICC vs. Temp
Figure 5. LNA1_ICC vs. Temp
5
4.5
4
10
9
5V
8
3V
4V
3.5
3
4V
7
5V
3V
6
2.5
2
5
4
-40°
25°
85°
-40°
25°
Temp (°C)
85°
Temp (°C)
SR01338
SR01339
Figure 9. Standby_ICC vs. Temp
Figure 6. LNA_2 ICC vs. Temp
28
26
24
22
20
18
16
14
12
10
70
65
60
55
50
45
40
5V
3V
4V
4V
3V
5V
-40°
25°
Temp (°C)
85°
-40°
25°
85°
Temp (°C)
SR01337
SR01344
Figure 10. Calibrate_ICC vs. Temp
Figure 7. Transmit_ICC vs. Temp
17
1997 May 22
Philips Semiconductors
Product specification
Low voltage GSM front-end transceiver
SA1620
-20
-22
-24
-26
-28
-30
-32
-34
-36
34
32
30
3V
28
4V
3V
26
5V
24
22
20
4V
5V
-40°
25°
Temp (°C)
85°
-40°
25°
Temp (°C)
85°
SR01342
SR01336
Figure 11. Receive_Gain Mode1 vs. Temp
Figure 14. Receive_Gain_Mode4 vs. Temp
15
13
11
9
-15
-16
-17
-18
-19
-20
-21
-22
-23
-24
-25
3V
4V
5V
4V
5V
3V
7
5
-40°
25°
85°
-40°
25°
85°
Temp (°C)
Temp (°C)
SR01335
SR01343
Figure 12. Receive_Gain_Mode2 vs. Temp
Figure 15. Receive IIP3 vs. Temp
0
-1
-2
-3
-4
-5
-6
5V
4V
3V
-40°
25°
85°
Temp (°C)
SR01341
Figure 13. Receive_Gain_Mode3 vs. Temp
18
1997 May 22
Philips Semiconductors
Product specification
Low voltage GSM front-end transceiver
SA1620
2.0
10.80
10.40
10.00
9.60
3.0V
3.0V
1.9
5.0V
2.7V
2.7V
5.5V
1.8
1.7
1.6
5.0V
5.5V
9.20
–40
0
25
85
–40
0
25
85
TEMPERATURE (°C)
TEMPERATURE (°C)
SR00140
SR00134
Figure 16. Receive LNA1 Noise Figure
Figure 18. Receive Mixer Noise Figure
10.00
9.00
8.00
7.00
6.00
2.50
2.30
2.10
1.90
1.70
1.50
5.5V
5.0V
5.5V
3.0V
3.0V
2.7V
5.0V
2.7V
–40
0
25
85
SR00137
–40
0
25
85
TEMPERATURE (°C)
TEMPERATURE (°C)
SR00149
Figure 17. Receive LNA2 Noise Figure
Figure 19. Transmit Power @ -25dBm
12
11
10
9
5V
4V
3V
8
7
6
5
4
-40°
25°
85°
Temp (°C)
SR01345
Figure 20. Transmit_Power @ –20 dBm Input
19
1997 May 22
Philips Semiconductors
Product specification
Low voltage GSM front-end transceiver
SA1620
3.02
3.01
3.00
2.99
2.98
2.97
9.50
9.00
–40
0
5.5V
5.0V
8.50
8.00
7.50
7.00
2.7V
25
3.0V
85
–40
0
25
85
SR00150
0
3
6
9
12
15
18
21
24
27
30
TEMPERATURE (°C)
FORCED CURRENT (mA)
SR00153
Figure 21. Transmit Power @ -15dBm
Figure 24. Regulator 2 Load Regulation (V
= 3.5V)
BATT
3.01
3.00
–40
9.00
8.50
8.00
7.50
5.5V
2.99
2.98
3.0V
0
25
5.0V
2.97
2.7V
85
2.96
2.95
2.94
2.93
7.00
–25.00
–20.00
–15.00
3.3
3.5
4.5
5.5
6.5
7.5
SR00154
INPUT POWER (dBm)
FORCED CURRENT (mA)
SR00151
Figure 22. Transmit Power @ 25°C
Figure 25. Regulator 1 Line Regulation @ 100mA Load
3.01
–40
–40
3.00
0
0
25
2.99
25
2.98
85
2.98
85
2.97
2.93
2.96
3.3
0
10
20
30
40
50
60
70
80
90
100
3.5
4.5
5.5
6.5
7.5
FORCED CURRENT (mA)
FORCED CURRENT (mA)
SR00155
SR00152
Figure 23. Regulator 1 Load Regulation (V
= 3.5V)
Figure 26. Regulator 2 Line Regulation @ 30mA Load
BATT
20
1997 May 22
Philips Semiconductors
Product specification
Low voltage GSM front-end transceiver
SA1620
100
90
80
70
60
50
40
30
20
12
10
V
= 3V
CC
V
= 3V
CC
Temp = 25°C
8
6
Temp = 25°C
4
2
0
-2
-4
R546 (Ω)
R546 (Ω)
SR00156
SR00157
Figure 27. Transmit Output Power vs R(546) @ V = 3V
Figure 28. Transmit Mode Current vs R(546) @ V = 3V
CC
CC
21
1997 May 22
Philips Semiconductors
Product specification
Low voltage GSM front-end transceiver
SA1620
PIN FUNCTIONS
PIN
PIN
PIN
PIN
DC V
EQUIVALENT CIRCUIT
DC V
EQUIVALENT CIRCUIT
No. MNEMONIC
No. MNEMONIC
1
12
1
2
V
3.0
12
13
V
BM
3.0
CC
CC
GND
0.0
2
IN2
0.8
POnRx
CMOS
INPUT
—
+
14
14
3
4
GNDL2
0.0
0.0
GNDL2a
15
16
GND
Rxif
0.0
3.0
16
17
5
5
6
OUT2
2.2
17
18
19
RxifX
GND
Txif
3.0
0.0
2.2
B
—
+
6
CMOS
INPUT
19
20
A
—
+
20
TxifX
GND
2.2
7
7
CMOS
INPUT
21
22
0.0
3.0
22
V
CC
Tx
8
8
9
INM
0.4
0.4
23
24
GND
0.0
3.0
24
V
CC
Tx
9
INMX
25
26
GND
0.0
10
11
COMP2
COMP1
2.2
2.2
CON2
CMOS
INPUT
—
+
10 or 11
26
SR00162
Figure 29. Pin Functions
22
1997 May 22
Philips Semiconductors
Product specification
Low voltage GSM front-end transceiver
SA1620
PIN FUNCTIONS (continued)
PIN
PIN
PIN
PIN
DC V
EQUIVALENT CIRCUIT
DC V
EQUIVALENT CIRCUIT
No. MNEMONIC
No. MNEMONIC
—
+
POnBuf
27
28
LOin
2.2
37
37
38
CMOS
INPUT
27
28
LOinX
2.2
PDTx
CMOS
INPUT
—
+
38
CON1
CMOS
INPUT
—
29
29
+
39
40
GndTx
TxOx
0.0
3.0
40
41
30
31
GndReg1
VReg2
0.0
3.0
V
BATT
—
41
42
TxO
3.0
0.0
+
31
GndTx
GndReg2
32
V
BATT
43
RETx
0.4
43
+
–
—
+
32
VRegF2
3.0
GndReg2
44
44
IN1
0.8
V
BATT
—
+
33
VReg1
3.0
0.0
33
GndReg1
45
45
46
GndL1
GndTx
0.0
0.0
34
35
GndReg1
POn
—
+
35
CMOS
INPUT
47
47
48
OUT1
2.2
3.0
36
48
—
+
V
CC
L1
36
V
BATT
3.0
SR00163
Figure 29. Pin Functions (continued)
23
1997 May 22
Philips Semiconductors
Product specification
Low voltage GSM front-end transceiver
SA1620
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
SOT313-2
24
1997 May 22
Philips Semiconductors
Product specification
Low voltage GSM front-end transceiver
SA1620
NOTES
25
1997 May 22
Philips Semiconductors
Product specification
Low voltage GSM front-end transceiver
SA1620
DEFINITIONS
Data Sheet Identification
Product Status
Definition
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
Objective Specification
Formative or in Design
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Preliminary Specification
Product Specification
Preproduction Product
Full Production
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. PhilipsSemiconductorsmakesnorepresentationorwarrantythatsuchapplicationswillbesuitableforthespecifiedusewithoutfurthertesting
or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
orsystemswheremalfunctionofaPhilipsSemiconductorsandPhilipsElectronicsNorthAmericaCorporationProductcanreasonablybeexpected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1997
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Philips
Semiconductors
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