SA5753DK [NXP]
Audio processor - filter and control section; 音频处理器 - 过滤器和控制单元
| 型号： | SA5753DK |
| 厂家： | 
NXP |
| 描述： | Audio processor - filter and control section |
| 文件： | 总15页 (文件大小：105K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
SA5753
Audio processor — filter and control
section
Product specification
Replaces data of 1995 July 7
1997 Nov 07
IC17 Data Handbook
Philips
Semiconductors
Philips Semiconductors
Product specification
Audio processor – filter and control section
SA5753
DESCRIPTION
PIN CONFIGURATION
The SA5753 is a high performance low power CMOS audio signal
processing system especially designed to meet the requirements for
small size and low voltage operation of hand-held equipment. The
SA5753 subsystem includes complementary transmit/receive voice
band (300-3000Hz), switched capacitor bandpass filters with
pre-emphasis and de-emphasis respectively, a transmit low pass
filter, peak deviation limiter for transmit, digitally controlled
attenuators for signal level and volume control, audio path mute
switches, a programmable DTMF generator, power-down circuitry
DK Package
1
2
20
19
18
17
16
15
14
13
TXBF
TX
IN
OUT
TXBF
DATA
IN
OUT
3
PREMP
V
TX MUTE
IN
4
SDA
DD
5
VOX
SCL
CTL
2
6
GND
HPDN
SA5753
for low current standby, power-on reset capability, and an I C
interface. When the SA5753 is used with an SA5752 (companding
function), the complete audio processing system of an AMPS,
TACS, NAMPS or NTACS cellular telephone is easily implemented.
7
DEMP
CLK
IN
OUT
8
AUDIO
DFT
IN
9
SPKR
EAR
RX MUTE
12
11
OUT
The system also meets the requirements of the proposed NAMPS or
NTACS specification, and can be used in cordless telephone
applications.
10
RX DEMOD
IN
OUT
SR00666
2
The SA5753 can be operated without the I C bus interface by
pulling DFT (Pin 13) HIGH.
Figure 1. Pin Configuration
FEATURES
• Low 3V supply
BENEFITS
• Very compact application
• Miniature SSOP package
• Low power
• Long battery life in portable equipment
• Complete cellular audio function with the SA5752
• High performance
APPLICATIONS
• Built-in programmable DTMF generator
• Cellular radio
• Built-in digitally controlled attenuators for modulation and volume
control
• Mobile communications
• High performance cordless telephones
• 2-way radio
• Built-in peak-deviation limiter
2
• I C Bus controlled
• Power-on reset
• Power down capability
• Programmable mute control
• Meets AMPS/TACS/NAMPS/NTACS requirements
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
ORDER CODE
DWG #
20-Pin Plastic Shrink Small Outline Package (SSOP)
-40 to +85°C
SA5753DK
SOT266-1
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
-0.3 to 6
UNIT
V
V
V
Power supply voltage range
Voltage applied to any other pin
Storage temperature
DD
IN
-0.3 to V +0.3
V
DD
o
-65 to +150
-40 to +85
C
°C
T
A
Ambient operating temperature
2
1997 Nov 07
853-1722 18666
Philips Semiconductors
Product specification
Audio processor – filter and control section
SA5753
PIN DESCRIPTIONS
PIN NO.
SYMBOL
DESCRIPTION
1
TXBF
Transmit bandpass filter input
Transmit bandpass filter output
Pre-emphasis input
IN
2
3
TXBF
OUT
PREMP
IN
4
V
DD
Positive supply
5
VOX
Vox control output
CTL
6
HPDN
DEMP
Power-down I/O
7
De-emphasis output
Audio input
OUT
8
AUDIO
IN
OUT
OUT
9
SPKR
Audio output to speaker
Audio output to earpiece
Rx demodulated audio signal input
10
11
12
13
14
15
16
17
18
19
20
EAR
RX DEMOD
RX MUTE
DFT
IN
RX audio signal mute input
2
Default input, non-I C or stand-alone operation
CLK
Clock input (1.2MHz)
IN
GND
SCL
Ground
2
I C serial clock line
2
SDA
I C serial data line
TX MUTE
Tx audio signal mute input
Data input
DATA
IN
TX
Transmit output
OUT
3
1997 Nov 07
Philips Semiconductors
Product specification
Audio processor – filter and control section
SA5753
DC ELECTRICAL CHARACTERISTICS
o
T = 25 C, V = +3.3V, unless otherwise specified. See test circuit, Figure 2.
A
DD
LIMITS
TYP
SYMBOL
PARAMETER
Power supply voltage
TEST CONDITIONS
UNIT
MIN
MAX
V
DD
3.0
3.3
5.5
V
Operating
IDLE
Power Down (PWDN)
1.7
600
200
mA
µA
µA
I
Supply current
DD
Input current high
TX MUTE, RX MUTE, HPDN
DFT
V = V
IN DD
–10
0
0
+10
+10
+30
µA
µA
I
IH
Input current low
TX MUTE, RX MUTE,
HPDN, DFT
V
IN
= GND
–30
–10
–10
0
0
+10
µA
µA
I
IL
V
Input voltage high
Input voltage low
0.7V
V
DD
V
V
IH
DD
V
0
0.3V
DD
IL
AC ELECTRICAL CHARACTERISTICS
o
T = 25 C, V = +3.3V. See test circuit, Figure 2. Clock frequency = 1.2MHz; test level = 0dBV = 77.5mV = -20dBm, unless otherwise
A
DD
RMS
specified. All gain control blocks (Attenuators) = 0dB gain, NAMPS and VCO bits set to 0.
LIMITS
TYP
40
SYMBOL
PARAMETER
RX BPF anti alias rejection
TEST CONDITIONS
UNIT
MIN
MAX
dB
RX BPF input impedance
f= 1kHz
f = 1kHz
100
0
kΩ
RX BPF gain with de-emphasis
RX BPF gain with de-emphasis
RX BPF gain with de-emphasis
RX BPF gain with de-emphasis
RX BPF gain with de-emphasis
RX BPF noise with de-emphasis
RX dynamic range
-1.0
1.0
dB
f = 100Hz
-30
dBm0
dBm0
dBm0
dBm0
f = 300Hz
8.5
9.6
11.5
-8.5
f = 3kHz
-11.5
-10.0
-58
f = 5.9kHz
300Hz-3kHz
with deemphasis
f = 1kHz
200
80
µV
RMS
dB
DEMP
DEMP
output impedance
output swing (1%)
ouput swing (1%)
40
Ω
OUT
OUT
OUT
2kΩ to V
; f = 1kHz
2.4
2.4
2.4
200
V
DD/2
P-P
P-P
P-P
SPKR
EAR
50kΩ toV
; f = 1kHz
V
DD
-1
V
V
DD/2
output swing (1%)
50kΩ to V
f = 1kHz
DD/2;
V
-1
OUT
DD
SPKR
noise / EAR
noise
µV
RMS
OUT
OUT
CLK high
2.1
0
3.0
1.0
V
IN
CLK low
V
IN
TX BPF anti alias rejection
TX BPF input impedance
TX BPF noise
f > 50kHz
f = 3kHz
40
100
200
-39
dB
KΩ
300 - 3000kHz
f = 5.9kHz
f = 1kHz, 0dBV
f = 100Hz
f = 300Hz
f = 3kHz
µV
RMS
TX LPF gain
-36
dBm0
dB
TX LPF gain with pre-emphasis
TX LPF gain with pre-emphasis
TX LPF gain with pre-emphasis
TX LPF gain with pre-emphasis
TX LPF gain with pre-emphasis
TX LPF gain with pre-emphasis
TX overall gain
2.43
-19
dBm0
dBm0
dBm0
dBm0
dBm0
dB
-10.45
9.14
-28
f = 5900Hz
f = 9kHz
-48
1kHz
2.43
-58
TX overall gain
100Hz
-44
dBm0
dBm0
TX overall gain
300Hz
-11.5
-10.4
-8.5
4
1997 Nov 07
Philips Semiconductors
Product specification
Audio processor – filter and control section
SA5753
AC ELECTRICAL CHARACTERISTICS (continued)
LIMITS
TYP
9
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
MAX
MIN
TX overall gain
TX overall gain
3kHz
8
9.6
-45
dBm0
dBm0
dB
5.9kHz
-52
TX BPF dynamic range
PREMP input impedance
TBD
100
0.75
f = 3kHz
kΩ
IN
TX
Slew rate
C = 15pF
L
V/µs
Ω
OUT
Output impedance
Output swing (limiting)
Output swing (1% THD)
f = 3kHz
40
1.2
1.0
V
P-P
P-P
V
5kΩ load (25°C)
Tx DTMF signal with TXLPF and pre-emphasis
Rx DTMF sidetone
0.45
V/kHz
dBm0
–0.8
5.2
Time delay to mute from RX MUTE or TX MUTE
transition
V
IN
V
IN
= V to V
IH
0.5
0.5
µs
µs
IL
= V to V
IH
IL
Table 1. Gain Control Blocks (Bit 0 is Least Significant Bit)
TYPICAL GAIN (dB)
MIN
SYMBOL
Bits
TYPICAL STEP (dB)
MAX
0
A1
A2a
A2b
A3
4
5
2
4
4
4
4
–0.8
±0.25
–12.0
–3.75
–24.0
–17.0
–3.5
+3.75
0
–6, (–12 on first)
–1.0
–2.0
+3.5
0
A4
±0.5
A6
–2.0
–30.0
–3.5
A7
±0.5
+3.5
+1.9 in A2b
–7.6 in A4
NAMPS
VCO
1
1
+6.0 in A4
MSB sets the sign of the gain
MSB = 0 for gain
MSB = 1 for attenuation
For A2a, A4 and A7:
For all Gain Blocks:
All bits set to 0 = 0dB gain
All bits set to 1 = maximum gain or attenuation
a. A1 compensates for microphone gain variations in the transmit
path.
FUNCTIONAL DESCRIPTION
The SA5753 is an audio signal processor designed to meet the
requirements of compact low voltage radio telephone equipment. It
includes transmit and receive bandpass filters for voiceband
(300-3000Hz) with pre-emphasis and de-emphasis respectively, a
transmit peak deviation limiter, voice channel mute switches and a
b. A2a compensates for transmitter dynamic range variations due to
manufacturing tolerances of the SA5753 and SA5752 compandor
companion device. To meet AMPS requirements, the dynamic
range between the zero crossing signal level of the compandor
and the peak signal allowed by the deviation limiter is adjusted to
12.34dB.
2
data path which can be summed into the transmit channel. An I C
interface is provided for software programmability of a DTMF
generator, mute polarity, selection of different power down and
operating modes and control of the gain in both the transmit and
receive channels.
c. A2b allows coarse attenuation to be inserted in the transmit path
to eliminate positive feedback effects in hands-free speaker
applications. First step is 12dB followed by two steps of 6dB.
Software programmable gain control allows the device to be
automatically optimized during equipment production and offers
flexibility during normal operation.
d. A3 sets the gain between the DATA pin (Pin 19) and the TX
IN
OUT
pin (Pin 20) and should be adjusted after A2a and A4 have been
previously optimized. The SA5753 will interface directly with the
UMA1000T data processor (which produces a 2Vpk data signal).
For NAMPS applications an additional 10 to 14dB resistive divider
Gain Blocks
The programmable gain blocks are shown in Table 1 and Figure 2.
The purpose for each block is as follows:
must be added at the DATA pin (Pin 19) for a 2V data signal.
IN
5
1997 Nov 07
Philips Semiconductors
Product specification
Audio processor – filter and control section
SA5753
e. A4 compensates for transmit gain variations due to manufacturing
Although the POWER DOWN mode exhibits lower power
tolerances of the SA5753, SA5752 and VCO connected to TX
consumption, glitches may occur when transferring to an active
mode because of the previous high impedance of the I/O pins.
OUT
(Pin 20). After A2a has been adjusted to set dynamic range then
A4 is used to set the peak output voltage at TX (Pin 20) such
OUT
The VOX
and HPDN pins (Pins 5 and 6) still have the same
CTL
that a nominal 10kHz/V VCO produces a peak deviation of 12kHz
to meet AMPS specifications.
value as R8B7 and R5B1 in all low power modes.
2
Operation Without Using the I C Bus
f. A6 is the volume control for both the SPKR
and EAR
.
OUT
OUT
2
The SA5753 can be operated in a default mode with the I C bus
bypassed. To use this mode, the DFT pin (Pin 13) is pulled HIGH,
g. A7 compensates for manufacturing tolerances in the SA5753 and
preceeding demodulator. For AMPS requirements, a 1kHz tone
with 2.9kHz deviation should produce an output signal at
2
then the I C bus is bypassed and the SA5753 operates as if all
2
register bits in the I C address map table are set to ‘0’ except R1B2
DEMP
(Pin 7) corresponding to the zero crossing signal level
OUT
(S13), R0B0 (S10) and R0B1 (S9), which are set to ‘1’ to enable the
receiver output. R6B2 (PWDN), which is controlled by the state of
the HPDN pin (Pin 6), which is an input in DEFAULT mode.
of the expandor.
NAMPS and VCO Offsets
For NAMPS applications, a ‘1’ programmed into R5B3 (register 5, bit
3) will offset the transmit gain for NAMPS applications. It is
recommended that A2a and A4 be programmed after the NAMPS
option is set to compensate for manufacturing tolerances in the
NAMPS offset, itself.
When HPDN is pulled HIGH, the R6B2 bit is set to ‘0’ and the
SA5753 is placed in it’s normal operating mode with all Gain Control
Blocks set to 0dB except A3, which is set to –2dB.
When HPDN is pulled LOW, the R6B2 bit is set to ‘1’ and the
SA5753 enters POWER DOWN.
When the VCO bit of R5B2 is a ‘1’, an extra gain of 6dB is provided
There is no on-chip pull-up or pull-down structure on the HPDN pin
and so it must not be allowed to float in DEFAULT mode since the
operating mode of the SA5753 will then be undetermined.
at TX
for direct interface to VCOs with a nominal gain of 5kHz/V.
OUT
2
Operation Using the I C Communications Bus
The SA5753 includes on-chip gain blocks and options which can be
The Tx MUTE and Rx MUTE pins must be pulled LOW to enable the
transmit and receive paths, respectively.
2
programmed through an I C interface bus. To use this capability,
the DFT pin (Pin 13) must be pulled LOW. In this mode, all signal
level adjustments can be made through software with no external
potentiometers required.
The VOXCTL pin (Pin 5) will follow the value of the control bit stored
in R8B7 prior to pulling DFT HIGH.
The DTMF is disabled in the DEFAULT mode.
With DFT pulled LOW, the HPDN pin (Pin 6) is an OUTPUT having
the same value as the program bit in register 5 bit 1 (R5B1) of the
2
Programming Without the I C Protocol
control register bit map. The value at the VOX
output (Pin 5) is
CTL
In the default mode, with DFT (Pin 13) and HPDN (Pin 6) pulled
HIGH, the registers in the control register bit map are chained
together so that bit 0 of a register is connected to bit 7 of the
preceeding register with R0B6, R0B7, R1B6 and R1B7 bypassed,
i.e., R0B5 is connected to R1B0, R1B5 is connected to R2B0, R2B7
is connected to R3B0, etc. Bits can then be loaded as a serial
the same as the program bit in R8B7. The HPDN and VOX
outputs can be used to control the state of the SA5752 companion
device.
CTL
Power On Reset and Power Down Modes
In order to avoid undefined states of the SA5753 when power is
initially applied, a power-on-reset circuit is incorporated which
defaults RxP and TxP such that the receive and transmit paths are
muted if a ‘high’ voltage is applied to RX MUTE and TX MUTE (Pins
12 and 18). RX MUTE and TX MUTE include on-chip pull up
resistors so, during power up, the user may apply a logic ‘1’ to these
pins or leave them floating. After power up, the registers can be
programmed and the mutes removed by a quick access write to R0.
2
stream through the SDA pin of the I C bus by the negative edge of a
2
shifting clock applied at the SCL pin of the I C bus. When a bit is
loaded at SDA it will load first into R0B0 and then will be shifted to
R8B7 after 68 clock edges.
A total of 68 clock pulses (applied at SCL) are therefore required to
completely load the registers.
In this mode of operation the contents of the register map are also
Three software controlled low power modes are provided on the
SA5753. These are POWER DOWN (PWDN), IDLE and DENA and
can be selected by programming a ‘1’ into R6B2, R6B1 or R6B0 as
follows. In PWDN mode (R6B2=1) both the voice and data
channels are powered down with the respective I/O pins at a high
impedance. In DENA mode (R6B1=1) the voice channels are
shifted out from the VOX
R8B7. After power up there is no reset within the registers so the
first 68 bits clock out at the VOX
value.
pin since it takes the same value as
CTL
pin will have an indeterminate
CTL
Summary: To use this capability, the DFT pin and the HPDN pin
must be pulled HIGH, the serial bit stream loaded through SCL
synchronous with the negative clock edge applied at SCL for 68
clock pulses, and then the DFT pin pulled LOW.
powered down, but the data channel (from DATA and TX
) is
OUT
IN
fully active. In IDLE mode (R6B1=1, R6B0=1) both voice and data
channels are powered down. (See Table on page 8.)
NOTE: Default Mode is not tested in production.
The difference between selecting IDLE and PWDN is that the former
maintains the normal operational bias voltages at all voice and data
I/O pins and provides a glitch-free transfer from power down to a
fully active mode and vice-versa.
6
1997 Nov 07
Philips Semiconductors
Product specification
Audio processor – filter and control section
SA5753
2
Cordless Telephone Applications
I C Bus Data Configurations
2
For cordless telephone applications, a switch S12 is provided
(R5B0) to route data through the complete transmit path while
The SA5753 is always a slave receiver in the I C bus configuration).
The slave address consists of eight bits in the serial mode and is
internally fixed.
inhibiting the voice channel. In the receive path, a quick access
2
mode is provided through the I C to disable both EAR
and
OUT
Control Registers
SPKR , by setting R0B0 and R0B1, when data is detected at the
OUT
The control register bit map is shown below. Either a quick access
or normal address mode can be used, determined by the two MSB
bits in the first word following the SA5753 address word. If the quick
access mode is used, the registers R0 or R1 can be updated by
sending only two bytes of information (address plus update). If R0
or R1 are updated using the address mode, then B7 and B6 of the
data word are ignored. In all access modes, incremental register
addressing is supported with following words updating the next
register until a ‘stop’ bit is sent.
DEMP
pin (Pin 7).
OUT
2
I C CHARACTERISTICS
2
The I C bus is for 2-way, 2-line communication between different
ICs or modules. The two lines are a serial data line (SDA) and a
serial clock line (SCL). Both SDA and SCL are bidirectional lines
connected to a positive supply voltage via a pull-up resistor. When
the bus is free, both lines are HIGH. Data transfer may be initiated
only when the bus is not busy (both lines HIGH).
High Tone DTMF Register
The output devices, or stages, connected to the bus must have an
open drain or open collector output in order to perform the
wired-AND function.
MSB
LSB
HD7 HD6 HD5 HD4 HD3 HD2 HD1 HD0
2
The eight bits determine the output frequency by the following
formula.:
Data at the I C bus can be transferred at a rate up to 100kbits/s.
The number of devices connected to the bus is solely dependent on
the maximum allowed bus capacitance of 400pF.
High Frequency = 1200kHz/6/HD
where HD is the value of the register.
For devices operating over a wide range of supply voltages, such as
the SA5753, the following levels have been defined for a logical
LOW and HIGH;
Low Tone DTMF Register
MSB
LSB
V
ILMAX
V
IHMIN
= 0.3V (max. input LOW voltage)
DD
LD7 LD6 LD5 LD4 LD3 LD2 LD1 LD0
= 0.7V (min. input HIGH voltage)
DD
The eight bits determine the output frequency by the following
formula.:
Data Transfer
Data is transferred from a transmitting device to a receiving device
with one data bit transferred during each clock pulse on the SCL
line. The transmitter also generates the clock once arbitration has
given it control of the SCL line. The data on the SDA line must
remain stable during the HIGH period of the clock cycle, otherwise it
may be interpreted as a control signal.
Low Frequency = 1200kHz/14/LD
where LD is the value of the register.
The operation of the 96ms DTMF timer is initiated by the loading of
the low tone DTMF register. This timer terminates transmission of
the tones as the generated tones cross the reference level after
96ms. The on time of the tones can thus vary by up to one cycle of
the tones.
Start and Stop Conditions
Both data and clock lines remain HIGH when the bus is not busy. A
HIGH to LOW transition of the data line while the clock line is HIGH
is defined as a start condition. A LOW to HIGH transition of the data
line while the clock is HIGH is defined as a stop condition.
Continuous tones can be obtained by again loading DTC = 1 in R1,
bit 5.
Single tones can be obtained by loading 2 into the unused tone
register to silence it.
Acknowledgement
Loading a value of 1 or 0 into the registers will default the register
value to 257 or 256 for high tone or low tone, respectively.
Following each byte of data transfered, the receiver must
acknowledge successful reception. To do this the transmitter
releases the SDA line (allowing it to go HIGH) at the end of each
transmitted byte, and it is pulled LOW by the receiver. If this
condition is maintained during the next HIGH period of the clock
pulse (called the acknowledge clock pulse) then data transfer is
resumed. If the receiver does not pull the SDA line LOW, the
transmitter will abort the transfer.
Phase continuous frequency modulation can be produced by loading
a new value into a DTMF register during continuous operation
(DTC=1).
7
1997 Nov 07
Philips Semiconductors
Product specification
Audio processor – filter and control section
SA5753
2
I C Address and Access
S
A7 A6 A5 A4 A3 A2 A1 A0 ACK F7 F6 F5 F4 F3 F2 F1 F0 ACK ...
P
S = start, A0 = 0, ACK = acknowledge, P = stop, A7–0 = SA5753 address fixed internally at 1000000.
Access mode is determined by F7, F6.
All access modes support incremental addressing.
Mode
F7
0
F6
0
Action
quick access
quick access
test mode
Load F5–F0 to R0B5 – R0B0
Load F5-F0 to R1B5 – R1B0
For test only. DO NOT USE.
0
1
1
0
address mode
1
1
F3–F0 point to register
Address Map
Address
Register Bits
REG
F3 F2 F1 F0
B7
B6
B5
RxM
DTC
HD5
B4
TxM
B3
B2
B1
B0
S10
Y
Y
Y
R0
R1
R2
R3
R4
R5
R6
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
A2bb1 A2bb0 S9
Y
S4
S8
S13
HD2
LD2
S7
S2
HD7
LD7
HD6
LD6
HD4
LD4
HD3
LD3
HD1
LD1
A4b1
HD0
LD0
A4b0
LD5
A1b3 A1b2 A1b1 A1b0
A6b3 A6b2 A6b1 A6b0
A2ab4 A2ab3 A2ab2 A2ab1
A3b3 A3b2 A3b1 A3b0
A4b3 A4b2
NAMPS VCO
HPDN S12
A2ab0 PWDN IDLE 1 IDLE 0
R7
R8
0
1
1
0
1
0
1
0
A7b3 A7b2
S11 RxP
A7b1
TxP
A7b0
S1
VOX
S3
S5
S6
CTL
Y = ignored in address mode.
For all bits TRUE = ‘1’
A1b3–0
A2ab4–0
A2bb1–0
=
=
=
program bits for gain block A1
program bits for gain block A2a
program bits for gain block A2b
TxP
DTC
S1
=
=
transmit mute polarity
DTMF continuous
=
bypass TXBPF
A3b3–0
A4b4–0
=
=
program bits for gain block A3
program bits for gain block A4
S2
S3
=
=
bypass compressor in TX path, inhibit pre-emph input
bypass pre-emp and limiter in Tx path
S4
S5
S6
S7
S8
S9
=
=
=
=
=
=
enable DTMF to TX path and inhibit PREMP and S2.
bypass RXBPF
bypass de-emph in RX path
bypass expandor in RX path, inhibit audio input
A5b2–0
A6b3–0
A7b3–0
HD7–0
LD7–0
=
=
=
=
=
=
program bits for gain block A5
program bits for gain block A6
program bits for gain block A7
high tone DTMF
low tone DTMF
program bit for NAMPS offset
IN
enable DTMF to RX path and inhibit AUDIO and S7.
IN
NAMPS
enable SPKR
OUT
VCO
RxM
TxM
RxP
=
=
=
=
6dB higher TX
receive mute
transmit mute
receive mute polarity
S10 =
S11 =
S12 =
S13 =
enable EAR
bypass TXLPF
cordless data option established
enable data path
OUT
OUT
VOX
HPDN
=
=
enable VOX of compandor/expander circuit. This bit appears at the VOX
enable power down of compandor circuit. This bit appears at the HPDN pin (Pin 6) of the SA5753
pin (Pin 5) of the SA5753.
CTL
CTL
PWDN, IDLE1, IDLE0 see Table below
Low Power Modes (R6B0 – R6B2)
PWDN
IDLE1
IDLE0
2
1
0
X
1
X
0
(PWDN) Complete power down except I C, I/Os high impedance.
(DENA) Low power, I/Os at V /2, DATA to TX enabled.
DD
IN
OUT
0
0
1
0
1
0
(IDLE) Low power, I/Os at V /2, DATA to TX
Normal operation.
disabled.
OUT
DD
IN
0
0
1
DATA to TX
disabled.
OUT
IN
X = don’t care.
SR00667
8
1997 Nov 07
Philips Semiconductors
Product specification
Audio processor – filter and control section
SA5753
220nF
20
TX
S12
OUT
S11
S1
ATTN 4
220nF
220nF
MUTE
TX
TXLPF
Σ
1
2
TXBPF
TXBF
TXBF
S12
IN
S13
ATTN 1
V
REF
OUT
33nF
ATTN 3
19
18
DATA
IN
PREEMPH
AND
SOFT LIM
S3
33nF
TX MUTE
3
4
PREMP
I2C R8B1
IN
S2
ATTN 2
I2C R0B4
V
DD
.1µF
17
16
SDA
SCL
S2
S4
2
I
C INTERFACE
AND
REGISTERS
5
6
VOX
CTL
I2C R8B7
S4
HPDN
I2C R5B1
S6
DTMF
GEN
15
14
13
GND
2.2µF
1.2MHz
DEEMPH
7
8
DEMP
OUT
CLK
IN
S7
S7
S8
S5 RXBPF
DFT
220nF
S8
AUDIO
IN
I2C R0B5
220nF
220nF
I2C R8B3
MUTE
RX
9
S9
12
11
RX MUTE
SPEAKER
EAR
OUT
ATTN 6
ATTN 7
RX DEMOD
IN
10
OUT
S10
220nF
SR00668
Figure 2. SA5753 Test and Application Circuit
9
1997 Nov 07
Philips Semiconductors
Product specification
Audio processor – filter and control section
SA5753
SR00669
Figure 3. Application Diagram for the Audio Processor
10
1997 Nov 07
Philips Semiconductors
Product specification
Audio processor – filter and control section
SA5753
Companding and Amplifier Section
SA5752
Filter and Control Section
SA5753
PREAMP
MICROPHONE
NOISE
CANCEL
TX
SUMMING
BANDPASS
AMP
AUDIO TO
TRANSMITTER
FILTER
GAIN
CONTROL
VOX
VOX
OUTPUT
TX
TX
LOW
PRE–
PASS
FILTER
EMPHASIS
COMPRESSOR
RX
DE–
EMPHASIS
RX
BANDPASS
FILTER
AUDIO FROM
RECEIVER
DEMODULATOR
EXPANDOR
DTMF
GENERATOR
HEADPHONE
PA
CLOCK
1.2MHz
2
I
C
ATTENUATOR
BUS
INTERFACE
PA
FROM SYSTEM
2
CONTROLLER I C BUS
SPEAKER
VOX CONTROL
TDA7050T
SR00661
Figure 4. Typical Configuration of Audio Processor (APROC) System Chip Set
11
1997 Nov 07
Philips Semiconductors
Product specification
Audio processor – filter and control section
SA5753
DEMOD DATA
DATA PROCESSOR
POWER SUPPLY
TXEN
DATA
DEMOD
SA5752
RF BLOCK
POWER SUPPLY ENABLE
SA5753
LOGIC UNIT
TDA7050
MOD
VOX
8
2
I
C
EAR
MIC
CONTROL UNIT
SPEAKER
SR00670
Figure 5. APROC Application Diagram
2.5
2
2.5
2
+85°C
NORMAL
1.5
1
1.5
1
+25°C
-40°C
IDLE
0.5
0
0.5
0
I
vs V
vs TEMP
CC
CC
POWER DOWN
3.5
2
2.5
3
3.5
V
4
4.5
5
5.5
2
2.5
3
4
4.5
5
5.5
(V)
CC
V
(V)
CC
SR00671
SR00672
Figure 6. SA5753 Normal Operation
Figure 7. SA5753 Power Mode Comparison (I
)
CC
12
1997 Nov 07
Philips Semiconductors
Product specification
Audio processor – filter and control section
SA5753
1000
900
800
700
600
500
400
300
200
100
0
1
0.8
0.6
0.4
0.2
0
-40°C
+25°C
-0.2
-0.4
-0.6
-0.8
-1
+85°C
-30 -28 -26 -24 -22 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2
0
ATTENUATION LEVEL (dB)
POWER SUPPLY (V)
SR00674
SR00673
Figure 8. Gain Control, A6 Linearity
Figure 9. Power Supply vs Noise at TXBPF (25°C)
13
1997 Nov 07
Philips Semiconductors
Product specification
Audio processor — filter and control section
SA5753
SSOP20: plastic shrink small outline package; 20 leads; body width 4.4 mm
SOT266-1
14
1997 Nov 07
Philips Semiconductors
Product specification
Audio processor — filter and control section
SA5753
DEFINITIONS
Data Sheet Identification
Product Status
Definition
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
Objective Specification
Formative or in Design
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Preliminary Specification
Product Specification
Preproduction Product
Full Production
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. PhilipsSemiconductorsmakesnorepresentationorwarrantythatsuchapplicationswillbesuitableforthespecifiedusewithoutfurthertesting
or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
orsystemswheremalfunctionofaPhilipsSemiconductorsandPhilipsElectronicsNorthAmericaCorporationProductcanreasonablybeexpected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1997
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Philips
Semiconductors
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