SAA1101P [NXP]
IC SPECIALTY CONSUMER CIRCUIT, PDIP28, PLASTIC, DIP-28, Consumer IC:Other;
| 型号： | SAA1101P |
| 厂家： | 
NXP |
| 描述： | IC SPECIALTY CONSUMER CIRCUIT, PDIP28, PLASTIC, DIP-28, Consumer IC:Other 电机 |
| 文件： | 总18页 (文件大小：116K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
SAA1101
Universal sync generator (USG)
January 1990
Product specification
File under Integrated Circuits, IC02
Philips Semiconductors
Product specification
Universal sync generator (USG)
SAA1101
FEATURES
• Programmable to seven standards
• Additional outputs to simplify signal processing
• Can be synchronized to an external sync. signal
• Option to select the 524/624 line mode instead of the 525/625 line mode
• Lock from subcarrier to line frequency
GENERAL DESCRIPTION
The SAA1101 is a Universal Sync Generator (USG) and is designed for application in video sources such as cameras,
film scanners, video generators and associated apparatus. The circuit can be considered as a successor to the SAA1043
sync generator and the SAA1044 subcarrier coupling IC.
QUICK REFERENCE DATA
SYMBOL
VDD
PARAMETER
supply voltage range (pin 28)
MIN. MAX.
UNIT
4.5
5.5
10
24
V
IDD
quiescent supply current
clock oscillator frequency
−
−
µA
fOSC
MHz
ORDERING AND PACKAGE INFORMATION
EXTENDED
PACKAGE
PIN POSITION MATERIAL
TYPE NUMBER
PINS
CODE
SOT117 (1)
SOT136A (2)
SAA1101P
SAA1101T
28
28
DIL
SO28
plastic
plastic
Notes
1. SOT117-1; 1996 December 02.
2. SOT136-1; 1996 December 02.
January 1990
2
Philips Semiconductors
Product specification
Universal sync generator (USG)
SAA1101
GM9H1
,
January 1990
3
Philips Semiconductors
Product specification
Universal sync generator (USG)
SAA1101
PINNING
SYMBOL PIN
DESCRIPTION
page
FSI
1
subcarrier oscillator input, where fmax = 5 MHz
subcarrier oscillator output
FSI
FSO
CS1
CS0
OSCI
OSCO
VLE
V
Z
Y
X
1
2
28
27
26
25
24
DD
FSO
CS1
CS0
OSCI
OSCO
VLE
PH
2
3
clock frequency selection - CMOS input
clock frequency selection - CMOS input
clock oscillator input, where fmax = 24 MHz
clock oscillator output
3
4
4
5
CLO
5
6
23 NORM
HD
6
7
vertical in-lock enable - CMOS input
phase detector output - 3-state output
lock mode selection - CMOS input
lock mode selection - CMOS input
22
21 VD
7
8
SAA1101
LM1
LM0
ECS
9
PH
8
10
11
LM1
LM0
ECS
WMP
9
20
19
18
17
16
external composite sync. signal - CMOS Schmitt-trigger
input
CLP
CS
CB
BK
10
11
RR
SI
12
13
frame reset - CMOS Schmitt-trigger input
RR 12
set identification, used to set the correct field sequence in
PAL-mode. The correction (inversion of fH2) is done at the
left-hand slope of the SI-pulse. Minimum pulse width is
800 ns. CMOS Schmitt-trigger input.
SI
13
14
V
15 ID
SS
MGH190
VSS
ID
14
15
16
ground
identification - push-pull output
Fig.2 Pinning configuration;
SOT117.
BK
burst key (PAL/NTSC), chroma-blanking (SECAM) -
push-pull output
CB
17
18
19
20
21
22
23
composite blanking - push-pull output
composite sync. - push-pull output
clamp pulse - push-pull output
FUNCTIONAL DESCRIPTION
Generation of pulses
CS
CLP
WMP
VD
white measurement pulse-3-state output
vertical drive pulse - push-pull output
horizontal drive pulse - push-pull output
Generation of standard pulses such
as sync, blanking and burst for TV
systems: PAL B/G, PALN, PALM,
SECAM and NTSC. In addition a
number of non-standard pulses have
been supplied to simplify signal
processing. These signals include -
horizontal drive, vertical drive, clamp
pulse, identification etc. It is possible
to select the 524/624 line mode
instead of the 525/625 line mode for
all the above TV systems for
HD
NORM
used with X, Y and Z to select TV system; NORM = 0,
625/525 line mode (standard);
NORM = 1, 624/524 line mode - CMOS input
CLO
X
24
25
26
27
28
clock output - push-pull output
TV system selection input - CMOS input
TV system selection input - CMOS input
TV system selection input - CMOS input
voltage supply
Y
Z
VDD
applications such as robotics, games
and computers.
January 1990
4
Philips Semiconductors
Product specification
Universal sync generator (USG)
SAA1101
subcarrier input is, in this case, used as an external
input for the horizontal reference, see Fig.3(d).
Lock modes
The USG offers four lock modes:
• Lock from the subcarrier
SELECTION OF LOCK MODE
• Slow sync. lock, external Href
• Slow sync. lock, internal Href
• Fast sync. lock, internal Href
Lock mode is selected using the inputs LM0 and LM1 as
illustrated in the Table below.
LOCK FROM SUBCARRIER
LM0
LM1
SELECTION
lock to subcarrier
Lock from subcarrier to the line frequency for the above
mentioned TV systems is given below; the horizontal
frequency (fH) = 15.625 kHz for 625 line systems and
15.734264 kHz for 525 line systems.
0
0
1
1
0
1
0
1
slow sync. lock external Href
slow sync. lock internal Href
fast sync. lock internal Href
SECAM (1 and 2)
PALN
282fH
229.2516fH
227.5fH
NTSC (1 and 2)
PALM
227.25fH
283.7516fH
PAL B/G
These relationships are obtained by the use of a phase
locked loop and the internal programmed divider chain,
see Fig.3(a).
LOCK TO AN EXTERNAL SIGNAL SOURCE
The following methods can be used to lock to an external
signal source:
1. Sync. lock slow; the line frequency is locked to an
external signal. The line and frame information are
extracted from the external sync. signal and used
separately in the lock system. The line information is
used in a phase-locked loop where external and
internal line frequencies are compared by the same
phase detector as is used for the subcarrier lock. The
external frame information is compared with the
internal frame in a slow lock system; mismatch of
internal and external frames will result in the addition
or suppression of one line depending on the direction
of the fault. The maximum lock time for frame lock is
6.25 s, see Fig.3(b).
2. Sync. lock fast. A fast lock of frames is possible with a
frame reset which is extracted out of the incoming
external sync. signal, see Fig.3(c).
3. Sync. lock with external reference. Lock of an external
sync. signal to the line frequency with an external line
reference to make possible a shifted lock. The
January 1990
5
Philips Semiconductors
Product specification
Universal sync generator (USG)
SAA1101
The different lock modes are illustrated by the following figures:
handbook, halfpage
n × f
H
handbook, halfpage
n × f
H
LINE
OSCILLATOR
LINE
OSCILLATOR
OSCO
OSCI
8
OSCO
OSCI
6
5
6
5
FSI
ECS
PH
PH
8
1
11
SUB-
CARRIER
SAA1101
SAA1101
OSCILLATOR
FSO
2
10
9
10
9
LM0
LM1
LM0
LM1
logic 1
logic 1
MGH195
logic 0
logic 1
MGH193
Fig.3 (a) Lock to subcarrier.
Fig.3 (c) Fast sync lock, internal H ref
handbook, halfpage
handbook, halfpage
n × f
n × f
H
H
LINE
OSCILLATOR
LINE
OSCILLATOR
H
D
OSCO OSCI
5
OSCO
OSCI
τ
22 6
6
5
FSI
PH
ECS
PH
8
1
8
11
H
ref
SAA1101
SAA1101
ECS
11
10
9
10
9
LM0
LM1
LM0
LM1
logic 0
logic 1
MGH192
logic 0
logic 1
MGH194
Fig.3 (b) Slow sync lock, internal Href
Fig.3 (d) Slow sync lock, external H ref
January 1990
6
Philips Semiconductors
Product specification
Universal sync generator (USG)
SAA1101
LOCK WITH HORIZONTAL AND VERTICAL SIGNALS
(slow lock modes only)
It is possible to use horizontal and vertical signals instead of composite sync signals. The connections in this situation
are: the external horizontal signal is connected to the ECS input (pin 11) and the vertical signal to the RR input (pin 12).
The HIGH time of the horizontal pulse must be less than 14.4 µs, otherwise it will be detected as being a vertical pulse
and will corrupt the vertical slow lock system.
Selection of Clock Frequency
The clock frequency is selected using the CS0 and CS1 inputs as illustrated below.
CS0
CS1
FREQUENCY
160fH
625 LINES
2.5
525 LINES
2.517482
UNITS
MHz
0
0
1
1
0
1
0
1
160fH
960fH
1440fH
5
5.034964
MHz
15
22.5
15.104893
22.657340
MHz
MHz
Where the horizontal frequency, fH = 15.625 kHz for 625 lines and 15.734264 kHz for 525 lines.
Oscillators
The subcarrier oscillator has FSI as its input and FSO as its output. It is always used as a crystal oscillator with a series
resonance crystal with parallel load capacitor. The maximum frequency, fmax = 5 MHz and the load capacitor,
CL = 10 < CL < 35 pF.
The clock oscillator has OSCI as its input and OSCO as its output. It can be used with an LC oscillator or a series
resonance crystal with parallel load capacitor (Fig.4). The maximum frequency, fmax = 24 MHz and the load capacitor,
CL = 10 < CL < 35 pF.
Selection of 625/525 (standard; interlaced mode) or 624/524 lines (non-interlaced mode)
Selection is achieved using the NORM input. When NORM = 0, 625/525 (standard) lines are selected;
when NORM = 1, 624/524 line are selected.
Output Dimensions
All push-pull outputs: standard output 2 mA.
White measurement pulse, WMP: 3-state output 2 mA.
Phase detector, PH: 3-state output 2 mA.
January 1990
7
Philips Semiconductors
Product specification
Universal sync generator (USG)
SAA1101
handbook, halfpage
39 pF
OSCI
5
6
500 kΩ
SAA1101
15 MHz
39 pF
OSCO
1 kΩ
MGH196
Fig.4 Crystal oscillator circuit.
Selection of TV System
Selection of the required TV system is achieved by the X, Y and Z inputs as illustrated by the following Table.
SYSTEM
X
Y
Z
SECAM1
PALN
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
NTSC1
PALM
SECAM2
PAL B/G
NTSC2
0 (with identifier)
1
0 (short blanking)
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER MIN.
supply voltage
MAX.
UNIT
VDD
VI
−0.5
−0.5
−
+7
DD + 0.5 (1)
V
input voltage
V
V
II
maximum input current
maximum output current
maximum supply current in VDD
maximum power dissipation
storage temperature range
±10
±10
25
mA
mA
mA
mW
°C
IO
−
IDD
Ptot
Tstg
−
−
400
+150
−55
Note
1. Input voltage should not exceed 7 V.
January 1990
8
Philips Semiconductors
Product specification
Universal sync generator (USG)
SAA1101
CHARACTERISTICS
V
DD = 4.5 to 5.5 V; Tamb = −25 to +70 °C unless otherwise specified
SYMBOL PARAMETER CONDITIONS
Supplies
MIN.
TYP.
MAX. UNIT
VDD
IDD
supply voltage
4.5
−
−
5.5
V
supply current (quiescent)
input leakage current
Tamb = 25 °C
−
10
µA
Inputs
±II
Tamb = 25 °C
−
−
100
nA
CMOS COMPATIBLE; X, Y, Z, NORM, CS0, CS1, LM0, LM1 AND VLE
VIH
VIL
input voltage HIGH
input voltage LOW
0.7VDD
−
−
−
V
V
−
0.3VDD
SCHMITT TRIGGER INPUTS; ECS, RR AND SI
VT+
VT−
VH
positive-going threshold
negative-going threshold
hysteresis
−
2.5
1.5
1
4
−
−
V
V
V
1
0.4
OSCILLATOR INPUTS; OSCI AND FSI
VIH
VIL
input voltage HIGH
input voltage LOW
0.7VDD
−
−
−
V
V
−
0.3VDD
Outputs
PUSH-PULL OUTPUTS; CB, CS, BK, ID, HD, VD, CLP AND CLO
VOH
VOL
output voltage HIGH
output voltage LOW
−IO = 2 mA; VDD = 5 V
4.5
−
−
−
V
V
IO = 2 mA; VDD = 5 V
−
0.5
OSCILLATOR OUTPUTS; OSCO AND FSO
VOH
VOL
output voltage HIGH
output voltage LOW
−IO = 0.75 mA; VDD = 5 V 4.5
−
−
−
V
V
IO = 0.75 mA; VDD = 5 V
−
0.5
3-STATE OUTPUTS; WMP AND PH
VOH
VOL
±IOZ
output voltage HIGH
−IO = 2 mA; VDD = 5V
IO = 2 mA; V DD = 5V
Tamb = 25 °C
4.5
−
−
−
−
−
V
output voltage LOW
OFF-state current
0.5
50
V
−
nA
January 1990
9
Philips Semiconductors
Product specification
Universal sync generator (USG)
SAA1101
OUTPUT WAVEFORMS
The output waveforms for the different modes of operation are illustrated by Figs 5 and 6.
GM1H98
f
January 1990
10
i
start half picture
1st half
picture
CS
CS
CB
2nd half
picture
t
WCB
1st half
picture
21H + t
WCB
NTSC 1
(2)
2nd half
picture
CB
VD
BK
BK
BK
BK
BK
BK
CB
CB
6H
1st half
picture
NTSC 1 + 2
(2)
2nd half
picture
9H
1st half
picture
(1)
11H
2nd half
picture
PAL−M
3rd half
picture
4th half
picture
1st half
picture
19H + t
WCB
NTSC 2
(2)
2nd half
picture
MGH197
(1) H = 1 horizontal scan.
(2) NTSC mode reset; the fourth half picture is identical to the second half picture for NTSC.
Fig.6 Typical output waveforms for NTSC and PAL-M. In the 524-line mode the output waveforms are identical to the first half picture of NTSC
and are not interlaced.
Philips Semiconductors
Product specification
Universal sync generator (USG)
SAA1101
WAVEFORM TIMING
The waveform timing depends on the frequency of the oscillator input (fOSCI). This is illustrated in the table below as the
number (N) of oscillations at OSCI. The timings are derived from N × tOSCI ± 100 ns.
One horizontal scan (H) = 320 × tOSCI =1/fH.
Where tOSCI = 200 ns for PAL/SECAM and 198.6 ns for NTSC/PAL-M
SYMBOL
PARAMETER
PAL
NTSC
PAL-M
SECAM
UNIT
N
Composite sync (CS)
tWSC1
horizontal sync pulse 4.8
4.77
4.77
4.8
µs
24
width
tWSC2
tWSC3
−
equalizing pulse width 2.4
serration pulse width 4.8
2.38
4.77
3
2.38
4.77
3
2.4
4.8
2.5
µs
µs
H
12
24
−
duration of
2.5
pre-equalizing pulses
−
−
duration of
post-equalizing
pulses
2.5
3
3
3
2.5
2.5
H
H
−
−
duration of serration
pulses
2.5
3.5
Composite blanking (CB)
HORIZONTAL BLANKING PULSE WIDTH
tWCB
tWCB
tWCB
PAL/SECAM/PAL-M
NTSC1
12
−
−
11.12
12
−
µs
µs
µs
60
56
53
11.12
−
−
NTSC2
−
10.53 (note1)
−
FRONT PORCH
tPCBCS front porch
1.6
1.59
1.59
1.6
µs
8
DURATION OF VERTICAL BLANKING
−
−
−
PAL/SECAM/PAL-M
NTSC1
25H + tWCB
−
21H + tWCB
25H + tWCB
−
−
−
−
−
−
−
−
21H + tWCB
19H + tWCB
−
−
−
−
NTSC2
Burst key (BK) (not SECAM)
tWBK
tPCSBK
−
burst key pulse width 2.4
CS to burst key delay 5.6
burst suppression
2.38
5.56
9
2.38
5.76
11
−
−
−
µs
µs
H
12
28
−
9
POSITION OF BURST SUPPRESSION
−
−
−
−
first half picture
H623 to H6
H523 to H6
H523 to H8
−
−
−
−
−
−
−
−
−
−
−
−
second half picture
third half picture
fourth half picture
H310 to H318 H261 to H269 H260 to H270
H622 to H5 H523 to H6 H522 to H7
H311 to H319 H261 to H269 H259 to H269
January 1990
12
Philips Semiconductors
Product specification
Universal sync generator (USG)
SAA1101
SYMBOL
PARAMETER
PAL
NTSC
PAL-M
SECAM
UNIT
N
Burst key (BK) (SECAM)
tWBK
chroma pulse width
CS to chroma delay
−
−
−
−
−
−
7.2
1.6
µs
36
tPBKCS
µs
8
DURATION OF VERTICAL BLANKING
−
−
SECAM1
SECAM2
−
−
−
−
−
−
note 2
note 3
−
−
−
−
Clamp pulse (CLP)
tWCLP
clamp pulse width
CS to CLP delay
2.4
1.6
2.38
1.59
2.38
1.59
2.4
1.6
µs
µs
12
8
tPCSCLP
Horizontal drive (HD)
tWHD
tPHDCS
−
pulse width
7.2
0.8
64
7.15
0.79
7.15
0.79
63.56
7.2
0.8
64
µs
µs
µs
36
4
CS to HD delay
repetition period
63.56
−
Vertical drive (VD)
−
VD duration
CS to VD delay
10
6
6
10
H
−
tPVDCS
1.6
1.59
1.59
1.6
µs
8
White measurement pulse (WMP)
−
−
−
pulse width
2.4
34.4
10
2.38
34.16
9
2.38
34.16
9
2.4
34.4
10
µs
µs
H
12
172
−
CS to WMP delay
duration of WMP
POSITION OF WMP
−
−
first half picture
second half picture
H163 to H173 H134 to H143 H134 to H143 H163 to H173
H475 to H485 H396 to H405 H396 to H405 H475 to H485
−
−
−
−
Identification (ID)
tWID
pulse width
CS to ID delay
12
11.12
1.59
11.12
1.59
12
µs
µs
60
8
tPIDCS
1.6
1.6
POSITION OF ID
−
−
first half picture
second half picture
H7 to H15
H8 to H22
H8 to H22
H7 to H15
−
−
−
−
H320 to H328 H271 to H285 H271 to H285 H320 to H328
Notes to the characteristics
1. Horizontal blanking pulse width for NTSC2 can be 11.12 µs maximum
2. SECAM1, first half picture: 25H + tWBK except H320 to H328. Second half picture: 24.5H + tWBK except H7 to H15.
3. SECAM2, first half picture: 25H + tWBK. Second half picture: 24.5H + tWBK
.
January 1990
13
Philips Semiconductors
Product specification
Universal sync generator (USG)
SAA1101
horizontal
t
WSC1
sync pulse
composite
sync
t
WSC2
equalizing pulse
serration pulse
CS
CB
t
WSC3
horizontal
blanking pulse
composite
blanking
t
WCB
t
PCBS2
t
t
WBK
PCBSK
burst key (PAL)
burst key/
chrominance
blanking
BK
HD
(SECAM)
chrominance
blanking
t
WBK
t
PBKCS
t
horizontal drive
t
WHD
PHDCS
t
WCPL
CLP clamp pulse
t
PCSCLP
t
SECAM
ID
WID
identification
t
PIDCS
start, stop
vertical drives
VD
t
PVDCS
MLA029
Fig.7 Waveform timing.
January 1990
14
Philips Semiconductors
Product specification
Universal sync generator (USG)
SAA1101
PACKAGE OUTLINES
handbook, full pagewidth
DIP28: plastic dual in-line package; 28 leads (600 mil)
SOT117-1
D
M
E
A
2
A
L
A
1
c
e
w M
Z
b
1
(e )
1
b
M
H
28
15
pin 1 index
E
1
14
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
max.
A
A
Z
(1)
(1)
1
2
UNIT
mm
b
b
c
D
E
e
e
L
M
M
w
1
1
E
H
min.
max.
max.
1.7
1.3
0.53
0.38
0.32
0.23
36.0
35.0
14.1
13.7
3.9
3.4
15.80
15.24
17.15
15.90
5.1
0.51
4.0
2.54
0.10
15.24
0.60
0.25
0.01
1.7
0.013
0.009
0.066
0.051
0.020
0.014
1.41
1.34
0.56
0.54
0.15
0.13
0.62
0.60
0.68
0.63
inches
0.20
0.020
0.16
0.067
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-11-17
95-01-14
SOT117-1
051G05
MO-015AH
January 1990
15
Philips Semiconductors
Product specification
Universal sync generator (USG)
SAA1101
SO28: plastic small outline package; 28 leads; body width 7.5 mm
SOT136-1
D
E
A
X
c
y
H
v
M
A
E
Z
28
15
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
14
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.30
0.10
2.45
2.25
0.49
0.36
0.32
0.23
18.1
17.7
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
mm
2.65
1.27
0.050
1.4
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.71
0.014 0.009 0.69
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches 0.10
0.055
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-01-24
97-05-22
SOT136-1
075E06
MS-013AE
January 1990
16
Philips Semiconductors
Product specification
Universal sync generator (USG)
SAA1101
Several techniques exist for reflowing; for example,
SOLDERING
Introduction
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
WAVE SOLDERING
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
Wave soldering techniques can be used for all SO
packages if the following conditions are observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
DIP
SOLDERING BY DIPPING OR BY WAVE
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
• The package footprint must incorporate solder thieves at
the downstream end.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
REPAIRING SOLDERED JOINTS
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
REPAIRING SOLDERED JOINTS
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
SO
REFLOW SOLDERING
Reflow soldering techniques are suitable for all SO
packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
January 1990
17
Philips Semiconductors
Product specification
Universal sync generator (USG)
SAA1101
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
January 1990
18
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