SAA5297_技术文档

INTEGRATED CIRCUITS

DATA SHEET

SAA5x9x family

Economy teletext and TV

microcontrollers

1997 Jul 07

Preliminary speciﬁcation

File under Integrated Circuits, IC02

Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

CONTENTS

9.7

Language group identification

9.8

9.9

525-line operation

On Screen Display characters

Control characters

Quadruple width display (SAA549x)

Page attributes

Display modes

On Screen Display boxes

Screen colour

Redefinable Colours (SAA549x)

Cursor

Other display features

Display timing

Horizontal timing

Vertical timing

1

FEATURES

9.10

9.11

9.12

9.13

9.14

9.15

9.16

9.17

9.18

9.19

9.20

9.21

9.22

9.23

1.1

1.2

1.3

1.4

1.5

1.6

General

Microcontroller

Teletext acquisition

Teletext Display

Additional features of SAA529xA devices

Additional features of SAA549x devices

2

3

4

5

6

GENERAL DESCRIPTION

ORDERING INFORMATION

QUICK REFERENCE DATA

BLOCK DIAGRAM

PINNING INFORMATION

Display position

Clock generator

6.1

6.2

Pinning

Pin description

10

CHARACTER SETS

7

FUNCTIONAL DESCRIPTION

10.1

10.2

10.3

10.4

10.5

10.6

Pan-European

Russian

Greek/Turkish

Arabic/English/French

Thai

7.1

7.2

7.3

7.4

Microcontroller

80C51 Features not supported

Additional features

Microcontroller interfacing

Arabic/Hebrew

8

TELETEXT DECODER

11

12

13

LIMITING VALUES

8.1

8.2

8.3

8.4

8.5

8.6

Data slicer

Acquisition timing

Teletext acquisition

Rolling headers and time

Error checking

Memory organisation of SAA5296/7,

SAA5296/7A and SAA5496/7

Inventory page

Memory Organisation of SAA5291, SAA5291A

and SAA5491

Packet 26 processing

VPS

Wide Screen Signalling (SAA529xA and

SAA549x only)

CHARACTERISTICS

CHARACTERISTICS FOR THE I²C-BUS

INTERFACE

14

15

16

17

18

QUALITY SPECIFICATIONS

APPLICATION INFORMATION

EMC GUIDELINES

8.7

8.8

PACKAGE OUTLINES

SOLDERING

8.9

8.10

8.11

18.1

18.2

18.3

Introduction

SDIP

QFP

8.12

8.13

8.14

8.15

8.16

525-line world system teletext

Fastext detection

Page clearing

Full channel operation

Independent data services (SAA5291,

SAA5291A, SAA5491 only)

19

20

21

DEFINITIONS

LIFE SUPPORT APPLICATIONS

PURCHASE OF PHILIPS I²C COMPONENTS

9

THE DISPLAY

9.1

9.2

9.3

9.4

9.5

9.6

Introduction

Character matrix

East/West selection

National option characters

The twist attribute

On Screen Display symbols

1997 Jul 07

2

Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

1

FEATURES

General

1.4

Teletext Display

• 525-line and 625-line display

• 12 × 10 character matrix

1.1

• Single chip microcontroller with integrated teletext

decoder

• Double height, width and size On-Screen Display (OSD)

• Definable border colour

• Single +5 V power supply

• Single crystal oscillator for teletext decoder, display and

• Enhanced display features including meshing and

microcontroller

shadowing

• Teletext function can be powered-down independently

of microcontroller function for reduced power

consumption in stand-by

• 260 characters in mask programmed ROM

• Automatic FRAME output control with manual override

• RGB push pull output to standard decoder ICs

• Pin compatibility throughout family.

• Stable display via slave synchronisation to Horizontal

Sync and Vertical Sync.

1.2

Microcontroller

• 80C51 microcontroller core

1.5

Additional features of SAA529xA devices

• 16/32/64 kbyte mask programmed ROM

• 256/768/1280 bytes of microcontroller RAM

• Wide Screen Signalling (WSS) bit decoding (line 23).

1.6

Additional features of SAA549x devices

• Eight 6-bit Pulse Width Modulator (PWM) outputs for

control of TV analog signals

• Wide Screen Signalling bit decoding (line 23)

• Quad width OSD capability

• One 14-bit PWM for Voltage Synthesis Tuner control

• Four 8-bit Analog-to-Digital converters

• 32 additional OSD characters in mask programmed

• 2 high current open-drain outputs for directly driving

ROM

LED’s etc.

• I²C-bus interface

• 8 foreground and 8 background colours definable from a

palette of 64.

• External ROM and RAM capability on QFP80 package

version.

2

GENERAL DESCRIPTION

The SAA529x, SAA529xA and SAA549x family of

microcontrollers are a derivative of the Philips’

industry-standard 80C51 microcontroller and are intended

for use as the central control mechanism in a television

receiver. They provide control functions for the television

system and include an integrated teletext function.

1.3

Teletext acquisition

• 1 page and 10 page Teletext version

• Acquisition of 525-line and 625-line World System

Teletext, with automatic selection

• Acquisition and decoding of VPS data (PDC system A)

• Page clearing in under 64 µs (1 TV line)

The teletext hardware has the capability of decoding and

displaying both 525-line and 625-line World System

Teletext. The same display hardware is used both for

Teletext and On-Screen Display, which means that the

display features give greater flexibility to differentiate the

TV set.

• Separate storage of extension packets

(SAA5296/7, SAA5296/7A and SAA5496/7)

• Inventory of transmitted Teletext pages stored in the

Transmitted Page Table (TPT) and Subtitle Page Table

(SPT) (SAA5296/7, SAA5296/7A and SAA5496/7)

The family offers both 1 page and 10 page Teletext

capability, in a range of ROM sizes. Increasing display

capability is offered from the SAA5290 to the SAA5497.

• Automatic detection of FASTEXT transmission

• Real-time packet 26 engine for processing accented

(and other) characters

• Comprehensive Teletext language coverage

• Video signal quality detector.

1997 Jul 07

3

Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

3

ORDERING INFORMATION

PACKAGE

PROGRAM

MEMORY (ROM)

TYPE NUMBER⁽¹⁾

NAME

DESCRIPTION

VERSION

SAA5290PS/nnn

SDIP52 plastic shrink dual in-line package; 52 leads

(600 mil)

SOT247-1 16 kbytes

SAA5291PS/nnn

SAA5291APS/nnn

SAA5296PS/nnn

SAA5296APS/nnn

SAA5491PS/nnn

SAA5496PS/nnn

SAA5291H/nnn

SAA5291AH/nnn

SAA5296H/nnn

SAA5296AH/nnn

SAA5491H/nnn

SAA5496H/nnn

SAA5297PS/nnn

SAA5297APS/nnn

SAA5497PS/nnn

SAA5297H/nnn

SAA5297AH/nnn

SAA5497H/nnn

plastic shrink dual in-line package; 52 leads

(600 mil)

SDIP52

SOT247-1 32 kbytes

plastic quad ﬂat package; 80 leads (lead length

QFP80

SOT318-2 32 kbytes and external

1.95 mm); body 14 × 20 × 2.8 mm

plastic shrink dual in-line package; 52 leads

(600 mil)

SDIP52

SOT247-1 64 kbytes

plastic quad ﬂat package; 80 leads (lead length

QFP80

SOT318-2 64 kbytes or external

1.95 mm); body 14 × 20 × 2.8 mm

Note

1. ‘nnn’ is a three-digit number uniquely referencing the microcontroller program mask and OSD mask.

4

QUICK REFERENCE DATA

SYMBOL

PARAMETER

MIN.

4.5

TYP.

5.0

MAX.

5.5

UNIT

V_DDA

supply voltages

V

V_DDM

V_DDT

f_xtal

crystal frequency

−

12

−

MHz

°C

T_amb

I_DDM

operating ambient temperature

microcontroller supply current

−20

−

+70

35

20

mA

SAA5290, SAA5291, SAA5291A and SAA5491

I_DDA

I_DDT

analog supply current

teletext supply current

−

35

40

50

65

mA

SAA5296, SAA5296A, SAA5297, SAA5297A, SAA5496 and SAA5497

I_DDA

I_DDT

analog supply current

teletext supply current

−

35

50

80

mA

1997 Jul 07

4

Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

5

BLOCK DIAGRAM

V

SSA SSD

BLACK

IREF

DDA

DDM

DDT

handbook, full pagewidth

CVBS0,

CVBS1

TELETEXT

ACQUISITION

R, G, B,

VDS,

COR

DATA SLICER

DISPLAY

PAGE

RAM

VSYNC

HSYNC

FRAME

ACQUISITION

TIMING

DISPLAY

TIMING

SAA5x9x

XTALIN

XTALOUT

OSCGND

OSCILLATOR

512 × 8

AUX RAM

32K × 8

ROM

256 × 8

RAM

TEXT

INTERFACE

data

address

8051

MICRO-

RESET

CONTROLLER

2

I C-BUS

INTERFACE

int

TIMER/

CTRS

ADC

PWM

PORT 1

PORT 0

PORT 3

PORT 2

MGK462

P1.0 to P1.7

P0.0 to P0.7

P3.0 to P3.7

P2.0 to P2.7

Fig.1 Block diagram.

1997 Jul 07

5

Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

6

PINNING INFORMATION

Pinning

6.1

handbook, halfpage

P2.0/TPWM

1

2

3

4

5

6

7

8

9

52 P1.5

P2.1/PWM0

P2.2/PWM1

P2.3/PWM2

P2.4/PWM3

P2.5/PWM4

P2.6/PWM5

P2.7/PWM6

P3.0/ADC0

51 P1.4

50 P1.7/SDA

49 P1.6/SCL

48 P1.3/T1

47 P1.2/INT0

46 P1.1/T0

45 P1.0/INT1

V

44

DDM

P3.1/ADC1 10

P3.2/ADC2 11

P3.3/ADC3 12

43 RESET

42 XTALOUT

41 XTALIN

40 OSCGND

V

13

SSD

SAA5x9x

V

P0.0 14

P0.1 15

P0.2 16

P0.3 17

P0.4 18

P0.5 19

P0.6 20

39

38

DDT

DDA

V

37 VSYNC

36 HSYNC

35 VDS

34

33

32

R

G

B

P0.7 21

V

22

31 RGBREF

SSA

CVBS0 23

CVBS1 24

30 P3.4/PWM7

29

28

COR

V

BLACK

IREF

25

26

SSD

27 FRAME

MGK461

Fig.2 Pin configuration (SDIP52).

6

1997 Jul 07

Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

handbook, full pagewidth

64 P1.1/T0

P2.6/PWM5

P2.7/PWM6

P3.0/ADC0

n.c.

1

2

3

4

5

6

7

8

9

63 P1.0/INT1

62

V

DDM

61 P1.3/T1

60 P1.2/INT0

59 RESET

58 XTALOUT

57 XTALIN

56 OSCGND

55 A8

P3.1/ADC1

P3.2/ADC2

P3.3/ADC3

P2.5/PWM4

P2.4/PWM3

RD 10

WR 11

54 A9

53 A10

V

12

SSD

SAA5x9x

52 A11

EA 13

P0.0 14

P0.1 15

P0.2 16

51

V

DDT

50 REF+

49

V

DDA

48 P3.6

PSEN 17

ALE 18

REF− 19

P0.3 20

P0.4 21

P3.7 22

n.c. 23

47 VSYNC

46 P3.5

45 HSYNC

44 P3.4/PWM7

43 VDS

42

41

R

G

P0.5 24

MGL157

Fig.3 Pin configuration (QFP80).

7

1997 Jul 07

Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

6.2

Pin description

Table 1 SDIP52 and QFP80 packages

SYMBOL

DESCRIPTION

SDIP52

QFP80

P2.0/TPWM

P2.1/PWM0

P2.2/PWM1

P2.3/PWM2

P2.4/PWM3

P2.5/PWM4

P2.6/PWM5

P2.7/PWM6

P3.0/ADC0

P3.1/ADC1

P3.2/ADC2

P3.3/ADC3

P3.4/PWM7

P3.5

1

2

77

78

79

80

9

Port 2: 8-bit open-drain bidirectional port with alternative functions.

P2.0/TPWM is the output for the 14-bit high precision PWM.

P2.1/PWM0 to P2.7/PWM6 are the outputs for the 6-bit PWMs 0 to 6.

3

4

5

6

8

7

1

8

2

9

3

Port 3: 8-bit open-drain bidirectional port with alternative functions.

P3.0/ADC0 to P3.3/ADC3 are the inputs for the software ADC facility.

P3.4/PWM7 is the output for the 6-bit PWM7.

10

11

12

30

−

5

6

7

44

46

48

22

12

14

15

16

20

21

24

25

26

27

28

29

30

P3.6

−

P3.7

−

V_SSD

13

14

15

16

17

18

19

20

21

22

23

24

25

Digital ground.

P0.0

Port 0: 8-bit open-drain bidirectional port.

P0.1

P0.5 and P0.6 have 10 mA current sinking capability for direct drive of LEDs.

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

V_SSA

Analog ground.

CVBS0

Composite video inputs; a positive-going 1 V (peak-to-peak) input is required,

connected via a 100 nF capacitor.

CVBS1

BLACK

Video black level storage input: this pin should be connected to V_SSAvia a

100 nF capacitor.

IREF

26

27

31

36

Reference current input for analog circuits, connected to V_SSAvia a 27 kΩ

resistor.

FRAME

De-interlace output synchronised with the VSYNC pulse to produce a

non-interlaced display by adjustment of the vertical deﬂection circuits.

V_SSD

COR

28

29

37

38

Internally connected; this pin should be connected to digital ground.

Open-drain, active LOW output which allows selective contrast reduction of

the TV picture to enhance a mixed mode display.

1997 Jul 07

8

Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

SYMBOL

DESCRIPTION

SDIP52

QFP80

LRGBREF

31

32

33

34

35

36

39

40

41

42

43

45

DC input voltage to deﬁne the output HIGH level on the RGB pins.

Pixel rate output of the BLUE colour information.

B

G

Pixel rate output of the GREEN colour information.

Pixel rate output of the RED colour information.

R

VDS

HSYNC

Video/data switch push-pull output for dot rate fast blanking.

Schmitt trigger input for a TTL level version of the horizontal sync pulse; the

polarity of this pulse is programmable by register bit TXT1.H POLARITY.

VSYNC

37

47

Schmitt trigger input for a TTL level version of the vertical sync pulse;

the polarity of this pulse is programmable by register bit TXT1.V POLARITY.

V_DDA

38

39

40

41

42

43

49

51

56

57

58

59

+5 V analog power supply.

+5 V teletext power supply.

Crystal oscillator ground.

V_DDT

OSCGND

XTALIN

XTALOUT

RESET

12 MHz crystal oscillator input.

12 MHz crystal oscillator output.

If the reset input is HIGH for at least 3 machine cycles (36 oscillator periods)

while the oscillator is running, the device is reset; this pin should be

connected to V_DDMvia a 2.2 µF capacitor.

V_DDM

44

45

46

47

48

49

50

51

52

62

63

64

60

61

65

66

67

68

+5 V microcontroller power supply.

P1.0/INT1

P1.1/T0

P1.2/INT0

P1.3/INT1

P1.6/SCL

P1.7/SDA

P1.4

Port 1: 8-bit open-drain bidirectional port with alternate functions.

P1.0/INT1 is external interrupt 1 which can be triggered on the rising and

falling edge of the pulse.

P1.1/T0 is the counter/timer 0.

P1.2/INT0 is external interrupt 0.

P1.3/T1 is the counter/timer 1.

P1.6/SCL is the serial clock input for the I²C-bus.

P1.5

P1.7/SDA is the serial data port for the I²C-bus.

Positive reference voltage for software driven ADC.

Negative reference voltage for software driven ADC.

Read control signal to external Data Memory.

Write control signal to external Data Memory.

Enable signal for external Program Memory.

External latch enable signal; active HIGH.

REF+

REF−

RD

−

50

19

10

11

17

18

13

WR

PSEN

ALE

EA

Control signal used to select external (LOW) or internal (HIGH) Program

Memory.

AD0 to AD7

A8 to A15

−

69 to 76 Address lines A0 to A7 multiplexed with data lines D0 to D7.

55 to 52, Address lines A8 to A15.

35 to 32

1997 Jul 07

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Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

7

FUNCTIONAL DESCRIPTION

Microcontroller

7.3

Additional features

The following features are provided in addition to the

standard 80C51 features.

7.1

The functionality of the microcontroller used in this family

is described here with reference to the industry-standard

80C51 microcontroller. A full description of its functionality

can be found in the “80C51-Based 8-Bit Microcontrollers;

Data Handbook IC20”. Using the 80C51 as a reference,

the changes made to this family fall into two categories:

7.3.1

INTERRUPTS

The external INT1 interrupt is modified to generate an

interrupt on both the rising and falling edges of the INT1

pin, when EX1 bit is set. This facility allows for software

pulse width measurement for handling of a remote control.

• Features not supported by the SAA529x, SAA529xA or

SAA549x devices

7.3.2

BIT LEVEL I²C-BUS INTERFACE

• Features found on the SAA529x, SAA529xA or

SAA549x devices but not supported by the 80C51.

For reasons of compatibility with SAA5290, the SAA5291,

SAA5291A and SAA5491 contain a bit level serial I/O

which supports the I²C-bus. P1.6/SCL and P1.7/SDA are

the serial I/O pins. These two pins meet the I²C-bus

specification “The I²C-bus and how to use it (including

specifications)” concerning the input levels and output

drive capability. Consequently, these two pins have an

open-drain output configuration. All the four following

modes of the I²C-bus are supported.

7.2

80C51 features not supported

7.2.1

INTERRUPT PRIORITY

The IP SFR is not implemented and all interrupts are

treated with the same priority level. The normal

prioritisation of interrupts is maintained within the level.

Table 2 Interrupts and vectors address

• Master transmitter

• Master receiver

• Slave transmitter

• Slave receiver.

INTERRUPT SOURCE

VECTOR ADDRESS

Reset

000H

003H

00BH

013H

01BH

02BH

053H

External INT0

Timer 0

Three SFRs support the function of the bit-level I²C-bus

hardware: S1INT, S1BIT and S1SCS and are enabled by

setting register bit TXT8.I²C SELECT to logic 0.

External INT1

Timer 1

Byte I²C-bus

Bit I²C-bus; note 1

7.3.3

BYTE LEVEL I²C-BUS INTERFACE

The byte level serial I/O supports the I²C-bus protocol.

P1.6/SCL and P1.7/SDA are the serial I/O pins. These two

pins meet the I²C-bus specification concerning the input

levels and output drive capability. Consequently, these two

pins have an open-drain output configuration.

Note

1. SAA5290, SAA5291, SAA5291A and SAA5491 only.

7.2.2

OFF-CHIP MEMORY

The byte level I²C-bus serial port is identical to the I²C-bus

serial port on the 8xC552. The operation of the subsystem

is described in detail in the 8xC552 data sheet found in

“80C51-Based 8-Bit Microcontrollers; Data Handbook

IC20”.

The SDIP52 version does not support the use of off-chip

program memory or off-chip data memory.

7.2.3

IDLE AND POWER-DOWN MODES

As Idle and Power-down modes are not supported, their

respective bits in PCON are not available.

Four SFRs support the function of the byte level I²C-bus

hardware, they are S1CON, S1STA, S1DAT and S1ADR

and are enabled by setting register bit TXT8.I²C SELECT

to logic 1.

7.2.4

UART FUNCTION

The 80C51 UART is not available. As a consequence the

SCON and SBUF SFRs are removed and the ES bit in the

IE SFR is unavailable.

7.3.4

LED SUPPORT

Port pins P0.5 and P0.6 have a 10 mA current sinking

capability to enable LEDs to be driven directly.

1997 Jul 07

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Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

7.3.5

6-BIT PWM DACS

Eight 6-bit DACs are available to allow direct control of analog parts of the television.

Each low resolution 6-bit DAC is controlled by its associated Special Function Register (PWM0 to PWM7). The PWM

outputs are alternative functions of Port 2 and Port 3.4. The PWE bit in the SFR for the port corresponding to the PWM

should be set to logic 1 for correct operation of the PWM, e.g. if PWM0 is to be used, P2.1 should be set to logic 1 setting

the port pin to high-impedance.

7.3.5.1

Pulse Width Modulator Registers (PWM0 to PWM7)

Table 3 Pulse Width Modulator Registers (see Table 10 for addresses)

7

6

5

4

3

2

1

0

PWE

−

PV5

PV4

PV3

PV2

PV1

PV0

Table 4 Description of PWMn bits (n = 0 to 7)

BIT

SYMBOL

DESCRIPTION

7

PWE

If PWE is set to a logic 1, the corresponding PWM is active and controls its assigned

port pin. If PWE is set to a logic 0, the port pin is controlled by the corresponding bit in

the port SFR.

6

5

4

3

2

1

0

−

Not used.

PV5

PV4

PV3

PV2

PV1

PV0

The output of the PWM is a pulse of period 21.33 µs with a pulse HIGH time determined

by the binary value of these 6-bits multiplied by 0.33 µs. PV5 is the most significant bit.

1997 Jul 07

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Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

in the 6-bit PWMs. The 7 least significant bits, TDACL.TD6

to TDACL.TD0 (LSB), extend certain pulses by a further

0.33 µs, e.g. if the 7 least significant bits are given the

value 01H, then 1 in 128 cycles is extended. If the 7 least

significant bits are given the value 02H, then

7.3.6

14-BIT PWM DAC

One 14-bit DAC is available to allow direct control of

analog sections of the television. The 14-bit PWM is

controlled using Special Function Registers TDACL and

TDACH.

2 in 128 cycles is extended, and so forth.

The output of the TPWM is a pulse of period 42.66 µs. The

7 most significant bits, TDACH.TD13

(MSB) to TDACH.TD8 and TDACL.TD7, alter the pulse

width between 0 and 42.33 µs, in much the same way as

The TPWM will not start to output a new value until after

writing a value to TDACH. Therefore, if the value is to be

changed, TDACL should be written to before TDACH.

7.3.6.1

TPWM High Byte Register (TDACH)

Table 5 TPWM High Byte Register (SFR address D3H)

7

6

5

4

3

2

1

0

PWE

−

TD13

TD12

TD11

TD10

TD9

TD8

Table 6 Description of TDACH bits

BIT

SYMBOL

DESCRIPTION

7

PWE

If PWE is set to a logic 1, the TPWM is active and controls port line P2.0. If PWE is set

to a logic 0, the port pin is controlled by the corresponding bit in the port SFR.

6

5

4

3

2

1

0

−

Not used.

TD13

TD12

TD11

TD10

TD9

These 6-bits along with bit TD7 in the TDACL register control the pulse width period.

TD13 is the most signiﬁcant bit.

TD8

7.3.6.2

TPWM Low Byte Register (TDACL)

Table 7 TPWM Low Byte Register (SFR address D2H)

7

6

5

4

3

2

1

0

TD7

TD6

TD5

TD4

TD3

TD2

TD1

TD0

Table 8 Description of TDACL bits

BIT

SYMBOL

DESCRIPTION

7

TD7

This bit is used with bits TD13 to TD8 in the TDACH register to control the pulse width

period.

6 to 0

TD6 to TD0 These 7-bits extend certain pulses by a further 0.33 µs.

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Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

must be performed at least 1 instruction cycle before the

setting of SAD.ST to ensure comparison is made using the

correct SAD.SAD7 to SAD.SAD4 value.

7.3.7

SOFTWARE ADC

Up to 4 successive approximation ADCs can be

implemented in software by making use of the on-chip 8-bit

DAC and multiplexed voltage comparator. The software

ADC uses 4 analog inputs which are multiplexed with

P3.0 to P3.3.

The output of the comparator is SAD.VHI, and is valid after

1 instruction cycle following the setting of SAD.ST to a

logic 1.

Table 9 ADC input channel selection

CH1

CH0

INPUT PIN

0

1

0

1

0

1

P3.3/ADC3

P3.0/ADC0

P3.1/ADC1

P3.2/ADC2

handbook, halfpage

P3.0

P3.1

P3.2

P3.3

ST

C1

1D

VH1

MULTIPLEXER

CH1, CH0

8-BIT DAC

The control of the ADC is achieved using the Special

Function Registers SAD and SADB.

REF−

REF+

SAD7 to SAD0

MGL115

SAD.CH1 and SAD.CH0 select one of the four inputs to

pass to the comparator. The other comparator input

comes from the DAC, whose value is set by SAD.SAD7

(MSB) to SAD.SAD4 and SADB.SAD3 to SADB.SAD0

(LSB). The setting of the value SAD.SAD7 to SAD.SAD4

Fig.4 SAD block diagram.

1997 Jul 07

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Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

7.4.2

SPECIAL FUNCTION REGISTERS BIT DESCRIPTIONS

Table 11 SFRs bit description

REGISTER

FUNCTION

Interrupt Enable Register (IE)

EA

disable all interrupts (logic 0) or use individual interrupt enable bits (logic 1)

bit I²C-bus interrupt enable (logic 1)

byte I²C-bus interrupt enable (logic 1)

ES1

ES2

ET1

EX1

ET0

EX0

enable timer 1 overﬂow interrupt (logic 1)

enable external interrupt 1 (logic 1)

enable timer 0 overﬂow interrupt (logic 1)

enable external interrupt 0 (logic 1)

Power Control Register (PCON)

ARD

AUX-RAM disable bit. Disables the 512 bytes of internal AUX-RAM (logic 1);

all MOVX-instructions access the external data memory

GF1

GF0

general purpose ﬂag 1

general purpose ﬂag 0

Program Status Word (PSW)

CY

carry ﬂag

AC

auxiliary carry ﬂag

ﬂag 0

F0

RS1,RS0

register bank select control bits

overﬂow ﬂag

OV

P

parity ﬂag

6-bit Pulse Width Modulator Control Registers (PWM0 to PWM7)

PWE

activate this PWM and take control of respective port pin (logic 1)

binary value sets high time of PWM output

PV5 to PV0

Serial Interface Slave Address Register (S1ADR); note 1

ADR6 to ADR0

GC

I²C-bus slave address to which the device will respond

enables response to the I²C-bus general call address

Serial Interface Control Register (S1CON); note 1

CR2 to CR0

ENSI

STA

clock rate bits

I²C-bus interface enable

start condition ﬂag

stop condition ﬂag

interrupt ﬂag

STO

SI

AA

assert acknowledge ﬂag

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Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

REGISTER

FUNCTION

Serial Interface Data Register (S1DAT); note 1

DAT7 to DAT0

Serial Interface Status Register (S1STA) - READ only; note 1

STAT4 to STAT0

I²C-bus interface status

Serial Interface Data Register (S1BIT) - READ; note 2

SDI

I²C-bus data bit input

Serial Interface Data Register (S1BIT) - WRITE; note 2

SDO

I²C-bus data bit output

Serial Interface Interrupt Register (S1INT); note 2

SI

I²C-bus interrupt ﬂag

Serial Interface Control Register (S1SCS) - READ; note 2

I²C-bus data

SDI

serial data input at SDA

serial clock input at SCL

clock LOW-to-HIGH transition ﬂag

bus busy ﬂag

SCI

CLH

BB

RBF

WBF

STR

ENS

read bit ﬁnished ﬂag

write bit ﬁnished ﬂag

clock stretching enable (logic 1)

enable serial I/O (logic 1)

Serial Interface Control Register (S1SCS) - WRITE; note 2

SDO

SCO

CLH

STR

ENS

serial data output at SDA

serial clock output at SCL

clock LOW-to-HIGH transition ﬂag

clock stretching enable (logic 1)

enable serial I/O (logic 1)

Software ADC Control Register (SAD)

VHI

comparator output indicating that analog input voltage greater than DAC voltage (logic 1)

ADC input channel selection bits; see Table 11

CH1 and CH0

ST

initiate voltage comparison (logic 1); this bit is automatically reset to logic 0

4 MSB’s of DAC input value

SAD7 to SAD4

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Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

REGISTER

FUNCTION

Software ADC Control Register (SADB)

SAD3 to SAD0

4 LSB’s of DAC input value

Timer/Counter Control Register (TCON)

TF1

TR1

TF0

TR0

IE1

timer 1 overﬂow ﬂag

timer 1 run control bit

timer 0 overﬂow ﬂag

timer 0 run control bit

interrupt 1 edge ﬂag

interrupt 1 type control bit

interrupt 0 edge ﬂag

interrupt 0 type control bit

IT1

IE0

IT0

14-bit PWM MSB Register (TDACH)

PWE

activate this 14-bit PWM and take over port pin (logic 1)

6 MSBs of 14-bit number to be output by the 14-bit PWM

TD13 to TD8

14-bit PWM LSB Register (TDACL)

TD7 to TD0

8 LSBs of 14-bit number to be output by the 14-bit PWM

Timer 0 High byte (TH0)

TH07 to TH00

8 MSBs of Timer 0 16-bit counter

Timer 1 High byte (TH1)

TH17 to TH10

8 MSBs of Timer 1 16-bit counter

Timer 0 Low byte (TL0)

TL07 to TL00

8 LSBs of Timer 0 16-bit counter

Timer 1 Low byte (TL1)

TL17 to TL10

8 LSBs of Timer 1 16-bit counter

Timer/Counter Mode Control Register (TMOD)

GATE

C/T

gating control

counter or timer selector

mode control bits

M1, M0

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Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

REGISTER

FUNCTION

Teletext Register 0 (TXT0) - WRITE only

X24 POSN

store packet 24 in extension packet memory (logic 0) or page memory (logic 1)

display X24 from page memory (logic 0) or extension packet memory (logic 1)

FRAME output switched off automatically if any video displayed (logic 1)

disable writing of rolling headers and time into memory (logic 1)

DISPLAY X24

AUTO FRAME

DISABLE HDR

ROLL

DISPLAY STATUS

ROW ONLY

display row 24 only (logic 1)

DISABLE FRAME

VPS ON

FRAME output always LOW (logic 1)

enable capture of VPS data (logic 1)

INV ON⁽³⁾

enable capture of inventory page in block 8 (logic 1)

Teletext Register 1 (TXT1) - WRITE only

EXT PKT OFF⁽³⁾

8-BIT

disable decoding of extension packets (logic 1)

data in packets 0 to 24 written into memory without error checking (logic 1)

prevent teletext acquisition section writing to memory (logic 1)

ACQ OFF

X26 OFF

disable automatic processing of packet 26 data (logic 1)

FULL FIELD

FIELD POLARITY

H POLARITY

V POLARITY

decode teletext on VBI lines only (logic 0) or decode teletext on any line (logic 1)

VSYNC in ﬁrst half of the line (logic 0) or second half of the line (logic 1) at start of even ﬁeld

HSYNC input positive-going (logic 0) or negative-going (logic 1)

VSYNC input positive-going (logic 0) or negative-going (logic 1)

Teletext Register 2 (TXT2) - WRITE only

REQ3 to REQ0⁽³⁾

SC2 to SC0

selects which page is modiﬁed by TXT3 page request data

start column at which page request data written to TXT3, page request data is placed

Teletext Register 3 (TXT3) - WRITE only

PRD4 to PRD0 page request data

Teletext Register 4 (TXT4) - WRITE only

OSD BANK

ENABLE⁽⁴⁾

bank switching of OSD enabled (logic 1)

QUAD WIDTH

ENABLE⁽⁴⁾

enable quad width characters (logic 1)

EAST/ WEST

western languages selected (logic 0) or Eastern languages selected (logic 1)

disable display of double height teletext control codes (logic 1) in OSD boxes

DISABLE DBL

HGHT

B MESH ENABLE

C MESH ENABLE

TRANS ENABLE

enable meshing of area with black background (logic 1)

enable meshing of area with other background colours (logic 1)

set black background to transparent i.e. video is displayed (logic 1)

SHADOW ENABLE enable south-east shadowing (logic 1)

1997 Jul 07

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Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

REGISTER

FUNCTION

Teletext Register 5 (TXT5) - WRITE only

BKGND OUT

BKGND IN

COR OUT

COR IN

background colour displayed outside teletext boxes (logic 1)

background colour displayed inside teletext boxes (logic 1)

COR output active outside teletext boxes (logic 1)

COR output active inside teletext boxes (logic 1)

text displayed outside teletext boxes (logic 1)

TEXT OUT

TEXT IN

text displayed inside teletext boxes (logic 1)

PICTURE ON OUT video picture displayed outside teletext boxes (logic 1)

PICTURE ON IN video picture displayed inside teletext boxes (logic 1)

Teletext Register 6 (TXT6) - WRITE only

See TXT5

this register has the same meaning as TXT5 but is only invoked if either newsﬂash (C5) or

subtitle (C6) bit in row 25 of the basic page memory is set

Teletext Register 7 (TXT7) - WRITE only

STATUS ROW TOP display row 24 below (logic 0) or above (logic 1) teletext page

CURSOR ON

REVEAL

display cursor at location pointed to by TXT9 and TXT10 (logic 1)

display characters in areas with the conceal attribute set (logic 1)

display rows 0 to 11 (logic 0) or 12 to 23 (logic 1) when the double height bit is set

display each character as twice normal height (logic 1)

enable teletext boxes in memory row 24 (logic 1)

TOP/BOTTOM

DOUBLE HEIGHT

BOX ON 24

BOX ON 1-23

BOX ON 0

enable teletext boxes in memory rows 1 to 23 (logic 1)

enable teletext boxes in memory row 0 (logic 1)

Teletext Register 8 (TXT8)

I²C SELECT⁽²⁾

IDS ENABLE⁽²⁾

select bit I²C-bus (logic 0) or byte I²C-bus (logic 1)

capture teletext Independent Date Services (logic 1)

disable special treatment of Spanish packet 26 decoding

DISABLE

SPANISH⁽²⁾

PKT 26 RECEIVED set to logic 1 when packet 26 teletext data processed

WSS RECEIVED⁽⁵⁾set to logic 1 when wide screen signalling data received

WSS ON⁽⁵⁾

enable acquisition of wide screen signalling data

CVBS0/CVBS1

select CVBS0 (logic 0) or CVBS1 (logic 1) input to the device

Teletext Register 9 (TXT9) - WRITE only

CURSOR FREEZE locks current cursor position (logic 1)

CLEAR MEMORY

A0

write 20H into every location in teletext memory (logic 1)

TXT11 accesses the basic page memory, selected by TXT15 on the 10 page device, (logic 0)

or extension packet memory (logic 1)

R4 to R0

memory row to be accessed by TXT11

1997 Jul 07

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Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

REGISTER

FUNCTION

Teletext Register 10 (TXT10) - WRITE only

C5 to C0

memory column to be accessed by TXT11

Teletext Register 11 (TXT11)

D7 to D0

data byte written to, or read from teletext memory

Teletext Register 12 (TXT12) - READ only

625/525 SYNC

a 625-line CVBS signal (logic 0), or a 525-line CVBS signal (logic 1) is being input

ROM VER R4 to R0 mask programmable identiﬁcation for character set

TXT ON

power has been applied to the teletext hardware (logic 1)

CVBS input can be locked on by the teletext decoder (logic 1)

VIDEO SIGNAL

QUALITY

Teletext Register 13 (TXT13)

VPS RECEIVED

PAGE CLEARING

525 DISPLAY

525 TEXT

set to logic 1 when VPS data is received

set when software requested page clear in progress

set to logic 1 when 525-line syncs are driving the display

set to logic 1 when 525-line teletext is received

625 TEXT

set to logic 1 when 625-line teletext is received

PKT 8/30

set to logic 1 when packet 8/30 is detected

FASTEXT

set to logic 1 when packet X27/0 is detected

TIB

text interface busy; logic 1 indicates that TXT registers 0 to 16 cannot currently be accessed

Teletext Register 14 (TXT 14) - WRITE only; note 3

PAGE3 to PAGE0 selects which page to display

Teletext Register 15 (TXT15) - WRITE only; note 3

BLOCK3 to BLOCK0 selects which memory block accessed by TXT9, 10 and 11

Teletext Register 16 (TXT16) - WRITE only

Y2 to Y0

X1 to X0

sets vertical position of display area

sets horizontal position of display area

Teletext Register 17 (TXT17) - Write only

FORCE ACQ0,1

FORCE 625

force acquisition mode

force display to 625-line mode

force display to 525-line mode

FORCE 525

SCREEN COL 2 to 0 deﬁnes colour displayed instead of TV picture and black background

1997 Jul 07

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Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

REGISTER

FUNCTION

Wide Screen Signalling Register 1 (WSS1) - READ only; note 5

WSS 0-3 ERROR

WSS3 to WSS0

error ﬂag for bits WSS0 to WSS3

signalling bits to deﬁne aspect ratio (group 1)

Wide Screen Signalling Register 2 (WSS2) - READ only; note 5

WSS 4-7 ERROR

WSS7 to WSS4

error ﬂag for bits WSS4 to WSS7

signalling bits to deﬁne enhanced services (group 2)

Wide Screen Signalling Register 3 (WSS3) - READ only; note 5

WSS11-13 ERROR error ﬂag for bits WSS11 to WSS13

WSS13 to WSS11

WSS8-10 ERROR

WSS10 to WSS8

signalling bits to deﬁne reserved elements (group 4)

error ﬂag for bits WSS8 to WSS10

signalling bits to deﬁne subtitles (group 3)

Colour Look-Up Table Register (CLUT) - WRITE only; note 4

CLUT ENABLE

CLUT ADDRESS

B1

enable the colour look-up table (logic 1)

load CLUT address (logic 1) or CLUT data (logic 0)

most signiﬁcant BLUE component data

least signiﬁcant BLUE component data

B0

G1 or ENTRY3

G0 or ENTRY2

R1 or ENTRY1

R0 or ENTRY0

most signiﬁcant GREEN component data or most signiﬁcant bit of CLUT address

least signiﬁcant GREEN component data or CLUT address

most signiﬁcant RED component data or CLUT address

least signiﬁcant RED component data or least signiﬁcant bit of CLUT address

Notes

1. Available on SAA5296, SAA5296A, SAA5297, SAA5297A, SAA5496, SAA5497 permanently and SAA5290,

SAA5291, SAA5291A, SAA5491 when TXT8.I²C SELECT set to logic 1.

2. Available on SAA5290, SAA5291, SAA5291A and SAA5491.

3. Available on SAA5296, SAA5296A, SAA5297, SAA5297A, SAA5496, SAA5497.

4. Available on SAA5491, SAA5496, SAA5497.

5. Available on SAA5291A, SAA5296A, SAA5297A, SAA5491, SAA5496, SAA5497.

1997 Jul 07

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Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

When the HOLD bit is set to a logic 0 the teletext decoder

will not recognise any page as having the correct page

number and no pages will be captured. In addition to

providing the user requested hold function this bit should

be used to prevent the inadvertent capture of an unwanted

page when a new page request is being made. For

example, if the previous page request was for page 100

and this was being changed to page 234, it would be

possible to capture page 200 if this arrived after only the

requested magazine number had been changed.

8

TELETEXT DECODER

Data slicer

8.1

The data slicer extracts the digital teletext data from the

incoming analog waveform. This is performed by sampling

the CVBS waveform and processing the samples to

extract the teletext data and clock.

8.2

Acquisition timing

The acquisition timing is generated from a logic level

positive-going composite sync signal VCS. This signal is

generated by a sync separator circuit which adaptively

slices the sync pulses. The acquisition clocking and timing

are locked to the VCS signal using a digital

The E1 and E0 bits control the error checking which should

be carried out on packets 1 to 23 when the page being

requested is captured. This is described in more detail in

Section 8.5.

phase-locked-loop. The phase error in the acquisition

phase-locked-loop is detected by a signal quality circuit

which disables acquisition if poor signal quality is detected.

For the ten page device, each packet can only be written

into one place in the teletext RAM so if a page matches

more than one of the page requests the data is written into

the area of memory corresponding to the lowest numbered

matching page request.

8.3

Teletext acquisition

This family is capable of acquiring 625-line and 525-line

World System Teletext see “World System Teletext and

Data Broadcasting System”. Teletext pages are identified

by seven numbers: magazine (page hundreds), page tens,

page units, hours tens, hours units, minutes tens and

minutes units. The last four digits, hours and minutes, are

known as the subcode, and were originally intended to be

time related, hence their names. A page is requested by

writing a series of bytes into the TXT3 SFR which

At power-up each page request defaults to any page, hold

on and error check Mode 0.

Table 12 The contents of the Page request RAM

START

COLUMN

PRD4

PRD3 PRD2 PRD1 PRD0

0

DO CARE HOLD MAG2 MAG1 MAG0

Magazine

corresponds to the number of the page required.

1

2

3

DO CARE PT3

Page Tens

PT2

PU2

X

PT1

PU1

HT1

PT0

PU0

HT0

The bytes written into TXT3 are put into a small RAM with

an auto-incrementing address. The start address for the

RAM is set using the TXT2 SFR. Table 12 shows the

contents of the page request RAM.

DO CARE PU3

Page Units

DO CARE

Hours

X

TXT2.REQ0 to TXT2.REQ3 determine which of the

10 page requests is being modified for a 10 page teletext

decoder. If TXT2.REQ is given a value greater than 09H,

then data written into TXT3 is ignored.

Tens

4

5

6

7

DO CARE HU3

Hours

Units

HU2

MT2

MU2

X

HU1

MT1

MU1

E1

HU0

MT0

MU0

E0

Up to 10 pages of teletext can be acquired on the 10 page

device, when TXT1.EXT PKT OFF is set to logic 1, and up

to 9 pages can be acquired when this bit is set to logic 0.

DO CARE

Minutes

Tens

X

If the ‘DO CARE’ bit for part of the page number is set to a

logic 0 then that part of the page number is ignored when

the teletext decoder is deciding whether a page being

received off air should be stored or not. For example, if the

‘DO CARE’ bits for the 4 subcode digits are all set to

logic 0s then every subcode version of the page will be

captured.

DO CARE MU3

Minutes

Units

X

1997 Jul 07

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Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

The last 8 characters of the page header are used to

provide a time display and are always extracted from every

valid page header as it arrives and written into the display

block.

Table 13 Notation used in Table 12

MNEMONIC

DESCRIPTION

MAG

PT

Magazine

Page Tens

The TXT0.DISABLE HEADER ROLL bit prevents any data

being written into row 0 of the page memory except when

a page is acquired off air i.e. rolling headers and time are

not written into the memory. The TXT1.ACQ OFF bit

prevents any data being written into the memory by the

teletext acquisition section.

PU

HT

HU

MT

MU

E

Page Units

Hours Tens

Hours Units

Minutes Tens

Minutes Units

Error check mode

When a parallel magazine mode transmission is being

received only headers in the magazine of the page

requested are considered valid for the purposes of rolling

headers and time. Only one magazine is used even if don’t

care magazine is requested. When a serial magazine

mode transmission is being received all page headers are

considered to be valid.

8.4

Rolling headers and time

When a new page has been requested it is conventional

for the decoder to turn the header row of the display green

and to display each page header as it arrives until the

correct page has been found.

8.5

Error checking

When a page request is changed (i.e. when the TXT3 SFR

is written to) a flag (PBLF) is written into bit 5, column 9,

row 25 of the corresponding block of the page memory.

The state of the flag for each block is updated every TV

line, if it is set for the current display block, the acquisition

section writes all valid page headers which arrive into the

display block and automatically writes an alphanumeric

green character into column 7 of row 0 of the display block

every TV line.

Before teletext packets are written into the page memory

they are error checked. The error checking carried out

depends on the packet number, the byte number, the error

check mode bits in the page request data and the TXT1.8

BIT bit.

If an uncorrectable error occurs in one of the Hamming

checked addressing and control bytes in the page header

or in the Hamming checked bytes in packet 8/30, bit 4 of

the byte written into the memory is set, to act as an error

flag to the software. If uncorrectable errors are detected in

any other Hamming checked data the byte is not written

into the memory.

When a requested page header is acquired for the first

time, rows 1 to 23 of the relevant memory block are

cleared to space, i.e. have 20H written into every column,

before the rest of the page arrives. Row 24 is also cleared

if the TXT0.X24 POSN bit is set. If the TXT1.EXT PKT OFF

bit is set the extension packets corresponding to the page

are also cleared.

1997 Jul 07

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Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

Packet X/0

handbook, full pagewidth

'8-bit' bit = 0

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

'8-bit' bit = 1

0

1

2

3

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

Packet X/1-23

'8-bit' bit = 0, error check mode = 0

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

'8-bit' bit = 0, error check mode = 1

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

'8-bit' bit = 0, error check mode = 2

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

'8-bit' bit = 0, error check mode = 3

0

1 2 3 4 5 6 7 8

0

1 2 3 4 5 6 7 8

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

'8-bit' bit = 1

0

1 2 3

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

Packet X/24

'8-bit' bit = 0

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

'8-bit' bit = 1

0

1

2

3

Packet X/27/0

0

1

2

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

Packet 8/30/0,1

0

1 2

Packet 8/30/2,3,4-15

0

1

2

3

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

MGK465

8-bit

data

odd parity

checked

8/4 Hamming

checked

Fig.5 Error checking.

1997 Jul 07

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Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

The interrupted sequence (C9) bit is automatically dealt

with by the acquisition section so that rolling headers do

not contain discontinuities in the page number sequence.

8.6

Memory organisation of SAA5296/7,

SAA5296/7A and SAA5496/7

The teletext memory is divided into 10 blocks. Normally,

when the TXT1.EXT PKT OFF bit is logic 0, each of blocks

0 to 8 contains a teletext page arranged in the same way

as the basic page memory (see Fig.6) of the page device

and block 9 contains extension packets (see Fig.7).

The magazine serial (C11) bit indicates whether the

transmission is a serial or a parallel magazine

transmission. This affects the way the acquisition section

operates and is dealt with automatically.

The newsflash (C5), subtitle (C6), suppress header (C7),

inhibit display (C10) and language control (C12 to 14) bits

are dealt with automatically by the display section,

described below.

When the TXT1.EXT PKT OFF bit is logic 1, no extension

packets are captured and block 9 of the memory is used to

store another page.

The number of the memory block into which a page is

written corresponds to the page request number which

resulted in the capture of the page.

The update (C8) bit has no effect on the hardware. The

remaining 32 bytes of the page header are parity checked

and written into columns 8 to 39 of row 0. Bytes which

pass the parity check have the MSB set to a logic 0 and

are written into the page memory. Bytes with parity errors

are not written into the memory.

Packet 0, the page header, is split into 2 parts when it is

written into the text memory. The first 8 bytes of the header

contain control and addressing information. They are

Hamming decoded and written into columns 0 to 7 of

row 25 (see Table 15). Row 25 also contains the

magazine number of the acquired page and the PBLF flag

but the last 14 bytes are unused and may be used by the

software, if necessary. The Hamming error flags are set if

the on-board 8/4 Hamming checker detects that there has

been an uncorrectable (2 bit) error in the associated byte.

Table 14 Notation used in Table 15

MNEMONIC

DESCRIPTION

Magazine

MAG

PT

Page Tens

PU

Page Units

Hours Tens

Hours Units

Minutes Tens

Minutes Units

It is possible for the page to still be acquired if some of the

page address information contains uncorrectable errors if

that part of the page request was a ‘don’t care’. There is no

error flag for the magazine number as an uncorrectable

error in this information prevents the page being acquired.

HT

HU

MT

MU

Table 15 The data in row 25 of the basic page memory

COL

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

0

−

0

−

0

Hamming error

FOUND

PU3

PT3

MU3

C4

PU2

PT2

MU2

MT2

HU2

C5

PU1

PT1

MU1

MT1

HU1

HT1

C8

PU0

PT0

MU0

MT0

HU0

HT0

C7

1

0

2

0

3

0

4

0

HU3

C6

5

0

6

0

C10

C14

0

C9

7

0

C13

MAG2

0

C12

MAG1

0

C11

MAG0

0

8

9

PBLF

−

0

10 to 23

unused

−

1997 Jul 07

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Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

Basic Page Blocks (0 to 8/9)

handbook, full pagewidth

0

6

7

8

39

Row 0 OSD only

Packet X/0

Packet X/1

Packet X/2

Packet X/3

Packet X/4

Packet X/5

Packet X/6

Packet X/7

Packet X/8

Packet X/9

Packet X/10

Packet X/11

Packet X/12

Packet X/13

Packet X/14

Packet X/15

Packet X/16

Packet X/17

Packet X/18

Packet X/19

Packet X/20

Packet X/21

Packet X/22

Packet X/23

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

(1)

Packet X/24

(2)

25

Control Data

VPS Data

MGK466

0

9

23

(1) If ‘X24 Posn’ bit = 1.

(2) VPS data block 9, unused in blocks 0 to 8.

Fig.6 Packet storage locations.

1997 Jul 07

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Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

Extension Packet Block (9)

(1)

handbook, full pagewidth

Row

0

1

2

Packet X/24 for page in block 0

Packet X/27/0 for page in block 0

Packet 8/30/0.1

Packet 8/30/2.3

3

(1)

Packet X/24 for page in block 1

4

Packet X/27/0 for page in block 1

5

6

(1)

Packet X/24 for page in block 2

Packet X/27/0 for page in block 2

7

(1)

8

Packet X/24 for page in block 3

Packet X/27/0 for page in block 3

9

(1)

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

Packet X/24 for page in block 4

Packet X/27/0 for page in block 4

(1)

Packet X/24 for page in block 5

Packet X/27/0 for page in block 5

(1)

Packet X/24 for page in block 6

Packet X/27/0 for page in block 6

(1)

Packet X/24 for page in block 7

Packet X/27/0 for page in block 7

(1)

Packet X/24 for page in block 8

Packet X/27/0 for page in block 8

Packet 8/30/4-15

VPS Data

23

MGD163

0

9

(1) If ‘X24 Position’ bit = 0.

Fig.7 Extension packet storage locations.

1997 Jul 07

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Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

each page number, from 100 to 8FF, is represented by a

bit in the table.

8.7

Inventory page

If the TXT0.INV ON bit is a logic 1, memory block 8 is used

as an inventory page.The inventory page consists of two

tables: the Transmitted Page Table (TPT) and the Subtitle

Page Table (SPT).

The bit for a particular page in the TPT is set when a page

header is received for that page. The bit in the SPT is set

when a page header for the page is received which has the

‘subtitle’ page header control bit (C6) set.

In each table, every possible combination of the page tens

and units digit, 00H to FFH, is represented by a byte. Each

bit of these bytes corresponds to a magazine number so

Before the inventory page is enabled the software must

ensure that page request 8 is put on hold.

Bytes in the table

handbook, full pagewidth

column

0

8

16

24

32

39

row n

n + 1

n + 6

n + 7

Bytes in each byte

bit

7

0

6xx

5xx

4xx

3xx

2xx

1xx

8xx

7xx

MGD160

Fig.8 Table organisation.

1997 Jul 07

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Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

0

39

handbook, full pagewidth

Row 0

1

2

Transmitted

Pages

Table

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

Subtitle

Pages

Table

Unused

MGD165

0

23

Fig.9 Inventory page organisation.

1997 Jul 07

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Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

8.8

Memory Organisation of SAA5290, SAA5291, SAA5291A and SAA5491

Teletext packets each contain 40 bytes of data and one packet is stored in each row of the text memory, the row used

being dependent on the packet number.

Packet 0, the page header, is split into 2 parts when it is written into the text memory. The first 8 bytes of the header

contain control and addressing information. They are Hamming decoded and written into columns 0 to 7 of row 25.

Basic Page Block

0

handbook, full pagewidth

6

7

8

39

Row 0 OSD only

aw/ag

Packet X/0

Packet X/1

Packet X/2

Packet X/3

Packet X/4

Packet X/5

Packet X/6

Packet X/7

Packet X/8

Packet X/9

Packet X/10

Packet X/11

Packet X/12

Packet X/13

Packet X/14

Packet X/15

Packet X/16

Packet X/17

Packet X/18

Packet X/19

Packet X/20

Packet X/21

Packet X/22

Packet X/23

Packet X/24

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

(1)

23

25

Control Data

VPS Data

0

9

Extension Packet Memory

(2)

Row 0

Packet X/24

1

2

Packet X/27/0

Packet 8/30

MGK467

(1) If X24 Position bit = 1.

(2) If X24 Position bit = 0.

Fig.10 Packet storage locations.

1997 Jul 07

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Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

The TXT8.Pkt 26 received bit is set by the hardware

whenever a character is written into the page memory by

the packet 26 decoding hardware. The flag can be reset by

writing a logic 0 into the SFR bit.

8.9

Packet 26 processing

One of the uses of packet 26 is to transmit characters

which are not in the basic teletext character set. The family

automatically decodes packet 26 data and, if a character

corresponding to that being transmitted is available in the

character set, automatically writes the appropriate

character code into the correct location in the teletext

memory. This is not a full implementation of the packet 26

specification allowed for in level 2 teletext, and so is often

referred to as level 1.5.

8.10 VPS

When the TXT0. VPS ON bit is set, any VPS data present

on line 16, field 0 of the CVBS signal at the input of the

teletext decoder is error checked and stored in row 25,

block 0 for SAA5291, SAA5291A, SAA5491 and row 25,

block 9 for SAA5296/7, SAA5296/7A, SAA5496/7 of the

basic page memory. The device automatically detects

whether teletext or VPS is being transmitted on this line

and decodes the data appropriately.

By convention, the packets 26 for a page are transmitted

before the normal packets. To prevent the default

character data overwriting the packet 26 data the device

incorporates a mechanism which prevents packet 26 data

from being overwritten. On the SAA5291,SAA5291A and

SAA5491 devices this mechanism is disabled when the

Spanish national option is detected as the Spanish

transmission system sends even parity (i.e. incorrect)

characters in the basic page locations corresponding to

the characters sent via packet 26 and these will not

overwrite the packet 26 characters anyway. The special

treatment of Spanish national option is prevented if

TXT12.ROM VER R4 is logic 0 or if the TXT8.DISABLE

SPANISH is set.

Each VPS byte in the memory consists of 4 bi-phase

decoded data bits (bits 0 to 3), a bi-phase error flag (bit 4)

and three 0s (bits 5 to 7).

The TXT13.VPS Received bit is set by the hardware

whenever VPS data is acquired. The flag can be reset by

writing a logic 0 into the SFR bit. Full details of the VPS

system can be found in “Specification of the Domestic

Video Programme Delivery Control System (PDC); EBU

Tech. 3262-E”.

Packet 26 data is processed regardless of the

TXT1.EXT PKT OFF bit, but setting theTXT1.X26 OFF

disables packet 26 processing.

Table 16 VPS data storage

COLUMN

ROW

0 TO 9

10 TO 11 12 TO 13 14 TO 15 16 TO 17 18 TO 19 20 TO 21 22 TO 23

VPS

byte 11

VPS

byte 12

VPS

byte 13

VPS

byte 14

VPS

byte 15

VPS

byte 4

VPS

byte 5

Row 25 Teletext page header data

1997 Jul 07

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Philips Semiconductors

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Economy teletext and TV microcontrollers

SAA5x9x family

The first 8 data bytes of packet X/1/24 are used to extend

the Fastext prompt row to 40 characters. These characters

are written into whichever part of the memory the

packet 24 is being written into (determined by the ‘X24

Posn’ bit).

8.11 Wide Screen Signalling (SAA529xA and

SAA549x only)

The Wide Screen Signalling data transmitted on line 23

gives information on the aspect ratio and display position

of the transmitted picture, the position of subtitles and on

the camera/film mode. Some additional bits are reserved

for future use. A total of 14 data bits are transmitted.

Packets X/0/27/0 contain 5 Fastext page links and the link

control byte and are captured, Hamming checked and

stored by in the same way as are packets X/27/0 in

625-line text. Packets X/1/27/0 are not captured.

All of the available data bits transmitted by the Wide

Screen Signalling signal are captured by the appropriate

device in the family and stored in SFRs WSS1, WSS2 and

WSS3. The bits are stored as groups of related bits and an

error flag is provided for each group to indicate when a

transmission error has been detected in one or more of the

bits in the group.

Because there are only 2 magazine bits in 525-line text,

packets with the magazine bits all set to a logic 0 are

referred to as being in magazine 4. Therefore, the

broadcast service data packet is packet 4/30, rather than

packet 8/30. As in 625 line text, the first 20 bytes of packet

4/30 contain encoded data which is decoded in the same

way as that in packet 8/30. The last 12 bytes of the packet

contains half of the parity encoded status message.

Packet 4/0/30 contains the first half of the message and

packet 4/1/30 contains the second half. The last 4 bytes of

the message are not written into memory. The first

20 bytes of the each version of the packet are the same so

they are stored whenever either version of the packet is

acquired.

Wide screen signalling data is only acquired when the

TXT8.WSS ON bit is set.

The TXT8.WSS RECEIVED bit is set by the hardware

whenever wide screen signalling data is acquired. The flag

can be reset by writing a logic 0 into the SFR bit.

8.12 525-line world system teletext

As well as the 625-line teletext format described

previously, the family can acquire teletext in the 525-line

WST (World System Teletext) format.

In 525-line text each packet 26 only contains ten 24/18

Hamming encoded data triplets, rather than the 13 found

in 625-line text. The tabulation bit is used as an extra bit

(the MSB) of the designation code, allowing 32 packet 26s

to be transmitted for each page. The last byte of each

packet 26 is ignored.

The 525-line format is similar to the 625-line format but the

data rate is lower and there are less data bytes per packet

(32 rather than 40). There are still 40 characters per

display row so extra packets are sent each of which

contains the last 8 characters for four rows. These packets

can be identified by looking at the ‘tabulation bit’ (T), which

replaces one of the magazine bits in 525-line teletext.

When an ordinary packet with T = 1 is received, the

decoder puts the data into the four rows starting with that

corresponding to the packet number, but with the 2 LSB’s

set to logic 0. For example, a packet 9 with T = 1 (packet

X/1/9) contains data for rows 8, 9, 10 and 11. The error

checking carried out on data from packets with T = 1

depends on the setting of the TXT1. 8 BIT bit and the error

checking control bits in the page request data and is the

same as that applied to the data written into the same

memory location in the 625-line format.

The device automatically detects whether 525 or 625-line

teletext is being received by checking whether teletext

packets are being recognised, and switching to the other

system if they aren’t.

The TXT13.625 TXT bit is set if the device has decided,

using the algorithm above, that 625-line text is being

received. The TXT13.525 Text bit is set if the device has

decided that 525-line text is being received. If the device

has not decided which type of text is being received then

neither flag is set.

The ‘FORCE ACQ0’ and ‘FORCE ACQ1’ bits in TXT17

can be used to override the automatic detection and

selection mechanism; see Table 17.

The rolling time display (the last 8 characters in row 0) is

taken from any packets X/1/1, 2 or 3 received. In parallel

magazine mode only packets in the correct magazine are

used for rolling time. Packet number X/1/0 is ignored.

The tabulation bit is also used with extension packets.

1997 Jul 07

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Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

Table 17 Acquisition selection table

FORCE ACQ1

FORCE ACQ0

TIMING

TELETEXT STANDARD

0

1

0

1

0

1

automatic

525-line

625-line

automatic

525-line

625-line

525-line

handbook, full pagewidth

0

6

7

8

39

Row 0 OSD only aw/ag

Packet X/0/0

Packet X/0/1

Packet X/0/2

Packet X/0/3

Packet X/0/4

Packet X/0/5

Packet X/0/6

Packet X/0/7

Packet X/0/8

Packet X/0/9

Packet X/0/10

Packet X/0/11

Packet X/0/12

Packet X/0/13

Packet X/0/14

Packet X/0/15

Packet X/0/16

Packet X/0/17

Packet X/0/18

Packet X/0/19

Packet X/0/20

Packet X/0/21

Packet X/0/22

Packet X/0/23

Packet X/0/24

Rolling time

Packet X/1/1

1

2

3

4

Packet X/1/4

Packet X/1/8

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

Packet X/1/12

Packet X/1/16

Packet X/1/20

(1)

Packet X/1 /24

25

Control Data

MGK468

0

9

23

(1) If X24 Position bit = 1.

Fig.11 Ordinary packet storage locations, 525-line.

1997 Jul 07

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Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

This allows the device to be used with teletext

8.13 Fastext detection

transmissions occupying the entire TV channel and with

data extracted from different TV broadcast standards (e.g.:

MAC packet teletext).

When a packet 27, designation code 0 is detected,

whether or not it is acquired, the TXT13.FASTEXT bit is

set. If the device is receiving 525-line teletext, a packet

X/0/27/0 is required to set the flag. The flag can be reset

by writing a logic 0 into the SFR bit.

8.16 Independent data services (SAA5291,

SAA5291A, SAA5491 only)

When a packet 8/30 is detected, or a packet 4/30 when the

device is receiving a 525-line transmission, the TXT13.Pkt

8/30 is set. The flag can be reset by writing a logic 0 into

the SFR bit.

When the TXT8.IDS ENABLE bit is set, SAA5291

becomes a receiver for teletext ‘Independent Data

Services’. These services use teletext packet numbers 30

and 31 to transmit data from a central database to a large

number of distributed receivers.

8.14 Page clearing

Unlike normal teletext data, IDS data is not organised into

pages but into ‘data channels’.

When a page header is acquired for the first time after a

new page request or a page header is acquired with the

erase (C4) bit set the page memory is ‘cleared’ to spaces

before the rest of the page arrives.

There are 16 data channels, identified by the magazine

number and the LSB of the packet number (actually, the

second byte of the magazine and packet number group).

Data channel 0 is the familiar packet 8/30, used to transmit

broadcast related information.

When this occurs, the space code (20H) is written into

every location of rows 1 to 23 of the basic page memory,

row 1 of the extension packet memory and the row where

teletext packet 24 is written. This last row is either row 24

of the basic page memory, if the TXT0.X24 POSN bit is

set, or row 0 of the extension packet memory, if the bit is

not set. Page clearing takes place before the end of the TV

line in which the header arrived which initiated the page

clear. This means that the 1 field gap between the page

header and the rest of the page which is necessary for

many teletext decoders is not required.

The data channel to be captured by the device is selected

by writing to column 0 of the page request RAM.

Only IDS packets from the selected data channel are

captured and rows 0 to 23 of the basic page memory are

used to store the last 24 packets acquired. The first IDS

packet acquired after theTXT8.IDS ENABLE bit is set is

written into row 0, the next into row 1 and so on until 24

packets have been acquired. The internal packet counter

then rolls over and the 25th packet is written into row 0.

The hardware never initiates a page clear in IDS mode but

if the software initiates one the packet counter is reset to 0

after the memory is cleared.

The software can also initiate a page clear, by setting the

TXT9.CLEAR MEMORY bit. When it does so, every

location in the memory is cleared. The CLEAR MEMORY

bit is not latched so the software does not have to reset it

after it has been set.

The data bytes in the IDS packers are not error checked in

any way.

Only one page can be cleared in a TV line so if the

software requests a page clear it will be carried out on the

next TV line on which the hardware does not force the

page to be cleared. A flag, TXT13.PAGE CLEARING, is

provided to indicate that a software requested page clear

is being carried out. The flag is set when a logic 1 is written

into the TXT9.CLEAR MEMORY bit and is reset when the

page clear has been completed.

The software must keep track of which of the IDS packets

in the memory it has processed and detect newly arrived

packets. It can do this by writing a value which cannot be

produced by the 8/4 Hamming checker (such as FFH) into

column 0 of each row and detecting when it is over written.

The 24 packet buffer is sufficient to ensure that the device

will not be overwhelmed by IDS data sent in the vertical

blanking interval, but it may not be able to cope with full

channel IDS data.

At power-on and reset the whole of the page memory is

cleared and theTXT13.PAGE CLEARING bit will be set.

IDS data is dealt with in the same way for both the

525 and 625-line teletext standards.

8.15 Full channel operation

If the TXT1.FULL FIELD bit is set the device will acquire

data transmitted on any TV line, not just during the vertical

blanking interval.

1997 Jul 07

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Philips Semiconductors

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Economy teletext and TV microcontrollers

SAA5x9x family

Table 18 Page request RAM for IDS data

COL

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

0

X

Data Ch 3 Data Ch 2 Data Ch 1 Data Ch 0

1 to 7

X

9

THE DISPLAY

Introduction

9.4

National option characters

The meanings of some character codes between 20H and

7FH depend on the C12 to C14 language control bits from

the teletext page header.

9.1

The capabilities of the display are based on the

requirements of level 1 teletext, with some enhancements

for use with locally generated on screen displays.

The interpretation of the C12 to C14 language control bits

is dependent on the East/West bit.

The display consists of 25 rows each of 40 characters,

with the characters displayed being those from

rows 0 to 24 of the basic page memory. If the

9.5

The twist attribute

TXT7.STATUS ROW TOP bit is set row 24 is displayed at

the top of the screen, followed by row 0, but normally

memory rows are displayed in numerical order.

In many of the character sets, the ‘twist’ serial attribute

(code 1BH) can be used to switch to an alternate basic

character code table, e.g. to change from the Hebrew

alphabet to the Arabic alphabet on an Arab/Hebrew

device. For some national option languages the alternate

code table is the default, and a twist control character will

switch to the first code table.

The teletext memory stores 8 bit character codes which

correspond to a number of displayable characters and

control characters, which are normally displayed as

spaces. The character set of the device is described in

more detail below.

The display hardware on the devices allows one language

to invoke the alternate code table by default when the

East/West register bit is a logic 0 and another when the bit

is a logic 1. In all of the character sets defined so far, the

language which invokes the alternate code table is the

same for either setting of the East/West bit.

9.2

Character matrix

Each character is defined by a matrix 12 pixels wide and

10 pixels high. When displayed, each pixel is ¹⁄₁₂µs wide

and 1 TV line, in each field, high.

9.6

On Screen Display symbols

9.3

East/West selection

In the character sets character codes 80H to 9FH are OSD

symbols not addressed by the teletext decoding hardware.

An editor is available to allow these characters to be

redefined by the customer.

In common with their predecessors, these devices store

teletext pages as a series of 8 bit character codes which

are interpreted as either control codes (to change colour,

invoke flashing etc.) or displayable characters. When the

control characters are excluded, this gives an addressable

set of 212 characters at any given time.

The SAA549x allows another 32 OSD symbols. These are

selected using the ‘graphics’ serial attribute.

More characters than this were required to give the

language coverage required from the first version of the

device, so the TXT4.East/West bit was introduced to allow

the meanings of character codes D0H to FFH to be

changed, depending on where in Europe the device was to

be used.

9.7

Language group identiﬁcation

The devices have a readable register TXT12 which

contains a 5 bit identification code TXT12.ROM VER R4 to

TXT12.ROM VER R0 which is intended for use in

identifying which character set the device is using.

This bit is still used with the other language variants,

although the name East/West may not make much sense.

1997 Jul 07

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Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

colour to be changed to any colour with a single control

character and independently of the foreground colour. The

background colour is changed from the position of the

background colour control character.

9.8

525-line operation

When used with 525-line display syncs, the devices modify

their displays such that the bottom line is omitted from

each character cell. The character sets have been

designed to be readable under these circumstances and

anyone designing OSD symbols is advised to consider this

mode of operation.

Displayable characters between a ‘flash’ (08H) and a

‘steady’ (09H) control character will flash on and off.

Displayable characters between a ‘conceal display’ (18H)

character and an alphanumerics or graphics control

character are displayed as spaces, unless the

TXT7.REVEAL bit is set.

9.9

On Screen Display characters

Character codes 80H to 9FH are not addressed by the

hardware and can be redefined by the customer, as OSD

characters if necessary.

The ‘contiguous graphics’ (19H) and ‘separated graphics’

(1AH) characters control the way in which mosaic shapes

are displayed. The difference between the two is shown in

Fig.12.

The alternative character shapes in columns 8a and 9a

(SAA549x only) can be displayed when the ‘graphics’

serial attribute is set. This increases the number of

customer definable characters to 64.

Control characters encountered between a ‘hold graphics’

(1EH) control character and a ‘release graphics’ (1FH)

control character are displayed as the last character

displayed in graphics mode, rather than as spaces. From

the hold graphics character until the first character

displayed in graphics mode the held character is a space.

To ensure compatibility with devices only having 32 OSD

characters, the additional OSD characters are only

accessible when the TXT4.OSD BANK ENABLE bit is set.

If this bit is not set, the characters in columns 8 and 9 will

be displayed in both alphanumeric and graphics modes.

The ‘start box’ (0BH) and ‘end box’ (0AH) characters are

used to define teletext boxes. Two start box characters are

required to begin a teletext box, with the box starting

between the 2 characters. The box ends after an end box

character has been encountered. The display can be set

up so that different display modes are invoked inside and

outside teletext boxes e.g. text inside boxes but TV

outside. This is described in Section 9.13.

9.10 Control characters

Character codes 00H to 1FH, B0H to B7H and

BCH to BFH are interpreted as control characters which

can be used to change the colour of the characters, the

background colour, the size of characters, and various

other features. All control characters are normally

displayed as spaces.

The ‘normal size’ (0CH), ‘double height’ (0DH), ‘double

width’ (0EH) and ‘double size’ (0FH) control characters are

used to change the size of the characters displayed. If any

double height (or double size) characters are displayed on

a row the whole of the next row is displayed as spaces.

Double height display is not possible on either row 23 or

row 24.

The alphanumerical colour control characters

(00H to 07H) are used to change colour of the characters

displayed.

The graphics control characters (10H to 17H) change the

colour of the characters and switch the display into a mode

where the codes in columns 2, 3, 6 and 7 of the character

table (see the character table above) are displayed as the

block mosaic characters in columns 2a, 3a, 6a and 7a.

The display of mosaics is switched off using one of the

alphanumerics colour control characters.

The character in the position occupied by the right hand

half of a double width (or double size) character is ignored,

unless it is a control character in which case it takes effect

on the next character displayed. This allows double width

to be used to produce a display in which blank spaces do

not appear when character attributes are changed.

The ‘new background’ character (1DH) the background

colour of the display, sets the background colour equal to

the current foreground colour. The ‘black background’

character (1CH) changes the background colour to black

independently of the current foreground colour. The

background colour control characters in the upper half of

the code table (B0H to B7H) are additions to the normal

teletext control characters which allow the background

The size implying OSD (BCH to BFH) control characters

are not standard teletext control characters and have been

included in this device to allow OSD messages to be

generated with the minimum disruption to the teletext page

stored in the memory. These characters are described in

full later in this document.

1997 Jul 07

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Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

This is because if two consecutive size implying OSD

control characters are used, the first starts the OSD box

and the second finishes the OSD box, and therefore no

OSD box is defined.

handbook, halfpage

Quadruple width characters must not start in columns 37,

38 or 39 of the display since the whole of the character

cannot be displayed.

9.12 Page attributes

Row 25 of the basic page memory contains control data

from the page header of the page stored in the memory.

The bits which affect the display are the newsflash (C5),

subtitle (C6), suppress header (C7), inhibit display (C10)

and language control (C12 to 14) bits.

mosaics character 7FH

contiguous

mosaics character 7FH

separated

MGL117

If either the newsflash or the subtitle bit is set a different

SFR is used to define the display mode, as described in

Section 9.13.

Fig.12 Contiguous and separated mosaics.

The suppress header bit causes the header row (row 0) to

be displayed as if every character was a space and the

inhibit display bit has this effect on every display row.

9.11 Quadruple width display (SAA549x)

The language control bits cause certain character codes to

be interpreted differently, as described above.

Two successive double width control characters will

invoke quadruple width display. Quad width display is

terminated by another size control character.

9.13 Display modes

Any combination of two of the four controls which invoke

double width display (double width, double size, double

width OSD and double size OSD) can invoke quad width

display. If a double size control character is part of the

sequence, characters will be displayed in quad width and

double height.

The device signals the TVs display circuits to display the

R, G and B outputs of the device, rather than the video

picture, by outputting a logic 1 on the VDS output. The way

in which this signal is switched is controlled by the bits in

the TXT5 and TXT6 SFRs. There are 3 control functions -

text on, background on and picture on. Separate sets of

bits are used inside and outside teletext boxes so that

different display modes can be invoked. Also, different

SFRs are used depending on whether the newsflash (C5)

or subtitle (C6) bits in row 25 of the basic page memory are

set (SFR TXT6) or not (SFR TXT5). This allows the

software to set up the type of display required on

To ensure that broadcast teletext pages can be displayed

correctly, quadruple width will only be displayed if the

TXT4.QUAD WIDTH ENABLE bit is set. If this bit is not set,

two successive double width characters will invoke double

width display.

If quadruple width characters are to be used within OSD

boxes (see later section) then the first of the width

characters must be either ‘double width’ (OEH) or ‘double

size’ (OFH).

newsflash and subtitle pages (e.g. text inside boxes, TV

picture outside) this will be invoked without any further

software intervention when such a page is acquired.

1997 Jul 07

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Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

When teletext box control characters are present in the

page memory, whichever is relevant of the ‘Boxes On

Row 0’, ‘Boxes On Row 1 to 23’ and ‘Boxes On Row 24’

SFR bits in TXT17 must be set if the display mode is to

change in the box. These bits are present to allow boxes

in certain areas of the screen to be disabled so that teletext

boxes can be used for the display of OSD messages

without the danger of subtitles in boxes, which may also be

in the page memory, being displayed. The use of teletext

boxes for OSD messages has been superseded in this

device by the OSD box concept, described later, but these

bits remain to allow teletext boxes to be used, if required.

Setting the shadow TXT4.SHADOW ENABLE bit will add

a ‘south east’ shadow to the text, significantly enhancing

its readability in mix mode. Shadowing is illustrated in

Fig.13.

The readability of text can also be enhanced using

‘meshing’. Meshing causes the VDS signal to switch so

that when the text background colour should be displayed

every other pixel is displayed from the video picture. Text

foreground pixels are always displayed.

The TXT4.BMESH bit enables meshing on areas of the

screen within the text display area with black as the

background colour. The TXT4.CMESH bit has the same

effect on areas with other background colours. Meshing

can only be invoked in areas displayed in text mode i.e.

where the TXT5.TEXT IN and TXT5.BKGND IN bits are

both set to logic 1s, and in OSD boxes. Meshed text can

also be shadowed. Meshing is illustrated in Fig.13.

The COR bits in the TXT5 and TXT6 SFRs control when

the COR output of the device is activated (i.e. pulled

down). This output is intended to act on the TV’s display

circuits to reduce the contrast of the video display when it

is active. The result of contrast reduction is to improve the

readability of the text in a mixed text and video display.

The TXT4.TRANS bit causes areas of black background

colour to become transparent i.e. video is displayed

instead of black background. Black background

transparency can also only be invoked in areas displayed

in text mode i.e. where the TXT5.TEXT IN and

TXT5.BKGND IN bits are both set to a logic 1, and in OSD

boxes.

The bits in the TXT5 and TXT6 SFRs allow the display to

be set up so that, for example, the areas inside teletext

boxes will be contrast reduced when a subtitle is being

displayed but that the rest of the screen will be displayed

as normal video.

Table 19 Display control bits

PICTURE ON

TEXT ON

BACKGROUND ON

EFFECT

text mode, black screen

0

1

0

1

0

1

X

0

1

X

0

1

text mode, background always black

text mode

TV mode

mixed text and TV mode

text mode, TV picture outside text area

1997 Jul 07

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Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

normal mix mode

SE shadowing

handbook, halfpage

meshing

meshing and shadowing

TV picture

black

text foreground colour

text background colour

MGL118

Fig.13 Meshing and shadowing.

Table 20 Enhanced display mode selection

SHADOW TRANS BMESH CMESH

DISPLAY

normal, unshadowed, unmeshed text

0

1

0

1

0

1

X

0

1

0

1

0

1

text with coloured backgrounds meshed, black background solid

text with coloured backgrounds solid, black background meshed

text with all backgrounds meshed

text with coloured backgrounds solid, black background transparent

text with coloured backgrounds meshed, black background transparent

shadowed text with coloured backgrounds meshed, black background

solid

1

0

1

0

shadowed text with coloured backgrounds solid, black background

meshed

1

0

1

0

shadowed text with all backgrounds meshed

X

shadowed text with coloured backgrounds solid, black background

transparent

1

X

1

shadowed text with coloured backgrounds meshed, black background

transparent

1997 Jul 07

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Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

Screen colour is displayed from 10.5 to 62.5 µs after the

active edge of the HSync input and on TV lines 23 to 310

inclusive, for a 625-line display, and lines 17 to 260

inclusive for a 525-line display.

9.14 On Screen Display boxes

The size implying OSD control characters (BCH to BFH)

are intended to allow OSD messages to be displayed with

the minimum disruption to the teletext page stored in the

page memory. OSD boxes are not the same as teletext

boxes created using the teletext boxing control characters

(0AH and 0BH).

When the screen colour has been redefined, no TV picture

is displayed so the FRAME de-interlace output can be

activated, if the SFR bits controlling FRAME are set up to

allow this.

When one of these characters occurs the display size

changes appropriately (to normal size for BCH, double

height for BDH, double width for BEH and double size for

BFH) and an OSD box starts from the next character

position (‘set after’). The OSD box ends either at the end

of the row of text or at the next size implying OSD

character. When an OSD box is ended using another size

implying OSD character the box ends at the position of the

control character (‘set at’). This arrangement allows

displays to be created without blank spaces at the ends of

the OSD boxes.

Table 21 Screen colours

SCREEN

COL 2

SCREEN

COL 1

SCREEN

COL 0

SCREEN

COLOUR

0

1

0

1

0

1

0

1

0

1

0

1

0

1

transparent

red

green

yellow

blue

To prevent control characters from the teletext page

affecting the display of the OSD message the flash,

teletext box, conceal, separated graphics, twist and hold

graphics functions are all reset at the start of an OSD box,

as they are at the start of the row. In order to allow the most

commonly used display attributes to be set up before the

box starts the foreground colour, background colour and

mosaics on/off attributes are not reset.

magenta

cyan

white

9.16 Redeﬁnable Colours (SAA549x)

The CLUT SFR can be used to load a colour look-up table

(CLUT) which allows the 8 foreground colours and

8 background colours to be redefined. Each entry has

6 bits, 2 for each colour component, giving a total palette

of 64 colours from which to choose.

The text within an OSD box is always displayed in text

mode i.e. as if the Text On and Bkgnd On bits are both set

to a logic 1. The type of display produced inside an OSD

box is, therefore, dependent on the states of the

TXT4.SHADOW ENABLE, TXT4.TRANS ENABLE,

TXT4.BMESH ENABLE and TXT4.CMESH ENABLE

register bits, as described previously. OSD boxes can only

be displayed in TV mode i.e. when the Picture On SFR bit

is a logic 1 and the Text On SFR bit is a logic 0, both inside

and outside text boxes and for both normal and

newsflash/subtitle pages.

When the CLUT.CLUT ENABLE bit is a logic 0 the CLUT

is disabled and the device will display the normal, full

intensity, teletext colours.

The meaning of the least significant 6 bits of the CLUT

SFR depends on the setting of the CLUT.CLUT

ADDRESS bit when the register is written to. If the

CLUT.CLUT ADDRESS bit is a logic 1, the 4 LSB’s of the

SFR contain the address of the entry in the CLUT which

will be modified by subsequent writes to the CLUT SFR. If

the CLUT.CLUT ADDRESS bit is a logic 0, the 6 LSB’s of

the SFR define a colour which will be written into the CLUT

at the address defined by a previous write to the CLUT

SFR. An entry is written into the CLUT whenever the CLUT

SFR is written to, unless the CLUT.CLUT ADDRESS bit is

set.

The display of OSD boxes is not affected by the C7,

suppress header, and C10, inhibit display, control bits

stored in row 25 of the page memory.

9.15 Screen colour

The register bits TXT17.SCREEN COL2 to COL0 can be

used to define a colour to be displayed in place of TV

picture and the black background colour. If the bits are all

set to logic 0s, the screen colour is defined as ‘transparent’

and the TV picture and background colour are displayed

as normal.

Table 22 shows which CLUT entry corresponds to which

full intensity colour. The contents of the CLUT are not reset

at power-up and should be defined by the software before

the CLUT is enabled.

1997 Jul 07

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Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

The Fastext prompt row (packet 24) can be displayed from

the extension packet memory by setting the

TXT0.DISPLAY X/24 bit. When this bit is set the data

displayed on display row 24 is taken from row 0 in the

extension packet memory.

Table 22 CLUT Address

CLUT ADDRESS FULL INTENSITY EQUIVALENT

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

black foreground

red foreground

When the display from extension packet block option is

enabled, the display will revert to row 24 of the basic page

memory if bit 3 of the link control byte in packet 27 is set.

green Foreground

yellow foreground

blue foreground

magenta foreground

cyan foreground

white foreground

black background

red background

9.19 Display timing

The display synchronises to the device’s HSync and

VSync inputs. A typical configuration is shown in Fig.14.

The HSync and VSync signals are derived from the signals

driving the deflection coils of the TV. The CVBS input is

only used to extract teletext from. Locking the display to

the signals from the scan circuits allows the device give a

stable display under almost all signal conditions.

green background

yellow background

blue background

magenta background

cyan background

white background

The polarity of the input signals which the device is

expecting can be set using the TXT1.H polarity and

TXT1.V polarity bits. If the polarity bit is a logic 0, a positive

going signal is expected and if it is a logic 1, a negative

going signal is expected.

9.17 Cursor

9.20 Horizontal timing

If the TXT7.CURSOR ON bit is set, a cursor is displayed.

The cursor operates by reversing the background and

foreground colours in the character position pointed to by

the active row and column bits in the TXT9 and TXT10

SFRs.

Every time an HSync pulse is received the display

resynchronizes to its leading edge. To get maximum

display stability, the HSync input must have fast edges,

free of noise to ensure that there is no uncertainty in the

timing of the signal to which the display synchronisation

circuits must lock.

Setting the TXT9.CURSOR FREEZE bit, causes the

cursor to stay in its current position, no matter what

happens to the active row and column positions. This

means that the software can read data from the memory

(e.g. TOP table information) without affecting the position

of the cursor.

The display area starts 17.2 µs into the line and lasts for

40 µs. The display area will be in the centre of the screen

if the HSync pulse is aligned with line flyback signal.

Therefore, it is better to derive HSync directly from the line

flyback or from an output of the line output transformer

than from, say, slicing the sandcastle signal as this would

introduce delays which would shift the display to the right.

9.18 Other display features

Setting the TXT7.DOUBLE HEIGHT bit causes the normal

height of all display characters to be doubled and the

whole of the display area to be occupied by half of the

display rows. Characters normally displayed double height

will be displayed quadruple height when this bit is set.

Rows 12 to 24 can be enlarged, rather then rows 0 to 11,

by setting the TXT7.TOP/BOTTOM bit.

9.21 Vertical timing

The vertical display timing also resynchronizes to every

sync pulse received. This means that the device can

produce a stable display on both 625 and 525-line

screens. Display starts on the 41st line of each field and

continues for 250 lines, or until the end of the field.

This feature can be used for either a user controlled

‘enlarge’ facility or to provide very large characters for

OSD.

Normally, television displays are interlaced, i.e. only every

other TV line is displayed on each field. It is normal to

de-interlace teletext displays to prevent the displayed

characters flickering up and down. In many TV designs this

The display of rows 0 to 23 can be disabled by setting the

TXT0.DISLAY STATUS ROW ONLY bit.

1997 Jul 07

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Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

is achieved by modulating the vertical deflection current in

such a way that odd fields are shifted up and even fields

are shifted down on the screen so that lines 1 and 314,

2 and 315 etc. are overlaid. The FRAME output is

provided to facilitate this.

9.22 Display position

The position of the display relative to the HSync and

VSync inputs can be varied over a limited range to allow

for optimum TV set-up.

The horizontal position is controlled by the X0 and X1 bits

in TXT16. Table 23 gives the time from the active edge of

the HSync to the start of the display area for each setting

of X0 and X1.

If the active edge of Vsync occurs in the first half of a TV

line this is an even field and the FRAME output should be

a logic 0 for this field. Similarly, if VSync is in the second

half of the line this is an odd field and FRAME should be a

logic1. The algorithm used to derive Frame is such that a

consistent output will be obtained no matter where the

VSync signal is relative to the HSync signal, even if VSync

occurs at the start and mid points of a line.

Table 23 Display horizontal position

Hsync TO DISPLAY

X1

X0

(µs)

Setting the TXT0.DISABLE FRAME bit forces the FRAME

output to a logic 0. Setting the TXT0.AUTO FRAME bit

causes the FRAME output to be active when just text is

being displayed but to be forced to a logic 0 when any

video is being displayed. This allows the de-interlacing

function to take place with virtually no software

intervention.

0

1

0

1

0

1

17.2

16.2

15.2

14.2

The line on which the display area starts depends on

whether the display is 625-line or 525-line and on the

setting of the Y0 to Y2 bits in TXT16. Table 24 gives the

first display line for each setting of Y0 to Y2, for both

625 and 525-line display.

Some TV architectures do not use the FRAME output but

accomplish the de-interlacing function in the vertical

deflection IC, under software control, by delaying the start

of the scan for one field by half a line, so that lines in this

field are moved up by one TV line. In such TVs, VSync

may occur in the first half of the line at the start of an odd

field and in the second half of the line at the start of an even

field. In order to obtain correct de-interlacing in these

circumstances, the TXT1.FIELD POLARITY must be set to

reverse the assumptions made by the vertical timing

circuits on the timing of VSync in each field. The start of the

display may be delayed by a line. The ‘Field Polarity’ bit

does not affect the FRAME output.

On the other field, the display starts on the equivalent line.

Table 24 Display vertical position

FIRST LINE FOR DISPLAY

Y2

Y1

Y0

625-LINE

525-LINE

0

1

0

1

0

1

0

1

0

1

0

1

0

1

42

44

46

48

34

36

38

40

28

30

32

34

20

22

24

26

handbook, halfpage

CVBS

RGB

VIDEO

DECODING

CRT

TUNER/IF

DISPLAY

HSYNC, VSYNC

SYNC

CIRCUITS

RGB, VDS

SAA5x9x

FRAME

MGK464

Fig.14 Timing configuration.

1997 Jul 07

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Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

64 µs

handbook, full pagewidth

23

lines

52 µs

∆Y

10.5

µs

∆X

40 µs

25

250

lines

287

lines lines

312

TEXT DISPLAY AREA

rows

40 characters

TV PICTURE AREA

FIELD SCANNING AREA

MGL122

Fig.15 625-line display format.

63.55 µs

52 µs

handbook, full pagewidth

17

lines

∆Y

10.5

µs

∆X

40 µs

25

rows

225

lines

243

lines lines

263

TEXT DISPLAY AREA

40 characters

TV PICTURE AREA

FIELD SCANNING AREA

MGL123

Fig.16 525-line display format.

47

1997 Jul 07

Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

9.23 Clock generator

The oscillator circuit is a single-stage inverting amplifier in a Pierce oscillator configuration. The circuitry between OSCIN

and OSCOUT is basically an inverter biased to the transfer point. A crystal must be used as the feedback element to

complete the oscillator circuitry. It is operated in parallel resonance. OSCIN is the high gain amplifier input and OSCOUT

is the output. To drive the device externally OSCIN is driven from an external source and OSCOUT is left open-circuit.

handbook, halfpage

OSCGND

V

(1)

SS

OSCIN

C1

C2

OSCIN

external clock

not connected

OSCOUT

V

SS

MLC110

MLC111

(1) The values of C1 and C2 depend on the crystal specification:

C1 = C2 = 2C_L.

Fig.17 Oscillator circuit.

Fig.18 Oscillator circuit driven from external source.

1997 Jul 07

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Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

10 CHARACTER SETS

The two Pan-European character sets are shown in Figs 20 and 21. The character sets for Russian, Greek/Turkish,

Arabic/English/French, Thai and Arabic/Hebrew are available on request.

10.1 Pan-European

handbook, full pagewidth

MGL133

Fig.19 Pan-European geographical coverage.

1997 Jul 07

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Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

GM1L24

h a n d b o o k , f u l l p a g e w i d t h

1997 Jul 07

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Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

handbook, full pagewidth

LANGUAGE

CHARACTER

5D 5E 5F

23

5B

5C

60

7B

7C

7D

7E

E/W C12 C13 C14

24

40

(1)

ENGLISH

GERMAN

0

1

0

1

0

1

0

1

0

(1)

SWEDISH

(1)

ITALIAN

(1)

FRENCH

0

1

0

1

0

SPANISH

TURKISH

ENGLISH

(1)

(2)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

(1)

POLISH

(1)

GERMAN

(1)

ESTONIAN

(2)

GERMAN

(2)

GERMAN

(1)

SERBO-CROAT

(1)

CZECH

(1)

1

RUMANIAN

MGL125

(1) Languages in bold typeface conform to the EBU document SP492 or where superseded ETSI document pr ETS 300 706 with respect to

C12/C13/C14 definition.

(2) Languages in italic typeface are included for backward compatibility with previous generation of Philips teletext decoders.

Fig.21 National option characters.

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Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

10.2 Russian

handbook, full pagewidth

MGL128

Fig.22 Russian geographical coverage.

10.3 Greek/Turkish

handbook, full pagewidth

MGL129

Fig.23 Greek/Turkish geographical coverage.

52

1997 Jul 07

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Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

10.4 Arabic/English/French

handbook, full pagewidth

MGL131

Fig.24 Arabic/English/French geographical coverage.

10.5 Thai

handbook, full pagewidth

MGL132

Fig.25 Thai geographical coverage.

1997 Jul 07

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Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

10.6 Arabic/Hebrew

book, full pagewidth

MGL130

Fig.26 Arabic/Hebrew geographical coverage.

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Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

11 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL

V_DD

PARAMETER

supply voltage (all supplies)

CONDITIONS

MIN.

−0.3

MAX.

+6.5

UNIT

V

V_I

input voltage (any input)

note 1

−0.3

−

V_DD+ 0.5

±10

V_O

I_O

output voltage (any output)

output current (each output)

DC input or output diode current

operating ambient temperature

storage temperature

mA

°C

I_IOK

T_amb

T_stg

−

±20

−20

−55

+70

+125

°C

Note

1. This value has an absolute maximum of 6.5 V independent of V_DD

.

12 CHARACTERISTICS

V_DD= 5 V ±10%; V_SS= 0 V; T_amb= −20 to +70 °C; unless otherwise speciﬁed.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supplies

V_DD

I_DDM

V_DD

I_DDM

I_DDA

I_DDT

supply voltage (V_DDto V_SS

)

4.5

−

5.0

5.5

40

5.5

35

50

65

V

microcontroller supply current

supply voltage

25

5.0

20

35

40

mA

V

4.5

−

microcontroller supply current

analog supply current

mA

−

teletext supply current

SAA5290, SAA5291,

SAA5291A, SAA5491

−

I_DDT

teletext supply current

SAA5296/7, SAA5296/7A,

SAA5496/7

−

50

80

mA

Digital inputs

RESET, EA

V_IL

V_IH

I_LI

LOW-level input voltage

−0.3

−

0.2V_DD− 0.1

V

HIGH-level input voltage

input leakage current

input capacitance

0.7V_DD

−10

−

V_DD+ 0.3

V

V_I= 0 to V_DD

+10

4

µA

pF

C_I

HSYNC AND VSYNC

V_thf

V_thr

V_HYS

C_I

switching threshold falling

0.2V_DD

−

V

switching threshold rising

hysteresis voltage

−

0.8V_DD

V

0.33V_DD

−

V

input capacitance

−

4

pF

1997 Jul 07

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Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Digital outputs

R, G AND B; NOTE 1

V_OL

V_OH

Z_O

C_L

I_O

LOW-level output voltage

HIGH-level output voltage

output impedance

I_OL= 2 mA

0

V

−

0.2

V

I_OH= −2 mA

_RGBREF− 0.3 V_RGBREFV_RGBREF+ 0.4 V

−

150

50

Ω

load capacitance

pF

mA

ns

DC output current

−4

t_r

output rise time

between 10 and 90%;

C_L= 50 pF

20

t_f

output fall time

between 90 and 10%;

C_L= 50 pF

−

20

ns

VDS

V_OL

V_OH

C_L

LOW-level output voltage

HIGH-level output voltage

load capacitance

I_OL= 1.6 mA

0

V

−

0.2

V

I_OH= −1.6 mA

_DD− 0.3

V_DD+ 0.4

V

50

20

pF

ns

t_r

output rise time

between 10 and 90%;

C_L= 50 pF

t_f

output fall time

between 90 and 10%;

C_L= 50 pF

−

20

ns

V

R, G, B AND VDS

t_skewskew delay between any two

pins

20

COR (OPEN-DRAIN OUTPUT)

V_OH

HIGH-level pull-up output

V_DD

voltage

V_OL

I_OL

C_L

LOW-level output voltage

LOW-level output current

load capacitance

I_OL= 2 mA

0

−

0.5

2

V

mA

pF

25

FRAME, RD, WR, ALE, PSEN, AD0 TO AD7, A8 TO A15

V_OH

V_OL

I_OL

HIGH-level output voltage

LOW-level output voltage

LOW-level output current

load capacitance

I_OL= 8 mA

0

−

0.5

V_DD

+8

V

I_OL= −8 mA

V

_DD− 0.5

V

−8

mA

pF

C_L

−

100

1997 Jul 07

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Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

SYMBOL

Digital input/outputs

P0.0 TO P0.4, P0.7, P1.0 TO P1.5, P2.0 TO P2.7 AND P3.0 TO P3.4

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

V_IL

V_IH

C_I

LOW-level input voltage

HIGH-level input voltage

input capacitance

−0.3

−

0.2V_DD− 0.1

V

0.2V_DD+ 0.9

V_DD+ 0.3

V

−

0

−

4

pF

V

V_OL

C_L

LOW-level output voltage

load capacitance

I_OL= 3.2 mA

0.45

50

pF

P0.5 AND P0.6

V_IL

V_IH

C_I

LOW-level input voltage

−0.3

−

0.2V_DD− 0.1

V

HIGH-level input voltage

input capacitance

0.2V_DD+ 0.9

V_DD+ 0.3

V

−

0

−

4

pF

V

V_OL

C_L

LOW-level output voltage

load capacitance

I_OL= 10 mA

0.45

50

pF

P1.6 AND P1.7

V_IL

V_IH

C_I

LOW-level input voltage

−0.3

3.0

−

+1.5

V_DD+ 0.3

5

V

HIGH-level input voltage

input capacitance

V

pF

V

V_OL

C_L

t_f

LOW-level output voltage

load capacitance

I_OL= 3 mA

0

0.5

−

400

pF

ns

output fall time

between 3 and 1 V

−

200

Analog inputs

CVBS0 AND CVBS1

V_sync

sync voltage amplitude

0.1

0.7

0.3

1.0

0.6

1.4

V

V_vid(p-p)

video input voltage amplitude

(peak-to-peak value)

Z_source

V_IH

Z_I

source impedance

HIGH level input voltage

input impedance

−

250

Ω

3.0

2.5

−

V_DD+ 0.3

V

5.0

−

kΩ

pF

C_I

input capacitance

10

IREF

R_gnd

resistor to ground

−

27

−

kΩ

RGBREF; NOTE 1

V_I

I_I

input voltage

DC input current

−0.3

−

V_DD

12

V

−

mA

1997 Jul 07

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Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

REF+, REF−

V_IH

Z_I

HIGH level input voltage

input impedance

3.0

2.5

−

V_DD+ 0.3

V

5.0

−

kΩ

pF

C_I

input capacitance

−

10

ADC0, ADC1 and ADC2

V_IL

LOW-level input voltage

−0.3

−

V_DD

V

Analog input/output

BLACK

C_BLACK

V_BLACK

storage capacitor to ground

−

100

−

nF

V

black level voltage for nominal

sync amplitude

1.8

2.15

2.5

I_LI

input leakage current

-10

−

+10

µA

Crystal oscillator

OSCIN

V_IL

V_IH

C_I

LOW-level input voltage

−0.3

−

0.2V_DD− 0.1

V_DD+ 0.3

10

V

HIGH-level input voltage

input capacitance

0.7V_DD

V

−

pF

OSCOUT

C_O

output capacitance

−

10

pF

CRYSTAL SPECIFICATION; NOTE 2

f_xtal

C_L

C1

C0

R_r

nominal frequency

load capacitance

series capacitance

parallel capacitance

resonance resistance

temperature range

adjustment tolerance

drift

−

12

32

18.5

4.9

35

+25

−

MHz

pF

fF

−

T

_amb= 25 °C

−

T

−

pF

Ω

T_amb= 25 °C

−

T_xtal

X_j

-20

−

+70

°C

T_amb= 25 °C

±50 × 10^-6

±30 × 10^-6

X_d

−

Notes

1. All RGB current is sourced from the RGBREF pin. The maximum effective series resistance between RGBREF and

the R, G and B pins is 150 Ω.

2. Crystal order number 4322 143 05561.

1997 Jul 07

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Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

13 CHARACTERISTICS FOR THE I²C-BUS INTERFACE

SYMBOL

PARAMETER

INPUT

OUTPUT

I²C-BUS SPECIFICATION

SCL timing

t_HD;STA

t_LOW

t_HIGH

t_rC

START condition hold time

SCL LOW time

≥4.0 µs

note 1

≥4.0 µs

≥4.7 µs

≥4.0 µs

≤1.0 µs

≤0.3 µs

≥4.7 µs

≥4.0 µs

≤1.0 µs

≤0.3 µs

note 1

SCL HIGH time

SCL rise time

≥4.0 µs; note 2

note 3

t_fC

SCL fall time

≤0.3 µs; note 4

SDA timing

t_SU;DAT1

t_HD;DAT

t_SU;STA

t_SU;STO

t_BUF

data set-up time

≥250 ns

≥0 ns

note 1

≥250 ns

≥0 ns

data hold time

note 1

repeated START set-up time

STOP condition set-up time

bus free time

≥4.7 µs

≥4.0 µs

≥4.7 µs

≤1.0 µs

≤0.3 µs

note 1

≥4.7 µs

≥4.0 µs

≥4.7 µs

≤1.0 µs

≤0.3 µs

note 1

t_rD

SDA rise time

note 3

t_fD

SDA fall time

≤0.3 µs; note 4

Notes

1. This parameter is determined by the user software. It must comply with the I²C-bus specification.

2. This value gives the auto-clock pulse length which meets the I²C-bus specification for the special crystal frequency.

Alternatively, the SCL pulse must be timed by software.

3. The rise time is determined by the external bus line capacitance and pull-up resistor. It must be less than 1 µs.

4. The maximum capacitance on bus lines SDA and SCL is 400 pF.

1997 Jul 07

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Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

LM1C04

h a n d b o o k , f u l l p a g e w

1997 Jul 07

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Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

14 QUALITY SPECIFICATIONS

This device will meet Philips Semiconductors General Quality Specification for Business group “Consumer Integrated

Circuits SNW-FQ-611-Part E”; “Quality Reference Handbook, order number 9398 510 63011”. The principal

requirements are shown in Table 25 to 28.

Table 25 Acceptance tests per lot; note 1

TEST

Mechanical

Electrical

REQUIREMENTS

cumulative target: <80 ppm

Table 26 Processability tests (by package family); note 2

TEST

solderability

mechanical

<7% LTPD

<15% LTPD

solder heat resistance <15% LTPD

Table 27 Reliability tests (by process family); note 3

TEST

CONDITIONS

REQUIREMENTS

<1000 FPM at T_j= 70 °C

<2000 FPM

operational life

humidity life

168 hours at T_j= 150 °C

temperature, humidity, bias 1000 hours, 85 °C, 85% RH

(or equivalent test)

temperature cycling

performance

T

_stg(min)to T_stg(max)

<2000 FPM

Table 28 Reliability tests (by device type)

TEST

CONDITIONS

REQUIREMENTS

ESD and latch-up

ESD Human body model 100 pF, 1.5 kΩ

ESD Machine model 200 pF, 0 Ω

latch-up

2000 V

200 V

100 mA, 1.5 × V_DD(absolute maximum)

Notes to Tables 25, 26 and 27

1. ppm = fraction of defective devices, in parts per million.

2. LTPD = Lot Tolerance Percent Defective.

3. FPM = fraction of devices failing at test condition, in failures per million.

1997 Jul 07

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Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

15 APPLICATION INFORMATION

GM4K63

ndbook, full pagewidth

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Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

when using SM capacitors (which are also most effective

at high frequencies). Each supply pin should be connected

separately to the power connection of the PCB, preferably

via at least one wire link which:

16 EMC GUIDELINES

If possible, a ground plane under the whole IC should be

present, i.e. no signal tracks running underneath the IC as

shown in Fig.29.

1. May be replaced by a ferrite or inductor at a later point

if necessary

The ground plane under the IC should be connected by the

widest possible connection back to the ground connection

of the PCB, and electrolytic decoupling capacitor. It should

preferably not connect to other grounds on the way and no

wire links should be present in this connection. The use of

wire links increases ground bounce by introducing

inductance into the ground, thereby reducing the

2. Will introduce a small amount of inductance.

Signals connected to the +5 V supply e.g. via a pull-up

resistors, should be connected to the +5 V supply before

the wire link to the IC (i.e. not the IC side). This will prevent

if from being polluted and conduct or radiate noise onto

signal lines, which may then radiate themselves.

electrolytic capacitor’s decoupling efficiency.

The supply pins should be decoupled at the pin, to the

ground plane under the IC. This is easily accomplished

OSCGND should connect only to the crystal load

capacitors (and not GND).

GND +5 V

handbook, full pagewidth

electrolytic decoupling capacitor (2 µF)

wire links

other

GND

connections

SM decoupling capacitors (10 to 100 nF)

V

DDD

DDA

DDM

under-IC GND plane

GND connection

note: no wire links

IC

V

SSA

SSD

MGL127

Fig.29 Power supply and GND connections for SOT247-1.

1997 Jul 07

63

Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

17 PACKAGE OUTLINES

SDIP52: plastic shrink dual in-line package; 52 leads (600 mil)

SOT247-1

D

M

E

A

2

A

L

A

1

c

e

(e )

1

w M

Z

b

1

M

H

b

52

27

pin 1 index

E

1

26

0

5

10 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

A

max.

A

2

max.

(1)

Z

1

w

UNIT

b

c

D

E

e

L

M

H

1

E

min.

max.

1.3

0.8

0.53

0.40

0.32

0.23

47.9

47.1

14.0

13.7

3.2

2.8

15.80

15.24

17.15

15.90

mm

5.08

0.51

4.0

1.778

15.24

0.18

1.73

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

EIAJ

90-01-22

95-03-11

SOT247-1

1997 Jul 07

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Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

QFP80: plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm

SOT318-2

y

X

A

64

65

41

40

Z

E

e

Q

A

2

H

A

E

(A )

3

E

A

1

w M

p

θ

pin 1 index

L

p

b

L

80

25

detail X

1

24

w M

Z

v

M

D

A

B

b

p

e

D

B

H

v

D

0

5

scale

10 mm

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

Q

v

w

y

Z

E

θ

1

2

3

p

E

p

D

max.

7^o

0^o

0.25 2.90

0.05 2.65

0.45 0.25 20.1 14.1

0.30 0.14 19.9 13.9

24.2 18.2

23.6 17.6

1.0

0.6

1.4

1.2

1.0

0.6

1.2

0.8

mm

3.2

0.25

0.8

1.95

0.2

0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

EIAJ

92-12-15

95-02-04

SOT318-2

1997 Jul 07

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Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

Reflow soldering requires solder paste (a suspension of

fine solder particles, flux and binding agent) to be applied

to the printed-circuit board by screen printing, stencilling or

pressure-syringe dispensing before package placement.

18 SOLDERING

18.1 Introduction

There is no soldering method that is ideal for all IC

packages. Wave soldering is often preferred when

through-hole and surface mounted components are mixed

on one printed-circuit board. However, wave soldering is

not always suitable for surface mounted ICs, or for

printed-circuits with high population densities. In these

situations reflow soldering is often used.

Several techniques exist for reflowing; for example,

thermal conduction by heated belt. Dwell times vary from

50 to 300 seconds depending on heating method. Typical

reflow temperatures range from 215 to 250 °C.

Preheating is necessary to dry the paste and evaporate

the binding agent. Preheat for 45 minutes at 45 °C.

This text gives a very brief insight to a complex technology.

A more in-depth account of soldering ICs can be found in

our “IC Package Databook” (order code 9398 652 90011).

18.3.2 WAVE SOLDERING

Wave soldering is not recommended for QFP packages.

This is because of the likelihood of solder bridging due to

closely-spaced leads and the possibility of incomplete

solder penetration in multi-lead devices.

18.2 SDIP

18.2.1 SOLDERING BY DIPPING OR BY WAVE

The maximum permissible temperature of the solder is

260 °C; solder at this temperature must not be in contact

with the joint for more than 5 seconds. The total contact

time of successive solder waves must not exceed

5 seconds.

If wave soldering cannot be avoided, the following

conditions must be observed:

• A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)

soldering technique should be used.

The device may be mounted up to the seating plane, but

the temperature of the plastic body must not exceed the

specified maximum storage temperature (T_{stg max}). If the

printed-circuit board has been pre-heated, forced cooling

may be necessary immediately after soldering to keep the

temperature within the permissible limit.

• The footprint must be at an angle of 45° to the board

direction and must incorporate solder thieves

downstream and at the side corners.

Even with these conditions, do not consider wave

soldering the following packages: QFP52 (SOT379-1),

QFP100 (SOT317-1), QFP100 (SOT317-2),

QFP100 (SOT382-1) or QFP160 (SOT322-1).

18.2.2 REPAIRING SOLDERED JOINTS

During placement and before soldering, the package must

be fixed with a droplet of adhesive. The adhesive can be

applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the

adhesive is cured. Maximum permissible solder

temperature is 260 °C, and maximum duration of package

immersion in solder is 10 seconds, if cooled to less than

150 °C within 6 seconds. Typical dwell time is 4 seconds

at 250 °C.

Apply a low voltage soldering iron (less than 24 V) to the

lead(s) of the package, below the seating plane or not

more than 2 mm above it. If the temperature of the

soldering iron bit is less than 300 °C it may remain in

contact for up to 10 seconds. If the bit temperature is

between 300 and 400 °C, contact may be up to 5 seconds.

18.3 QFP

18.3.1 REFLOW SOLDERING

A mildly-activated flux will eliminate the need for removal

of corrosive residues in most applications.

Reflow soldering techniques are suitable for all QFP

packages.

18.3.3 REPAIRING SOLDERED JOINTS

The choice of heating method may be influenced by larger

plastic QFP packages (44 leads, or more). If infrared or

vapour phase heating is used and the large packages are

not absolutely dry (less than 0.1% moisture content by

weight), vaporization of the small amount of moisture in

them can cause cracking of the plastic body. For more

information, refer to the Drypack chapter in our “Quality

Reference Handbook” (order code 9397 750 00192).

Fix the component by first soldering two diagonally-

opposite end leads. Use only a low voltage soldering iron

(less than 24 V) applied to the flat part of the lead. Contact

time must be limited to 10 seconds at up to 300 °C. When

using a dedicated tool, all other leads can be soldered in

one operation within 2 to 5 seconds between

270 and 320 °C.

1997 Jul 07

66

Philips Semiconductors

Preliminary speciﬁcation

Economy teletext and TV microcontrollers

SAA5x9x family

19 DEFINITIONS

Data sheet status

Objective speciﬁcation

Preliminary speciﬁcation

Product speciﬁcation

This data sheet contains target or goal speciﬁcations for product development.

This data sheet contains preliminary data; supplementary data may be published later.

This data sheet contains ﬁnal product speciﬁcations.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or

more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation

of the device at these or at any other conditions above those given in the Characteristics sections of the speciﬁcation

is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the speciﬁcation.

20 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these

products can reasonably be expected to result in personal injury. Philips customers using or selling these products for

use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such

improper use or sale.

21 PURCHASE OF PHILIPS I²C COMPONENTS

Purchase of Philips I²C components conveys a license under the Philips’ I²C patent to use the

components in the I²C system provided the system conforms to the I²C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

1997 Jul 07

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Hungary: see Austria

India: Philips INDIA Ltd, Band Box Building, 2nd floor,

254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,

Tel. +91 22 493 8541, Fax. +91 22 493 0966

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,

TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,

209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,

Tel. +66 2 745 4090, Fax. +66 2 398 0793

Indonesia: see Singapore

Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. +353 1 7640 000, Fax. +353 1 7640 200

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,

Tel. +90 212 279 2770, Fax. +90 212 282 6707

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,

TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,

252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461

Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,

20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,

MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,

Tel. +81 3 3740 5130, Fax. +81 3 3740 5077

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,

Tel. +1 800 234 7381

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,

Tel. +82 2 709 1412, Fax. +82 2 709 1415

Uruguay: see South America

Vietnam: see Singapore

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,

Tel. +60 3 750 5214, Fax. +60 3 757 4880

Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. +381 11 625 344, Fax.+381 11 635 777

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,

Tel. +9-5 800 234 7381

Middle East: see Italy

For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,

Internet: http://www.semiconductors.philips.com

Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825

SCA55

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed

without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license

under patent- or other industrial or intellectual property rights.

Printed in The Netherlands

547047/00/01/pp68

Date of release: 1997 Jul 07

Document order number: 9397 750 01952


型号：	SAA5297
厂家：	NXP
描述：	Economy teletext and TV microcontrollers 经济图文电视和电视微控制器微控制器电视
文件：	总68页 (文件大小：614K)
中文：	中文翻译
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