SAA5541PS/NNNN [NXP]
TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD); 电视微控制器,具有隐藏式字幕( CC)和屏幕显示( OSD )型号: | SAA5541PS/NNNN |
厂家: | NXP |
描述: | TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) |
文件: | 总84页 (文件大小:339K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
SAA55xx
TV microcontrollers with Closed
Captioning (CC) and On-Screen
Display (OSD)
Preliminary specification
2000 Feb 23
Supersedes data of 1999 Aug 02
File under Integrated Circuits, IC02
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
CONTENTS
15.1
16
I2C-bus port selection
MEMORY INTERFACE
1
2
3
4
5
6
FEATURES
16.1
16.2
16.3
16.4
Memory structure
Memory mapping
Addressing memory
Page clearing
GENERAL DESCRIPTION
QUICK REFERENCE DATA
ORDERING INFORMATION
BLOCK DIAGRAM
17
DATA CAPTURE
Data Capture features
DISPLAY
17.1
18
PINNING INFORMATION
6.1
6.2
Pinning
Pin description
18.1
Display features
18.2
18.3
18.4
18.5
18.6
18.7
18.8
18.9
18.10
18.11
18.12
18.13
18.14
18.15
Display modes
7
MICROCONTROLLER
Microcontroller features
MEMORY ORGANIZATION
Display feature descriptions
Character and attribute coding
Screen and global controls
Text display controls
Display positioning
Character set
7.1
8
8.1
8.2
8.3
8.4
8.5
8.6
ROM bank switching
RAM organisation
Data memory
SFR memory
Character set feature bits
External (auxiliary) memory
ROM addressing
Redefinable characters
Display synchronization
Video/Data switch (Fast Blanking) polarity
Video/data switch adjustment
RGB brightness control
Contrast reduction
9
REDUCED POWER MODES
9.1
9.2
9.3
Idle mode
Power-down mode
Standby mode
19
20
21
22
23
24
MEMORY MAPPED REGISTERS (MMR)
LIMITING VALUES
10
I/O FACILITY
10.1
10.2
10.3
10.4
I/O ports
Port type
Port alternative functions
LED support
CHARACTERISTICS
QUALITY AND RELIABILITY
APPLICATION INFORMATION
11
INTERRUPT SYSTEM
ELECTROMAGNETIC COMPATIBILITY
(EMC) GUIDELINES
11.1
11.2
11.3
11.4
Interrupt enable structure
Interrupt enable priority
Interrupt vector address
Level/edge interrupt
25
PACKAGE OUTLINES
SOLDERING
26
26.1
Introduction to soldering through-hole mount
packages
Soldering by dipping or by solder wave
Manual soldering
Suitability of through-hole mount IC packages
for dipping and wave soldering methods
12
TIMER/COUNTER
13
WATCHDOG TIMER
26.2
26.3
26.4
13.1
14
Watchdog Timer operation
PULSE WIDTH MODULATORS
14.1
14.2
14.3
14.4
PWM control
Tuning Pulse Width Modulator (TPWM)
TPWM control
Software ADC (SAD)
I2C-BUS SERIAL I/O
27
28
29
DEFINITIONS
LIFE SUPPORT APPLICATIONS
PURCHASE OF PHILIPS I2C COMPONENTS
15
2000 Feb 23
2
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
1
FEATURES
• Single-chip microcontroller with integrated On-Screen
Display (OSD)
• One Time Programmable (OTP) memory for both
Program ROM and character sets
• Single power supply: 3.0 to 3.6 V
• 5 V tolerant digital inputs and I/O
2
GENERAL DESCRIPTION
• 29 I/O port via individual addressable controls
The SAA55xx OSD only family of devices are a derivative
of the Philips industry standard 80C51 microcontroller and
are intended for use as the central control mechanism in a
television receiver. They provide control functions for the
television system, On-Screen Display (OSD) and some
versions include an integrated data capture function.
• Programmable I/O for push-pull, open-drain and
quasi-bidirectional
• Two port lines with 8 mA sink (at <0.4 V) capability, for
direct drive of Light Emitting Diode (LED)
• Single crystal oscillator for microcontroller, OSD and
The main differences between the OSD only family and the
SAA55xx Text/CC family of baseline devices are:
data capture
• Power reduction modes: Standby, Idle and Power-down
• Byte level I2C-bus up to 200 kHz with dual port I/O
• Program ROM size: 16 to 64-kbyte
• Display RAM size: 1.25-kbyte (1 page Text OSD or
CC/OSD)
(Slave mode up to 400 kHz)
• 32 Dynamically Redefinable Characters for OSDs
• Auxiliary RAM size: 0.75-kbyte
• Special graphic characters allowing four colours per
• No teletext data capture (Closed Caption only)
• Additional power saving mode (Standby).
character
• Selectable character height 9, 10, 13 and 16 TV lines
• Pin compatibility throughout family
• Operating temperature: −20 to +70°C.
2000 Feb 23
3
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
3
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
Supply
VDDX
IDDP
any supply voltage (VDD to VSS
)
3.0
3.3
3.6
V
periphery supply current; note 1
core supply current
1
−
−
mA
mA
µA
IDDC
−
12
18
IDDC(id)
IDDC(pd)
IDDC(stb)
IDDA
Idle mode core supply current
Power-down mode core supply current
Standby mode core supply current
analog supply current
−
383
666
5.1
45
600
900
9
−
µA
−
mA
mA
µA
−
48
IDDA(id)
IDDA(pd)
IDDA(stb)
fxtal
Idle mode analog supply current
Power-down mode analog supply current
Standby mode analog supply current
Fundamental mode nominal frequency
operating ambient temperature
storage temperature
−
444
433
809
12
700
700
950
−
−
µA
−
µA
−
MHz
°C
Tamb
−20
−55
−
+70
+125
Tstg
−
°C
Note
1. Peripheral supply current is dependent on external components and voltage levels on I/Os.
4
ORDERING INFORMATION
PACKAGE(2)
TYPE NUMBER(1)
NAME
ROM
RAM
CC
DESCRIPTION
VERSION
SAA5540PS/nnnn SDIP52
SAA5541PS/nnnn
plastic shrink dual in-line package; SOT247-1 16-kbyte
256-byte
512-byte
750-byte
750-byte
750-byte
yes
yes
yes
yes
yes
52 leads (600 mil)
32-kbyte
SAA5542PS/nnnn
48-kbyte
64-kbyte
24-kbyte
SAA5543PS/nnnn
SAA5547PS/nnnn
Notes
1. ‘nnnn’ is a four digit number uniquely referencing the microcontroller program mask.
2. For details of the LQFP100 package, please contact your local regional sales office for availability.
2000 Feb 23
4
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
5
BLOCK DIAGRAM
TV CONTROL
AND
2
I C-bus, general I/O
INTERFACE
ROM
(16 TO 64-KBYTE)
MICROPROCESSOR
(80C51)
SRAM
(256-BYTE)
DRAM
MEMORY
(UP TO 2-KBYTE)
INTERFACE
R
G
DATA
CAPTURE
DISPLAY
CVBS
CVBS
B
VDS
DATA
CAPTURE
TIMING
VSYNC
HSYNC
DISPLAY
TIMING
GSA005
Fig.1 Block diagram (top level architecture).
2000 Feb 23
5
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
6
PINNING INFORMATION
Pinning
6.1
handbook, halfpage
P2.0/TPWM
1
2
3
4
5
6
7
8
9
52 P1.5/SDA1
51 P1.4/SCL1
50 P1.7/SDA0
49 P1.6/SCL0
48 P1.3/T1
P2.1/PWM0
P2.2/PWM1
P2.3/PWM2
P2.4/PWM3
P2.5/PWM4
P2.6/PWM5
P2.7/PWM6
P3.0/ADC0
47 P1.2/INT0
46 P1.1/T0
45 P1.0/INT1
44
V
DDP
P3.1/ADC1 10
P3.2/ADC2 11
P3.3/ADC3 12
43 RESET
42 XTALOUT
41 XTALIN
40 OSCGND
V
13
SSC
SAA55xx
P0.0 14
P0.1 15
P0.2 16
P0.3 17
P0.4 18
P0.5 19
P0.6 20
P0.7 21
39
38
V
V
DDC
SSP
37 VSYNC
36 HSYNC
35 VDS
34
33
32
31
R
G
B
V
V
22
SSA
DDA
CVBS0 23
CVBS1 24
30 P3.4/PWM7
29 COR
SYNC_FILTER 25
IREF 26
28 VPE
27 FRAME
MBK951
Fig.2 SDIP52 pin configuration.
6
2000 Feb 23
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
P2.7/PWM6
P3.0/ADC0
n.c.
1
2
3
4
5
6
7
8
9
V
75
DDP
74 n.c.
73 RESET
P3.1/ADC1
P3.2/ADC2
P3.3/ADC3
n.c.
n.c.
72
71
XTALOUT
70 XTALIN
OSCGND
n.c.
69
68
67
n.c.
n.c.
n.c.
n.c. 10
66 n.c.
V
11
n.c.
n.c.
V
65
64
63
SSC
V
12
SSP
P0.5 13
n.c. 14
n.c. 15
P0.0 16
P0.1 17
P0.2 18
n.c. 19
n.c. 20
n.c. 21
P0.3 22
n.c. 23
P0.4 24
P3.7 25
SAA55xx
DDC
62 VPE_2
n.c.
V
61
60
59
SSP
P3.6
58 n.c.
n.c.
n.c.
57
56
55 VSYNC
54 P3.5
HSYNC
VDS
53
52
51 n.c.
GSA001
Fig.3 LQFP100 pin configuration.
7
2000 Feb 23
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
6.2
Pin description
Table 1 SDIP52 and LQFP100 packages
PIN
SYMBOL
TYPE
DESCRIPTION
SDIP52
LQFP100
P2.0/TPWM
P2.1/PWM0
P2.2/PWM1
P2.3/PWM2
P2.4/PWM3
P2.5/PWM4
P2.6/PWM5
P2.7/PWM6
P3.0/ADC0
P3.1/ADC1
P3.2/ADC2
P3.3/ADC3
P3.4/PWM7
P3.5
1
2
100
93
94
95
96
97
98
1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
−
Port 2. 8-bit programmable bidirectional port with
alternative functions.
3
P2.0/TPWM is the output for the 14-bit high precision
PWM. P2.1/PWM0 to P2.7/PWM6 are the outputs for
the 6-bit PWMs 0 to 6.
4
5
6
7
8
9
2
Port 3. 8-bit programmable bidirectional port with
alternative functions.
10
11
12
30
−
4
5
P3.0/ADC0 to P3.3/ADC3 are the inputs for the
software ADC facility. P3.4/PWM7 is the output for the
6-bit PWM7. P3.5 to P3.7 have no alternative
functions and are only available with the LQFP100
package.
6
44
54
59
25
11
16
17
18
22
24
13
28
29
30
31
P3.6
−
P3.7
−
VSSC
13
14
15
16
17
18
19
20
21
22
23
core ground
P0.0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
−
Port 0. 8-bit programmable bidirectional port.
P0.1
P0.5 and P0.6 have 8 mA current sinking capability for
direct drive of LEDs.
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
VSSA
analog ground
CVBS0
I
Composite Video Baseband Signal (CVBS) input. A
positive-going 1 V (peak-to-peak) input is required.
CVBS1
24
25
32
34
I
I
Connected via a 100 nF capacitor.
SYNC_FILTER
CVBS sync filter input. This pin should be connected
to VSSA via a 100 nF capacitor.
IREF
26
27
35
41
I
Reference current input for analog circuits, connected
to VSSA via a 24 KΩ resistor.
FRAME
O
De-interlace output synchronised with the VSYNC
pulse to produce a non-interlaced display by
adjustment of the vertical deflection circuits.
VPE
28
42
I
OTP programming voltage
2000 Feb 23
8
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
PIN
SYMBOL
COR
TYPE
DESCRIPTION
SDIP52
LQFP100
29
43
O
Open-drain, active LOW output which allows selective
contrast reduction of the TV picture to enhance a
mixed mode display.
VDDA
B
31
32
33
34
35
45
46
47
48
52
−
+3.3 V analog power supply
O
O
O
O
Pixel rate output of the BLUE colour information.
Pixel rate output of the GREEN colour information.
Pixel rate output of the RED colour information.
G
R
VDS
Video/data switch push-pull output for dot rate fast
blanking.
HSYNC
VSYNC
36
37
53
55
I
I
Schmitt triggered input TTL version of the horizontal
sync pulse. The polarity of this pulse is programmable
by register bit TXT1.H POLARITY.
Schmitt triggered input for a TTL version of the vertical
sync pulse. The polarity of this pulse is programmable
by register bit TXT1.V POLARITY.
VSSP
38
39
40
41
42
43
12, 60
63
−
−
−
I
periphery ground
VDDC
+3.3 V core power supply
crystal oscillator ground
12 MHz crystal oscillator input
12 MHz crystal oscillator output
OSCGND
XTALIN
XTALOUT
RESET
69
70
71
O
I
73
If the reset input is HIGH for at least 2 machine cycles
(24 oscillator periods) while the oscillator is running,
the device is reset. This pin should be connected to
VDDP via a capacitor.
VDDP
44
45
46
47
48
49
50
51
52
75
76
78
79
80
81
82
83
84
−
+3.3 V periphery power supply
P1.0/INT1
P1.1/T0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Port 1. 8-bit programmable bidirectional port with
alternative functions.
P1.2/INT0
P1.3/T1
P1.0/INT1 is external interrupt 1 which can be
triggered on the rising and falling edge of the pulse.
P1.1/T0 is the Counter/Timer 0. P1.2/INT0 is external
interrupt 0. P1.3/T1 is the Counter/Timer 1.
P1.6/SCL0 is the serial clock input for the I2C-bus and
P1.7/SDA0 is the serial data port for the I2C-bus.
P1.4/SCL1 is the serial clock input for the I2C-bus and
P1.5/SDA1 is the serial data port for the I2C-bus.
P1.6/SCL0
P1.7/SDA0
P1.4/SCL1
P1.5/SDA1
VPE_2
n.c.
−
−
62
I
OTP programming voltage
not connected
3, 7 to 10, 14, 15,
19 to 21, 23, 26, 27, 33,
36 to 40, 49 to 51,
−
56 to 58, 61, 64 to 68,
72, 74, 77, 85 to 92, 99
2000 Feb 23
9
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
7
MICROCONTROLLER
8
MEMORY ORGANIZATION
The functionality of the microcontroller used on this device
is described here with reference to the industry standard
80C51 microcontroller. A full description of its functionality
can be found in the “Handbook IC20, 80C51-Based 8-bit
Microcontrollers”.
The device has the capability of a maximum of 64-kbyte
Program ROM and 2-kbyte Data RAM internally.
8.1
ROM bank switching
As the Program ROM does not exceed 64 kbytes in any of
the OSD only variants, ROM bank switching is not
required.
7.1
Microcontroller features
• 80C51 microcontroller core standard instruction set and
timing
The memory and security bits are structured as shown in
Fig.4.
• 1 µs machine cycle
The OSD only security bits are set as shown in Fig.5 for
production programmed devices.
• Maximum 64K × 8-bit program ROM
• 2 × 8-bit auxiliary RAM, maximum of 1.25 kbytes
required for display
The OSD only security bits are set as shown in Fig.6 for
production blank devices.
• Interrupt controller for individual enable/disable with two
level priority
8.2
RAM organisation
• Two 16-bit timer/counter registers
• Watchdog Timer
The Internal Data RAM is organized into two areas, Data
memory and Special Function Registers (SFRs).
• Auxiliary RAM page pointer
• 16-bit data pointer
8.3
Data memory
The Data memory is 256 × 8-bit, and occupies the address
range 00H to FFH when using indirect addressing and
00H to 7FH when using direct addressing. The SFRs
occupy the address range 80H to FFH and are accessible
using direct addressing only.
• Standby, Idle and Power-down modes
• 29 general I/O lines
• Eight 6-bit Pulse Width Modulator (PWM) outputs for
control of TV analog signals
• One 14-bit PWM for Voltage Synthesis Tuner (VST)
control
The lower 128 bytes of Data memory are mapped as
shown in Fig.8.
• 8-bit Analog-to-Digital Converter (ADC) with four
multiplexed inputs
The lowest 24 bytes are grouped into 4 banks of
8 registers, the next 16 bytes above the register banks
form a block of bit addressable memory space.
• 2 high current outputs for directly driving LEDs
• I2C-bus byte level bus interface with dual ports.
The upper 128 bytes are not allocated for any special area
or functions.
2000 Feb 23
10
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
MEMORY
SECURITY BITS INTERACTION
PROGRAM ROM
USER ROM PROGRAMMING
(ENABLE/DISABLE)
VERIFY
(ENABLE/DISABLE)
USER ROM
(64K x 8-BIT)
CHARACTER ROM
USER ROM PROGRAMMING
(ENABLE/DISABLE)
VERIFY
(ENABLE/DISABLE)
USER ROM
(9K x 12-BIT)
GSA006
Fig.4 Memory and security bit structures.
MEMORY
SECURITY BITS SET
USER ROM PROGRAMMING
(ENABLE/DISABLE)
VERIFY
(ENABLE/DISABLE)
PROGRAM ROM
DISABLED
DISABLED
ENABLED
ENABLED
CHARACTER ROM
GSA007
Fig.5 Security bits for production devices.
11
2000 Feb 23
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
MEMORY
SECURITY BITS SET
USER ROM PROGRAMMING
(ENABLE/DISABLE)
VERIFY
(ENABLE/DISABLE)
PROGRAM ROM
ENABLED
ENABLED
ENABLED
CHARACTER ROM
ENABLED
GSA008
Fig.6 Security bits for production blank devices.
handbook, halfpage
SPECIAL
FUNCTION
REGISTERS
DATA
MEMORY
FFH
accessible
by indirect
addressing
only
accessible
by direct
addressing
only
upper 128 bytes
80H
7FH
accessible
by direct
and indirect
addressing
lower 128 bytes
00H
MBK956
Fig.7 Internal data memory.
12
2000 Feb 23
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
handbook, halfpage
7FH
30H
2FH
bit-addressable space
(bit addresses 00H to 7FH)
20H
1FH
R7
R0
R7
18H
17H
R0
R7
10H
0FH
4 banks of 8 registers
(R0 to R7)
R0
R7
08H
07H
R0
0
MGM677
Fig.8 Lower 128 bytes of internal RAM.
2000 Feb 23
13
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
8.4
SFR memory
The Special Function Register (SFR) space is used for port latches, timer, peripheral control, acquisition control, display control, etc. These registers
can only be accessed by direct addressing. Sixteen of the addresses in the SFR space are both bit and byte addressable. The bit addressable SFRs
are those whose address ends in 0H or 8H. A summary of the SFR map in address order is shown in Table 2.
A description of each of the SFR bits is shown in Table 3 which presents the SFRs in alphabetical order.
Table 2 SFR memory map
ADD R/W
NAME
7
6
5
4
3
2
1
0
RESET
80H R/W
81H R/W
82H R/W
83H R/W
87H R/W
88H R/W
89H R/W
8AH R/W
8BH R/W
8CH R/W
8DH R/W
90H R/W
PO
SP
P07
SP7
P06
SP6
P05
SP5
P04
SP4
P03
SP3
P02
SP2
P01
SP1
P00
SP0
FFH
07H
00H
00H
00H
00H
00H
00H
00H
00H
00H
FFH
FFH
00H
00H
FFH
00H
FFH
FFH
00H
00H
FFH
00H
00H
00H
DPL
DPH
PCON
TCON
TMOD
TL0
DPL7
DPH7
0
DPL6
DPL5
DPH5
RFI
DPL4
DPL3
DPH3
GF1
DPL2
DPH2
GF0
DPL1
DPH1
PD
DPL0
DPH0
IDL
DPH6
ARD
DPH4
WLE
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
GATE
TL07
TL17
TH07
TH17
P17
C/T
M1
M0
GATE
TL03
C/T
M1
M0
TL06
TL05
TL04
TL02
TL01
TL00
TL1
TL16
TL15
TL14
TL13
TL12
TL11
TL10
TH0
TH1
P1
TH06
TH05
TH15
P15
TH04
TH03
TH13
P13
TH02
TH12
P12
TH01
TH00
TH16
TH14
TH11
TH10
P16
P14
P11
P10
96H R/W P0CFGA P0CFGA7
97H R/W P0CFGB P0CFGB7
P0CFGA6
P0CFGB6
0
P0CFGA5
P0CFGB5
0
P0CFGA4
P0CFGB4
DC_COMP
P1CFGA4
P1CFGB4
P24
P0CFGA3
P0CFGB3
SAD3
P1CFGA3
P1CFGB3
P23
P0CFGA2
P0CFGB2
SAD2
P1CFGA2
P1CFGB2
P22
P0CFGA1
P0CFGB1
SAD1
P1CFGA1
P1CFGB1
P21
P0CFGA0
P0CFGB0
SAD0
P1CFGA0
P1CFGB0
P20
98H R/W
SADB
0
9EH R/W P1CFGA P1CFGA7
9FH R/W P1CFGB P1CFGB7
P1CFGA6
P1CFGB6
P26
P1CFGA5
P1CFGB5
P25
A0H R/W
P2
P27
A6H R/W P2CFGA P2CFGA7
A7H R/W P2CFGB P2CFGB7
P2CFGA6
P2CFGB6
EBUSY
P36
P2CFGA5
P2CFGB5
ES2
P2CFGA4
P2CFGB4
ECC
P2CFGA3
P2CFGB3
ET1
P2CFGA2
P2CFGB2
EX1
P2CFGA1
P2CFGB1
ET0
P2CFGA0
P2CFGB0
EX0
A8H R/W
B0H R/W
B2H R/W
B3H R/W
B4H R/W
IE
EA
P37
P3
P35
P34
P33
P32
P31
P30
TXT18
TXT19
TXT20
NOT3
TEN
NOT2
TC2
NOT1
TC1
NOT0
TC0
0
0
BS1
BS0
0
0
TS1
TS0
DRCS
ENABLE
OSD
PLANES
0
0
OSD LANG OSD LAN2 OSD LAN1 OSD LAN0
ENABLE
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
ADD R/W
NAME
7
6
5
4
3
2
1
0
RESET
B5H R/W
TXT21
DISP
LINES1
DISP
LINES0
CHAR SIZE1
CHAR
SIZE0
I2C PORT 1
CC ON
I2C PORT 0
CC/TXT
02H
B6H
R
TXT22
CCLIN
IP
GPF7
GPF6
0
GPF5
0
GPF4
CS4
GPF3
CS3
PT1
GPF2
CS2
GPF1
CS1
PT0
GPF0
CS0
XXH
15H
00H
00H
B7H R/W
B8H R/W
B9H R/W
0
0
0
PBUSY
PES2
PCC
PX1
PX0
TXT17
FORCE
ACQ1
FORCE
ACQ0
FORCE
DISP1
FORCE
DISP0
SCREEN
COL2
SCREEN
COL1
SCREEN
COL0
BEH R/W P3CFGA P3CFGA7
BFH R/W P3CFGB P3CFGB7
P3CFGA6
P3CFGB6
P3CFGA5
P3CFGB5
P3CFGA4
P3CFGB4
P3CFGA3
P3CFGB3
P3CFGA2
P3CFGB2
P3CFGA1
P3CFGB1
P3CFGA0
P3CFGB0
FFH
00H
00H
C0H R/W
C1H R/W
C4H R/W
TXT0
TXT1
TXT4
(reserved)
0
(reserved)
0
AUTO
FRAME
(reserved)
0
(reserved)
0
DISABLE
FRAME
(reserved)
0
(reserved)
0
(reserved)
0
(reserved)
0
(reserved)
0
(reserved)
0
(reserved)
0
FIELD
H
V
00H
00H
POLARITY POLARITY POLARITY
OSD BANK
ENABLE
QUAD
WIDTH
ENABLE
EAST/WEST DISABLE
DOUBLE
B MESH
ENABLE
C MESH
ENABLE
TRANS
ENABLE
SHADOW
ENABLE
HEIGHT
C5H R/W
C6H R/W
C7H R/W
C8H R/W
C9H R/W
TXT5
TXT6
TXT7
TXT8
TXT9
BKGND
OUT
BKGND IN
COR OUT
COR OUT
COR IN
COR IN
TEXT OUT
TEXT OUT
TEXT IN
TEXT IN
BOX ON 24
WSS
PICTURE
ON OUT
PICTURE
ON IN
03H
03H
00H
00H
00H
BKGND
OUT
BKGND IN
PICTURE
ON OUT
PICTURE
ON IN
(reserved)
0
CURSOR
ON
(reserved)
0
(reserved)0
DOUBLE
HEIGHT
BOX ON
1 − 23
BOX ON 0
(reserved)
0
FLICKER
STOP ON
(reserved)
0
DISABLE
SPANISH
PKT 26
RECEIVED RECEIVED
WSS ON
R1
CVBS1/
CVBS0
CURSOR
FREEZE
CLEAR
MEMORY
(reserved)
0
R4
R3
R2
R0
CAH R/W
CBH R/W
CCH R
TXT10
TXT11
TXT12
0
0
C5
D5
C4
D4
C3
D3
C2
D2
C1
D1
1
C0
D0
00H
00H
D7
D6
525/625
SYNC
ROM VER4 ROM VER3 ROM VER2 ROM VER1 ROM VER0
VIDEO
SIGNAL
QUALITY
XXXX
XX1X
D0H R/W
D2H R/W
D3H R/W
PSW
C
AC
TD6
1
F0
RS1
TD4
RS0
TD3
OV
TD2
−
P
00H
00H
40H
TDACL
TDACH
TD7
TD5
TD13
TD1
TD9
TD0
TD8
TPWE
TD12
TD11
TD10
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
ADD R/W
D4H R/W
D5H R/W
D6H R/W
NAME
PWM7
PWM0
PWM1
CCDAT1
S1CON
S1STA
S1DAT
S1ADR
PWM3
PWM4
PWM5
PWM6
ACC
7
6
1
5
4
3
2
1
0
RESET
40H
40H
40H
00H
00H
F8H
00H
00H
40H
40H
40H
40H
00H
40H
00H
00H
00H
PW7E
PW0E
PW1E
CCD17
CR2
PW7V5
PW0V5
PW1V5
CCD15
STA
PW7V4
PW0V4
PW1V4
CCD14
STO
PW7V3
PW0V3
PW1V3
CCD13
SI
PW7V2
PW0V2
PW1V2
CCD12
AA
PW7V1
PW0V1
PW1V1
CCD11
CR1
PW7V0
PW0V0
PW1V0
CCD10
CR0
1
1
D7H
D8H R/W
D9H
R
CCD16
ENSI
STAT3
DAT6
ADR5
1
R
STAT4
DAT7
ADR6
PW3E
PW4E
PW5E
PW6E
ACC7
PW2E
CCD27
VHI
STAT2
DAT5
STAT1
DAT4
STAT0
DAT3
0
0
0
DAH R/W
DBH R/W
DCH R/W
DDH R/W
DEH R/W
DFH R/W
E0H R/W
E4H R/W
DAT2
DAT1
DAT0
ADR4
PW3V5
PW4V5
PW5V5
PW6V5
ACC5
PW2V5
CCD25
CH0
ADR3
PW3V4
PW4V4
PW5V4
PW6V4
ACC4
PW2V4
CCD24
ST
ADR2
PW3V3
PW4V3
PW5V3
PW6V3
ACC3
PW2V3
CCD23
SAD7
B3
ADR1
PW3V2
PW4V2
PW5V2
PW6V2
ACC2
PW2V2
CCD22
SAD6
B2
ADR0
PW3V1
PW4V1
PW5V1
PW6V1
ACC1
PW2V1
CCD21
SAD5
B1
GC
PW3V0
PW4V0
PW5V0
PW6V0
ACC0
PW2V0
CCD20
SAD4
B0
1
1
1
ACC6
1
PWM2
CCDAT2
SAD
E7H
R
CCD26
CH1
B6
E8H R/W
F0H R/W
F8H R/W
B
B7
B5
B4
TXT13
(reserved)
0
PAGE
CLEARING
525
DISPLAY
(reserved)
0
(reserved)
0
(reserved)
0
(reserved)
0
(reserved)
0
XXXX
XXX0
FAH R/W XRAMP
FBH R/W ROMBK
XRAMP7
XRAMP6
0
XRAMP5
0
XRAMP4
0
XRAMP3
0
XRAMP2
0
XRAMP1
XRAMP0
00H
00H
STANDBY
(reserved)
0
(reserved)
0
FEH
W
WDTKEY
WDT
WKEY7
WDV7
WKEY6
WDV6
WKEY5
WDV5
WKEY4
WDV4
WKEY3
WDV3
WKEY2
WDV2
WKEY1
WDV1
WKEY0
WDV0
00H
00H
FFH R/W
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
Table 3 SFR bit description
BIT
FUNCTION
Accumulator (ACC)
ACC7 to ACC0
accumulator value
B Register (B)
B7 to B0
B register value
CC data byte 1 (CCDAT1)
CCD17 to CCD10
closed caption first data byte
closed caption second data byte
closed caption slice line using 525-line number
CC data byte 2 (CCDAT2)
CCD26 to CCD20
CC line (CCLIN)
CS4 to CS0
Data Pointer High byte (DPH)
DPH7 to DPH0
data pointer high byte, used with DPL to address auxiliary memory
data pointer low byte, used with DPH to address auxiliary memory
Data pointer Low byte (DPL)
DPL7 to DPL0
Interrupt Enable Register (IE)
EA
disable all interrupts (logic 0), or use individual interrupt enable bits (logic 1)
enable BUSY interrupt
enable I2C-bus interrupt
EBUSY
ES2
ECC
ET1
enable closed caption interrupt
enable Timer 1 interrupt
EX1
ET0
enable external interrupt 1
enable Timer 0 interrupt
EX0
enable external interrupt 0
Interrupt Priority Register (IP)
PBUSY
PES2
PCC
PT1
priority EBUSY interrupt
priority ES2 Interrupt
priority ECC interrupt
priority Timer 1 interrupt
priority external interrupt 1
priority Timer 0 interrupt
priority external interrupt 0
PX1
PT0
PX0
Port 0 (P0)
P07 to P00
Port 0 I/O register connected to external pins
2000 Feb 23
17
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
BIT
FUNCTION
Port 1 (P1)
P17 to P10
Port 2 (P2)
P27 to P20
Port 3 (P3)
P37 to P30
Port 1 I/O register connected to external pins
Port 2 I/O register connected to external pins
Port 3 I/O register connected to external pins; P37 to P35 are only available with
the LQFP100 package
Port 0 Configuration A (P0CFGA) and Port 0 Configuration B (P0CFGB)
P0CFGA<7:0> and P0CFGB<7:0> These two registers are used to configure Port 0 pins. For example, the I/O
configuration of Port 0 pin 3 is controlled using bit 3 in both P0CFGA and
P0CFGB. P0CFGB<x>/P0CFGA<x>:
00 = P0.x in open-drain configuration
01 = P0.x in quasi-bidirectional configuration
10 = P0.x in high-impedance configuration
11 = P0.x in push-pull configuration
Port 1 Configuration A (P1CFGA) and Port 1 Configuration B (P1CFGB)
P1CFGA<7:0> and P1CFGB<7:0> These two registers are used to configure Port 1 pins. For example, the I/O
configuration of Port 1 pin 3 is controlled using bit 3 in both P1CFGA and
P1CFGB. P1CFGB<x>/P1CFGA<x>:
00 = P1.x in open-drain configuration
01 = P1.x in quasi-bidirectional configuration
10 = P1.x in high-impedance configuration
11 = P1.x in push-pull configuration
Port 2 Configuration A (P2CFGA) and Port 2 Configuration B (P2CFGB)
P2CFGA<7:0> and P2CFGB<7:0> These two registers are used to configure Port 2 pins. For example, the I/O
configuration of Port 2 pin 3 is controlled by using bit 3 in both P2CFGA and
P2CFGB. P2CFGB<x>/P2CFGA<x>:
00 = P2.x in open-drain configuration
01 = P2.x in quasi-bidirectional configuration
10 = P2.x high-impedance configuration
11 = P2.x push-pull configuration
Port 3 Configuration A (P3CFGA) and Port 3 Configuration B (P3CFGB)
P3CFGA<7:0> and P3CFGB<7:0> These two registers are used to configure Port 3 pins. For example, the I/O
configuration of Port 3 pin 3 is controlled using bit 3 in both P3CFGA and
P3CFGB. P3CFGB<x>/P3CFGA<x>:
00 = P3.x in open-drain configuration
01 = P3.x in quasi-bidirectional configuration
10 = P3.x in high-impedance configuration
11 = P3.x in push-pull configuration
2000 Feb 23
18
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
BIT
FUNCTION
Power Control Register (PCON)
ARD
RFI
auxiliary RAM disable, all MOVX instructions access the external data memory
disable ALE during internal access to reduce radio frequency interference
Watchdog Timer enable
WLE
GF1
GF0
PD
general purpose flag
general purpose flag
Power-down mode activation bit
IDL
Idle mode activation bit
Program Status Word (PSW)
C
carry bit
AC
auxiliary carry bit
F0
flag 0, general purpose flag
register bank selector bits; RS<1:0>:
00 = Bank 0 (00H to 07H)
01 = Bank 1 (08H to 0FH)
10 = Bank 2 (10H to 17H)
11 = Bank 3 (18H to 1FH)
overflow flag
RS1 to RS0
OV
P
parity bit
Pulse Width Modulator 0 Control Register (PWM0)
PW0E
activate this PWM (logic 1)
pulse width modulator high time
PW0V5 to PW0V0
Pulse Width Modulator 1 Control Register (PWM1)
PW1E
activate this PWM (logic 1)
pulse width modulator high time
PW1V5 to PW1V0
Pulse Width Modulator 2 Control Register (PWM2)
PW2E
activate this PWM (logic 1)
pulse width modulator high time
PW2V5 to PW2V0
Pulse Width Modulator 3 Control Register (PWM3)
PW3E
activate this PWM (logic 1)
pulse width modulator high time
PW3V5 to PW3V0
Pulse Width Modulator 4 Control Register (PWM4)
PW4E
activate this PWM (logic 1)
pulse width modulator high time
PW4V5 to PW4V0
Pulse Width Modulator 5 Control Register (PWM5)
PW5E
activate this PWM (logic 1)
pulse width modulator high time
PW5V5 to PW5V0
2000 Feb 23
19
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
BIT
FUNCTION
Pulse Width Modulator 6 Control Register (PWM6)
PW6E
activate this PWM (logic 1)
pulse width modulator high time
PW6V5 to PW6V0
Pulse Width Modulator 7 Control Register (PWM7)
PW7E
activate this PWM (logic 1)
PW7V5 to PW7V0
pulse width modulator high time
Standby mode enabled (logic 1)
ROM Bank (ROMBK)
STBY
I2C-bus Slave Address Register (S1ADR)
ADR6 to ADR0
GC
I2C-bus slave address to which the device will respond
enable I2C-bus general call address (logic 1)
I2C-bus Control Register (S1CON)
CR2 to CR0
clock rate bits; CR<2:0>:
000 = 100 kHz bit rate
001 = 3.75 kHz bit rate
010 = 150 kHz bit rate
011 = 200 kHz bit rate
100 = 25 kHz bit rate
101 = 1.875 kHz bit rate
110 = 37.5 kHz bit rate
111 = 50 kHz bit rate
ENSI
STA
enable I2C-bus interface (logic 1)
START flag. When this bit is set in slave mode, the hardware checks the I2C-bus
and generates a START condition if the bus is free or after the bus becomes free.
If the device operates in master mode it will generate a repeated START
condition.
STO
STOP flag. If this bit is set in a master mode a STOP condition is generated.
A STOP condition detected on the I2C-bus clears this bit. This bit may also be set
in slave mode in order to recover from an error condition. In this case no STOP
condition is generated to the I2C-bus, but the hardware releases the SDA and
SCL lines and switches to the not selected receiver mode. The STOP flag is
cleared by the hardware.
2000 Feb 23
20
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
BIT
FUNCTION
SI
Serial Interrupt flag. This flag is set and an interrupt request is generated, after
any of the following events occur:
• A START condition is generated in master mode
• The own slave address has been received during AA = 1
• The general call address has been received while S1ADR.GC and AA = 1
• A data byte has been received or transmitted in master mode (even if arbitration
is lost)
• A data byte has been received or transmitted as selected slave
• A STOP or START condition is received as selected slave receiver or
transmitter. While the SI flag is set, SCL remains LOW and the serial transfer is
suspended. SI must be reset by software.
AA
Assert Acknowledge flag. When this bit is set, an acknowledge is returned
after any one of the following conditions:
• Own slave address is received
• General call address is received (S1ADR.GC = 1)
• A data byte is received, while the device is programmed to be a master receiver
• A data byte is received, while the device is selected slave receiver.
When the bit is reset, no acknowledge is returned. Consequently, no interrupt is
requested when the own address or general call address is received.
I2C-bus Data Register (S1DAT)
DAT7 to DAT0
I2C-bus data
I2C-bus Status Register (S1STA)
STAT4 to STAT0
I2C-bus interface status
Software ADC Register (SAD)
VHI
analog input voltage greater than DAC voltage (logic 1)
CH1 to CH0
ADC input channel select; CH<1:0>:
00 = ADC3
01 = ADC0
10 = ADC1
11 = ADC2
ST(1)
initiate voltage comparison between ADC input channel and SAD value
4 MSBs of DAC input word
SAD7 to SAD4
Software ADC Control Register (SADB)
DC_COMP
enable DC comparator mode (logic 1)
SAD3 to SAD0
4 LSBs of SAD value
stack pointer value
Stack Pointer (SP)
SP7 to SP0
2000 Feb 23
21
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
BIT
FUNCTION
Timer/Counter Control Register (TCON)
TF1
Timer 1 overflow flag. Set by hardware on timer/counter overflow. Cleared by
hardware when processor vectors to interrupt routine.
TR1
TF0
Timer 1 run control bit. Set/cleared by software to turn timer/counter on/off.
Timer 0 overflow flag. Set by hardware on timer/counter overflow. Cleared by
hardware when processor vectors to interrupt routine.
TR0
IE1
Timer 0 run control bit. Set/cleared by software to turn timer/counter on/off.
Interrupt 1 edge flag (both edges generate flag). Set by hardware when
external interrupt edge detected. Cleared by hardware when interrupt processed.
IT1
IE0
IT0
Interrupt 1 type control bit. Set/cleared by software to specify edge/LOW level
triggered external interrupts.
Interrupt 0 edge l flag. Set by hardware when external interrupt edge detected.
Cleared by hardware when interrupt processed.
Interrupt 0 type flag. Set/cleared by software to specify falling edge/LOW level
triggered external interrupts.
14-bit PWM MSB Register (TDACH)
TPWE
activate this 14-bit PWM (logic 1)
TD13 to TD8
6 MSBs of 14-bit number to be output by the 14-bit PWM
14-bit PWM LSB Register (TDACL)
TD7 to TD0
8 LSBs of 14-bit number to be output by the 14-bit PWM
Timer 0 high byte
Timer 0 High byte (TH0)
TH07 to TH00
Timer 1 High byte (TH1)
TH17 to TH10
Timer 1 high byte
Timer 0 Low byte (TL0)
TL07 to TL00
Timer 0 low byte
Timer 1 Low byte (TL1)
TL17 to TL10
Timer 1 low byte
Timer/Counter Mode Control (TMOD)
GATE
C/T
gating control Timer/Counter 1
Counter/Timer 1 selector
M1 to M0
mode control bits timer/counter 1; M<1:0>:
00 = 8-bit timer or 8-bit counter with divide-by-32 prescaler
01 = 16-bit time interval or event counter
10 = 8-bit time interval or event counter with automatic reload upon overflow;
reload value stored in TH1
11 = stopped
GATE
C/T
gating control Timer/Counter 0
Counter/Timer 0 selector
2000 Feb 23
22
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
BIT
FUNCTION
mode control bits timer/counter 0; M<1:0>:
M1 to M0
00 = 8-bit timer or 8-bit counter with divide-by-32 prescaler
01 = 16-bit time interval or event counter
10 = 8-bit time interval or event counter with automatic reload upon overflow;
reload value stored in TH0
11 = one 8-bit time interval or event counter and one 8-bit time interval counter
Text Register 0 (TXT0)
AUTO FRAME
frame output is switched off automatically if any video displayed (logic 1)
force frame output to be LOW (logic 1)
DISABLE FRAME
Text Register 1 (TXT1)
FIELD POLARITY
H POLARITY
VSYNC pulse in second half of line during even field (logic 1)
HSYNC reference edge is negative going (logic 1)
VSYNC reference edge is negative going (logic 1)
V POLARITY
Text Register 4 (TXT4)
OSD BANK ENABLE
alternate OSD location available via graphic attribute, additional 32 location
(logic 1)
QUAD WIDTH ENABLE
EAST/WEST
enable display of quadruple width characters (logic 1)
eastern character selection of character codes A0H to FFH (logic 1)
disable normal decoding of double height characters (logic 1)
enable meshing of black background (logic 1)
DISABLE DOUBLE HEIGHT
B MESH ENABLE
C MESH ENABLE
TRANS ENABLE
enable meshing of coloured background (logic 1)
display black background as video (logic 1)
SHADOW ENABLE
display shadow/fringe (default SE black) (logic 1)
Text Register 5 (TXT5)
BKGND OUT
BKGND IN
background colour displayed outside teletext boxes (logic 1)
background colour displayed inside teletext boxes (logic 1)
COR active outside teletext and OSD boxes (logic 1)
COR active inside teletext and OSD boxes (logic 1)
text displayed outside teletext boxes (logic 1)
COR OUT
COR IN
TEXT OUT
TEXT IN
text displayed inside teletext boxes (logic 1)
PICTURE ON OUT
PICTURE ON IN
video displayed outside teletext boxes (logic 1)
video displayed inside teletext boxes (logic 1)
Text Register 6 (TXT6)
BKGND OUT
BKGND IN
COR OUT
background colour displayed outside teletext boxes (logic 1)
background colour displayed inside teletext boxes (logic 1)
COR active outside teletext and OSD boxes (logic 1)
COR active inside teletext and OSD boxes (logic 1)
text displayed outside teletext boxes (logic 1)
COR IN
TEXT OUT
TEXT IN
text displayed inside teletext boxes (logic 1)
PICTURE ON OUT
video displayed outside teletext boxes (logic 1)
2000 Feb 23
23
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
BIT
PICTURE ON IN
FUNCTION
video displayed inside teletext boxes (logic 1)
Text Register 7 (TXT7)
CURSOR ON
DOUBLE HEIGHT
BOX ON 24
display cursor at position given by TXT9 and TXT10 (logic 1)
display each character as twice normal height (logic 1)
enable display of teletext boxes in memory row 24 (logic 1)
enable display of teletext boxes in memory row 1 to 23 (logic 1)
enable display of teletext boxes in memory row 0 (logic 1)
BOX ON 1 − 23
BOX ON 0
Text Register 8 (TXT8)
FLICKER STOP ON
DISABLE SPANISH
PKT 26 RECEIVED(2)
WSS RECEIVED(2)
WSS ON
disable ‘Flicker Stopper’ circuitry (logic 1)
disable special treatment of Spanish packet 26 characters (logic 1)
packet 26 data has been processed (logic 1)
wide screen signalling data has been processed (logic 1)
enable acquisition of WSS data (logic 1)
CVBS1/CVBS0
select CVBS1 as source for device (logic 1)
Text Register 9 (TXT9)
CURSOR FREEZE
CLEAR MEMORY(1)
R4 to R0(2)
lock cursor at current position (logic 1)
clear memory block pointed to by TXT15
current memory row value
Text Register 10 (TXT10)
C5 to C0(3)
current memory column value
Text Register 11 (TXT11)
D7 to D0
data value written or read from memory location defined by TXT9, TXT10 and
TXT15
Text Register 12 (TXT12)
525/625 SYNC(4)
525-line CVBS signal is being received (logic 1)
mask programmable identification for character set
acquisition can be synchronised to CVBS (logic 1)
ROM VER4 to ROM VER0
VIDEO SIGNAL QUALITY
Text Register 13 (TXT13)
PAGE CLEARING
525 DISPLAY
software or power-on page clear in progress (logic 1)
525-line synchronisation for display (logic 1)
Text Register 17 (TXT17)
FORCE ACQ1 to FORCE ACQ0
FORCE ACQ<1:0>:
00 = automatic selection
01 = force 525 timing, force 525 teletext standard
10 = force 625 timing, force 625 teletext standard
11 = force 625 timing, force 525 teletext standard
2000 Feb 23
24
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
BIT
FUNCTION
FORCE DISP1 to FORCE DISP0
FORCE DISP<1:0>:
00 = automatic selection
01 = force display to 525 mode (9 lines per row)
10 = force display to 625 mode (10 lines per row)
11 = not valid (default to 625 mode)
SCREEN COL2 to SCREEN COL0 Defines colour to be displayed instead of TV picture and black background; these
bits are equivalent to the RGB components. SCREEN COL<2:0>:
000 = transparent
001 = CLUT entry 9
010 = CLUT entry 10
011 = CLUT entry 11
100 = CLUT entry 12
101 = CLUT entry 13
110 = CLUT entry 14
111 = CLUT entry 15
Text Register 18 (TXT18)
NOT3 to NOT0
BS1 to BS0
national option table selection, maximum of 31 when used with EAST/WEST bit
basic character set selection
Text Register 19 (TXT19)
TEN
enable twist character set (logic 1)
TC2 to TC0
TS1 to TS0
language control bits (C12, C13 and C14) that has twisted character set
twist character set selection
Text Register 20 (TXT20)
DRCS ENABLE
OSD PLANES
re-map column 9 to DRCS in TXT mode (logic 1)
character code columns 8 and 9 defined as double plane characters (logic 1)
OSD LANG ENABLE
enable use of OSD LAN<2:0> to define language option for display, instead of
C12, C13 and C14
OSD LAN2 to OSD LAN0
Text Register 21 (TXT21)
DISP LINES1 to DISP LINES0
alternative C12, C13 and C14 bits for use with OSD menus
the number of display lines per character row; DISP LINES<1:0>:
00 = 10 lines per character (defaults to 9 lines in 525 mode)
01 = 13 lines per character
10 = 16 lines per character
11 = reserved (logic 1)
CHAR SIZE1 to CHAR SIZE0
character matrix size; CHAR SIZE<1:0>:
00 = 10 lines per character (matrix 12 × 10)
01 = 13 lines per character (matrix 12 × 13)
10 = 16 lines per character (matrix 12 × 16)
11 = reserved
I2C PORT 1
2000 Feb 23
enable I2C-bus Port 1 selection (P1.5/SDA1 and P1.4/SCL1) (logic 1)
25
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
BIT
FUNCTION
closed caption acquisition on (logic 1)
CC ON
I2C PORT 0
enable I2C-bus Port 0 selection (P1.7/SDA0 and P1.6/SCL0) (logic 1)
CC/TXT
display configured for CC mode (logic 1)
Text Register 22 (TXT22)
GPF7 to GPF5
GPF4
general purpose register, bits defined by mask programmable bits
reserved
GPF3
PWM0, PWM1, PWM2 and PWM3 output on Port 2.1 to Port 2.4 respectively
(logic 1)
GPF2
enable closed caption acquisition (logic 1)
reserved
GPF1 and GPF0
Watchdog Timer (WDT)
WDV7 to WDV0
Watchdog Timer period
Watchdog Timer Key (WDTKEY)
WKEY7 to WKEY0(5)
XRAMP
Watchdog Timer Key value
XRAMP7 to XRAMP0
internal RAM access upper byte address
Notes
1. This flag is set by software and reset by hardware.
2. Valid range TXT mode 0 to 24.
3. Valid range TXT mode 0 to 39.
4. Only valid when VIDEO SIGNAL QUALITY is set.
5. Must be set to 55H to disable Watchdog Timer when active.
2000 Feb 23
26
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
8.5
Character set feature bits
Features available on the OSD only devices are reflected in a specific area of the Character ROM. These sections of the
Character ROM are mapped to two Special Function Registers: TXT22 and TXT12. Character ROM address 09FEH is
mapped to SFR TXT22 as shown in Table 4. Character ROM address 09FFH is mapped to SFR TXT12 as shown in
Table 6.
Table 4 Character ROM - TXT22 mapping
U = used; X = reserved
MAPPED ITEMS
11
10
9
8
7
6
5
4
3
2
1
0
Character ROM
address 09FEH
X
X
X
X
X
X
X
X
U
U
X
X
Mapped to TXT22
−
−
−
−
7
6
5
4
3
2
1
0
Table 5 Description of Character ROM address 09FEH bits
BIT
DESCRIPTION
0 to 1
2
reserved; normally all set to logic 1
1 = enable CC acquisition
0 = disable CC acquisition
3
1 = PWM0, PWM1, PWM2 and PWM3 output routed to Port 2.1 to Port 2.4 respectively
0 = PWM0, PWM1, PWM2 and PWM3 output routed to Port 3.0 to Port 3.3 respectively
4 to 11
reserved; normally all set to logic 1
Table 6 Character ROM - TXT12 mapping
U = used; X = reserved
MAPPED ITEMS
11
10
9
8
7
6
5
4
3
2
1
0
Character ROM
address 09FFH
X
X
X
X
X
X
X
X
X
X
X
X
Mapped to TXT12
−
−
−
−
−
−
−
6
5
4
3
2
Table 7 Description of Character ROM address 09FFH bits
BIT
DESCRIPTION
0 to 11
reserved; normally all set to logic 1
2000 Feb 23
27
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
8.6
External (auxiliary) memory
8.6.1
AUXILIARY RAM PAGE SELECTION
The normal 80C51 external memory area has been
mapped internally to the device, this means that the MOVX
instruction accesses memory internal to the device.
The Auxiliary RAM page pointer is used to select one of
the 256 pages within the Auxiliary RAM, not all pages are
allocated; refer to Fig.9 for further detail. A page consists
of 256 consecutive bytes.
handbook, halfpage
7FFFH
FFFFH
8C00H
8BFFH
DYNAMICALLY
REDEFINABLE
CHARACTERS
8800H
87FFH
DISPLAY REGISTERS
87F0H
871FH
CLUT
8700H
2400H
23FFH
DISPLAY RAM
FOR
TEXT OSD
84FFH
ADDITIONAL
DATA RAM
(1)
8460H
2000H
845FH
DISPLAY RAM
FOR
CLOSED CAPTION
02FFH
DATA RAM
0000H
(1)
8000H
GSA009
lower 32 kbytes
upper 32 kbytes
(1) Display RAM for Closed Caption and Text is shared.
Fig.9 Auxiliary RAM allocation.
2000 Feb 23
28
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
FFFFH
FFH
SFR XRAMP = FFH
SFR XRAMP = FEH
00H
FFH
FF00H
FEFFH
00H
FE00H
MOVX @ Ri,A
MOVX A, @ Ri
MOVX @ DPTR,A
MOVX A, @ DPTR
01FFH
FFH
SFR XRAMP = 01H
SFR XRAMP = 00H
00H
FFH
0100H
00FFH
00H
0000H
MBK958
Fig.10 Indirect addressing of Auxiliary RAM.
2000 Feb 23
29
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
9
REDUCED POWER MODES
• The third method of terminating Idle mode is with an
external hardware reset. Since the oscillator is running,
the hardware reset need only be active for two machine
cycles (24 clocks at 12 MHz) to complete the reset
operation. Reset defines all SFRs and Display memory
to an initialized state, but maintains all other RAM
values. Code execution commences with the Program
Counter set to ‘0000’.
There are three power saving modes: Standby, Idle and
Power-down, incorporated into the OSD only device.
When utilizing any of these modes, power to the device
(VDDP, VDDC and VDDA) should be maintained, since power
saving is achieved by clock gating on a section by section
basis.
9.1
Idle mode
9.2
Power-down mode
During Idle mode, Acquisition, Display and the Central
Processing Unit (CPU) sections of the device are disabled.
The following functions remain active:
In Power-down mode the crystal oscillator is stopped.
The contents of all SFRs and Data memory are
maintained, However, the contents of the Auxiliary/Display
memory are lost. The port pins maintain the values defined
by their associated SFRs. Since the output values on RGB
and VDS are maintained the display output must be made
inactive before entering Power-down mode.
• Memory interface
• I2C-bus interface
• Timer/Counters
• Watchdog Timer
• Pulse Width Modulators.
The Power-down mode is activated by setting the PD bit in
the PCON register. It is advised to disable the Watchdog
Timer prior to entering Power-down.
To enter Idle mode the IDL bit in the PCON register must
be set. The Watchdog Timer must be disabled prior to
entering the Idle mode to prevent the device being reset.
Once in Idle mode, the crystal oscillator continues to run,
but the internal clock to the CPU, Acquisition and Display
are gated out. However, the clocks to the Memory
interface, I2C-bus interface, timer/counters, Watchdog
Timer and Pulse Width Modulators are maintained.
The CPU state is frozen along with the status of all SFRs,
internal RAM contents are maintained, as are the device
output pin values.
There are three methods of exiting Power-down mode:
• An external interrupt provides the first mechanism for
waking from Power-down. Since the clock is stopped,
external interrupts need to be set level sensitive prior to
entering Power-down. The interrupt is serviced, and
following the instruction RETI, the next instruction to be
executed will be the one after the instruction that put the
device into Power-down mode.
• A second method of exiting power-down is via an
interrupt generated by the SAD DC Compare circuit.
When the device is configured in this mode, detection of
a certain analog threshold at the input to the SAD may
be used to trigger wake-up of the device i.e. TV Front
Panel Key-press. As above, the interrupt is serviced,
and following the instruction RETI, the next instruction to
be executed will be the one following the instruction that
put the device into the Power-down.
Since the output values on Red Green Blue (RGB) and the
Video Data Switch (VDS) are maintained the display
output must be disabled before entering this mode.
There are three methods to recover from Idle mode:
• Assertion of an enabled interrupt will cause the IDL bit to
be cleared by hardware, thus terminating Idle mode.
The interrupt is serviced, and following the instruction
RETI, the next instruction to be executed will be the one
after the instruction that put the device into Idle mode.
• The third method of terminating the Power-down mode
is with an external hardware reset. Reset defines all
SFRs and Display memory, but maintains all other RAM
values. Code execution commences with the Program
Counter set to ‘0000’.
• A second method of exiting the Idle mode is via an
interrupt generated by the Software Analog-to-Digital
(SAD) DC Compare circuit. When the device is
configured in this mode, detection of an analog
threshold at the input to the SAD may be used to trigger
wake-up of the device i.e. TV Front Panel Key-press.
As above, the interrupt is serviced, and following the
instruction RETI, the next instruction to be executed will
be the one following the instruction that put the device
into Idle mode.
2000 Feb 23
30
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
9.3
Standby mode
10.2.1 OPEN-DRAIN
When Standby mode is entered both Acquisition and
Display sections are disabled. The following functions
remain active:
The open-drain configuration can be used for bidirectional
operation of a port. It requires an external pull-up resistor,
the pull-up voltage has a maximum value of 5.5 V, to allow
connection of the device into a 5 V environment.
• 80C51 core
Note that the I2C-bus ports (P1.4, P1.5, P1.6 and P1.7)
can only be configured as open-drain.
• Memory interface
• I2C-bus interface
• Timer/Counters
• Watchdog Timer
• Software ADC
10.2.2 QUASI-BIDIRECTIONAL
The quasi-bidirectional configuration is a combination of
open-drain and push-pull. It requires an external pull-up
resistor to VDDP (nominally 3.3 V). When a signal transition
from LOW-to-HIGH is output from the device, the pad is
put into push-pull configuration for one clock cycle
(166 ns) after which the pad goes into open-drain
configuration. This configuration is used to speed up the
edges of signal transitions. This is the default state of
operation of the pads after reset.
• Pulse Width Modulators
To enter Standby mode, the STANDBY control bit in the
ROMBK SFR (bit 7) must be set. It can be used in
conjunction with either Idle or Power-down modes to
switch between power saving modes. This mode enables
the 80C51 core to decode either IR remote commands or
receive I2C-bus commands without the device being fully
powered.
10.2.3 HIGH-IMPEDANCE
The Standby state is maintained upon exit from either the
Idle mode or Power-down mode. No wake-up from
Standby is necessary as the 80C51 core remains
operational.
The high-impedance configuration can be used for input
only operation of the port. When using this configuration
the two output transistors are turned off.
10.2.4 PUSH-PULL
Since the output values on RGB and VDS are maintained
the display output must be disabled before entering this
mode.
The push-pull configuration can be used for output only.
In this configuration the signal is driven to either 0 V or
VDDP, which is nominally 3.3 V.
10 I/O FACILITY
10.1 I/O ports
10.3 Port alternative functions
Ports 1, 2 and 3 are shared with alternative functions to
enable control of external devices and circuitry.
The alternative functions are enabled by setting the
appropriate SFR and also writing a logic 1 to the port bit
that the function occupies.
The SAA55xx devices have 29 I/O lines, each is
individually addressable, or form 3 parallel 8-bit
addressable ports which are Port 0, Port 1 and Port 2.
Port 3 has 5-bit parallel I/Os only.
10.2 Port type
10.4 LED support
All individual ports can be programmed to function in one
of four I/O configurations: open-drain, quasi-bidirectional,
high-impedance and push-pull. The I/O configuration is
selected using two associated Port Configuration
Registers: PnCFGA and PnCFGB (where n = port number
0, 1, 2 or 3); see Table 3.
Port pins P0.5 and P0.6 have a 8 mA current sinking
capability to enable LEDs in series with current limiting
resistors to be driven directly, without the need for
additional buffering circuitry.
2000 Feb 23
31
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
11 INTERRUPT SYSTEM
If requests of the same priority level are received
simultaneously, an internal polling sequence determines
which request is serviced. Thus, within each priority level
there is a second priority structure determined by the
polling sequence as defined in Table 8.
The device has six interrupt sources, each of which can be
enabled or disabled. When enabled each interrupt can be
assigned one of two priority levels. There are four
interrupts that are common to the 80C51, two of these are
external interrupts (EX0 and EX1) and the other two are
timer interrupts (ET0 and ET1). In addition to the
conventional 80C51, one application specific interrupt is
incorporated internal to the device which has following
functionality:
Table 8 Interrupt priority (within same level)
PRIORITY WITHIN
LEVEL
INTERRUPT
VECTOR
SOURCE
EX0
ET0
highest
0003H
000BH
0013H
001BH
002BH
0033H
• Display Busy interrupt (EBUSY). An interrupt is
generated when the display enters either a Horizontal or
Vertical Blanking Period. i.e. indicates when the
microcontroller can update the display RAM without
causing undesired effects on the screen. This interrupt
can be configured in one of two modes using the MMR
Configuration (address 87FFH, bit TXT/V):
−
EX1
−
ET1
−
−
ES2
EBUSY
lowest
– Text Display Busy. An interrupt is generated on each
active horizontal display line when the Horizontal
Blanking Period is entered
11.3 Interrupt vector address
The processor acknowledges an interrupt request by
executing a hardware generated LCALL to the appropriate
servicing routine. The interrupt vector addresses for each
source are shown in Table 8.
– Vertical Display Busy. An interrupt is generated on
each vertical display field when the Vertical Blanking
period is entered.
11.4 Level/edge interrupt
11.1 Interrupt enable structure
The external interrupt can be programmed to be either
level-activated or transition-activated by setting or clearing
the IT0/IT1 bits in the Timer Control SFR (TCON).
Each of the individual interrupts can be enabled or
disabled by setting or clearing the relevant bit in the
Interrupt Enable Register (IE). All interrupt sources can
also be globally disabled by clearing the EA bit (IE.7).
Table 9 External interrupt activation
11.2 Interrupt enable priority
ITx
0
LEVEL
active LOW
−
EDGE
−
Each interrupt source can be assigned one of two priority
levels. The interrupt priorities are defined by the Interrupt
Priority Register (IP). A low priority interrupt can be
interrupted by a high priority interrupt, but not by another
low priority interrupt. A high priority interrupt can not be
interrupted by any other interrupt source. If two requests of
different priority level are received simultaneously, the
request with the highest priority level is serviced.
1
INT0 = negative edge
INT1 = positive and negative edge
The external interrupt INT1 differs from the standard
80C51 interrupt in that it is activated on both edges when
in edge sensitive mode. This is to allow software pulse
width measurement for handling remote control inputs.
2000 Feb 23
32
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
H1
L1
highest priority level 1
EX0
highest priority level 0
H2
L2
ET0
EX1
H3
L3
H4
L4
ET1
H5
L5
ES2
lowest priority level 1
lowest priority level 0
H6
L6
EBUSY
GSA033
interrupt
source
source
enable
global
enable
priority
control
<
>
<
>
SFR IE 0:6
SFR IE.7
SFR IP 0:6
Fig.11 Interrupt structure.
2000 Feb 23
33
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
12 TIMER/COUNTER
The 8-bit timer is incremented every ‘t’ seconds where:
Two 16-bit timers/counters are incorporated Timer 0 and
Timer 1. Both can be configured to operate as either timers
or event counters.
1
1
t = 12 × 2048 ×
= 12 × 2048 ×
= 2.048 ms
--------
fosc
---------------------
12 × 106
In Timer mode, the register is incremented on every
machine cycle. It is therefore counting machine cycles.
Since the machine cycle consists of twelve oscillator
periods, the count rate is 1⁄12fosc = 1 MHz.
13.1 Watchdog Timer operation
The Watchdog operation is activated when the WLE bit in
the Power Control SFR (PCON) is set. The Watchdog can
be disabled by software by loading the value 55H into the
Watchdog Timer Key SFR (WDTKEY). This must be
performed before entering the Idle or Power-down mode to
prevent exiting the mode prematurely.
In Counter mode, the register is incremented in response
to a negative transition at its corresponding external pin T0
or T1. Since the pins T0 and T1 are sampled once per
machine cycle, it takes two machine cycles to recognise a
transition, this gives a maximum count rate of
1⁄24fosc = 0.5 MHz.
Once activated the Watchdog Timer SFR (WDT) must be
reloaded before the timer overflows. The WLE bit must be
set to enable loading of the WDT SFR, once loaded the
WLE bit is reset by hardware, this is to prevent erroneous
software from loading the WDT SFR.
There are six Special Function Registers used to control
the timers/counters. These are: TCON, TMOD, TL0, TH0,
TL1 and TH1.
The value loaded into the WDT defines the Watchdog
Interval (WI).
The timer/counter function is selected by control bits C/T in
the Timer Mode SFR (TMOD). These two Timer/Counters
have four operating modes, which are selected by bit-pairs
(M1 and M0) in TMOD. Detail of the modes of operation is
given in “Handbook IC20, 80C51-Based 8-bit
Microcontrollers”.
WI = (256 – WDT) × t = (256 – WDT) × 2.048 ms
The range of intervals is from WDT = 00H which gives
524 ms to WDT = FFH which gives 2.048 ms.
TL0 and TH0 are the actual Timer/Counter registers for
Timer 0. TL0 is the low byte and TH0 is the high byte.
TL1 and TH1 are the actual Timer/Counter registers for
Timer 1. TL1 is the low byte and TH1 is the high byte.
14 PULSE WIDTH MODULATORS
The device has eight 6-bit Pulse Width Modulated (PWM)
outputs for analog control of e.g. volume, balance, bass,
treble, brightness, contrast, hue and saturation. The PWM
outputs generate pulse patterns with a repetition rate of
21.33 µs, with the high time equal to the PWM SFR value
multiplied by 0.33 µs. The analog value is determined by
the ratio of the high time to the repetition time, a D.C.
voltage proportional to the PWM setting is obtained by
means of an external integration network (low-pass filter).
13 WATCHDOG TIMER
The Watchdog Timer is a counter that once in an overflow
state forces the microcontroller into a reset condition.
The purpose of the Watchdog Timer is to reset the
microcontroller if it enters an erroneous processor state
(possibly caused by electrical noise or RFI) within a
reasonable period of time. When enabled, the Watchdog
circuitry will generate a system reset if the user program
fails to reload the Watchdog Timer within a specified length
of time known as the Watchdog Interval (WI).
14.1 PWM control
The relevant PWM is enabled by setting the PWM enable
bit PWxE in the PWMx Control Register (where x = 0 to 7).
The high time is defined by the value PWxV<5:0>.
The Watchdog Timer consists of an 8-bit counter with an
11-bit prescaler. The prescaler is fed with a signal whose
frequency is 1⁄12fosc (1 MHz for 12 MHz oscillator).
2000 Feb 23
34
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
14.2 Tuning Pulse Width Modulator (TPWM)
The resolution of the DAC voltage with a nominal value is
3.3
⁄256 ≈ 13 mV. The external analog voltage has a lower
The device has a single 14-bit PWM that can be used for
Voltage Synthesis Tuning. The method of operation is
similar to the normal PWM except that the repetition period
is 42.66 µs.
value equivalent to VSSA and an upper value equivalent to
DDP − Vtn, where Vtn is the threshold voltage for an N type
V
Metal Oxide Semiconductor transistor. The reason for this
is that the input pins for the analog signals (P3.0 to P3.3)
are 5 V tolerant for normal port operations, i.e. when not
used as analog input. To protect the analog multiplexer
and comparator circuitry from the 5 V, a series transistor is
used to limit the voltage. This limiting introduces a voltage
drop equivalent to Vtn (≈0.6 V) on the input voltage. The
maximum value of Vtn is 0.75 V, therefore for worst case
calculations, the maximum input to the SAD should be
calculated as VDD(min) − 0.75 V. Therefore, for an input
voltage in the range VDDP to VDDP − Vtn the SAD returns
the same comparison value.
14.3 TPWM control
Two SFRs are used to control the TPWM, they are TDACL
and TDACH. The TPWM is enabled by setting the
TPWE bit in the TDACH SFR. The most significant bits
TD<13:7> alter the high period between 0 and 42.33 µs.
The seven least significant bits TD<6:0> extend certain
pulses by a further 0.33 µs, e.g. if TD<6:0> = 01H then
1 in 128 periods will be extended by 0.33 µs, if
TD<6:0> = 02H then 2 in 128 periods will be extended.
The TPWM will not start to output a new value until TDACH
has been written to. Therefore, if the value is to be
changed, TDACL should be written before TDACH.
14.4.3 SAD DC COMPARATOR MODE
The SAD module incorporates a DC Comparator mode
which is selected using the DC_COMP control bit in the
SADB SFR. This mode enables the microcontroller to
detect a threshold crossing at the input to the selected
analog input pin (P3.0/ADC0, P3.1/ADC1, P3.2/ADC2 or
P3.3/ADC3) of the software ADC. A level sensitive
interrupt is generated when the analog input voltage level
at the pin falls below the analog output level of the SAD
DAC.
14.4 Software ADC (SAD)
Four successive approximation Analog-to-Digital
Converters can be implemented in software by making use
of the on-board 8-bit Digital-to-Analog Converter and
Analog Comparator.
14.4.1 SAD CONTROL
This mode is intended to provide the device with a
wake-up mechanism from Power-down or Idle mode when
a key-press on the front panel of the TV is detected.
The control of the required analog input is done using the
channel select bits CH<1:0> in the SAD SFR, this selects
the required analog input to be passed to one of the inputs
of the comparator. The second comparator input is
generated by the DAC whose value is set by the bits
SAD<7:0> in the SAD and SADB SFRs. A comparison
between the two inputs is made when the start compare bit
ST in the SAD SFR is set, this must be at least one
instruction cycle after the SAD<7:0> value has been set.
The result of the comparison is given on VHI one
instruction cycle after the setting of ST.
The following software sequence should be used when
utilizing this mode for Power-down or Idle:
1. Disable INT1 using the IE SFR.
2. Set INT1 to level sensitive using the TCON SFR.
3. Set the DAC digital input level to the desired threshold
level using SAD/SADB SFRs and select the required
input pin (P3.0/ADC0, P3.1/ADC1, P3.2/ADC2 or
P3.3/ADC3) using CH<1:0> in the SAD SFR.
14.4.2 SAD INPUT VOLTAGE
4. Enter DC Compare mode by setting the DC_COMP
enable bit in the SADB SFR.
The external analog voltage that is used for comparison
with the internally generated DAC voltage does not have
the same voltage range. The DAC has a lower reference
5. Enable INT1 using the IE SFR.
6. Enter Power-down/Idle mode. Upon wake-up the SAD
should be restored to its conventional operating mode
by disabling the DC_COMP control bit.
level of VSSA and an upper reference level of VDDP
.
2000 Feb 23
35
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
V
handbook, halfpage
DDP
ADC0
ADC1
ADC2
ADC3
MUX
4 : 1
<
>
>
CH 1:0
VHI
<
SAD 3:0
8-BIT
DAC
<
>
SADB 3:0
MBK960
Fig.12 SAD block diagram.
2000 Feb 23
36
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
15 I2C-BUS SERIAL I/O
16.1 Memory structure
The I2C-bus consists of a serial data (SDA) line and a
serial clock (SCL) line. The definition of the I2C-bus
protocol can be found in the document “The I2C-bus and
how to use it (including specification)”. This document may
be ordered using the code 9398 393 40011.
The memory is partitioned into two distinct areas, the
dedicated Auxiliary RAM area, and the Display RAM area.
The Display RAM area when not being used for Data
Capture or Display can be used as an extension to the
auxiliary RAM area.
The device operates in four modes:
• Master transmitter
• Master receiver
16.1.1 AUXILIARY RAM
The Auxiliary RAM is not initialised at power-up.
Application software must initialize this Auxiliary RAM. The
contents of the Auxiliary RAM area, and the Display RAM
are maintained during Standby and Idle modes, but are
lost if Power-down mode is entered.
• Slave transmitter
• Slave receiver.
The microcontroller peripheral is controlled by the Serial
Control SFR (S1CON) and its status is indicated by the
Status SFR (S1STA). Information is transmitted/received
to/from the I2C-bus using the Data SFR (S1DAT) and the
Slave Address SFR (S1ADR) is used to configure the
slave address of the peripheral.
16.1.2 DISPLAY RAM
The Display RAM (Block 0 only) is initialised on power-up
to a value of 20H. The contents of the Display RAM are
maintained when entering Idle mode. If Idle mode is exited
using an interrupt then the contents are unchanged, if Idle
mode is exited using a reset then the contents are
re-initialised to 20H.
The byte level I2C-bus serial port is identical to the I2C-bus
serial port on the P8xCE558, except for the clock rate
selection bits CR<2:0> in S1CON. The operation of the
subsystem is described in detail in the “P8xCE558 data
sheet”.
Full Closed Caption display requires a display RAM from
8000H to 845FH. The memory from 8460H to 84FFH
(must be initialized by the application software) can be
utilized as an extension to the dedicated contiguous
Auxiliary RAM that occupies 000H to 02FFH.
15.1 I2C-bus port selection
Two I2C-bus ports are available SCL0/SDA0 and
SCL1/SDA1. The selection of the port is done using
TXT21.I2C PORT 0 and TXT21.I2C PORT 1. When the
port is enabled, any information transmitted from the
device goes onto the enabled port. Any information
transmitted to the device can only be acted on if the port is
enabled.
16.2 Memory mapping
The dedicated Auxiliary RAM area occupies 0.75 kbytes,
with an address range from 0000H to 02FFH. The Display
RAM occupies 1.25 kbytes with an address range from
2000H to 24FFH for TXT mode and 8000H to 84FFH for
CC mode. The two modes although having different
address ranges occupy the same physical DRAM area.
If both ports are enabled then data transmitted from the
device is seen on both ports, however data transmitted to
the device on one port can not be seen on the other port.
The hardware will only initialize 1-kbyte (block 0) of the
available 1.25 kbytes on the device. The application
software must initialize this additional 0.25 kbytes if it is to
be used as display RAM or auxiliary RAM.
16 MEMORY INTERFACE
The memory interface controls access to the embedded
DRAM, refreshing of the DRAM and page clearing.
The DRAM is shared between Data Capture, display and
microcontroller sections.
The Data Capture section uses the DRAM to store
acquired information that has been requested. The display
reads from the DRAM information and converts it into RGB
values. The microcontroller uses the DRAM as embedded
auxiliary RAM.
2000 Feb 23
37
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
16.3 Addressing memory
16.4 Page clearing
Page clearing is performed on request from the
microcontroller under the control of the embedded
software.
The memory can be addressed by the microcontroller in
two ways, either directly using a MOVX command, or via
Special Function Registers depending on what address is
required.
At power-on and reset the Text Display memory (from
2000H to 23FFH) is cleared to the value of 20H.
The TXT13.PAGE CLEARING bit will be set while this
takes place.
The dedicated Auxiliary RAM, and Display memory in the
range 8000H to 84FFH, can only be accessed using the
MOVX command.
The Display memory in the range 2000H to 23FFH can
either be directly accessed using the MOVX, or via the
Special Function Registers.
16.4.1 DATA CAPTURE PAGE CLEAR
Not present in the SAA55xx OSD only devices.
16.3.1 TXT DISPLAY MEMORY SFR ACCESS
16.4.2 SOFTWARE PAGE CLEAR
The Display memory when in TXT mode (see Fig.14) is
configured as 40 columns wide by 25 rows and occupies
1K × 8 bits of memory. The row and column is selected
using TXT9.R<4:0> and TXT10.C<5:0>. The data at the
selected position can be read or written using
TXT11.D<7:0>.
The software can also initiate a page clear, by setting the
TXT9.CLEAR MEMORY bit. The CLEAR MEMORY bit is
not latched so the software does not have to reset it after
it has been set.
Only one page can be cleared in a TV line so if the
software requests a page clear it will be carried out on the
next TV line on which the Data Capture hardware does not
force the page to be cleared. A flag, TXT13.PAGE
CLEARING, is provided to indicate that a software
requested page clear is being carried out. The flag is set
when a logic 1 is written into the TXT9.CLEAR MEMORY
bit and is reset when the page clear has been completed.
Whenever a read or write is performed on TXT11, the row
values stored in TXT9 and column value stored in TXT10
are automatically incremented. For rows 0 to 24 the
column value is incremented up to a maximum of 39, at
which point it resets to a logic 0 and increments the row
counter value. When row 25 column 23 is reached the
values of the row and column are both reset to logic 0.
Inventory page clearing in not present in the SAA55xx
OSD only devices.
Writing values outside of the valid range for TXT9 or
TXT10 will cause undetermined operation of the
auto-incrementing function for accesses to TXT11.
16.3.2 TXT DISPLAY MEMORY MOVX ACCESS
It is important for the generation of OSD displays, that use
this mode of access, to understand the mapping of the
MOVX address onto the display row and column value.
This mapping of row and column onto address is shown in
Table 10. The values shown are added onto a base
address for the required memory block (see Fig.13) to give
a 16-bit address.
Table 10 Column and row to MOVX address (lower 10 bits of address)
ROW
Row 0
Row 1
...
COL.0
000H
020H
...
...
...
...
...
...
...
...
COL.23
017H
037H
...
...
...
...
...
...
...
...
COL.31
01FH
03FH
...
COL.32
3F8H
3F0H
...
...
...
...
...
...
...
...
COL.39
3FFH
3F7H
...
Row 23
Row 24
Row 25
2E0H
300H
320H
3F7H
317H
337H
2FFH
31FH
340H
338H
347H
33FH
2000 Feb 23
38
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
lower 32 kbytes
upper 32 kbytes
7FFFH
FFFFH
handbook, halfpage
23FFH
2000H
TEXT DISPLAY
AUXILIARY
84FFH
8000H
02FFH
0000H
CC DISPLAY
GSA011
Fig.13 DRAM memory mapping.
2000 Feb 23
39
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
Column
0
10
20
30
39
Row 0
1
C
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
control data
non-displayable data
(byte 10 reserved)
0
9 10
23
<
>
<
>
active position TXT9.R 4:0 = 01H, TXT10.C 5:0 = 0AH, TXT11 = 43H
MBK962
Fig.14 TXT memory map.
2000 Feb 23
40
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
17 DATA CAPTURE
17.1.4 DATA CAPTURE TIMING
The Data Capture section takes in the analog Composite
Video and Blanking Signal (CVBS), and from this extracts
the required data, which is then decoded and stored in
memory.
The Data Capture timing section uses the synchronisation
information extracted from the CVBS signal to generate
the required horizontal and vertical reference timings.
The timing section automatically recognizes and selects
the appropriate timings for either 625 (50 Hz)
synchronisation or 525 (60 Hz) synchronisation.
The extraction of the data is performed in the digital
domain. The first stage is to convert the analog
CVBS signal into a digital form. This is done using an ADC
sampling at 12 MHz. The data and clock recovery is then
performed by a Multi-Rate Video Input Processor
(MulVIP). From the recovered data and clock, the serial
Closed Captioning data is converted to parallel and stored
as two bytes per line. The extracted data is stored in
SFR locations.
A flag TXT12.VIDEO SIGNAL QUALITY is set when the
timing section is locked correctly to the incoming CVBS
signal. When TXT12.VIDEO SIGNAL QUALITY is set
another flag TXT12.525/625 SYNC can be used to identify
the standard.
17.1.5 LINE 21 DATA SERVICES
17.1 Data Capture features
The Line 21 Data Services is transmitted on line 21 of a
525-line broadcast system and is used for Captioning
information, Text information and Extended Data Services.
Full Details can be found in “Recommended Practise for
Line 21 Data Service EIA-608”.
• Two CVBS inputs
• Data Capture for Line 21 Data Service
• Video Signal Quality Detector.
Closed Caption Line 21 data is only acquired when
TXT21.CC ON bit is set.
17.1.1 CVBS SWITCH
The CVBS switch is used to select the required analog
input depending on the value of TXT8.CVBS1/CVBS0.
Two bytes of data are stored per field in SFRs, the first bye
is stored in CCDAT1 and the second byte is stored in
CCDAT2. The contents of each CCDAT register are reset
to 00H at the start of the Closed Caption line defined by
CCLIN.CS<4:0>. At the end of the Closed Caption line an
interrupt is generated if IE.ECC is active.
17.1.2 ANALOG-TO-DIGITAL CONVERTER
The output of the CVBS switch is passed to a differential
to single ended converter, although in this device it is used
in single ended configuration with a reference. The analog
output of the differential to single ended converter is
converted into a digital representation by a full-flash ADC
with a sampling rate of 12 MHz.
The processing of the Closed Caption data to convert into
a displayable format is performed by software.
17.1.3 MULTI-RATE VIDEO INPUT PROCESSOR
The multi-rate video input processor is a Digital Signal
Processor designed to extract the data and recover the
clock from a digitized CVBS signal. The only data and
clock standard that can be recovered in the OSD only
devices is Closed Caption at a data rate of approximately
503.5 kHz.
2000 Feb 23
41
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
CVBS0 CVBS1
CVBS
SWITCH
CVBS
SYNC
SEPARATOR
ADC
SYNC_FILTER
<
>
data 7:0
VCS
DATA SLICER
ACQUISITION
TIMING
AND
CLOCK RECOVERY
TTC
TTD
ACQUISITION
FOR
CC/WSS
GSA010
output data to SFRs
Fig.15 Data Capture block diagram.
18 DISPLAY
• Globally selectable scan lines per row 9, 10, 13 or 16
• Globally selectable character matrix (H × V) 12 × 9,
12 × 10, 12 × 13 or 12 × 16
The display section is based on the requirements for US
Closed Caption. There are some enhancements for use
with locally generated On-Screen Displays.
• Italics
• Soft colours using CLUT with 4096 colour palette
• Underline
The display section reads the contents of the Display
memory and interprets the control/character codes. From
this information and other global settings, the display
produces the required RGB signals and video/data (Fast
Blanking) signal for a TV signal processing device.
• Overline
• Fringing (shadow) selectable from N-S-E-W direction
• Fringe colour selectable
• Meshing of defined area
• Contrast reduction of defined area
• Cursor
The display is synchronised to the TV signal processing
device by way of horizontal and vertical sync signals
provided by external circuits (Slave Sync mode). From
these signals all display timings are derived.
• Special Graphics characters with two planes, allowing
four colours per character
18.1 Display features
• Teletext style OSD and Enhanced OSD modes
• US Closed Caption features
• 32 software redefinable On-Screen Display characters
• 4 WST character sets (G0/G2) in single device
(e.g. Latin, Cyrillic, Greek, Arabic)
• Serial and Parallel display attributes
• Single/double/quadruple width and height for characters
• Scrolling of display region
• G1 Mosaic graphics, Limited G3 Line drawing
characters
• Variable flash rate controlled by software
• WST character sets and Closed (including extended)
Caption character set in a single device.
2000 Feb 23
42
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
CLK
VSYNC
HSYNC
DISPLAY
TIMING
address
data
PARALLEL/SERIAL
CONVERTER
AND FRINGING
address
data
control
MICROPROCESSOR
INTERFACE
FUNCTION
REGISTERS
address
address
data
DISPLAY DATA
ADDRESSING
ATTRIBUTE
HANDLING
to memory interface
from memory interface
data
DATA
BUFFER
CLUT RAM
data
CHARACTER
ROM
CHARACTER
FONT
ADDRESSING
AND
DRCs
address
DAC
DAC
G
DAC
MBK965
R
B
FB
Fig.16 Display block diagram.
43
2000 Feb 23
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
18.2 Display modes
TXT: This attribute is set by the control character ‘flash’
(08H) and remains valid until the end of the row or until
reset by the control character ‘steady’ (09H).
The display section has two distinct modes with different
features available in each. The two modes are:
• TXT: This is the display configured for WST with
additional serial and global attributes. The display is
configured as a fixed 25 rows with 40 characters per
row. In the OSD only family this mode can only be
utilised for display of Text style OSD, no Teletext Data
Capture is present.
18.3.2 BOXES
CC: This attribute is valid from the time set until end of row
or otherwise modified if set with Serial Mode 0. If set with
Serial Mode 1, then it is set from the next character
onwards.
In Text mode (within CC mode) the background colour is
displayed regardless of the setting of the box attribute bit.
Boxes take effect only during mixed mode, where boxes
are set in this mode the background colour is displayed.
Character locations where boxes are not set show
video/screen colour (depending on the setting in the
MMR Display Control) instead of the background colour.
• CC: This is the display configured as the US Closed
Caption mode. The display is configured as a maximum
of 16 rows with a maximum of 48 characters per row.
In both of the above modes the character matrix, and
TV lines per row can be defined. There is an option of
9, 10, 13 and 16 TV lines per display row, and a character
matrix (H × V) of 12 × 9, 12 × 10, 12 × 13 or 12 × 16. Not all
combinations of TV lines per row and maximum display
rows give a sensible OSD display, since there is a limited
number of TV scan lines available.
TXT: Two types of boxes exist, the teletext box and the
OSD box. The teletext box is activated by the ‘start box’
control character (0BH). Two start box characters are
required to begin a teletext box, with the box starting
between the 2 characters. The box ends at the end of the
line or after a ‘end box’ control character.
Special Function Register TXT21 and memory mapped
registers are used to control the mode selection.
TXT mode can also use OSD boxes, they are started using
size, implying OSD control characters (BCH, BDH, BEH
and BFH). The box starts after the control character (set
after) and ends either at the end of the row or at the next
size implying OSD character (set at).
18.3 Display feature descriptions
All display features are now described in detail for both
TXT and CC modes.
18.3.1 FLASH
The attributes flash, teletext box, conceal, separate
graphics, twist and hold graphics are all reset at the start
of an OSD box, as they are at the start of the row.
OSD boxes are only valid in TV mode which is defined by
TXT5 = 03H and TXT6 = 03H.
Flashing causes the foreground colour pixel to be
displayed as the background pixels.The flash frequency is
controlled by software setting and resetting the MMR
Status (see Table 28) at the appropriate interval.
CC: This attribute is valid from the time set (see Table 16)
until the end of the row or until otherwise modified.
2000 Feb 23
44
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
18.3.3 SIZE
Three vertical sizes are available normal (×1), double (×2)
and quadruple (×4). The control characters ‘normal size’
(0CH/BCH) enable normal size, the ‘double height’ or
‘double size’ (0DH/BDH/0FH/BFH) enable double height
characters. Quadruple height characters are achieved by
using double height characters and setting the global
attributes TXT7.DOUBLE HEIGHT (expand) and
TXT7.BOTTOM/TOP.
The size of the characters can be modified in both the
horizontal and vertical directions.
CC: Two sizes are available in both the horizontal and
vertical directions. The sizes available are normal (×1),
double (×2) height/width and any combination of these.
The attribute setting is always valid for the whole row.
Mixing of sizes within a row is not possible.
If double height characters are used in Teletext mode,
single height characters in the lower row of the double
height character are automatically disabled.
TXT: Three horizontal sizes are available normal (×1),
double (×2) and quadruple (×4). The control characters
‘normal size’ (0CH/BCH) enables normal size, the ‘double
width’ or ‘double size’ (0EH/BEH/0FH/BFH) enables
double width characters.
18.3.4 ITALIC
CC: This attribute is valid from the time set until the end of
the row or otherwise modified. The attribute causes the
character foreground pixels to be offset horizontally by
1 pixel per 4 scan lines (interlaced mode). The base is the
bottom left character matrix pixel. The pattern of the
character is indented as shown in Fig.17.
Any two consecutive combination of ‘double width’ or
‘double size’ (0EH/BEH/0FH/BFH) activates quadruple
width characters, provided quadruple width characters are
enabled by TXT4.QUAD WIDTH ENABLE.
TXT: The Italic attribute is not available.
12 × 16 character matrix
12 × 13 character matrix
8 10 0
12 × 10 character matrix
8 10 0 2 4 6 8 10
0
2
4
6
8 10 0
2
4
6
8 10 0
2
4
6
2
4
6
8 10 0
2
4
6
0
1
indented by 7/6/4
2
indented by 6/5/3
indented by 5/4/2
3
4
5
6
indented by 4/3/1
indented by 3/2/0
indented by 2/1
indented by 1/0
7
8
9
10
11
12
13
14
15
indented by 0
MBK970
Field 1
Field 2
Fig.17 Italic characters.
2000 Feb 23
45
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
18.3.5 COLOURS
18.3.7 BACKGROUND COLOUR
A CLUT (Colour Look-Up Table) with 16 colour entries is
provided. The colours are programmable out of a palette
of 4096 (4 bits per R, G and B). The CLUT is defined by
writing data to a RAM that resides in the MOVX address
space of the 80C51.
CC: This attribute is valid from the time set until end of row
or otherwise modified if set with Serial Mode 0. If set with
Serial Mode 1, then the colour is set from the next
character onwards.
The background colour can be chosen from all 16 CLUT
entries.
Table 11 CLUT colour values
TXT: The control character ‘new background’ (1DH) is
used to change the background colour to the current
foreground colour. The selection is immediate (set at) and
remains valid until the end of the row or until otherwise
modified.
RED<3:0> GREEN<3:0 BLUE<3:0> COLOUR
(B11 TO B8) >(B7 TO B4) (B3 TO B0)
ENTRY
0000
0000
....
0000
0000
....
0000
1111
....
0
1
....
14
15
The Text background control characters map to the CLUT
entries as shown in Table 13.
1111
1111
1111
1111
0000
1111
Table 13 Background CLUT mapping
18.3.6 FOREGROUND COLOUR
CONTROL
CODE
DEFINED
COLOUR
CLUT ENTRY
CC: The foreground colour can be chosen from 8 colours
on a character-by-character basis. Two sets of 8 colours
are provided. A serial attribute switches between the
banks (see Table 16, Serial Mode 1, bit 7). The colours are
the CLUT entries 0 to 7 or 8 to 15.
00H + 1DH
01H + 1DH
02H + 1DH
03H + 1DH
04H + 1DH
05H + 1DH
06H + 1DH
07H + 1DH
black
red
8
9
green
yellow
blue
10
11
12
13
14
15
TXT: The foreground colour is selected via a control
character (see Table 16). The colour control characters
take effect at the start of the next character (set-after) and
remain valid until the end of the row, or until modified by a
control character. Only 8 foreground colours are available.
magenta
cyan
white
The text foreground control characters map to the CLUT
entries is shown in Table 12.
18.3.8 BACKGROUND DURATION
The attribute when set takes effect from the current
position until the end of the text display defined in the MMR
Text Area End.
Table 12 Foreground CLUT mapping
CONTROL
CODE
DEFINED
COLOUR
CLUT ENTRY
CC: The background duration attribute (see Table 16,
Serial Mode 1, bit 8) in combination with the End Of Row
attribute (see Table 16, Serial Mode 1, bit 9) forces the
background colour to be displayed on the row until the end
of the text area is reached.
00H
01H
02H
03H
04H
05H
06H
07H
black
red
0
1
2
3
4
5
6
7
green
yellow
blue
TXT: This attribute is not available.
magenta
cyan
white
2000 Feb 23
46
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
18.3.9 UNDERLINE
CC: The fringe attribute (see Table 16, Serial Mode 0,
bit 9) is valid from the time set until the end of the row or
otherwise modified.
The underline attribute causes the characters to have the
bottom scan line of the character cell forced to foreground
colour, including spaces. If background duration is set,
then underline is set until the end of the text area.
TXT: The display of fringing in TXT mode is controlled by
the TXT4.SHADOW ENABLE bit.
CC: The underline attribute (see Table 16, Serial Mode
0/1, bit 4) is valid from the time set until the end of row or
otherwise modified.
When set, all the alphanumeric characters being displayed
are shadowed, graphics characters are not shadowed.
18.3.13 MESHING
TXT: This attribute is not available.
The attribute effects the background colour being
displayed. Alternate pixels are displayed as the
background colour or video.The structure is offset by
1 pixel from scan line to scan line, thus achieving a
checker board display of the background colour and video.
An example of meshing is shown in Fig.19.
18.3.10 OVERLINE
The overline attribute causes the characters to have the
top scan line of the character cell forced to foreground
colour, including spaces. If background duration is set,
then overline is set until the end of the text area.
CC: The setting of the MSH bit in MMR Display Control
has the effect of meshing any background colour.
CC: The overline attribute (see Table 16, Serial Mode 0/1,
bit 5) is valid from the time set until end of row or otherwise
modified. Overlining of italic characters is not possible.
TXT: There are two meshing attributes one that only
affects black background colours TXT4.B MESH ENABLE
and a second that only affects backgrounds other than
black TXT4.C MESH ENABLE. A black background is
defined as CLUT entry 8, a non-black background is
defined as CLUT entry 9 to 15.
TXT: This attribute is not available.
18.3.11 END OF ROW
CC: The number of characters in a row is flexible and can
be determined by the end of row attribute (see Table 16,
Serial Mode 1, bit 9). However, the maximum number of
character positions displayed is determined by the setting
of the MMR Text Position Horizontal and MMR Text Area
End.
18.3.14 CURSOR
The cursor operates by reversing the background and
foreground colours in the character position pointed to by
the active cursor position. The cursor is enabled using
TXT7.CURSOR ON. When active, the row the cursor
appears on is defined by TXT9.R<4:0> and the column is
defined by TXT10.C<5:0>. The position of the cursor can
be fixed using TXT9.CURSOR FREEZE. The cursor
display is shown in Fig.20.
Note that when using the end of row attribute the next
character location after the attribute should always be
occupied by a ‘space’.
TXT: This attribute is not available, row length is fixed at
40 characters.
CC: The valid range for row is 0 to 15. The valid range for
column is 0 to 47. The cursor remains rectangular at all
times, its shape is not affected by italic attribute, therefore
it is not advised to use the cursor with italic characters.
18.3.12 FRINGING
A fringe (shadow) can be defined around characters. The
fringe direction is individually selectable in any of the
North, South, East and West direction using the MMR
Fringing Control. The colour of the fringe can also be
defined as one of the entries in the CLUT, again using
MMR Fringing Control. An example of south and
south-west fringing is shown in Fig.18.
TXT: The valid range for row positioning is 0 to 24.
The valid range for column is 0 to 39.
2000 Feb 23
47
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
MBK972
Fig.18 South and south-west fringing.
MBK973
Fig.19 Meshing and Meshing/fringing (south + west).
A B C D E F
MBK971
Fig.20 Cursor display.
48
2000 Feb 23
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
18.3.15 SPECIAL GRAPHICS CHARACTERS
Table 14 Special character colour allocation
CC/TXT: Several special characters are provided for
improved OSD effects. These characters provide a choice
of four colours within a character cell. The total number of
special graphics characters is limited to 16. They are
stored in the character codes 8XH and 9XH of the
character table (32 ROM characters), or in the DRCs
which overlay character codes 8XH and 9XH. Each
special graphics character uses two consecutive normal
characters.
PLANE 1 PLANE 0
COLOUR ALLOCATION
0
0
1
1
0
1
0
1
background colour
foreground colour
CLUT entry 6
CLUT entry 7
If the screen colour is transparent (implicit in mixed mode)
and inside the object the box attribute is set, then the
object is surrounded by video. If the box attribute is not set
the background colour inside the object will also be
displayed as transparent.
Fringing, underline and overline is not possible for special
graphics characters. Special graphics characters are
activated when TXT20.OSD PLANES = 1.
background colour
"set at" (Mode 0)
serial attribute
background colour
"set after" (Mode 1)
VOLUME
foreground colour
normal character
background colour
foreground colour 6
foreground colour 7
special character
MGK550
This example could also be done with 8 special characters.
Fig.21 Special character example.
2000 Feb 23
49
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
18.4 Character and attribute coding
Table 15 Parallel character coding
BITS DESCRIPTION
0 to 7 8 bit character code
This section describes the character and attribute coding
for each mode.
8 to 10
11
3 bits for 8 foreground colours
mode bit: 0 = Parallel code
18.4.1 CC MODE
Character coding is split into character oriented attributes
(parallel) and character group coding (serial). The serial
attributes take effect either at the position of the attribute
(set at), or at the following location (set after) and remain
effective until either modified by a new serial attribute or
until the end of the row. A serial attribute is represented as
a space (the space character itself however is not used for
this purpose), the attributes that are still active,
e.g. overline and underline will be visible during the display
of the space.
18.4.2 TXT MODE
Character coding is in a serial format, with only one
attribute being changed at any single location. The serial
attributes take effect either at the position of the attribute
(set at), or at the following location (set after). The attribute
remains effective until either modified by new serial
attributes or until the end of the row.
The default settings at the start of a row are:
• Foreground colour white (CLUT address 7)
• Background colour black (CLUT address 8)
• Horizontal size ×1, vertical size ×1 (normal size)
• Alphanumeric on
The default setting at the start of a row is:
• ×1 size
• Flash off
• Overline off
• Contiguous mosaic graphics
• Release mosaics
• Underline off
• Italics off
• Flash off
• Display mode = superimpose
• Fringing off
• Box off
• Conceal off
• Background colour duration = 0
• End of row = 0.
• Twist off.
The attributes have individual codes which are defined in
the basic character table (see Fig.22).
The coding is done in 12-bit words. The codes are stored
sequentially in the Display memory. A maximum of
768 character positions can be defined for a single display.
2000 Feb 23
50
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
Table 16 Serial character coding
DESCRIPTION
BIT
SERIAL MODE 1
SERIAL MODE 0
(SET AT)
CHAR.POS. 1 (SET AT)
CHAR.POS. >1 (SET AFTER)
0 to 3 4 bits for 16 background colours
4 bits for 16 background colours
4 bits for 16 background colours
4
5
6
7
8
Underline switch:
0 = underline off
1 = underline on
Horizontal size:
0 = normal
1 = ×2
Underline switch:
0 = underline off
1 = underline on
Overline switch:
0 = overline off
1 = overline on
Vertical size:
0 = normal
1 = ×2
Overline switch:
0 = overline off
1 = overline on
Display mode:
0 = superimpose
1 = boxing
Display mode:
0 = superimpose
1 = boxing
Display mode:
0 = superimpose
1 = boxing
Flash switch:
0 = flash off
1 = flash on
Foreground colour switch:
0 = Bank 0 (colours 0 to 7)
1 = Bank 1 (colours 8 to 15)
Foreground colour switch:
0 = Bank 0 (colours 0 to 7)
1 = Bank 1 (colours 8 to 15)
Italics switch
0 = italics off
1 = italics on
Background colour duration:
0 = stop BGC
1 = set BGC to end of row
Background colour duration (set
at):
0 = stop BGC
1 = set BGC to end of row
9
Fringing switch:
0 = fringing off
1 = fringing on
End of row:
0 = continue row
1 = end row
End of row (set at):
0 = continue row
1 = end row
10
11
Switch for serial coding:
0 = mode 0
1 = mode 1
Switch for serial coding:
0 = mode 0
1 = mode 1
Switch for serial coding
0 = mode 0
1 = mode 1
Mode bit:
Mode bit:
Mode bit:
1 = serial code
1 = serial code
1 = serial code
2000 Feb 23
51
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
E/W = 0
1
E/W = 1
1 1
B
I
T
S
b
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
7
b
0
0
0
0
1
0
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
6
b
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
1
1
5
b
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
4
b
b
b
b
3
2 1
column
r
0
1
2
2a
3
3a
4
5
6
6a
7
7a
8
8a
9
9a
A
B
C
D
E
F
D
E
F
o
w
back-
ground
black
alpha
black
graphics
black
nat
opt
nat
opt
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
OSD
OSD
OSD
OSD
OSD
OSD
OSD
back
ground
red
alpha
red
graphics
red
OSD
OSD
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
back-
ground
green
graphics
green
alpha
green
2
3
OSD
OSD
OSD
back-
ground
yellow
graphics
yellow
alpha
yellow
nat
opt
OSD
OSD
OSD
OSD
OSD
OSD
OSD
OSD
back-
ground
blue
alpha
blue
graphics
blue
nat
opt
4
back-
ground
magenta
graphics
magenta
alpha
magenta
OSD
OSD
OSD
OSD
OSD
OSD
OSD
OSD
OSD
OSD
OSD
OSD
OSD
OSD
OSD
OSD
OSD
OSD
OSD
OSD
OSD
OSD
OSD
OSD
5
back-
ground
cyan
alpha
cyan
graphics
cyan
6
back-
ground
white
alpha
white
graphics
white
7
conceal
display
8
flash
contiguous
graphics
9
steady
separated
graphics
A
B
C
D
E
F
end box
start box
nat
opt
nat
opt
twist
OSD
OSD
OSD
OSD
OSD
OSD
OSD
OSD
black
back -
ground
normal
size
OSD
nat
opt
nat
opt
normal
height
new
back -
ground
double
height
OSD
double
height
nat
opt
nat
opt
OSD
OSD
OSD
OSD
OSD
OSD
OSD
OSD
OSD
OSD
OSD
OSD
double
width
OSD
hold
graphics
nat
opt
nat
opt
double
width
double
size
OSD
double
size
release
graphics
nat
opt
MBK974
nat
opt
character dependent on the language of page, refer to National Option characters
customer definable On-Screen Display character
OSD
ahdnbok,uflapegwidt
Fig.22 TXT basic character set (Pan-European).
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
18.5 Screen and global controls
18.5.3 DISPLAY MODES
A number of attributes are available that affect the whole
display region, and cannot be applied selectively to
regions of the display.
CC: When attributes superimpose or boxing (see
Table 16, Serial Mode 0/1, bit 6) are set, the resulting
display depends on the setting of the following screen
control mode bits in the MMR Display Control.
18.5.1 TV SCAN LINES PER ROW
TXT: The display mode is controlled by the bits in the
TXT5 and TXT6 registers. There are three control
functions - Text on, Background on and Picture on.
Separate sets of bits are used inside and outside teletext
boxes so that different display modes can be invoked.
TXT6 is used if the newsflash (C5) or subtitle (C6) bits in
row 25 of the basic page memory are set otherwise TXT5
is used. This allows the software to set up the type of
display required on newsflash and subtitle pages (e.g. text
inside boxes, TV picture outside) this will be invoked
without any further software intervention when such a
page is acquired.
The number of TV scan lines per field used for each
display row can be defined, the value is independent of the
character size being used. The number of lines can be
either 10, 13 or 16 per display row. The number of TV scan
lines per row is defined TXT21.DISP LINES<1:0>.
A value of 9 lines per row can be achieved if the display is
forced into 525-line display mode by
TXT17.FORCE DISP<1:0>, or if the device is in 10 line
mode and the automatic detection circuitry within display
finds 525-line display syncs.
18.5.2 CHARACTER MATRIX (H X V)
When teletext box control characters are present in the
display page memory, the appropriate box control bit must
be set, TXT7.BOX ON 0, TXT7.BOX ON 1 − 23 or
TXT7.BOX ON 24. This allows the display mode to be
different inside the teletext box compared to outside.
These bits are present to allow boxes in certain areas of
the screen to be disabled. The use of teletext boxes for
OSD messages has been superseded in this device by the
OSD box concept, but these bits remain to allow teletext
boxes to be used, if required.
There are three different character matrices available,
these are 12 x 10, 12 x 13 and 12 x 16. The selection is
made using TXT21.CHAR SIZE<1:0> and is independent
of the number of display lines per row.
If the character matrix is less than the number of TV scan
lines per row then the matrix is padded with blank lines. If
the character matrix is greater than the number of TV scan
lines then the character is truncated.
Table 17 Display modes
MOD 0 MOD 1
DISPLAY MODE
Video
Full Text
DESCRIPTION
0
1
0
0
Disables all display activities, sets the RGB to true black and VDS to video.
Displays screen colour at all locations not covered by character foreground
or background colour. The box attribute has no effect.
0
1
1
1
Mixed Screen Colour Displays screen colour at all locations not covered by character foreground,
within boxed areas or, background colour.
Mixed Video
Mixed Video mode displays video at all locations not covered by character
foreground, within boxed areas or, background colour.
Table 18 TXT display control bits
PICTURE ON
TEXT ON
BACKGROUND ON
EFFECT
Text mode, black screen
0
0
0
1
1
1
0
1
1
0
1
1
X
0
1
X
0
1
Text mode, background always black
Text mode
Video mode
Mixed text and TV mode
Text mode, TV picture outside text area
18.5.4 SCREEN COLOUR
2000 Feb 23
53
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
Screen colour is displayed from 10.5 ms to 62.5 ms after
the active edge of the HSYNC input and on TV lines
23 to 310 inclusive, for a 625-line display, and lines
17 to 260 inclusive for a 525-line display.
18.6.2 DISPLAY MAP
The display map allows a flexible allocation of data in the
memory to individual rows.
Sixteen words are provided in the display memory for this
purpose. The lower 10 bits address the first word in the
memory where the row data starts. This value is an offset
in terms of 16-bit words from the start of Display memory
(8000H). The most significant bit enables the display when
not within the scroll (dynamic) area.
CC: The screen colour is defined by the MMR Display
Control and points to a location in the CLUT table.
The screen colour covers the full video width. It is visible
when the Full Text or Mixed Screen Colour mode is set
and no foreground or background pixels are being
displayed.
The display map memory is fixed at the first 16 words in
the Closed Caption display memory.
TXT: The register bits TXT17.SCREEN COL<2:0> can be
used to define a colour to be displayed in place of
TV picture and the black background colour. If the bits are
all set to zero, the screen colour is defined as ‘transparent’
and TV picture and background colour are displayed as
normal. Otherwise the bits define CLUT entries 9 to 15.
Table 19 Display map bit allocation
BIT
FUNCTION
11
Text display enable, valid outside soft
scroll area. 0 = disable; 1 = enable.
18.6 Text display controls
10
This bit is reserved, should be set to
logic 0.
18.6.1 TEXT DISPLAY CONFIGURATION (CC MODE)
9 to 0
Pointer to row data.
Two types of areas are possible. The one area is static and
the other is dynamic. The dynamic area allows scrolling of
a region to take place. The areas cannot cross each other.
Only one scroll region is possible.
2000 Feb 23
54
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
Display memory
Text area
ROW
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
10
11
3
4
9
display
possible
soft scrolling
display possible
Enable
bit = 0
display
map
entries
10
10
11
12
13
14
15
11
12
13
14
15
display
possible
MBK966
display
data
Fig.23 Display map and data pointers.
2000 Feb 23
55
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
18.6.3 SOFT SCROLL ACTION
If the number of rows allocated to the scroll counter is
larger than the defined visible scroll area, this allows parts
of rows at the top and bottom to be displayed during the
scroll function. The registers can be written throughout the
field and the values are updated for display with the next
field sync. Care should be taken that the register pairs are
written to by the software in the same field.
The dynamic scroll region is defined by the MMR Scroll
Area, MMR Scroll Range, MMR Top Scroll line and the
MMR Status. The scroll area is enabled when the SCON
bit is set in MMR Status.
The position of the soft scroll area window is defined using
the Soft Scroll Position (SSP<3:0>), and the height of the
window is defined using the Soft Scroll Height (SSH<3:0>)
both are in MMR Scroll Range. The rows that are scrolled
through the window are defined using the Start Scroll Row
(STS<3:0>) and the Stop Scroll Row (SPS<3:0>) both are
in MMR Scroll Area.
Only a region that contains only single height rows or only
double height rows can be scrolled.
TXT: The display is organised as a fixed size of 25 rows
(0 to 24) of 40 columns (0 to 39), This is the standard size
for teletext transmissions. The control data in row 25 is not
displayed but is used to configure the display page
correctly.
The soft scrolling function is done by modifying the Scroll
Line (SCL<3:0>) in MMR Top Scroll Line. and the first
scroll row value SCR<3:0> in the MMR Status.
ROW
0
1
2
3
4
5
6
7
start scroll row
usable for
OSD display
<
>
STS 3:0 e.g. 3
soft scrolling area
start scroll row
soft scroll position
<
>
pointer SSP 3:0 e.g. 6
should not be used
for OSD display
soft scroll height
<
>
SSH 3:0 e.g. 4
8
9
should not be used
for OSD display
10
11
12
13
14
15
usable for
OSD display
<
>
SPS 3:0 e.g. 11
MBK967
Fig.24 Soft scroll area.
2000 Feb 23
56
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
0-63
lines
ROW
row0
0
1
2
row1
P01 NBC
row2
row3
row4
row5
row6
row7
row8
3
scroll area
offset
4
5
6
7
8
9
Closed Captioning data row n
Closed Captioning data row n+1
Closed Captioning data row n+2
Closed Captioning data row n+3
10
11
12
13
14
15
visible area
for scrolling
Closed Captioning data row n+4
row13
row14
MBK977
Fig.25 CC text areas.
2000 Feb 23
57
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
0
39
Row 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
control data
non-displayable data
byte 10 reserved
0
9 10
23
MBK968
Fig.26 TXT text area.
2000 Feb 23
58
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
18.7 Display positioning
The display consists of the screen colour covering the whole screen and the text area that is placed within the visible
screen area.
The screen colour extends over a large vertical and horizontal range so that no offset is needed. The text area is offset
in both directions relative to the vertical and horizontal sync pulses.
horizontal sync
6 lines
offset
screen colour
offset = 8 µs
text
vertical
offset
SCREEN COLOUR AREA
TEXT AREA
horizontal
sync
delay
vertical
sync
0.25 character
offset
text area start
text area end
MGL150
56 µs
Fig.27 Display area positioning.
2000 Feb 23
59
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
18.7.1 SCREEN COLOUR DISPLAY AREA
The width of the text area is defined in the MMR Text Area
End Register by setting the end character value
TAE<5:0>. This number determines where the
background colour of the Text Area will end if set to extend
to the end of the row. It will also terminate the character
fetch process thus eliminating the necessity of a row end
attribute. This entails however writing to all positions.
This area is covered by the screen colour. The screen
colour display area starts with a fixed offset of 8 µs from
the leading edge of the horizontal sync pulse in the
horizontal direction. A vertical offset is not necessary.
Table 20 Screen colour display area
The vertical offset is set in the MMR Text Position Vertical.
The offset value VOL<5:0> is done in number of TV scan
lines.
POSITION
525-LINE
Horizontal
Start at 8 µs after leading edge of
horizontal sync for 56 µs.
Note that the Text Position Vertical Register should not be
set to 00H as the Display Busy interrupt is not generated
in these circumstances.
Vertical
Line 9, Field 1 (321, Field 2) to leading
edge of vertical sync (line numbering
using 625 standard).
18.8 Character set
18.7.2 TEXT DISPLAY AREA
To facilitate the global nature of the device the character
set has the ability to accommodate a large number of
characters, which can be stored in different matrices.
The text area can be defined to start with an offset in both
the horizontal and vertical direction.
Table 21 Text display area
18.8.1 CHARACTER MATRICES
POSITION
DESCRIPTION
The character matrices that can be accommodated in both
display modes are:
Horizontal
Up to 48 full sized characters per row.
Start position setting from 8 to 64
characters from the leading edge of
horizontal sync. Fine adjustment in
quarter characters.
(H × V × planes) 12 × 9 × 1, 12 × 10 × 1, 12 × 13 × 1,
12 × 16 × 1.
These modes allow two colours per character position.
In CC mode two additional character matrices are
available to allow four colours per character.
Vertical
256 lines (nominal 41 to 297). Start
position setting from leading edge of
vertical sync, legal values are
4 to 64 lines (line numbering using
625 standard).
(H × V × planes) 12 × 13 × 2, 12 × 16 × 2.
The characters are stored physically in ROM in a matrix of
size either 12 × 10 or 12 × 16.
The horizontal offset is set in the MMR Text Area Start.
The offset is done in full width characters using TAS<5:0>
and quarter characters using HOP<1:0> for fine setting.
The values 00H to 08H for TAS<5:0> will result in a
corrupted display.
The value 09H should also be avoided in the MMR Text
Area Start as corruption of the row 24 display can occur.
Alternative values are C8H or 49H to overcome this
problem.
2000 Feb 23
60
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
18.8.2 CHARACTER SET SELECTION
The alternative/twist character set is defined by
TXT19.TS<1:0>. Since the alternative character set is an
option it can be enabled or disabled using TXT19.TEN,
and the language code that is defined for the alternative
set is defined by TXT19.TC<2:0>.
Four character sets are available in the device. A set can
consist of alphanumeric characters as required by the
WST or US Closed Captioning, Customer definable
On-Screen Display characters, and Special Graphic
characters.
The National option table is selected using
TXT18.NOT<3:0>. A maximum of 31 National option
tables can be defined when combined with the
EAST/WEST control bit located in register TXT4.
CC: Only a single character set can be used for display
and this is selected using the Basic Set selection
TXT18.BS<1:0>. When selecting a character set in
CC mode, the Twist Set selection TXT19.TS<1:0> should
be set to the same value as TXT18.BS<1:0> for correct
operation.
An example of the character set selection and definitions
is show in Table 22.
An example of the National option reference table is shown
in Table 23. Only a certain number of national options will
be relevant for each of the Character sets.
TXT: Two character sets can be displayed at once. These
are the basic G0 set or the alternative G0 set (Twist Set).
The basic set is selected using TXT18.BS<1:0>.
Table 22 Character set selection
BS1/TS1
BS0/TS0
CHARACTER SET
EXAMPLE LANGUAGE
0
0
1
1
0
1
0
1
Set 0
Set 1
Set 2
Set 3
Latin
Greek
−
Closed Caption
Table 23 National option selection
C12
C13
C14
NOT<3:0> = 0000 NOT<3:0> = 0001 NOT<3:0> = 0010
...
NOT<3:0> = 1110
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
English
German
Swedish
Italian
French
Spanish
Czech
−
Polish
German
Swedish
Italian
French
−
English
German
Swedish
Italian
...
...
...
...
...
...
...
...
Polish
German
Estonian
Lettish
Russian
Serb-Croat
Czech
French
Spanish
Turkish
−
Czech
−
−
2000 Feb 23
61
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
18.9 ROM addressing
Three ROMs are used to generate the correct pixel information. The first contains the National option look-up table, the
second contains the Basic character look-up table and the third contains the Character pixel information.
Although these are individual ROMs, since they do not need to be accessed simultaneously they are all combined into
a single ROM unit.
2400H
CHARACTER PIXEL DATA
(71680 × 12-BIT)
0800H
LOOK-UP SET 3
LOOK-UP SET 2
LOOK-UP SET 1
LOOK-UP SET 0
0600H
0400H
0200H
0000H
710 TEXT
OR
+
430 TEXT 176 CC
0800H
0000H
LOOK-UP
BASIC + NATIONAL OPTION
2048 LOCATIONS
MBK978
Fig.28 ROM organisation.
2000 Feb 23
62
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
18.9.1 CHARACTER TABLE
CC: The character table is shown in Fig.29.
TXT: One of the character set options (Pan-European: Latin) is shown in Fig.22.
Character code columns (bits 4 to 7)
0
1
2
SP
!
3
0
1
2
3
4
5
6
7
8
9
:
4
5
P
Q
R
S
T
U
V
W
X
Y
Z
[
6
ú
a
b
c
d
e
f
7
p
q
r
8
9
A
B
C
D
E
F
®
@
0
1
A
B
C
D
E
F
G
H
I
˚
1/2
¿
2
"
#
s
t
3
4
™
¢
$
5
%
&
u
v
w
x
y
z
ç
6
£
g
h
i
7
´
(
8
à
_
è
â
ê
î
9
)
A
B
C
D
E
F
á
+
,
j
J
;
k
l
K
L
<
=
>
?
é
-
]
m
n
o
Ñ
ñ
n
M
N
O
ô
û
.
/
Í
ó
MBK976
Special characters in column 8 and 9
Additional table locations for normal characters
Table locations for normal characters
Fig.29 Closed Caption character table.
2000 Feb 23
63
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
18.10 Redefinable characters
The remapping of the standard OSD to the DRCs is
activated when the TXT20.DRCS ENABLE bit is set.
The selection of Normal or Special OSD symbols is
defined by the TXT20.OSD PLANES.
A number of Dynamically Redefinable Characters (DRCs)
are available. These are mapped onto the normal
character codes, and replace the predefined ROM value.
Each character is stored in a matrix of 12 × 16 × 1
(V × H × planes), this allows for all possible character
matrices to be defined within a single location.
There are 32 DRCs, the first 16 occupy the character
codes 80H to 8FH, the second 16 occupy the locations
90H to 9FH. This allows for 32 DRCs or 16 Special DRCs.
address (HEX)
8800
character code
80H
CHARACTER 0
CHARACTER 1
CHARACTER 2
881F
8820
character 0
address (HEX)
81H
82H
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
883F
8840
885F
A
8BC0
CHARACTER 30
CHARACTER 31
9EH
9FH
8BDF
8BE0
12 bits
8BFF
MBK969
Fig.30 Organisation of DRC RAM.
2000 Feb 23
64
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
18.11 Display synchronization
Table 25 RGB brightness
The horizontal and vertical synchronizing signals from the
TV deflection are used as inputs. Both signals can be
inverted before being delivered to the Phase Selector
section.
BRI3 TO BRI0
RGB BRIGHTNESS
0000
...
lowest value
...
1111
highest value
CC: The polarity is controlled using either VPOL or HPOL
bits in the MMR Text Position Vertical.
18.15 Contrast reduction
TXT: The TXT1.H POLARITY and TXT1.V POLARITY bits
control the polarity.
CC: This feature is not available in CC mode.
TXT: The COR bits in SFRs TXT5 and TXT6 control when
the COR output of the device is activated (i.e. pulled
LOW). This output is intended to act on the TV’s display
circuits to reduce contrast of the video when it is active.
The result of contrast reduction is to improve the
A line locked 12 MHz clock is derived from the 12 MHz free
running oscillator by the Phase Selector. This line locked
clock is used to clock the whole of the Display block.
The horizontal and vertical sync signals are synchronized
with the 12 MHz clock before being used in the display
section.
readability of the text in a mixed teletext and video display.
The bits in the TXT5 and TXT6 SFRs allow the display to
be set up so that, for example, the areas inside teletext
boxes will be contrast reduced when a subtitle is being
displayed but that the rest of the screen will be displayed
as normal video.
18.12 Video/Data switch (Fast Blanking) polarity
The polarity of the video/data (Fast Blanking) signal can be
inverted. The polarity is set with the VDSPOL bit in the
MMR RGB Brightness.
19 MEMORY MAPPED REGISTERS (MMR)
Table 24 Fast blanking signal polarity
The memory mapped registers are used to control the
display. The registers are mapped into the microcontroller
MOVX address space, starting at address 87F0H and
extending to 87FFH.
VDSPOL
VDS
CONDITION
RGB display
Video display
RGB display
Video display
0
0
1
1
1
0
0
1
Table 26 MMR address summary
REGISTER
NUMBER
MEMORY
ADDRESS
FUNCTION
18.13 Video/data switch adjustment
To take into account the delay between the RGB values
and the VDS signal due to external buffering, the
VDS signal can be moved in relation to the RGB signals.
The VDS signal can be set to be either a clock cycle before
or after the RGB signal, or coincident with the RGB signal.
This is done using VDEL<2:0> in the MMR Configuration.
0
1
87F0H
87F1H
87F2H
87F3H
87F4H
87F5H
87F6H
87F7H
87F8H
87F9H
87FAH
87FBH
87FCH
87FDH
87FEH
87FFH
Display Control
Text Position Vertical
Text Area Start
Fringing Control
Text Area End
Scroll Area
2
3
4
5
18.14 RGB brightness control
6
Scroll Range
RGB Brightness
Status
7
A brightness control is provided to allow the RGB upper
output voltage level to be modified. The nominal value is
1 V into a 150 Ω resistor, but can be varied between
0.7 V and 1.2 V.
8
9
reserved
10
11
12
13
14
15
reserved
reserved
The brightness is set in MMR RGB Brightness.
HSYNC Delay
VSYNC Sync Delay
Top Scroll Line
Configuration
2000 Feb 23
65
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
Table 27 MMR map
ADD R/W
NAME
7
6
5
4
3
2
1
0
RESET
87F0 R/W Display
Control
SRC3
SRC2
SRC1
SRC0
−
MSH
MOD1 MOD0
00H
87F1 R/W Text Position VPOL
Vertical
HPOL
HOP0
FRC2
−
VOL5
TAS5
FRC1
TAE5
VOL4
TAS4
FRC0
TAE4
VOL3
TAS3
FRDN
TAE3
VOL2
TAS2
FRDE
TAE2
VOL1
TAS1
FRDS
TAE1
VOL0
TAS0
FRDW
TAE0
00H
00H
00H
00H
87F2 R/W Text Area
Start
HOP1
FRC3
−
87F3 R/W Fringing
Control
87F4 R/W Text Area
End
87F5 R/W Scroll Area
SSH3
SSH2
SPS2
−
SSH1
SPS1
−
SSH0
SPS0
−
SSP3
STS3
BRI3
SSP2
STS2
BRI2
SSP1
STS1
BRI1
SSP0
STS0
BRI0
00H
00H
00H
87F6 R/W Scroll Range SPS3
87F7 R/W RGB VDSPOL
Brightness
Status
87F8
R
BUSY
FIELD
−
SCON FLR
SCON FLR
SCR3
SCR3
HSD3
SCR2
SCR2
HSD2
SCR1
SCR1
HSD1
SCR0
SCR0
HSD0
00H
00H
00H
W
−
−
87FC R/W HSYNC
Delay
HSD6
HSD5
VSD5
−
HSD4
87FD R/W VSYNC
Delay
−
−
VSD6
VSD4
VSD3
SCL3
VSD2
SCL2
−
VSD1
SCL1
−
VSD0
SCL0
−
00H
00H
00H
87FE R/W Top Scroll
Line
−
−
87FF R/W Configuration CC
VDEL2 VDEL1 VDEL0 TXT/V
2000 Feb 23
66
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
Table 28 MMR bit definition
REGISTER BIT
Display Control
FUNCTION
SRC3 to SRC0
MSH
screen colour definition
meshing all background colours (logic 1)
00 = Video
MOD1 to MOD0
01 = Full Text
10 = Mixed Screen Colour
11 = Mixed Video
Text Position Vertical
VPOL
inverted input polarity (logic 1)
inverted input polarity (logic 1)
HPOL
VOL5 to VOL0
display start vertical offset from VSYNC (lines)
Text Area Start
HOP1 to HOP0
TAS5 to TAS0
fine horizontal offset in quarter of characters
text area start
Fringing Control
FRC3 to FRC0
FRDN
fringing colour, value address of CLUT
fringe in north direction (logic 1)
fringe in east direction (logic 1)
fringe in south direction (logic 1)
fringe in west direction (logic 1)
FRDE
FRDS
FRDW
Text Area End
TAE5 to TAE0
Scroll Area
text area end, in full characters
SSH3 to SSH0
SSP3 to SSP0
soft scroll height
soft scroll position
Scroll Range
SPS3 to SPS0
STS3 to STS0
stop scroll row
start scroll row
RGB Brightness
VDSPOL
VDS polarity
0 = RGB (1), Video (0)
1 = RGB (0), Video (1)
RGB brightness control
BRI3 to BRI0
2000 Feb 23
67
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
REGISTER BIT
Status read
FUNCTION
BUSY
access to display memory could cause display problems (logic 1)
even field (logic 1)
FIELD
FLR
active flash region background only displayed (logic 1)
first scroll row
SCR3 to SCR0
Status write
SCON
scroll area enabled (logic 1)
FLR
active flash region background colour only displayed (logic 1)
first scroll row
SCR3 to SCR0
HSYNC Delay
HSD6 to HSD0
VSYNC Delay
VSD6 to VSD0
Top Scroll Line
SCL3 to SCL0
Configuration
HSYNC delay, in full size characters
VSYNC delay in number of 8-bit 12 MHz clock cycles
top line for scroll
CC
closed caption mode (logic 1)
VDEL2 to VDEL0
pixel delay between VDS and RGB output
000 = VDS switched to video, not active
001 = VDS active one pixel earlier then RGB
010 = VDS synchronous to RGB
100 = VDS active one pixel after RGB
BUSY signal switch; horizontal (logic 1)
TXT/V
2000 Feb 23
68
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
20 LIMITING VALUES
In accordance with Absolute Maximum Rating System (IEC 60134).
SYMBOL
VDDX
PARAMETER
CONDITIONS
MIN.
−0.5
MAX.
UNIT
supply voltage (all supplies)
input voltage (any input)
output voltage (any output)
output current (each output)
DC input or output diode current
ambient temperature
+4.0
V
V
V
VI
note 1
note 1
−0.5
−0.5
−
VDD + 0.5 or 4.1
VDD + 0.5
±10
VO
IO
mA
mA
°C
IIOK
Tamb
Tstg
−
±20
−20
−55
+70
storage temperature
+125
°C
Note
1. This maximum value refers to 5 V tolerant I/Os and may be 6 V maximum, but only when VDD is present.
21 CHARACTERISTICS
VDD = 3.3 V ± 10%; VSS = 0 V; Tamb = −20 to +70 °C; unless otherwise specified.
SYMBOL
Supplies
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDDX
IDDP
any supply voltage (VDD to VSS
Periphery supply current
core supply current
)
3.0
1
3.3
−
3.6
−
V
note 1
mA
mA
µA
µA
IDDC
−
12
18
IDDC(id)
IDDC(pd)
Idle mode core supply current
−
383
666
600
900
Power-down mode core supply
current
−
IDDC(stb)
Standby mode core supply
current
−
5.1
9
mA
IDDA
analog supply current
−
−
−
45
48
mA
µA
µA
IDDA(id)
IDDA(pd)
Idle mode analog supply current
444
433
700
700
Power-down mode analog supply
current
IDDA(stb)
Standby mode analog supply
current
−
809
950
µA
Digital inputs
RESET
VIL
LOW-level input voltage
HIGH-level input voltage
−
−
−
−
1.00
−
V
V
V
VIH
1.85
0.44
Vhys
hysteresis voltage of Schmitt
trigger input
0.58
ILI
input leakage current
VI = 0
−
−
0.17
µA
kΩ
Rpd
equivalent pull-down resistance
VI = VDD
55.73
70.71
92.45
2000 Feb 23
69
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
HSYNC AND VSYNC
VIL
LOW-level input voltage
HIGH-level input voltage
−
−
−
−
0.96
V
V
V
VIH
Vhys
1.80
0.40
−
hysteresis voltage of Schmitt
trigger input
0.56
ILI
input leakage current
VI = 0 to VDD
−
−
0.00
µA
Digital outputs
FRAME, VDS
VOL
VOH
tr
LOW-level output voltage
IOL = 3 mA
IOH = 3 mA
−
−
−
0.13
−
V
HIGH-level output voltage
output rise time
2.84
7.50
V
10% to 90%;
CL = 70 pF
8.85
10.90
ns
tf
output fall time
10% to 90%;
CL = 70 pF
6.70
7.97
10.00
ns
COR (OPEN-DRAIN OUTPUT)
VOL
VOH
LOW-level output voltage
IOL = 3 mA
−
−
−
0.14
V
V
HIGH-level pull-up output voltage IOL = −3 mA;
2.84
−
push-pull
VIL
VIH
ILI
LOW-level input voltage
HIGH-level input voltage
−
−
0.00
5.50
0.12
11.10
V
0.00
−
−
V
input leakage current
output rise time
VI = 0 to VDD
−
µA
ns
tf
10% to 90%;
CL = 70 pF
7.20
8.64
output fall time
10% to 90%;
CL = 70 pF
4.90
7.34
9.40
ns
Digital input/outputs
P0.0 TO P0.4, P0.7, P1.0 TO P1.1, P2.1 TO P2.7, P3.0 TO P3.7
VIL
LOW-level input voltage
HIGH-level input voltage
−
−
−
−
0.98
−
V
V
V
VIH
Vhys
1.78
0.41
hysteresis voltage of Schmitt
trigger input
0.55
ILI
input leakage current
VI = 0 to VDD
IOL = 4 mA
−
−
−
−
0.01
0.18
5.50
µA
V
VOL
VOH
LOW-level output voltage
HIGH-level output voltage
−
IOH = −4 mA
2.81
V
push-pull
tr
tf
output rise time
output fall time
10% to 90%;
CL = 70 pF
push-pull
6.50
5.70
8.47
7.56
10.70
10.00
ns
ns
10% to 90%;
CL = 70 pF
2000 Feb 23
70
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
P1.2, P1.3 AND P2.0
VIL
LOW-level input voltage
HIGH-level input voltage
−
−
−
−
0.99
V
V
V
VIH
Vhys
1.80
0.42
−
hysteresis voltage of Schmitt
trigger input
0.56
ILI
input leakage current
VI = 0 to VDD
IOL = 4 mA
−
−
−
−
0.02
0.17
5.50
µA
V
VOL
VOH
LOW-level output voltage
HIGH-level output voltage
−
IOH = −4 mA
2.81
V
push-pull
tr
output rise time
output fall time
10% to 90%;
CL = 70 pF
push-pull
7.00
5.40
8.47
7.36
10.50
9.30
ns
ns
tf
10% to 90%;
CL = 70 pF
P0.5 AND P0.6
VIL
LOW-level input voltage
HIGH-level input voltage
input leakage current
−
−
−
−
−
−
−
0.98
−
V
VIH
ILI
1.82
−
V
VI = 0 to VDD
IOL = 8 mA
0.11
0.58
0.20
5.50
µA
V
Vhys
VOL
VOH
hysteresis of Schmitt trigger input
LOW-level output voltage
HIGH-level output voltage
0.42
−
V
IOH = −8 mA
2.76
V
push-pull
tr
tf
output rise time
output fall time
10% to 90%;
CL = 70 pF
push-pull
7.40
4.20
8.22
4.57
8.80
5.20
ns
ns
10% to 90%;
CL = 70 pF
P1.4 TO P1.7 (OPEN-DRAIN)
VIL
LOW-level input voltage
−
−
−
−
1.08
−
V
V
V
VIH
Vhys
HIGH-level input voltage
1.99
0.49
hysteresis voltage of Schmitt
trigger input
0.60
ILI
input leakage current
LOW-level output voltage
output fall time
VI = 0 to VDD
IOL = 8 mA
−
−
0.13
µA
V
VOL
tf
−
−
0.35
10% to 90%;
CL = 70 pF
69.70
83.67
103.30
ns
Analog inputs
CVBS0 AND CVBS1
Vsync
sync voltage amplitude
0.1
0.7
0.3
1.0
0.6
1.4
V
V
Vvid(p-p)
video input voltage amplitude
(peak-to-peak value)
Zsource
source impedance
0
−
250
Ω
2000 Feb 23
71
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
SYMBOL
VIH
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
HIGH-level input voltage
input capacitance
3.0
−
−
VDDA + 0.3
10
V
CI
−
pF
IREF
Rgnd
resistor to ground
resistor
−
24
−
kΩ
tolerance 2%
ADC0 TO ADC3
VIH
CI
HIGH-level input voltage
−
−
−
−
VDDA
10
V
input capacitance
pF
VPE
VIH
HIGH-level input voltage
−
−
9.0
V
Analog outputs
R, G AND B
IOL
IOH
output current (Black Level)
VDDA = 3.3 V
−10
−
+10
7.3
µA
output current (maximum
Intensity)
VDDA = 3.3 V
Intensity level
code = 15 dec
6.0
6.67
4.7
mA
output current (70% of full
Intensity)
VDDA = 3.3 V
4.2
5.1
mA
Intensity level
code = 0 dec
Rload
CL
load resistor to VSSA
load capacitance
resistor
tolerance 5%
−
−
150
−
Ω
−
15
pF
Analog input/output
SYNC_FILTER
Csync
Vsync
storage capacitor to ground
−
100
−
nF
V
sync filter level voltage for
nominal sync amplitude
0.35
0.55
0.75
Crystal oscillator
XTALIN
VIL
VIH
CI
LOW-level input voltage
VSSA
−
−
−
−
V
HIGH-level input voltage
input capacitance
−
−
VDDA
10
V
pF
XTALOUT
CO
output capacitance
−
−
10
pF
2000 Feb 23
72
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Crystal specification; notes 2 and 3
fxtal
nominal frequency
fundamental
mode
−
12
−
MHz
CL
C1
Rr
crystal load capacitance
crystal motional capacitance
resonance resistance
−
−
−
−
−
−
−
−
30
20
60
−
pF
fF
Tamb = 25 °C
Tamb = 25 °C
Ω
Cosc
C0
Txtal
Xj
capacitors at XTALIN, XTALOUT Tamb = 25 °C
note 4
pF
pF
°C
crystal holder capacitance
temperature range
adjustment tolerance
drift
Tamb = 25 °C
−
note 5
−20
−
+25
−
+85
Tamb = 25 °C
±50 × 10−6
±100 × 10−6
Xd
−
−
Notes
1. Peripheral current is dependent on external components and voltage levels on I/Os.
2. Crystal order number 4322 143 05561.
3. If the 4322 143 05561 crystal is not used, then the formulae in the crystal specification should be used. Where
IO = 7 pF, the mean of the capacitances due to the chip at XTALIN and at XTALOUT. Cext is a value for the mean
C
of the stray capacitances due to the external circuit at XTALIN and XTALOUT. The maximum value for the crystal
holder capacitance is to ensure start-up − Cosc may need to be reduced from the initially selected value.
4. Cosc(typ) = 2CL – (CIO – Cext
)
1
2
5. C0(max) = 35 – (C osc + CIO + Cext
)
--
2000 Feb 23
73
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
Table 29 I2C-bus characteristics
FAST-MODE I2C-bus
MIN. MAX.
400
SYMBOL
PARAMETER
UNIT
kHz
fSCL
SCL clock frequency
0
tBUF
bus free time between a STOP and START condition
1.3
0.6
−
−
µs
µs
tHD;STA
hold time (repeated) START condition. After this period, the first
clock pulse is generated.
tLOW
tHIGH
tSU;STA
tHD;DAT
tSU;DAT
tr
LOW period of the SCL clock
1.3
0.6
0.6
0
−
µs
µs
µs
µs
ns
ns
ns
µs
pF
HIGH period of the SCL clock
−
set up time for a repeated START condition
data hold time; notes 1 and 2
−
0.9
−
data set up time; note 3
100
20
20
0.6
−
rise time of both SDA and SCL signals; note 4
fall time of both SDA and SCL signals; note 4
set up time for STOP condition
300
300
−
tf
tSU;STO
Cb
capacitive load for each bus line
400
Notes
1. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL
signal) in order to bridge the undefined region of the falling edge of SCL.
2. The maximum fHD;DAT has only to be met if the device does not stretch the LOW period tLOW of the SCL signal.
3. A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tSU;DAT ≥250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal.
If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
t
rmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C-bus specification) before the SCL line
is released.
4. Cb = total capacitance of one bus line in pF.
2000 Feb 23
74
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
22 QUALITY AND RELIABILITY
This device will meet Philips Semiconductors General Quality Specification for Business group “Consumer Integrated
Circuits SNW-FQ-611-Part E”. The principal requirements are shown in Tables 30 to 33.
Table 30 Acceptance tests per lot
TEST
REQUIREMENTS
REQUIREMENTS
Mechanical
Electrical
cumulative target: <80 ppm
cumulative target: <100 ppm
Table 31 Processability tests (by package family)
TEST
Solderability
0/16 on all lots
0/15 on all lots
0/15 on all lots
Mechanical
Solder heat resistance
Table 32 Reliability tests (by process family)
TEST
CONDITIONS
168 hours at Tj = 150 °C
REQUIREMENTS
<1000 FPM at Tj = 150 °C
Operational life
Humidity life
temperature, humidity, bias 1000 hours, <2000 FPM
85 °C, 85% RH (or equivalent test)
Temperature cycling
performance
Tstg(min) to Tstg(max)
<2000 FPM
Table 33 Reliability tests (by device type)
TEST
CONDITIONS
ESD Human body model 100 pF, 1.5 kW 2000 V
REQUIREMENTS
ESD and latch-up
ESD Machine model 200 pF, 0 W
latch-up
200 V
100 mA, 1.5 × VDD (absolute maximum)
Notes to Tables 30 to 33
1. ppm = fraction of defective devices, in parts per million.
2. FPM = fraction of devices failing at test condition, in Failures Per Million.
3. FITS = Failures In Time Standard.
2000 Feb 23
75
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
g
V
V
40 V
DD
DD
V
A0
A1
A2
DD
RC
EEPROM
PCF8582E
PH2369
V
tune
SCL
SDA
V
V
DD
DD
V
SS
47 µF
100 nF
V
DD
V
V
V
SS
SS
SS
V
SS
V
V
DD
SS
P2.0/TPWM
P2.1/PWM0
P2.2/PWM1
P2.3/PWM2
P2.4/PWM3
P2.5/PWM4
P2.6/PWM5
P2.7/PWM6
P3.0/ADC0
P3.1/ADC1
P3.2/ADC2
P3.3/ADC3
P1.5/SDA1
P1.4/SCL1
1
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
brightness
contrast
2
P1.7/SDA0
P1.6/SCL0
P1.3/T1
3
TV
control
signals
saturation
hue
4
5
P1.2/INT0
P1.1/T0
volume (L)
volume (R)
6
7
P1.0/INT1
8
V
V
V
SS
DD
DDP
IR
RECEIVER
9
V
10 µF
AFC
V
DD
RESET
AV status
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
XTALOUT
XTALIN
12 MHz
V
DD
program+
program−
56 pF
100 nF
V
OSCGND
SSC
47 µF
V
V
SAA55xx
V
SS
DD
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
DDC
VHF-L
VHF-H
UHF
V
V
SS
SSP
V
SS
VSYNC
TV control
signals
field flyback
line flyback
menu
HSYNC
VDS
R
minus(−)
plus(+)
G
V
1 kΩ
1 kΩ
DD
B
V
SS
V
V
to TV's
display
circuits
V
DD
SSA
DDA
150 Ω
V
V
SS
DD
CVBS0
CVBS1
P3.4/PWM7
COR
100 nF
100 nF
29
28
27
V
SS
VPE
SYNC_FILTER
IREF
CVBS (IF)
CVBS (SCART)
V
SS
FRAME
24 kΩ
100 nF
MBK980
V
SS
Fig.31 Application diagram.
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
24 ELECTROMAGNETIC COMPATIBILITY (EMC)
GUIDELINES
Using a device socket will unfortunately add to the area
and inductance of the external bypass loop.
Optimization of circuit return paths and minimisation of
common mode emission will be assisted by using a double
sided printed-circuit board (PCB) with low inductance
ground plane.
A ferrite bead or inductor with resistive characteristics at
high frequencies may be utilised in the supply line close to
the decoupling capacitor to provide a high impedance.
To prevent pollution by conduction onto the signal lines
(which may then radiate) signals connected to the
On a single-sided PCB a local ground plane under the
whole Integrated Circuit (IC) should be present as shown
in Fig.32. This should be connected by the widest possible
connection back to the PCB ground connection, and bulk
electrolytic decoupling capacitor. It should preferably not
connect to other grounds on the way, and no wire links
should be present in this connect. The use of wire links
increases ground bounce by introducing inductance into
the ground.
V
DD supply via a pull up resistor should not be connected
to the IC side of this ferrite component.
OSCGND should be connected only to the crystal load
capacitors and not the local or circuit ground.
Physical connection distances to associated active
devices should be short.
Output traces should be routed with close proximity to
mutually coupled ground return paths.
The supply pins can be decoupled at the pin to the ground
plane under the IC. This is easily accomplished using
surface mount capacitors, which are more effective than
leaded components at high frequency.
GND +3.3 V
electrolytic decoupling capacitor (2 µF)
ferrite beads
other
GND
connections
SM decoupling capacitors (10 to 100 nF)
under-IC GND plane
under-IC GND plane
GND connection
note: no wire links
IC
V
V
SSA
SSC
MBK979
Fig.32 Power supply connections for EMC.
77
2000 Feb 23
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
25 PACKAGE OUTLINES
SDIP52: plastic shrink dual in-line package; 52 leads (600 mil)
SOT247-1
D
M
E
A
2
A
L
A
1
c
e
(e )
1
w M
Z
b
1
M
H
b
52
27
pin 1 index
E
1
26
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
max.
A
A
2
max.
(1)
(1)
Z
1
w
UNIT
b
b
c
D
E
e
e
L
M
M
H
1
1
E
min.
max.
1.3
0.8
0.53
0.40
0.32
0.23
47.9
47.1
14.0
13.7
3.2
2.8
15.80
15.24
17.15
15.90
mm
5.08
0.51
4.0
1.778
15.24
0.18
1.73
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-03-11
99-12-27
SOT247-1
MS-020
2000 Feb 23
78
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm
SOT407-1
y
X
A
51
75
50
26
(1)
76
Z
E
e
H
A
E
2
E
A
(A )
3
A
1
w M
p
θ
b
L
p
L
pin 1 index
detail X
100
1
25
Z
D
v
M
A
B
e
w M
b
p
D
B
H
v
M
5
D
0
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
θ
1
2
3
p
E
p
D
E
max.
7o
0o
0.15 1.45
0.05 1.35
0.27 0.20 14.1 14.1
0.17 0.09 13.9 13.9
16.25 16.25
15.75 15.75
0.75
0.45
1.15 1.15
0.85 0.85
mm
1.6
0.25
0.5
1.0
0.2 0.08 0.08
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
00-01-19
00-02-01
SOT407-1
136E20
MS-026
2000 Feb 23
79
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
26 SOLDERING
The total contact time of successive solder waves must not
exceed 5 seconds.
26.1 Introduction to soldering through-hole mount
packages
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg(max)). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
This text gives a brief insight to wave, dip and manual
soldering. A more in-depth account of soldering ICs can be
found in our “Data Handbook IC26; Integrated Circuit
Packages” (document order number 9398 652 90011).
Wave soldering is the preferred method for mounting of
through-hole mount IC packages on a printed-circuit
board.
26.3 Manual soldering
Apply the soldering iron (24 V or less) to the lead(s) of the
package, either below the seating plane or not more than
2 mm above it. If the temperature of the soldering iron bit
is less than 300 °C it may remain in contact for up to
10 seconds. If the bit temperature is between
26.2 Soldering by dipping or by solder wave
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joints for more than 5 seconds.
300 and 400 °C, contact may be up to 5 seconds.
26.4 Suitability of through-hole mount IC packages for dipping and wave soldering methods
SOLDERING METHOD
PACKAGE
DIPPING
WAVE
DBS, DIP, HDIP, SDIP, SIL
suitable
suitable(1)
Note
1. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.
2000 Feb 23
80
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
27 DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
28 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
29 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
2000 Feb 23
81
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
NOTES
2000 Feb 23
82
Philips Semiconductors
Preliminary specification
TV microcontrollers with Closed Captioning (CC)
and On-Screen Display (OSD)
SAA55xx
NOTES
2000 Feb 23
83
Philips Semiconductors – a worldwide company
Argentina: see South America
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399
Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140,
Tel. +61 2 9704 8141, Fax. +61 2 9704 8139
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,
Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210
Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773
Pakistan: see Singapore
Belgium: see The Netherlands
Brazil: see South America
Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 68 9211, Fax. +359 2 68 9102
Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,
Tel. +48 22 5710 000, Fax. +48 22 5710 001
Portugal: see Spain
Romania: see Italy
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 755 6918, Fax. +7 095 755 6919
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,
Colombia: see South America
Czech Republic: see Austria
Tel. +65 350 2538, Fax. +65 251 6500
Slovakia: see Austria
Slovenia: see Italy
Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,
Tel. +45 33 29 3333, Fax. +45 33 29 3905
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
Tel. +27 11 471 5401, Fax. +27 11 471 5398
Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615 800, Fax. +358 9 6158 0920
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,
Tel. +33 1 4099 6161, Fax. +33 1 4099 6427
South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 821 2382
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 2353 60, Fax. +49 40 2353 6300
Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 93 301 6312, Fax. +34 93 301 4107
Hungary: see Austria
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745
India: Philips INDIA Ltd, Band Box Building, 2nd floor,
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. +91 22 493 8541, Fax. +91 22 493 0966
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2741 Fax. +41 1 488 3263
Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813
Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI),
Tel. +39 039 203 6838, Fax +39 039 203 6800
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Uruguay: see South America
Vietnam: see Singapore
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Middle East: see Italy
Tel. +381 11 3341 299, Fax.+381 11 3342 553
For all other countries apply to: Philips Semiconductors,
Internet: http://www.semiconductors.philips.com
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
69
SCA
© Philips Electronics N.V. 2000
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753504/02/pp84
Date of release: 2000 Feb 23
Document order number: 9397 750 06788
相关型号:
©2020 ICPDF网 联系我们和版权申明