SAA7108E [NXP]

PC-CODEC; PC- CODEC


型号：	SAA7108E
厂家：	NXP
描述：	PC-CODEC PC- CODEC 消费电路商用集成电路 PC
文件：	总202页 (文件大小：940K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

INTEGRATED CIRCUITS

DATA SHEET

SAA7108E; SAA7109E

PC-CODEC

Product speciﬁcation

2004 Mar 16

Supersedes data of 2001 Dec 12

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

CONTENTS

10.3

10.4

10.5

10.6

Clock and real-time synchronization signals

Video expansion port (X port)

Image port (I port)

Host port for 16-bit extension of video data I/O

(H port)

FEATURES

1.1

1.2

1.3

1.4

Video decoder

Video scaler

Video encoder

Common features

10.7

Basic input and output timing diagrams for the

I and X ports

BOUNDARY SCAN TEST

APPLICATIONS

11.1

11.2

Initialization of boundary scan circuit

Device identification codes

GENERAL DESCRIPTION

QUICK REFERENCE DATA

ORDERING INFORMATION

BLOCK DIAGRAMS

PINNING

LIMITING VALUES

THERMAL CHARACTERISTICS

CHARACTERISTICS OF THE DIGITAL

VIDEO ENCODER PART

FUNCTIONAL DESCRIPTION OF DIGITAL

VIDEO ENCODER PART

CHARACTERISTICS OF THE DIGITAL

VIDEO DECODER PART

8.1

8.2

Reset conditions

Input formatter

TIMING

16.1

16.2

Digital video encoder part

Digital video decoder part

8.3

8.4

RGB LUT

Cursor insertion

8.5

8.6

8.7

8.8

RGB Y-C_B-C_Rmatrix

Horizontal scaler

Vertical scaler and anti-flicker filter

FIFO

APPLICATION INFORMATION

17.1

17.2

Analog output voltages

Suggestions for a board layout

I²C-BUS DESCRIPTION

8.9

Border generator

8.10

8.11

8.12

8.13

8.14

8.15

8.16

8.17

Oscillator and Discrete Time Oscillator (DTO)

Low-pass Clock Generation Circuit (CGC)

Encoder

RGB processor

Triple DAC

Timing generator

I²C-bus interface

Programming the graphics acquisition scaler of

the video encoder

18.1

18.2

Digital video encoder part

Digital video decoder part

PROGRAMMING START SET-UP OF

DIGITAL VIDEO DECODER PART

19.1

19.2

19.3

19.4

Decoder part

Audio clock generation part

Data slicer and data type control part

Scaler and interfaces

8.18

Input levels and formats

PACKAGE OUTLINE

SOLDERING

FUNCTIONAL DESCRIPTION OF DIGITAL

VIDEO DECODER PART

21.1

Introduction to soldering surface mount

packages

Reflow soldering

Wave soldering

Manual soldering

9.1

9.2

9.3

9.4

Decoder

Decoder output formatter

Scaler

VBI data decoder and capture

(subaddresses 40H to 7FH)

Image port output formatter

(subaddresses 84H to 87H)

Audio clock generation

(subaddresses 30H to 3FH)

21.2

21.3

21.4

21.5

Suitability of surface mount IC packages for

wave and reflow soldering methods

9.5

9.6

DATA SHEET STATUS

DEFINITIONS

DISCLAIMERS

PURCHASE OF PHILIPS I²C COMPONENTS

INPUT/OUTPUT INTERFACES AND PORTS

OF DIGITAL VIDEO DECODER PART

10.1

10.2

Analog terminals

Audio clock signals

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

FEATURES

1.1

Video decoder

• Six analog inputs, internal analog source selectors, e.g.

6 × CVBS or (2 × Y/C and 2 × CVBS) or (1 × Y/C and

4 × CVBS)

• Enhanced ITU 656 output format on IPD output bus

• Two analog preprocessing channels in differential

containing:

CMOS style for best S/N-performance

– active video

• Fully programmable static gain or Automatic Gain

Control (AGC) for the selected CVBS or Y/C channel

– raw CVBS data for INTERCAST applications

(27 MHz data rate)

• Switchable white peak control

– decoded VBI data

• Two built-in analog anti-aliasing filters

• Detection of copy protected input signals according to

the macrovision standard. Can be used to prevent

unauthorized recording of pay-TV or video tape signals.

• Two 9-bit video CMOS Analog-To-Digital Converters

(ADCs), digitized CVBS or Y/C signals are available on

the IPD (Image Port Data) port under I²C-bus control

• On-chip clock generator

1.2

Video scaler

• Line-locked system clock frequencies

• Both up and downscaling

• Digital PLL for horizontal sync processing and clock

• Conversion to square pixel format

• NTSC to 288 lines (video phone)

generation, horizontal and vertical sync detection

• Requires only one crystal (either 24.576 MHz or

• Phase accuracy better than ¹/₆₄pixel or line, horizontally

32.11 MHz) for all standards

or vertically

• Automatic detection of 50 and 60 Hz field frequency,

and automatic switching between PAL and NTSC

standards

• Independent scaling definitions for odd and even fields

• Anti-alias filter for horizontal scaling

• Provides output as

• Luminance and chrominance signal processing for

PAL BGHI, PAL N, combination PAL N, PAL M,

NTSC M, NTSC-Japan, NTSC N, NTSC 4.43 and

SECAM

– scaled active video

– raw CVBS data for INTERCAST, WAVE-PHORE,

POPCON applications or general VBI data decoding

(27 MHz or sample rate converted)

• User programmable luminance peaking or aperture

correction

• Local video output for Y-C_B-C_R4 : 2 : 2 format (VMI,

VIP, ZV).

• Cross-colour reduction for NTSC by chrominance comb

filtering

• PAL delay line for correcting PAL phase errors

1.3

Video encoder

• Brightness Contrast Saturation (BCS) and hue control

on-chip

• Digital PAL/NTSC encoder with integrated high quality

scaler and anti-flicker filter for TV output from a PC

• Two multi functional real-time output pins controlled by

I²C-bus

• 27 MHz crystal-stable subcarrier generation

• Maximum graphics pixel clock 45 MHz at double edged

clocking, synthesized on-chip or from external source

• Multi-standard VBI data slicer decoding World Standard

Teletext (WST), North-American Broadcast Text

System (NABTS), Closed Caption (CC), Wide Screen

Signalling (WSS), Video Programming System (VPS),

Vertical Interval Time Code (VITC) variants

(EBU/SMPTE) etc.

• Up to 800 × 600 graphics data at 60 Hz or 50 Hz with

programmable underscan range

• Three Digital-to-Analog Converters (DACs) at 27 MHz

sample rate for CVBS (BLUE, C_B), VBS (GREEN,

CVBS) and C (RED, C_R) (signals in parenthesis are

optional); all at 10-bit resolution

• Standard ITU 656 Y-C_B-C_R4 : 2 : 2 format (8-bit) on IPD

output bus

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

• Selectable cross-colour reduction to improve CVBS

1.4

Common features

output

• 5 V tolerant digital I/O ports

• I²C-bus controlled (full read-back ability by an external

controller, bit rate up to 400 kbits/s)

• Non-interlaced C_B-Y-C_Ror RGB input at maximum

4 : 4 : 4 sampling

• Downscaling from 1 : 1 to 1 : 2 and up to 20% upscaling

• Versatile power-save modes

• Optional interlaced C_B-Y-C_Rinput Digital Versatile Disk

(DVD)

• Boundary scan test circuit complies with the “IEEE Std.

1149.b1-1994” (separate ID codes for decoder and

encoder)

• Optional non-interlaced RGB output to drive second

VGA monitor (bypass mode, maximum 45 MHz)

• Monolithic CMOS 3.3 V device

• BGA156 package

• 3 × 256 bytes RGB Look-Up Table (LUT)

• Support for hardware cursor

• Moisture Sensitive Level (MSL): e3.

• Programmable border colour of underscan area

• On-chip 27 MHz crystal oscillator (3rd-harmonic or

fundamental 27 MHz crystal)

APPLICATIONS

• Notebook (low-power consumption)

• PCMCIA card application

• AGP based graphics cards

• PC editing

• Encoder can be master or slave

• Programmable horizontal and vertical input

synchronization phase

• Programmable horizontal sync output phase

• Internal Colour Bar Generator (CBG)

• Optional support of various VBI data insertion as

– WST-625, WSS, VPS

• Image processing

• Video phone applications

• INTERCAST and PC teletext applications

• Security applications

– WST-525, NABTS

• Hybrid satellite set-top boxes.

– Closed Caption, Copy Generation Management

System (CGMS)

• Macrovision Pay-per-View copy protection system

rev. 7.01 and rev. 6.1 as option; this applies to

SAA7108E only. The device is protected by USA patent

numbers 4631603, 4577216 and 4819098 and other

intellectual property rights. Use of the Macrovision

anti-copy process in the device is licensed for

non-commercial home use only. Reverse engineering or

disassembly is prohibited. Please contact your nearest

Philips Semiconductors sales office for more

information.

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

GENERAL DESCRIPTION

including source selection, anti-aliasing filter and

Analog-to-Digital Converter (ADC), automatic clamp and

gain control, a Clock Generation Circuit (CGC), and a

digital multi-standard decoder (PAL BGHI, PAL M, PAL N,

combination PAL N, NTSC M, NTSC-Japan, NTSC N,

NTSC 4.43 and SECAM).

The SAA7108E; SAA7109E is a new multi-standard video

decoder and encoder chip, offering high quality video input

and TV output processing as required by PC-99

specifications. It enables hardware manufacturers to

implement versatile video functions on a significantly

reduced printed-circuit board area at very competitive

costs.

The decoder includes a brightness, contrast and

saturation control circuit, a multi-standard VBI data slicer

and a 27 MHz VBI data bypass. The pure 3.3 V (5 V

compatible) CMOS circuit SAA7108E; SAA7109E,

consisting of an analog front-end and digital video

decoder, a digital video encoder and analog back-end, is a

highly integrated circuit especially designed for desktop

video applications.

Separate pins for supply voltages as well as for I²C-bus

control and boundary scan test have been provided for the

video encoder and decoder sections to ensure both

flexible handling and optimized noise behaviour.

The video encoder is used to encode PC graphics data at

maximum 800 × 600 resolution to PAL (50 Hz) or NTSC

(60 Hz) video signals. A programmable scaler and

interlacer ensures properly sized and flicker-free TV

display as CVBS or S-video output.

The decoder is based on the principle of line-locked clock

decoding and is able to decode the colour of PAL, SECAM

and NTSC signals into ITU-R BT.601 compatible colour

component values.

Alternatively, the three Digital-to-Analog Converters

(DACs) can output RGB signals together with a TTL

composite sync to feed SCART connectors.

The encoder can operate fully independently at its own

variable pixel clock, transporting graphics input data, and

at the line-locked, single crystal-stable video encoding

clock.

When the scaler/interlacer is bypassed, a second VGA

monitor can be connected to the RGB outputs and

separate H and V-syncs as well, thereby serving as an

auxiliary monitor at maximum 800 × 600 resolution/60 Hz

(PIXCLK < 45 MHz).

As an option, it is possible to slave the video PAL/NTSC

encoding to the video decoder clock with the encoder FIFO

acting as a buffer to decouple the line-locked decoder

clock from the crystal-stable encoder clock.

The video decoder, a 9-bit video input processor, is a

combination of a 2-channel analog pre-processing circuit

QUICK REFERENCE DATA

SYMBOL

V_DDD

PARAMETER

CONDITIONS

MIN.

3.0

TYP. MAX. UNIT

digital supply voltage

3.3

−

3.6

3.45

V_DDA

T_amb

P_A+D

analog supply voltage

3.15

ambient temperature

°C

analog and digital power dissipation note 1

−

1.4

Note

1. Power dissipation is extremely dependent on programming and selected application.

ORDERING INFORMATION

TYPE

PACKAGE

NUMBER

NAME

DESCRIPTION

VERSION

SAA7108E

BGA156

plastic ball grid array package; 156 balls; body 15 × 15 × 1.15 mm

SOT472-1

SAA7109E

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

BLOCK DIAGRAMS

digital video

handbook, full pagewidth

input and output

X port

ANALOG VIDEO

ACQUISITION AND

DEMODULATOR

I port

CVBS, Y/C

analog

video input

digital

video output

SCALER

(IPD)

VIDEO DECODER PART

VIDEO ENCODER PART

SCALER

AND

INTERLACER

Y-C -C /RGB

CVBS, Y/C

RGB

analog

video output

digital video

graphics input

VIDEO

ENCODER

MHB903

Fig.1 Simplified block diagram.

2004 Mar 16

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DDEe

SSAe

SSEe

DUMP

TDIe

TCKe

TMSe

DDAe

SSIe

RSET

TRSTe

TDOe

DDXe

DDIe

SSXe

A10, B6, D6

B9, C9,

C5,

A7,

C1, C2, B1,

B2, A2, B4,

B3, A3, F3,

H1, H2, H3

RGB TO Y-C -C

CURSOR

INSERTION

PD11 to

PD0

INPUT

FORMATTER

RGB LUT

(OR BYPASS)

MATRIX

(OR BYPASS)

VERTICAL

DECIMATOR

4 : 4 : 4 to 4 : 2 : 2

(OR BYPASS)

HORIZONTAL

SCALER

SCALER AND

ANTI-FLICKER

FILTER

FIFO

PIXCLKI

BLUE_CB_CVBS

GREEN_VBS_CVBS

RED_CR_C

VIDEO

ENCODER

BORDER

GENERATOR

TRIPLE

DAC

SAA7108E

SAA7109E

HSM_CSYNC

VSM

OSCILLATOR/

DTO

TIMING

GENERATOR

CGC

LOW-PASS

I C-BUS

PIXCLKO

CONTROL

XTALOe

G1 F1 G3 E3 C4

SDAe

mhb902

XTALIe

VSVGC

HSVGC

CBO

RESET

TTX_SRES

FSVGC

SCLe

27 MHz

TTXRQ_XCLKO2

Fig.2 Block diagram (video encoder part).

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[

]

LLC2

RTS0

XCLK XPD 7:0

XRV

XTRI

TEST5

TEST3

TEST1

TEST0

[

]

LLC

RTCO

(1)

RTS1 XDQ

XRH XRDY

HPD 7:0

SDAd SCLd

TEST4

TEST2

M14 L14 L13 K13 L10 M3 M4 K2, K3,

L1 to L3

N2 L5 N3 K1

A13, D12, C12, L12

B12, A12, C11,

B11, A11

M11

C10 B10 H13

M1, M2, N1

REAL-TIME OUTPUT

EXPANSION PORT PIN MAPPING

I/O CONTROL

I C-BUS

M12

N14

RES

chrominance of 16-bit input

X PORT I/O FORMATTING

E14, D14,

C14, B14,

E13, D13,

C13, B13

CLOCK GENERATION

AND

POWER-ON CONTROL

XTOUTd

XTALId

XTALOd

SAA7108E

SAA7109E

A/B

MUX

PROGRAMMING

ARRAY

[

]

IPD 7:0

H14

G12

F13

F14

G13

IDQ

P13

P11

P10

AI11

AI12

IGPH

IGPV

IGP0

IGP1

EVENT CONTROLLER

DIGITAL

AI21

DECODER

ANALOG

WITH

AI22

DUAL

ADC

FIR-PREFILTER

PRESCALER

AND

HORIZONTAL

FINE

ADAPTIVE

COMB

LINE

VERTICAL

FIFO

AI23

SCALING

BUFFER

(PHASE)

SCALING

VIDEO

FIFO

FILTER

AI24

SCALER BCS

8(16)

MUX

M10

AOUT

H12

P12

ICLK

AI1D

AI2D

BOUNDARY

SCAN

AUDIO

CLOCK

GENERATION

GENERAL PURPOSE

VBI DATA SLICER

TEXT

FIFO

TEST

J14

N10

AGND

ITRDY

ITRI

G14

VIDEO/TEXT

ARBITER

M7,

D11, F11,

J4, J11,

L4, L11

D10, G11, M8, M9, E11, K4, H4, H11, N7 to N9,

N4 M6 M5 N6 N5 K12 J13 K14 J12 L8 P5

L7, L9

N11

K11

L6, M13 N12, N13

MHB887

TCKd TDId AMCLK ASCLK

SSEd

DDXd

DDId

DDAd

TMSd TDOd ALRCLK AMXCLK

(1)

DDEd

TRSTd

SSAd

SSXd

SSId

(1) The pins RTCO and ALRCLK are used for configuration of the I²C-bus interface

and the definition of the crystal oscillator frequency at RESET (pin strapping).

Fig.3 Block diagram (video decoder part).

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

PINNING

SYMBOL

PIN TYPE⁽¹⁾

DESCRIPTION

PD7

MSB of encoder input bus with C_B-Y-C_R4 : 2 : 2; see Tables 25 to 31 for pin

assignment

PD4

MSB − 3 of encoder input bus with C_B-Y-C_R4 : 2 : 2; see Tables 25 to 31 for

pin assignment

TRSTe

I/pu

test reset input for Boundary Scan Test (BST) (encoder); active LOW; with

internal pull-up; notes 2 and 3

XTALIe

XTALOe

DUMP

V_SSXe

RSET

V_DDAe

HPD0

HPD3

HPD7

PD9

27 MHz crystal input (encoder)

27 MHz crystal output (encoder)

DAC reference pin (encoder), 12 Ω resistor connected to V_SSAe

ground for oscillator (encoder)

DAC reference pin (encoder), 1 kΩ resistor connected to V_SSAe

3.3 V analog supply voltage (encoder)

MSB − 7 of Host Port Data (HPD) output bus

MSB − 4 of HPD output bus

A10

A11

A12

A13

I/O

MSB of HPD output bus

see Tables 25, 30 and 31 for pin assignment with different encoder input

formats

PD8

PD5

PD6

see Tables 25, 30 and 31 for pin assignment with different encoder input

formats

MSB − 2 of encoder input bus with C_B-Y-C_R4 : 2 : 2; see Tables 25 to 31 for

pin assignment

MSB − 1 of encoder input bus with C_B-Y-C_R4 : 2 : 2; see Tables 25 to 31 for

pin assignment

TDIe

I/pu

test data input for BST (encoder); note 4

3.3 V analog supply voltage (encoder)

DAC reference pin (encoder); connected to A7

analog ground (encoder)

V_DDAe

DUMP

V_SSAe

V_DDAe

TEST1

HPD1

HPD4

IPD0

3.3 V analog supply voltage (encoder)

scan test input 1, do not connect

MSB − 6 of HPD output bus

B10

B11

B12

B13

B14

I/O

MSB − 3 of HPD output bus

MSB − 7 of IPD output bus

IPD4

MSB − 3 of Image Port Data (IPD) output bus

PD11

see Tables 25, 30 and 31 for pin assignment with different encoder input

formats

PD10

see Tables 25, 30 and 31 for pin assignment with different encoder input

formats

TTX_SRES

teletext input or sync reset input (encoder)

TTXRQ_XCLKO2

teletext request output or 13.5 MHz clock output of the crystal oscillator

(encoder)

V_SSIe

digital ground core (encoder)

BLUE or C_Bor CVBS output

BLUE_CB_CVBS

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

SYMBOL

PIN TYPE⁽¹⁾

DESCRIPTION

GREEN or VBS or CVBS output

GREEN_VBS_CVBS C7

RED_CR_C

V_DDAe

RED or C_Ror C output

3.3 V analog supply voltage (encoder)

scan test input 2, do not connect

MSB − 5 of HPD output bus

TEST2

HPD2

C10

C11

C12

C13

C14

I/O

HPD5

MSB − 2 of HPD output bus

IPD1

MSB − 6 of IPD output bus

IPD5

MSB − 2 of IPD output bus

TDOe

test data output for BST (encoder); note 4

reset input (encoder); active LOW

RESET

TMSe

I/pu

test mode select input for BST (encoder); note 4

3.3 V digital supply voltage for core (encoder)

digital ground core (encoder)

V_DDIe

V_SSIe

V_DDXe

3.3 V supply voltage for oscillator (encoder)

vertical synchronization output to VGA monitor (non-interlaced)

VSM

HSM_CSYNC

horizontal synchronization output to VGA monitor (non-interlaced) or

composite sync for RGB-SCART

V_DDAe

V_DDEd

V_DDId

HPD6

IPD2

D10

D11

D12

D13

D14

3.3 V analog supply voltage (encoder)

3.3 V digital supply voltage for peripheral cells (decoder)

3.3 V digital supply voltage for core (decoder)

MSB − 1 of HPD output bus

I/O

MSB − 5 of IPD output bus

IPD6

MSB − 1 of IPD output bus

TCKe

SCLe

HSVGC

I/pu

test clock input for BST (encoder); note 4

I²C-bus serial clock input (encoder)

I/O

horizontal synchronization output to Video Graphics Controller (VGC)

(optional input)

V_SSEe

V_SSId

E11

E12

E13

E14

−

digital ground peripheral cells (encoder)

digital ground core (decoder)

not connected

n.c.

IPD3

I/O

MSB − 4 of IPD output bus

IPD7

MSB of IPD output bus

VSVGC

PIXCLKI

PD3

vertical synchronization output to VGC (optional input)

pixel clock input (looped through)

MSB − 4 of encoder input bus with C_B-Y-C_R4 : 2 : 2; see Tables 25 to 31 for

pin assignment

V_DDEe

V_DDId

n.c.

−

3.3 V digital supply voltage for peripheral cells (encoder)

3.3 V digital supply voltage for core (decoder)

not connected

F11

F12

F13

F14

IGPV

IGP0

multi-purpose vertical reference output with IPD output bus

general purpose output signal 0 with IPD output bus

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

SYMBOL

PIN TYPE⁽¹⁾

DESCRIPTION

FSVGC

SDAe

CBO

I/O

frame synchronization output to VGC (optional input)

I²C-bus serial data input/output (encoder)

composite blanking output to VGC; active LOW

pixel clock output to VGC

PIXCLKO

V_DDEd

IGPH

IGP1

G11

G12

G13

G14

3.3 V digital supply voltage for peripheral cells (decoder)

multi-purpose horizontal reference output with IPD output bus

general purpose output signal 1 with IPD output bus

programmable control signals for IPD output bus

ITRI

I/(O)

PD2

MSB − 5 of encoder input bus with C_B-Y-C_R4 : 2 : 2; see Tables 25 to 31 for

pin assignment

PD1

PD0

MSB − 6 of encoder input bus with C_B-Y-C_R4 : 2 : 2; see Tables 25 to 31 for

pin assignment

MSB − 7 of encoder input bus with C_B-Y-C_R4 : 2 : 2; see Tables 25 to 31 for

pin assignment

V_SSEd

H11

H12

H13

H14

digital ground for peripheral cells (decoder)

clock for IPD output bus (optional clock input)

scan test output, do not connect

V_SSEd

ICLK

I/O

TEST0

IDQ

data qualiﬁer for IPD output bus

TEST4

TEST5

TEST3

V_DDId

scan test output, do not connect

scan test input, do not connect

3.3 V digital supply voltage for core (decoder)

audio master external clock input

V_DDId

J11

J12

J13

AMXCLK

ALRCLK

(I/)O

audio left/right clock output; can be strapped to supply via a 3.3 kΩ resistor to

indicate that the default 24.576 MHz crystal (ALRCLK = 0; internal pull-down)

has been replaced by a 32.110 MHz crystal (ALRCLK = 1); notes 5 and 6

ITRDY

XTRI

J14

target ready input for IPD output bus

control signal for all X port pins

MSB of XPD bus

XPD7

XPD6

V_SSId

I/O

MSB − 1 of XPD bus

digital ground core (decoder)

audio master clock output, must be less than 50% of crystal clock

real-time status or sync information line 0

audio serial clock output

V_SSId

K11

K12

K13

K14

AMCLK

RTS0

ASCLK

XPD5

XPD4

XPD3

V_DDId

XRV

I/O

MSB − 2 of XPD bus

MSB − 3 of XPD bus

MSB − 4 of XPD bus

3.3 V digital supply voltage for core (decoder)

vertical reference for XPD bus

I/O

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

SYMBOL

PIN TYPE⁽¹⁾

DESCRIPTION

V_SSEd

V_DDEd

V_DDXd

V_DDEd

RTS1

V_DDId

SDAd

RTCO

digital ground for peripheral cells (decoder)

3.3 V digital supply voltage for peripheral cells (decoder)

3.3 V supply voltage for oscillator (decoder)

3.3 V digital supply voltage for peripheral cells (decoder)

real-time status or sync information line 1

L10

L11

L12

L13

3.3 V digital supply voltage for core (decoder)

I²C-bus serial data input/output (decoder)

I/O

(I/)O

real-time control output; contains information about actual system clock

frequency, ﬁeld rate, odd/even sequence, decoder status, subcarrier

frequency and phase and PAL sequence (see external document “RTC

Functional Description”, available on request); the RTCO pin is enabled via

I²C-bus bit RTCE; see notes 5 and 7 and Table 146

LLC2

XPD2

XPD1

XCLK

XDQ

L14

I/O

I/pu

line-locked ¹⁄₂clock output (13.5 MHz nominal)

MSB − 5 of XPD bus

MSB − 6 of XPD bus

clock for XPD bus

data qualiﬁer for XPD bus

TMSd

TCKd

V_SSAd

V_DDAd

AOUT

SCLd

RES

test mode select input for BST (decoder); note 4

test clock input for BST (decoder); note 4

analog ground (decoder)

3.3 V analog supply voltage (decoder)

analog test output (do not connect)

I²C-bus serial clock input (decoder)

reset output signal; active LOW (decoder)

digital ground for peripheral cells (decoder)

line-locked clock output (27 MHz nominal)

MSB − 7 of XPD bus

M10

M11

M12

M13

M14

V_SSEd

LLC

XPD0

XRH

I/O

horizontal reference for XPD bus

data input ready for XPD bus

XRDY

TRSTd

I/pu

test reset input for BST (decoder); active LOW; with internal pull-up;

notes 2 and 3

TDOd

TDId

I/pu

test data output for BST (decoder); note 4

test data input for BST (decoder); note 4

analog ground (decoder)

V_SSAd

AGND

V_DDAd

V_SSAd

analog ground (decoder)

N10

N11

N12

N13

N14

analog ground (decoder) connected to substrate

3.3 V analog supply voltage (decoder)

analog ground (decoder)

chip enable or reset input (with internal pull-up)

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

SYMBOL

PIN TYPE⁽¹⁾

DESCRIPTION

27 MHz crystal input (decoder)

27 MHz crystal output (decoder)

XTALId

XTALOd

XTOUTd

V_SSXd

AI24

crystal oscillator output signal (decoder); auxiliary signal

ground for crystal oscillator (decoder)

analog input 24

AI23

analog input 23

AI2D

differential analog input for channel 2; connect to ground via a capacitor

AI22

analog input 22

AI21

P10

P11

P12

P13

analog input 21

AI12

analog input 12

AI1D

differential analog input for channel 1; connect to ground via a capacitor

analog input 11

AI11

Notes

1. Pin type: I = input, O = output, S = supply, pu = pull-up.

2. For board design without boundary scan implementation connect TRSTe and TRSTd to ground.

3. This pin provides easy initialization of the Boundary Scan Test (BST) circuit. TRSTe and TRSTd can be used to force

the Test Access Port (TAP) controller to the TEST_LOGIC_RESET state (normal operation) at once.

4. In accordance with the “IEEE1149.1” standard the pads TDIe (TDId), TMSe (TMSd), TCKe (TCKd) and TRSTe

(TRSTd) are input pads with an internal pull-up resistor and TDOe (TDOd) is a 3-state output pad.

5. Pin strapping is done by connecting the pin to supply via a 3.3 kΩ resistor. During the power-up reset sequence the

corresponding pins are switched to input mode to read the strapping level. For the default setting no strapping

resistor is necessary (internal pull-down).

6. Pin ALRCLK: 0 = 24.576 MHz crystal (default); 1 = 32.110 MHz crystal.

7. Pin RTCO: operates as I²C-bus slave address pin; RTCO = 0 slave address 42H/43H (default); RTCO = 1 slave

address 40H/41H.

MHB888

handbook, halfpage

SAA7108E

SAA7109E

2 3 4 5 6 7 8 9 10 11 12 13 14

Fig.4 Pin configuration.

2004 Mar 16

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Table 1 Pin assignment (top view)

PD7

PD8

PD10

PD4

PD5

TRSTe XTALIe XTALOe

DUMP

GREEN_

V_SSXe

RSET V_DDAeHPD0 HPD3

V_DDAeTEST1 HPD1 HPD4

HPD7

IPD0

IPD1

PD9

PD6

TDIe

V_DDAe

V_SSAe

IPD4

IPD5

PD11

TTX_ TTXRQ_ V_SSIe

SRES XCLKO2

BLUE_

CB_CVBS VBS_CVBS

RED_CR_C V_DDAeTEST2 HPD2 HPD5

TDOe RESET TMSe

V_DDIe

V_SSEe

V_DDEe

V_SSIe

V_DDXe

VSM

HSM_CSYNC V_DDAeV_DDEdV_DDId

HPD6

n.c.

IPD2

IPD3

IPD6

IPD7

IGP0

ITRI

TCKe

SCLe HSVGC

V_SSId

V_DDId

V_DDEd

V_SSEd

F VSVGC PIXCLKI

G FSVGC SDAe

PD3

n.c.

IGPV

IGP1

CBO PIXCLKO

IGPH

ICLK

PD2

PD1

PD0

V_SSEd

V_DDId

V_SSId

TEST0

IDQ

TEST4 TEST5 TEST3

V_DDIdAMXCLK ALRCLK ITRDY

XTRI

XPD5

XPD2

XPD0

XPD7

XPD4

XPD1

XRH

XPD6

XPD3

XCLK

XRDY

V_SSIdAMCLK

RTS0 ASCLK

V_DDId

XDQ

XRV

TMSd

TDOd

V_SSEd

TCKd

TDId

AI24

V_DDEd

V_SSAd

AI23

V_DDXd

V_DDAd

V_SSAd

AI2D

V_DDEdRTS1 V_DDId

SDAd

RES

RTCO

V_SSEd

V_SSAd

AI11

LLC2

LLC

V_DDAdAOUT SCLd

TRSTd

V_SSAdAGND V_DDAdV_SSAd

XTALId XTALOd XTOUTd V_SSXd

AI22

AI21

AI12

AI1D

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

FUNCTIONAL DESCRIPTION OF DIGITAL VIDEO

ENCODER PART

For ease of analog post filtering the signals are twice

oversampled to 27 MHz before digital-to-analog

conversion.

The digital video encoder encodes digital luminance and

colour difference signals (C_B-Y-C_R) or digital RGB signals

into analog CVBS, S-video and, optionally, RGB or

C_R-Y-C_Bsignals. NTSC M, PAL B/G and sub-standards

are supported.

The total filter transfer characteristics (scaler and

anti-flicker filter are not taken into account) are illustrated

in Figs 5 to 10. All three DACs are realized with full 10-bit

resolution. The C_R-Y-C_Bto RGB dematrix can be

bypassed (optionally) in order to provide the upsampled

C_R-Y-C_Binput signals.

The SAA7108E; SAA7109E can be directly connected to a

PC video graphics controller with a maximum resolution of

800 × 600 at a 50 or 60 Hz frame rate. A programmable

scaler scales the computer graphics picture so that it will fit

into a standard TV screen with an adjustable underscan

area. Non-interlaced-to-interlaced conversion is optimized

with an adjustable anti-flicker filter for a flicker-free display

at a very high sharpness.

The 8-bit multiplexed C_B-Y-C_Rformats are “ITU-R BT.656”

(D1 format) compatible, but the SAV and EAV codes can

be decoded optionally, when the device is operated in

slave mode. For assignment of the input data to the rising

or falling clock edge see Tables 25 to 31.

In order to display interlaced RGB signals through a

euro-connector TV set, a separate digital composite sync

signal (pin HSM_CSYNC) can be generated; it can be

advanced up to 31 periods of the 27 MHz crystal clock in

order to be adapted to the RGB processing of a TV set.

Besides the most common 16-bit 4 : 2 : 2 C_B-Y-C_Rinput

format (using 8 pins with double edge clocking), other

C_B-Y-C_Rand RGB formats are also supported; see

Tables 25 to 31.

A complete 3 × 256 bytes Look-Up Table (LUT), which can

be used, for example, as a separate gamma corrector, is

located in the RGB domain; it can be loaded either through

the video input port PD (Pixel Data) or via the I²C-bus.

The SAA7108E; SAA7109E synthesizes all necessary

internal signals, colour subcarrier frequency and

synchronization signals from that clock.

Wide screen signalling data can be loaded via the I²C-bus

and is inserted into line 23 for standards using a 50 Hz

field rate.

The SAA7108E; SAA7109E supports a 32 × 32 × 2-bit

hardware cursor, the pattern of which can also be loaded

through the video input port or via the I²C-bus.

VPS data for program dependent automatic start and stop

of such featured VCRs is loadable via the I²C-bus.

It is also possible to encode interlaced 4 : 2 : 2 video

signals such as PC-DVD; for that the anti-flicker filter, and

in most cases the scaler, will simply be bypassed.

The IC also contains Closed Caption and extended data

services encoding (line 21), and supports teletext insertion

for the appropriate bit stream format at a 27 MHz clock rate

(see Fig.50). It is also possible to load data for the copy

generation management system into line 20 of every field

(525/60 line counting).

Besides the applications for video output, the SAA7108E;

SAA7109E can also be used for generating a kind of

auxiliary VGA output, when the RGB non-interlaced input

signal is fed to the DACs. This may be of interest for

example, when the graphics controller provides a second

graphics window at its video output port.

A number of possibilities are provided for setting different

video parameters such as:

The basic encoder function consists of subcarrier

generation, colour modulation and insertion of

synchronization signals at a crystal-stable clock rate of

13.5 MHz (independent of the actual pixel clock used at

the input side), corresponding to an internal 4 : 2 : 2

bandwidth in the luminance/colour difference domain.

Luminance and chrominance signals are filtered in

accordance with the standard requirements of “RS-170-A”

and “ITU-R BT.470-3”.

• Black and blanking level control

• Colour subcarrier frequency

• Variable burst amplitude etc.

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

MBE737

handbook, full pagewidth

(dB)

−6

−12

−18

−24

−30

−36

(1)

(2)

−42

−48

−54

f (MHz)

(1) SCBW = 1.

(2) SCBW = 0.

Fig.5 Chrominance transfer characteristic 1.

MBE735

handbook, halfpage

(dB)

(1)

(2)

−2

−4

−6

0.4

0.8

1.2

1.6

f (MHz)

(1) SCBW = 1.

(2) SCBW = 0.

Fig.6 Chrominance transfer characteristic 2.

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

MGD672

handbook, full pagewidth

(dB)

(4)

(2)

(3)

−6

−12

−18

(1)

−24

−30

−36

−42

−48

−54

f (MHz)

(1) CCRS1 = 0; CCRS0 = 1.

(2) CCRS1 = 1; CCRS0 = 0.

(3) CCRS1 = 1; CCRS0 = 1.

(4) CCRS1 = 0; CCRS0 = 0.

Fig.7 Luminance transfer characteristic 1 (excluding scaler).

MBE736

handbook, halfpage

(dB)

(1)

−1

−2

−3

−4

−5

f (MHz)

(1) CCRS1 = 0; CCRS0 = 0.

Fig.8 Luminance transfer characteristic 2 (excluding scaler).

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

MGB708

handbook, full pagewidth

(dB)

−6

−12

−18

−24

−30

−36

−42

−48

−54

f (MHz)

Fig.9 Luminance transfer characteristic in RGB (excluding scaler).

MGB706

handbook, full pagewidth

(dB)

−6

−12

−18

−24

−30

−36

−42

−48

−54

f (MHz)

Fig.10 Colour difference transfer characteristic in RGB (excluding scaler).

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

8.1

Reset conditions

If Y-C_B-C_Ris being applied as a 27 Mbyte/s data stream,

the output of the input formatter can be used directly to

feed the video encoder block.

To activate the reset a pulse at least of 2 crystal clocks

duration is required.

During reset (RESET = LOW) plus an extra 32 crystal

clock periods, FSVGC, VSVGC, CBO, HSVGC and

TTX_SRES are set to input mode and HSM_CSYNC and

VSM are set to 3-state. A reset also forces the I²C-bus

interface to abort any running bus transfer and sets it into

receive condition.

8.3

RGB LUT

The three 256-byte RAMs of this block can be addressed

by three 8-bit wide signals, thus it can be used to build any

transformation, e.g. a gamma correction for RGB signals.

In the event that the indexed colour data is applied, the

RAMs are addressed in parallel.

After reset, the state of the I/Os and other functions is

defined by the strapping pins until an I²C-bus access

redefines the corresponding registers; see Table 2.

The LUTs can either be loaded by an I²C-bus write access

or can be part of the pixel data input through the PD port.

In the latter case, 256 × 3 bytes for the R, G and B LUT are

expected at the beginning of the input video line, two lines

before the line that has been defined as first active line,

until the middle of the line immediately preceding the first

active line. The first 3 bytes represent the first RGB LUT

data, and so on.

Table 2 Strapping pins

TIED

PRESET

FSVGC (pin G1)

LOW NTSC M encoding, PIXCLK

ﬁts to 640 × 480 graphics

input

8.4

Cursor insertion

HIGH PAL B/G encoding, PIXCLK

ﬁts to 640 × 480 graphics

input

A 32 × 32 dots cursor can be overlaid as an option; the bit

map of the cursor can be uploaded by an I²C-bus write

access to specific registers or in the pixel data input via the

PD port. In the latter case the 256 bytes defining the cursor

bit map (2 bits per pixel) are expected immediately

following the last RGB LUT data in the line preceding the

first active line.

VSVGC (pin F1)

CBO (pin G3)

LOW 4 : 2 : 2 Y-C_B-C_Rgraphics

input (format 0)

HIGH 4 : 4 : 4 RGB graphics input

(format 3)

LOW input demultiplex phase:

LSB = LOW

The cursor bit map is set up as follows: each pixel

occupies 2 bits. The meaning of these bits depends on the

CMODE I²C-bus register as described in Table 5.

Transparent means that the input pixels are passed

through, the ‘cursor colours’ can be programmed in

separate registers.

HIGH input demultiplex phase:

LSB = HIGH

HSVGC (pin E3)

LOW input demultiplex phase:

MSB = LOW

HIGH input demultiplex phase:

MSB = HIGH

The bit map is stored with 4 pixels per byte, aligned to the

least significant bit. So the first pixel is in bits 0 and 1, the

next pixel in bits 3 and 4 and so on. The first index is the

column, followed by the row; index 0,0 is the upper left

corner.

TTXRQ_XCLKO2 LOW slave (FSVGC, VSVGC and

(pin C4)

HSVGC are inputs, internal

colour bar is active)

HIGH master (FSVGC, VSVGC

and HSVGC are outputs)

Table 3 Layout of a byte in the cursor bit map

pixel n + 3

D1 D0

pixel n + 2

D1 D0

pixel n + 1

D1 D0

pixel n

8.2

Input formatter

The input formatter converts all accepted PD input data

formats, either RGB or Y-C_B-C_R, to a common internal

RGB or Y-C_B-C_Rdata stream.

For each direction, there are 2 registers controlling the

position of the cursor, one controls the position of the

‘hot spot’, the other register controls the insertion position.

The hot spot is the ‘tip’ of the pointer arrow.

When double-edge clocking is used, the data is internally

split into portions PPD1 and PPD2. The clock edge

assignment must be set according to the I²C-bus control

bits EDGE1 and EDGE2 for correct operation.

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

It can have any position in the bit map. The actual position

registers describe the co-ordinates of the hot spot. Again

0,0 is the upper left corner. While it is not possible to move

the hot spot beyond the left respectively upper screen

border this is perfectly legal for the right respectively lower

border. It should be noted that the cursor position is

described relative to the input resolution.

The matrix and formatting blocks can be bypassed for

Y-C_B-C_Rgraphics input.

When the auxiliary VGA mode is selected, the output of the

cursor insertion block is immediately directed to the triple

DAC.

8.6

Horizontal scaler

Table 4 Cursor bit map

The high quality horizontal scaler operates on the 4 : 2 : 2

data stream. Its control engines compensate the colour

phase offset automatically.

BYTE

D7 D6 D5 D4 D3 D2 D1 D0

row 0 row 0 row 0 row 0

column 3 column 2 column 1 column 0

row 0 row 0 row 0 row 0

column 7 column 6 column 5 column 4

The scaler starts processing after a programmable

horizontal offset and continues with a number of input

pixels. Each input pixel is a programmable fraction of the

current output pixel (XINC/4096). A special case is

XINC = 0, this sets the scaling factor to 1.

row 0

column

row 0

column

row 0

column 9 column 8

row 0

If the SAA7108E; SAA7109E input data is in accordance

with “ITU-R BT.656”, the scaler enters another mode.

In this event, XINC needs to be set to 2048 for a scaling

factor of 1. With higher values, upscaling will occur.

...

row 0

column

row 0

column

row 0

column

row 0

column

The phase resolution of the circuit is 12 bits, giving a

maximum offset of 0.2 after 800 input pixels. Small FIFOs

rearrange a 4 : 2 : 2 data stream at the scaler output.

row 0

column

row 0

column

row 0

column

row 0

column

8.7

Vertical scaler and anti-ﬂicker ﬁlter

...

The functions scaling, Anti-Flicker Filter (AFF) and

re-interlacing are implemented in the vertical scaler.

254

row 31

column

row 31

column

row 31

column

row 31

column

Besides the entire input frame, it receives the first and last

lines of the border to allow anti-flicker filtering.

255

row 31

column

row 31

column

row 31

column

row 31

column

The circuit generates the interlaced output fields by scaling

down the input frames with different offsets for odd and

even fields. Increasing the YSKIP setting reduces the

anti-flicker function. A YSKIP value of 4095 switches it off;

see Table 129.

Table 5 Cursor modes

CURSOR MODE

CURSOR

PATTERN

The programming is similar to the horizontal scaler. For the

re-interlacing, the resolutions of the offset registers are not

sufficient, so the weighting factors for the first lines can

also be adjusted. YINC = 0 sets the scaling factor to 1;

YIWGTO and YIWGTE must not be 0.

CMODE = 0

CMODE = 1

second cursor colour second cursor colour

ﬁrst cursor colour

transparent

ﬁrst cursor colour

transparent

Due to the re-interlacing, the circuit can perform upscaling.

The maximum factor depends on the setting of the

anti-flicker function and can be derived from the formulae

given in Section 8.17.

inverted input

auxiliary cursor

colour

8.5

RGB Y-C_B-C_Rmatrix

RGB input signals to be encoded to PAL or NTSC are

converted to the Y-C_B-C_Rcolour space in this block. The

colour difference signals are fed through low-pass filters

and formatted to a ITU-R BT.601 like 4 : 2 : 2 data stream

for further processing.

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

8.8

FIFO

Input to the encoder, at 27 MHz clock (e.g. DVD), is either

originated from computer graphics at pixel clock, fed

through the FIFO and border generator, or a ITU-R BT.656

style signal.

The FIFO acts as a buffer to translate from the PIXCLK

clock domain to the XTAL clock domain. The write clock is

PIXCLK and the read clock is XTAL. An underflow or

overflow condition can be detected via the I²C-bus read

access.

Luminance is modified in gain and in offset (the offset is

programmable in a certain range to enable different black

level set-ups). A blanking level can be set after insertion of

a fixed synchronization pulse tip level, in accordance with

standard composite synchronization schemes. Other

manipulations used for the Macrovision anti-taping

process, such as additional insertion of AGC super-white

pulses (programmable in height), are supported by the

SAA7108E only.

In order to avoid underflows and overflows, it is essential

that the frequency of the synthesized PIXCLK matches to

the input graphics resolution and the desired scaling

factor. It is suggested to refer to Tables 6 to 23 for some

representative combinations.

8.9

Border generator

To enable easy analog post filtering, luminance is

interpolated from a 13.5 MHz data rate to a 27 MHz data

rate, thereby providing luminance in a 10-bit resolution.

The transfer characteristics of the luminance interpolation

filter are illustrated in Figs 7 and 8. Appropriate transients

at start/end of active video and for synchronization pulses

are ensured.

When the graphics picture is to be displayed as interlaced

PAL, NTSC, S-video or RGB on a TV screen, it is desired

in many cases not to lose picture information due to the

inherent overscanning of a TV set. The desired amount of

underscan area, which is achieved through appropriate

scaling in the vertical and horizontal direction, can be filled

in the border generator with an arbitrary true colour tint.

Chrominance is modified in gain (programmable

separately for C_Band C_R), and a standard dependent

burst is inserted, before baseband colour signals are

interpolated from a 6.75 MHz data rate to a 27 MHz data

rate. One of the interpolation stages can be bypassed,

thus providing a higher colour bandwidth, which can be

used for the Y and C output. The transfer characteristics of

the chrominance interpolation filter are illustrated in

Figs 5 and 6.

8.10 Oscillator and Discrete Time Oscillator (DTO)

The master clock generation is realized as a 27 MHz

crystal oscillator, which can operate with either a

fundamental wave crystal or a 3rd-harmonic crystal.

The crystal clock supplies the DTO of the pixel clock

synthesizer, the video encoder and the I²C-bus control

block. It also usually supplies the triple DAC, with the

exception of the auxiliary VGA mode, where the triple DAC

is clocked by the pixel clock (PIXCLK).

The amplitude (beginning and ending) of the inserted

burst, is programmable in a certain range that is suitable

for standard signals and for special effects. After the

succeeding quadrature modulator, colour is provided on

the subcarrier in 10-bit resolution.

The DTO can be programmed to synthesize all relevant

pixel clock frequencies between circa 18 and 44 MHz.

8.11 Low-pass Clock Generation Circuit (CGC)

The numeric ratio between the Y and C outputs is in

accordance with the standards.

This block reduces the phase jitter of the synthesized pixel

clock. It works as a tracking filter for all relevant

synthesized pixel clock frequencies.

8.12.2 TELETEXT INSERTION AND ENCODING (NOT

SIMULTANEOUSLY WITH REAL-TIME CONTROL)

8.12 Encoder

Pin TTX_SRES receives a WST or NABTS teletext

bitstream sampled at the crystal clock. At each rising edge

of the output signal (TTXRQ) a single teletext bit has to be

provided after a programmable delay at input pin

TTX_SRES.

8.12.1 VIDEO PATH

The encoder generates luminance and colour subcarrier

output signals from the Y, C_Band C_Rbaseband signals,

which are suitable for use as CVBS or separate Y and C

signals.

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

Phase variant interpolation is achieved on this bitstream in

the internal teletext encoder, providing sufficient small

phase jitter on the output text lines.

The transfer curves of luminance and colour difference

components of RGB are illustrated in Figs 9 and 10.

8.14 Triple DAC

TTXRQ_XCLKO2 provides a fully programmable request

signal to the teletext source, indicating the insertion period

of bitstream at lines which can be selected independently

for both fields. The internal insertion window for text is set

to 360 (PAL WST), 296 (NTSC WST) or 288 (NABTS)

teletext bits including clock run-in bits. The protocol and

timing are illustrated in Fig.50.

Both Y and C signals are converted from digital-to-analog

in a 10-bit resolution at the output of the video encoder.

Y and C signals are also combined into a 10-bit CVBS

signal.

The CVBS output signal occurs with the same processing

delay as the Y, C and optional RGB or C_R-Y-C_Boutputs.

Absolute amplitude at the input of the DAC for CVBS is

Alternatively, this pin can be provided with a buffered

crystal clock (XCLK) of 13.5 MHz.

reduced by ¹⁵

⁄₁₆with respect to Y and C DACs to make

maximum use of the conversion ranges.

8.12.3 VIDEO PROGRAMMING SYSTEM (VPS) ENCODING

RED, GREEN and BLUE signals are also converted from

digital-to-analog, each providing a 10-bit resolution.

Five bytes of VPS information can be loaded via the

I²C-bus and will be encoded in the appropriate format into

line 16.

The reference currents of all three DACs can be adjusted

individually in order to adapt for different output signals.

In addition, all reference currents can be adjusted

commonly to compensate for small tolerances of the

on-chip band gap reference voltage.

8.12.4 CLOSED CAPTION ENCODER

Using this circuit, data in accordance with the specification

of Closed Caption or extended data service, delivered by

the control interface, can be encoded (line 21). Two

dedicated pairs of bytes (two bytes per field), each pair

Alternatively, all currents can be switched off to reduce

power dissipation.

preceded by run-in clocks and framing code, are possible. All three outputs can be used to sense for an external load

(usually 75 Ω) during a pre-defined output. A flag in the

The actual line number in which data is to be encoded, can

I²C-bus status byte reflects whether a load is applied or

be modified in a certain range.

not.

The data clock frequency is in accordance with the

If the SAA7108E; SAA7109E is required to drive a second

definition for NTSC M standard 32 times horizontal line

(auxiliary) VGA monitor, the DACs receive the signal

frequency.

directly from the cursor insertion block. In this event, the

Data LOW at the output of the DACs corresponds to 0 IRE,

data HIGH at the output of the DACs corresponds to

approximately 50 IRE.

DACs are clocked at the incoming PIXCLKI instead of the

27 MHz crystal clock used in the video encoder.

8.15 Timing generator

It is also possible to encode Closed Caption data for 50 Hz

field frequencies at 32 times the horizontal line frequency.

The synchronization of the SAA7108E; SAA7109E is able

to operate in two modes; slave mode and master mode.

8.12.5 ANTI-TAPING (SAA7108E ONLY)

In slave mode, the circuit accepts sync pulses on the

bidirectional FSVGC (frame sync), VSVGC (vertical sync)

and HSVGC (horizontal sync) pins: the polarities of the

signals can be programmed. The frame sync signal is only

necessary when the input signal is interlaced, in other

cases it may be omitted. If the frame sync signal is present,

it is possible to derive the vertical and the horizontal phase

from it by setting the HFS and VFS bits. HSVGC and

VSVGC are not necessary in this case, so it is possible to

switch the pins to output mode.

For more information contact your nearest Philips

Semiconductors sales office.

8.13 RGB processor

This block contains a dematrix in order to produce RED,

GREEN and BLUE signals to be fed to a SCART plug.

Before Y, C_Band C_Rsignals are de-matrixed, individual

gain adjustment for Y and colour difference signals and

2 times oversampling for luminance and 4 times

oversampling for colour difference signals is performed.

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

8.16 I²C-bus interface

Alternatively, the device can be triggered by auxiliary

codes in a ITU-R BT.656 data stream via PD7 to PD0.

The I²C-bus interface is a standard slave transceiver,

supporting 7-bit slave addresses and 400 kbits/s

guaranteed transfer rate. It uses 8-bit subaddressing with

an auto-increment function. All registers are write and

read, except two read only status bytes.

Only vertical frequencies of 50 and 60 Hz are allowed with

the SAA7108E; SAA7109E. In slave mode, it is not

possible to lock the encoders colour carrier to the line

frequency with the PHRES bits.

In the (more common) master mode, the time base of the

circuit is continuously free-running. The IC can output a

frame sync at pin FSVGC, a vertical sync at pin VSVGC, a

horizontal sync at pin HSVGC and a composite blanking

signal at pin CBO. All of these signals are defined in the

PIXCLK domain. The duration of HSVGC and VSVGC are

fixed, they are 64 clocks for HSVGC and 1 line for VSVGC.

The leading slopes are in phase and the polarities can be

programmed.

The register bit map consists of an RGB Look-Up Table

(LUT), a cursor bit map and control registers. The LUT

contains three banks of 256 bytes, where each RGB triplet

is assigned to one address. Thus a write access needs the

LUT address and three data bytes following subaddress

FFH. For further write access auto-incrementing of the

LUT address is performed. The cursor bit map access is

similar to the LUT access but contains only a single byte

per address.

The I²C-bus slave address is defined as 88H.

The input line length can be programmed. The field length

is always derived from the field length of the encoder and

the pixel clock frequency that is being used.

8.17 Programming the graphics acquisition scaler

of the video encoder

CBO acts as a data request signal. The circuit accepts

input data at a programmable number of clocks after CBO

goes active. This signal is programmable and it is possible

to adjust the following (see Figs 48 and 49):

In order to program the graphics acquisition scaler it is first

necessary to determine the input and output field timings.

The timings are controlled by decoding binary counters

that index the position in the current line and field

respectively. In both cases, 0 means the start of the sync

pulse.

• The horizontal offset

• The length of the active part of the line

• The distance from active start to first expected data

• The vertical offset separately for odd and even fields

• The number of lines per input field.

At 60 Hz, the first visible pixel has the index 256,

710 pixels can be encoded; at 50 Hz, the index is 284,

702 pixels can be visible. Some variables are defined

below:

In most cases, the vertical offsets for odd and even fields

are equal. If they are not, then the even field will start later.

The SAA7108E; SAA7109E will also request the first input

lines in the even field, the total number of requested lines

will increase by the difference of the offsets.

• InPix: the number of active pixels per input line

• InPpl: the length of the entire input line in pixel clocks

• InLin: the number of active lines per input field/frame

• TPclk: the pixel clock period

As stated above, the circuit can be programmed to accept

the look-up and cursor data in the first 2 lines of each field.

The timing generator provides normal data request pulses

for these lines; the duration is the same as for regular lines.

The additional request pulses will be suppressed with

LUTL set to logic 0; see Table 139. The other vertical

timings do not change in this case, so the first active line

can be number 2, counted from 0.

• OutPix: the number of active pixels per output line

• OutLin: the number of active lines per output field

• TXclk: the encoder clock period (37.037 ns).

The output lines should be centred on the screen. It should

be noted that the encoder has 2 clocks per pixel;

see Table 106.

ADWHS = 256 + 710 − OutPix (60 Hz);

ADWHS = 284 + 702 − OutPix (50 Hz);

ADWHE = ADWHS + OutPix × 2 (all frequencies)

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

For vertical, the procedure is the same. At 60 Hz, the first

line with video information is number 19, 240 lines can be

active. For 50 Hz, the numbers are 23 and 287;

see Table 112.

Once the timings are known the scaler can be

programmed.

XOFS can be chosen arbitrarily, the condition being that

XOFS + XPIX ≤ HLEN is fulfilled. Values given by the

VESA display timings are preferred.

240 – OutLin

FAL = 19 +

FAL = 23 +

(60 Hz);

(50 Hz);

---------------------------------

OutPix

-----------------

InPix

------------

HLEN = InPpl − 1 XPIX =

XINC =

× 4096

287 – OutLin

---------------------------------

XINC needs to be rounded up, it needs to be set to 0 for a

scaling factor of 1.

LAL = FAL + OutLin (all frequencies)

Most TV sets use overscan, and not all pixels respectively

lines are visible. There is no standard for the factor, it is

highly recommended to make the number of output pixels

and lines adjustable. A reasonable underscan factor is

10%, giving approximately 640 output pixels per line.

YPIX = InLin

YSKIP defines the anti-flicker function. 0 means maximum

flicker reduction but minimum vertical bandwidth, 4095

gives no flicker reduction and maximum bandwidth.

The total number of pixel clocks per line and the input

horizontal offset need to be chosen next. The only

constraint is that the horizontal blanking has at least

10 clock pulses.

OutLin

YINC = ---------------------- × 1 +

InLin + 2

YSKIP

-----------------

4095

× 4096

YINC

YIWGTO =

YIWGTE =

+ 2048

-------------

The required pixel clock frequency can be determined in

the following way: Due to the limited internal FIFO size, the

input path has to provide all pixels in the same time frame

as the encoders vertical active time. The scaler also has to

process the first and last border lines for the anti-flicker

function. Thus:

YINC – YSKIP

-------------------------------------

When YINC = 0 it sets the scaler to scaling factor 1. The

initial weighting factors must not be set to 0 in this case.

YIWGTE may go negative. In this event, YINC should be

added and YOFSE incremented. This can be repeated as

often as necessary to make YIWGTE positive.

262.5 × 1716 × TXclk

TPclk =

(60 Hz)

---------------------------------------------------------------------------------------

InLin + 2

InPpl × integer

× 262.5

----------------------

OutLin

Due to the limited amount of memory it is not possible to

get valid vertical scaler settings only from the formulae

above. In some cases it is necessary to adjust the vertical

offsets or the scaler increment to get valid settings.

Tables 6 to 23 show verified settings. They are organised

in the following way: The tables are separate for the

standard to be encoded, the input resolution and three

different anti-flicker filter settings. Each table contains

5 vertical sizes with 5 different offsets. They are intended

to be selected according to the current TV set. The

corresponding horizontal resolutions of 640 pixels give

proper aspect ratios. They can be adjusted according to

the formulae above. The next line gives a minimum size

intended to fit on the screen under all circumstances. The

corresponding horizontal resolution is 620 pixels.

Overscan is only possible with an input resolution of

800 × 600 pixels. Where possible, the corresponding

settings are given on the last lines of the tables.

312.5 × 1728 × TXclk

TPclk =

(50 Hz)

---------------------------------------------------------------------------------------

InLin + 2

OutLin

InPpl × integer

× 312.5

----------------------

TXclk

and for the pixel clock generator PCL =

× 2²¹

--------------

TPclk

(all frequencies); see Table 115.

The input vertical offset can be taken from the assumption

that the scaler should just have finished writing the first line

when the encoder starts reading it:

FAL × 1716 × TXclk

YOFS =

– 2 (60 Hz)

– 2 (50 Hz)

----------------------------------------------------

InPpl × TPclk

FAL × 1728 × TXclk

----------------------------------------------------

InPpl × TPclk

In most cases the vertical offsets will be the same for odd

and even fields. The results should be rounded down.

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

8.18 Input levels and formats

The SAA7108E; SAA7109E accepts digital Y, C_B, C_Ror RGB data with levels (digital codes) in accordance with

“ITU-R BT.601”; see Table 24.

For C and CVBS outputs, deviating amplitudes of the colour difference signals can be compensated for by independent

gain control setting, while gain for luminance is set to predefined values, distinguishable for 7.5 IRE set-up or without

set-up.

The RGB, respectively C_R-Y-C_Bpath features an individual gain setting for luminance (GY) and colour difference signals

(GCD). Reference levels are measured with a colour bar, 100% white, 100% amplitude and 100% saturation.

Table 6 Y scaler programming at NTSC, input frame size: 640 × 400, full anti-ﬂicker ﬁlter

TV LINE

OFFSET FAL LAL

PCL

YINC YSKIP

YOFSO

YOFSE

YIWGTO

YIWGTE

Regular size (horizontal TV size: 640 pixels, offset ±10 pixels)

212

214

216

218

220

−4

−2

241

243

245

247

249

242

244

246

248

250

243

245

247

249

251

244

246

248

250

252

245

247

249

251

253

1851099

1836201

1817578

1802680

1784057

2163

2181

2202

2222

2245

3128

3138

3148

3158

3168

1080

1090

1100

1110

1120

−4

−2

−4

−2

−4

−2

−4

−2

Overscan (horizontal size: 710 pixels)

241

Small size (horizontal size: 620 pixels)

204

241

1925590

2079

3087

1039

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

Table 7 Y scaler programming at NTSC, input frame size: 640 × 400, half anti-ﬂicker ﬁlter

TV LINE

OFFSET FAL LAL

PCL

YINC YSKIP

YOFSO

YOFSE

YIWGTO

YIWGTE

Regular size (horizontal TV size: 640 pixels, offset ±10 pixels)

212

214

216

218

220

−4

−2

241

243

245

247

249

242

244

246

248

250

243

245

247

249

251

244

246

248

250

252

245

247

249

251

253

1851099

1836201

1817578

1802680

1784057

3123

3135

3145

3155

3165

1820

1790

1750

1720

1680

3668

3683

3698

3714

3729

596

611

626

642

657

−4

−2

−4

−2

−4

−2

−4

−2

Full size (horizontal size: 710 pixels)

241

Small size (horizontal size: 620 pixels)

204

241

1925590

3087

1980

3589

551

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

Table 8 Y scaler programming at NTSC, input frame size: 640 × 400, no anti-ﬂicker ﬁlter

TV LINE

OFFSET FAL LAL

PCL

YINC YSKIP

YOFSO

YOFSE

YIWGTO

YIWGTE

Regular size (horizontal TV size: 640 pixels, offset ±10 pixels)

212

214

216

218

220

−4

−2

241

243

245

247

249

242

244

246

248

250

243

245

247

249

251

244

246

248

250

252

245

247

249

251

253

1851099

1836201

1817578

1802680

1784057

4094

4090

4088

4093

4092

4090

3655

3580

3510

3445

3370

4092

4091

4092

4091

216

253

288

322

358

−4

−2

−4

−2

−4

−2

−4

−2

Full size (horizontal size: 710 pixels)

241

Small size (horizontal size: 620 pixels)

204

241

1925590

4087

3950

4089

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

Table 9 Y scaler programming at NTSC, input frame size: 640 × 480, full anti-ﬂicker ﬁlter

TV LINE

OFFSET FAL LAL

PCL

YINC YSKIP

YOFSO

YOFSE

YIWGTO

YIWGTE

Regular size (horizontal TV size: 640 pixels, offset ±10 pixels)

212

214

216

218

220

−4

−2

241

243

245

247

249

242

244

246

248

250

243

245

247

249

251

244

246

248

250

252

245

247

249

251

253

2219829

2201206

2178859

2160236

2141613

1804

1819

1836

1853

1870

2948

2957

2965

2974

2982

900

909

917

926

934

−4

−2

−4

−2

−4

−2

−4

−2

Full size (horizontal size: 710 pixels)

241

Small size (horizontal size: 620 pixels)

204

241

2309218

1734

2941

866

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

Table 10 Y scaler programming at NTSC, input frame size: 640 × 480, half anti-ﬂicker ﬁlter

TV LINE

OFFSET FAL LAL

PCL

YINC YSKIP

YOFSO

YOFSE

YIWGTO

YIWGTE

Regular size (horizontal TV size: 640 pixels, offset ±10 pixels)

212

214

216

218

220

−4

−2

241

243

245

247

249

242

244

246

248

250

243

245

247

249

251

244

246

248

250

252

245

247

249

251

253

2219829

2201206

2178859

2160236

2141613

2704

2730

2756

2781

2807

2048

3399

3412

3424

3437

3450

327

340

352

365

378

−4

−2

−4

−2

−4

−2

−4

−2

Full size (horizontal size: 710 pixels)

241

Small size (horizontal size: 620 pixels)

204

241

2309218

2602

2048

3348

276

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

Table 11 Y scaler programming at NTSC, input frame size: 640 × 480, no anti-ﬂicker ﬁlter

TV LINE

OFFSET FAL LAL

PCL

YINC YSKIP

YOFSO

YOFSE

YIWGTO

YIWGTE

Regular size (horizontal TV size: 640 pixels, offset ±10 pixels)

212

214

216

218

220

−4

−2

241

243

245

247

249

242

244

246

248

250

243

245

247

249

251

244

246

248

250

252

245

247

249

251

253

2219829

2201206

2178859

2160236

2141613

3607

3639

3675

3709

3741

4095

3849

3866

3883

3900

3917

3362

3413

3464

3515

3566

−4

−2

−4

−2

−4

−2

−4

−2

Full size (horizontal size: 710 pixels)

241

Small size (horizontal size: 620 pixels)

204

241

2309218

3471

4095

3781

3158

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

Table 12 Y scaler programming at NTSC, input frame size: 800 × 600, full anti-ﬂicker ﬁlter

TV LINE

OFFSET FAL LAL

PCL

YINC YSKIP

YOFSO

YOFSE

YIWGTO

YIWGTE

Regular size (horizontal TV size: 640 pixels, offset ±10 pixels)

212

214

216

218

220

−4

−2

241

243

245

247

249

242

244

246

248

250

243

245

247

249

251

244

246

248

250

252

245

247

249

251

253

3551726

3518354

3484982

3451610

3423006

1443

1457

1470

1484

1497

102

2769

2776

2782

2789

2796

721

728

734

741

748

−4

−2

−4

−2

−4

−2

−4

−2

Full size (horizontal size: 710 pixels)

241 18 259

3122659

1642

1389

2867

2742

819

694

Small size (horizontal size: 620 pixels)

204

241

3689981

106

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

Table 13 Y scaler programming at NTSC, input frame size: 800 × 600, half anti-ﬂicker ﬁlter

TV LINE

OFFSET FAL LAL

PCL

YINC YSKIP

YOFSO

YOFSE

YIWGTO

YIWGTE

Regular size (horizontal TV size: 640 pixels, offset ±10 pixels)

212

214

216

218

220

−4

−2

241

243

245

247

249

242

244

246

248

250

243

245

247

249

251

244

246

248

250

252

245

247

249

251

253

3551726

3518354

3484982

3451610

3423006

2165

2185

2205

2226

2246

2048

102

3129

3140

3150

3160

3170

−4

−2

−4

−2

−4

−2

−4

−2

Full size (horizontal size: 710 pixels)

241 18 259

3122659

2461

2083

2048

3277

3089

205

Small size (horizontal size: 620 pixels)

204

241

3689981

106

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

Table 14 Y scaler programming at NTSC, input frame size: 800 × 600, no anti-ﬂicker ﬁlter

TV LINE

OFFSET FAL LAL

PCL

YINC YSKIP

YOFSO

YOFSE

YIWGTO

YIWGTE

Regular size (horizontal TV size: 640 pixels, offset ±10 pixels)

212

214

216

218

220

−4

−2

241

243

245

247

249

242

244

246

248

250

243

245

247

249

251

244

246

248

250

252

245

247

249

251

253

3551726

3518354

3484982

3451610

3423006

2887

2912

2941

2969

2994

4095

102

103

3490

3504

3517

3531

3544

2282

2323

2364

2405

2446

−4

−2

−4

−2

−4

−2

−4

−2

Full size (horizontal size: 710 pixels)

241 18 259

3122659

3282

2778

4095

3687

3436

2875

2119

Small size (horizontal size: 620 pixels)

204

241

3689981

106

107

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

Table 15 Y scaler programming at PAL, input frame size: 640 × 400, full anti-ﬂicker ﬁlter

TV LINE

OFFSET FAL LAL

PCL

YINC YSKIP

YOFSO

YOFSE

YIWGTO

YIWGTE

Regular size (horizontal TV size: 640 pixels, offset ±10 pixels)

255

257

259

261

263

−4

−2

290

292

294

296

298

291

293

295

297

299

292

294

296

298

300

293

295

297

299

301

294

296

298

300

302

1528590

1516163

1506842

1494414

1481987

2600

2602

2621

2623

2641

2661

2684

3347

3357

3367

3377

3387

1299

1309

1319

1329

1339

−4

−2

−4

−2

−4

−2

−4

−2

Full size (horizontal size: 702 pixels)

288

Small size (horizontal size: 620 pixels)

250

291

1559659

2549

3321

1273

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

Table 16 Y scaler programming at PAL, input frame size: 640 × 400, half anti-ﬂicker ﬁlter

TV LINE

OFFSET FAL LAL

PCL

YINC YSKIP

YOFSO

YOFSE

YIWGTO

YIWGTE

Regular size (horizontal TV size: 640 pixels, offset ±10 pixels)

255

257

259

261

263

−4

−2

290

292

294

296

298

291

293

295

297

299

292

294

296

298

300

293

295

297

299

301

294

296

298

300

302

1528590

1516163

1506842

1494414

1481987

3346

3360

3362

3378

3384

1170

1150

1120

1100

1070

3996

4012

4070

4042

4057

924

940

998

970

985

−4

−2

−4

−2

−4

−2

−4

−2

Full size (horizontal size: 702 pixels)

288

Small size (horizontal size: 620 pixels)

250

291

1559659

3322

1240

3707

1039

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

Table 17 Y scaler programming at PAL, input frame size: 640 × 400, no anti-ﬂicker ﬁlter

TV LINE

OFFSET FAL LAL

PCL

YINC YSKIP

YOFSO

YOFSE

YIWGTO

YIWGTE

Regular size (horizontal TV size: 640 pixels, offset ±10 pixels)

255

257

259

261

263

−4

−2

290

292

294

296

298

291

293

295

297

299

292

294

296

298

301

293

295

297

299

301

294

296

298

300

302

1528590

1516163

1506842

1494414

1481987

4095

4093

4091

4094

4093

4092

2350

2300

2250

2200

2150

4092

4091

869

894

919

944

968

−4

−2

−4

−2

−4

−2

−4

−2

Full size (horizontal size: 702 pixels)

288

Small size (horizontal size: 620 pixels)

250

291

1559659

4087

2470

4089

806

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

Table 18 Y scaler programming at PAL, input frame size: 640 × 480, full anti-ﬂicker ﬁlter

TV LINE

OFFSET FAL LAL

PCL

YINC YSKIP

YOFSO

YOFSE

YIWGTO

YIWGTE

Regular size (horizontal TV size: 640 pixels, offset ±10 pixels)

255

257

259

261

263

−4

−2

290

292

294

296

298

291

293

295

297

299

292

294

296

298

300

293

295

297

299

301

294

296

298

300

302

1833066

1820638

1805104

1792676

1777142

2168

2185

2202

2204

2202

2219

2238

3131

3139

3148

3156

3165

1083

1091

1100

1108

1117

−4

−2

−4

−2

−4

−2

−4

−2

Full size (horizontal size: 702 pixels)

288

Small size (horizontal size: 620 pixels)

250

291

1870348

2125

3110

1062

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

Table 19 Y scaler programming at PAL, input frame size: 640 × 480, half anti-ﬂicker ﬁlter

TV LINE

OFFSET FAL LAL

PCL

YINC YSKIP

YOFSO

YOFSE

YIWGTO

YIWGTE

Regular size (horizontal TV size: 640 pixels, offset ±10 pixels)

255

257

259

261

263

−4

−2

290

292

294

296

298

291

293

295

297

299

292

294

296

298

300

293

295

297

299

301

294

296

298

300

302

1833066

1820638

1805104

1792676

1777142

3254

3277

3305

3328

3354

2048

3673

3686

3698

3711

3724

601

614

626

639

652

−4

−2

−4

−2

−4

−2

−4

−2

Full size (horizontal size: 702 pixels)

288

Small size (horizontal size: 620 pixels)

250

291

1870348

3108

1890

3600

607

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

Table 20 Y scaler programming at PAL, input frame size: 640 × 480, no anti-ﬂicker ﬁlter

TV LINE

OFFSET FAL LAL

PCL

YINC YSKIP

YOFSO

YOFSE

YIWGTO

YIWGTE

Regular size (horizontal TV size: 640 pixels, offset ±10 pixels)

255

257

259

261

263

−4

−2

290

292

294

296

298

291

293

295

297

299

292

294

296

298

300

293

295

297

299

301

294

296

298

300

302

1833066

1820638

1805104

1792676

1777142

4093

4090

4092

4088

4095

3630

3570

3510

3450

3400

4091

4095

228

258

288

318

345

−4

−2

−4

−2

−4

−2

−4

−2

Full size (horizontal size: 702 pixels)

288

Small size (horizontal size: 620 pixels)

250

291

1870348

4088

3780

4090

152

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

Table 21 Y scaler programming at PAL, input frame size: 800 × 600, full anti-ﬂicker ﬁlter

TV LINE

OFFSET FAL LAL

PCL

YINC YSKIP

YOFSO

YOFSE

YIWGTO

YIWGTE

Regular size (horizontal TV size: 640 pixels, offset ±10 pixels)

255

257

259

261

263

−4

−2

290

292

294

296

298

291

293

295

297

299

292

294

296

298

300

293

295

297

299

301

294

296

298

300

302

2930917

2911033

2887172

2863311

2843427

1736

1749

1763

1778

1790

2915

2922

2929

2935

2942

867

874

881

887

894

−4

−2

−4

−2

−4

−2

−4

−2

Full size (horizontal size: 702 pixels)

288 22 310

2596864

1960

1701

3027

2898

979

850

Small size (horizontal size: 620 pixels)

250

291

2990569

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

Table 22 Y scaler programming at PAL, input frame size: 800 × 600, half anti-ﬂicker ﬁlter

TV LINE

OFFSET FAL LAL

PCL

YINC YSKIP

YOFSO

YOFSE

YIWGTO

YIWGTE

Regular size (horizontal TV size: 640 pixels, offset ±10 pixels)

255

257

259

261

263

−4

−2

290

292

294

296

298

291

293

295

297

299

292

294

296

298

300

293

295

297

299

301

294

296

298

300

302

2930917

2911033

2887172

2863311

2843427

2604

2625

2645

2666

2686

2048

3349

3359

3369

3379

3390

277

287

297

307

318

−4

−2

−4

−2

−4

−2

−4

−2

Full size (horizontal size: 702 pixels)

288 22 310

2596864

2940

2553

2048

3517

3323

445

251

Small size (horizontal size: 620 pixels)

250

291

2990569

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

Table 23 Y scaler programming at PAL, input frame size: 800 × 600, no anti-ﬂicker ﬁlter

TV LINE

OFFSET FAL LAL

PCL

YINC YSKIP

YOFSO

YOFSE

YIWGTO

YIWGTE

Regular size (horizontal TV size: 640 pixels, offset ±10 pixels)

255

257

259

261

263

−4

−2

290

292

294

296

298

291

293

295

297

299

292

294

296

298

300

293

295

297

299

301

294

296

298

300

302

2930917

2911033

2887172

2863311

2843427

3473

3500

3527

3555

3582

4095

100

3783

3796

3810

3823

3837

3161

3202

3242

3284

3324

−4

−2

−4

−2

−4

−2

−4

−2

Full size (horizontal size: 702 pixels)

288 22 310

2596864

3923

3405

4095

4007

3748

3836

3059

Small size (horizontal size: 620 pixels)

250

291

2990569

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

Table 24 “ITU-R BT.601” signal component levels

Table 26 Pin assignment for input format 1

5 + 5 + 5-BIT 4 : 4 : 4 NON-INTERLACED RGB

SIGNALS⁽¹⁾

COLOUR

C_B

235 128 128 235 235 235

210 16 146 235 235 16

170 166 235 235

145 54

C_R

FALLING

CLOCK EDGE

RISING

CLOCK EDGE

White

Yellow

Cyan

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

Green

Magenta

Red

235

106 202 222 235

240 235

Blue

240 110

128 128

235

Black

Note

1. Transformation:

a) R = Y + 1.3707 × (C_R− 128)

Table 27 Pin assignment for input format 2

5 + 6 + 5-BIT 4 : 4 : 4 NON-INTERLACED RGB

b) G = Y − 0.3365 × (C_B− 128) − 0.6982 × (C_R− 128)

c) B = Y + 1.7324 × (C_B− 128).

FALLING

CLOCK EDGE

RISING

CLOCK EDGE

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

Table 25 Pin assignment for input format 0

8 + 8 + 8-BIT 4 : 4 : 4 NON-INTERLACED

RGB/C_B-Y-C_R

FALLING

CLOCK EDGE

RISING

CLOCK EDGE

PD11

PD10

PD9

PD8

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

G3/Y3

G2/Y2

R7/C_R7

R6/C_R6

R5/C_R5

R4/C_R4

R3/C_R3

R2/C_R2

R1/C_R1

R0/C_R0

G7/Y7

G1/Y1

G0/Y0

Table 28 Pin assignment for input format 3

8 + 8 + 8-BIT 4 : 2 : 2 NON-INTERLACED C_B-Y-C_R

FALLING RISING FALLING RISING

B7/C_B7

B6/C_B6

B5/C_B5

B4/C_B4

B3/C_B3

B2/C_B2

B1/C_B1

B0/C_B0

CLOCK

EDGE

CLOCK

EDGE

CLOCK

EDGE

n + 1

CLOCK

EDGE

n + 1

G6/Y6

PD7

C_B7(0)

C_B6(0)

C_B5(0)

C_B4(0)

C_B3(0)

C_B2(0)

C_B1(0)

C_B0(0)

Y7(0)

Y6(0)

Y5(0)

Y4(0)

Y3(0)

Y2(0)

Y1(0)

Y0(0)

C_R7(0)

C_R6(0)

C_R5(0)

C_R4(0)

C_R3(0)

C_R2(0)

C_R1(0)

C_R0(0)

Y7(1)

Y6(1)

Y5(1)

Y4(1)

Y3(1)

Y2(1)

Y1(1)

Y0(1)

G5/Y5

PD6

PD5

PD4

PD3

PD2

PD1

PD0

G4/Y4

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

Table 29 Pin assignment for input format 4

Table 31 Pin assignment for input format 6

8 + 8 + 8-BIT 4 : 2 : 2 INTERLACED C_B-Y-C_R

(ITU-R BT.656, 27 MHz CLOCK)

8 + 8 + 8-BIT 4 : 4 : 4 NON-INTERLACED

RGB/C_B-Y-C_R

RISING

CLOCK

EDGE

RISING

CLOCK

EDGE

n + 1

RISING

CLOCK

EDGE

n + 2

RISING

CLOCK

EDGE

n + 3

FALLING

CLOCK EDGE

RISING

CLOCK EDGE

PD11

PD10

PD9

PD8

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

G4/Y4

G3/Y3

R7/C_R7

R6/C_R6

R5/C_R5

R4/C_R4

R3/C_R3

G7/Y7

PD7

C_B7(0)

C_B6(0)

C_B5(0)

C_B4(0)

C_B3(0)

C_B2(0)

C_B1(0)

C_B0(0)

Y7(0)

Y6(0)

Y5(0)

Y4(0)

Y3(0)

Y2(0)

Y1(0)

Y0(0)

C_R7(0)

C_R6(0)

C_R5(0)

C_R4(0)

C_R3(0)

C_R2(0)

C_R1(0)

C_R0(0)

Y7(1)

Y6(1)

Y5(1)

Y4(1)

Y3(1)

Y2(1)

Y1(1)

Y0(1)

G2/Y2

PD6

PD5

PD4

PD3

PD2

PD1

PD0

B7/C_B7

B6/C_B6

B5/C_B5

B4/C_B4

B3/C_B3

G0/Y0

G6/Y6

G5/Y5

R2/C_R2

R1/C_R1

R0/C_R0

G1/Y1

B2/C_B2

B1/C_B1

B0/C_B0

Table 30 Pin assignment for input format 5; note 1

8-BIT NON-INTERLACED INDEX COLOUR

FALLING

CLOCK EDGE

RISING

CLOCK EDGE

PD11

PD10

PD9

PD8

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

INDEX7

INDEX6

INDEX5

INDEX4

INDEX3

INDEX2

INDEX1

INDEX0

Note

1. X = don’t care.

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

FUNCTIONAL DESCRIPTION OF DIGITAL VIDEO DECODER PART

Decoder

9.1

9.1.1

ANALOG INPUT PROCESSING

The SAA7108E; SAA7109E offers six analog signal inputs, two analog main channels with source switch, clamp circuit,

analog amplifier, anti-alias filter and video 9-bit CMOS ADC; see Fig.14.

9.1.2

ANALOG CONTROL CIRCUITS

The anti-alias filters are adapted to the line-locked clock frequency via a filter control circuit. The characteristics are

illustrated in Fig.11. During the vertical blanking period, gain and clamping control is frozen.

MGD138

(dB)

−6

−12

−18

−24

−30

−36

−42

f (MHz)

Fig.11 Anti-alias filter.

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

9.1.2.1

Clamping

The AGC (automatic gain control for luminance) is used to

amplify a CVBS or Y signal to the required signal

amplitude, which is matched to the ADCs input voltage

range. The AGC active time is the sync bottom of the video

signal.

The clamping control circuit controls the correct clamping

of the analog input signals. A coupling capacitor is used to

store and filter the clamping voltage. An internal digital

clamp comparator generates the information with respect

to clamp-up or clamp-down. The clamping levels for the

two ADC channels are fixed for luminance (60) and

chrominance (128). Clamping time in normal use is set

with the HCL pulse at the back porch of the video signal.

Signal (white) peak control limits the gain at signal

overshoots. The influence of supply voltage variation

within the specified range is automatically eliminated by

clamping and automatic gain control. The flow charts show

more details of the AGC; see Figs 15 and 16.

9.1.2.2

Gain control

The gain control circuit receives (via the I²C-bus) the static

gain levels for the two analog amplifiers, or controls one of

these amplifiers automatically via a built-in Automatic Gain

Control (AGC) as part of the Analog Input Control (AICO).

TV line

analog line blanking

controlled

ADC input level

analog input level

255

maximum

+3 dB

GAIN

HSY

CLAMP

HCL

0 dB

range 9 dB

0 dB

(1 V (p-p) 18/56 Ω)

−6 dB

minimum

MHB325

MGL065

Fig.12 Analog line with clamp (HCL) and gain

range (HSY).

Fig.13 Automatic gain range.

2004 Mar 16

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TEST

SELECTOR

AND

M10

AOUT

BUFFER

AI24

AI23

[

]

AOSL 1:0

SOURCE

SWITCH

AI2D

ANALOG

AMPLIFIER

DAC9

CLAMP

CIRCUIT

ANTI-ALIAS

FILTER

BYPASS

SWITCH

ADC2

ADC1

AI22

AI21

P10

[

]

FUSE 1:0

P11

P12

P13

AI12

AI1D

AI11

ANALOG

AMPLIFIER

DAC9

CLAMP

CIRCUIT

ANTI-ALIAS

FILTER

BYPASS

SWITCH

SOURCE

SWITCH

[

]

FUSE 1:0

VERTICAL

BLANKING

CONTROL

MODE

CONTROL

CLAMP

CONTROL

GAIN

CONTROL

ANTI-ALIAS

CONTROL

HCL

VBLNK

SVREF

GLIMB HSY

GLIMT

WIPA

VBSL

HOLDG

GAFIX

WPOFF

MODE3

MODE2

MODE1

MODE0

[

]

SLTCA

GUDL 1:0

[

GAI 28:20

ANALOG CONTROL

[

GAI 18:10

HLNRS

UPTCV

CROSS MULTIPLEXER

MHB892

AD2BYP AD1BYP

CVBS/LUM CVBS/CHR

Fig.14 Analog input processing using the SAA7108E; SAA7109E as differential front-end with 9-bit ADC.

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

ANALOG INPUT

AMPLIFIER

gain

DAC

ANTI-ALIAS FILTER

ADC

LUMA/CHROMA DECODER

NO ACTION

VBLK

HOLDG

HSY

254

X = 1

X = 0

248

+/− 0

+1/L

+1/F

+1/LLC2 −1/LLC2

−1/LLC2

STOP

GAIN ACCUMULATOR (18 BITS)

[

]

ACTUAL GAIN VALUE 9-BIT (AGV) −3/+6 dB

HSY

AGV

UPDATE

FGV

X = system variable.

GAIN VALUE 9-BIT

Y = (IAGV − FGVI) > GUDL.

VBLK = vertical blanking pulse.

HSY = horizontal sync pulse.

AGV = actual gain value.

MHB531

FGV = frozen gain value.

Fig.15 Gain flow chart.

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

ANALOG INPUT

ADC

NO BLANKING ACTIVE

VBLK

<- CLAMP

GAIN ->

HCL

HSY

CLL

SBOT

WIPE

slow + GAIN

NO CLAMP

+ CLAMP

− CLAMP

fast − GAIN

+ GAIN

− GAIN

MGC647

WIPE = white peak level (254).

SBOT = sync bottom level (1).

CLL = clamp level [60 Y (128 C)].

HSY = horizontal sync pulse.

HCL = horizontal clamp pulse.

Fig.16 Clamp and gain flow.

2004 Mar 16

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CVBS-IN

or Y-IN

DELAY

COMPENSATION

LUMINANCE-PEAKING

SUBTRACTOR

LDEL

Y/CVBS

YCOMB

LOW-PASS,

CHR

Y-DELAY ADJUSTMENT

[

]

DBRI 7:0

[

DCON 7:0

QUADRATURE

MODULATOR

INTERPOLATION

LOW-PASS 3

[

DSAT 7:0

[

]

RAWG 7:0

[

]

LUFI 3:0

SET_RAW

SET_VBI

[

RAWO 7:0

[

CSTD 2:0

COLO

[

]

YDEL 2:0

LUBW UV

CVBS-IN

or CHR-IN

QUADRATURE

DEMODULATOR

LOW-PASS 1

DOWNSAMPLING

ADAPTIVE

COMB FILTER

BRIGHTNESS

CONTRAST

SATURATION

CONTROL

LOW-PASS 2

CHBW

Y-OUT/

CVBS-OUT

UV-OUT

CCOMB

YCOMB

LDEL

SET_RAW

SET_VBI

[

]

LCBW 2:0

SUBCARRIER

GENERATION 2

RAW DATA

GAIN AND

OFFSET

HREF-OUT

BYPS

CONTROL

SECAM

PROCESSING

LDEL

YCOMB

CHROMINANCE

INCREMENT

DELAY

UV SET_RAW

SET_VBI

CHROMINANCE

INCREMENT

DTO-RESET

PHASE

DEMODULATOR

CHROMA

GAIN

CONTROL

AMPLITUDE

DETECTOR

SUBCARRIER

GENERATION 1

SUBCARRIER

INCREMENT

GENERATION

AND

PAL DELAY LINE

BURST GATE

ACCUMULATOR

UV-

ADJUSTMENT

SECAM

RECOMBINATION

LOOP FILTER

DIVIDER

HUEC

CDTO INCS

DCVF

SET_RAW

SET_VBI

SECS

CODE

FCTC

ACGC

[

]

CSTD 2:0

[

]

CGAIN 6:0

[

]

IDEL 3:0

MHB532

RTCO

/2 switch signal

Fig.17 Chrominance and luminance processing.

ahdnbok,uflapegwidt

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

9.1.3.1

Chrominance path

• Baseband ‘bell’ filters to reconstruct the amplitude and

phase equalized 0° and 90° FM signals

The 9-bit CVBS or chrominance input signal is fed to the

input of a quadrature demodulator, where it is multiplied by

two time-multiplexed subcarrier signals from the subcarrier

generation block 1 (0 and 90° phase relationship to the

demodulator axis). The frequency is dependent on the

chosen colour standard.

• Phase demodulator and differentiator

(FM demodulation)

• De-emphasis filter to compensate the pre-emphasized

input signal, including frequency offset compensation

(DB or DR white carrier values are subtracted from the

signal, controlled by the SECAM switch signal).

The time-multiplexed output signals of the multipliers are

low-pass filtered (low-pass 1). Eight characteristics are

programmable via LCBW3 to LCBW0 to achieve the

desired bandwidth for the colour difference signals (PAL,

NTSC) or the 0° and 90° FM signals (SECAM).

The succeeding chrominance gain control block amplifies

or attenuates the C_B-C_Rsignal according to the required

ITU 601/656 levels. It is controlled by the output signal

from the amplitude detection circuit within the burst

processing block.

The chrominance low-pass 1 characteristic also influences

the grade of cross-luminance reduction during horizontal

colour transients (large chrominance bandwidth means

strong suppression of cross-luminance). If the Y comb

filter is disabled when YCOMB = 0 the filter directly

influences the width of the chrominance notch within the

luminance path (large chrominance bandwidth means

wide chrominance notch resulting to lower luminance

bandwidth).

The burst processing block provides the feedback loop of

the chrominance PLL and contains the following:

• Burst gate accumulator

• Colour identification and killer

• Comparison nominal/actual burst amplitude (PAL/NTSC

standards only)

• Loop filter chrominance gain control (PAL/NTSC

standards only)

The low-pass filtered signals are fed to the adaptive comb

filter block. The chrominance components are separated

from the luminance via a two-line vertical stage (four lines

for PAL standards) and a decision logic circuit between the

filtered and the non-filtered output signals: this block is

bypassed for SECAM signals. The comb filter logic can be

enabled independently for the succeeding luminance and

chrominance processing by YCOMB (subaddress 09H,

bit 6) and/or CCOMB (subaddress 0EH, bit 0). It is always

bypassed during VBI or raw data lines, programmable by

the LCRn registers (subaddresses 41H to 57H);

see Section 9.2.

• Loop filter chrominance PLL (only active for PAL/NTSC

standards)

• PAL/SECAM sequence detection, H/2-switch

generation.

The increment generation circuit produces the Discrete

Time Oscillator (DTO) increment for both subcarrier

generation blocks. It contains a division by the increment

of the line-locked clock generator to create a stable

phase-locked sine signal under all conditions (e.g. for

non-standard signals).

The PAL delay line block eliminates crosstalk between the

chrominance channels in accordance with the PAL

standard requirements. For NTSC colour standards, the

delay line can be used as an additional vertical filter.

If desired, it can be switched off by DCVF = 1. It is always

disabled during VBI or raw data lines programmable by the

LCRn registers (subaddresses 41H to 57H), see

Section 9.2. The embedded line delay is also used for

SECAM recombination (cross-over switches).

The separated C_B-C_Rcomponents are further processed

by a second filter stage (low-pass 2) to modify the

chrominance bandwidth without influencing the luminance

path. It’s characteristic is controlled by CHBW

(subaddress 10H, bit 3). For the complete transfer

characteristic of low-pass filters 1 and 2 see

Figs 18 and 19.

The SECAM processing (bypassed for QAM standards)

contains the following blocks:

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

MHB533

(dB)

−3

−6

−9

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

−45

−48

−51

−54

−57

−60

(1)

(2)

(3)

(4)

(1) LCBW[2:0] = 000.

(2) LCBW[2:0] = 010.

(3) LCBW[2:0] = 100.

(4) LCBW[2:0] = 110.

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0

f (MHz)

(dB)

−3

−6

−9

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

−45

−48

−51

−54

−57

−60

(5)

(6)

(7)

(8)

(5) LCBW[2:0] = 001.

(6) LCBW[2:0] = 011.

(7) LCBW[2:0] = 101.

(8) LCBW[2:0] = 111.

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0

f (MHz)

Fig.18 Transfer characteristics of the chrominance low-pass at CHBW = 0.

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

MHB534

(dB)

−3

−6

−9

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

−45

−48

−51

−54

−57

−60

(1)

(2)

(3)

(4)

(1) LCBW[2:0] = 000.

(2) LCBW[2:0] = 010.

(3) LCBW[2:0] = 100.

(4) LCBW[2:0] = 110.

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0

f (MHz)

(dB)

−3

−6

−9

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

−45

−48

−51

−54

−57

−60

(5)

(6)

(7)

(8)

(5) LCBW[2:0] = 001.

(6) LCBW[2:0] = 011.

(7) LCBW[2:0] = 101.

(8) LCBW[2:0] = 111.

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0

f (MHz)

Fig.19 Transfer characteristics of the chrominance low-pass at CHBW = 1.

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

9.1.3.2

Luminance path

The interpolated C_B-C_Rsamples are multiplied by two

time-multiplexed subcarrier signals from the subcarrier

generation block 2. This second DTO is locked to the first

subcarrier generator by an increment delay circuit

matched to the processing delay, which is different for

PAL and NTSC standards according to the chosen comb

filter algorithm. The two modulated signals are finally

added to create the re-modulated chrominance signal.

The rejection of the chrominance components within the

9-bit CVBS or Y input signal is done by subtracting the

re-modulated chrominance signal from the CVBS input.

The comb filtered C_B-C_Rcomponents are interpolated

(upsampled) by the low-pass 3 block. It’s characteristic is

controlled by LUBW (subaddress 09H, bit 4) to modify the

width of the chrominance ‘notch’ without influencing the

chrominance path. The programmable frequency

characteristics available, in conjunction with the

LCBW2 to LCBW0 settings, can be seen in Figs 20 to 23.

It should be noted that these frequency curves are only

valid for Y comb disabled filter mode (YCOMB = 0).

In comb filter mode the frequency response is flat. The

centre frequency of the notch is automatically adapted to

the chosen colour standard.

The frequency characteristic of the separated luminance

signal can be further modified by the succeeding

luminance filter block. It can be configured as peaking

(resolution enhancement) or low-pass block by

LUFI3 to LUFI0 (subaddress 09H, bits 3 to 0). The 16

resulting frequency characteristics can be seen in Fig.24.

The LUFI3 to LUFI0 settings can be used as a user

programmable sharpness control.

The luminance filter block also contains the adjustable

Y delay part; programmable by YDEL2 to YDEL0

(subaddress 11H, bits 2 to 0).

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

MHB535

(dB)

−3

−6

−9

(1)

(2)

(3)

(4)

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

−45

−48

−51

−54

−57

−60

(1) LCBW[2:0] = 000.

(2) LCBW[2:0] = 010.

(3) LCBW[2:0] = 100.

(4) LCBW[2:0] = 110.

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0

f (MHz)

(dB)

−3

−6

−9

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

−45

−48

−51

−54

−57

−60

(5)

(6)

(7)

(8)

(5) LCBW[2:0] = 001.

(6) LCBW[2:0] = 011.

(7) LCBW[2:0] = 101.

(8) LCBW[2:0] = 111.

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0

f (MHz)

Fig.20 Transfer characteristics of the luminance notch filter in 3.58 MHz mode (Y-comb filter disabled) at

LUBW = 0.

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

MHB536

(dB)

−3

−6

−9

(1)

(2)

(3)

(4)

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

−45

−48

−51

−54

−57

−60

(1) LCBW[2:0] = 000

(2) LCBW[2:0] = 010

(3) LCBW[2:0] = 100

(4) LCBW[2:0] = 110

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0

f (MHz)

(dB)

−3

−6

−9

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

−45

−48

−51

−54

−57

−60

(5)

(6)

(7)

(8)

(5) LCBW[2:0] = 001

(6) LCBW[2:0] = 011

(7) LCBW[2:0] = 101

(8) LCBW[2:0] = 111

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0

f (MHz)

Fig.21 Transfer characteristics of the luminance notch filter in 3.58 MHz mode (Y-comb filter disabled) at

LUBW = 1.

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

MHB537

(dB)

−3

−6

−9

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

−45

−48

−51

−54

−57

−60

(1)

(2)

(3)

(4)

(1) LCBW[2:0] = 000.

(2) LCBW[2:0] = 010.

(3) LCBW[2:0] = 100.

(4) LCBW[2:0] = 110.

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0

f (MHz)

(dB)

−3

−6

−9

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

−45

−48

−51

−54

−57

−60

(5)

(6)

(7)

(8)

(5) LCBW[2:0] = 001.

(6) LCBW[2:0] = 011.

(7) LCBW[2:0] = 101.

(8) LCBW[2:0] = 111.

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0

f (MHz)

Fig.22 Transfer characteristics of the luminance notch filter in 4.43 MHz mode (Y-comb filter disabled) at

LUBW = 0.

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

MHB538

(dB)

−3

−6

−9

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

−45

−48

−51

−54

−57

−60

(1)

(2)

(3)

(4)

(1) LCBW[2:0] = 000.

(2) LCBW[2:0] = 010.

(3) LCBW[2:0] = 100.

(4) LCBW[2:0] = 110.

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0

f (MHz)

(dB)

−3

−6

−9

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

−45

−48

−51

−54

−57

−60

(5)

(6)

(7)

(8)

(5) LCBW[2:0] = 001.

(6) LCBW[2:0] = 011.

(7) LCBW[2:0] = 101.

(8) LCBW[2:0] = 111.

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0

f (MHz)

Fig.23 Transfer characteristics of the luminance notch filter in 4.43 MHz mode (Y-comb filter disabled) at

LUBW = 1.

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

MHB539

(dB)

(1)

(2)

(3)

(4)

(5)

(6)

(7)

(8)

(1) LUFI[3:0] = 0001.

(2) LUFI[3:0] = 0010.

(3) LUFI[3:0] = 0011.

(4) LUFI[3:0] = 0100.

(5) LUFI[3:0] = 0101.

(6) LUFI[3:0] = 0110.

(7) LUFI[3:0] = 0111.

(8) LUFI[3:0] = 0000.

−1

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

f (MHz)

(dB)

−3

−6

(9)

(10)

(11)

(12)

(13)

(14)

(15)

(16)

−9

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

(9) LUFI[3:0] = 1000.

(10) LUFI[3:0] = 1001.

(11) LUFI[3:0] = 1010.

(12) LUFI[3:0] = 1011.

(13) LUFI[3:0] = 1100.

(14) LUFI[3:0] = 1101.

(15) LUFI[3:0] = 1110.

(16) LUFI[3:0] = 1111.

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

f (MHz)

Fig.24 Transfer characteristics of the luminance peaking/low-pass filter (sharpness).

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

9.1.3.3

Brightness Contrast Saturation (BCS) control and decoder output levels

The resulting Y (CVBS) and C_B-C_Rsignals are fed to the BCS block, which contains the following functions:

• Chrominance saturation control by DSAT7 to DSAT0

• Luminance contrast and brightness control by DCON7 to DCON0 and DBRI7 to DBRI0

• Raw data (CVBS) gain and offset adjustment by RAWG7 to RAWG0 and RAWO7 to RAWO0

• Limiting Y-C_B-C_Ror CVBS to the values 1 (minimum) and 254 (maximum) to fulfil “ITU Recommendation 601/656”.

+255

+240

+255

+240

handbook, full pagewidth

blue 100%

blue 75%

red 100%

red 75%

white

+235

+212

colourless

LUMINANCE 100%

+128

-COMPONENT

C -COMPONENT

yellow 75%

cyan 75%

+44

+16

+44

+16

yellow 100%

cyan 100%

black

+16

MHB730

a. Y output range.

b. C_Boutput range.

c. C_Routput range.

“ITU Recommendation 601/656” digital levels with default BCS (decoder) settings DCON[7:0] = 44H, DBRI[7:0] = 80H and DSAT[7:0] = 40H.

Equations for modification to the Y-C_B-C_Rlevels via BCS control I²C-bus bytes DBRI, DCON and DSAT.

DCON

Luminance:

Y_OUT= Int

× (Y – 128) + DBRI

-----------------

DSAT

Chrominance:(C_RC_B)_OUT= Int

× (C , C_B– 128) + 128

---------------

It should be noted that the resulting levels are limited to 1 to 254 in accordance with “ITU Recommendation 601/656”.

Fig.25 Y-C_B-C_Rrange for scaler input and X port output.

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

+255

+209

+255

+199

white

LUMINANCE

black

black shoulder

+71

+60

black shoulder = black

+60

SYNC

sync bottom

MGD700

a. Sources containing 7.5 IRE black level offset (e.g. NTSC M).

b. Sources not containing black level offset.

CVBS levels with default settings RAWG[7:0] = 64 and RAWO[7:0] = 128.

Equation for modification of the raw data levels via bytes RAWG and RAWO:

RAWG

CVBS_OUT= Int

× (CVBS_nom– 128) + RAWO

------------------

It should be noted that the resulting levels are limited to 1 to 254 in accordance with “ITU Recommendation 601/656”.

Fig.26 CVBS (raw data) range for scaler input, data slicer and X port output.

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

9.1.4

SYNCHRONIZATION

The internal signal LFCO is a digital-to-analog converted

signal provided by the horizontal PLL. It is a multiple of the

line frequency:

The prefiltered luminance signal is fed to the

synchronization stage. Its bandwidth is further reduced to

1 MHz by a low-pass filter. The sync pulses are sliced and

fed to the phase detectors where they are compared with

the sub-divided clock frequency. The resulting output

signal is applied to the loop filter to accumulate all phase

deviations. Internal signals (e.g. HCL and HSY) are

generated in accordance with analog front-end

requirements. The loop filter signal drives an oscillator to

generate the line frequency control signal (LFCO);

see Fig.27.

6.75 MHz = 429 × f_H(50 Hz), or

6.75 MHz = 432 × f_H(60 Hz).

The LFCO signal is multiplied Internally by a factor of

2 and 4 in the PLL circuit (including phase detector, loop

filtering, VCO and frequency divider) to obtain the output

clock signals. The rectangular output clocks have a 50%

duty cycle.

Table 32 Decoder clock frequencies

The detection of ‘pseudo syncs’ as part of the macrovision

copy protection standard is also done within the

synchronization circuit.

CLOCK

FREQUENCY (MHz)

XTAL

LLC

24.576 or 32.110

The result is reported as flag COPRO within the decoder

status byte at subaddress 1FH.

LLC2

13.5

6.75

3.375

LLC4 (internal)

LLC8 (virtual)

9.1.5

CLOCK GENERATION CIRCUIT

The internal CGC generates all clock signals required for

the video input processor.

ZERO

CROSS

DETECTION

BAND PASS

FC = LLC/4

PHASE

DETECTION

LOOP

FILTER

LFCO

OSCILLATOR

LLC

DIVIDER

1/2

DIVIDER

1/2

LLC2

MHB330

Fig.27 Block diagram of the clock generation circuit.

9.1.6

POWER-ON RESET AND CE INPUT

A missing clock, insufficient digital or analog V_DDAdsupply voltages (below 2.7 V) will start the reset sequence; all outputs

are forced to 3-state (see Fig.28). The indicator output RES is LOW for approximately 128 LLC after the internal reset

and can be applied to reset other circuits of the digital TV system.

It is possible to force a reset by pulling the Chip Enable (CE) to ground. After the rising edge of CE and sufficient power

supply voltage, the outputs LLC, LLC2 and SDAd return from 3-state to active, while the other signals have to be

activated via programming.

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

POC V

DDA

DDD

ANALOG

DIGITAL

CLOCK

PLL

LLC

POC

LOGIC

POC

DELAY

RES

RESINT

CLK0

XTALO

LLCINT

RESINT

LLC

RES

(internal

reset)

20 to 200 µs

PLL-delay

896 LCC

digital delay

MHB331

some ms

128 LCC

1 ms

POC = Power-on Control.

CE = chip enable input.

XTALO = crystal oscillator output.

LLCINT = internal system clock.

RESINT = internal reset.

LLC = line-locked clock output.

RES = reset output.

Fig.28 Power-on control circuit.

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

9.2

Decoder output formatter

For each LCR value, from 2 to 23, the data type can be

programmed individually. LCR2 to LCR23 refer to line

numbers. The selection in LCR24 values is valid for the

rest of the corresponding field. The upper nibble contains

the value for field 1 (odd), the lower nibble for field 2

(even). The relationship between LCR values and line

numbers can be adjusted via VOFF8 to VOFF0, located in

subaddresses 5BH (bit 4) and 5AH (bits 7 to 0) and FOFF

subaddress 5BH (bit 7). The recommended values are

VOFF[8:0] = 03H for 50 Hz sources (with FOFF = 0) and

VOFF[8:0] = 06H for 60 Hz sources (with FOFF = 1), to

accommodate line number conventions as used for PAL,

SECAM and NTSC standards; see Tables 34 to 37.

The output interface block of the decoder part contains the

ITU 656 formatter for the expansion port data output

XPD7 to XPD0 (see Section 10.4.1) and the control circuit

for the signals needed for the internal paths to the scaler

and data slicer part. It also controls the selection of the

reference signals for the RT port (RTCO, RTS0 and

RTS1) and the expansion port (XRH, XRV and XDQ).

The generation of the decoder data type control signals

SET_RAW and SET VBI is also done within this block.

These signals are decoded from the requested data type

for the scaler input and/or the data slicer, selectable by the

control registers LCR2 to LCR24 (see Section 18.2.4.2).

Table 33 Data formats at decoder output

DATA TYPE NUMBER

DATA TYPE

teletext EuroWST, CCST

European Closed Caption

DECODER OUTPUT DATA FORMAT

raw

Video Programming Service (VPS)

Wide screen signalling bits

US teletext (WST)

raw

US Closed Caption (line 21)

video component signal, VBI region

CVBS data

raw

Y-C_B-C_R4 : 2 : 2

raw

teletext

raw

VITC/EBU time codes (Europe)

VITC/SMPTE time codes (USA)

reserved

raw

US NABTS

raw

MOJI (Japanese)

Japanese format switch (L20/22)

video component signal, active video region

raw

Y-C_B-C_R4 : 2 : 2

2004 Mar 16

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Table 34 Relationship of LCR to line numbers in 525 lines/60 Hz systems (part 1)

Vertical line offset, VOFF[8:0] = 06H (subaddresses 5BH[4] and 5AH[7:0]); horizontal pixel offset, HOFF[10:0] = 347H (subaddresses 5BH[2:0] and

59H[7:0]); FOFF = 1 (subaddress 5BH[7])

Line number

(1st ﬁeld)

521

522

523

active video

261

524

525

269

equalization pulses

serration pulses

equalization pulses

Line number

(2nd ﬁeld)

259

260

262

263

264

265

equalization pulses

266

267

268

270

271

272

active video

serration pulses

equalization pulses

LCR

Table 35 Relationship of LCR to line numbers in 525 lines/60 Hz systems (part 2)

Vertical line offset, VOFF[8:0] = 06H (subaddresses 5BH[4] and 5AH[7:0]); horizontal pixel offset, HOFF[10:0] = 347H (subaddresses 5BH[2:0] and

59H[7:0]); FOFF = 1 (subaddress 5BH[7])

Line number

(1st ﬁeld)

273

274

275

276

277

nominal VBI lines F1

278 279

nominal VBI lines F2

15 16

280

281

282

283

284

285

active video

286 287

Line number

(2nd ﬁeld)

288

active video

LCR

Table 36 Relationship of LCR to line numbers in 625 lines/50 Hz systems (part 1)

Vertical line offset, VOFF[8:0] = 03H (subaddresses 5BH[4] and 5AH[7:0]); horizontal pixel offset, HOFF[10:0] = 347H (subaddresses 5BH[2:0] and

59H[7:0]); FOFF = 0 (subaddress 5BH[7])

Line number

(1st ﬁeld)

621

622

active video

310

623

624

equalization pulses

312 313

625

serration pulses

315

equalization pulses

317 318

Line number

(2nd ﬁeld)

309

311

314

316

active video

equalization pulses

serration pulses

equalization pulses

LCR

Table 37 Relationship of LCR to line numbers in 625 lines/50 Hz systems (part 2)

Vertical line offset, VOFF[8:0] = 03H (subaddresses 5BH[4] and 5AH[7:0]); horizontal pixel offset, HOFF[10:0] = 347H (subaddresses 5BH[2:0] and

59H[7:0]); FOFF = 0 (subaddress 5BH[7])

Linenumber

(1st ﬁeld)

nominal VBI lines F1

active video

Linenumber 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338

(2nd ﬁeld)

nominal VBI lines F2

13 14 15

active video

23 24

LCR

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

625

312

624

311

622

309

623

310

...

ITU counting

single field counting

CVBS

HREF

F_ITU656

(1)

V123

[

]

VSTO 8:0 = 134H

VGATE

FID

[

]

VSTA 8:0 = 15H

(a) 1st field

312

313

314

315

316

317

318

319

335

336

ITU counting

single field counting

311

309

310

...

CVBS

HREF

F_ITU656

(1)

V123

[

]

VSTO 8:0 = 134H

VGATE

FID

(b) 2nd field

[

]

VSTA 8:0 = 15H

MHB540

(1) The inactive going edge of the V123 signal indicates whether the field is odd or even. If HREF is active during

the falling edge of V123, the field is ODD (field 1). If HREF is inactive during the falling edge of V123, the field

is EVEN. The specific position of the slope is dependent on the internal processing delay and may change a

few clock cycles from version to version.

The control signals listed above are available on pins RTS0, RTS1, XRH and XRV according to the following table:

NAME

HREF

RTS0 (PIN K13) RTS1 (PIN L10) XRH (PIN N2) XRV (PIN L5)

−

F_ITU656

V123

VGATE

FID

For further information see programming section, Tables 167, 168 and 169.

Fig.29 Vertical timing diagram for 50 Hz/625 line systems.

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

525

262

...

ITU counting

single field counting

CVBS

HREF

F_ITU656

(1)

V123

[

]

VSTO 8:0 = 101H

VGATE

FID

[

]

VSTA 8:0 = 011H

(a) 1st field

265

266

267

268

269

270

271

272

284

285

ITU counting

single field counting

264

262

263

...

CVBS

HREF

F_ITU656

(1)

V123

[

]

VSTO 8:0 = 101H

VGATE

FID

(b) 2nd field

[

]

VSTA 8:0 = 011H

MHB541

(1) The inactive going edge of the V123 signal indicates whether the field is odd or even. If HREF is active during

the falling edge of V123, the field is ODD (field 1). If HREF is inactive during the falling edge of V123, the field

is EVEN. The specific position of the slope is dependent on the internal processing delay and may change a

few clock cycles from version to version.

The control signals listed above are available on pins RTS0, RTS1, XRH and XRV according to the following table:

NAME

HREF

RTS0 (PIN K13

RTS1 (PIN L10) XRH (PIN N2) XRV (PIN L5)

−

F_ITU656

V123

VGATE

FID

For further information see programming section, Tables 167, 168 and 169.

Fig.30 Vertical timing diagram for 60 Hz/525 line systems.

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

burst

CVBS input

processing delay ADC to expansion port:

140 × 1/LLC

expansion port

data output

sync clipped

HREF (50 Hz)

12 × 2/LLC

144 × 2/LLC

720 × 2/LLC

5 × 2/LLC

CREF

CREF2

2 × 2/LLC

−107

HS (50 Hz)

programming range

(step size: 8/LLC)

108

HREF (60 Hz)

16 × 2/LLC

138 × 2/LLC

720 × 2/LLC

1 × 2/LLC

CREF

CREF2

HS (60 Hz)

2 × 2/LLC

programming range

(step size: 8/LLC)

107

−106

MHB542

The signals HREF, HS, CREF2 and CREF are available on pins RTS0 and/or RTS1 (see Section 18.2.2.19 Tables 167 and 168);

their polarity can be inverted via RTP0 and/or RTP1.

The signals HREF and HS are available on pin XRH (see Section 18.2.2.20 Table 169).

Fig.31 Horizontal timing diagram (50/60 Hz).

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

9.3

Scaler

The overall H and V zooming (HV_zoom) is restricted by

the input/output data rate relationships. With a safety

margin of 2% for running in and running out, the maximum

HV_zoom is equal to:

The High Performance video Scaler (HPS) is based on the

system as implemented in the SAA7140, but enhanced in

some aspects. Vertical upsampling is supported and the

processing pipeline buffer capacity is enhanced, to allow

more flexible video stream timing at the image port,

discontinuous transfers and handshake. The internal data

flow from block to block is discontinuous dynamically, due

to the scaling process.

T_input_field – T_v_blanking

in_pixel × in_lines × out_cycle_per_pix × T_out_clk

0.98 ×

-------------------------------------------------------------------------------------------------------------------------------------

For example:

1. Input from decoder: 50 Hz, 720 pixel, 288 lines, 16-bit

data at 13.5 MHz data rate, 1 cycle per pixel; output:

8-bit data at 27 MHz, 2 cycles per pixel; the maximum

HV_zoom is equal to:

The flow is controlled by internal data valid and data

request flags (internal handshake signalling) between the

sub-blocks. Therefore the entire scaler acts as a pipeline

buffer. Depending on the actually programmed scaling

parameters the effective buffer can exceed to an entire

line. The access/bandwidth requirements to the VGA

frame buffer are reduced significantly.

20 ms – 24 × 64 µs

720 × 288 × 2 × 37 ns

0.98 ×

= 1.18

--------------------------------------------------------

2. Input from X port: 60 Hz, 720 pixel, 240 lines, 8-bit

data at 27 MHz data rate (ITU 656), 2 cycles per pixel;

output via I + H port: 16-bit data at 27 MHz clock,

1 cycle per pixel; the maximum HV_zoom is equal to:

The high performance video scaler in the SAA7108E;

SAA7109E has the following major blocks.

16.666 ms – 22 × 64 µs

720 × 240 × 1 × 37 ns

0.98 ×

= 2.34

--------------------------------------------------------------

• Acquisition control (horizontal and vertical timer) and

task handling (the region/field/frame based processing)

The video scaler receives its input signal from the video

decoder or from the expansion port (X port). It gets 16-bit

Y-C_B-C_R4 : 2 : 2 input data at a continuous rate of

13.5 MHz from the decoder. A discontinuous data stream

can be accepted from the expansion port, normally 8-bit

wide ITU 656 like Y-C_B-C_Rdata, accompanied by a pixel

qualifier on XDQ.

• Prescaler, for horizontal downscaling by an integer

factor, combined with appropriate band limiting filters,

especially anti-aliasing for CIF format

• Brightness, saturation and contrast control for scaled

output data

• Line buffer, with asynchronous read and write, to

support vertical upscaling (e.g. for videophone

application, converting 240 into 288 lines, Y-C_B-C_R

4 : 2 : 2)

The input data stream is sorted into two data paths, one for

luminance (or raw samples), and one for time multiplexed

chrominance C_Band C_Rsamples. A Y-C_B-C_R4 : 1 : 1

input format is converted to 4 : 2 : 2 for the horizontal

prescaling and vertical filter scaling operation.

• Vertical scaling, with phase accurate Linear Phase

Interpolation (LPI) for zoom and downscaling, or phase

accurate Accumulation Mode (ACM) for large

The scaler operation is defined by two programming pages

A and B, representing two different tasks that can be

applied field alternating or to define two regions in a field

(e.g. with different scaling range, factors, and signal

source during odd and even fields).

downscaling ratios and better anti-alias suppression

• Variable Phase Delay (VPD), operates as horizontal

phase accurate interpolation for arbitrary non-integer

scaling ratios, supporting conversion between square

and rectangular pixel sampling

Each programming page contains control for:

• Signal source selection and formats

• Output formatter for scaled Y-C_B-C_R4 : 2 : 2,

Y-C_B-C_R4 : 1 : 1 and Y only (format also for raw data)

• Task handling and trigger conditions

• FIFO, 32-bit wide, with 64 pixel capacity in Y-C_B-C_R

• Input and output acquisition window definition

• H prescaler, V scaler and H phase scaling.

formats

• Output interface, 8 or 16-bit (only if extended by H port)

data pins wide, synchronous or asynchronous

operation, with stream events on discrete pins, or coded

in the data stream.

Raw VBI data will be handled as specific input format and

need its own programming page (equals own task).

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SAA7108E; SAA7109E

In VBI pass through operation the processing of prescaler

and vertical scaling has to be disabled, however the

horizontal fine scaling VPD can be activated. Upscaling

(oversampling, zooming), free of frequency folding, up to

factor 3.5 can be achieved, as required by some software

data slicing algorithms.

9.3.1.1

Input ﬁeld processing

The trigger event for the field sequence detection from

external signals (X port) are defined in subaddress 92H.

The state of the scalers horizontal reference signal at the

time of the vertical reference edge is taken from the X port

as field sequence identifier (FID). For example, if the falling

edge of the XRV input signal is the reference and the state

of XRH input is logic 0 at that time, the detected field ID is

logic 0.

These raw samples are transported through the image

port as valid data and can be output as Y only format. The

lines are framed by SAV and EAV codes.

The bits XFDV[92H[7]] and XFDH[92H[6]] define the

detection event and state of the flag from the X port. For

the default setting of XFDV and XFDH at ‘00’ is taken from

the state of the horizontal input at the falling edge of the

vertical input.

9.3.1

ACQUISITION CONTROL AND TASK HANDLING

(SUBADDRESSES 80H, 90H, 91H, 94H TO 9FH

AND C4H TO CFH)

The acquisition control receives horizontal and vertical

synchronization signals from the decoder section or from

the X port. The acquisition window is generated via pixel

and line counters at the appropriate places in the data

path. Only qualified pixels and lines (lines with qualified

pixel) are counted from the X port.

The scaler gets corresponding field ID information directly

from the SAA7108E; SAA7109E decoder path.

The FID flag is used to determine whether the first or

second field of a frame is going to be processed within the

scaler, and it is also used as trigger conditions for the task

handling (see bits STRC[1:0] 90H[1:0]).

The acquisition window parameters are as follows:

• Signal source selection: input video stream and formats

from the decoder, or from the X port (programming bits

SCSRC[1:0] 91H[5:4] and FSC[2:0] 91H[2:0])

According to ITU 656, FID at logic 0 means first field of a

frame. To ease the application, the polarities of the

detection results on the X port signals and the internal

decoder ID can be changed via XFDH.

Remark: The input of raw VBI data from the internal

decoder should be controlled via the decoder output

formatter and the LCR registers (see Section 9.2)

As the V sync from the decoder path has a half line timing

(due to the interlaced video signal), but the scaler

processing only recognises full lines, during 1st fields from

the decoder the line count of the scaler can possibly shift

by one line, compared to the 2nd field. This can be

compensated for by switching the vertical trigger event, as

defined by XDV0, to the opposite V sync edge or by using

the vertical scalers phase offsets. The vertical timing of the

decoder can be seen in Figs 29 and 30.

• Vertical offset: defined in lines of the video source,

parameter YO[11:0] 99H[3:0] 98H[7:0]

• Vertical length: defined in lines of the video source,

parameter YS[11:0] 9BH[3:0] 9AH[7:0]

• Vertical length: defined in number of target lines, as a

result of vertical scaling, parameter YD[11:0] 9FH[3:0]

9EH[7:0]

• Horizontal offset: defined in number of pixels of the

video source, parameter XO[11:0] 95H[3:0] 94H[7:0]

As the horizontal and vertical reference events inside the

ITU 656 data stream (from X port) and the real-time

reference signals from the decoder path are processed

differently, the trigger events for the input acquisition also

have to be programmed differently.

• Horizontal length: defined in number of pixels of the

video source, parameter XS[11:0] 97H[3:0] 96H[7:0]

• Horizontal destination size: defined in target pixels after

fine scaling, parameter XD[11:0] 9DH[3:0] 9CH[7:0].

The source start offset XO(11:0) and YO(11:0) opens the

acquisition window, and the target size (XD11 to XD0,

YD11 to YD0) closes the window, however the window is

cut vertically if there are less output lines than required.

The trigger events for the pixel and line counts are the

horizontal and vertical reference edges as defined in

subaddress 92H.

The task handling is controlled by subaddress 90H;

see Section 9.3.1.2.

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SAA7108E; SAA7109E

Table 38 Processing trigger and start

XDV1

92H[5]

XDV0

92H[4]

XDH

92H[2]

DESCRIPTION

Internal decoder: The processing triggers at the falling edge of the V123 pulse

(see Figs 29 (50 Hz) and 30 (60 Hz)), and starts earliest with the rising edge of the

decoder HREF at line number:

4/7 (50/60 Hz, 1st field), respectively 3/6 (50/60 Hz, 2nd field) (decoder count)

2/5 (50/60 Hz, 1st field), respectively 2/5 (50/60 Hz, 2nd field) (decoder count)

External ITU 656 stream: The processing starts earliest with SAV at line number 23

(50 Hz system), respectively line 20 (60 Hz system) (according ITU 656 count)

9.3.1.2

Task handling

Remarks:

• To activate a task, the start condition must be

fulfilled and the acquisition window offsets must be

reached. For example, in case of ‘start immediately’,

and two regions are defined for one field, the offset of

the lower region must be greater than (offset + length) of

the upper region, if not, the actual counted H and V

position at the end of the upper task is beyond the

programmed offsets and the processing will ‘wait for

next V’.

The task handler controls the switching between the two

programming register sets. It is controlled by

subaddresses 90H and C0H. A task is enabled via the

global control bits TEA[80H[4]] and TEB[80H[5]]. The

handler is then triggered by events which can be defined

for each register set.

In the event of a programming error the task handling and

the complete scaler can be reset to the initial states by the

software reset bit SWRST[88H[5]] being set to logic 0.

A software reset must be done after programming

especially if the programming registers, related acquisition

window and scaler are reprogrammed while a task is

active.

• Basically, the trigger conditions are checked when a

task is activated. It is important to know that they are

not checked while a task is inactive. So it is not possible

to trigger to the next logic 0 or logic 1 with overlapping

offset and active video ranges between the tasks (e.g.

task A STRC[2:0] = 2, YO[11:0] = 310 and task B

STRC[2:0] = 3, YO[11:0] = 310 results in an output field

rate of ⁵⁰⁄₃Hz).

The difference in the disabling/enabling of a task, which is

evaluated at the end of a running task (when SWRST is set

to logic 0) is that it sets the internal state machines directly

to their idle states.

• After power-on or software reset

(via SWRST[88H[5]]) task B gets priority over

task A.

The start condition for the handler is defined by bits

STRC[1:0] 90H[1:0] and means: start immediately, wait for

next V sync, next FID at logic 0 or next FID at logic 1. The

FID is evaluated if the vertical and horizontal offsets are

reached.

With RPTSK[90H[2]] at logic 1 the actual running task is

repeated (under the defined trigger conditions) before

handing control over to the alternate task.

To support field rate reduction, the handler is also enabled

to skip fields (bits FSKP[2:0] 90H[5:3]) before executing

the task. A TOGGLE flag is generated (used for the correct

output field processing), which changes state at the

beginning of a task every time a task is activated;

examples are given in Section 9.3.1.3.

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9.3.1.3

Output ﬁeld processing

When OFIDC = 0, the scalers input field ID is available as

output field ID on bit 6 of SAV and EAV, and respectively

on pin IGP0 (IGP1), if the FID output is selected.

As a reference for the output field processing, two signals

are available for the back-end hardware.

When OFIDC[90H[6]] = 1, the TOGGLE information is

available as output field ID on bit 6 of SAV and EAV, and

respectively on pin IGP0 (IGP1) if the FID output is

selected.

These signals are the input field ID from the scaler source

and a TOGGLE flag, which shows that an active task is

used an odd (1, 3, 5...) or even (2, 4, 6...) number of times.

Using a single or both tasks and reducing the field or frame

rate with the task handling functionality, the TOGGLE

information can be used to reconstruct an interlaced

scaled picture at a reduced frame rate. The TOGGLE flag

is not synchronized to the input field detection, as it is only

dependent on the interpretation of this information by the

external hardware i.e. whether the output of the scaler is

processed correctly; see Section 9.3.3.

Additionally bit 7 of SAV and EAV can be defined via

CONLH[90H[7]]. When CONLH[90H[7]] = 0 (default) it

sets bit 7 to logic 1; a logic 1 inverts the SAV/EAV bit 7.

So it is possible to mark the output of both tasks by

different SAV/EAV codes. This bit can also be seen as

‘task flag’ on the pins IGP0 (IGP1), if the TASK output is

selected.

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Table 39 Example for ﬁeld processing

FIELD SEQUENCE FRAME/FIELD

SUBJECT

EXAMPLE 1⁽¹⁾

EXAMPLE 2⁽²⁾⁽³⁾

EXAMPLE 3^(2)(4)(5)

EXAMPLE 4^(2)(4)(6)

1/1

1/2

2/1 1/1 1/2 2/1 2/2 1/1 1/2 2/1 2/2 3/1 3/2

1/1

1/2 2/1

2/2

3/1 3/2

Processed by task

State of detected

ITU 656 FID

TOGGLE ﬂag

0⁽⁷⁾

1⁽⁷⁾

Bit 6 of SAV/EAV byte

Required sequence

conversion at the vertical

scaler⁽⁸⁾

↓

UP UP LO UP LO UP LO UP LO UP LO

↓

LO UP

↓

UP LO

↓

UP UP LO UP LO LO UP LO LO UP UP

LO LO

UP UP

Output⁽⁹⁾

Notes

1. Single task every field; OFIDC = 0; subaddress 90H at 40H; TEB[80H[5]] = 0.

2. Tasks are used to scale to different output windows, priority on task B after SWRST.

3. Both tasks at ¹⁄₂frame rate; OFIDC = 0; subaddresses 90H at 43H and C0H at 42H.

4. In examples 3 and 4 the association between input FID and tasks can be flipped, dependent on which time the SWRST is de-asserted.

5. Task B at ²⁄₃frame rate constructed from neighbouring motion phases; task A at ¹⁄₃frame rate of equidistant motion phases; OFIDC = 1;

subaddresses 90H at 41H and C0H at 45H.

6. Task A and B at ¹⁄₃frame rate of equidistant motion phases; OFIDC = 1; subaddresses 90H at 41H and C0H at 49H.

7. State of prior field.

8. It is assumed that input/output FID = 0 (upper lines); UP = upper lines; LO = lower lines.

9. O = data output; NO = no output.

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

9.3.2

HORIZONTAL SCALING

• The bit XC2_1[A2H[3]], which defines the weighting of

the incoming pixels during the averaging process

The overall horizontal scaling factor has to be split into a

binary and a rational value according to the following

– XC2_1 = 0

– XC2_1 = 1

1 + 1...+ 1 + 1

1 + 2...+ 2 + 1.

output pixel

equation: H scale ratio =

------------------------------

input pixel

The prescaler creates a prescale dependent FIR low-pass,

with up to 64 + 7 filter taps. The parameter XACL[5:0] can

be used to vary the low-pass characteristic for a given

integer prescale of ¹⁄_XPSC[5:0]. The user can therewith

decide between signal bandwidth (sharpness impression)

and alias.

1024

H scale ratio =

--------------------------- ------------------------------

XPSC[5:0] XSCY[12:0]

where, the parameter of the prescaler XPSC[5:0] = 1 to 63

and the parameter of VPD phase interpolation

XSCY[12:0] = 300 to 8191 (0 to 299 are only theoretical

values). For example, ¹⁄_3.5is split into ¹⁄₄× 1.14286. The

binary factor is processed by the prescaler, the arbitrary

non-integer ratio is achieved via the variable phase delay

VPD circuitry, called horizontal fine scaling. The latter

calculates horizontally interpolated new samples with a

6-bit phase accuracy, which relates to less than 1 ns jitter

for regular sampling schemes. Together the prescaler and

fine scaler form the horizontal scaler of the SAA7108E;

SAA7109E.

The equation for the XPSC[5:0] calculation is:

Npix_in

XPSC[5:0] = lower integer of

-----------------------

Npix_out

Where:

the range is 1 to 63 (value 0 is not allowed);

Npix_in = number of input pixel, and

Npix_out = number of desired output pixel over the

complete horizontal scaler.

Using the accumulation length function of the prescaler

(XACL[5:0] A1H[5:0]), application and destination

dependent (e.g. scale for display or for a compression

machine), a compromise between visible bandwidth and

alias suppression can be found.

The use of the prescaler results in a XACL[5:0] and

XC2_1 dependent gain amplification. The amplification

can be calculated according to the equation:

DC gain = [(XACL[5:0] − XC2_1) + 1] × (XC2_1 + 1)

It is recommended to use sequence lengths and weights,

which results in a 2^NDC gain amplification, as these

amplitudes can be renormalized by the XDCG[2:0]

9.3.2.1

Horizontal prescaler (subaddresses

A0H to A7H and D0H to D7H)

The prescaling function consists of an FIR anti-alias filter

stage and an integer prescaler, which together form an

adaptive prescale dependent low-pass filter to balance the

sharpness and aliasing effects.

controlled

shifter of the prescaler.

------

2^N

The renormalization range of XDCG[2:0] is 1, ¹⁄₂... down

to ¹⁄₁₂₈

The FIR pre-filter stage implements different low-pass

characteristics to reduce the anti-alias for downscales in

the range of 1 to ¹⁄₂. A CIF optimized filter is built-in, which

reduces artefacts for CIF output formats (to be used in

combination with the prescaler set to ¹⁄₂scale); see

Table 40.

Other amplifications have to be normalized by using the

following BCS control circuitry. In these cases the

prescaler has to be set to an overall gain ≤1, e.g. for an

accumulation sequence of ‘1 + 1 + 1’ (XACL[5:0] = 2 and

XC2_1 = 0), XDCG[2:0] must be set to ‘010’, which

equals ¹⁄₄and the BCS has to amplify the signal to ⁴⁄₃

(SATN[7:0] and CONT[7:0] value = lower integer of

⁴⁄₃× 64).

The function of the prescaler is defined by:

• An integer prescaling ratio XPSC[5:0] A0H[5:0] (equals

1 to 63), which covers the integer downscale range

1 to ¹⁄₆₃

The use of XACL[5:0] is XPSC[5:0] dependent.

XACL[5:0] must be <2 × XPSC[5:0].

• An averaging sequence length XACL[5:0] A1H[5:0]

(equals 0 to 63); range 1 to 64

XACL[5:0] can be used to find a compromise between

bandwidth (sharpness) and alias effects.

• A DC gain renormalization XDCG[2:0] A2H[2:0];

1 down to ¹⁄₁₂₈

)

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Remark: Due to bandwidth considerations XPSC[5:0] and

XACL[5:0] can be chosen differently to the previously

mentioned equations or Table 41, as the horizontal phase

scaling is able to scale in the range from zooming up by

For example, if XACL[5:0] = 5, XC2_1 = 1, then

DC gain = 10 and the required XDCG[2:0] = 4.

The horizontal source acquisition timing and the

prescaling ratio is identical for both the luminance and

chrominance path, but the FIR filter settings can be

defined differently in the two channels.

factor 3 to downscaling by a factor of ¹⁰²⁴

⁄

8191

Figs 34 and 35 show some frequency characteristics of

the prescaler.

Fade-in and fade-out of the filters is achieved by copying

an original source sample each as first and last pixel after

prescaling.

Table 41 shows the recommended prescaler

programming. Other programming, than given in Table 41,

may result in better alias suppression, but the resulting

DC gain amplification needs to be compensated by the

BCS control, according to the equation:

Figs 32 and 33 show the frequency characteristics of the

selectable FIR filters.

2^XDCG[2:0]

DC gain × 64

CONT[7:0] = SATN[7:0] = lower integer of

----------------------------------

Where:

2^XDCG[2:0]≥ DC gain

DC gain = (XC2_1 + 1) × XACL[5:0] + (1 − XC2_1).

Table 40 FIR preﬁlter functions

PFUV[1:0] A2H[7:6]

PFY[1:0] A2H[5:4]

LUMINANCE FILTER

COEFFICIENTS

CHROMINANCE COEFFICIENTS

bypassed

1 2 1

bypassed

1 2 1

−1 1 1.75 4.5 1.75 1 −1

1 2 2 2 1

3 8 10 8 3

1 2 2 2 1

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MHB543

(dB)

−3

−6

−9

(1)

(2)

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

(3)

(1) PFY[1:0] = 01.

(2) PFY[1:0] = 10.

(3) PFY[1:0] = 11.

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

f_sig/f_clock

0.5

Fig.32 Luminance prefilter characteristic.

MHB544

(dB)

−3

−6

−9

(1)

(2)

(3)

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

(1) PFUV[1:0] = 01.

(2) PFUV[1:0] = 10.

(3) PFUV[1:0] = 11.

0.025

0.05

0.075

0.1

0.125

0.15

0.175

0.2

0.225

f_sig/f_clock

0.25

Fig.33 Chrominance prefilter characteristic.

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MHB545

(dB)

−3

−6

−9

(5)

(4)

(3)

(2)

(1)

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

XC2_1 = 0; Zero’s at

f = n ×

------------------------

XACL + 1

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

f_sig/f_clock

0.5

with XACL = (1), (2), (3),

(4) or (5)

Fig.34 Examples for prescaler filter characteristics: effect of increasing XACL[5:0].

MHB546

(dB)

(1)

3 dB at 0.25

−3

(2)

6 dB at 0.33

−6

(6) (5)

(4)

(3)

−9

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

(1) XC2_1 = 0 and

XACL[5:0] = 1.

(2) XC2_1 = 1 and

XACL[5:0] = 2.

(3) XC2_1 = 0 and

XACL[5:0] = 3.

(4) XC2_1 = 1 and

XACL[5:0] = 4.

(5) XC2_1 = 0 and

XACL[5:0] = 7.

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

f_sig/f_clock

0.5

(6) XC2_1 = 1 and

XACL[5:0] = 8.

Fig.35 Examples for prescaler filter characteristics: setting XC2_1 = 1.

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Product speciﬁcation

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SAA7108E; SAA7109E

Table 41 Example of XACL[5:0] usage

RECOMMENDED VALUES

FOR LOWER BANDWIDTH FOR HIGHER BANDWIDTH

FIR

PREFILTER

PFY[1:0]/

PRESCALE XPSC

RATIO

[5:0]

REQUIREMENTS REQUIREMENTS

PFUV[1:0]

XACL[5:0]

XC2_1

XDCG[2:0] XACL[5:0]

XC2_1

XDCG[2:0]

0 to 2

⁄

(1 2 1) × ¹⁄₄

(1 1) × ¹⁄₂

(1)

(1 2 2 2 1) × ¹⁄₈

(1 1 1 1) × ¹⁄₄

(1)

(1 1 1 1 1 1 1 1) × ¹⁄₈

(1 2 2 2 1) × ¹⁄₈

(1)

(1 2 2 2 2 2 2 2 1) × ¹⁄₁₆

(1 1 1 1 1 1 1 1) × ¹⁄₈

(1 2 2 2 2 2 2 2 1) × ¹⁄₁₆

(1 1 1 1 1 1 1 1) × ¹⁄₈

(1 2 2 2 2 2 2 2 1) × ¹⁄₁₆

(1 1 1 1 1 1 1 1) × ¹⁄₈

(1)

(1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) × ¹⁄₁₆

(1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1) × ¹⁄₃₂

(1 2 2 2 2 2 2 2 1) × ¹⁄₁₆

(1)

(1 2 2 2 2 2 2 2 1) × ¹⁄₁₆

⁄

(1)

(1 2 2 2 2 2 2 2 1) × ¹⁄₁₆

⁄

Note

1. Resulting FIR function.

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SAA7108E; SAA7109E

9.3.2.2

Horizontal ﬁne scaling (variable phase delay

ﬁlter; subaddresses A8H to AFH and

D8H to DFH)

9.3.3.1

Line FIFO buffer (subaddresses 91H, B4H and

C1H, E4H)

The line FIFO buffer is a dual ported RAM structure for

768 pixels, with asynchronous write and read access. The

line buffer can be used for various functions, but not all

functions may be available simultaneously.

The horizontal fine scaling (VPD) should operate at scaling

ratios between ¹⁄₂and 2 (0.8 and 1.6), but can also be

used for direct scaling in the range from ¹⁄_7.999to

(theoretical) zoom 3.5 (restriction due to the internal data

path architecture), without prescaler.

The line buffer can buffer a complete unscaled active video

line or more than one shorter lines (only for non-mirror

mode), for selective repetition for vertical zoom-up.

In combination with the prescaler a compromise between

sharpness impression and alias can be found, which is

signal source and application dependent.

For zooming up from 240 lines to 288 lines e.g., every

fourth line is requested (read) twice from the vertical

scaling circuitry for calculation.

For the luminance channel a filter structure with 10 taps is

implemented, for the chrominance a filter with 4 taps.

For conversion of a 4 : 2 : 0 or 4 : 1 : 0 input sampling

scheme (MPEG, video phone, Indeo YUV-9) to ITU like

sampling scheme 4 : 2 : 2, the chrominance line buffer is

read twice or four times, before being refilled again by the

source. By means of the input acquisition window

definition it has to be preserved, that the processing starts

with a line containing luminance and chrominance

information for 4 : 2 : 0 and 4 : 1 : 0 input. The bits

FSC[2:1] 91H[2:1] define the distance between the Y/C

lines. In case of 4 : 2 : 2 and 4 : 1 : 1 FSC2 and FSC1

have to be set to ‘00’.

Luminance and chrominance scale increments

(XSCY[12:0] A9H[4:0] A8H[7:0] and XSCC[12:0] ADH[4:0]

ACH[7:0]) are defined independently, but must be set in a

2 : 1 relationship in the actual data path implementation.

The phase offsets XPHY[7:0] AAH[7:0] and XPHC[7:0]

AEH[7:0] can be used to shift the sample phases slightly.

XPHY[7:0] and XPHC[7:0] covers the phase offset range

7.999T to ¹⁄₃₂T. The phase offsets should also be

programmed in a 2 : 1 ratio.

The underlying phase controlling DTO has a 13-bit

resolution.

The line buffer can also be used for mirroring, i.e. for

flipping the image left to right, for the vanity picture in video

phone application (bit YMIR[B4H[4]]). In mirror mode only

one active prescaled line can be held in the FIFO at a time.

According to the equations

Npix_in

XPSC[5:0] Npix_out

XSCY[12:0] = 1024 ×

and

--------------------------- -----------------------

The line buffer can be utilized as excessive pipeline buffer

for discontinuous and variable rate transfer conditions at

the expansion port or image port.

XSCY[12:0]

XSCC[12:0] =

------------------------------

The VPD covers the scale range from 0.125 to zoom 3.5.

The VPD acts equivalent to a polyphase filter with 64

possible phases. In combination with the prescaler, it is

possible to get high accurate samples from a highly

anti-aliased integer downscaled input picture.

9.3.3.2

Vertical scaler (subaddresses B0H to BFH and

E0H to EFH)

Vertical scaling of any ratio from 64 (theoretical zoom)

to ¹⁄₆₃(icon) can be applied.

The vertical scaling block consists of another line delay,

and the vertical filter structure, that can operate in two

different modes. These are the Linear Phase Interpolation

(LPI) and Accumulation (ACM) modes, controlled by

YMODE[B4H[0]].

9.3.3

VERTICAL SCALING

The vertical scaler of the SAA7108E; SAA7109E decoder

part consists of a line FIFO buffer for line repetition and the

vertical scaler block, which implements the vertical scaling

on the input data stream in 2 different operational modes

from theoretical zoom by 64 down to icon size ¹⁄₆₄. The

vertical scaler is located between the BCS and horizontal

fine scaler, so that the BCS can be used to compensate for

the DC gain amplification of the ACM mode (see

Section 9.3.3.2) as the internal RAMs are only 8-bit wide.

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• LPI mode: In the linear phase interpolation mode

(YMODE = 0) two neighbouring lines of the source video

stream are added together, but weighted by factors

corresponding to the vertical position (phase) of the

target output line relative to the source lines. This linear

interpolation has a 6-bit phase resolution, which equals

64 intra line phases. It interpolates between two

consecutive input lines only. The LPI mode should be

applied for scaling ratios around 1 (down to ¹⁄₂), it must

be applied for vertical zooming.

• BCS value to compensate DC gain in ACM mode

(contrast and saturation have to be set): CONT[7:0]

A5H[7:0] respectively SATN[7:0] A6H[7:0]

Nline_out

= lower integer of

× 64 , or

------------------------

Nline_in

1024

× 64

------------------------------

YSCY[15:0]

9.3.3.3

Use of the vertical phase offsets

• ACM mode: The vertical Accumulation (ACM) mode

(YMODE = 1) represents a vertical averaging window

over multiple lines, sliding over the field. This mode also

generates phase correct output lines. The averaging

window length corresponds to the scaling ratio, resulting

in an adaptive vertical low-pass effect, to greatly reduce

aliasing artefacts. ACM can be applied for downscales

only from ratio 1 down to ¹⁄₆₄. ACM results in a scale

dependent DC gain amplification, which has to be

precorrected by the BCS control of the scaler part.

As shown in Section 9.3.1.3, the scaler processing may

run randomly over the interlaced input sequence.

Additionally the interpretation and timing between ITU 656

field ID and real-time detection by means of the state of

H sync at the falling edge of V sync may result in different

field ID interpretation.

A vertically scaled interlaced output also gets a larger

vertical sampling phase error, if the interlaced input fields

are processed, without regard to the actual scale at the

starting point of operation (see Fig.36).

The phase and scale controlling DTO calculates in 16-bit

resolution, controlled by parameters YSCY[15:0] B1H[7:0]

B0H[7:0] and YSCC[15:0] B3H[7:0] B2H[7:0], continuously

over the entire filed. A start offset can be applied to the

phase processing by means of the parameters

YPY3[7:0] to YPY0[7:0] in BFH[7:0] to BCH[7:0] and

YPC3[7:0] to YPC0[7:0] in BBH[7:0] to B8H[7:0]. The start

phase covers the range of ²⁵⁵₃₂to ¹⁄₃₂lines offset.

⁄

The four events to be considered are illustrated in Fig.37.

In Tables 42 and 43 PHO is a usable common phase

offset.

It should be noted that the equations in Fig.37 also

produce an interpolated output for the unscaled case, as

the geometrical reference position for all conversions is

the position of the first line of the lower field (see Table 42).

By programming appropriate, opposite, vertical start

phase values (subaddresses B8H to BFH and

E8H to EFH) depending on odd/even field ID of the source

video stream and A/B page cycle, frame ID conversion and

field rate conversion are supported (i.e. de-interlacing,

re-interlacing).

If there is no need for UP-LO and LO-UP conversion and

the input field ID is the reference for the back-end

operation, then it is UP-LO = UP-UP and LO-UP = LO-LO

and the ¹⁄₂line phase shift (PHO + 16) that can be

skipped; this case is given in Table 43.

The SAA7108E; SAA7109E supports 4 phase offset

registers per task and component (luminance and

chrominance). The value of 20H represents a phase shift

of one line.

Figs 36 and 37 and Tables 42 and 43 describe the use of

the offsets.

Remark: The vertical start phase, as well as the

scaling ratio are defined independently for luminance

and chrominance channels, but must be set to the

same values in the actual implementation for accurate

4 : 2 : 2 output processing.

The registers are assigned to the following events;

e.g. subaddresses B8H to BBH:

• B8H: 00 = input field ID 0, task status bit 0 (toggle

status, see Section 9.3.1.3)

The vertical processing communicates on its input side

with the line FIFO buffer. The scale related equations are:

• B9H: 01 = input field ID 0, task status bit 1

• BAH: 10 = input field ID 1, task status bit 0

• BBH: 11 = input field ID 1, task status bit 1.

• Scaling increment calculation for ACM and LPI mode,

downscale and zoom: YSCY[15:0] and YSCC[15:0]

Nline_in

Nline_out

= lower integer of 1024 ×

------------------------

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Depending on the input signal (interlaced or non-interlaced) and the task processing (50 Hz or field reduced processing

with one or two tasks, see examples in Section 9.3.1.3), other combinations may also be possible, but the basic

equations are the same.

scaled output,

no phase offset

scaled output,

with phase offset

unscaled input

ﬁeld 1

ﬁeld 2

ﬁeld 1

ﬁeld 2

ﬁeld 1

ﬁeld 2

correct scale dependent position

scale dependent start offset

mismatched vertical line distances

MHB547

Fig.36 Basic problem of interlaced vertical scaling (example: downscale ³⁄₅).

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handbook, full pagewidth

ﬁeld 1

upper

ﬁeld 2

lower

ﬁeld 1

ﬁeld 2

ﬁeld 1

ﬁeld 2

case UP-UP

case LO-LO

case UP-LO

case LO-UP

MHB548

1024

YSCY[15:0]

------------------------------

Offset =

= 32 = 1 line shift

C = scale increment =

------------

D = no offset = 0

A = input line shift = 16

YSCY[15:0]

------------------------------

B = input line shift+ scale increment =

-- --

+ 16

Fig.37 Derivation of the phase related equations (example: interlace vertical scaling down to ³⁄₅, with field

conversion).

Table 42 Examples for vertical phase offset usage: global equations

INPUT FIELD UNDER

PROCESSING

OUTPUT FIELD

INTERPRETED AS

EQUATION FOR PHASE OFFSET

CALCULATION (DECIMAL VALUES)

USED ABBREVIATION

Upper input lines

upper output lines

lower output lines

UP-UP

UP-LO

PHO + 16

YSCY[15:0]

------------------------------

PHO +

PHO

+ 16

Lower input lines

upper output lines

lower output lines

LO-UP

LO-LO

YSCY[15:0]

------------------------------

PHO +

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Table 43 Vertical phase offset usage; assignment of the phase offsets

DETECTED INPUT

FIELD ID

VERTICAL PHASE

OFFSET

TASK STATUS BIT

CASE

EQUATION TO BE USED

0 = upper lines

1 = lower lines

YPY0[7:0] and

YPC0[7:0]

case 1⁽¹⁾UP-UP (PHO)

case 2⁽²⁾UP-UP

case 3⁽³⁾UP-LO

YPY1[7:0] and

YPC1[7:0]

case 1

case 2

case 3

case 1

UP-UP (PHO)

UP-LO

UP-UP

YPY2[7:0] and

YPC2[7:0]

YSCY[15:0]

------------------------------

LO-LO PHO +

– 16

case 2

case 3

case 1

LO-UP

LO-LO

1 = lower lines

YPY3[7:0] and

YPC3[7:0]

YSCY[15:0]

------------------------------

LO-LO PHO +

case 2

case 3

LO-LO

LO-UP

Notes

1. Case 1: OFIDC[90H[6]] = 0; scaler input field ID as output ID; back-end interprets output field ID at logic 0 as upper

output lines.

2. Case 2: OFIDC[90H[6]] = 1; task status bit as output ID; back-end interprets output field ID at logic 0 as upper output

lines.

3. Case 3: OFIDC[90H[6]] = 1; task status bit as output ID; back-end interprets output field ID at logic 1 as upper output

lines.

9.4

VBI data decoder and capture

(subaddresses 40H to 7FH)

For lines 2 to 24 of a field, per VBI line, 1 of 16 standards

can be selected (LCRxxx[41:57[7:0]]: 23 × 2 × 4-bit

programming bits). The definition for line 24 is valid for the

rest of the corresponding field, normally no text data (video

data) should be selected there (LCR24 = FFH) to stop the

activity of the VBI data slicer during active video.

The SAA7108E; SAA7109E contains a versatile VBI data

decoder.

The implementation and programming model accords to

the VBI data slicer the built-in multimedia video data

acquisition circuit of the SAA5284.

To adjust the slicers processing to the input signal source,

there are offsets in the horizontal and vertical direction

available (parameters HOFF[5B,59[2:0,7:0]],

VOFF[5B,5A[4,7:0]] and FOFF[5B[7]]).

The circuitry recovers the actual clock phase during the

clock run-in period, slices the data bits with the selected

data rate, and groups them into bytes. The result is

buffered into a dedicated VBI data FIFO with a capacity of

2 × 56 bytes (2 × 14 Dwords). The clock frequency, signal

source, field frequency and accepted error count must be

defined in subaddress 40H.

In difference to the scalers counting, the slicers offsets

define the position of the horizontal and vertical trigger

events related to the processed video field. The trigger

events are the falling edge of HREF and the falling edge of

V123 from the decoder processing part.

The VBI data standards that are supported are given in

Table 44.

The relationship of these programming values to the input

signal and the recommended values can be seen in

Tables 34 to 37.

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Table 44 Data types supported by the data slicer block

DATA TYPE

NUMBER

DATA RATE

(Mbits/s)

WINDOW

HAM

CHECK

STANDARD TYPE

FRAMING CODE

27H

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

teletext EuroWST, CCST

European Closed Caption

VPS

6.9375

WST625

CC625

VPS

always

0.500

001

9951H

wide screen signalling bits

US teletext (WST)

US Closed Caption (line 21)

(video data selected)

(raw data selected)

teletext

1E3C1FH

27H

WSS

5.7272

0.503

WST525

CC525

disable

always

001

none

6.9375

programmable

general text optional

VITC625

VITC/EBU time codes (Europe) 1.8125

VITC/SMPTE time codes (USA) 1.7898

VITC525

open

US NABTS

5.7272

NABTS

optional

MOJI (Japanese)

5.7272

programmable (A7H) Japtext

Japanese format switch (L20/22)

programmable

none

open

no sliced data transmitted

(video data selected)

disable

9.5

Image port output formatter

(subaddresses 84H to 87H)

The disconnected data stream at the scaler output is

accompanied by a data valid flag (or data qualifier), or is

transported via a gated clock. Clock cycles with invalid

data on the I port data bus (including the HPD pins in 16-bit

output mode) are marked with code 00H.

The output interface consists of a FIFO for video and for

sliced text data, an arbitration circuit, which controls the

mixed transfer of video and sliced text data over the I port,

and a decoding and multiplexing unit, which generates the

8 or 16-bit wide output data stream together with the

accompanying reference and help information.

The output interface also arbitrates the transfer between

scaled video data and sliced text data over the I port

output.

The clock for the output interface can be derived from an

internal clock, decoder, expansion port or an externally

provided clock which is appropriate, for example, for the

VGA and frame buffer. The clock can be up to 33 MHz.

The scaler provides the following video related timing

reference events (signals), which are available on pins as

defined by subaddresses 84H and 85H:

The bits VITX1 and VITX0 (subaddress 86H) are used to

control the arbitration.

The serialization of the internal 32-bit Dwords to 8-bit or

16-bit output (optional), as well as the insertion of the

extended ITU 656 codes (SAV/EAV for video data, ANC or

SAV/EAV codes for sliced text data) are also done here.

For handshaking with the VGA controller, or other memory

or bus interface circuitry, programmable FIFO flags are

provided; see Section 9.5.2.

• Output field ID

• Start and end of vertical active video range

• Start and end of active video line

• Data qualifier or gated clock

• Actually activated programming page (if CONLH is

used)

• Threshold controlled FIFO filling flags (empty, full, filled)

• Sliced data marker.

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9.5.1

SCALER OUTPUT FORMATTER

(SUBADDRESSES 93H AND C3H)

FSI[2:0] defines the horizontal packing of the data,

FOI[1:0] defines how many Y only lines are expected

before a Y/C line will be formatted. If FYSK is set to logic 0

preceding Y only lines will be skipped, and the output will

always start with a Y/C line.

The output formatter organizes the packing into the output

FIFO. The following formats are available:

Y-C_B-C_R4 : 2 : 2, Y-C_B-C_R4 : 1 : 1, Y-C_B-C_R4 : 2 : 0,

Y-C_B-C_R4 : 1 : 0, Y only (e.g. for raw samples). The

formatting is controlled by FSI[2:0] 93H[2:0], FOI[1:0]

93H[4:3] and FYSK[93H[5]].

Additionally the output formatter limits the amplitude range

of the video data (controlled by ILLV[85H[5]]); see

Table 47.

The data formats are defined on Dwords, or multiples

thereof, and are similar to the video formats as

recommended for PCI multimedia applications (see

SAA7146A). Planar formats are not supported.

Table 45 Byte stream for different output formats

OUTPUT FORMAT

Y-C_B-C_R4 : 2 : 2

Y-C_B-C_R4 : 1 : 1

Yonly

BYTE SEQUENCE FOR 8-BIT OUTPUT MODES

C_B0

Y0 C_R0

Y1 Y2

Y1 C_B2

Y1 C_B4

Y3 Y4

Y2 C_R2

Y2 C_R4

Y5 Y6

Y3 C_B4

Y3 Y4

Y7 Y8

Y4 C_R4

Y5 Y6

C_B6

C_B8

Y9 Y10

Y11 Y12

Y13

Table 46 Explanation to Table 45

NAME

EXPLANATION

C_Bn

C_B(B − Y) colour difference component, pixel number n = 0, 2, 4 to 718

Y (luminance) component, pixel number n = 0, 1, 2, 3 to 719

C_Rn

C_R(R − Y) colour difference component, pixel number n = 0, 2, 4 to 718

Table 47 Limiting range on I port

VALID RANGE

DECIMAL VALUE HEXADECIMAL VALUE

SUPPRESSED CODES (HEXADECIMAL VALUE)

LIMIT STEP

ILLV[85H[5]]

LOWER RANGE

UPPER RANGE

1 to 254

8 to 247

01 to FE

08 to F7

00 to 07

F8 to FF

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9.5.2

VIDEO FIFO (SUBADDRESS 86H)

The decoded VBI data is collected in the dedicated VBI

data FIFO. Once the capture of a line is completed, the

FIFO can be streamed through the image port, preceded

by a header, giving the line number and standard.

The video FIFO at the scaler output contains 32 Dwords.

That corresponds to 64 pixels in 16-bit Y-C_B-C_R4 : 2 : 2

format. But as the entire scaler can act as a pipeline buffer,

the actually available buffer capacity for the image port is

much higher, and can exceed beyond a video line.

The VBI data period can be signalled via the sliced data

flag on pin IGP0 or IGP1. The decoded VBI data is lead by

the ITU ancillary data header (DID[5:0] 5DH[5:0] at value

<3EH) or by SAV/EAV codes selected by DID[5:0] at value

3EH or 3FH. IGP0 or IGP1 is set if the first byte of the ANC

header is valid on the I port bus; it is reset if an SAV

occurs. Therefore it may frame multiple lines of text data

output, in case the video processing starts with a distance

of several video lines to the region of text data. Valid sliced

data from the text FIFO is available on the I port as long as

the IGP0 or IGP1 flag is set and the data qualifier is active

on pin IDQ.

The image port and the video FIFO, can operate with the

video source clock (synchronous mode) or with an

externally provided clock (asynchronous, and burst mode),

as appropriate for the VGA controller or attached frame

buffer.

The video FIFO provides 4 internal flags, which report to

what extent the FIFO is actually filled. These are:

• The FIFO Almost Empty (FAE) flag

• The FIFO combined flag (FCF) or FIFO filled, which is

set at almost full level and reset, with hysteresis, only

after the level crosses below the almost empty mark

The decoded VBI data is presented in two different data

formats, controlled by bit RECODE.

RECODE = 1: values 00H and FFH will be recoded to

even parity values 03H and FCH

• The FIFO Almost Full (FAF) flag

• The FIFO Overflow (FOVL) flag.

RECODE = 0: values 00H and FFH may occur in the

data stream as detected.

The trigger levels for FAE and FAF are programmable by

FFL[1:0] 86H[3:2] (16, 24, 28, full) and FEL[1:0] 86H[1:0]

(16, 8, 4, empty).

9.5.4

VIDEO AND TEXT ARBITRATION (SUBADDRESS 86H)

The state of this flag can be seen on pins IGP0 or IGP1.

The pin mapping is defined by subaddresses 84H

and 85H; see Section 10.5.

Sliced text data and scaled video data are transferred over

the same bus, the I port. The mixed transfer is controlled

by an arbitration circuit. If the video data is transferred

without any interrupt and the video FIFO does not need to

buffer any output pixel, the text data is inserted after the

end of a scaled video line, normally during the video

blanking interval.

9.5.3

TEXT FIFO

The data of the terminal VBI data slicer is collected in the

text FIFO before transmission over the I port is requested

(normally before the video window starts) and partitioned

into two FIFO sections. A complete line is fed into the FIFO

before a data transfer is requested. So normally, one line

of text data is ready for transfer while the next text line is

collected. Thus sliced text data is delivered as a block of

qualified data, without any qualification gaps in the byte

stream of the I port.

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9.5.5

DATA STREAM CODING AND REFERENCE SIGNAL

GENERATION (SUBADDRESSES 84H, 85H AND 93H)

If ITU 656 like codes are not required, they can be

suppressed in the output stream.

As horizontal and vertical reference signals are logic 1,

active gate signals are generated, which frame the transfer

of the valid output data. Alternatively, the horizontal and

vertical trigger pulses can be generated on the rising

edges of the gates.

As a further option, it is possible to provide the scaler with

an external gating signal on pin ITRDY. It is therefore

possible to hold the data output for a certain time and to

get valid output data in bursts of a guaranteed length.

The sketched reference signals and events can be

mapped to the I port output pins IDQ, IGPH, IGPV, IGP0

and IGP1. The polarities of all the outputs can be modified

to enable flexible use. The default polarity for the qualifier

and reference signals is logic 1 (active).

Due to the dynamic FIFO behaviour of the complete scaler

path, the output signal timing has no fixed timing

relationship to the real-time input video stream. Thus fixed

propagation delays, in terms of clock cycles, related to the

analog input can not be defined.

Table 48 shows the relevant and supported SAV and EAV

coding.

The data stream is accompanied by a data qualifier.

Additionally invalid data cycles are marked with code 00H.

Table 48 SAV/EAV codes on the I port

SAV/EAV CODES ON I PORT⁽¹⁾(HEX)

MSB⁽²⁾OF SAV/EAV BYTE = 0 MSB⁽²⁾OF SAV/EAV BYTE = 1

EVENT DESCRIPTION

COMMENT

FIELD ID = 0

FIELD ID = 1

FIELD ID = 0

FIELD ID = 1

Next pixel is FIRST pixel of any

active line

HREF = active;

VREF = active

Previous pixel was LAST pixel

of any active line, but not the

last

HREF = inactive;

VREF = active

Next pixel is FIRST pixel of any

V-blanking line

HREF = active;

VREF = inactive

Previous pixel was LAST pixel

of the last active line or of any

V-blanking line

HREF = inactive;

VREF = inactive

No valid data, do not capture

and do not increment pointer

IDQ pin inactive

Notes

1. The leading byte sequence is: FFH-00H-00H.

2. The MSB of the SAV/EAV code byte is controlled by:

a) Scaler output data: task A MSB = CONLH[90H[7]]; task B

b) VBI data slicer output data: DID[5:0] 5DH[5:0] = 3EH

MSB = CONLH[C0H[7]].

MSB = 1; DID[5:0] 5DH[5:0] = 3FH

MSB = 0.

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invalid data

timing reference code

internal header

sliced data

and filling data

D_{DC_3}D_{DC_4}CS BC

timing reference code

invalid data

end of raw VBI line

00 00

00 EAV

...

FF 00 00 SAV SDID DC IDI1 IDI2

1_3

1_4

2_1

...

FF 00 00 EAV 00

MHB549

1_1

1_2

...

ANC data output is only filled up

to the Dword boundary

ANC header

00 FF

internal header

FF DID SDID DC IDI1 IDI2

sliced data

...

1_3

1_4

... D_{DC_3}D_{DC_4}CS BC

ANC header active for DID (subaddress 5DH) <3EH

Fig.38 Sliced data formats on the I port in 8-bit mode.

Table 49 Explanation to Fig.38

NAME

EXPLANATION

SAV

start of active data; see Table 50

SDID sliced data identiﬁcation: NEP⁽¹⁾, EP⁽²⁾, SDID5 to SDID0, freely programmable via I²C-bus subaddress 5EH, bits 5 to 0, e. g. to be used as

source identiﬁer

Dword count: NEP⁽¹⁾, EP⁽²⁾, DC5 to DC0. DC describes the number of succeeding 32-bit words:

• For SAV/EAV mode DC is fixed to 11 Dwords (byte value 4BH)

• For ANC mode it is: DC = ¹⁄₄(C + n), where C = 2 (the two data identification bytes IDI1 and IDI2) and n = number of decoded bytes

according to the chosen text standard.

Note that the number of valid bytes inside the stream can be seen in the BC byte.

IDI1

IDI2

D_{n_m}

internal data identiﬁcation 1: OP⁽³⁾, FID (ﬁeld 1 = 0, ﬁeld 2 = 1), LineNumber8 to LineNumber3 = Dword 1 byte 1; see Table 50

internal data identiﬁcation 2: OP⁽³⁾, LineNumber2 to LineNumber0, DataType3 to DataType0 = Dword 1 byte 2; see Table 50

Dword number n, byte number m

D_{DC_4}last Dword byte 4, note: for SAV/EAV framing DC is ﬁxed to 0BH, missing data bytes are ﬁlled up; the ﬁll value is A0H

the check sum byte, the check sum is accumulated from the SAV (respectively DID) byte to the D_{DC_4}byte

number of valid sliced bytes counted from the IDI1 byte

EAV

end of active data; see Table 50

Notes

1. Inverted EP (bit 7); for EP see note 2.

2. Even parity (bit 6) of bits 5 to 0.

3. Odd parity (bit 7) of bits 6 to 0.

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Table 50 Bytes stream of the data slicer

NICK

NAME

COMMENT

subaddress

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

DID,

SAV,

EAV

NEP⁽¹⁾

NEP

EP⁽²⁾

FID⁽³⁾

I1⁽⁴⁾

I0⁽⁴⁾

5DH = 00H

subaddress 5DH;

bit 5 = 1

FID⁽³⁾

D4[5DH] D3[5DH] D2[5DH] D1[5DH] D0[5DH]

subaddress 5DH

bit 5 = 3EH; note 5

V⁽⁶⁾

H⁽⁷⁾

subaddress 5DH

bit 5 = 3FH; note 5

SDID

programmable via

subaddress 5EH

NEP

D5[5EH] D4[5EH] D3[5EH] D2[5EH] D1[5EH] D0[5EH]

DC⁽⁸⁾

IDI1

IDI2

NEP

OP⁽⁹⁾

EP⁽²⁾

FID⁽³⁾

LN2⁽¹⁰⁾LN1⁽¹⁰⁾

DC5

LN8⁽¹⁰⁾

DC4

LN7⁽¹⁰⁾

LN0⁽¹⁰⁾

CS4

DC3

LN6⁽¹⁰⁾

DT3⁽¹¹⁾

CS3

DC2

LN5⁽¹⁰⁾

DT2⁽¹¹⁾

CS2

DC1

LN4⁽¹⁰⁾

DT1⁽¹¹⁾

CS1

DC0

LN3⁽¹⁰⁾

DT0⁽¹¹⁾

CS0

check sum byte

valid byte count

CS6

CS5

CNT5

CNT4

CNT3

CNT2

CNT1

CNT0

Notes

1. NEP = inverted EP (see note 2).

2. EP = Even Parity of bits 5 to 0.

3. FID = 0: field 1; FID = 1: field 2.

4. I1 = 0 and I0 = 0: before line 1; I1 = 0 and I0 = 1: lines 1 to 23; I1 = 1 and I0 = 0: after line 23; I1 = 1 and I0 = 1:

line 24 to end of field.

5. Subaddress 5DH at 3EH and 3FH are used for ITU 656 like SAV/EAV header generation; recommended value.

6. V = 0: active video; V = 1: blanking.

7. H = 0: start of line; H = 1: end of line.

8. DC = Data Count in Dwords according to the data type.

9. OP = Odd Parity of bits 6 to 0.

10. LN = Line Number.

11. DT = Data Type according to table.

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9.6

Audio clock generation

(subaddresses 30H to 3FH)

• Audio master Clocks Nominal Increment, ACNI[21:0]

36H[5:0] 35H[7:0] 34H[7:0] according to the equation:

audio frequency

crystal frequency

× 2²³

The SAA7108E; SAA7109E incorporates the generation of

a field-locked audio clock, as an auxiliary function for video

capture. An audio sample clock, that is locked to the field

frequency, ensures that there is always the same

predefined number of audio samples associated with a

field, or a set of fields. This ensures synchronous playback

of audio and video after digital recording (e.g. capture to

hard disk), MPEG or other compression or non-linear

editing.

ACNI[21:0] = round

--------------------------------------------

See Table 51 for examples.

Remark: For standard applications the synthesized audio

clock AMCLK can be used directly as master clock and as

input clock for port AMXCLK (short cut) to generate

ASCLK and ALRCLK. For high-end applications it is

recommended to use an external analog PLL circuit to

enhance the performance of the generated audio clock.

9.6.1

MASTER AUDIO CLOCK

The audio clock is synthesized from the same crystal

frequency as the line-locked video clock is generated. The

master audio clock is defined by the parameters:

• Audio master Clocks Per Field, ACPF[17:0] 32H[1:0]

31H[7:0] 30H[7:0] according to the equation:

audio frequency

field frequency

ACPF[17:0] = round

------------------------------------------

Table 51 Programming examples for audio master clock generation

CRYSTAL

FREQUENCY

(MHz)

ACPF

ACNI

FIELD

(Hz)

DECIMAL

HEX

DECIMAL

HEX

AMCLK = 256 × 48 kHz (12.288 MHz)

245760

3C000

3210190

30FBCE

32.11

59.94

205005

320CD

3210190

30FBCE

−

24.576

59.94

AMCLK = 256 × 44.1 kHz (11.2896 MHz)

225792

188348

225792

188348

37200

2DFBC

37200

2949362

3853517

2D00F2

3ACCCD

32.11

59.94

24.576

59.94

2DFBC

AMCLK = 256 × 32 kHz (8.192 MHz)

163840

136670

163840

136670

28000

215DE

28000

215DE

2140127

2796203

20A7DF

2AAAAB

32.11

59.94

24.576

59.94

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9.6.2

SIGNALS ASCLK AND ALRCLK

Two binary divided signals ASCLK and ALRCLK are provided for slower serial digital audio signal transmission and for

channel-select. The frequencies of these signals are defined by the parameters:

f_AMXCLK

• SDIV[5:0] 38H[5:0] according to the equation: f_ASCLK

SDIV[5:0] = ^AMXCLK– 1

-------------------------------------

-------------------

(SDIV + 1) × 2

2f_ASCLK

f_ASCLK

----------------------

2f_ALRCLK

• LRDIV[5:0] 39H[5:0] according to the equation: f_ALRCLK

LRDIV[5:0] =

--------------------------

LRDIV × 2

See Table 52 for examples.

Table 52 Programming examples for ASCLK/ALRCLK clock generation

SDIV

LRDIV

AMXCLK

(MHz)

ASCLK

(kHz)

ALRCLK

(kHz)

DECIMAL

HEX

DECIMAL

HEX

1536

768

12.288

11.2896

8.192

1411.2

2822.4

1024

44.1

2048

9.6.3

OTHER CONTROL SIGNALS

Further control signals are available to define reference clock edges and vertical references; see Table 53

Table 53 Control signals

CONTROL

DESCRIPTION

SIGNAL

APLL[3AH[3]] Audio PLL mode:

0: PLL closed

1: PLL open

AMVR[3AH[2]] Audio Master clock Vertical Reference:

0: internal vertical reference

1: external vertical reference

LRPH[3AH[1]] ALRCLK Phase:

0: invert ASCLK, ALRCLK edges triggered by falling edge of ASCLK

1: do not invert ASCLK, ALRCLK edges triggered by rising edge of ASCLK

SCPH[3AH[0]] ASCLK Phase:

0: invert AMXCLK, ASCLK edges triggered by falling edge of AMXCLK

1: do not invert AMXCLK, ASCLK edges triggered by rising edge of AMXCLK

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10 INPUT/OUTPUT INTERFACES AND PORTS OF

DIGITAL VIDEO DECODER PART

10.1 Analog terminals

The SAA7108E; SAA7109E has 6 analog inputs

AI21 to AI24, AI11 and AI12 (see Table 54) for composite

video CVBS or S-video Y/C signal pairs. Additionally, there

are two differential reference inputs, which must be

connected to ground via a capacitor equivalent to the

decoupling capacitors at the 6 inputs. There are no

peripheral components required other than the decoupling

capacitors and 18 Ω/56 Ω termination resistors, one set

per connected input signal (see also application example

in Fig.52). Two anti-alias filters are integrated, and self

adjusting via the clock frequency.

The SAA7108E; SAA7109E has 5 different I/O interfaces.

These are:

• Analog video input interface, for analog CVBS and/or

Y and C input signals

• Audio clock port

• Digital real-time signal port (RT port)

• Digital video expansion port (X port), for unscaled digital

video input and output

• Digital image port (I port) for scaled video data output

and programming

Clamp and gain control for the two ADCs are also

integrated. An analog video output pin (AOUT) is provided

for testing purposes.

• Digital host port (H port) for extension of the image port

or expansion port from 8 to 16-bit.

Table 54 Analog pin description

SYMBOL

I/O

DESCRIPTION

BIT

AI24 to AI21

P6, P7, P9

and P10

analog video signal inputs, e.g. 2 CVBS signals and MODE3 to MODE0

two Y/C pairs can be connected simultaneously

AI12 and AI11 P11 and P13

AOUT M10

analog video output, for test purposes

AOSL1 and AOSL0

AI1D and AI2D P12 and P8

analog reference pins for differential ADC operation

−

10.2 Audio clock signals

The SAA7108E; SAA7109E also synchronizes the audio clock and sampling rate to the video frame rate, via a very slow

PLL. This ensures that the multimedia capture and compression processes always gather the same predefined number

of samples per video frame.

An audio master clock AMCLK and two divided clocks, ASCLK and ALRCLK, are generated; see Table 55.

•

ASCLK: can be used as audio serial clock

• ALRCLK: audio left/right channel clock.

The ratios are programmable, see Section 9.6.

Table 55 Audio clock pin description

SYMBOL PIN I/O

DESCRIPTION

BIT

AMCLK

K12

audio master clock output

ACPF[17:0] 32H[1:0] 31H[7:0] 30H[7:0]

and ACNI[21:0] 36H[5:0] 35H[7:0]

34H[7:0]

AMXCLK J12

external audio master clock input for the clock

division circuit, can be directly connected to

output AMCLK for standard applications

−

ASCLK

K14

serial audio clock output, can be synchronized to SDIV[5:0] 38H[5:0] and SCPH[3AH[0]]

rising or falling edge of AMXCLK

ALRCLK J13

audio channel (left/right) clock output, can be

synchronized to rising or falling edge of ASCLK

LRDIV[5:0] 39H[5:0] and LRPH[3AH[1]]

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10.3 Clock and real-time synchronization signals

The Line-Locked Clock (LLC) is the double pixel clock at a

nominal 27 MHz. It is locked to the selected video input,

generating baseband video pixels according to “ITU

recommendation 601”. In order to support interfacing

circuits, a direct pixel clock LLC2 is also provided.

A crystal accurate frequency reference is required for the

generation of the line-locked video (pixel) clock LLC, and

the frame-locked audio serial bit clock. An oscillator is

built-in, for fundamental or 3rd-harmonic crystals. The

supported crystal frequencies are 32.11 or 24.576 MHz

(defined during reset by strapping pin ALRCLK).

The pins for line and field timing reference signals are

RTCO, RTS1 and RTS0. Various real-time status

information can be selected for the RTS pins. The signals

are always available (output) and reflect the

synchronization operation of the decoder part in the

SAA7108E; SAA7109E. The function of the RTS1 and

RTS0 pins can be defined by bits RTSE1[3:0] 12H[7:4] and

RTSE0[3:0] 12H[3:0]; see Table 56.

Alternatively pins XTALId and XTALIe can be driven from

an external single-ended oscillator.

The crystal oscillation can be propagated as clock to other

ICs in the system via pin XTOUTd.

Table 56 Clock and real-time synchronization signals

SYMBOL PIN

I/O

DESCRIPTION

BIT

Crystal oscillator

XTALId

input for crystal oscillator, or reference clock

output of crystal oscillator

−

XTALOd

XTOUTd

reference (crystal) clock output drive (optional)

XTOUTE[14H[3]]

Real-time signals (RT port)

LLC

M14

line-locked clock; nominal 27 MHz, double pixel clock locked to the

selected video input signal

−

LLC2

L14

L13

line-locked pixel clock; nominal 13.5 MHz

−

RTCO

real-time control output; transfers real-time status information

supporting RTC level 3.1 (see external document “RTC Functional

Description”, available on request)

RTS0

RTS1

K13

L10

real-time status information line 0; can be programmed to carry

various real-time informations; see Table 167

RTSE0[3:0] 12H[3:0]

RTSE1[3:0] 12H[7:4]

real-time status information line 1; can be programmed to carry

various real-time informations; see Table 168

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10.4 Video expansion port (X port)

As output, these are direct copies of the decoder signals.

The expansion port is intended for transporting video

streams of image data from other digital video circuits such

as MPEG encoder/decoder and video phone codec, to the

image port (I port); see Table 57.

The data transfers through the expansion port represent a

single D1 port, with half duplex mode. The SAV and EAV

codes may be inserted optionally for data input (controlled

by bit XCODE[92H[3]]). The input/output direction is

switched for complete fields only.

The expansion port consists of two groups of signals/pins:

• 8-bit data, I/O, regular video components Y-C_B-C_R

4 : 2 : 2, i.e. C_B-Y-C_R-Y, byte serial, exceptionally raw

video samples (e.g. ADC test). In input mode the data

bus can be extended to 16-bit by pins HPD7 to HPD0.

• Clock, synchronization and auxiliary signals,

accompanying the data stream, I/O.

Table 57 Signals dedicated to the expansion port

SYMBOL

I/O

DESCRIPTION

BIT

XPD7 to

XPD0

K2, K3,

L1 to L3,

M1, M2

and N1

I/O X port data: in output mode controlled by decoder OFTS[2:0] 13H[2:0], 91H[7:0]

section, for data format see Table 58; in input mode and C1H[7:0]

Y-C_B-C_R4 : 2 : 2 serial input data or luminance part

of a 16-bit Y-C_B-C_R4 : 2 : 2 input

XCLK

I/O clock at expansion port: if output, then copy of LLC; XCKS[92H[0]]

as input normally a double pixel clock of up to

32 MHz or a gated clock (clock gated with a

qualiﬁer)

XDQ

I/O data valid ﬂag of the expansion port input

(qualiﬁer): if output, then decoder (HREF and

VGATE) gate (see Fig.31)

−

XRDY

data request ﬂag = ready to receive, to work with

optional buffer in external device, to prevent internal

buffer overﬂow;

XRQT[83H[2]]

second function: input related task ﬂag A/B

XRH

XRV

XTRI

I/O horizontal reference signal for the X port: as output: XRHS[13H[6]], XFDH[92H[6]]

HREF or HS from the decoder (see Fig.31); as

input: a reference edge for horizontal input timing

and a polarity for input ﬁeld ID detection can be

deﬁned

and XDH[92H[2]]

I/O vertical reference signal for the X port: as output:

V123 or ﬁeld ID from the decoder,

XRVS[1:0] 13H[5:4],

XFDV[92H[7]] and XDV[1:0]

see Figs 29 and 30; as input: a reference edge for 92H[5:4]

vertical input timing and for input ﬁeld ID detection

can be deﬁned

port control: switches X port input to 3-state

XPE[1:0] 83H[1:0]

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10.4.1 X PORT CONFIGURED AS OUTPUT

• Raw samples (data types 0 to 5 and 7 to 14): C_B-C_R

samples are similar to data type 6, but CVBS samples

are transferred instead of processed luminance samples

within the Y time slots.

If the data output is enabled at the expansion port, then the

data stream from the decoder is present. The data format

of the 8-bit data bus is dependent on the chosen data type

which is selectable by the line control registers LCR2

to LCR24; see Table 33. In contrast to the image port, the

sliced data format is not available on the expansion port.

Instead, raw CVBS samples are always transferred if any

sliced data type is selected.

The amplitude and offset of the CVBS signal is

programmable via RAWG7 to RAWG0 and

RAWO7 to RAWO0, see Chapter 18,

Tables 174 and 175. For nominal levels see Fig.26.

The relationship of LCR programming to line numbers is

described in Section 9.2; see Tables 34 to 37.

Details of some of the data types on the expansion port are

as follows:

The data type selections by LCR are overruled by setting

OFTS2 = 1 (subaddress 13H bit 2). This setting is mainly

intended for device production testing. The VPO-bus

carries the upper or lower 8 bits of the two ADCs

depending on the OFTS[1:0] 13H[1:0] settings; see

Table 169. The output configuration is done via

MODE[3:0] 02H[3:0] settings; see Table 151. If a Y/C

mode is selected, the expansion port carries the

multiplexed output signals of both ADCs, in CVBS mode

the output of only one ADC. No timing reference codes are

generated in this mode.

• Active video: (data type 15) contains components

Y-C_B-C_R4 : 2 : 2 signal, 720 active pixels per line. The

amplitude and offsets are programmable via

DBRI7 to DBRI0, DCON7 to DCON0,

DSAT7 to DSAT0, OFFU1, OFFU0, OFFV1 and

OFFV0. For nominal levels see Fig.25.

• Test line: (data type 6) is similar to the active video

format, with some constraints within the data

processing:

– adaptive chrominance comb filter, vertical filter

(chrominance comb filter for NTSC standards, PAL

phase error correction) within the chrominance

processing are disabled

Remark: The LSBs (bit 0) of the ADCs are also available

on pin RTS0; see Table 167.

The SAV/EAV timing reference codes define the start and

end of valid data regions. The ITU-blanking code

sequence ‘- 80 - 10 - 80 - 10 -...’ is transmitted during the

horizontal blanking period, between EAV and SAV.

– adaptive luminance comb filter, peaking and

chrominance trap are bypassed within the luminance

processing.

This data type is defined for future enhancements. It can

be activated for lines containing standard test signals

within the vertical blanking period. Currently most

sources do not contain test lines. For nominal levels

see Fig.25.

The position of the F bit is constant according to ITU 656;

see Tables 60 and 61.

The V bit can be generated in two different ways (see

Tables 60 and 61) controlled via OFTS1 and OFTS0; see

Table 169.

F and V bits change synchronously with the EAV code.

Table 58 Data format on the expansion port

TIMING

REFERENCE

CODE (HEX)⁽¹⁾

TIMING

BLANKING

REFERENCE

PERIOD

BLANKING

PERIOD

720 PIXELS Y-C_B-C_R4 : 2 : 2 DATA⁽²⁾

CODE (HEX)⁽¹⁾

... 80 10 FF 00 00 SAV C_B0 Y0 C_R0 Y1 C_B2 Y2 ... C_R718 Y719 FF 00 00 EAV 80 10 ...

Notes

1. The generation of the timing reference codes can be suppressed by setting OFTS[2:0] to ‘010’; see Table 169. In

this event the code sequence is replaced by the standard ‘- 80 - 10 -’ blanking values.

2. If raw samples or sliced data are selected by the line control registers (LCR2 to LCR24), the Y samples are replaced

by CVBS samples.

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Table 59 SAV/EAV format on expansion port XPD7 to XPD0

BIT 6

(F)

BIT 5

(V)

BIT 4

(H)

BIT 3 BIT 2 BIT 1 BIT 0

(P3) (P2) (P1) (P0)

BIT 7

ﬁeld bit

vertical blanking bit

VBI: V = 1

format

reserved; evaluation not

recommended (protection

bits according to ITU 656)

1st field: F = 0

2nd field: F = 1

H = 0 in SAV format

H = 1 in EAV format

active video: V = 0

for vertical timing see Tables 60 and 61

Table 60 525 lines/60 Hz vertical timing

LINE NUMBER

F (ITU 656)

OFTS[2:0] = 000 (ITU 656)

OFTS[2:0] = 001

1 to 3

4 to 19

according to selected VGATE position type via

VSTA and VSTO (subaddresses 15H to 17H);

see Tables 171 to 173

22 to 261

262

263

264 and 265

266 to 282

283

284

285 to 524

525

Table 61 625 lines/50 Hz vertical timing

LINE NUMBER

F (ITU 656)

OFTS[2:0] = 000 (ITU 656)

OFTS[1:0] = 10

1 to 22

according to selected VGATE position type via

VSTA and VSTO (subaddresses 15H to 17H);

see Tables 171 to 173

24 to 309

310

311 and 312

313 to 335

336

337 to 622

623

624 and 625

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10.4.2 X PORT CONFIGURED AS INPUT

The data formats at the image port are defined in Dwords

of 32 bits (4 bytes), such as the related FIFO structures.

However, the physical data stream at the image port is

only 16-bit or 8-bit wide; in 16-bit mode data pins HPD7

to HPD0 are used for chrominance data. The four bytes of

the Dwords are serialized in words or bytes.

If data input mode is selected at the expansion port, then

the scaler can choose its input data stream from the

on-chip video decoder, or from the expansion port

(controlled by bit SCSRC[1:0] 91H[5:4]). Byte serial

Y-C_B-C_R4 : 2 : 2, or subsets for other sampling schemes,

or raw samples from an external ADC may be input (see

also bits FSC[2:0] 91H[2:0]). The input data stream must

be accompanied by an external clock XCLK, qualifier XDQ

and reference signals XRH and XRV. Instead of the

reference signal, embedded SAV and EAV codes,

according to ITU 656, can also be accepted. The

protection bits are not evaluated.

The available formats are as follows:

• Y-C_B-C_R4 : 2 : 2

• Y-C_B-C_R4 : 1 : 1

• Raw samples

• Decoded VBI data.

For handshaking with the receiving VGA controller, or

other memory or bus interface circuitry, F, H and V

reference signals and programmable FIFO flags are

provided. The information is provided on pins IGP0, IGP1,

IGPH and IGPV. The function on these pins is controlled

via subaddresses 84H and 85H.

XRH and XRV carry the horizontal and vertical

synchronization signals for the digital video stream

through the expansion port. The field ID of the input video

stream is carried in the phase (edge) of XRV and state of

XRH, or directly as FS (frame sync, odd/even signal) on

the XRV pin (controlled by XFDV[92H[7]], XFDH[92H[6]]

and XDV[1:0] 92H[5:4]).

VBI data is collected over an entire line in its own FIFO and

transferred as an uninterrupted block of bytes. Decoded

VBI data can be signed by the VBI flag on pins IGP0 and

IGP1.

The trigger events on XRH (rising/falling edge) and XRV

(rising/falling both edges) for the scalers acquisition

window are defined by XDV[1:0] 92H[5:4] and

Because scaled video data and decoded VBI data may

come from different and asynchronous sources, an

arbitration scheme is needed. Normally the VBI data slicer

has priority.

XDH[92H[2]]. The signal polarity of the qualifier can also

be defined by bit XDQ[92H[1]]. As an alternative to the

qualifier, the input clock can be applied to a gated clock

(clock gated with a data qualifier, controlled by bit

XCKS[92H[0]]). In this event, all input data will be qualified.

The image port consists of the pins and/or signals, as

given in Table 62.

10.5 Image port (I port)

For pin constrained applications, or interfaces, the relevant

timing and data reference signals can also be encoded into

the data stream. Therefore the corresponding pins do not

need to be connected. The minimum image port

configuration requires 9 pins only, i.e. 8 pins for data

including codes, and 1 pin for clock or gated clock. The

inserted codes are defined in close relationship to the

ITU-R BT.656 (D1) recommendation, where possible.

The image port transfers data from the scaler as well as

from the VBI data slicer, if selected (maximum 33 MHz).

The reference clock is available at the ICLK pin as an

output or as an input (maximum 33 MHz). As an output,

the ICLK is derived from the line-locked decoder or

expansion port input clock. The data stream from the

scaler output is normally discontinuous. Therefore valid

data during a clock cycle is accompanied by a data

qualifying (data valid) flag on pin IDQ. For pin constrained

applications the IDQ pin can be programmed to function as

a gated clock output (bit ICKS2[80H[2]]).

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

The following deviations from “ITU 656 recommendation”

are implemented at the SAA7108E; SAA7109E image port

interface:

• VBI raw sample streams are enveloped with SAV and

EAV, like normal video

• Decoded VBI data is transported as Ancillary (ANC)

• SAV and EAV codes are only present in those lines,

where data is to be transferred, i.e. active video lines, or

VBI raw samples, no codes for empty lines

data, two modes:

– direct decoded VBI data bytes (8-bit) are directly

placed in the ANC data field, 00H and FFH codes

may appear in the data block (violation to

ITU-R BT.656)

• There may be more or less than 720 pixels between

SAV and EAV

• The data content and number of clock cycles during

horizontal and vertical blanking is undefined, and may

be not constant

– recoded VBI data bytes (8-bit) directly placed in ANC

data field, 00H and FFH codes will be recoded to

even parity codes 03H and FCH to suppress invalid

ITU-R BT.656 codes.

• The data stream may be interleaved with not-valid data

codes, 00H, but SAV and EAV 4-byte codes are not

interleaved with not-valid data codes

There are no empty cycles in the ancillary code or its data

field. The data codes 00H and FFH are suppressed

(changed to 01H or FEH respectively) in the active video

stream, as well as in the VBI raw sample stream (VBI

pass-through). As an option the number range can be

limited further.

• There may be an irregular pattern of not-valid data, or

IDQ, and as a result, ‘C_B- Y - C_R- Y -’ is not in a fixed

phase to a regular clock divider

Table 62 Signals dedicated to the image port

SYMBOL

I/O

DESCRIPTION

BIT

IPD7 to

IPD0

E14, D14,

C14, B14,

I/O I port data

ICODE[93H[7]], ISWP[1:0] 85H[7:6]

and IPE[1:0] 87H[1:0]

E13, D13,

C13 and B13

ICLK

IDQ

H12

H14

G12

I/O continuous reference clock at image port,

can be input or output, as output decoder

LLC or XCLK from X port

ICKS[1:0] 80H[1:0] and IPE[1:0]

87H[1:0]

data valid ﬂag at image port, qualiﬁer, with ICKS2[80H[2]], IDQP[85H[0]] and

programmable polarity;

secondary function: gated clock

IPE[1:0] 87H[1:0]

IGPH

horizontal reference output signal, copy of IDH[1:0] 84H[1:0], IRHP[85H[1]] and

the horizontal gate signal of the scaler, with IPE[1:0] 87H[1:0]

programmable polarity;

alternative function: HRESET pulse

IGPV

F13

vertical reference output signal, copy of the IDV[1:0] 84H[3:2], IRVP[85H[2]] and

vertical gate signal of the scaler, with

programmable polarity;

IPE[1:0] 87H[1:0]

alternative function: VRESET pulse

IGP1

IGP0

G13

F14

general purpose output signal for I port

IDG12[86H[4]], IDG1[1:0] 84H[5:4],

IG1P[85H[3]] and IPE[1:0] 87H[1:0]

general purpose output signal for I port

IDG02[86H[5]], IDG0[1:0] 84H[7:6],

IG0P[85H[4]] and IPE[1:0] 87H[1:0]

ITRDY

ITRI

J14

target ready input signals

−

G14

port control, switches I port into 3-state

IPE[1:0] 87H[1:0]

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

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SAA7108E; SAA7109E

10.6 Host port for 16-bit extension of video data I/O (H port)

The H port, pins HPD, can be used to extend the data I/O paths to 16-bit.

The I port has functional priority. If I8_16[93H[6]] is set to logic 1 the output drivers of the H port are enabled and are

dependent on the I port enable control. When I8_16 = 0, the HPD output is disabled.

Table 63 Signals dedicated to the host port

SYMBOL

A13, D12, C12, B12, I/O 16-bit extension for digital I/O

A12, C11, B11 and A11 (chrominance component)

I/O

DESCRIPTION

BIT

HPD7 to

HPD0

IPE[1:0] 87H[1:0], ITRI[8FH[6]] and

I8_16[93H[6]]

10.7 Basic input and output timing diagrams for the

I and X ports

10.7.2 X PORT INPUT TIMING

The input timing requirements at the X port are the same

as those for the I port output. However, the following

differences should be noted:

10.7.1 I PORT OUTPUT TIMING

The following diagrams (Figs 39 to 45) illustrate the output

timing via the I port. IGPH and IGPV are indicated as

logic 1 active gate signals. If reference pulses are

programmed, these pulses are generated on the rising

edge of the logic 1 active gates. Valid data is accompanied

by the output data qualifier on pin IDQ. In addition, invalid

cycles are marked with output code 00H.

• It is not necessary to mark invalid cycles with a 00H

code

• No constraints on the input qualifier (can be a random

pattern)

• XCLK may by a gated clock (XCLK AND external XDQ).

Remark: All timings illustrated are given for an

uninterrupted output stream (no handshake with the

external hardware).

The IDQ output pin may be defined to be a gated clock

output signal (ICLK AND internal IDQ).

ICLK

IDQ

[

]

IPD 7:0

SAV

IGPH

MHB550

Fig.39 Output timing at the I port for serial 8-bit data at start of a line (ICODE = 1).

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

ICLK

IDQ

[

]

IPD 7:0

IGPH

MHB551

Fig.40 Output timing at the I port for serial 8-bit data at start of a line (ICODE = 0).

ICLK

IDQ

[

]

IPD 7:0

EAV

IGPH

MHB552

Fig.41 Output timing at the I port for serial 8-bit data at end of a line (ICODE = 1).

100

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

ICLK

IDQ

[

]

IPD 7:0

IGPH

MHB553

Fig.42 Output timing at the I port for serial 8-bit data at end of a line (ICODE = 0).

ICLK

IDQ

[

]

IPD 7:0

n−1

[

HPD 7:0

SAV

EAV

IGPH

MHB554

Fig.43 Output timing for 16-bit data output via the I and H port with codes (ICODE = 1), timing is like 8-bit output,

but packages of 2 bytes per valid cycle.

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SAA7108E; SAA7109E

handbook, full pagewidth

IDQ

IGPH

IGPV

MHB555

Fig.44 Horizontal and vertical gate output timing.

handbook, full pagewidth

ICLK

IDQ

[

]

IPD 7:0

DID

SDID

[

HPD 7:0

SAV

EAV

sliced data

flag on IGP0

or IGP1

MHB733

Fig.45 Output timing for sliced VBI data in 8-bit serial output mode (dotted graphs for SAV/EAV mode).

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11 BOUNDARY SCAN TEST

The Boundary Scan Test (BST) functions BYPASS,

EXTEST, INTEST, SAMPLE, CLAMP and IDCODE are all

supported; see Table 64. Details about the JTAG

BST-TEST can be found in the specification “IEEE Std.

1149.1”. Two files containing the detailed Boundary Scan

Description Language (BSDL) of the SAA7108E;

SAA7109E are available on request.

The SAA7108E; SAA7109E has built-in logic and 2 times

5 dedicated pins to support boundary scan testing,

separately for the encoder and decoder part, which allows

board testing without special hardware (nails). The

SAA7108E; SAA7109E follows the “IEEE Std. 1149.1 -

Standard Test Access Port and Boundary-Scan

Architecture” set by the Joint Test Action Group (JTAG)

chaired by Philips.

The 10 special pins are Test Mode Select (TMSe and

TMSd), Test Clock (TCKe and TCKd), Test Reset

(TRSTe and TRSTd), Test Data Input (TDIe and TDId)

and Test Data Output (TDOe and TDOd), where extension

‘e’ refers to the encoder part and extension ‘d’ refers to the

decoder part.

Table 64 BST instructions supported by the SAA7108E; SAA7109E

INSTRUCTION

DESCRIPTION

BYPASS

This mandatory instruction provides a minimum length serial path (1 bit) between TDIe (or TDId)

and TDOe (or TDOd) when no test operation of the component is required.

EXTEST

SAMPLE

This mandatory instruction allows testing of off-chip circuitry and board level interconnections.

This mandatory instruction can be used to take a sample of the inputs during normal operation of

the component. It can also be used to preload data values into the latched outputs of the boundary

scan register.

CLAMP

This optional instruction is useful for testing when not all ICs have BST. This instruction addresses

the bypass register while the boundary scan register is in external test mode.

IDCODE

This optional instruction will provide information on the components manufacturer, part number and

version number.

INTEST

USER1

This optional instruction allows testing of the internal logic (no support for customers available).

This private instruction allows testing by the manufacturer (no support for customers available).

11.1 Initialization of boundary scan circuit

is the possibility to check for the correct ICs mounted after

production and to determine the version number of the ICs

during field service.

The Test Access Port (TAP) controller of an IC should be

in the reset state (TEST_LOGIC_RESET) when the IC is

in functional mode. This reset state also forces the

instruction register into a functional instruction such as

IDCODE or BYPASS.

When the IDCODE instruction is loaded into the BST

instruction register, the identification register will be

connected between TDIe (or TDId) and TDOe (or TDOd)

of the IC. The identification register will load a component

specific code during the CAPTURE_DATA_REGISTER

state of the TAP controller, this code can subsequently be

shifted out. At board level this code can be used to verify

component manufacturer, type and version number. The

device identification register contains 32 bits, numbered

31 to 0, where bit 31 is the most significant bit (nearest to

TDIe or TDId) and bit 0 is the least significant bit (nearest

to TDOe or TDOd); see Fig.46.

To solve the power-up reset, the standard specifies that

the TAP controller will be forced asynchronously to the

TEST_LOGIC_RESET state by setting the TRSTe or

TRSTd pin LOW.

11.2 Device identiﬁcation codes

A device identification register is specified in “IEEE Std.

1149.1b-1994”. It is a 32-bit register which contains fields

for the specification of the IC manufacturer, the IC part

number and the IC version number. Its biggest advantage

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PC-CODEC

SAA7108E; SAA7109E

MSB

LSB

handbook, full pagewidth

28 27

12 11

0111000100000010

(0111000100010100)

TDIe

(or TDId)

TDOe

(or TDOd)

nnnn

00000010101

SAA7108E

4-bit

version

code

16-bit part number

11-bit manufacturer

identification

MSB

LSB

28 27

12 11

0111000100000011

(0111000100010100)

TDIe

(or TDId)

TDOe

(or TDOd)

nnnn

00000010101

SAA7109E

4-bit

version

code

16-bit part number

11-bit manufacturer

identification

MHC165

Fig.46 32 bits of identification code.

12 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134); all ground pins connected together and

grounded (0 V); all supply pins connected together.

SYMBOL

V_DDD

V_DDA

V_i(A)

PARAMETER

digital supply voltage

CONDITIONS

MIN.

−0.5

MAX.

+4.6

UNIT

analog supply voltage

−0.5

+4.6

input voltage at analog inputs

+4.6

V_i(n)

input voltage at pins XTALI, SDA and SCL

input voltage at digital inputs or I/O pins

V_DDD+ 0.5

+4.6

V_i(D)

outputs in 3-state

outputs in 3-state;

note 1

+5.5

∆V_SS

T_stg

voltage difference between V_SSA(n)and V_SSD(n)

storage temperature

−

100

°C

−65

+150

T_amb

V_esd

ambient temperature

electrostatic discharge voltage

human body model;

note 2

−

±2000

machine model;

note 3

−

±150

Notes

1. Condition for maximum voltage at digital inputs or I/O pins: 3.0 V < V_DDD< 3.6 V.

2. Class 2 according to EIA/JESD22-114-B.

3. Class A according to EIA/JESD22-115-A.

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13 THERMAL CHARACTERISTICS

SYMBOL

PARAMETER

thermal resistance from junction to ambient

CONDITIONS

in free air

VALUE

UNIT

R_th(j-a)

32⁽¹⁾

K/W

Note

1. The overall R_th(j-a)value can vary depending on the board layout. To minimize the effective R_th(j-a)all power and

ground pins must be connected to the power and ground layers directly. An ample copper area direct under the

SAA7108E; SAA7109E with a number of through-hole plating, which connect to the ground layer (four-layer board:

second layer), can also reduce the effective R_th(j-a). Please do not use any solder-stop varnish under the chip. In

addition the usage of soldering glue with a high thermal conductance after curing is recommended.

14 CHARACTERISTICS OF THE DIGITAL VIDEO ENCODER PART

V_DDD= 3.0 to 3.6 V; T_amb= 0 to 70 °C (typical values measured at T_amb= 25 °C); unless otherwise speciﬁed.

SYMBOL

Supplies

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

V_DDA

V_DDD

I_DDA

analog supply voltage

digital supply voltage

analog supply current

digital supply current

3.15

3.3

3.45

3.0

3.3

107

3.6

120

note 1

I_DDD

note 2

Inputs

V_IL

LOW-level input voltage at all digital

input pins except pins SDAe

and SCLe

−0.5

−

+0.8

V_IH

HIGH-level input voltage at all

digital input pins except pins SDAe

and SCLe

2.0

V_DDD+ 0.3

I_LI

C_i

input leakage current

input capacitance

−

µA

clocks

data

I/Os at high-impedance −

Outputs; all digital output pins except pin SDAe

V_OL

V_OH

LOW-level output voltage

HIGH-level output voltage

I_OL= 2 mA

−

0.4

I_OH= −2 mA

2.4

−

I²C-bus; pins SDAe and SCLe

V_IL

V_IH

I_i

LOW-level input voltage

HIGH-level input voltage

input current

−0.5

0.7V_DDD

−10

−

0.3V_DDD

V_DDD+ 0.3

+10

V_i= LOW or HIGH

I_OL= 3 mA

µA

V_OL

LOW-level output voltage

(pin SDAe)

−

0.4

I_o

output current

during acknowledge

−

Clock timing; pins PIXCLKI and PIXCLKO

T_PIXCLK

t_d(CLKD)

cycle time

note 3

note 4

22.5

−

100

delay from PIXCLKO to PIXCLKI

−

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SYMBOL

PARAMETER

CONDITIONS

note 3

MIN.

TYP.

MAX.

UNIT

duty factor t_HIGH/T_PIXCLK

duty factor t_HIGH/T_CLKO2

rise time

output

note 3

−

t_r

t_f

fall time

−

Input timing

t_SU;DAT

t_HD;DAT

input data set-up time

input data hold time

−

Crystal oscillator

f_nom

nominal frequency

−

MHz

10⁻⁶

∆f/f_nom

permissible deviation of nominal

frequency

note 5

−50

−

+50

CRYSTAL SPECIFICATION

T_amb

C_L

ambient temperature

−

°C

Ω

load capacitance

−

R_S

C₁

series resistance

−

1.8

4.2

motional capacitance (typical)

parallel capacitance (typical)

1.2

2.8

1.5

3.5

C₀

Data and reference signal output timing

C_o(L)

t_o(h)

t_o(d)

output load capacitance

output hold time

−

output delay time

CVBS and RGB outputs

V_o(CVBS)(p-p)output voltage CVBS

(peak-to-peak value)

see Table 65

−

1.23

1.0

−

V_o(VBS)(p-p)output voltage VBS (S-video)

(peak-to-peak value)

V_o(C)(p-p)

output voltage C (S-video)

(peak-to-peak value)

0.89

0.7

V_o(RGB)(p-p)output voltage R, G, B

(peak-to-peak value)

∆V_o

inequality of output signal voltages

−

R_o(L)

output load resistance

−

37.5

−

Ω

B_DAC

output signal bandwidth of DACs

−3 dB

−

MHz

LSB

ILE_lf(DAC)

low frequency integral linearity error

of DACs

−

±3

DLE_lf(DAC)

low frequency differential linearity

error of DACs

−

±1

LSB

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SAA7108E; SAA7109E

Notes

1. Minimum value for I²C-bus bit DOWNA = 1.

2. Minimum value for I²C-bus bit DOWND = 1.

3. The data is for both input and output direction.

4. This parameter is arbitrary, if PIXCLKI is looped through the VGC.

5. If an internal oscillator is used, crystal deviation of nominal frequency is directly proportional to the deviation of

subcarrier frequency and line/field frequency.

15 CHARACTERISTICS OF THE DIGITAL VIDEO DECODER PART

V_DDD= 3.0 to 3.6 V; V_DDA= 3.1 to 3.5 V; T_amb= 0 to 70 °C (typical values measured at T_amb= 25 °C); timings and levels

refer to drawings and conditions illustrated in Fig.51; unless otherwise speciﬁed.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supplies

V_DDD

I_DDD

digital supply voltage

digital supply current

3.0

3.3

3.6

−

X port 3-state; 8-bit I port

−

P_D

power dissipation digital

part

300

−

V_DDA

I_DDA

analog supply voltage

analog supply current

3.15

3.3

3.45

AOSL1 and AOSL0 = 0

CVBS mode

−

Y/C mode

P_A

power dissipation analog

part

CVBS mode

150

240

450

540

Y/C mode

P_tot(A+D)

total power dissipation

analog and digital part

CVBS mode

Y/C mode

P_tot(A+D)(pd)

total power dissipation

analog and digital part in

power-down mode

CE pulled down to ground

P_tot(A+D)(ps)

total power dissipation

analog and digital part in

power-save mode

I²C-bus controlled via

address 88H = 0FH

−

Analog part

I_clamp

clamping current

V_I= 0.9 V DC

−

±8

−

µA

V_i(p-p)

input voltage

(peak-to-peak value)

for normal video levels

1 V (p-p), −3 dB

0.7

termination 27/47 Ω and

AC coupling required;

coupling capacitor = 22 nF

Z_i

C_i

input impedance

input capacitance

channel crosstalk

clamping current off

200

−

kΩ

−50

α_cs

f_i< 5 MHz

−

2004 Mar 16

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SAA7108E; SAA7109E

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

9-bit analog-to-digital converters

analog bandwidth

at −3 dB

−

MHz

deg

φ_diff

differential phase

(ampliﬁer plus anti-alias

ﬁlter bypassed)

G_diff

differential gain (ampliﬁer

plus anti-alias ﬁlter

bypassed)

−

f_clk(ADC)

ADC clock frequency

12.8

−

14.3

MHz

LSB

DLE_dc(d)

DC differential linearity

error

−

0.7

−

ILE_dc(i)

DC integral linearity error

−

LSB

Digital inputs

V_{IL(SDAd,SCLd)}LOW-level input voltage

pins SDAd and SCLd

−0.5

0.7V_DDD

−0.3

2.0

−

+0.3V_DDD

V_DDD+ 0.5

+0.8

V_{IH(SDAd,SCLd)}HIGH-level input voltage

pins SDAd and SCLd

V_IL(XTALId)

V_IH(XTALId)

V_IL(n)

LOW-level CMOS input

voltage pin XTALId

HIGH-level CMOS input

voltage pin XTALId

V_DDD+ 0.3

+0.8

LOW-level input voltage all

other inputs

−0.3

2.0

V_IH(n)

HIGH-level input voltage

all other inputs

5.5

I_LI

input leakage current

I/O leakage current

input capacitance

−

µA

I_LI/O

C_i

I/O at high-impedance

Digital outputs; note 1

V_OL(SDAd)

V_OL(clk)

V_OH(clk)

V_OL

LOW-level output voltage

pin SDAd

SDAd at 3 mA sink current

−

0.4

LOW-level output voltage

for clocks

−0.5

2.4

+0.6

HIGH-level output voltage

for clocks

V_DDD+ 0.5

0.4

LOW-level output voltage

all other digital outputs

V_OH

HIGH-level output voltage

all other digital outputs

2.4

V_DDD+ 0.5

Clock output timing (LLC and LLC2); note 2

C_L(LLC)

T_cy

output load capacitance

cycle time

−

pin LLC

pin LLC2

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SYMBOL

PARAMETER

CONDITIONS

C_L= 40 pF

MIN.

TYP.

MAX.

UNIT

duty factors for t_LLCH/t_LLC

and t_LLC2H/t_LLC2

−

t_r

t_f

rise time LLC and LLC2

fall time LLC and LLC2

0.2 V to V_DDD− 0.2 V

_DDD− 0.2 V to 0.2 V

−

t_d(LLC-LLC2)

delay time between LLC

and LLC2 output

measured at 1.5 V;

C_L= 25 pF

−4

Horizontal PLL

f_H(nom)

nominal line frequency

50 Hz ﬁeld

60 Hz ﬁeld

−

15625

15734

−

∆f_H/f_H(n)

permissible static deviation

5.7

Subcarrier PLL

f_sc(nom)

nominal subcarrier

frequency

PAL BGHI

NTSC M

PAL M

−

4433619

3579545

3575612

3582056

−

PAL N

∆f_sc

lock-in range

±400

Crystal oscillator for 32.11 MHz; note 3

f_xtal(nom)

nominal frequency

3rd-harmonic

−

32.11

−

MHz

∆f_xtal(nom)

permissible nominal

frequency deviation

−

±70 × 10⁻⁶

∆f_xtal(nom)(T)

permissible nominal

frequency deviation with

temperature

−

±30 × 10⁻⁶

CRYSTAL SPECIFICATION (X1)

T_amb(X1)

C_L

ambient temperature

−

°C

Ω

load capacitance

−

R_s

series resonance resistor

motional capacitance

parallel capacitance

−

C₁

1.5 ±20%

4.3 ±20%

C₀

−

Crystal oscillator for 24.576 MHz; note 3

f_xtal(nom)

nominal frequency

3rd-harmonic

−

24.576

−

MHz

∆f_xtal(nom)

permissible nominal

frequency deviation

−

±50 × 10⁻⁶

∆f_xtal(nom)(T)

permissible nominal

frequency deviation with

temperature

−

±20 × 10⁻⁶

CRYSTAL SPECIFICATION (X1)

T_amb(X1)

C_L

ambient temperature

−

°C

Ω

load capacitance

−

R_s

series resonance resistor

motional capacitance

−

C₁

1.5 ±20%

2004 Mar 16

109

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

SYMBOL

C₀

Clock input timing (XCLK)

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

parallel capacitance

−

3.5 ±20%

−

T_cy

cycle time

−

duty factors for t_LLCH/t_LLC

rise time

−

t_r

t_f

fall time

−

Data and control signal input timing X port, related to XCLK input

t_SU;DAT

t_HD;DAT

input data set-up time

input data hold time

−

Clock output timing

C_L

T_cy

output load capacitance

−

cycle time

duty factors for

t_XCLKH/t_XCLKL

t_r

t_f

rise time

fall time

0.6 to 2.6 V

2.6 to 0.6 V

−

Data and control signal output timing X port, related to XCLK output (for XPCK[1:0] 83H[5:4] = 00 is default);

note 2

C_L

output load capacitance

output hold time

−

t_OHD;DAT

t_PD

C_L= 15 pF

propagation delay from

positive edge of XCLK

output

−

Control signal output timing RT port, related to LLC output

C_L

output load capacitance

output hold time

−

t_OHD;DAT

t_PD

C_L= 15 pF

propagation delay from

positive edge of LLC

output

−

ICLK output timing

C_L

T_cy

output load capacitance

−

cycle time

duty factors for t_ICLKH/t_ICLKL

rise time

t_r

0.6 to 2.6 V

2.6 to 0.6 V

t_f

fall time

−

Data and control signal output timing I port, related to ICLK output (for IPCK[1:0] 87H[5:4] = 00 is default)

C_L

output load capacitance at

all outputs

−

t_OHD;DAT

output data hold time

C_L= 15 pF

−

2004 Mar 16

110

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

SYMBOL

t_o(d)

ICLK input timing

PARAMETER

CONDITIONS

C_L= 15 pF

MIN.

TYP.

MAX.

UNIT

output delay time

−

T_cy

cycle time

−

100

Notes

1. The levels must be measured with load circuits; 1.2 kΩ at 3 V (TTL load); C_L= 50 pF.

2. The effects of rise and fall times are included in the calculation of t_OHD;DATand t_PD. Timings and levels refer to

drawings and conditions illustrated in Fig.51.

3. The crystal oscillator drive level is 0.28 mW (typ.).

16 TIMING

16.1 Digital video encoder part

PIXCLK

handbook, full pagewidth

HIGH

2.4 V

PIXCLKO

PIXCLKI

1.5 V

0.4 V

d(CLKD)

2.0 V

1.5 V

0.8 V

HD;DAT

SU;DAT

2.0 V

0.8 V

PDn

o(d)

o(h)

2.4 V

any output

0.4 V

MHB904

Fig.47 Input/output timing specification.

2004 Mar 16

111

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

handbook, full pagewidth

HSVGC

CBO

XOFS

IDEL

XPIX

HLEN

MHB905

Fig.48 Horizontal input timing.

handbook, full pagewidth

HSVGC

VSVGC

CBO

YOFS

YPIX

MHB906

Fig.49 Vertical input timing.

112

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

16.1.1 TELETEXT TIMING

Time t_i(TTXW)is the internally used insertion window for

TTX data; it has a constant length that allows insertion of

360 teletext bits at a text data rate of 6.9375 Mbits/s (PAL),

296 teletext bits at a text data rate of 5.7272 Mbits/s (world

standard TTX) or 288 teletext bits at a text data rate of

5.7272 Mbits/s (NABTS). The insertion window is not

opened if the control bit TTXEN is zero.

Time t_FDis the time needed to interpolate input data TTX

and insert it into the CVBS and VBS output signal, such

that it appears at t_TTX= 9.78 µs (PAL) or t_TTX= 10.5 µs

(NTSC) after the leading edge of the horizontal

synchronization pulse.

Time t_PDis the pipeline delay time introduced by the

source that is gated by TTXRQ_XCLKO2 in order to

deliver TTX data. This delay is programmable by register

TTXHD. For every active HIGH state at output pin

TTXRQ_XCLKO2, a new teletext bit must be provided by

the source.

Using appropriate programming, all suitable lines of the

odd field (TTXOVS and TTXOVE) plus all suitable lines of

the even field (TTXEVS and TTXEVE) can be used for

teletext insertion.

It is essential to note that the two pins used for teletext

insertion must be configured for this purpose by the

correct I²C-bus register settings.

Since the beginning of the pulses representing the TTXRQ

signal and the delay between the rising edge of TTXRQ

and valid teletext input data are fully programmable

(TTXHS and TTXHD), the TTX data is always inserted at

the correct position after the leading edge of the outgoing

horizontal synchronization pulse.

handbook, full pagewidth

CVBS/Y

TTX

i(TTXW)

text bit #:

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

TTX_SRES

TTXRQ_XCLKO2

MHB891

Fig.50 Teletext timing.

2004 Mar 16

113

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

16.2 Digital video decoder part

handbook, full pagewidth

XCLKH

2.4 V

1.5 V

0.6 V

clock input

XCLK

SU;DAT

HD;DAT

2.0 V

0.8 V

data and

control inputs

(X port)

not valid

SU;DAT

HD;DAT

2.0 V

0.8 V

input

XDQ

o(d)

OHD;DAT

−2.4 V

−0.6 V

data and

control outputs

X port, I port

X(I)CLKL

X(I)CLKH

−2.6 V

−1.5 V

−0.6 V

clock outputs

LLC, LLC2, XCLK, ICLK

and ICLK input

MHB735

Fig.51 Data input/output timing diagram (X port, RT port and I port).

114

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

17 APPLICATION INFORMATION

(ID11)

(IF11)

(IJ4)

(EL9)

(EL7)

handbook, full pagewidth

(EG11)

(ED10)

(IJ11)

(IL4)

(AM8)

(IL11)

(AM9)

(XL8)

(AN11)

R27 0 Ω

R28 0 Ω

SDA

SCL

L12

SDAd

SCLd

M11

[

]

XPD 0:7

XPD7

XPD6

XPD5

XPD4

XPD3

XPD2

XPD1

XPD0

32.11 MHz

DDP

24.576 MHz

DGND

XPD7

XPD6

XPD5

XPD4

XPD3

XPD2

XPD1

XPD0

JP43 fXTAL

'strapping'

R12

AUDIO2

4.7 kΩ

I²C-BUS_Adr:40H/42H

[

]

XPCON 0:5

XPCON5

XPCON4

XPCON3

XPCON2

XPCON1

XPCON0

DGND

XTRI

XRV

DDP

JP44

R13

RCON0

XRH

4.7 kΩ

XCLK

XDQ

'strapping'

XRDY

[

]

HPD 0:7

A13 HPD7

D12 HPD6

C12 HPD5

B12 HPD4

A12 HPD3

C11 HPD2

B11 HPD1

A11 HPD0

HPD7

HPD6

HPD5

HPD4

HPD3

HPD2

HPD1

HPD0

C100

R19

18 Ω

R17

18 Ω

R16

18 Ω

R18

18 Ω

AI24

AI23

AI22

AI21

AI24

AI23

AI22

AI21

47 nF

C97

[

]

IPD 0:7

E14 IPD7

D14 IPD6

C14 IPD5

B14 IPD4

E13 IPD3

D13 IPD2

C13 IPD1

B13 IPD0

IPD7

IPD6

IPD5

IPD4

IPD3

IPD2

IPD1

IPD0

47 nF

C98

47 nF

C99

P10

47 nF

C109

[

]

IPCON 0:7

AI2D

AI12

AI11

AI1D

G14 IPCON7

F13 IPCON6

G12 IPCON5

G13 IPCON4

F14 IPCON3

H12 IPCON2

H14 IPCON1

J14 IPCON0

SAA7108E

SAA7109E

47 nF

C101

ITRI

IGPV

IGPH

IGP1

IGP0

ICLK

IDQ

R15

18 Ω

R20

P11

P13

P12

AI12

AI11

47 nF

C102

18 Ω

47 nF

C110

R21

56 Ω

R22

56 Ω

R23

56 Ω

R24

56 Ω

R25

56 Ω

R26

56 Ω

ITRDY

[

]

AUDIO 0:3

J12 AUDIO3

J13 AUDIO2

K14 AUDIO1

K12 AUDIO0

47 nF

AMXCLK

ALRCLK

ASCLK

AGND

AMCLK

R29

M10

[

]

RCON 0:2

AOUT

L13 RCON0

K13 RCON1

L10 RCON2

0 Ω

RTCO

RTS0

RTS1

R37 33 Ω

R38 33 Ω

L14

LLC2

LLC

LLC2

LLC

M14

M12

N14

RES

R47

DDP

open

BSC0

BSC1

BSC2

TMSd

TCKd

TRSTd

TDId

JP45

CE_Dec.

(AM8)

[

]

BSC 0:2

(AM9)

TDI_D

TDO_D

DGND

(AN11)

TDOd

(EL9)

(EL7)

(EG11)

(ED10)

(ID11)

(IF11)

(IJ4)

TEST5

TEST4

TEST3

TEST2

TEST1

TEST0

TEST5

TEST4

TEST3

TEST2

TEST1

TEST0

C10

B10

H13

(IJ11)

(IL4)

XTOUTd

XTALOd

XTALId

XTOUT

(IL11)

(XL8)

24.576

MHz

L34

10 µH

C55 C53 C54

C52 C48 C51 C49 C50 C60 C56 C59 C57 C58 C61

100 100 100 100 100 100 100 100 100 100 100

C107

1 nF

C103

10 pF

C104

10 pF

100 100 100

L36

ferrite

R49

AGND

DGND

DXGND

open

AGND

DGND

DXGND

open

3PAD

0 Ω

AGND

DGND

AGND

MHB893

Fig.52 Application circuit (decoder part).

115

2004 Mar 16

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(AA10)

(AB6)

(AB9)

(EF4)

(ID4)

DGND

DDP

JP48

JP51

JP50

JP49

JP52

(XD6)

MSB

R54

HSVGC

(AC9)

(AD9)

DEMUX/PHASE

3.3 kΩ

DGND

DDP

LSB

R57

R33 0 Ω

R34 0 Ω

CBO

DEMUX/PHASE

SDA

SCL

3.3 kΩ

SDAe

SCLe

DGND

DDP

PAL/NTSC

R56

FSVGC

[

]

XPD 0:11

XPD11 C1

XPD10 C2

74LVC04

PD11

PD10

PD9

PD8

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

3.3 kΩ

XPD9

XPD8

XPD7

XPD6

XPD5

XPD4

XPD3

XPD2

XPD1

XPD0

[

]

DGND

FLTR 0:2

DDP

U7A

FLTR0

FLTR1

FLTR2

RGB444/YUV422

RED_CR_C

GREEN_VBS_CVBS

BLUE_CB_CVBS

R55

VSVGC

JP53

INV/NOT_INV

3.3 kΩ

DGND

DDP

MASTER/SLAVE

/Colour bar

TTXRQ_XCLKO2

R58

'strapping'

3.3 kΩ

SAA7108E

SAA7109E

HSVGC

VSVGC

FSVGC

CBO

HSVGC

VSVGC

FSVGC

CBO

HSM_CSYNC

VSM

HSM_CSYNC

VSM

TP94

TP95

TP96

TP93

U7B

74LVC04

TTX_SRES

TP99

TP10

TTXRQ_XCLKO2

RSET

DUMP

U7C

74LVC04

TP98

R39 33 Ω

PIXCLKO

PIXCLKI

CLKOUT

CLKIN

resistor

as close

as possible

to pin

U7D

74LVC04

TP10

R32 0 Ω

TP100

C111

JP46

TERMLLC

DGND

U7E

74LVC04

TP97

BSC0

BSC1

BSC2

R52

12 Ω

R53

1 kΩ

4.7 pF

TMSe

TCKe

TRSTe

TDIe

U7F

R51

DDP

240 Ω

74LVC04

[

]

BSC 0:2

TDOe

TDIe

AGND

TDOe

RESET

(AD9)

(AC9)

(AB9)

DDP

(EF4)

(ID4)

XTALOe

XTALIe

JP47

RESd

(XD6)

(AB6)

L35

10 µH

(AA10)

R14

4.7 kΩ

27 MHz

C37

100

U7G

DDP

C106

10 pF

C105

10 pF

C108

1 nF

C63 C64 C69 C67 C68

100 100 100 100 100

C66 C62 C65

100 100 100

74LVC04

CP1

22 µF

L38

ferrite

GND

(10 V)

RESe

R50

open

EXGND DGND

AGND

open

3PAD

0 Ω

AGND

DGND

AGND

DGND

EXGND

DGND

AGND

MHB894

DGND

Fig.53 Application circuit (encoder part).

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

handbook, full pagewidth

SAA7108E

SAA7109E

SAA7108E

SAA7109E

SAA7108E

SAA7109E

XTALOd

XTALId

XTALOd

XTALId

32.11 MHz

4.7 µH

1 nF

MHB960

(1a) With 3rd-harmonic quartz.

Crystal load = 8 pF.

(1b) With fundamental quartz.

Crystal load = 20 pF.

(1c) With fundamental quartz.

Crystal load = 8 pF

handbook, full pagewidth

SAA7108E

SAA7109E

SAA7108E

SAA7109E

SAA7108E

SAA7109E

XTALOd

XTALId

XTALOd

24.576 MHz

4.7 µH

1 nF

MHB961

(2a) With 3rd-harmonic quartz.

Crystal load = 8 pF.

(2b) With fundamental quartz.

Crystal load = 20 pF.

(2c) With fundamental quartz.

Crystal load = 8 pF.

SAA7108E

SAA7109E

SAA7108E

SAA7109E

XTALOd

XTALId

32.11 MHz or

24.576 MHz

n.c.

clock

MHB962

(3a) With direct clock.

(3b) With fundamental quartz and restricted drive level. When P_driveof the internal oscillator

is too high, a resistance R_scan be placed in series with the oscillator output XTALOd.

Note: The decreased crystal amplitude results in a lower drive level but on the other hand

the jitter performance will decrease.

Fig.54 Oscillator application for decoder part.

117

2004 Mar 16

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

handbook, full pagewidth

SAA7108E

SAA7109E

SAA7108E

SAA7109E

XTALOe

XTALIe

27.00 MHz

4.7 µH

1 nF

MHB964

(1a) With 3rd-harmonic quartz.

Crystal load = 8 pF.

(1b) With fundamental quartz.

Crystal load = 20 pF.

handbook, full pagewidth

SAA7108E

SAA7109E

SAA7108E

SAA7109E

XTALOe

XTALIe

XTALOe

27.00 MHz

n.c.

clock

MHB965

(2a) With direct clock.

(2b) With fundamental quartz and restricted drive level. When P_driveof the internal oscillator

is too high, a resistance R_scan be placed in series with the oscillator output XTALOe.

Note: The decreased crystal amplitude results in a lower drive level but on the other hand

the jitter performance will decrease.

Fig.55 Oscillator application for encoder part.

2004 Mar 16

118

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

17.1 Analog output voltages

By setting the reference currents of the DACs as shown in

Table 65, standard compliant amplitudes can be achieved

for all signal combinations; it is assumed that in

subaddress 16H, parameter DACF = 0000b, that means

the fine adjustment for all DACs in common is set to 0%.

The analog output voltages are dependent on the total

load (typical value 37.5 Ω), the digital gain parameters and

the I²C-bus settings of the DAC reference currents (analog

settings).

If S-video output is desired, the adjustment for the C

(chrominance subcarrier) output should be identical to the

one for VBS (luminance plus sync) output.

The digital output signals in front of the DACs under

nominal (nominal here stands for the settings given in

Tables 88 to 95 for example a standard PAL or NTSC

signal) conditions occupy different conversion ranges, as

indicated in Table 65 for a ¹⁰⁰

⁄₁₀₀colour bar signal.

Table 65 Digital output signals conversion range

SET/OUT

CVBS, SYNC TIP-TO-WHITE VBS, SYNC TIP-TO-WHITE

RGB, BLACK-TO-WHITE

Digital settings

Digital output

Analog settings

Analog output

see Tables 88 to 95

1014

see Tables 88 to 95

881

see Table 83

876

e.g. B DAC = 1FH

1.23 V (p-p)

e.g. G DAC = 1BH

1.00 V (p-p)

e.g. R DAC = G DAC = B DAC = 0BH

0.70 V (p-p)

17.2 Suggestions for a board layout

Place the analog coupling (clamp) capacitors close to the

analog input pins. Place the analog termination resistors

close to the coupling capacitors.

Use separate ground planes for analog and digital ground.

Connect these planes only at one point directly under the

device, by using a 0 Ω resistor directly at the supply stage.

Use separate supply lines for the analog and digital supply.

Place the supply decoupling capacitors close to the supply

pins.

Be careful of hidden layout capacitors around the crystal

application.

Use serial resistors in clock, sync and data lines, to avoid

clock or data reflection effects and to soften data energy.

Use L_bead(ferrite coil) in each digital supply line close to

the decoupling capacitors to minimize radiation energy

(EMC).

2004 Mar 16

119

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18 I²C-BUS DESCRIPTION

18.1 Digital video encoder part

Table 66 Slave receiver bit allocation map (slave address 88H)

SUB

ADDR.

(HEX)

(1)

Status byte (read only)

Null

01 to 15

VER2

(1)

VER1

(1)

VER0

(1)

CCRDO

CCRDE

FSEQ

(1)

O_E

(1)

Common DAC adjust ﬁne

R DAC adjust coarse

G DAC adjust coarse

B DAC adjust coarse

MSM threshold

DACF3

RDACC3

GDACC3

BDACC3

DACF2

RDACC2

GDACC2

BDACC2

MSMT2

RCOMP

CID2

DACF1

RDACC1

GDACC1

BDACC1

MSMT1

GCOMP

CID1

DACF0

RDACC0

GDACC0

BDACC0

MSMT0

BCOMP

CID0

RDACC4

GDACC4

BDACC4

MSMT7

MSM

MSMT6

MSMT5

MSMT4

MSMT3

(1)

Monitor sense mode

Chip ID (02B or 03B, read only)

Wide screen signal

Real-time control, burst start

Sync reset enable, burst end

Copy generation 0

Copy generation 1

CG enable, copy generation 2

Output port control

Null

CID7

CID6

CID5

WSS5

WSS13

BS5

CID4

WSS4

WSS12

BS4

CID3

WSS3

WSS11

BS3

WSS7

WSS6

(1)

WSS2

WSS10

BS2

WSS1

WSS9

BS1

WSS0

WSS8

BS0

WSSON

(1)

SRES

CG07

CG15

CGEN

BE5

BE4

BE3

BE2

BE1

BE0

CG06

CG05

CG04

CG03

CG11

CG19

CG02

CG01

CG00

CG14

(1)

CG13

(1)

CG12

(1)

CG10

CG09

CG08

2E to 37

CG18

CG17

(1)

CG16

(1)

VBSEN

CVBSEN1 CVBSEN0

CEN

(1)

ENCOFF

CLK2EN

(1)

Gain luminance for RGB

Gain colour difference for RGB

Input port control 1

VPS enable, input control 2

VPS byte 5

GY4

GY3

GY2

GY1

GY0

GCD4

GCD3

GCD2

GCD1

GCD0

CBENB

VPSEN

VPS57

SYMP

(1)

DEMOFF

CSYNC

Y2C

UV2C

(1)

EDGE2

VPS51

VPS111

VPS121

VPS131

VPS141

CHPS1

EDGE1

VPS50

VPS110

VPS120

VPS130

VPS140

CHPS0

VPS56

VPS116

VPS126

VPS136

VPS146

CHPS6

VPS55

VPS115

VPS125

VPS135

VPS145

CHPS5

VPS54

VPS114

VPS124

VPS134

VPS144

CHPS4

VPS53

VPS113

VPS123

VPS133

VPS143

CHPS3

VPS52

VPS112

VPS122

VPS132

VPS142

CHPS2

VPS byte 11

VPS117

VPS127

VPS137

VPS147

CHPS7

VPS byte 12

VPS byte 13

VPS byte 14

Chrominance phase

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SUB

Gain U

ADDR.

(HEX)

GAINU7

GAINV7

GAINU8

GAINV8

GAINU6

GAINU5

GAINV5

BLCKL5

BLNNL5

GAINU4

GAINV4

BLCKL4

BLNNL4

GAINU3

GAINV3

BLCKL3

BLNNL3

GAINU2

GAINV2

BLCKL2

BLNNL2

GAINU1

GAINV1

BLCKL1

BLNNL1

GAINU0

GAINV0

BLCKL0

BLNNL0

Gain V

GAINV6

(1)

Gain U MSB, black level

Gain V MSB, blanking level

CCR, blanking level VBI

Null

(1)

CCRS1

CCRS0

BLNVB5

BLNVB4

BLNVB3

BLNVB2

BLNVB1

BLNVB0

(1)

Standard control

Burst amplitude

Subcarrier 0

DOWND

DOWNA

BSTA6

FSC06

FSC14

FSC22

FSC30

L21O06

L21O16

L21E06

YGS

SCBW

BSTA2

FSC02

FSC10

FSC18

FSC26

L21O02

L21O12

L21E02

PAL

FISE

(1)

BSTA5

FSC05

FSC13

FSC21

FSC29

L21O05

L21O15

L21E05

BSTA4

FSC04

FSC12

FSC20

FSC28

L21O04

L21O14

L21E04

BSTA3

FSC03

FSC11

FSC19

FSC27

L21O03

L21O13

L21E03

BSTA1

FSC01

FSC09

FSC17

FSC25

L21O01

L21O11

L21E01

BSTA0

FSC00

FSC08

FSC16

FSC24

L21O00

L21O10

L21E00

FSC07

FSC15

FSC23

FSC31

L21O07

L21O17

L21E07

Subcarrier 1

Subcarrier 2

Subcarrier 3

Line 21 odd 0

Line 21 odd 1

Line 21 even 0

Line 21 even 1

Null

L21E17

L21E16

L21E15

L21E14

L21E13

L21E12

L21E11

L21E10

(1)

Trigger control

Multi control

HTRIG7

HTRIG6

HTRIG9

BLCKON

CCEN0

HTRIG5

HTRIG8

PHRES1

TTXEN

HTRIG4

VTRIG4

PHRES0

SCCLN4

HTRIG3

VTRIG3

LDEL1

HTRIG2

VTRIG2

LDEL0

HTRIG1

VTRIG1

FLC1

HTRIG0

VTRIG0

FLC0

HTRIG10

(1)

Closed Caption, teletext enable

CCEN1

SCCLN3

ADWHS3

SCCLN2

ADWHS2

SCCLN1

SCCLN0

Active display window horizontal

start

ADWHS7

ADWHS6 ADWHS5 ADWHS4

ADWHE6 ADWHE5 ADWHE4

ADWHE10 ADWHE9 ADWHE8

ADWHS1 ADWHS0

Active display window horizontal

end

ADWHE7

ADWHE3

ADWHE2

ADWHE1 ADWHE0

(1)

MSBs ADWH

ADWHS10 ADWHS9 ADWHS8

TTX request horizontal start

TTX request horizontal delay

CSYNC advance

TTXHS7

TTXHS6

TTXHS5

TTXHS4

TTXHS3

TTXHD3

TTXHS2

TTXHS1

TTXHS0

(1)

TTXHD2

TTXHD1

TTXHD0

(1)

CSYNCA4 CSYNCA3 CSYNCA2 CSYNCA1 CSYNCA0

TTX odd request vertical start

TTX odd request vertical end

TTX even request vertical start

TTXOVS7 TTXOVS6 TTXOVS5 TTXOVS4 TTXOVS3 TTXOVS2 TTXOVS1 TTXOVS0

TTXOVE7 TTXOVE6 TTXOVE5 TTXOVE4 TTXOVE3 TTXOVE2 TTXOVE1 TTXOVE0

TTXEVS7 TTXEVS6 TTXEVS5 TTXEVS4 TTXEVS3 TTXEVS2 TTXEVS1 TTXEVS0

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SUB

ADDR.

(HEX)

TTX even request vertical end

First active line

Last active line

TTX mode, MSB vertical

Null

TTXEVE7 TTXEVE6 TTXEVE5 TTXEVE4 TTXEVE3 TTXEVE2 TTXEVE1 TTXEVE0

FAL7

LAL7

FAL6

LAL6

FAL5

FAL4

LAL4

FAL3

LAL3

FAL2

LAL2

FAL1

LAL1

FAL0

LAL0

LAL5

(1)

TTX60

LAL8

FAL8

TTXEVE8 TTXOVE8 TTXEVS8 TTXOVS8

(1)

Disable TTX line

FIFO status (read only)

Pixel clock 0

LINE12

LINE11

LINE10

LINE9

LINE8

LINE7

LINE6

LINE14

OVFL

LINE5

LINE13

UDFL

LINE20

LINE19

LINE18

LINE17

LINE16

LINE15

(1)

PCL07

PCL15

PCL06

PCL14

PCL05

PCL13

PCL04

PCL12

PCL03

PCL11

PCL02

PCL10

PCL01

PCL09

PCL00

PCL08

Pixel clock 1

Pixel clock 2

PCL23

PCL22

PCL21

PCL20

PCL19

PCL18

PCL17

PCL16

(1)

Null

84 to 8F

Horizontal offset

Pixel number

XOFS7

XPIX7

YOFSO7

YOFSE7

YOFSE9

YPIX7

EFS

XOFS6

XPIX6

XOFS5

XPIX5

XOFS4

XPIX4

YOFSO4

YOFSE4

YOFSO8

YPIX4

ILC

XOFS3

XPIX3

YOFSO3

YOFSE3

XPIX9

YPIX3

YFIL

XOFS2

XPIX2

YOFSO2

YOFSE2

XPIX8

YPIX2

HSL

XOFS1

XPIX1

XOFS0

XPIX0

Vertical offset odd

Vertical offset even

MSBs

YOFSO6

YOFSE6

YOFSE8

YPIX6

YOFSO5

YOFSE5

YOFSO9

YPIX5

YOFSO1

YOFSE1

XOFS9

YPIX1

YOFSO0

YOFSE0

XOFS8

YPIX0

Line number

Scaler CTRL, MCB YPIX

Sync control

PCBN

SLAVE

OFS

YPIX9

YPIX8

HFS

VFS

PFS

OVS

PVS

OHS

PHS

Line length

HLEN7

IDEL3

HLEN6

IDEL2

HLEN5

IDEL1

HLEN4

IDEL0

XINC4

YINC4

YINC8

HLEN3

HLEN2

HLEN10

XINC2

YINC2

XINC10

HLEN1

HLEN9

XINC1

YINC1

XINC9

HLEN0

HLEN8

XINC0

YINC0

XINC8

(1)

Input delay, MSB line length

Horizontal increment

Vertical increment

XINC7

YINC7

YINC11

XINC6

YINC6

YINC10

XINC5

YINC5

YINC9

XINC3

YINC3

XINC11

MSBs vertical and horizontal

increment

Weighting factor odd

Weighting factor even

Weighting factor MSB

Vertical line skip

YIWGTO7 YIWGTO6 YIWGTO5 YIWGTO4 YIWGTO3 YIWGTO2 YIWGTO1 YIWGTO0

YIWGTE7 YIWGTE6 YIWGTE5 YIWGTE4 YIWGTE3 YIWGTE2 YIWGTE1 YIWGTE0

YIWGTE11 YIWGTE10 YIWGTE9 YIWGTE8 YIWGTO11 YIWGTO10 YIWGTO9 YIWGTO8

YSKIP7

BLEN

YSKIP6

YSKIP5

YSKIP4

YSKIP3

YSKIP2

YSKIP1

YSKIP9

YSKIP0

YSKIP8

(1)

Blank enable for NI-bypass,

vertical line skip MSB

YSKIP11

YSKIP10

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SUB

Border colour Y

ADDR.

(HEX)

BCY7

BCU7

BCY6

BCU6

BCY5

BCU5

BCY4

BCU4

BCV4

BCY3

BCU3

BCV3

BCY2

BCU2

BCY1

BCU1

BCY0

BCU0

Border colour U

Border colour V

BCV7

BCV6

BCV5

BCV2

BCV1

BCV0

Cursor colour 1 R

CC1R7

CC1G7

CC1B7

CC2R7

CC2G7

CC2B7

AUXR7

AUXG7

AUXB7

XCP7

CC1R6

CC1G6

CC1B6

CC2R6

CC2G6

CC2B6

AUXR6

AUXG6

AUXB6

XCP6

CC1R5

CC1G5

CC1B5

CC2R5

CC2G5

CC2B5

AUXR5

AUXG5

AUXB5

XCP5

CC1R4

CC1G4

CC1B4

CC2R4

CC2G4

CC2B4

AUXR4

AUXG4

AUXB4

XCP4

CC1R3

CC1G3

CC1B3

CC2R3

CC2G3

CC2B3

AUXR3

AUXG3

AUXB3

XCP3

CC1R2

CC1G2

CC1B2

CC2R2

CC2G2

CC2B2

AUXR2

AUXG2

AUXB2

XCP2

CC1R1

CC1G1

CC1B1

CC2R1

CC2G1

CC2B1

AUXR1

AUXG1

AUXB1

XCP1

CC1R0

CC1G0

CC1B0

CC2R0

CC2G0

CC2B0

AUXR0

AUXG0

AUXB0

XCP0

Cursor colour 1 G

Cursor colour 1 B

Cursor colour 2 R

Cursor colour 2 G

Cursor colour 2 B

Auxiliary cursor colour R

Auxiliary cursor colour G

Auxiliary cursor colour B

Horizontal cursor position

Horizontal hot spot, MSB XCP

Vertical cursor position

Vertical hot spot, MSB YCP

Input path control

XHS4

XHS3

XHS2

XHS1

XHS0

XCP10

XCP9

XCP8

YCP7

YCP6

YCP5

YCP4

YCP3

YCP2

(1)

YCP1

YCP0

YHS4

YHS3

YHS2

YHS1

YHS0

YCP9

YCP8

LUTOFF

CMODE

LUTL

IF2

IF1

IF0

MATOFF

DFOFF

Cursor bit map

RAM address (see Table 140)

RAM address (see Table 141)

Colour look-up table

Note

1. All unused control bits must be programmed with logic 0 to ensure compatibility to future enhancements.

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

18.1.1 I²C-BUS FORMAT

Table 67 I²C-bus write access to control registers; see Table 72

S 1 0 0 0 1 0 0 0 A SUBADDRESS

DATA 0

--------

DATA n

Table 68 I²C-bus write access to cursor bit map (subaddress FEH); see Table 72

S 1 0 0 0 1 0 0 0 A FEH RAM ADDRESS DATA 0

Table 69 I²C-bus write access to colour look-up table (subaddress FFH); see Table 72

S 1 0 0 0 1 0 0 0 A FFH RAM ADDRESS DATA 0R DATA 0G

DATA 0B

--------

Table 70 I²C-bus read access to control registers; see Table 72

S 1 0 0 0 1 0 0 0 A SUBADDRESS Sr 1 0 0 0 1 0 0 1

DATA 0 Am -------- DATA n Am

Table 71 I²C-bus read access to cursor bit map or colour LUT; see Table 72

S 1 0 0 0 1 0 0 0 A FEH A RAM ADDRESS A Sr 1 0 0 0 1 0 0 1 A DATA 0 Am -------- DATA n Am P

FFH

Table 72 Explanations of Tables 67 to 71

CODE

DESCRIPTION

START condition

repeated START condition

slave address

1 0 0 0 1 0 0 X; note 1

acknowledge generated by the slave

acknowledge generated by the master

subaddress byte

SUBADDRESS; note 2

DATA

data byte

--------

continued data bytes and acknowledges

STOP condition

RAM ADDRESS

start address for RAM access

Notes

1. X is the read/write control bit; X = logic 0 is order to write; X = logic 1 is order to read.

2. If more than 1 byte of DATA is transmitted, then auto-increment of the subaddress is performed.

2004 Mar 16

124

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

18.1.2 SLAVE RECEIVER

Table 73 Subaddress 16H

DATA BYTE

DESCRIPTION

DACF

output level adjustment ﬁne in 1% steps for all DACs; default after reset is 00H; see Table 74

Table 74 Fine adjustment of DAC output voltage

BINARY

GAIN (%)

0111

0110

0101

0100

0011

0010

0001

0000

1000

1001

1010

1011

1100

1101

1110

1111

−1

−2

−3

−4

−5

−6

−7

Table 75 Subaddresses 17H to 19H

DATA BYTE

DESCRIPTION

RDACC

GDACC

BDACC

output level coarse adjustment for RED DAC; default after reset is 1BH for output of C signal

00000b ≡ 0.585 V to 11111b ≡ 1.240 V at 37.5 Ω nominal for full-scale conversion

output level coarse adjustment for GREEN DAC; default after reset is 1BH for output of VBS signal

00000b ≡ 0.585 V to 11111b ≡ 1.240 V at 37.5 Ω nominal for full-scale conversion

output level coarse adjustment for BLUE DAC; default after reset is 1FH for output of CVBS signal

00000b ≡ 0.585 V to 11111b ≡ 1.240 V at 37.5 Ω nominal for full-scale conversion

Table 76 Subaddress 1AH

DATA BYTE

DESCRIPTION

monitor sense mode threshold for DAC output voltage, should be set to 70

MSMT

2004 Mar 16

125

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

Table 77 Subaddress 1BH

LOGIC

DATA BYTE

DESCRIPTION

LEVEL

MSM

monitor sense mode off; RCOMP, GCOMP and BCOMP bits are not valid; default after reset

monitor sense mode on

RCOMP

(read only)

check comparator at DAC on pin C8 is active, output is loaded

check comparator at DAC on pin C8 is inactive, output is not loaded

check comparator at DAC on pin C7 is active, output is loaded

check comparator at DAC on pin C7 is inactive, output is not loaded

check comparator at DAC on pin C6 is active, output is loaded

check comparator at DAC on pin C6 is inactive, output is not loaded

GCOMP

(read only)

BCOMP

(read only)

Table 78 Subaddresses 26H and 27H

LOGIC

DATA BYTE

DESCRIPTION

LEVEL

WSS

−

wide screen signalling bits

3 to 0 = aspect ratio

7 to 4 = enhanced services

10 to 8 = subtitles

13 to 11 = reserved

WSSON

wide screen signalling output is disabled; default after reset

wide screen signalling output is enabled

Table 79 Subaddress 28H

LOGIC

DATA BYTE

DESCRIPTION

REMARKS

LEVEL

−

starting point of burst in clock cycles

PAL: BS = 33 (21H); default after reset if

strapping pin G1 tied HIGH

NTSC: BS = 25 (19H); default after reset if

strapping pin G1 tied LOW

Table 80 Subaddress 29H

LOGIC

DATA BYTE

DESCRIPTION

REMARKS

LEVEL

SRES

pin C3 accepts a teletext bit stream (TTX) default after reset

pin C3 accepts a sync reset input (SRES) a HIGH impulse resets synchronization of the

encoder (ﬁrst ﬁeld, ﬁrst line)

−

ending point of burst in clock cycles

PAL: BE = 29 (1DH); default after reset if

strapping pin G1 tied HIGH

NTSC: BE = 29 (1DH); default after reset if

strapping pin G1 tied LOW

2004 Mar 16

126

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

Table 81 Subaddresses 2AH to 2CH

LOGIC

DATA BYTE

DESCRIPTION

LEVEL

−

LSB of the respective bytes are encoded immediately after run-in, the MSBs of the

respective bytes have to carry the CRCC bits, in accordance with the deﬁnition of copy

generation management system encoding format.

CGEN

copy generation data output is disabled; default after reset

copy generation data output is enabled

Table 82 Subaddress 2DH

LOGIC

DATA BYTE

DESCRIPTION

LEVEL

VBSEN

pin C7 provides a component GREEN signal (CVBSEN1 = 0) or CVBS signal

(CVBSEN1 = 1)

pin C7 provides a luminance (VBS) signal; default after reset

pin C7 provides a component GREEN (G) or luminance (VBS) signal; default after reset

pin C7 provides a CVBS signal

CVBSEN1

CVBSEN0

CEN

pin C6 provides a component BLUE (B) or colour difference BLUE (C_B) signal

pin C6 provides a CVBS signal; default after reset

pin C8 provides a component RED (R) or colour difference RED (C_R) signal

pin C8 provides a chrominance signal (C) as modulated subcarrier for S-video; default after

reset

ENCOFF

CLK2EN

encoder is active; default after reset

encoder bypass, DACs are provided with RGB signal after cursor insertion block

pin C4 provides a teletext request signal (TTXRQ)

pin C4 provides the buffered crystal clock divided by two (13.5 MHz); default after reset

Table 83 Subaddresses 38H and 39H

DATA BYTE

DESCRIPTION

GY4 to GY0

Gain luminance of RGB (C_R, Yand C_B) output, ranging from (1 − ¹⁶⁄₃₂) to (1 + ¹⁵⁄₃₂).

Suggested nominal value = 0, depending on external application.

GCD4 to GCD0

Gain colour difference of RGB (C_R, Yand C_B) output, ranging from (1 − ¹⁶⁄₃₂) to (1 + ¹⁵⁄₃₂).

Suggested nominal value = 0, depending on external application.

2004 Mar 16

127

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

Table 84 Subaddress 3AH

LOGIC

DATA BYTE

DESCRIPTION

LEVEL

CBENB

SYMP

data from input ports is encoded

colour bar with ﬁxed colours is encoded

horizontal and vertical trigger is taken from FSVGC or both VSVGC and HSVGC; default

after reset

horizontal and vertical trigger is decoded out of “ITU-R BT.656” compatible data at PD port

Y-C_B-C_Rto RGB dematrix is active; default after reset

DEMOFF

CSYNC

Y2C

Y-C_B-C_Rto RGB dematrix is bypassed

pin D8 provides a horizontal sync for non-interlaced VGA components output (at PIXCLK)

pin D8 provides a composite sync for interlaced components output (at XTAL clock)

input luminance data is twos complement from PD input port

input luminance data is straight binary from PD input port; default after reset

input colour difference data is twos complement from PD input port

input colour difference data is straight binary from PD input port; default after reset

UV2C

Table 85 Subaddress 54H

LOGIC

DATA BYTE

DESCRIPTION

LEVEL

VPSEN

EDGE2

video programming system data insertion is disabled; default after reset

video programming system data insertion in line 16 is enabled

internal PPD2 data is sampled on the rising clock edge

internal PPD2 data is sampled on the falling clock edge; see Tables 25 to 30; default after

reset

EDGE1

internal PPD1 data is sampled on the rising clock edge; see Tables 25 to 30; default after

reset

internal PPD1 data is sampled on the falling clock edge

Table 86 Subaddresses 55H to 59H

DATA BYTE

DESCRIPTION

REMARKS

VPS5

ﬁfth byte of video programming system data

eleventh byte of video programming system data

twelfth byte of video programming system data

thirteenth byte of video programming system data

fourteenth byte of video programming system data

in line 16; LSB ﬁrst; all other bytes are not

relevant for VPS

VPS11

VPS12

VPS13

VPS14

2004 Mar 16

128

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

Table 87 Subaddress 5AH; note 1

DATA BYTE

DESCRIPTION

VALUE

6BH

RESULT

CHPS

phase of encoded colour subcarrier

(including burst) relative to horizontal

sync; can be adjusted in steps of

360/256 degrees

PAL B/G and data from input ports in master mode

PAL B/G and data from look-up table

16H

25H

NTSC M and data from input ports in master mode

NTSC M and data from look-up table

46H

Note

1. The default after reset is 00H.

Table 88 Subaddresses 5BH and 5DH

DATA BYTE

DESCRIPTION

CONDITIONS

REMARKS

GAINU

variable gain for

C_Bsignal; input

representation in

accordance with

“ITU-R BT.601”

white-to-black = 92.5 IRE GAINU = −2.17 × nominal to +2.16 × nominal

GAINU = 0

output subcarrier of U contribution = 0

GAINU = 118 (76H)

output subcarrier of U contribution = nominal

white-to-black = 100 IRE GAINU = −2.05 × nominal to +2.04 × nominal

GAINU = 0

output subcarrier of U contribution = 0

GAINU = 125 (7DH)

output subcarrier of U contribution = nominal

Table 89 Subaddresses 5CH and 5EH

DATA BYTE

DESCRIPTION

CONDITIONS

REMARKS

GAINV

variable gain for

C_Rsignal; input

representation in

accordance with

“ITU-R BT.601”

white-to-black = 92.5 IRE GAINV = −1.55 × nominal to +1.55 × nominal

GAINV = 0

output subcarrier of V contribution = 0

GAINV = 165 (A5H)

output subcarrier of V contribution = nominal

white-to-black = 100 IRE GAINV = −1.46 × nominal to +1.46 × nominal

GAINV = 0

output subcarrier of V contribution = 0

GAINV = 175 (AFH)

output subcarrier of V contribution = nominal

Table 90 Subaddress 5DH

DATA BYTE

DESCRIPTION

variable black level;

CONDITIONS

REMARKS

BLCKL

white-to-sync = 140 IRE; recommended value: BLCKL = 58 (3AH)

input representation note 1

in accordance with

BLCKL = 0; note 1

output black level = 29 IRE

“ITU-R BT.601”

BLCKL = 63 (3FH); note 1 output black level = 49 IRE

white-to-sync = 143 IRE; recommended value: BLCKL = 51 (33H)

note 2

BLCKL = 0; note 2

output black level = 27 IRE

BLCKL = 63 (3FH); note 2 output black level = 47 IRE

Notes

1. Output black level/IRE = BLCKL × 2/6.29 + 28.9.

2. Output black level/IRE = BLCKL × 2/6.18 + 26.5.

2004 Mar 16

129

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

Table 91 Subaddress 5EH

DATA BYTE

DESCRIPTION

variable blanking level

CONDITIONS

REMARKS

BLNNL

white-to-sync = 140 IRE;

note 1

recommended value: BLNNL = 46 (2EH)

BLNNL = 0; note 1

output blanking level = 25 IRE

BLNNL = 63 (3FH); note 1 output blanking level = 45 IRE

white-to-sync = 143 IRE;

note 2

recommended value: BLNNL = 53 (35H)

BLNNL = 0; note 2

output blanking level = 26 IRE

BLNNL = 63 (3FH); note 2 output blanking level = 46 IRE

Notes

1. Output black level/IRE = BLNNL × 2/6.29 + 25.4.

2. Output black level/IRE = BLNNL × 2/6.18 + 25.9; default after reset: 35H.

Table 92 Subaddress 5FH

DATA BYTE

CCRS

DESCRIPTION

select cross-colour reduction ﬁlter in luminance; see Table 93

BLNVB

variable blanking level during vertical blanking interval is typically identical to value of BLNNL

Table 93 Logic levels and function of CCRS

CCRS1

CCRS0

DESCRIPTION

no cross-colour reduction; for overall transfer characteristic of luminance see Fig.7

cross-colour reduction #1 active; for overall transfer characteristic see Fig.7

cross-colour reduction #2 active; for overall transfer characteristic see Fig.7

cross-colour reduction #3 active; for overall transfer characteristic see Fig.7

Table 94 Subaddress 61H

LOGIC

DATA BYTE

DESCRIPTION

LEVEL

DOWND

DOWNA

YGS

digital core in normal operational mode; default after reset

digital core in sleep mode and is reactivated with an I²C-bus address

DACs in normal operational mode; default after reset

DACs in Power-down mode

luminance gain for white − black 100 IRE

luminance gain for white − black 92.5 IRE including 7.5 IRE set-up of black

SCBW

enlarged bandwidth for chrominance encoding (for overall transfer characteristic of

chrominance in baseband representation see Figs 5 and 6)

standard bandwidth for chrominance encoding (for overall transfer characteristic of

chrominance in baseband representation see Figs 5 and 6); default after reset

PAL

NTSC encoding (non-alternating V component)

PAL encoding (alternating V component)

864 total pixel clocks per line

FISE

858 total pixel clocks per line

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130

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

Table 95 Subaddress 62H

DATA BYTE

DESCRIPTION

CONDITIONS

REMARKS

BSTA

amplitude of colour burst; white-to-black = 92.5 IRE;

recommended value:

BSTA = 63 (3FH)

input representation in

accordance with

“ITU-R BT.601”

burst = 40 IRE; NTSC encoding

BSTA = 0 to 2.02 × nominal

white-to-black = 92.5 IRE;

recommended value:

BSTA = 45 (2DH)

burst = 40 IRE; PAL encoding

BSTA = 0 to 2.82 × nominal

white-to-black = 100 IRE;

burst = 43 IRE; NTSC encoding

recommended value:

BSTA = 67 (43H)

BSTA = 0 to 1.90 × nominal

white-to-black = 100 IRE;

burst = 43 IRE; PAL encoding

recommended value:

BSTA = 47 (2FH); default after

reset

BSTA = 0 to 3.02 × nominal

Table 96 Subaddresses 63H to 66H (four bytes to program subcarrier frequency)

DATA BYTE

DESCRIPTION

CONDITIONS

REMARKS

FSC0 to

FSC3

_fsc= subcarrier frequency

FSC3 = most signiﬁcant byte;

FSC0 = least signiﬁcant byte

FSC = round ^fsc× 2³²; note 1

-------

(in multiples of line

frequency); f_llc= clock

frequency (in multiples of

line frequency)

f_llc

Note

1. Examples:

a) NTSC M: f_fsc= 227.5, f_llc= 1716 → FSC = 569408543 (21F07C1FH).

b) PAL B/G: f_fsc= 283.7516, f_llc= 1728 → FSC = 705268427 (2A098ACBH).

Table 97 Subaddresses 67H to 6AH

DATA BYTE

DESCRIPTION

REMARKS

L21O0

L21O1

L21E0

L21E1

ﬁrst byte of captioning data, odd ﬁeld

second byte of captioning data, odd ﬁeld

ﬁrst byte of extended data, even ﬁeld

second byte of extended data, even ﬁeld

LSBs of the respective bytes are encoded

immediately after run-in and framing code, the

MSBs of the respective bytes have to carry the

parity bit, in accordance with the deﬁnition of

line 21 encoding format.

Table 98 Subaddresses 6CH and 6DH

DATA BYTE

DESCRIPTION

HTRIG

sets the horizontal trigger phase related to chip-internal horizontal input

values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed; increasing HTRIG decreases

delays of all internally generated timing signals; the default value is 0

2004 Mar 16

131

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

Table 99 Subaddress 6DH

DATA BYTE

DESCRIPTION

sets the vertical trigger phase related to chip-internal vertical input

VTRIG

increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines;

variation range of VTRIG = 0 to 31 (1FH); the default value is 0

Table 100 Subaddress 6EH

LOGIC

DATA BYTE

DESCRIPTION

LEVEL

BLCKON

−

encoder in normal operation mode; default after reset

output signal is forced to blanking level

PHRES

LDEL

selects the phase reset mode of the colour subcarrier generator; see Table 101

selects the delay on luminance path with reference to chrominance path;

see Table 102

FLC

−

ﬁeld length control; see Table 103

Table 101 Logic levels and function of PHRES

DATA BYTE

DESCRIPTION

PHRES1

PHRES0

no subcarrier reset

subcarrier reset every two lines

subcarrier reset every eight ﬁelds

subcarrier reset every four ﬁelds

Table 102 Logic levels and function of LDEL

DATA BYTE

DESCRIPTION

no luminance delay; default after reset

LDEL1

LDEL0

1 LLC luminance delay

2 LLC luminance delay

3 LLC luminance delay

Table 103 Logic levels and function of FLC

DATA BYTE

DESCRIPTION

FLC1

FLC0

interlaced 312.5 lines/ﬁeld at 50 Hz, 262.5 lines/ﬁeld at 60 Hz; default after reset

non-interlaced 312 lines/ﬁeld at 50 Hz, 262 lines/ﬁeld at 60 Hz

non-interlaced 313 lines/ﬁeld at 50 Hz, 263 lines/ﬁeld at 60 Hz

2004 Mar 16

132

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

Table 104 Subaddress 6FH

DATA

BYTE

LOGIC

LEVEL

DESCRIPTION

CCEN

−

enables individual line 21 encoding; see Table 105

disables teletext insertion; default after reset

enables teletext insertion

TTXEN

SCCLN

selects the actual line, where Closed Caption or extended data are encoded;

line = (SCCLN + 4) for M-systems; line = (SCCLN + 1) for other systems

Table 105 Logic levels and function of CCEN

DATA BYTE

DESCRIPTION

CCEN1

CCEN0

line 21 encoding off; default after reset

enables encoding in ﬁeld 1 (odd)

enables encoding in ﬁeld 2 (even)

enables encoding in both ﬁelds

Table 106 Subaddresses 70H to 72H

DATA BYTE

DESCRIPTION

ADWHS

active display window horizontal start; deﬁnes the start of the active TV display portion after

the border colour

values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed

ADWHE

active display window horizontal end; deﬁnes the end of the active TV display portion before

the border colour

values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed

Table 107 Subaddress 73H

DATA BYTE

DESCRIPTION

REMARKS

TTXHS

start of signal TTXRQ on pin TTXRQ_XCLKO2

(CLK2EN = 0); see Fig.50

TTXHS = 42H; is default after

reset if strapped to PAL

TTXHS = 54H; is default after

reset if strapped to NTSC

Table 108 Subaddress 74H

DATA BYTE

DESCRIPTION

REMARKS

TTXHD

indicates the delay in clock cycles between rising edge minimum value: TTXHD = 2; is

of TTXRQ output signal on pin TTXRQ_XCLKO2

(CLK2EN = 0) and valid data at pin TTX_SRES

default after reset

Table 109 Subaddress 75H

DATA BYTE

DESCRIPTION

advanced composite sync against RGB output from 0 XTAL clocks to 31 XTAL clocks

CSYNCA

2004 Mar 16

133

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

Table 110 Subaddresses 76H, 77H and 7CH

DATA BYTE

DESCRIPTION

REMARKS

TTXOVS

ﬁrst line of occurrence of signal TTXRQ on pin TTXRQ_XCLKO2 TTXOVS = 05H; is default after

(CLK2EN = 0) in odd ﬁeld

reset if strapped to PAL

TTXOVS = 06H; is default after

reset if strapped to NTSC

line = (TTXOVS + 4) for M-systems

line = (TTXOVS + 1) for other systems

TTXOVE

last line of occurrence of signal TTXRQ on pin TTXRQ_XCLKO2 TTXOVE = 16H; is default after

(CLK2EN = 0) in odd ﬁeld

reset if strapped to PAL

TTXOVE = 10H; is default after

reset if strapped to NTSC

line = (TTXOVE + 3) for M-systems

line = TTXOVE for other systems

Table 111 Subaddresses 78H, 79H and 7CH

DATA BYTE

DESCRIPTION

REMARKS

TTXEVS

ﬁrst line of occurrence of signal TTXRQ on pin TTXRQ_XCLKO2 TTXEVS = 04H; is default after

(CLK2EN = 0) in even ﬁeld

reset if strapped to PAL

TTXEVS = 05H; is default after

reset if strapped to NTSC

line = (TTXEVS + 4) for M-systems

line = (TTXEVS + 1) for other systems

TTXEVE

last line of occurrence of signal TTXRQ on pin TTXRQ_XCLKO2 TTXEVE = 16H; is default after

(CLK2EN = 0) in even ﬁeld

reset if strapped to PAL

TTXEVE = 10H; is default after

reset if strapped to NTSC

line = (TTXEVE + 3) for M-systems

line = TTXEVE for other systems

Table 112 Subaddresses 7AH to 7CH

DATA BYTE

DESCRIPTION

FAL

ﬁrst active line = FAL + 4 for M-systems and FAL + 1 for other systems, measured in lines

FAL = 0 coincides with the first field synchronization pulse

LAL

last active line = LAL + 3 for M-systems and LAL for other system, measured in lines

LAL = 0 coincides with the first field synchronization pulse

Table 113 Subaddress 7CH

LOGIC

DATA BYTE

DESCRIPTION

LEVEL

TTX60

enables NABTS (FISE = 1) or European TTX (FISE = 0); default after reset

enables world standard teletext 60 Hz (FISE = 1)

Table 114 Subaddresses 7EH and 7FH

DATA BYTE

DESCRIPTION

LINE

individual lines in both ﬁelds (PAL counting) can be disabled for insertion of teletext by the respective

bits, disabled line = LINExx (50 Hz ﬁeld rate)

this bit mask is effective only if the lines are enabled by TTXOVS/TTXOVE and TTXEVS/TTXEVE

2004 Mar 16

134

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

Table 115 Subaddresses 81H to 83H

DATA BYTE

DESCRIPTION

PCL

deﬁnes the frequency of the synthesized pixel clock PIXCLKO;

PCL

f_PIXCLK

× f

× 8 ; f_XTAL= 27 MHz nominal, e.g. 640 × 480 to NTSC M: PCL = 20F63BH;

XTAL

-----------

2²⁴

640 × 480 to PAL B/G: PCL = 1B5A73H (as by strapping pins)

Table 116 Subaddresses 90H and 94H

DATA BYTE

DESCRIPTION

XOFS

horizontal offset; deﬁnes the number of PIXCLKs from horizontal sync (HSVGC) output to composite

blanking (CBO) output

Table 117 Subaddresses 91H and 94H

DATA BYTE

DESCRIPTION

XPIX

pixel in X direction; deﬁnes half the number of active pixels per input line (identical to the length of

CBO pulses)

Table 118 Subaddresses 92H and 94H

DATA BYTE

DESCRIPTION

YOFSO

vertical offset in odd ﬁeld; deﬁnes (in the odd ﬁeld) the number of lines from VSVGC to ﬁrst line with

active CBO; if no LUT data is requested, the ﬁrst active CBO will be output at YOFSO + 2; usually,

YOFSO = YOFSE with the exception of extreme vertical downscaling and interlacing

Table 119 Subaddresses 93H and 94H

DATA BYTE

DESCRIPTION

YOFSE

vertical offset in even ﬁeld; deﬁnes (in the even ﬁeld) the number of lines from VSVGC to ﬁrst line with

active CBO; if no LUT data is requested, the ﬁrst active CBO will be output at YOFSE + 2; usually,

YOFSE = YOFSO with the exception of extreme vertical downscaling and interlacing

Table 120 Subaddresses 95H and 96H

DATA BYTE

DESCRIPTION

YPIX

deﬁnes the number of requested input lines from the feeding device;

number of requested lines = YPIX + YOFSE − YOFSO

Table 121 Subaddress 96H

LOGIC

DATA BYTE

DESCRIPTION

LEVEL

EFS

frame sync signal at pin FSVGC ignored in slave mode

frame sync signal at pin FSVGC accepted in slave mode

normal polarity of CBO signal (HIGH during active video)

inverted polarity of CBO signal (LOW during active video)

the SAA7108E; SAA7109E is timing master to the graphics controller

the SAA7108E; SAA7109E is timing slave to the graphics controller

PCBN

SLAVE

2004 Mar 16

135

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

LOGIC

LEVEL

DATA BYTE

DESCRIPTION

ILC

if hardware cursor insertion is active, set LOW for non-interlaced input signals

if hardware cursor insertion is active, set HIGH for interlaced input signals

luminance sharpness booster disabled

YFIL

HSL

luminance sharpness booster enabled

normal trigger event handling of the horizontal state machine, if the SAA7108E;

SAA7109E is slave to HSVGC input

trigger event for horizontal state machine is shifted 128 PIXCLKs in advance, adapted

to a late HSVGC in slave mode

Table 122 Subaddress 97H

LOGIC

DATA BYTE

DESCRIPTION

LEVEL

HFS

horizontal sync is directly derived from input signal (slave mode) at pin HSVGC

horizontal sync is derived from a frame sync signal (slave mode) at pin FSVGC (only if

EFS is set HIGH)

VFS

vertical sync (ﬁeld sync) is directly derived from input signal (slave mode) at

pin VSVGC

vertical sync (ﬁeld sync) is derived from a frame sync signal (slave mode) at

pin FSVGC (only if EFS is set HIGH)

OFS

PFS

pin FSVGC is switched to input

pin FSVGC is switched to active output

polarity of signal at pin FSVGC in output mode (master mode) is active HIGH; rising

edge of the input signal is used in slave mode

polarity of signal at pin FSVGC in output mode (master mode) is active LOW; falling

edge of the input signal is used in slave mode

OVS

PVS

pin VSVGC is switched to input

pin VSVGC is switched to active output

polarity of signal at pin VSVGC in output mode (master mode) is active HIGH; rising

edge of the input signal is used in slave mode

polarity of signal at pin VSVGC in output mode (master mode) is active LOW; falling

edge of the input signal is used in slave mode

OHS

PHS

pin HSVGC is switched to input

pin HSVGC is switched to active output

polarity of signal at pin HSVGC in output mode (master mode) is active HIGH; rising

edge of the input signal is used in slave mode

polarity of signal at pin HSVGC in output mode (master mode) is active LOW; falling

edge of the input signal is used in slave mode

Table 123 Subaddresses 98H and 99H

DATA BYTE

DESCRIPTION

HLEN

number of PIXCLKs

horizontal length; HLEN =

– 1

----------------------------------------------------

line

2004 Mar 16

136

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

Table 124 Subaddress 99H

DATA BYTE

DESCRIPTION

IDEL

input delay; deﬁnes the distance in PIXCLKs between the active edge of CBO and the ﬁrst received

valid pixel

Table 125 Subaddresses 9AH and 9CH

DATA BYTE

DESCRIPTION

XINC

number of output pixels

--------------------------------------------------------------

line

incremental fraction of the horizontal scaling engine; XINC =

× 4096

--------------------------------------------------------------

number of input pixels

----------------------------------------------------------

line

Table 126 Subaddresses 9BH and 9CH

DATA BYTE

DESCRIPTION

YINC

number of active output lines

----------------------------------------------------------------------------

number of active input lines

incremental fraction of the vertical scaling engine; YINC =

× 4096

Table 127 Subaddresses 9DH and 9FH

DATA BYTE

DESCRIPTION

weighting factor for the ﬁrst line of the odd ﬁeld; YIWGTO =

YIWGTO

YINC

+ 2048

-------------

Table 128 Subaddresses 9EH and 9FH

DATA BYTE

DESCRIPTION

YIWGTE

YINC – YSKIP

-------------------------------------

weighting factor for the ﬁrst line of the even ﬁeld; YIWGTE =

Table 129 Subaddresses A0H and A1H

DATA BYTE

DESCRIPTION

YSKIP

vertical line skip; deﬁnes the effectiveness of the anti-ﬂicker ﬁlter; YSKIP = 0: most effective;

YSKIP = 4095: anti-ﬂicker ﬁlter switched off

Table 130 Subaddress A1H

LOGIC

DATA BYTE

DESCRIPTION

LEVEL

BLEN

no internal blanking for non-interlaced graphics in bypass mode; default after reset

forced internal blanking for non-interlaced graphics in bypass mode

Table 131 Subaddresses A2H to A4H

DATA BYTE

DESCRIPTION

luminance and colour difference portion of border colour in underscan area

BCY, BCU

and BCV

2004 Mar 16

137

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

Table 132 Subaddresses F0H to F2H

DATA BYTE

DESCRIPTION

CC1R, CC1G RED, GREEN and BLUE portion of ﬁrst cursor colour

and CC1B

Table 133 Subaddresses F3H to F5H

DATA BYTE

DESCRIPTION

CC2R, CC2G RED, GREEN and BLUE portion of second cursor colour

and CC2B

Table 134 Subaddresses F6H to F8H

DATA BYTE

DESCRIPTION

AUXR, AUXG RED, GREEN and BLUE portion of auxiliary cursor colour

and AUXB

Table 135 Subaddresses F9H and FAH

DATA BYTE

DESCRIPTION

XCP

horizontal cursor position

Table 136 Subaddress FAH

DATA BYTE

XHS

horizontal hot spot of cursor

Table 137 Subaddresses FBH and FCH

DATA BYTE

YCP

vertical cursor position

Table 138 Subaddress FCH

DATA BYTE

YHS

vertical hot spot of cursor

2004 Mar 16

138

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

Table 139 Subaddress FDH

LOGIC

DATA BYTE

DESCRIPTION

LEVEL

LUTOFF

CMODE

LUTL

colour look-up table is active

colour look-up table is bypassed

cursor mode; input colour will be inverted

auxiliary cursor colour will be inserted

LUT loading via input data stream is inactive

colour and cursor LUTs are loaded via input data stream

input format is 8 + 8 + 8 bit 4 : 4 : 4 non-interlaced RGB or C_B-Y-C_R

input format is 5 + 5 + 5 bit 4 : 4 : 4 non-interlaced RGB

input format is 5 + 6 + 5 bit 4 : 4 : 4 non-interlaced RGB

input format is 8 + 8 + 8 bit 4 : 2 : 2 non-interlaced C_B-Y-C_R

input format is 8 + 8 + 8 bit 4 : 2 : 2 interlaced C_B-Y-C_R(ITU-R BT.656, 27 MHz clock)

(in subaddresses 91H and 94H set XPIX = number of active pixels/line)

input format is 8-bit non-interlaced index colour

input format is 8 + 8 + 8 bit 4 : 4 : 4 non-interlaced RGB or C_B-Y-C_R(special bit ordering)

RGB to C_R-Y-C_Bmatrix is active

MATOFF

DFOFF

RGB to C_R-Y-C_Bmatrix is bypassed

down formatter (4 : 4 : 4 to 4 : 2 : 2) in input path is active

down formatter is bypassed

Table 140 Subaddress FEH

DATA BYTE

DESCRIPTION

CURSA

RAM start address for cursor bit map; the byte following subaddress FEH points to the ﬁrst cell to be

loaded with the next transmitted byte; succeeding cells are loaded by auto-incrementing until stop

condition

Table 141 Subaddress FFH

DATA BYTE

DESCRIPTION

COLSA

RAM start address for colour LUT; the byte following subaddress FFH points to the ﬁrst cell to be

loaded with the next transmitted byte; succeeding cells are loaded by auto-incrementing until stop

condition

In subaddresses 5BH, 5CH, 5DH, 5EH and 62H all IRE values are rounded up.

2004 Mar 16

139

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

18.1.3 SLAVE TRANSMITTER

Table 142 Slave transmitter (slave address 89H)

DATA BYTE

D4 D3

VER0 CCRDO CCRDE

FUNCTION

SUBADDRESS

Status byte

Chip ID

00H

1CH

80H

VER2

CID7

VER1

CID6

CID2

FSEQ

CID1

O_E

CID0

UDFL

CID5

CID4

CID3

FIFO status

OVFL

Table 143 Subaddress 00H

LOGIC

DATA BYTE

DESCRIPTION

LEVEL

VER

−

version identiﬁcation of the device: it will be changed with all versions of the IC that have

different programming models; current version is 010 binary

CCRDO

Closed Caption bytes of the odd ﬁeld have been encoded

the bit is reset after information has been written to the subaddresses 67H and 68H; it is

set immediately after the data has been encoded

CCRDE

Closed Caption bytes of the even ﬁeld have been encoded

the bit is reset after information has been written to the subaddresses 69H and 6AH; it is

set immediately after the data has been encoded

FSEQ

O_E

during ﬁrst ﬁeld of a sequence (repetition rate: NTSC = 4 ﬁelds, PAL = 8 ﬁelds)

not ﬁrst ﬁeld of a sequence

during even ﬁeld

during odd ﬁeld

Table 144 Subaddress 1CH

DATA BYTE

DESCRIPTION

CID

chip ID of SAA7108E = 02H; chip ID of SAA7109E = 03H

Table 145 Subaddress 80H

LOGIC

DATA BYTE

DESCRIPTION

LEVEL

OVFL

UDFL

no FIFO overﬂow

FIFO overﬂow has occurred; this bit is reset after this subaddress has been read

no FIFO underﬂow

FIFO underﬂow has occurred; this bit is reset after this subaddress has been read

2004 Mar 16

140

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

18.2 Digital video decoder part

18.2.1 I²C-BUS FORMAT

ACK-s

SLAVE ADDRESS W

SUBADDRESS

DATA

data transferred

(n bytes + acknowledge)

MHB339

a. Write procedure.

SLAVE ADDRESS W

SLAVE ADDRESS R

ACK-s

SUBADDRESS

ACK-s

DATA

ACK-m

data transferred

(n bytes + acknowledge)

MHB340

b. Read procedure (combined).

Fig.56 I²C-bus format.

Table 146 Description of I²C-bus format; note 1

CODE

DESCRIPTION

START condition

repeated START condition

SLAVE ADDRESS W ‘0100 0010’ (42H, default) or ‘0100 0000’ (40H; note 2)

SLAVE ADDRESS R ‘0100 0011’ (43H, default) or ‘0100 0001’ (41H; note 2)

ACK-s

acknowledge generated by the slave

acknowledge generated by the master

subaddress byte; see Tables 147 and 148

ACK-m

SUBADDRESS

DATA

data byte; see Table 148; if more than one byte DATA is transmitted the subaddress pointer is

automatically incremented

STOP condition

read/write control bit (LSB slave address); X = 0, order to write (the circuit is slave receiver);

X = 1, order to read (the circuit is slave transmitter)

Notes

1. The SAA7108E; SAA7109E supports the ‘fast mode’ I²C-bus specification extension (data rate up to 400 kbits/s).

2. If pin RTCO strapped to V_DDDvia a 3.3 kΩ resistor.

2004 Mar 16

141

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

Table 147 Subaddress description and access

SUBADDRESS

DESCRIPTION

ACCESS (READ/WRITE)

00H

chip version

reserved

read only

F0H to FFH

−

Video decoder: 01H to 2FH

01H to 05H

06H to 19H

1AH to 1EH

1FH

front-end part

read and write

decoder part

reserved

read and write

−

read only

−

video decoder status byte

reserved

20H to 2FH

Audio clock generation: 30H to 3FH

30H to 3AH

3BH to 3FH

audio clock generator

reserved

read and write

−

General purpose VBI data slicer: 40H to 7FH

40H to 5EH

5FH

VBI data slicer

reserved

read and write

−

read only

−

60H to 62H

63H to 7FH

VBI data slicer status

reserved

X port, I port and the scaler: 80H to EFH

80H to 8FH

90H to BFH

C0H to EFH

task independent global settings

read and write

task A deﬁnition

task B deﬁnition

2004 Mar 16

142

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Table 148 I²C-bus receiver/transmitter overview

SUB

ADDR.

(HEX)

Chip version: register 00H

Chip version (read only)

ID7

ID6

ID5

ID4

−

Video decoder: registers 01H to 2FH

FRONT-END PART: REGISTERS 01H TO 05H

(1)

Increment delay

IDEL3

MODE3

HOLDG

GAI13

IDEL2

MODE2

GAFIX

GAI12

GAI22

IDEL1

MODE1

GAI28

GAI11

GAI21

IDEL0

MODE0

GAI18

GAI10

GAI20

Analog input control 1

Analog input control 2

Analog input control 3

Analog input control 4

FUSE1

FUSE0

HLNRS

GAI16

GAI26

GUDL1

VBSL

GUDL0

WPOFF

GAI14

(1)

GAI17

GAI27

GAI15

GAI25

GAI24

GAI23

DECODER PART: REGISTERS 06H TO 2FH

Horizontal sync start

Horizontal sync stop

HSB7

HSS7

HSB6

HSS6

HSB5

HSS5

HSB4

HSS4

HSB3

HSS3

HSB2

HSS2

HSB1

HSS1

HSB0

HSS0

Sync control

AUFD

FSEL

FOET

HTC1

HTC0

HPLL

VNOI1

LUFI1

DBRI1

DCON1

DSAT1

VNOI0

LUFI0

Luminance control

BYPS

YCOMB

DBRI6

DCON6

DSAT6

HUEC6

CSTD2

CGAIN6

OFFU0

RTP1

LDEL

LUBW

LUFI3

LUFI2

Luminance brightness control

Luminance contrast control

Chrominance saturation control

Chrominance hue control

Chrominance control 1

Chrominance gain control

Chrominance control 2

Mode/delay control

DBRI7

DCON7

DSAT7

HUEC7

CDTO

ACGC

OFFU1

COLO

RTSE13

RTCE

DBRI5

DCON5

DSAT5

HUEC5

CSTD1

CGAIN5

OFFV1

HDEL1

RTSE11

XRVS1

AOSL1

DBRI4

DCON4

DSAT4

HUEC4

CSTD0

CGAIN4

OFFV0

HDEL0

RTSE10

XRVS0

AOSL0

DBRI3

DCON3

DSAT3

HUEC3

DCVF

DBRI2

DCON2

DSAT2

HUEC2

FCTC

DBRI0

DCON0

DSAT0

HUEC0

CCOMB

CGAIN0

LCBW0

YDEL0

RTSE00

OFTS0

APCK0

HUEC1

(1)

CGAIN3

CHBW

RTP0

CGAIN2

LCBW2

YDEL2

RTSE02

OFTS2

OLDSB

CGAIN1

LCBW1

YDEL1

RTSE01

OFTS1

APCK1

RT signal control

RTSE12

XRHS

RTSE03

HLSEL

XTOUTE

RT/X port output control

Analog/ADC/compatibility

control

CM99

UPTCV

VGATE start, FID change

VGATE stop

VSTA7

VSTO7

VSTA6

VSTO6

VSTA5

VSTO5

VSTA4

VSTO4

VSTA3

VSTO3

VSTA2

VSTO2

VSTA1

VSTO1

VSTA0

VSTO0

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SUB

Miscellaneous,

ADDR.

(HEX)

(1)

LLCE

LLC2E

VGPS

VSTO8

VSTA8

VGATE conﬁguration and MSBs

Raw data gain control

Raw data offset control

Reserved

RAWG7

RAWG6

RAWG5

RAWG4

RAWG3

RAWG2

RAWG1

RAWG0

RAWO7

RAWO6

RAWO5

RAWO4

RAWO3

RAWO2

RAWO1

RAWO0

(1)

1A to 1E

Status byte video decoder

(read only, OLDSB = 0)

INTL

HLVLN

FIDT

GLIMT

GLIMB

WIPA

COPRO

RDCAP

Status byte video decoder

(read only, OLDSB = 1)

INTL

HLCK

FIDT

GLIMT

GLIMB

WIPA

SLTCA

CODE

(1)

Reserved

20 to 2F

Audio clock generator part: registers 30H to 3FH

Audio master clock cycles per

ﬁeld

ACPF7

ACPF6

ACPF5

ACPF4

ACPF3

ACPF2

ACPF1

ACPF9

ACPF0

ACPF8

ACPF15

ACPF14

ACPF13

ACPF12

ACPF11

ACPF10

(1)

ACPF17

ACPF16

(1)

Reserved

Audio master clock nominal

increment

ACNI7

ACNI6

ACNI5

ACNI4

ACNI3

ACNI2

ACNI1

ACNI9

ACNI0

ACNI8

ACNI15

ACNI14

ACNI13

ACNI12

ACNI11

ACNI10

(1)

ACNI21

ACNI20

ACNI19

ACNI18

ACNI17

ACNI16

(1)

Reserved

Clock ratio AMXCLK to ASCLK

Clock ratio ASCLK to ALRCLK

SDIV5

SDIV4

SDIV3

LRDIV3

APLL

SDIV2

LRDIV2

AMVR

SDIV1

LRDIV1

LRPH

SDIV0

LRDIV0

SCPH

LRDIV5

LRDIV4

(1)

Audio clock generator basic

set-up

(1)

Reserved

3B to 3F

General purpose VBI data slicer part: registers 40H to 7FH

(1)

Slicer control 1

41 to 57

HAM_N

LCRn_6

FC6

FCE

LCRn_5

FC5

HUNT_N

LCRn_4

FC4

LCR2 to LCR24 (n = 2 to 24)

Programmable framing code

LCRn_7

FC7

LCRn_3

FC3

LCRn_2

FC2

LCRn_1

FC1

LCRn_0

FC0

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SUB

ADDR.

(HEX)

Horizontal offset for slicer

Vertical offset for slicer

HOFF7

VOFF7

FOFF

HOFF6

VOFF6

HOFF5

HOFF4

VOFF4

VOFF8

HOFF3

HOFF2

VOFF2

HOFF1

VOFF1

HOFF9

HOFF0

VOFF0

HOFF8

VOFF5

VOFF3

(1)

Field offset and MSBs for

RECODE

HOFF10

horizontal and vertical offset

(1)

Reserved (for testing)

Header and data identiﬁcation

(DID) code control

FVREF

DID5

DID4

DID3

DID2

DID1

DID0

(1)

Sliced data identiﬁcation (SDID)

code

SDID5

SDID4

SDID3

SDID2

SDID1

SDID0

(1)

Reserved

Slicer status byte 0 (read only)

Slicer status byte 1 (read only)

Slicer status byte 2 (read only)

Reserved

−

FC8V

FC7V

VPSV

LN8

PPV

LN7

CCV

LN6

−

F21_N

LN5

LN4

LN3

(1)

LN2

(1)

LN1

(1)

LN0

(1)

DT3

(1)

DT2

(1)

DT1

(1)

DT0

(1)

63 to 7F

X port, I port and the scaler part: registers 80H to EFH

TASK INDEPENDENT GLOBAL SETTINGS: 80H TO 8FH

(1)

Global control 1

Reserved

SMOD

(1)

TEB

(1)

TEA

(1)

ICKS3

(1)

ICKS2

(1)

ICKS1

(1)

ICKS0

(1)

81 and

(1)

X port I/O enable and output

clock phase control

XPCK1

XPCK0

XRQT

XPE1

XPE0

I port signal deﬁnitions

I port signal polarities

IDG01

ISWP1

VITX1

IDG00

ISWP0

VITX0

IDG11

ILLV

IDG10

IG0P

IDV1

IG1P

FFL1

IDV0

IRVP

FFL0

IDH1

IRHP

FEL1

IDH0

IDQP

FEL0

I port FIFO ﬂag control and

arbitration

IDG02

IDG12

(1)

I port I/O enable, output clock

and gated clock phase control

IPCK3

IPCK2

IPCK1

IPCK0

IPE1

IPE0

(1)

Power save control

Reserved

89 to 8E

CH4EN

CH2EN

SWRST

DPROG

SLM3

(1)

SLM1

(1)

SLM0

(1)

Status information scaler part

XTRI

ITRI

FFIL

FFOV

PRDON

ERROF

FIDSCI

FIDSCO

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SUB

ADDR.

(HEX)

TASK A DEFINITION: REGISTERS 90H TO BFH

Basic settings and acquisition window deﬁnition

Task handling control

CONLH

CONLV

XFDV

OFIDC

HLDFV

XFDH

FSKP2

SCSRC1

XDV1

FSKP1

SCSRC0

XDV0

FSKP0

SCRQE

XCODE

RPTSK

FSC2

XDH

STRC1

FSC1

XDQ

STRC0

FSC0

X port formats and conﬁguration

X port input reference signal

deﬁnitions

XCKS

I port output formats and

conﬁguration

ICODE

I8_16

FYSK

FOI1

FOI0

FSI2

FSI1

FSI0

Horizontal input window start

Horizontal input window length

Vertical input window start

XO7

(1)

XO6

(1)

XO5

(1)

XO4

(1)

XO3

XO11

XS3

XO2

XO10

XS2

XO1

XO9

XS1

XS9

YO1

YO9

YS1

YS9

XD1

XD9

YD1

YD9

XO0

XO8

XS0

XS8

YO0

YO8

YS0

YS8

XD0

XD8

YD0

YD8

XS7

(1)

XS6

(1)

XS5

(1)

XS4

(1)

XS11

YO3

XS10

YO2

YO7

(1)

YO6

(1)

YO5

(1)

YO4

(1)

YO11

YS3

YO10

YS2

Vertical input window length

Horizontal output window length

Vertical output window length

YS7

(1)

YS6

(1)

YS5

(1)

YS4

(1)

YS11

XD3

YS10

XD2

XD7

(1)

XD6

(1)

XD5

(1)

XD4

(1)

XD11

YD3

XD10

YD2

YD7

(1)

YD6

(1)

YD5

(1)

YD4

(1)

YD11

YD10

FIR ﬁltering and prescaling

Horizontal prescaling

Accumulation length

(1)

XPSC5

XACL5

PFY1

XPSC4

XACL4

PFY0

XPSC3

XACL3

XC2_1

XPSC2

XACL2

XDCG2

XPSC1

XACL1

XDCG1

XPSC0

XACL0

XDCG0

Prescaler DC gain and FIR

preﬁlter control

PFUV1

PFUV0

(1)

Reserved

Luminance brightness control

Luminance contrast control

Chrominance saturation control

Reserved

BRIG7

BRIG6

BRIG5

BRIG4

BRIG3

BRIG2

BRIG1

BRIG0

CONT7

CONT6

CONT5

CONT4

CONT3

CONT2

CONT1

CONT0

SATN7

SATN6

SATN5

SATN4

SATN3

SATN2

SATN1

SATN0

(1)

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SUB

ADDR.

(HEX)

Horizontal phase scaling

Horizontal luminance scaling

increment

XSCY7

XSCY6

XSCY5

XSCY4

XSCY12

XPHY4

XSCY3

XSCY11

XPHY3

XSCY2

XSCY10

XPHY2

XSCY1

XSCY9

XPHY1

XSCY0

XSCY8

XPHY0

(1)

Horizontal luminance phase

offset

XPHY7

XPHY6

XPHY5

(1)

Reserved

Horizontal chrominance scaling

increment

XSCC7

XSCC6

XSCC5

XSCC4

XSCC12

XPHC4

XSCC3

XSCC11

XPHC3

XSCC2

XSCC10

XPHC2

XSCC1

XSCC9

XPHC1

XSCC0

XSCC8

XPHC0

(1)

Horizontal chrominance phase

offset

XPHC7

XPHC6

XPHC5

(1)

Reserved

Vertical scaling

Vertical luminance scaling

increment

YSCY7

YSCY15

YSCC7

YSCY6

YSCY14

YSCC6

YSCY5

YSCY13

YSCC5

YSCY4

YSCY12

YSCC4

YSCC12

YSCY3

YSCY11

YSCC3

YSCY2

YSCY10

YSCC2

YSCY1

YSCY9

YSCC1

YSCY0

YSCY8

YSCC0

YSCC8

Vertical chrominance scaling

increment

YSCC15

YSCC14

YSCC13

YSCC11

YSCC10

YSCC9

(1)

Vertical scaling mode control

Reserved

YMIR

(1)

YMODE

(1)

B5 to B7

Vertical chrominance phase

offset ‘00’

YPC07

YPC06

YPC05

YPC04

YPC14

YPC24

YPC34

YPY04

YPY14

YPY24

YPC03

YPC02

YPC01

YPC00

YPC10

YPC20

YPC30

YPY00

YPY10

YPY20

Vertical chrominance phase

offset ‘01’

YPC17

YPC27

YPC37

YPY07

YPY17

YPY27

YPC16

YPC26

YPC36

YPY06

YPY16

YPY26

YPC15

YPC25

YPC35

YPY05

YPY15

YPY25

YPC13

YPC23

YPC33

YPY03

YPY13

YPY23

YPC12

YPC22

YPC32

YPY02

YPY12

YPY22

YPC11

YPC21

YPC31

YPY01

YPY11

YPY21

Vertical chrominance phase

offset ‘10’

Vertical chrominance phase

offset ‘11’

Vertical luminance phase

offset ‘00’

Vertical luminance phase

offset ‘01’

Vertical luminance phase

offset ‘10’

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SUB

ADDR.

(HEX)

Vertical luminance phase

offset ‘11’

YPY37

YPY36

YPY35

YPY34

YPY33

YPY32

YPY31

YPY30

TASK B DEFINITION REGISTERS C0H TO EFH

Basic settings and acquisition window deﬁnition

Task handling control

CONLH

CONLV

XFDV

OFIDC

HLDFV

XFDH

I8_16

FSKP2

SCSRC1

XDV1

FSKP1

SCSRC0

XDV0

FSKP0

SCRQE

XCODE

FOI0

RPTSK

FSC2

XDH

FSI2

XO2

STRC1

FSC1

XDQ

FSI1

XO1

XO9

XS1

STRC0

FSC0

XCKS

FSI0

XO0

XO8

XS0

X port formats and conﬁguration

Input reference signal deﬁnition

I port formats and conﬁguration

Horizontal input window start

ICODE

FYSK

FOI1

XO7

(1)

XO6

(1)

XO5

(1)

XO4

(1)

XO3

XO11

XS3

XO10

XS2

Horizontal input window length

Vertical input window start

XS7

(1)

XS6

(1)

XS5

(1)

XS4

(1)

XS11

YO3

XS10

YO2

XS9

XS8

YO7

(1)

YO6

(1)

YO5

(1)

YO4

(1)

YO1

YO9

YS1

YO0

YO11

YS3

YO10

YS2

YO8

Vertical input window length

Horizontal output window length

Vertical output window length

YS7

(1)

YS6

(1)

YS5

(1)

YS4

(1)

YS0

YS11

XD3

YS10

XD2

YS9

YS8

XD7

(1)

XD6

(1)

XD5

(1)

XD4

(1)

XD1

XD9

YD1

YD9

XD0

XD8

YD0

YD8

XD11

YD3

XD10

YD2

YD7

(1)

YD6

(1)

YD5

(1)

YD4

(1)

YD11

YD10

FIR ﬁltering and prescaling

(1)

Horizontal prescaling

Accumulation length

XPSC5

XACL5

PFY1

XPSC4

XACL4

PFY0

XPSC3

XACL3

XC2_1

XPSC2

XACL2

XDCG2

XPSC1

XACL1

XDCG1

XPSC0

XACL0

XDCG0

Prescaler DC gain and FIR

preﬁlter control

PFUV1

PFUV0

(1)

Reserved

Luminance brightness control

Luminance contrast control

Chrominance saturation control

Reserved

BRIG7

BRIG6

BRIG5

BRIG4

BRIG3

BRIG2

BRIG1

BRIG0

CONT7

CONT6

CONT5

CONT4

CONT3

CONT2

CONT1

CONT0

SATN7

SATN6

SATN5

SATN4

SATN3

SATN2

SATN1

SATN0

(1)

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SUB

ADDR.

(HEX)

Horizontal phase scaling

Horizontal luminance scaling

increment

XSCY7

XSCY6

XSCY5

XSCY4

XSCY12

XPHY4

XSCY3

XSCY11

XPHY3

XSCY2

XSCY10

XPHY2

XSCY1

XSCY9

XPHY1

XSCY0

XSCY8

XPHY0

(1)

Horizontal luminance phase

offset

XPHY7

XPHY6

XPHY5

(1)

Reserved

Horizontal chrominance scaling

increment

XSCC7

XSCC6

XSCC5

XSCC4

XSCC12

XPHC4

XSCC3

XSCC11

XPHC3

XSCC2

XSCC10

XPHC2

XSCC1

XSCC9

XPHC1

XSCC0

XSCC8

XPHC0

(1)

Horizontal chrominance phase

offset

XPHC7

XPHC6

XPHC5

(1)

Reserved

Vertical scaling

Vertical luminance scaling

increment

YSCY7

YSCY15

YSCC7

YSCY6

YSCY14

YSCC6

YSCY5

YSCY13

YSCC5

YSCY4

YSCY12

YSCC4

YSCC12

YSCY3

YSCY11

YSCC3

YSCY2

YSCY10

YSCC2

YSCY1

YSCY9

YSCC1

YSCY0

YSCY8

YSCC0

YSCC8

Vertical chrominance scaling

increment

YSCC15

YSCC14

YSCC13

YSCC11

YSCC10

YSCC9

(1)

Vertical scaling mode control

Reserved

YMIR

(1)

YMODE

(1)

E5 to E7

Vertical chrominance phase

offset ‘00’

YPC07

YPC06

YPC05

YPC04

YPC14

YPC24

YPC34

YPC03

YPC02

YPC01

YPC00

YPC10

YPC20

YPC30

Vertical chrominance phase

offset ‘01’

YPC17

YPC27

YPC37

YPC16

YPC26

YPC36

YPC15

YPC25

YPC35

YPC13

YPC23

YPC33

YPC12

YPC22

YPC32

YPC11

YPC21

YPC31

Vertical chrominance phase

offset ‘10’

Vertical chrominance phase

offset ‘11’

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SUB

ADDR.

(HEX)

Vertical luminance phase

offset ‘00’

YPY07

YPY17

YPY27

YPY37

YPY06

YPY16

YPY26

YPY36

YPY05

YPY15

YPY25

YPY35

YPY04

YPY14

YPY24

YPY34

YPY03

YPY13

YPY23

YPY33

YPY02

YPY12

YPY22

YPY32

YPY01

YPY11

YPY21

YPY31

YPY00

YPY10

YPY20

YPY30

Vertical luminance phase

offset ‘01’

Vertical luminance phase

offset ‘10’

Vertical luminance phase

offset ‘11’

Note

1. All unused control bits must be programmed with logic 0 to ensure compatibility to future enhancements.

18.2.2 I²C-BUS DETAIL

18.2.2.1 Subaddress 00H

Table 149 Chip version (CV) identiﬁcation; 00H[7:4]; read only register

LOGIC LEVELS

FUNCTION

ID7

ID6

ID5

ID4

CV0

Chip Version (CV)

CV3

CV2

CV1

18.2.2.2 Subaddress 01H

The programming of the horizontal increment delay is used to match internal processing delays to the delay of the ADC. Use recommended position

only.

Table 150 Horizontal increment delay; 01H[3:0]

FUNCTION

IDEL3

IDEL2

IDEL1

IDEL0

No update

Minimum delay

Recommended position

Maximum delay

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

18.2.2.3 Subaddress 02H

Table 151 Analog input control 1 (AICO1); 02H[7:0]

BIT

DESCRIPTION

SYMBOL VALUE

FUNCTION

7 and 6 analog function select;

see Fig.14

FUSE[1:0]

ampliﬁer plus anti-alias ﬁlter bypassed

ampliﬁer active

ampliﬁer plus anti-alias ﬁlter active

5 and 4 update hysteresis for

9-bit gain; see Fig.15

GUDL[1:0]

off

±1 LSB

±2 LSB

±3 LSB

3 to 0 mode selection

MODE[3:0] 0000 Mode 0: CVBS (automatic gain) from AI11 (pin P13);

see Fig.57

0001 Mode 1: CVBS (automatic gain) from AI12 (pin P11);

see Fig.58

0010 Mode 2: CVBS (automatic gain) from AI21 (pin P10);

see Fig.59

0011 Mode 3: CVBS (automatic gain) from AI22 (pin P9);

see Fig.60

0100 Mode 4: CVBS (automatic gain) from AI23 (pin P7);

see Fig.61

0101 Mode 5: CVBS (automatic gain) from AI24 (pin P6);

see Fig.62

0110 Mode 6: Y (automatic gain) from AI11 (pin P13) + C (gain

adjustable via GAI28 to GAI20) from AI21 (pin P10);

note 1; see Fig.63

0111 Mode 7: Y (automatic gain) from AI12 (pin P11) + C (gain

adjustable via GAI28 to GAI20) from AI22 (pin P9); note 1;

see Fig.64

1000 Mode 8: Y (automatic gain) from AI11 (pin P13) + C (gain

adapted to Y gain) from AI21 (pin P10); note 1; see Fig.65

1001 Mode 9: Y (automatic gain) from AI12 (pin P11) + C (gain

adapted to Y gain) from AI22 (pin P9); note 1; see Fig.66

1010 Modes 10 to 15: reserved

1111

Note

1. To take full advantage of the Y/C modes 6 to 9 the I²C-bus bit BYPS (subaddress 09H, bit 7) should be set to logic 1

(full luminance bandwidth).

2004 Mar 16

151

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

AI24

AI23

AI22

AI21

AI24

AI23

AI22

AI21

AD2

AD1

AD2

CHROMA

LUMA

AI12

AI11

LUMA

AD1

AI12

AI11

MHB559

MHB560

Fig.57 Mode 0; CVBS (automatic gain).

Fig.58 Mode 1; CVBS (automatic gain).

AI24

AI23

AI22

AI21

AI23

AI22

AI21

AD2

AD1

AD2

AD1

CHROMA

LUMA

AI12

AI11

AI12

AI11

MHB561

MHB562

Fig.59 Mode 2; CVBS (automatic gain).

Fig.60 Mode 3; CVBS (automatic gain).

AI24

AI23

AI22

AI21

AI23

AI22

AI21

AD2

AD1

AD2

AD1

CHROMA

LUMA

AI12

AI11

AI12

AI11

MHB563

MHB564

Fig.61 Mode 4; CVBS (automatic gain).

Fig.62 Mode 5; CVBS (automatic gain).

2004 Mar 16

152

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

AI24

AI23

AI22

AI21

AI24

AI23

AI22

AI21

AD2

AD1

AD2

CHROMA

LUMA

AI12

AI11

LUMA

AD1

AI12

AI11

MHB565

MHB566

I²C-bus bit BYPS (subaddress 09H, bit 7) should be set to logic 1

(full luminance bandwidth).

I²C-bus bit BYPS (subaddress 09H, bit 7) should be set to logic 1

(full luminance bandwidth).

Fig.63 Mode 6; Y + C (gain channel 2 adjusted via

GAI2).

Fig.64 Mode 7; Y + C (gain channel 2 adjusted via

GAI2).

AI24

AI23

AI22

AI21

AI23

AI22

AI21

AD2

CHROMA

LUMA

AI12

AI11

AI12

AI11

AD1

MHB567

MHB568

I²C-bus bit BYPS (subaddress 09H, bit 7) should be set to logic 1

(full luminance bandwidth).

I²C-bus bit BYPS (subaddress 09H, bit 7) should be set to logic 1

(full luminance bandwidth).

Fig.65 Mode 8; Y + C (gain channel 2 adapted to Y

gain).

Fig.66 Mode 9; Y + C (gain channel 2 adapted to Y

gain).

2004 Mar 16

153

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

18.2.2.4 Subaddress 03H

Table 152 Analog input control 2 (AICO2); 03H[6:0]

BIT

DESCRIPTION

SYMBOL VALUE

FUNCTION

HL not reference select

HLNRS

1⁽¹⁾

normal clamping if decoder is in unlocked state

reference select if decoder is in unlocked state

AGC hold during vertical

blanking period

VBSL

short vertical blanking (AGC disabled during equalization

and serration pulses)

long vertical blanking (AGC disabled from start of

pre-equalization pulses until start of active video (line 22 for

60 Hz, line 24 for 50 Hz)

white peak control off

WPOFF

HOLDG

GAFIX

0⁽¹⁾

white peak control active

white peak control off

automatic gain control

integration

AGC active

AGC integration hold (freeze)

automatic gain controlled by MODE3 to MODE0

gain is user programmable via GAI[17:10] and GAI[27:20]

see Table 154

gain control ﬁx

static gain control channel 2

sign bit

GAI28

GAI18

static gain control channel 1

sign bit

see Table 153

Note

1. HLNRS = 1 should not be used in combination with WPOFF = 0.

18.2.2.5 Subaddress 04H

Table 153 Analog input control 3 (AICO3); static gain control channel 1; 03H[0] and 04H[7:0]

SIGN BIT

03H[0]

CONTROL BITS 7 TO 0

DECIMAL

VALUE

GAIN

(dB)

GAI18

GAI17

GAI16

GAI15

GAI14

GAI13

GAI12

GAI11

GAI10

0...

−3

...144

145...

...511

18.2.2.6 Subaddress 05H

Table 154 Analog input control 4 (AICO4); static gain control channel 2; 03H[1] and 05H[7:0]

SIGN BIT

03H[1]

CONTROL BITS 7 TO 0

DECIMAL

VALUE

GAIN

(dB)

GAI28

GAI27

GAI26

GAI25

GAI24

GAI23

GAI22

GAI21

GAI20

0...

−3

...144

145...

...511

2004 Mar 16

154

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

18.2.2.7 Subaddress 06H

Table 155 Horizontal sync start; 06H[7:0]

CONTROL BITS 7 TO 0

HSB5 HSB4 HSB3

forbidden (outside available central counter range)

DELAY TIME

(STEP SIZE = 8/LLC)

HSB7

HSB6

HSB2

HSB1

HSB0

−128...−109 (50 Hz)

−128...−108 (60 Hz)

−108 (50 Hz)...

−107 (60 Hz)...

...108 (50 Hz)

...107 (60 Hz)

109...127 (50 Hz)

108...127 (60 Hz)

forbidden (outside available central counter range)

18.2.2.8 Subaddress 07H

Table 156 Horizontal sync stop; 07H[7:0]

CONTROL BITS 7 TO 0

DELAY TIME

(STEP SIZE = 8/LLC)

HSS7

HSS6

HSS5

HSS4

HSS3

HSS2

HSS1

HSS0

−128...−109 (50 Hz)

−128...−108 (60 Hz)

forbidden (outside available central counter range)

−108 (50 Hz)...

−107 (60 Hz)...

...108 (50 Hz)

...107 (60 Hz)

109...127 (50 Hz)

108...127 (60 Hz)

forbidden (outside available central counter range)

2004 Mar 16

155

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

18.2.2.9 Subaddress 08H

Table 157 Sync control; 08H[7:0]

BIT

DESCRIPTION

SYMBOL VALUE

FUNCTION

automatic ﬁeld detection

AUFD

FSEL

FOET

ﬁeld state directly controlled via FSEL

automatic ﬁeld detection; recommended setting

50 Hz, 625 lines

ﬁeld selection

60 Hz, 525 lines

forced ODD/EVEN

toggle

ODD/EVEN signal toggles only with interlaced source

ODD/EVEN signal toggles ﬁeldwise even if source is

non-interlaced

4 and 3 horizontal time constant HTC[1:0]

selection

TV mode, recommended for poor quality TV signals only; do

not use for new applications

VTR mode, recommended if a deﬂection control circuit is

directly connected to the SAA7108E; SAA7109E

reserved

fast locking mode; recommended setting

PLL closed

horizontal PLL

HPLL

PLL open; horizontal frequency ﬁxed

normal mode; recommended setting

1 and 0 vertical noise reduction VNOI[1:0]

fast mode, applicable for stable sources only; automatic ﬁeld

detection (AUFD) must be disabled

free running mode

vertical noise reduction bypassed

2004 Mar 16

156

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

18.2.2.10 Subaddress 09H

Table 158 Luminance control; 09H[7:0]

BIT

DESCRIPTION

SYMBOL VALUE

FUNCTION

chrominance trap/comb ﬁlter

bypass

BYPS

chrominance trap or luminance comb ﬁlter active;

default for CVBS mode

chrominance trap or luminance comb ﬁlter bypassed;

default for S-video mode

adaptive luminance comb

ﬁlter

YCOMB

LDEL

disabled (= chrominance trap enabled, if BYPS = 0)

active, if BYPS = 0

processing delay in non comb

ﬁlter mode

processing delay is equal to internal pipelining delay

one (NTSC standards) or two (PAL standards) video

lines additional processing delay

remodulation bandwidth for

luminance; see Figs 20 to 23

LUBW

small remodulation bandwidth (narrow chrominance

notch

large remodulation bandwidth (wider chrominance

notch smaller luminance bandwidth)

higher luminance bandwidth)

3 to 0 sharpness control, luminance LUFI[3:0]

0001 resolution enhancement ﬁlter; 8.0 dB at 4.1 MHz

0010 resolution enhancement ﬁlter; 6.8 dB at 4.1 MHz

0011 resolution enhancement ﬁlter; 5.1 dB at 4.1 MHz

0100 resolution enhancement ﬁlter; 4.1 dB at 4.1 MHz

0101 resolution enhancement ﬁlter; 3.0 dB at 4.1 MHz

0110 resolution enhancement ﬁlter; 2.3 dB at 4.1 MHz

0111 resolution enhancement ﬁlter; 1.6 dB at 4.1 MHz

0000 plain

ﬁlter characteristic; see

Fig.24

1000 low-pass ﬁlter; 2 dB at 4.1 MHz

1001 low-pass ﬁlter; 3 dB at 4.1 MHz

1010 low-pass ﬁlter; 3 dB at 3.3 MHz; 4 dB at 4.1 MHz

1011 low-pass ﬁlter; 3 dB at 2.6 MHz; 8 dB at 4.1 MHz

1100 low-pass ﬁlter; 3 dB at 2.4 MHz; 14 dB at 4.1 MHz

1101 low-pass ﬁlter; 3 dB at 2.2 MHz; notch at 3.4 MHz

1110 low-pass ﬁlter; 3 dB at 1.9 MHz; notch at 3.0 MHz

1111 low-pass ﬁlter; 3 dB at 1.7 MHz; notch at 2.5 MHz

18.2.2.11 Subaddress 0AH

Table 159 Luminance brightness control: decoder part; 0AH[7:0]

CONTROL BITS 7 TO 0

OFFSET

DBRI7

DBRI6

DBRI5

DBRI4

DBRI3

DBRI2

DBRI1

DBRI0

255 (bright)

128 (ITU level)

0 (dark)

2004 Mar 16

157

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

18.2.2.12 Subaddress 0BH

Table 160 Luminance contrast control: decoder part; 0BH[7:0]

CONTROL BITS 7 TO 0

DCON7 DCON6 DCON5 DCON4 DCON3 DCON2 DCON1 DCON0

GAIN

1.984 (maximum)

1.063 (ITU level)

1.0

0 (luminance off)

−1 (inverse luminance)

−2 (inverse luminance)

18.2.2.13 Subaddress 0CH

Table 161 Chrominance saturation control: decoder part; 0CH[7:0]

CONTROL BITS 7 TO 0

GAIN

DSAT7

DSAT6

DSAT5

DSAT4

DSAT3

DSAT2

DSAT1

DSAT0

1.984 (maximum)

1.0 (ITU level)

0 (colour off)

−1 (inverse chrominance)

−2 (inverse chrominance)

18.2.2.14 Subaddress 0DH

Table 162 Chrominance hue control: 0DH[7:0]

CONTROL BITS 7 TO 0

HUE PHASE (DEG)

HUEC7

HUEC6

HUEC5

HUEC4

HUEC3

HUEC2

HUEC1

HUEC0

+178.6...

...0...

...−180

2004 Mar 16

158

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

18.2.2.15 Subaddress 0EH

Table 163 Chrominance control 1; 0EH[7:0]

FUNCTION

BIT

DESCRIPTION

clear DTO

SYMBOL

VALUE

50 Hz/625 LINES

disabled

60 Hz/525 LINES

CDTO

Every time CDTO is set, the internal subcarrier DTO

phase is reset to 0° and the RTCO output generates a

logic 0 at time slot 68 (see document “RTC Functional

Description”, available on request). So an identical

subcarrier phase can be generated by an external device

(e.g. an encoder).

6 to 4 colour standard selection CSTD[2:0]

000

001

010

PAL BGDHI (4.43 MHz)

NTSC 4.43 (50 Hz)

NTSC M (3.58 MHz)

PAL 4.43 (60 Hz)

Combination-PAL N

(3.58 MHz)

NTSC 4.43 (60 Hz)

011

100

101

110

111

NTSC N (3.58 MHz)

reserved

PAL M (3.58 MHz)

NTSC-Japan (3.58 MHz)

reserved

SECAM

reserved; do not use

disable chrominance

vertical ﬁlter and PAL

phase error correction

DCVF

chrominance vertical ﬁlter and PAL phase error

correction on (during active video lines)

chrominance vertical ﬁlter and PAL phase error

correction permanently off

fast colour time constant FCTC

nominal time constant

fast time constant for special applications

adaptive chrominance

comb ﬁlter

CCOMB

disabled

active

18.2.2.16 Subaddress 0FH

Table 164 Chrominance gain control; 0FH[7:0]

BIT

DESCRIPTION

SYMBOL

VALUE

FUNCTION

automatic chrominance

gain control

ACGC

programmable gain via CGAIN6 to CGAIN0; need to be

set for SECAM standard

6 to 0 chrominance gain value

(if ACGC is set to logic 1)

CGAIN[6:0] 000 0000 minimum gain (0.5)

010 0100 nominal gain (1.125)

111 1111 maximum gain (7.5)

2004 Mar 16

159

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

18.2.2.17 Subaddress 10H

Table 165 Chrominance control 2; 10H[7:0]

BIT

DESCRIPTION

SYMBOL VALUE

FUNCTION

7 and 6 ﬁne offset adjustment B − Y component

OFFU[1:0]

OFFV[1:0]

CHBW

0 LSB

¹⁄₄LSB

¹⁄₂LSB

³⁄₄LSB

0 LSB

¹⁄₄LSB

¹⁄₂LSB

³⁄₄LSB

small

5 and 4 ﬁne offset adjustment R − Y component

chrominance bandwidth; see Figs 18 and 19

wide

2 to 0 combined luminance/chrominance bandwidth LCBW[2:0]

adjustment; see Figs 18 to 24

000

smallest chrominance

bandwidth/largest luminance

bandwidth

...

... to ...

111

largest chrominance

bandwidth/smallest luminance

bandwidth

18.2.2.18 Subaddress 11H

Table 166 Mode/delay control; 11H[7:0]

BIT

DESCRIPTION

SYMBOL VALUE

FUNCTION

colour on

COLO

automatic colour killer enabled

colour forced on

polarity of RTS1 output signal

RTP1

non inverted

inverted

5 and 4 ﬁne position of HS (steps in 2/LLC)

HDEL[1:0]

polarity of RTS0 output signal

RTP0

non inverted

inverted

−4...

2 to 0 luminance delay compensation (steps in

2/LLC)

YDEL[2:0]

100

000

011

...0...

...3

2004 Mar 16

160

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

18.2.2.19 Subaddress 12H

Table 167 RT signal control: RTS0 output; 12H[3:0]

The polarity of any signal on RTS0 can be inverted via RTP0[11H[3]].

RTS0 OUTPUT

RTSE03 RTSE02 RTSE01 RTSE00

3-state

Constant LOW

CREF (13.5 MHz toggling pulse; see Fig.31)

CREF2 (6.75 MHz toggling pulse; see Fig.31)

HL; horizontal lock indicator (note 1):

HL = 0: unlocked

HL = 1: locked

VL; vertical and horizontal lock:

VL = 0: unlocked

VL = 1: locked

DL; vertical and horizontal lock and colour detected:

DL = 0: unlocked

DL = 1: locked

Reserved

HREF, horizontal reference signal; indicates 720 pixels valid data on the

expansion port. The positive slope marks the beginning of a new active line.

HREF is also generated during the vertical blanking interval (see Fig.31).

HS:

programmable width in LLC8 steps via HSB[7:0] 06H[7:0] and HSS[7:0]

07H[7:0]

fine position adjustment in LLC2 steps via HDEL[1:0] 11H[5:4]; see Fig.31

HQ; HREF gated with VGATE

Reserved

V123; vertical sync (see vertical timing diagrams Figs 29 and 30)

VGATE; programmable via VSTA[8:0] 17H[0] 15H[7:0], VSTO[8:0] 17H[1]

16H[7:0] and VGPS[17H[2]]

LSBs of the 9-bit ADC’s

FID; position programmable via VSTA[8:0] 17H[0] 15H[7:0];

see vertical timing diagrams Figs 29 and 30

Note

1. Function of HL is selectable via HLSEL[13H[3]]:

a) HLSEL = 0: HL is standard horizontal lock indicator.

b) HLSEL = 1: HL is fast horizontal lock indicator (use is not recommended for sources with unstable timebase e.g.

VCRs).

2004 Mar 16

161

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

Table 168 RT signal control: RTS1 output; 12H[7:4]

The polarity of any signal on RTS1 can be inverted via RTP1[11H[6]].

RTS1 OUTPUT CONTROL

RTSE13 RTSE12 RTSE11 RTSE10

3-state

Constant LOW

CREF (13.5 MHz toggling pulse; see Fig.31)

CREF2 (6.75 MHz toggling pulse; see Fig.31)

HL; horizontal lock indicator (note 1):

HL = 0: unlocked

HL = 1: locked

VL; vertical and horizontal lock:

VL = 0: unlocked

VL = 1: locked

DL; vertical and horizontal lock and colour detected:

DL = 0: unlocked

DL = 1: locked

Reserved

HREF, horizontal reference signal: indicates 720 pixels valid data on the

expansion port. The positive slope marks the beginning of a new active line.

HREF is also generated during the vertical blanking interval (see Fig.31).

HS:

programmable width in LLC8 steps via HSB[7:0] 06H[7:0] and HSS[7:0]

07H[7:0]

fine position adjustment in LLC2 steps via HDEL[1:0] 11H[5:4]; see Fig.31

HQ; HREF gated with VGATE

Reserved

V123; vertical sync (see vertical timing diagrams Figs 29 and 30)

VGATE; programmable via VSTA[8:0] 17H[0] 15H[7:0], VSTO[8:0] 17H[1]

16H[7:0] and VGPS[17H[2]]

Reserved

FID; position programmable via VSTA[8:0] 17H[0] 15H[7:0];

see vertical timing diagrams Figs 29 and 30

Note

1. Function of HL is selectable via HLSEL[13H[3]]:

a) HLSEL = 0: HL is standard horizontal lock indicator.

b) HLSEL = 1: HL is fast horizontal lock indicator (use is not recommended for sources with unstable timebase e.g.

VCRs).

2004 Mar 16

162

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

18.2.2.20 Subaddress 13H

Table 169 RT/X port output control; 13H[7:0]

BIT

DESCRIPTION

SYMBOL VALUE

FUNCTION

RTCO output enable

RTCE

3-state

enabled

X port XRH output

selection

XRHS

HREF (see Fig.31)

HS:

programmable width in LLC8 steps via HSB[7:0] 06H[7:0]

and HSS[7:0] 07H[7:0]

fine position adjustment in LLC2 steps via HDEL[1:0]

11H[5:4] (see Fig.31)

5 and 4 X port XRV output

selection

XRVS[1:0]

V123; see Figs 29 and 30

ITU 656 related ﬁeld ID; see Figs 29 and 30

inverted V123

inverted ITU 656 related ﬁeld ID

copy of inverted HLCK status bit (default)

fast horizontal lock indicator (for special applications only)

ITU 656

horizontal lock indicator

selection

HLSEL

2 to 0 XPD7 to XPD0 (port

output format selection);

see Section 10.4

OFTS[2:0]

000

001

ITU 656 like format with modiﬁed ﬁeld blanking according

to VGATE position (programmable via VSTA[8:0] 17H[0]

15H[7:0], VSTO[8:0] 17H[1] 16H[7:0] and VGPS[17H[2]])

010

011

100

Y-C_B-C_R4 : 2 : 2 8-bit format (no SAV/EAV codes inserted)

reserved

multiplexed AD2/AD1 bypass (bits 8 to 1) dependent on

mode settings; if both ADCs are selected AD2 is output at

CREF = 1 and AD1 is output at CREF = 0

101

multiplexed AD2/AD1 bypass (bits 7 to 0) dependent on

mode settings; if both ADCs are selected AD2 is output at

CREF = 1 and AD1 is output at CREF = 0

110

111

reserved

multiplexed ADC MSB/LSB bypass dependent on mode

settings; only one ADC should be selected at a time;

ADx8 to ADx1 are outputs at CREF = 1 and ADx7 to ADx0

are outputs at CREF = 0

2004 Mar 16

163

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

18.2.2.21 Subaddress 14H

Table 170 Analog/ADC/compatibility control; 14H[7:0]

BIT

DESCRIPTION

SYMBOL VALUE

FUNCTION

compatibility bit for

SAA7199

CM99

off (default)

on (to be set only if SAA7199 is used for re-encoding in

conjunction with RTCO active)

update time interval for

AGC value

UPTCV

horizontal update (once per line)

vertical update (once per ﬁeld)

AOUT connected to internal test point 1

AOUT connected to input AD1

AOUT connected to input AD2

AOUT connected to internal test point 2

pin P4 (XTOUTd) 3-stated

5 and 4 analog test select

AOSL[1:0]

XTOUTd output enable

XTOUTE

OLDSB

pin P4 (XTOUTd) enabled

decoder status byte

standard

selection; see Table 176

backward compatibility to SAA7112

application dependent

1 and 0 ADC sample clock

phase delay

APCK[1:0]

2004 Mar 16

164

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18.2.2.22 Subaddress 15H

Table 171 VGATE start; FID polarity change; 17H[0] and 15H[7:0]

Start of VGATE pulse (LOW-to-HIGH transition) and polarity change of FID pulse, VGPS = 0; see Figs 29 and 30.

MSB

17H[0]

CONTROL BITS 7 TO 0

FRAME LINE

COUNTING

DECIMAL

VALUE

FIELD

VSTA8

VSTA7

VSTA6

VSTA5

VSTA4

VSTA3

VSTA2

VSTA1 VSTA0

50 Hz

1st

2nd

1st

312

0...

314

2nd

1st

315

312

625

...310

262

2nd

1st

60 Hz

2nd

1st

267

0...

2nd

1st

268

265

...260

2nd

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18.2.2.23 Subaddress 16H

Table 172 VGATE stop; 17H[1] and 16H[7:0]

Stop of VGATE pulse (HIGH-to-LOW transition), VGPS = 0; see Figs 29 and 30.

MSB

17H[1]

CONTROL BITS 7 TO 0

FRAME LINE

COUNTING

DECIMAL

VALUE

FIELD

VSTO8

VSTO7 VSTO6 VSTO5 VSTO4 VSTO3 VSTO2 VSTO1 VSTO0

50 Hz

1st

2nd

1st

312

0...

314

2nd

1st

315

312

625

...310

262

2nd

1st

60 Hz

2nd

1st

267

0...

2nd

1st

268

265

...260

2nd

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

18.2.2.24 Subaddress 17H

Table 173 Miscellaneous/VGATE MSBs; 17H[7:6] and 17H[2:0]

BIT

DESCRIPTION

SYMBOL VALUE

FUNCTION

LLC output enable

LLCE

LLC2E

VGPS

enable

3-state

enable

3-state

LLC2 output enable

alternative VGATE

position

VGATE position according to Tables 171 and 172

VGATE occurs one line earlier during ﬁeld 2

see Table 172

MSB VGATE stop

MSB VGATE start

VSTO8

VSTA8

see Table 171

18.2.2.25 Subaddress 18H

Table 174 Raw data gain control; RAWG[7:0] 18H[7:0]; see Fig.26

CONTROL BITS 7 TO 0

RAWG7 RAWG6 RAWG5 RAWG4 RAWG3 RAWG2 RAWG1 RAWG0

GAIN

255 (double amplitude)

128 (nominal level)

0 (off)

18.2.2.26 Subaddress 19H

Table 175 Raw data offset control; RAWO[7:0] 19H[7:0]; see Fig.26

CONTROL BITS 7 TO 0

RAWO7 RAWO6 RAWO5 RAWO4 RAWO3 RAWO2 RAWO1 RAWO0

OFFSET

−128 LSB

0 LSB

+128 LSB

2004 Mar 16

167

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

18.2.2.27 Subaddress 1FH

Table 176 Status byte video decoder; 1FH[7:0]; read only register

I²C-BUS

CONTROL

BIT

OLDSB

14H[2]

BIT

DESCRIPTION

VALUE

FUNCTION

status bit for interlace detection

INTL

HLVLN

HLCK

−

non-interlaced

interlaced

both loops locked

unlocked

locked

status bit for horizontal and vertical loop

status bit for locked horizontal frequency

identiﬁcation bit for detected ﬁeld frequency

unlocked

50 Hz

FIDT

60 Hz

gain value for active luminance channel is

limited; maximum (top)

GLIMT

GLIMB

WIPA

not active

active

gain value for active luminance channel is

limited; minimum (bottom)

not active

active

white peak loop is activated

not active

active

copy protected source detected according to

macrovision version up to 7.01

COPRO

SLTCA

RDCAP

CODE

not active

active

slow time constant active in WIPA mode

not active

active

ready for capture (all internal loops locked)

not active

active

colour signal in accordance with selected

standard has been detected

not active

active

18.2.3 PROGRAMMING REGISTER AUDIO CLOCK GENERATION

See equations in Section 9.6 and examples in Tables 51 and 52.

18.2.3.1 Subaddresses 30H to 32H

Table 177 Audio master clock (AMCLK) cycles per ﬁeld

SUBADDRESS

CONTROL BITS 7 TO 0

30H

31H

32H

ACPF7

ACPF15

−

ACPF6

ACPF14

−

ACPF5

ACPF13

−

ACPF4

ACPF12

−

ACPF3

ACPF11

−

ACPF2

ACPF10

−

ACPF1

ACPF9

ACPF17

ACPF0

ACPF8

ACPF16

2004 Mar 16

168

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

18.2.3.2 Subaddresses 34H to 36H

Table 178 Audio master clock (AMCLK) nominal increment

SUBADDRESS

CONTROL BITS 7 TO 0

34H

35H

36H

ACNI7

ACNI15

−

ACNI

ACNI14

−

ACNI5

ACNI13

ACNI21

ACNI4

ACNI12

ACNI20

ACNI3

ACNI11

ACNI19

ACNI2

ACNI10

ACNI18

ACNI1

ACNI9

ACNI17

ACNI0

ACNI8

ACNI16

18.2.3.3 Subaddress 38H

Table 179 Clock ratio audio master clock (AMXCLK) to serial bit clock (ASCLK)

SUBADDRESS

CONTROL BITS 7 TO 0

SDIV4 SDIV3

38H

−

SDIV5

SDIV2

SDIV1

SDIV0

18.2.3.4 Subaddress 39H

Table 180 Clock ratio serial bit clock (ASCLK) to channel select clock (ALRCLK)

SUBADDRESS

CONTROL BITS 7 TO 0

LRDIV4 LRDIV3

39H

−

LRDIV5

LRDIV2

LRDIV1

LRDIV0

18.2.3.5 Subaddress 3AH

Table 181 Audio clock control; 3AH[3:0]

BIT

DESCRIPTION

SYMBOL VALUE

FUNCTION

audio PLL modes

APLL

AMVR

LRPH

SCPH

PLL active, AMCLK is ﬁeld-locked

PLL open, AMCLK is free-running

audio master clock

vertical reference

vertical reference pulse is taken from internal decoder

vertical reference is taken from XRV input (expansion port)

ALRCLK edges triggered by falling edges of ASCLK

ALRCLK edges triggered by rising edges of ASCLK

ASCLK edges triggered by falling edges of AMCLK

ASCLK edges triggered by rising edges of AMCLK

ALRCLK phase

ASCLK phase

18.2.4 PROGRAMMING REGISTER VBI DATA SLICER

18.2.4.1 Subaddress 40H

Table 182 Slicer control 1; 40H[6:4]

BIT

DESCRIPTION

Hamming check

SYMBOL VALUE

FUNCTION

HAM_N

Hamming check for 2 bytes after framing code,

dependent on data type (default)

no Hamming check

framing code error

amplitude searching

FCE

one framing code error allowed

no framing code errors allowed

amplitude searching active (default)

amplitude searching stopped

HUNT_N

2004 Mar 16

169

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

18.2.4.2 Subaddresses 41H to 57H

Table 183 Line control register; LCR2 to LCR24 (41H to 57H); see Sections 9.2 and 9.4

BITS 7 TO 4

BITS 3 TO 0

(41H TO 57H)

NAME

DESCRIPTION

FRAMING CODE

DT[3:0] 62H[3:0] DT[3:0] 62H[3:0]

(FIELD 1)

(FIELD 2)

WST625

CC625

VPS

teletext EuroWST, CCST

European Closed Caption

video programming service

wide screen signalling bits

US teletext (WST)

27H

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

001

9951H

WSS

1E3C1FH

WST525

CC525

Test line

Intercast

27H

US Closed Caption (line 21)

video component signal, VBI region

raw data

001

−

General text teletext

programmable

VITC625

VITC525

Reserved

NABTS

Japtext

JFS

VITC/EBU time codes (Europe)

programmable

VITC/SMPTE time codes (USA)

reserved

programmable

−

US NABTS

−

programmable (A7H)

programmable

−

MOJI (Japanese)

Japanese format switch (L20/22)

Active video video component signal, active video

region (default)

18.2.4.3 Subaddress 58H

Table 184 Programmable framing code; slicer set 58H[7:0]; see Tables 44 and 183

FRAMING CODE FOR PROGRAMMABLE DATA TYPES

Default value

CONTROL BITS 7 TO 0

FC[7:0] = 40H

18.2.4.4 Subaddress 59H

Table 185 Horizontal offset for slicer; slicer set 59H and 5BH

HORIZONTAL OFFSET

Recommended value

CONTROL BITS 5BH[2:0]

CONTROL BITS 59H[7:0]

HOFF[10:8] = 3H

HOFF[7:0] = 47H

2004 Mar 16

170

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

18.2.4.5 Subaddress 5AH

Table 186 Vertical offset for slicer; slicer set 5AH and 5BH

CONTROL BIT 5BH[4]

CONTROL BITS 5AH[7:0]

VOFF[7:0]

VERTICAL OFFSET

Minimum value 0

VOFF8

00H

38H

03H

06H

Maximum value 312

Value for 50 Hz 625 lines input

Value for 60 Hz 525 lines input

18.2.4.6 Subaddress 5BH

Table 187 Field offset, and MSBs for horizontal and vertical offsets; slicer set 5BH[7:6]

See Sections 18.2.4.4 and 18.2.4.5 for HOFF[10:8] 5BH[2:0] and VOFF8[5BH[4]].

BIT DESCRIPTION SYMBOL

VALUE

FUNCTION

ﬁeld offset

FOFF

no modiﬁcation of internal ﬁeld indicator (default for 50 Hz

625 lines input sources)

invert ﬁeld indicator (default for 60 Hz 525 lines input sources)

let data unchanged (default)

recode

RECODE

convert 00H and FFH data bytes into 03H and FCH

18.2.4.7 Subaddress 5DH

Table 188 Header and data identiﬁcation (DID; ITU 656) code control; slicer set 5DH[7:0]

BIT

DESCRIPTION

SYMBOL VALUE

FUNCTION

ﬁeld ID and V-blank selection

for text output (F and V

reference selection)

FVREF

F and V output of slicer is LCR table dependent

F and V output is taken from decoder real time signals

EVEN_ITU and VBLNK_ITU

5 to 0 default; DID[5:0] = 00H

DID[5:0] 00 0000 ANC header framing; see Fig.38 and Table 50

11 1110 DID[5:0] = 3EH SAV/EAV framing, with FVREF = 1

11 1111 DID[5:0] = 3FH SAV/EAV framing, with FVREF = 0

special cases of DID

programming

18.2.4.8 Subaddress 5EH

Table 189 Sliced data identiﬁcation (SDID) code; slicer set 5EH[5:0]

BIT DESCRIPTION SYMBOL VALUE

5 to 0 SDID codes SDID[5:0] 00H

FUNCTION

default

2004 Mar 16

171

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

18.2.4.9 Subaddress 60H

Table 190 Slicer status byte 0; 60H[6:2]; read only register

BIT

DESCRIPTION

SYMBOL VALUE

FUNCTION

framing code valid

FC8V

FC7V

VPSV

PPV

no framing code (0 error) in the last frame detected

framing code with 0 error detected

no framing code (1 error) in the last frame detected

framing code with 1 error detected

no VPS in the last frame

framing code valid

VPS valid

VPS detected

PALplus valid

no PALplus in the last frame

PALplus detected

Closed Caption valid

CCV

no Closed Caption in the last frame

Closed Caption detected

18.2.4.10 Subaddresses 61H and 62H

Table 191 Slicer status byte 1; 61H[5:0] and slicer status byte 2; 62H[7:0]; read only registers

SUBADDRESS

BIT

SYMBOL

F21_N

DESCRIPTION

ﬁeld ID as seen by the VBI slicer; for ﬁeld 1: bit 5 = 0

line number

61H

4 to 0

7 to 4

3 to 0

LN[8:4]

LN[3:0]

DT[3:0]

62H

data type; according to Table 44

18.2.5 PROGRAMMING REGISTER INTERFACES AND SCALER PART

18.2.5.1 Subaddress 80H

Table 192 Global control 1; global set 80H[6:4]

SWRST moved to subaddress 88H[5]; note 1.

CONTROL BITS 6 TO 4

TASK ENABLE CONTROL

SMOD

TEB

TEA

Task of register set A is disabled

Task of register set A is enabled

Task of register set B is disabled

Task of register set B is enabled

The scaler window deﬁnes the F and V timing of the scaler output

VBI data slicer deﬁnes the F and V timing of the scaler output

Note

1. X = don’t care.

2004 Mar 16

172

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

Table 193 Global control 1; global set 80H[3:0]; note 1

CONTROL BITS 3 TO 0

I PORT AND SCALER BACK-END CLOCK SELECTION

ICKS3

ICKS2

ICKS1

ICKS0

ICLK output and back-end clock is line-locked clock LLC from decoder

ICLK output and back-end clock is XCLK from X port

ICLK output is LLC and back-end clock is LLC2 clock

Back-end clock is the ICLK input

X⁽²⁾

IDQ pin carries the data qualiﬁer

IDQ pin carries a gated back-end clock (IDQ AND CLK)

IDQ generation only for valid data

IDQ qualiﬁes valid data inside the scaling region and all data outside the

scaling region

Notes

1. Although the ICLKO I/O is independent of ICKS2 and ICKS3, this selection can only be used if ICKS2 = 1.

2. X = don’t care.

18.2.5.2 Subaddresses 83H to 87H

Table 194 X port I/O enable and output clock phase control; global set 83H[5:4]

CONTROL BITS 5 AND 4

OUTPUT CLOCK PHASE CONTROL

XPCK1

XPCK0

XCLK default output phase, recommended value

XCLK output inverted

XCLK phase shifted by about 3 ns

XCLK output inverted and shifted by about 3 ns

Table 195 X port I/O enable and output clock phase control; global set 83H[2:0]

CONTROL BITS 2 TO 0

X PORT I/O ENABLE

XRQT

XPE1

XPE0

X port output is disabled by software

X⁽¹⁾

X port output is enabled by software

X port output is enabled by pin XTRI at logic 0

X port output is enabled by pin XTRI at logic 1

XRDY output signal is A/B task ﬂag from event handler (A = 1)

XRDY output signal is ready signal from scaler path (XRDY = 1 means

SAA7108E; SAA7109E is ready to receive data)

Note

1. X = don’t care

2004 Mar 16

173

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

Table 196 I port signal deﬁnitions; global set 84H[7:6] and 86H[5]

CONTROL BITS

I PORT SIGNAL DEFINITIONS

86H[5]

84H[7:6]

IDG02 IDG01 IDG00

IGP0 is output ﬁeld ID, as deﬁned by OFIDC[90H[6]]

IGP0 is A/B task ﬂag, as deﬁned by CONLH[90H[7]]

IGP0 is sliced data ﬂag, framing the sliced VBI data at the I port

IGP0 is set to logic 0 (default polarity)

IGP0 is the output FIFO almost ﬁlled ﬂag

IGP0 is the output FIFO overﬂow ﬂag

IGP0 is the output FIFO almost full ﬂag, level to be programmed in subaddress 86H

IGP0 is the output FIFO almost empty ﬂag, level to be programmed in subaddress 86H

Table 197 I port signal deﬁnitions; global set 84H[5:4] and 86H[4]

CONTROL BITS

I PORT SIGNAL DEFINITIONS

86H[4]

84H[5:4]

IDG12 IDG11 IDG10

IGP1 is output ﬁeld ID, as deﬁned by OFIDC[90H[6]]

IGP1 is A/B task ﬂag, as deﬁned by CONLH[90H[7]]

IGP1 is sliced data ﬂag, framing the sliced VBI data at the I port

IGP1 is set to logic 0 (default polarity)

IGP1 is the output FIFO almost ﬁlled ﬂag

IGP1 is the output FIFO overﬂow ﬂag

IGP1 is the output FIFO almost full ﬂag, level to be programmed in subaddress 86H

IGP1 is the output FIFO almost empty ﬂag, level to be programmed in subaddress 86H

Table 198 I port output signal deﬁnitions; global set 84H[3:0]; note 1

CONTROL BITS 3 TO 0

I PORT OUTPUT SIGNAL DEFINITIONS

IDV1

IDV0

IDH1

IDH0

IGPH is a H-gate signal, framing the scaler output

IGPH is an extended H-gate (framing H-gate during scaler output and scaler

input H-reference outside the scaler window)

IGPH is a horizontal trigger pulse, on active going edge of H-gate

IGPH is a horizontal trigger pulse, on active going edge of extended H-gate

IGPV is a V-gate signal, framing scaled output lines

IGPV is the V-reference signal from scaler input

IGPV is a vertical trigger pulse, derived from V-gate

IGPV is a vertical trigger pulse derived from input V-reference

Note

1. X = don’t care.

2004 Mar 16

174

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

Table 199 X port signal deﬁnitions text slicer; global set 85H[7:5]; note 1

CONTROL BITS 7 TO 5

X PORT SIGNAL DEFINITIONS TEXT SLICER

ISWP1

ISWP0

ILLV

Video data limited to range 1 to 254

Video data limited to range 8 to 247

Dword byte swap, inﬂuences serial output timing

D0 D1 D2 D3

D1 D0 D3 D2

D2 D3 D0 D1

D3 D2 D1 D0

FF 00 00 SAV C_B0 Y0 C_R0 Y1

00 FF SAV 00 Y0 C_B0 Y1 C_R0

00 SAV FF 00 C_R0 Y1 C_B0 Y0

SAV 00 00 FF Y1 C_R0 Y0 C_B0

Note

1. X = don’t care.

Table 200 I port reference signal polarities; global set 85H[4:0]; note 1

CONTROL BITS 4 TO 0

I PORT REFERENCE SIGNAL POLARITIES

IG0P

IG1P

IRVP

IRHP

IDQP

IDQ at default polarity (1 = active)

IDQ is inverted

IGPH at default polarity (1 = active)

IGPH is inverted

IGPV at default polarity (1 = active)

IGPV is inverted

IGP1 at default polarity

IGP1 is inverted

IGP0 at default polarity

IGP0 is inverted

Note

1. X = don’t care.

2004 Mar 16

175

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

Table 201 I port FIFO ﬂag control and arbitration; global set 86H[7:4]; note 1

CONTROL BITS 7 TO 4

FUNCTION

VITX1

VITX0

IDG02

IDG12

See subaddress 84H: IDG11 and IDG10

See subaddress 84H: IDG01 and IDG00

I port signal deﬁnitions

I port data output inhibited

Only video data are transferred

Only text data are transferred (no EAV, SAV will occur)

Text and video data are transferred, text has priority

Note

1. X = don’t care.

Table 202 I port FIFO ﬂag control and arbitration; global set 86H[3:0]; note 1

CONTROL BITS 3 TO 0

I PORT FIFO FLAG CONTROL AND ARBITRATION

FFL1

FFL0

FEL1

FEL0

FAE FIFO ﬂag almost empty level

<16 Dwords

<8 Dwords

<4 Dwords

0 Dwords

FAF FIFO ﬂag almost full level

≥16 Dwords

≥24 Dwords

≥28 Dwords

32 Dwords

Note

1. X = don’t care.

2004 Mar 16

176

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

Table 203 I port I/O enable, output clock and gated clock phase control; global set 87H[7:4]; note 1

CONTROL BITS 7 TO 4

OUTPUT CLOCK AND GATED CLOCK PHASE CONTROL

IPCK3⁽²⁾IPCK2⁽²⁾

IPCK1

IPCK0

ICLK default output phase

ICLK phase shifted by ¹⁄₂clock cycle

recommended for ICKS1 = 1

and ICKS0 = 0 (subaddress 80H)

ICLK phase shifted by about 3 ns

ICLK phase shifted by ¹⁄₂clock cycle + approximately

3 ns alternatively to setting ‘01’

IDQ = gated clock default output phase

IDQ = gated clock phase shifted by ¹⁄₂clock cycle

recommended

for gated clock output

IDQ = gated clock phase shifted by approximately 3 ns

IDQ = gated clock phase shifted by ¹⁄₂clock cycle + approximately

3 ns

alternatively to setting ‘01’

Notes

1. X = don’t care.

2. IPCK3 and IPCK2 only affects the gated clock (subaddress 80H, bit ICKS2 = 1).

Table 204 I port I/O enable, output clock and gated clock phase control; global set 87H[1:0]

CONTROL BITS 1 AND 0

I PORT I/O ENABLE

IPE1

IPE0

I port output is disabled by software

I port output is enabled by software

I port output is enabled by pin ITRI at logic 0

I port output is enabled by pin ITRI at logic 1

2004 Mar 16

177

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

18.2.5.3 Subaddress 88H

Table 205 Power save control; global set 88H[7:4]; note 1

CONTROL BITS 7 TO 4

POWER SAVE CONTROL

CH4EN

CH2EN SWRST⁽²⁾DPROG

DPROG = 0 after reset

DPROG = 1 can be used to assign that the device has been

programmed; this bit can be monitored in the scalers status byte,

bit PRDON; if DPROG was set to logic 1 and PRDON status bit

shows a logic 0 a power-up or start-up fail has occurred

Scaler path is reset to its idle state, software reset

Scaler is switched back to operation

AD1x analog channel is in power-down mode

AD1x analog channel is active

AD2x analog channel is in power-down mode

AD2x analog channel is active

Notes

1. X = don’t care.

2. Bit SWRST is now located here.

Table 206 Power save control; global set 88H[3] and 88H[1:0]; note 1

CONTROL BITS 3, 1 AND 0

POWER SAVE CONTROL

SLM3

SLM1

SLM0

Decoder and VBI slicer are in operational mode

Decoder and VBI slicer are in Power-down mode; scaler only operates, if scaler

input and ICLK source is the X port (refer to subaddresses 80H and 91H/C1H)

Scaler is in operational mode

Scaler is in Power-down mode; scaler in Power-down stops I port output

Audio clock generation active

Audio clock generation in Power-down and output disabled

Note

1. X = don’t care.

2004 Mar 16

178

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

18.2.5.4 Subaddress 8FH

Table 207 Status information scaler part; 8FH[7:0]; read only register

I²C-BUS

STATUS BIT

BIT

FUNCTION⁽¹⁾

XTRI

status on input pin XTRI, if not used for 3-state control, usable as hardware ﬂag for software

use

ITRI

status on input pin ITRI, if not used for 3-state control, usable as hardware ﬂag for software

use

FFIL

status of the internal ‘FIFO almost ﬁlled’ ﬂag

FFOV

status of the internal ‘FIFO overﬂow’ ﬂag

PRDON

ERROF

copy of bit DPROG, can be used to detect power-up and start-up fails

error ﬂag of scalers output formatter, normally set, if the output processing needs to be

interrupted, due to input/output data rate conﬂicts, e.g. if output data rate is much too low and

all internal FIFO capacity used

FIDSCI

status of the ﬁeld sequence ID at the scalers input

FIDSCO

status of the ﬁeld sequence ID at the scalers output, scaler processing dependent

Note

1. Status information is unsynchronized and shows the actual status at the time of I²C-bus read.

18.2.5.5 Subaddresses 90H and C0H

Table 208 Task handing control; register set A [90H[7:6]] and B [C0H[7:6]]; note 1

CONTROL BITS 7 AND 6

EVENT HANDLER CONTROL

Output ﬁeld ID is ﬁeld ID from scaler input

CONLH

OFIDC

Output ﬁeld ID is task status ﬂag, which changes every time an selected task

is activated (not synchronized to input ﬁeld ID)

Scaler SAV/EAV byte bit 7 and task ﬂag = 1, default

Scaler SAV/EAV byte bit 7 and task ﬂag = 0

Note

1. X = don’t care.

Table 209 Task handling control; register set A [90H[5:3]] and B [C0H[5:3]]

CONTROL BITS 5 TO 3

EVENT HANDLER CONTROL

FSKP2

FSKP1

FSKP0

Active task is carried out directly

1 ﬁeld is skipped before active task is carried out

... ﬁelds are skipped before active task is carried out

6 ﬁelds are skipped before active task is carried out

7 ﬁelds are skipped before active task is carried out

...

2004 Mar 16

179

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

Table 210 Task handling control; register set A [90H[2:0]] and B [C0H[2:0]]; note 1

CONTROL BITS 2 TO 0

EVENT HANDLER CONTROL

RPTSK

STRC1

STRC0

Event handler triggers immediately after ﬁnishing a task

Event handler triggers with next V-sync

Event handler triggers with ﬁeld ID = 0

Event handler triggers with ﬁeld ID = 1

If active task is ﬁnished, handling is taken over by the next task

Active task is repeated once, before handling is taken over by the next task

Note

1. X = don’t care.

18.2.5.6 Subaddresses 91H to 93H

Table 211 X port formats and conﬁguration; register set A [91H[7:3]] and B [C1H[7:3]]; note 1

CONTROL BITS 7 TO 3

HLDFV SCSRC1 SCSRC0 SCRQE

SCALER INPUT FORMAT AND CONFIGURATION SOURCE

SELECTION

CONLV

Only if XRQT[83H[2]] = 1: scaler input source reacts on

SAA7108E; SAA7109E request

Scaler input source is a continuous data stream, which cannot

be interrupted (must be logic 1 if SAA7108E; SAA7109E

decoder part is source of scaler or XRQT[83H[2]] = 0)

Scaler input source is data from decoder, data type is

provided according to Table 44

Scaler input source is Y-C_B-C_Rdata from X port

Scaler input source is raw digital CVBS from selected analog

channel, for backward compatibility only, further use is not

recommended

Scaler input source is raw digital CVBS (or 16-bit Y + C_B-C_R, if

no 16-bit output are active) from X port

SAV/EAV code bits 6 and 5 (F and V) may change between

SAV and EAV

SAV/EAV code bits 6 and 5 (F and V) are synchronized to

scalers output line start

SAV/EAV code bit 5 (V) and V gate on pin IGPV as generated

by the internal processing; see Fig.44

SAV/EAV code bit 5 (V) and V gate are inverted

Note

1. X = don’t care.

2004 Mar 16

180

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

Table 212 X port formats and conﬁguration; register set A [91H[2:0]] and B [C1H[2:0]]; note 1

CONTROL BITS 2 TO 0

SCALER INPUT FORMAT AND CONFIGURATION FORMAT

CONTROL

FSC2⁽²⁾

FSC1⁽²⁾

FSC0

Input is Y-C_B-C_R4 : 2 : 2 like sampling scheme

Input is Y-C_B-C_R4 : 1 : 1 like sampling scheme

Chroma is provided every line, default

Chroma is provided every 2nd line

Chroma is provided every 3rd line

Chroma is provided every 4th line

Notes

1. X = don’t care.

2. FSC2 and FSC1 only to be used, if X port input source don’t provide chroma information for every input line. X port

input stream must contain dummy chroma bytes.

Table 213 X port input reference signal deﬁnitions; register set A [92H[7:4]] and B [C2H[7:4]]; note 1

CONTROL BITS 7 TO 4

X PORT INPUT REFERENCE SIGNAL DEFINITIONS

XFDV

XFDH

XDV1

XDV0

Rising edge of XRV input and decoder V123 is vertical reference

Falling edge of XRV input and decoder V123 is vertical reference

XRV is a V-sync or V gate signal

XRV is a frame sync, V pulses are generated internally on both edges of

FS input

X port ﬁeld ID is state of XRH at reference edge on XRV (deﬁned by

XFDV)

Field ID (decoder and X port ﬁeld ID) is inverted

Reference edge for ﬁeld detection is falling edge of XRV

Reference edge for ﬁeld detection is rising edge of XRV

Note

1. X = don’t care.

2004 Mar 16

181

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

Table 214 X port input reference signal deﬁnitions; register set A [92H[3:0]] and B [C2H[3:0]]; note 1

CONTROL BITS 3 TO 0

X PORT INPUT REFERENCE SIGNAL DEFINITIONS

XCODE

XDH

XDQ

XCKS

XCLK input clock and XDQ input qualiﬁer are needed

Data rate is deﬁned by XCLK only, no XDQ signal used

Data are qualiﬁed at XDQ input at logic 1

Data are qualiﬁed at XDQ input at logic 0

Rising edge of XRH input is horizontal reference

Falling edge of XRH input is horizontal reference

Reference signals are taken from XRH and XRV

Reference signals are decoded from EAV and SAV

Note

1. X = don’t care.

Table 215 I port output format and conﬁguration; register set A [93H[7:5]] and B [C3H[7:5]]; note 1

CONTROL BITS 7 TO 5

I PORT OUTPUT FORMATS AND CONFIGURATION

ICODE

I8_16

FYSK

All lines will be output

Skip the number of leading Yonly lines, as deﬁned by FOI1 and FOI0

Dwords are transferred byte wise, see subaddress 85H bits ISWP1 and ISWP0

Dwords are transferred 16-bit word wise via IPD and HPD, see subaddress 85H bits

ISWP1 and ISWP0

No ITU 656 like SAV/EAV codes are available

ITU 656 like SAV/EAV codes are inserted in the output data stream, framed by a

qualiﬁer

Note

1. X = don’t care.

2004 Mar 16

182

Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

Table 216 I port output format and conﬁguration; register set A [93H[4:0]] and B [C3H[4:0]]; note 1

CONTROL BITS 4 TO 0

I PORT OUTPUT FORMATS AND CONFIGURATION

FOI1

FOI0

FSI2

FSI1

FSI0

4 : 2 : 2 Dword formatting

4 : 1 : 1 Dword formatting

4 : 2 : 0, only every 2nd line Y + C_B-C_Routput, in between

Yonly output

4 : 1 : 0, only every 4th line Y + C_B-C_Routput, in between

Yonly output

Yonly

Not deﬁned

No leading Yonly line, before 1st Y + C_B-C_Rline is output

1 leading Y only line, before 1st Y + C_B-C_Rline is output

2 leading Y only lines, before 1st Y + C_B-C_Rline is output

3 leading Y only lines, before 1st Y + C_B-C_Rline is output

Note

1. X = don’t care.

18.2.5.7 Subaddresses 94H to 9BH

Table 217 Horizontal input window start; register set A [94H[7:0]; 95H[3:0]] and B [C4H[7:0]; C5H[3:0]]

CONTROL BITS

HORIZONTAL INPUT

ACQUISITION WINDOW

DEFINITION OFFSET IN

X (HORIZONTAL) DIRECTION⁽¹⁾

A [95H[3:0]]

B [C5H[3:0]]

A [94H[7:0]]

B [C4H[7:0]]

XO11 XO10 XO9 XO8 XO7 XO6 XO5 XO4 XO3 XO2 XO1 XO0

A minimum of 2 should be kept, due

to a line counting mismatch

Odd offsets are changing the

C_B-C_Rsequence in the output

stream to C_R-C_Bsequence

Maximum possible pixel

offset = 4095

Note

1. Reference for counting are luminance samples.

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PC-CODEC

SAA7108E; SAA7109E

Table 218 Horizontal input window length; register set A [96H[7:0]; 97H[3:0]] and B [C6H[7:0]; C7H[3:0]]

CONTROL BITS

A [96H[7:0]]

HORIZONTAL INPUT

ACQUISITION WINDOW

DEFINITION INPUT WINDOW

LENGTH IN X (HORIZONTAL)

DIRECTION⁽¹⁾

A [97H[3:0]]

B [C7H[3:0]]

B [C6H[7:0]]

XS11 XS10 XS9 XS8 XS7 XS6 XS5 XS4 XS3 XS2 XS1 XS0

No output

Odd lengths are allowed, but will be

rounded up to even lengths

Maximum possible number of input

pixels = 4095

Note

1. Reference for counting are luminance samples.

Table 219 Vertical input window start; register set A [98H[7:0]; 99H[3:0]] and B [C8H[7:0]; C9H[3:0]]

CONTROL BITS

VERTICAL INPUT ACQUISITION

WINDOW DEFINITION OFFSET IN

Y (VERTICAL) DIRECTION⁽¹⁾

A [99H[3:0]]

B [C9H[3:0]]

A [98H[7:0]]

B [C8H[7:0]]

YO11 YO10 YO9 YO8 YO7 YO6 YO5 YO4 YO3 YO2 YO1 YO0

Line offset = 0

Line offset = 1

Maximum line offset = 4095

Note

1. For trigger condition: STRC[1:0] 90H[1:0] = 00; YO + YS > (number of input lines per field − 2), will result in field

dropping. Other trigger conditions: YO > (number of input lines per field − 2), will result in field dropping.

Table 220 Vertical input window length; register set A [9AH[7:0]; 9BH[3:0]] and B [CAH[7:0]; CBH[3:0]]

CONTROL BITS

VERTICAL INPUT ACQUISITION

WINDOW DEFINITION INPUT

WINDOW LENGTH IN

Y (VERTICAL) DIRECTION⁽¹⁾

A [9BH[3:0]]

B [CBH[3:0]]

A [9AH[7:0]]

B [CAH[7:0]]

YS11 YS10 YS9 YS8 YS7 YS6 YS5 YS4 YS3 YS2 YS1 YS0

No input lines

1 input line

Maximum possible number of input

lines = 4095

Note

1. For trigger condition: STRC[1:0] 90H[1:0] = 00; YO + YS > (number of input lines per field − 2), will result in field

dropping. Other trigger conditions: YS > (number of input lines per field − 2), will result in field dropping.

2004 Mar 16

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Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

18.2.5.8 Subaddresses 9CH to 9FH

Table 221 Horizontal output window length; register set A [9CH[7:0]; 9DH[3:0]] and B [CCH[7:0]; CDH[3:0]]

CONTROL BITS

A [9CH[7:0]]

HORIZONTAL OUTPUT

ACQUISITION WINDOW

DEFINITION NUMBER OF

DESIRED OUTPUT PIXEL IN

X (HORIZONTAL) DIRECTION⁽¹⁾

A [9DH[3:0]]

B [CDH[3:0]]

B [CCH[7:0]]

XD11 XD10 XD9 XD8 XD7 XD6 XD5 XD4 XD3 XD2 XD1 XD0

No output

Odd lengths are allowed, but will be

ﬁlled up to even lengths

Maximum possible number of input

pixels = 4095; note 2

Notes

1. Reference for counting are luminance samples.

2. If the desired output length is greater than the number of scaled output pixels, the last scaled pixel is repeated.

Table 222 Vertical output window length; register set A [9EH[7:0]; 9FH[3:0]] and B [CEH[7:0]; CFH[3:0]]

CONTROL BITS

VERTICAL OUTPUT ACQUISITION

WINDOW DEFINITION NUMBER

OF DESIRED OUTPUT LINES IN

Y (VERTICAL) DIRECTION

A [9FH[3:0]]

B [CFH[3:0]]

A [9EH[7:0]]

B [CEH[7:0]]

YD11 YD10 YD9 YD8 YD7 YD6 YD5 YD4 YD3 YD2 YD1 YD0

No output

1 pixel

Maximum possible number of output

lines = 4095; note 1

Note

1. If the desired output length is greater than the number of scaled output lines, the processing is cut.

18.2.5.9 Subaddresses A0H to A2H

Table 223 Horizontal prescaling; register set A [A0H[5:0]] and B [D0H[5:0]]

CONTROL BITS 5 TO 0

HORIZONTAL INTEGER PRESCALING RATIO (XPSC)

XPSC5 XPSC4 XPSC3 XPSC2 XPSC1 XPSC0

Not allowed

Downscale = 1

Downscale = ¹⁄₂

...

Downscale = ¹⁄₆₃

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Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

Table 224 Accumulation length; register set A [A1H[5:0]] and B [D1H[5:0]]

CONTROL BITS 5 TO 0

HORIZONTAL PRESCALER ACCUMULATION

SEQUENCE LENGTH (XACL)

XACL5 XACL4 XACL3 XACL2 XACL1 XACL0

Accumulation length = 1

Accumulation length = 2

...

Accumulation length = 64

Table 225 Prescaler DC gain and FIR preﬁlter control; register set A [A2H[7:4]] and B [D2H[7:4]]; note 1

CONTROL BITS 7 TO 4

FIR PREFILTER CONTROL

PFUV1

PFUV0

PFY1

PFY0

Luminance FIR ﬁlter bypassed

H_y(z) = ¹⁄₄(1 2 1)

H_y(z) = ¹⁄₈(−1 1 1.75 4.5 1.75 1 −1)

H_y(z) = ¹⁄₈(1 2 2 2 1)

Chrominance FIR ﬁlter bypassed

H_uv(z) = ¹⁄₄(1 2 1)

H_uv(z) = ¹⁄₃₂(3 8 10 8 3)

H_uv(z) = ¹⁄₈(1 2 2 2 1)

Note

1. X = don’t care.

Table 226 Prescaler DC gain and FIR preﬁlter control; register set A [A2H[3:0]] and B [D2H[3:0]]; note 1

CONTROL BITS 3 TO 0

PRESCALER DC GAIN

XC2_1

XDCG2

XDCG1

XDCG0

Prescaler output is renormalized by gain factor = 1

Prescaler output is renormalized by gain factor = ¹⁄₂

Prescaler output is renormalized by gain factor = ¹⁄₄

Prescaler output is renormalized by gain factor = ¹⁄₈

Prescaler output is renormalized by gain factor = ¹⁄₁₆

Prescaler output is renormalized by gain factor = ¹⁄₃₂

Prescaler output is renormalized by gain factor = ¹⁄₆₄

Prescaler output is renormalized by gain factor = ¹⁄₁₂₈

Weighting of all accumulated samples is factor 1;

e.g. XACL = 4

sequence 1 + 1 + 1 + 1 + 1

Weighting of samples inside sequence is factor 2;

e.g. XACL = 4

sequence 1 + 2 + 2 + 2 + 1

Note

1. X = don’t care.

2004 Mar 16

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Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

18.2.5.10 Subaddresses A4H to A6H

Table 227 Luminance brightness control; register set A [A4H[7:0]] and B [D4H[7:0]]

CONTROL BITS 7 TO 0

LUMINANCE

BRIGHTNESS CONTROL

BRIG7

BRIG6

BRIG5

BRIG4

BRIG3

BRIG2

BRIG1

BRIG0

Value = 0

Nominal value = 128

Value = 255

Table 228 Luminance contrast control; register set A [A5H[7:0]] and B [D5H[7:0]]

CONTROL BITS 7 TO 0

CONT7 CONT6 CONT5 CONT4 CONT3 CONT2 CONT1 CONT0

LUMINANCE CONTRAST

CONTROL

Gain = 0

Gain = ¹⁄₆₄

Nominal gain = 64

Gain = ¹²⁷

⁄

Table 229 Chrominance saturation control; register set A [A6H[7:0]] and B [D6H[7:0]]

CONTROL BITS 7 TO 0

CHROMINANCE

SATURATION CONTROL

SATN7

SATN6

SATN5

SATN4

SATN3

SATN2

SATN1

SATN0

Gain = 0

Gain = ¹⁄₆₄

Nominal gain = 64

Gain = ¹²⁷

⁄

18.2.5.11 Subaddresses A8H to AEH

Table 230 Horizontal luminance scaling increment; register set A [A8H[7:0]; A9H[7:0]] and B [D8H[7:0]; D9H[7:0]]

CONTROL BITS

HORIZONTAL LUMINANCE

SCALING INCREMENT

A [A9H[7:4]]

B [D9H[7:4]]

A [A9H[3:0]]

B [D9H[3:0]]

A [A8H[7:4]]

B [D8H[7:4]]

A [A8H[3:0]]

B [D8H[3:0]]

XSCY[15:12]⁽¹⁾

XSCY[11:8]

XSCY[7:4]

XSCY[3:0]

Scale = ¹⁰²⁴⁄₁(theoretical) zoom

0000

0001

0000

0010

0000

0110

Scale = ¹⁰²⁴

data path structure

Scale = ¹⁰²⁴

₁₀₂₃zoom

Scale = 1, equals 1024

⁄₂₉₄, lower limit deﬁned by

⁄

0000

0001

0011

0100

1111

0000

1111

0000

0001

1111

Scale = ¹⁰²⁴

⁄

₁₀₂₅downscale

₈₁₉₁downscale

⁄

Note

1. Bits XSCY[15:13] are reserved and are set to logic 0.

2004 Mar 16

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Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

Table 231 Horizontal luminance phase offset; register set A [AAH[7:0]] and B [DAH[7:0]]

CONTROL BITS 7 TO 0

HORIZONTAL LUMINANCE PHASE

OFFSET

XPHY7 XPHY6 XPHY5 XPHY4 XPHY3 XPHY2 XPHY1 XPHY0

Offset = 0

Offset = ¹⁄₃₂pixel

Offset = ³²

Offset = ²⁵⁵

⁄

₃₂= 1 pixel

₃₂pixel

⁄

Table 232 Horizontal chrominance scaling increment; register set A [ACH[7:0]; ADH[7:0]] and B [DCH[7:0]; DDH[7:0]]

CONTROL BITS

HORIZONTAL CHROMINANCE

SCALING INCREMENT

A [ADH[7:4]]

B [DDH[7:4]]

A [ADH[3:0]]

B [DDH[3:0]]

A [ACH[7:4]]

B [DCH[7:4]]

A [ACH[3:0]]

B [DCH[3:0]]

XSCC[15:12]⁽¹⁾

XSCC[11:8]

XSCC[7:4]

XSCC[3:0]

This value must be set to the

luminance value ¹⁄₂XSCY[15:0]

0000

0001

0000

1111

0000

1111

0000

0001

1111

Note

1. Bits XSCC[15:13] are reserved and are set to logic 0.

Table 233 Horizontal chrominance phase offset; register set A [AEH[7:0]] and B [DEH[7:0]]

CONTROL BITS 7 TO 0

HORIZONTAL CHROMINANCE

PHASE OFFSET

XPHC7 XPHC6 XPHC5 XPHC4 XPHC3 XPHC2 XPHC1 XPHC0

This value must be set to ¹⁄₂XPHY[7:0]

18.2.5.12 Subaddresses B0H to BFH

Table 234 Vertical luminance scaling increment; register set A [B0H[7:0]; B1H[7:0]] and B [E0H[7:0]; E1H[7:0]]

CONTROL BITS

VERTICAL LUMINANCE SCALING

INCREMENT

A [B1H[7:4]]

B [E1H[7:4]]

A [B1H[3:0]]

B [E1H[3:0]]

A [B0H[7:4]]

B [E0H[7:4]]

A [B0H[3:0]]

B [E0H[3:0]]

YSCY[15:12]

YSCY[11:8]

YSCY[7:4]

YSCY[3:0]

Scale = ¹⁰²⁴⁄₁(theoretical) zoom

0000

1111

0000

0011

0100

1111

0000

1111

0000

1111

0001

1111

0000

0001

1111

Scale = ¹⁰²⁴

Scale = 1, equals 1024

Scale = ¹⁰²⁴

₁₀₂₅downscale

⁄₁₀₂₃zoom

⁄

Scale = ¹⁄_63.999downscale

2004 Mar 16

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Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

Table 235 Vertical chrominance scaling increment; register set A [B2H[7:0]; B3H[7:0]] and B [E2H[7:0]; E3H[7:0]]

CONTROL BITS

VERTICAL CHROMINANCE

SCALING INCREMENT

A [B3H[7:4]]

B [E3H[7:4]]

A [B3H[3:0]]

B [E3H[3:0]]

A [B2H[7:4]]

B [E2H[7:4]]

A [B2H[3:0]]

B [E2H[3:0]]

YSCC[15:12]

YSCC[11:8]

YSCC[7:4]

YSCC[3:0]

This value must be set to the

luminance value YSCY[15:0]

0000

1111

0000

1111

0000

1111

0001

1111

Table 236 Vertical scaling mode control; register set A [B4H[4 and 0]] and B [E4H[4 and 0]]; note 1

CONTROL BITS 4 AND 0

VERTICAL SCALING MODE CONTROL

YMIR

YMODE

Vertical scaling performs linear interpolation between lines

Vertical scaling performs higher order accumulating interpolation, better alias

suppression

No mirroring

Lines are mirrored

Note

1. X = don’t care.

Table 237 Vertical chrominance phase offset ‘00’; register set A [B8H[7:0]] and B [E8H[7:0]]

CONTROL BITS 7 TO 0

VERTICAL CHROMINANCE PHASE

OFFSET

YPC07 YPC06 YPC05 YPC04 YPC03 YPC02 YPC01 YPC00

Offset = 0

Offset = ³²

Offset = ²⁵⁵

⁄

₃₂= 1 line

₃₂lines

⁄

Table 238 Vertical luminance phase offset ‘00’; register set A [BCH[7:0]] and B [ECH[7:0]]

CONTROL BITS 7 TO 0

VERTICAL LUMINANCE PHASE

OFFSET

YPY07 YPY06 YPY05 YPY04 YPY03 YPY02 YPY01 YPY00

Offset = 0

Offset = ³²

Offset = ²⁵⁵

⁄

₃₂= 1 line

₃₂lines

⁄

2004 Mar 16

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Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

19 PROGRAMMING START SET-UP OF DIGITAL VIDEO DECODER PART

19.1 Decoder part

The given values force the following behaviour of the SAA7108E; SAA7109E decoder part:

• The analog input AI11 expects an NTSC M, PAL B, D, G, H and I or SECAM signal in CVBS format; analog anti-alias

filter and AGC active

• Automatic field detection enabled

• Standard ITU 656 output format enabled on the expansion port

• Contrast, brightness and saturation control in accordance with ITU standards

• Adaptive comb filter for luminance and chrominance activated

• Pins LLC, LLC2, XTOUTd, RTS0, RTS1 and RTCO are set to 3-state.

Table 239 Decoder part start set-up values for the three main standards

VALUES (HEX)

SUB

ADDRESS

(HEX)

FUNCTION

BIT NAME⁽¹⁾

PAL B, D,

G, H AND I

NTSC M

SECAM

chip version

ID7 to ID4

read only

increment delay

X, X, X, X, IDEL3 to IDEL0

analog input control 1

FUSE1, FUSE0, GUDL1, GUDL0 and

MODE3 to MODE0

analog input control 2

X, HLNRS, VBSL, WPOFF, HOLDG,

GAFIX, GAI28 and GAI18

analog input control 3

analog input control 4

horizontal sync start

horizontal sync stop

sync control

GAI17 to GAI10

GAI27 to GAI20

HSB7 to HSB0

HSS7 to HSS0

AUFD, FSEL, FOET, HTC1, HTC0,

HPLL, VNOI1 and VNOI0

luminance control

BYPS, YCOMB, LDEL, LUBW and

LUFI3 to LUFI0

luminance brightness

control

DBRI7 to DBRI0

DCON7 to DCON0

DSAT7 to DSAT0

luminance contrast

control

chrominance saturation

control

chrominance hue control HUEC7 to HUEC0

chrominance control 1 CDTO, CSTD2 to CSTD0, DCVF, FCTC,

X and CCOMB

chrominance gain control ACGC and CGAIN6 to CGAIN0

chrominance control 2

OFFU1, OFFU0, OFFV1, OFFV0,

CHBW and LCBW2 to LCBW0

mode/delay control

COLO, RTP1, HDEL1, HDEL0, RTP0

and YDEL2 to YDEL0

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PC-CODEC

SAA7108E; SAA7109E

VALUES (HEX)

PAL B, D,

SUB

ADDRESS

(HEX)

FUNCTION

BIT NAME⁽¹⁾

NTSC M

SECAM

G, H AND I

RT signal control

RTSE13 to RTSE10 and

RTSE03 to RTSE00

RT/X port output control

RTCE, XRHS, XRVS1, XRVS0, HLSEL

and OFTS2 to OFTS0

analog/ADC/compatibility CM99, UPTCV, AOSL1, AOSL0,

control XTOUTE, OLDSB, APCK1 and APCK0

VGATE start, FID change VSTA7 to VSTA0

VGATE stop

VSTO7 to VSTO0

miscellaneous, VGATE

conﬁguration and MSBs

LLCE, LLC2E, X, X, X, VGPS,

VSTO8 and VSTA8

raw data gain control

raw data offset control

RAWG7 to RAWG0

RAWO7 to RAWO0

X, X, X, X, X, X, X, X

1A to 1E reserved

status byte video decoder INTL, HLVLN, FIDT, GLIMT, GLIMB,

(OLDSB = 0) WIPA, COPRO and RDCAP

read only

Note

1. All X values must be set to logic 0.

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PC-CODEC

SAA7108E; SAA7109E

19.2 Audio clock generation part

The given values force the following behaviour of the SAA7108E; SAA7109E audio clock generation part:

• Used crystal is 24.576 MHz

• Expected field frequency is 59.94 Hz (e.g. NTSC M standard)

• Generated audio master clock frequency at pin AMCLK is 256 × 44.1 kHz = 11.2896 MHz

• AMCLK is externally connected to AMXCLK (short-cut between pins K12 and J12)

• ASCLK = 32 × 44.1 kHz = 1.4112 MHz

• ALRCLK is 44.1 kHz.

Table 240 Audio clock part set-up values

SUB

ADDRESS

(HEX)

START VALUES

BIT NAME⁽¹⁾

ACPF7 to ACPF0

HEX

audio master clock cycles per

ﬁeld; bits 7 to 0

audio master clock cycles per

ﬁeld; bits 15 to 8

ACPF15 to ACPF8

audio master clock cycles per

ﬁeld; bits 17 and 16

X, X, X, X, X, X, ACPF17 and

ACPF16

reserved

X, X, X, X, X, X, X, X

ACNI7 to ACNI0

audio master clock nominal

increment; bits 7 to 0

audio master clock nominal

increment; bits 15 to 8

ACNI15 to ACNI8

audio master clock nominal

increment; bits 21 to 16

X, X, ACNI21 to ACNI16

reserved

X, X, X, X, X, X, X, X

X, X, SDIV5 to SDIV0

X, X, LRDIV5 to LRDIV0

clock ratio AMXCLK to ASCLK

clock ratio ASCLK to ALRCLK

audio clock generator basic

set-up

X, X, X, X, APLL, AMVR,

LRPH, SCPH

3B to 3F reserved

X, X, X, X, X, X, X, X

Note

1. All X values must be set to logic 0.

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Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

19.3 Data slicer and data type control part

The given values force the following behaviour of the SAA7108E; SAA7109E VBI data slicer part:

• Closed captioning data is expected at line 21 of field 1 (60 Hz/525 line system)

• All other lines are processed as active video

• Sliced data are framed by ITU 656 like SAV/EAV sequence (DID[5:0] = 3EH

MSB of SAV/EAV = 1).

Table 241 Data slicer start set-up values

SUB

ADDRESS

(HEX)

START VALUES

slicer control 1

BIT NAME⁽¹⁾

HEX

X, HAM_N, FCE, HUNT_N, X, X,

X, X

41 to 53 line control register 2 to 20

54 line control register 21

55 to 57 line control register 22 to 24

LCRn_7 to LCRn_0 (n = 2 to 20)

LCR21_7 to LCR21_0

LCRn_7 to LCRn_0 (n = 22 to 24)

FC7 to FC0

programmable framing code

horizontal offset for slicer

vertical offset for slicer

HOFF7 to HOFF0

VOFF7 to VOFF0

06⁽²⁾

83⁽²⁾

ﬁeld offset and MSBs for

FOFF, RECODE, X, VOFF8, X,

HOFF10 to HOFF8

horizontal and vertical offset

reserved

X, X, X, X, X, X, X, X

header and data identiﬁcation

code control

FVREF, X, DID5 to DID0

sliced data identiﬁcation code

reserved

X, X, SDID5 to SDID0

X, X, X, X, X, X, X, X

slicer status byte 0

−, FC8V, FC7V, VPSV, PPV, CCV,

−, −

read-only register

slicer status byte 1

slicer status byte 2

−, −, F21_N, LN8 to LN4

read-only register

LN3 to LN0, DT3 to DT0

Notes

1. All X values must be set to logic 0.

2. Changes for 50 Hz/625 line systems: subaddress 5AH = 03H and subaddress 5BH = 03H.

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SAA7108E; SAA7109E

19.4 Scaler and interfaces

19.4.1 TRIGGER CONDITION

Table 242 shows some examples for the scaler

programming where:

For trigger condition STRC[1:0] 90H[1:0] not equal ‘00’.

If the value of (YO + YS) is ≥262 (NTSC), and 312 (PAL)

the output field rate is reduced to 30 Hz and 25 Hz

respectively.

• prsc = prescale ratio

• fisc = fine scale ratio

• vsc = vertical scale ratio.

Horizontal and vertical offsets (XO and YO) have to be

used to adjust the displayed video in the display window.

As this adjustment is application dependent, the listed

values are only dummy values.

number of input pixel

number of output pixel

The ratio is defined as:

----------------------------------------------------------

In the following settings the VBI data slicer is inactive.

To activate the VBI data slicer, VITX[1:0] 86H[7:6] has to

be set to ‘11’. Depending on the VBI data slicer settings,

the sliced VBI data is inserted after the end of the scaled

video lines, if the regions of the VBI data slicer and scaler

overlap.

19.4.2 MAXIMUM ZOOM FACTOR

The maximum zoom factor is dependent on the back-end

data rate and is therefore back-end clock and data format

dependent (8 or 16-bit output). The maximum horizontal

zoom is limited to approximately 3.5, due to internal data

path restrictions.

To compensate for the running-in of the vertical scaler, the

vertical input window lengths are extended by

2 to 290 lines, respectively 242 lines for XS, but the scaler

increment calculations are done with 288, respectively

240 lines.

19.4.3 EXAMPLES

Table 242 Example of conﬁgurations

EXAMPLE

NUMBER

INPUT

WINDOW WINDOW

OUTPUT

SCALE

RATIOS

SCALER SOURCE AND REFERENCE EVENTS

analog input to 8-bit I port output, with SAV/EAV codes, 8-bit

serial byte stream decoder output at X port; acquisition trigger

at falling edge vertical and rising edge horizontal reference

signal; H and V gates on IGPH and IGPV, IGP0 = VBI sliced

data ﬂag, IGP1 = FIFO almost full, level ≥24, IDQ qualiﬁer

logic 1 active

720 × 240 720 × 240 prsc = 1;

ﬁsc = 1;

vsc = 1

analog input to 16-bit output, without SAV/EAV codes, Yon

I port, C_B-C_Ron H port and decoder output at X port;

acquisition trigger at falling edge vertical and rising edge

horizontal reference signal; H and V pulses on IGPH and IGPV,

output FID on IGP0, IGP1 ﬁxed to logic 1, IDQ qualiﬁer logic 0

active

704 × 288 768 × 288 prsc = 1;

ﬁsc = 0.91667;

vsc = 1

X port input 8 bit with SAV/EAV codes, no reference signals on 720 × 240 352 × 288 prsc = 2;

XRH and XRV, XCLK as gated clock; ﬁeld detection and

acquisition trigger on different events; acquisition triggers at

rising edge vertical and rising edge horizontal; I port output

8-bit with SAV/EAV codes like example number 1;

see Table 243

ﬁsc = 1.022;

vsc = 0.8333

X port and H port for 16-bit Y-C_B-C_R4 : 2 : 2 input (if no 16-bit 720 × 288 200 × 80 prsc = 2;

output selected); XRH and XRV as references; ﬁeld detection

and acquisition trigger at falling edge of vertical and rising edge

of horizontal; I port output 8-bit with SAV/EAV codes, but Yonly

output

ﬁsc = 1.8;

vsc = 3.6

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Product speciﬁcation

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Table 243 Scaler and interface conﬁguration examples

I²C-BUS

ADDRESS

(HEX)

EXAMPLE 1 EXAMPLE 2 EXAMPLE 3 EXAMPLE 4

HEX DEC HEX DEC HEX DEC HEX DEC

MAIN FUNCTION

Global settings

task enable, IDQ and back-end clock

deﬁnition

−

XCLK output phase and X port output enable

−

IGPH, IGPV, IGP0 and IGP1 output deﬁnition A0

signal polarity control and I port byte

swapping

FIFO ﬂag thresholds and video/text

arbitration

−

ICLK and IDQ output phase and I port enable 01

power save control and software reset F0

−

Task A: scaler input conﬁguration and output format settings

task handling

−

scaler input source and format deﬁnition

reference signal deﬁnition at scaler input

I port output formats and conﬁguration

Input and output window deﬁnition

horizontal input offset (XO)

−

horizontal input (source) window length (XS)

vertical input offset (YO)

720

−

704

−

720

−

720

−

vertical input (source) window length (YS)

242

−

290

−

242

−

290

−

horizontal output (destination) window length

(XD)

720

−

768

−

352

−

200

−

vertical output (destination) window length

(YD)

240

−

288

−

288

−

Preﬁltering and prescaling

integer prescale (value ‘00’ not allowed)

−

accumulation length for prescaler

FIR preﬁlter and prescaler DC normalization

scaler brightness control

−

128

scaler contrast control

scaler saturation control

2004 Mar 16

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Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

I²C-BUS

ADDRESS

(HEX)

EXAMPLE 1 EXAMPLE 2 EXAMPLE 3 EXAMPLE 4

HEX DEC HEX DEC HEX DEC HEX DEC

MAIN FUNCTION

Horizontal phase scaling

horizontal scaling increment for luminance

1024 AA

938

−

1048

1844

−

horizontal phase offset luminance

−

horizontal scaling increment for chrominance

512

−

469

−

524

−

922

−

horizontal phase offset chrominance

−

Vertical scaling

vertical scaling increment for luminance

1024

853

−

3686

−

1024

−

1024

−

3686

−

vertical scaling increment for chrominance

vertical scaling mode control

853

−

B8 to BF vertical phase offsets luminance and

chrominance (needs to be used for interlace the interlaced scaled output optimize according to

correct scaled output) Section 9.3.3.2

start with B8 to BF at 00H, if there are no problems with

2004 Mar 16

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20 PACKAGE OUTLINE

BGA156: plastic ball grid array package; 156 balls; body 15 x 15 x 1.15 mm

SOT472-1

ball A1

index area

detail X

1/2

A B

1/2

9 10 11 12 13 14

shape

optional (4x)

10 mm

scale

DIMENSIONS (mm are the original dimensions)

UNIT

max.

0.5

0.3

1.25

1.05

0.6

0.4

15.2 13.7 15.2 13.7

14.8 13.0 14.8 13.0

1.75

0.15 0.35

0.3

0.1

REFERENCES

JEDEC JEITA

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

144E

00-03-04

03-01-22

SOT472-1

MS-034

- - -

2004 Mar 16

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Philips Semiconductors

Product speciﬁcation

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21 SOLDERING

To overcome these problems the double-wave soldering

method was specifically developed.

21.1 Introduction to soldering surface mount

packages

If wave soldering is used the following conditions must be

observed for optimal results:

This text gives a very brief insight to a complex technology.

A more in-depth account of soldering ICs can be found in

our “Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).

• Use a double-wave soldering method comprising a

turbulent wave with high upward pressure followed by a

smooth laminar wave.

• For packages with leads on two sides and a pitch (e):

There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering can still be used for

certain surface mount ICs, but it is not suitable for fine pitch

SMDs. In these situations reflow soldering is

recommended.

– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the

transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the

printed-circuit board.

21.2 Reﬂow soldering

Reflow soldering requires solder paste (a suspension of

fine solder particles, flux and binding agent) to be applied

to the printed-circuit board by screen printing, stencilling or

pressure-syringe dispensing before package placement.

Driven by legislation and environmental forces the

The footprint must incorporate solder thieves at the

downstream end.

• For packages with leads on four sides, the footprint must

be placed at a 45° angle to the transport direction of the

printed-circuit board. The footprint must incorporate

solder thieves downstream and at the side corners.

worldwide use of lead-free solder pastes is increasing.

Several methods exist for reflowing; for example,

convection or convection/infrared heating in a conveyor

type oven. Throughput times (preheating, soldering and

cooling) vary between 100 and 200 seconds depending

on heating method.

During placement and before soldering, the package must

be fixed with a droplet of adhesive. The adhesive can be

applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the

adhesive is cured.

Typical reflow peak temperatures range from

215 to 270 °C depending on solder paste material. The

top-surface temperature of the packages should

preferably be kept:

Typical dwell time of the leads in the wave ranges from

3 to 4 seconds at 250 °C or 265 °C, depending on solder

material applied, SnPb or Pb-free respectively.

A mildly-activated flux will eliminate the need for removal

of corrosive residues in most applications.

• below 225 °C (SnPb process) or below 245 °C (Pb-free

process)

– for all BGA, HTSSON-T and SSOP-T packages

21.4 Manual soldering

– for packages with a thickness ≥ 2.5 mm

Fix the component by first soldering two

diagonally-opposite end leads. Use a low voltage (24 V or

less) soldering iron applied to the flat part of the lead.

Contact time must be limited to 10 seconds at up to

300 °C.

– for packages with a thickness < 2.5 mm and a

volume ≥ 350 mm³so called thick/large packages.

• below 240 °C (SnPb process) or below 260 °C (Pb-free

process) for packages with a thickness < 2.5 mm and a

volume < 350 mm³so called small/thin packages.

When using a dedicated tool, all other leads can be

soldered in one operation within 2 to 5 seconds between

270 and 320 °C.

Moisture sensitivity precautions, as indicated on packing,

must be respected at all times.

21.3 Wave soldering

Conventional single wave soldering is not recommended

for surface mount devices (SMDs) or printed-circuit boards

with a high component density, as solder bridging and

non-wetting can present major problems.

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21.5 Suitability of surface mount IC packages for wave and reﬂow soldering methods

SOLDERING METHOD

WAVE

REFLOW⁽²⁾

not suitable suitable

PACKAGE⁽¹⁾

BGA, HTSSON..T⁽³⁾, LBGA, LFBGA, SQFP, SSOP..T⁽³⁾, TFBGA,

USON, VFBGA

DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON,

HTQFP, HTSSOP, HVQFN, HVSON, SMS

not suitable⁽⁴⁾

suitable

PLCC⁽⁵⁾, SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended⁽⁵⁾⁽⁶⁾suitable

SSOP, TSSOP, VSO, VSSOP

CWQCCN..L⁽⁸⁾, PMFP⁽⁹⁾, WQCCN..L⁽⁸⁾

not recommended⁽⁷⁾

suitable

not suitable

Notes

1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy

from your Philips Semiconductors sales office.

2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with respect to time) and body size of the package, there is a risk that internal or external package

cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the

Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.

3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account

be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature

exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package body peak temperature

must be kept as low as possible.

4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder

cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,

the solder might be deposited on the heatsink surface.

5. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.

6. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not

suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than

0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

8. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted

on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar

soldering process. The appropriate soldering profile can be provided on request.

9. Hot bar or manual soldering is suitable for PMFP packages.

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Philips Semiconductors

Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

22 DATA SHEET STATUS

DATA SHEET

LEVEL

PRODUCT

STATUS⁽²⁾⁽³⁾

DEFINITION

STATUS⁽¹⁾

Objective data

Development This data sheet contains data from the objective speciﬁcation for product

development. Philips Semiconductors reserves the right to change the

speciﬁcation in any manner without notice.

Preliminary data Qualiﬁcation

This data sheet contains data from the preliminary speciﬁcation.

Supplementary data will be published at a later date. Philips

Semiconductors reserves the right to change the speciﬁcation without

notice, in order to improve the design and supply the best possible

product.

III

Product data

Production

This data sheet contains data from the product speciﬁcation. Philips

Semiconductors reserves the right to make changes at any time in order

to improve the design, manufacturing and supply. Relevant changes will

be communicated via a Customer Product/Process Change Notiﬁcation

(CPCN).

Notes

1. Please consult the most recently issued data sheet before initiating or completing a design.

2. The product status of the device(s) described in this data sheet may have changed since this data sheet was

published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.

3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

23 DEFINITIONS

24 DISCLAIMERS

Short-form specification

The data in a short-form

Life support applications

These products are not

specification is extracted from a full data sheet with the

same type number and title. For detailed information see

the relevant data sheet or data handbook.

designed for use in life support appliances, devices, or

systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips

Semiconductors customers using or selling these products

for use in such applications do so at their own risk and

agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

Limiting values definition Limiting values given are in

accordance with the Absolute Maximum Rating System

(IEC 60134). Stress above one or more of the limiting

values may cause permanent damage to the device.

These are stress ratings only and operation of the device

at these or at any other conditions above those given in the

Characteristics sections of the specification is not implied.

Exposure to limiting values for extended periods may

affect device reliability.

Right to make changes

Philips Semiconductors

reserves the right to make changes in the products -

including circuits, standard cells, and/or software -

described or contained herein in order to improve design

and/or performance. When the product is in full production

(status ‘Production’), relevant changes will be

Application information

Applications that are

communicated via a Customer Product/Process Change

Notification (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these

products, conveys no licence or title under any patent,

makes no representations or warranties that these

products are free from patent, copyright, or mask work

right infringement, unless otherwise specified.

described herein for any of these products are for

illustrative purposes only. Philips Semiconductors make

no representation or warranty that such applications will be

suitable for the specified use without further testing or

modification.

2004 Mar 16

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Product speciﬁcation

PC-CODEC

SAA7108E; SAA7109E

25 PURCHASE OF PHILIPS I²C COMPONENTS

Purchase of Philips I²C components conveys a license under the Philips’ I²C patent to use the

components in the I²C system provided the system conforms to the I²C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

2004 Mar 16

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Philips Semiconductors – a worldwide company

Contact information

For additional information please visit http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

For sales ofﬁces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.

SCA76

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed

without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license

under patent- or other industrial or intellectual property rights.

Printed in The Netherlands

R21/02/pp202

Date of release: 2004 Mar 16

Document order number: 9397 750 11446

SAA7108E [NXP]

相关型号：

SAA7108EEB

SAA7109

SAA7109A

SAA7109AE

SAA7109AE/V1/G,518

SAA7109E

SAA7110

SAA7110/7110A

SAA7110A

SAA7110AWP

SAA7110AWP-T

SAA7110AWPA