SAA7130HL/V1,518_技术文档

SAA7130HL

PCI video broadcast decoder

Rev. 04 — 11 April 2006

Product data sheet

1. General description

The SAA7130HL is a single chip solution to digitize and decode video, and capture it

through the PCI-bus.

Special means are incorporated to maintain the synchronization of audio to video. The

device offers versatile peripheral interfaces (GPIO) that support various extended

applications, e.g. analog audio pass-through for loopback cable to the sound card, or

capture of DTV and DVB transport streams, such as Vestigial Side Band (VSB),

Orthogonal Frequency Division Multiplexing (OFDM) and Quadrature Amplitude

Modulation (QAM) decoded digital television standards, see Figure 1.

2

I C-bus

TV TUNER:

CABLE

TERRESTRIAL

SATELLITE

DIGITAL CHANNEL DECODER:

VSB

QAM

OFDM

IF-PLL:

DVB

ATV

DTV

DVB

2

I C-BUS

EEPROM

SIF

AUDIO

DECODER:

BTSC

CVBS

TS

AF

(mono)

ENCODER:

MPEG2

audio

L/R

2

I S-bus ITU656

CVBS

S-video

DECODER FOR TV VIDEO

WITH TS INTERFACE AND

DMA MASTER INTO PCI-BUS

SAA7130HL

audio I/O

line-in

line-out

mhc169

PCI-bus

Fig 1. Application diagram for capturing live TV video in the PC, with optional extensions for enhanced DTV and

DVB capture

1.1 Introduction

The PCI video broadcast decoder SAA7130HL is a highly integrated, low cost and solid

foundation for TV capture in the PC, for analog TV and digital video broadcast. The

various multimedia data types are transported over the PCI-bus by bus-master-write, to

optimally exploit the streaming capabilities of a modern host-based system. Legacy

requirements are also taken care of.

SAA7130HL

Philips Semiconductors

PCI video broadcast decoder

The SAA7130HL meets the requirements of PC design guides 98/99 and 2001 and is

PCI 2.2 and Advanced Conﬁguration and Power Interface (ACPI) compliant.

The analog video is sampled by 9-bit ADCs, decoded by a multi-line adaptive comb ﬁlter

and scaled horizontally, vertically and by ﬁeld rate. Multiple video output formats (YUV and

RGB) are available, including packed and planar, gamma-compensated or

black-stretched.

Audio is routed as an analog signal via the loopback cable to the sound card.

The SAA7130HL provides a versatile peripheral interface to support system extensions,

e.g. MPEG encoding for time-shift viewing, or DSP applications for audio enhancements.

The channel decoder for digital video broadcast reception (ATSC or DVB) can re-use the

integrated video ADCs.

The Transport Stream (TS) is collected by a tailored interface and pumped through the

PCI-bus to the system memory in well-deﬁned buffer structures. Various internal events,

or peripheral status information, can be enabled as an interrupt on the PCI-bus.

1.2 Overview of TV decoders with PCI bridge

A TV decoder family with PCI interfacing has been created to support worldwide

TV broadcasting. The pin compatibility of these TV decoders offers the opportunity to

support different TV broadcast standards with one PCB layout.

Table 1:

TV decoder family with PCI interfacing

TV parameter

TV decoder type^[1]

SAA7130HL SAA7133HL SAA7134HL SAA7135HL

PCI bridge

version

2.2

7

2.2

7

2.2

7

2.2

7

DMA channel

TV video

decoding

PAL, NTSC and

SECAM

X

Video

scaling

2 dimension and

2 task scaler

X

Raw VBI

27 MHz sampling rate

FM A2 and NICAM

X

-

X

-

X

-

X

TV sound

decoding

BTSC (dbx-TV) plus

SAP; EIAJ

-

X

stereo sampling

-

32 kHz

X

32 kHz,

48 kHz

32 kHz,

48 kHz

(I²S-bus and DMA)

Radio

FM radio stereo

-

X

SAA7130HL_4

Product data sheet

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SAA7130HL

Philips Semiconductors

PCI video broadcast decoder

Table 1:

TV decoder family with PCI interfacing…continued

TV decoder type^[1]

SAA7130HL SAA7133HL SAA7134HL SAA7135HL

TV parameter

Audio

left and right

pass-through

X

stereo sampling

(I²S-bus and DMA)

-

32 kHz,

44.1 kHz,

48 kHz

32 kHz,

44.1 kHz,

48 kHz

32 kHz,

44.1 kHz,

48 kHz

video frame locked

audio

-

X

incredible surround

-

X

volume, bass and

treble control

volume only

Transport

stream

serial and parallel TS

X

GPIO

static I/O pins

27

4

27

4

27

4

27

4

interrupt input pins

I²C-bus multi-master

or slave

X

video out

X

[1] X = function available.

1.3 Related documents

This document describes the functionality and characteristics of the SAA7130HL.

Other documents related to the SAA7130HL are:

• User manual SAA7130HL/34HL, describing the programmability

• Application note SAA7130HL/34HL, pointing out recommendations for system

implementation

• Demonstration and reference boards, including description, schematics, etc.:

– Proteus-Pro: TV capture PCI card for analog TV (standards: B/G, I, D/K and L/L’)

– Europe: hybrid DVB-T and analog TV capture PCI card for European broadcasting.

• Data sheets of other devices referred to in this document, e.g:

– TDA8961: DTV channel decoder

– TD1316: ATV+DVB-T tuner

– TDA10045: DVB channel receiver

– TDA9886: analog IF-PLL

– TDA9889: digital IF-PLL

SAA7130HL_4

Product data sheet

Rev. 04 — 11 April 2006

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SAA7130HL

Philips Semiconductors

PCI video broadcast decoder

2. Features

2.1 PCI and DMA bus mastering

■ PCI 2.2 compliant including full Advanced Conﬁguration and Power Interface (ACPI)

■ System vendor ID, etc. via EEPROM

■ Hardware support for virtual addressing by MMU

■ DMA bus master write for video, VBI and TS

■ Conﬁgurable PCI FIFOs, graceful overﬂow

■ Packed and planar video formats, overlay clipping

2.2 TV video decoder and video scaling

■ All-standards TV decoder: NTSC, PAL and SECAM

■ Five analog video inputs: CVBS and S-video

■ Video digitizing by two 9-bit ADCs at 27 MHz

■ Sampling according ITU-R BT.601 with 720 pixels/line

■ Adaptive comb ﬁlter for NTSC and PAL, also operating for non-standard signals

■ Automatic TV standard detection

■ Three level Macrovision copy protection detection according to Macrovision detect

speciﬁcation revision 1

■ Control of brightness, contrast, saturation and hue

■ Versatile ﬁlter bandwidth selection

■ Horizontal and vertical downscaling or zoom

■ Adaptive anti-alias ﬁltering

■ Capture of raw VBI samples

■ Two alternating settings for active video scaling

■ Output in YUV and RGB

■ Gamma compensation, black stretching

2.3 TV audio I/O

■ Integrated analog audio pass-through for analog audio loopback cable to sound card

2.4 Peripheral interface

■ I²C-bus master interface: 3.3 V and 5 V

■ Digital video output: ITU and VIP formats

■ TS input: serial or parallel

■ General purpose I/O, e.g. for strapping and interrupt

■ Propagate reset and ACPI state D3-hot

2.5 General

■ Package: LQFP128

■ Power supply: 3.3 V only

■ Power consumption of typical application: 1 W

■ Standby state (D3-hot): < 0.02 W

SAA7130HL_4

Product data sheet

Rev. 04 — 11 April 2006

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SAA7130HL

Philips Semiconductors

PCI video broadcast decoder

■ All interface signals 5 V tolerant

■ Reference designs available

■ SDK for Windows (98, 2000 and XP) and Windows Driver Model (WDM)

3. Ordering information

Table 2:

Ordering information

Type

number

Package

Name

Description

Version

SAA7130HL LQFP128

plastic low proﬁle quad ﬂat package; 128 leads;

SOT425-1

body 14 × 20 × 1.4 mm

4. Block diagram

left 1

right 1

base-

band

ANALOG

NF/AUDIO

FRONT-END

audio

stereo

output

STEREO

BUFFER

AUDIO

OUTPUT

audio

inputs

left 2

right 2

SAA7130HL

ANALOG

VIDEO

FRONT-END

9-BIT

VIDEO

ADC

CV0

CV1

PIXEL ENGINE:

DIGITAL VIDEO

COMB FILTER

DECODER

CVBS

S-video

inputs

VIDEO

SCALER

MATRIX

GAMMA

FORMAT

PCI-bus

CV2

CV3

CV4

ANALOG

VIDEO

FRONT-END

9-BIT

VIDEO

ADC

TS data

TS PARALLEL

TS SERIAL

digital

data

inputs

2

I S-bus

GPIO

STATIC I/O

IRQ

REGISTER

UNIT

2

I C-bus

interrupt

ITU656

mhc170

Fig 2. Block diagram

SAA7130HL_4

Product data sheet

Rev. 04 — 11 April 2006

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SAA7130HL

Philips Semiconductors

PCI video broadcast decoder

5. Pinning information

5.1 Pinning

The SAA7130HL is packaged in a rectangular Low proﬁle Quad Flat Package (LQFP) with

128 pins, see Figure 3.

All the pins are shown sorted by number in Table 3.

Functional pin groupings are given in the following tables:

Power supply pins: Table 4

PCI interface pins: Table 5

Analog interface pins: Table 6

Joint Test Action Group (JTAG) test interface pins for boundary scan test: Table 7

I²C-bus multi-master interface: Table 8

General purpose interface (pins GPIO) and the main functions: Table 9

The characteristics of the pin types are detailed in Table 10.

1

102

SAA7130HL

38

65

001aac204

Fig 3. Pin conﬁguration

Table 3:

Pin allocation table

Pin Symbol

1

2

3

4

5

6

7

8

9

V_DDD

33

34

35

36

37

38

39

40

41

C/BE[1]#

AD[15]

AD[14]

AD[13]

AD[12]

V_DDD

65

66

67

68

69

70

71

72

73

V_DDD

97

98

99

V_SSA

GNT#

REQ#

AD[31]

AD[30]

AD[29]

AD[28]

AD[27]

AD[26]

V_CLK

GPIO17

GPIO16

GPIO15

GPIO14

GPIO13

GPIO12

V_DDD

RIGHT1

V_REF0

100 RIGHT2

101 n.c.

102 n.c.

V_SSD

103 OUT_RIGHT

104 OUT_LEFT

105 PROP_RST_N

PCI_CLK

AD[11]

SAA7130HL_4

Product data sheet

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SAA7130HL

Philips Semiconductors

PCI video broadcast decoder

Table 3:

Pin allocation table…continued

Pin Symbol

AD[25]

Pin Symbol

106 n.c.

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

AD[10]

AD[09]

AD[08]

C/BE[0]#

AD[07]

AD[06]

AD[05]

AD[04]

AD[03]

AD[02]

AD[01]

AD[00]

V_DDD

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

V_SSD

AD[24]

C/BE[3]#

IDSEL

AD[23]

AD[22]

AD[21]

AD[20]

AD[19]

V_DDD

GPIO11

GPIO10

GPIO9

GPIO8

GPIO7

GPIO6

GPIO5

GPIO4

GPIO3

GPIO2

GPIO1

GPIO0

GPIO27

GPIO26

GPIO25

SCL

107 V_REF3

108 V_SSA

109 CV2_C

110 V_DDA

111 n.c.

112 DRCV_Y

113 V_SSA

114 CV0_Y

115 V_DDA

116 CV1_Y

117 DRCV_C

118 CV3_C

119 V_SSA

V_SSD

AD[18]

AD[17]

AD[16]

C/BE[2]#

FRAME#

IRDY#

V_SSD

GPIO23

GPIO22

GPIO21

GPIO20

GPIO19

GPIO18

XTALI

120 CV4

121 TRST_N

122 TCK

TRDY#

DEVSEL#

STOP#

PERR#

SERR#

PAR

SDA

123 TMS

V_DDD

124 TDO

V_SSD

125 TDI

LEFT2

V_DDA

126 INT_A

127 PCI_RST#

128 V_SSD

XTALO

V_SSD

LEFT1

5.2 Pin description

Table 4:

Symbol

V_SSA

Power supply pins

Type

Description

97, 108,

113

AG

analog ground for integrated analog signal processing

and 119

V_DDA

V_SSD

95, 110

and 115

AS

analog supply voltage for integrated analog signal

processing

20, 39, 55, VG

64, 74, 93

digital ground for digital circuit, core and input/outputs

and 128

V_DDD

1, 19, 38,

54, 65, 73

and 92

VS

digital supply voltage for digital circuit, core and

input/outputs

SAA7130HL_4

Product data sheet

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SAA7130HL

Philips Semiconductors

PCI video broadcast decoder

[1]

Table 5:

Symbol

PCI_CLK

PCI interface pins

Type

Description

40

PI

PCI clock input: reference for all bus transactions, up to

33.33 MHz

PCI_RST#

127

PI

PCI reset input: will 3-state all PCI pins (active LOW)

AD[31] to

AD[00]

4 to 11,

PIO and

multiplexed address and data input or output:

bidirectional, 3-state

14 to 18, T/S

21 to 23,

34 to 37,

41 to 44

and

46 to 53

C/BE[3]# to

C/BE[0]#

12, 24, 33 PIO and

command code input or output: indicates type of

requested transaction and byte enable, for byte aligned

transactions (active LOW)

and 45

T/S

PAR

32

PIO and

T/S

parity input or output: driven by the data source, even

parity over all pins AD and C/BE#

FRAME#

25

PIO and

S/T/S

frame input or output: driven by the current bus master

(owner), to indicate the beginning and duration of a bus

transaction (active LOW)

TRDY#

27

PIO and

S/T/S

target ready input or output: driven by the addressed

target, to indicate readiness for requested transaction

(active LOW)

IRDY#

STOP#

IDSEL

26

29

13

PIO and

S/T/S

initiator ready input or output: driven by the initiator, to

indicate readiness to continue transaction (active LOW)

PIO and

S/T/S

stop input or output: target is requesting the master to

stop the current transaction (active LOW)

PI

initialization device select input: this input is used to

select the SAA7130HL during conﬁguration read and

write transactions

DEVSEL#

REQ#

28

3

PIO and

S/T/S

device select input or output: driven by the target device,

to acknowledge address decoding (active LOW)

PO

PCI request output: the SAA7130HL requests master

access to PCI-bus (active LOW)

GNT#

2

PI

PCI grant input: the SAA7130HL is granted to master

access PCI-bus (active LOW)

INT_A

126

30

31

PO and

O/D

interrupt A output: this pin is an open-drain interrupt

output, conditions assigned by the interrupt register

PERR#

SERR#

PIO and

S/T/S

parity error input or output: the receiving device detects

data parity error (active LOW)

PO and

O/D

system error output: reports address parity error (active

LOW)

[1] PCI-bus pins are located on the long side of the package to simplify PCI board layout requirements.

[1]

Table 6:

Symbol

XTALI

Analog interface pins

62

63

94

Type

CI

Description

quartz oscillator input: 32.11 MHz or 24.576 MHz

quartz oscillator output

XTALO

LEFT2

CO

AI

analog audio stereo left 2 input or mono input

SAA7130HL_4

Product data sheet

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SAA7130HL

Philips Semiconductors

PCI video broadcast decoder

[1]

Table 6:

Symbol

V_DDA

Analog interface pins…continued

95

Type

AS

Description

analog supply voltage (3.3 V)

LEFT1

96

AI

analog audio stereo left 1 input or mono input; default

analog pass-through to pin OUT_LEFT after reset

V_SSA

97

98

AG

AI

analog ground (for audio)

RIGHT1

analog audio stereo right 1 input or mono input; default

analog pass-through to pin OUT_RIGHT after reset

V_REF0

99

AR

analog reference ground for audio Sigma Delta ADC; to be

connected directly to analog ground (V_SSA

)

RIGHT2

n.c.

100

101

102

103

AI

-

analog audio stereo right 2 input or mono input

not connected

n.c.

-

not connected

OUT_RIGHT

AO

analog audio stereo right channel output; 1 V (RMS)

line-out, feeding the audio loopback cable via a coupling

capacitor of 2.2 µF

OUT_LEFT

104

AO

analog audio stereo left channel output; 1 V (RMS) line-out,

feeding the audio loopback cable via a coupling capacitor of

2.2 µF

PROP_RST_N 105

AO

-

analog output for test and debug purposes (active LOW)

not connected

n.c.

106

107

V_REF3

AR

analog reference voltage for audio FIR-DAC and SCART

audio input buffer; to be supported with two parallel

capacitors of 47 µF and 0.1 µF to analog ground (V_SSA

)

V_SSA

108

109

110

111

112

AG

AI

analog ground

CV2_C

V_DDA

composite video input (mode 2) or C input (modes 6 and 8)

analog power supply (3.3 V)

AS

-

n.c.

not connected

DRCV_Y

AR

differential reference connection (for CV0 and CV1); to be

supported with a capacitor of 47 nF to analog ground (V_SSA

)

V_SSA

113

114

115

116

117

AG

AI

analog ground

CV0_Y

V_DDA

composite video input (mode 0) or Y input (modes 6 and 8)

analog supply voltage (3.3 V)

AS

AI

CV1_Y

DRCV_C

composite video input (mode 1) or Y input (modes 7 and 9)

AR

differential reference connection (for CV2, CV3 and CV4); to

be supported with a capacitor of 47 nF to analog ground

(V_SSA

)

CV3_C

V_SSA

118

119

120

AI

composite video input (mode 3) or C input (modes 7 and 9)

analog ground

AG

AI

CV4

composite video input (mode 4)

[1] The SAA7130HL offers an interface for analog video and audio signals. The related analog supply pins are

included in this table.

SAA7130HL_4

Product data sheet

Rev. 04 — 11 April 2006

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SAA7130HL

Philips Semiconductors

PCI video broadcast decoder

Table 7:

Symbol

TRST_N

JTAG test interface pins

Type

Description

121

I

test reset input: drive LOW for normal operating (active

LOW)

TCK

TMS

122

123

I

test clock input: drive LOW for normal operating

test mode select input: tie HIGH or let ﬂoat for normal

operating

TDO

TDI

124

125

O

I

test serial data output: 3-state

test serial data input: tie HIGH or let ﬂoat for normal

operating

Table 8:

Symbol

SCL

I²C-bus multi-master interface

Type

Description

90

IO2

serial clock input (slave mode) or output (multi-master

mode)

SDA

91

IO2

GO

serial data input and output; always available

PROP_RST_N 105

propagate reset and D3-hot output; to peripheral board

circuitry

[1]

Table 9:

Symbol

GPIO pins and functions

Type

Function

Audio and

video port

outputs

TS capture

inputs

Raw DTV/DVB

outputs

GPIO

GPIO27

GPIO26

GPIO25

V_CLK

87

88

89

66

GIO

GO

-

R/W

-

V_CLK (also

gated)

ADC_CLK (out)

GPIO23

GPIO22

56

57

GIO

HSYNC

-

ADC_C[0] (LSB) R/W,

INT

VSYNC

TS_LOCK

(channel

-

R/W,

INT

decoder locked)

GPIO21

GPIO20

GPIO19

GPIO18

GPIO17

58

59

60

61

67

GIO

-

TS_S_D

(bit-serial data)

-

R/W

-

TS_CLK

(< 33 MHz)

-

TS_SOP (packet

start)

-

VAUX2

-

X_CLK_IN

R/W,

INT

VAUX1 (e.g.

VACTIVE)

-

ADC_Y[0] (LSB) R/W

SAA7130HL_4

Product data sheet

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SAA7130HL

Philips Semiconductors

PCI video broadcast decoder

[1]

Table 9:

Symbol

GPIO pins and functions…continued

Type

Function

Audio and

video port

outputs

TS capture

inputs

Raw DTV/DVB

outputs

GPIO

GPIO16

68

GIO

-

TS_VAL (valid

ﬂag)

-

R/W,

INT

GPIO15 to

GPIO8

69 to 72 GIO

and

VP[7:0] for

formats:

-

ADC_Y[8:1]

R/W

75 to 78

ITU-R BT.656,

VMI, VIP (1.1,

2.0), etc.

GPIO7 to

GPIO0

79 to 86 GIO

VP extension

for 16-bit

formats: ZV,

VIP-2, DMSD,

etc.

TS_P_D[7:0]

(byte-parallel

data)

ADC_C[8:1]

R/W

[1] The SAA7130HL offers a peripheral interface with General Purpose Input/Output (GPIO) pins. Dedicated

functions can be selected:

a) Digital Video Port (VP): output only; in 8-bit and 16-bit formats, such as VMI, DMSD (ITU-R BT.601);

zoom-video, with discrete sync signals; ITU-R BT.656; VIP (1.1 and 2.0), with sync encoded in SAV and

EAV codes.

b) Transport Stream (TS) capture input: from the peripheral DTV/DVB channel decoder; synchronized by

Start Of Packet (SOP); in byte-parallel or bit-serial protocol.

c) Digitized raw DTV/DVB samples stream output: from internal ADCs; to feed the peripheral DTV/DVB

channel decoder.

d) GPIO: as default (no other function selected); static (no clock); read and write from or to individually

selectable pins; latching ‘strap’ information at system reset time.

e) Use an external pull-up resistor of 4.7 kΩ at GPIO16 for an external 24.576 MHz crystal; due to an

internal pull-down resistor an open GPIO16 pin requires an external 32.11 MHz crystal.

f) Peripheral interrupt (INT) input: enabled by interrupt enable register; routed to PCI interrupt (INT_A).

5.2.1 Pin type description

Table 10: Characteristics of pin types and remarks

Pin type

AG

AI

Description

analog ground

analog input; video, audio and sound

analog output

AO

AR

AS

analog reference support pin

analog supply voltage (3.3 V)

CMOS input; 3.3 V level (not 5 V tolerant)

CMOS output; 3.3 V level (not 5 V tolerant)

digital input/output (GPIO); 3.3 V level (5 V tolerant)

digital output (GPIO); 3.3 V level (5 V tolerant)

JTAG test input

CI

CO

GIO

GO

I

IO2

digital input and output of the I²C-bus interface; 3.3 V and 5 V

compatible, auto-adapting

O

JTAG test output

O/D

open-drain output (for PCI-bus); multiple clients can drive LOW at the

same time, wired-OR, ﬂoating back to 3-state over several clock cycles

SAA7130HL_4

Product data sheet

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SAA7130HL

Philips Semiconductors

PCI video broadcast decoder

Table 10: Characteristics of pin types and remarks…continued

Pin type

PI

Description

input according to PCI-bus requirements

PIO

input and output according to PCI-bus requirements

output according to PCI-bus requirements

PO

S/T/S

sustained 3-state (for PCI-bus); previous owner drives HIGH for one

clock cycle before leaving to 3-state

T/S

VG

VS

3-state I/O (for PCI-bus); bidirectional

ground for digital supply

supply voltage (3.3 V)

Name ends with _N or # this pin or ‘signal’ is active LOW, i.e. the function is ‘true’ if the logic level

is LOW

6. Functional description

6.1 Overview of internal functions

The SAA7130HL is able to capture TV signals over the PCI-bus in personal computers by

a single chip; see Figure 4.

The SAA7130HL incorporates two 9-bit video ADCs and the entire decoding circuitry for

any analog TV signal: NTSC, PAL and SECAM, including non-standard signals, such as

playback from a VCR. The adaptive multi-line comb ﬁlter provides superb picture quality,

component separation, sharpness and high bandwidth. The video stream can be cropped

and scaled to the needs of the application. Scaling down as well as zooming up is

supported in the horizontal and vertical direction, and an adaptive ﬁlter algorithm prevents

aliasing artifacts. With the acquisition unit of the scaler two different ‘tasks’ can be deﬁned,

e.g. to capture video to the CPU for compression, and write video to the screen from the

same video source but with different resolution, color format and frame rate.

The SAA7130HL incorporates analog audio pass-through and support for the analog

audio loopback cable to the sound card function.

The decoded video streams are fed to the PCI-bus, and are also applied to a peripheral

streaming interface, in ITU, VIP or VMI format. A possible application extension is

on-board hardware MPEG compression, or other feature processing. The compressed

data is fed back through the peripheral interface, in parallel or serial format, to be captured

by the system memory through the PCI-bus. The Transport Stream (TS) from a DTV/DVB

channel decoder can be captured through the peripheral interface in the same way.

Video and transport streams are collected in a conﬁgurable FIFO with a total capacity of

1 kB. The DMA controller monitors the FIFO ﬁlling degree and master-writes the audio

and video stream to the associated DMA channel. The virtual memory address space

(from OS) is translated into physical (bus) addresses by the on-chip hardware Memory

Management Unit (MMU).

The application of the SAA7130HL is supported by reference designs and a set of drivers

for the Windows operating system (Windows driver model compliant).

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PCI video broadcast decoder

GPIO

5 analog

video

inputs

transport

reset stream input

digital video

output

stereo

output

stereo stereo

input 1 input 2

2

I C-bus

INPUT SELECTION

ANALOG AUDIO I/O

2

DTV-TS p/s

VIDEO PORT

(DIGITAL)

I C-BUS

INTERFACE

2

PASS-THROUGH (DEFAULT)

CLAMP AND GAIN

CONTROL

I S-BUS

INPUT

9-BIT ADC 9-BIT ADC

DECODER

(NTSC, PAL, SECAM)

PROPAGATE

RESET

LLC

ADAPTIVE

COMB FILTER

SAA7130HL

VIDEO SCALER

3-D

MATRIX

GAMMA

FORMAT

RAW VBI

PROGRAM PROGRAM

SET

VIDEO FIFOS

TS FIFOS

DMA CONTROL

BOUNDARY

SCAN TEST

OSCILLATOR

DMA CONTROL

ACPI POWER

MANAGEMENT

PCI-BUS INTERFACE

PCI-bus

test

crystal

mhc171

Fig 4. Functional diagram

6.2 Application examples

The SAA7130HL enables PC TV capture applications both on the PC motherboard and

on PCI add-on TV capture cards. Figure 5 and Figure 6 illustrate some examples of

add-on card applications.

Figure 5 shows the basic application to capture video from analog TV sources. The

proposed tuner types incorporate the RF tuning function and the IF down conversion.

Usually the IF down conversion stage also includes a single channel and analog sound

FM demodulator. The Philips tuner FI1216 MK2 is dedicated to the 50 Hz system

B/G standard as used in Europe. The FI1236 MK2 is the comparable type for the 60 Hz

system M standard for the USA. Both types are suited for terrestrial broadcast and for

cable reception. The tuner provides composite video and baseband audio as mono or

‘multiplexed’ (mpx) in case of BTSC. These analog video and sound signals are fed to the

appropriate input pins of the SAA7130HL.

Further analog video input signals, CVBS and/or Y-C, can be connected via the board

back panel, or the separate front connectors, e.g. from a camcorder. Accompanying

stereo audio signals can also be fed to the SAA7130HL.

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PCI video broadcast decoder

Video is digitized and decoded to YUV. The digital streams are pumped via DMA into the

PCI memory space.

The SAA7130HL incorporates the means for legacy analog audio signal routing. The

analog audio input signal is fed via an analog audio loopback cable into the line-in of a

legacy sound card. An external audio signal, that would have otherwise connected directly

to the sound card, is now routed through the SAA7130HL. This analog pass-through is

enabled as default by a system reset, i.e. without any driver involvement and before

system setup.

During the power-up procedure, the SAA7130HL will investigate the on-board EEPROM

to load the board-speciﬁc system vendor ID and board version ID into the related places

of the PCI conﬁguration space. The board vendor can store other board-speciﬁc data in

the EEPROM that is accessible via the I²C-bus.

TV CAPTURE PCI CARD

TV cable

TV TUNER AND

or

IF-PLL

terrestrial

2

I C-bus

CVBS

AF sound

(mono)

analog

audio

loopback

cable

CVBS

S-video

audio

DECODER FOR

TV VIDEO

SOUND

CARD

line-in

DMA MASTER

INTO PCI

2

I C-BUS EEPROM

SYSTEM

VENDOR ID

SAA7130HL

PCI-bus:

digital video, raw VBI, TS

AGP

SOUTH

BRIDGE

NORTH

BRIDGE

VGA AND

LOCAL MEMORY

ISA

SYSTEM

MEMORY

CPU AND

CACHE MEMORY

FSB

mhc172

Fig 5. TV mono capture card

Figure 6 shows an application extension with a hybrid TV tuner front-end and digital

terrestrial channel decoding for DVB-T.

The single-conversion tuner TD1316 provides two dedicated IF signals for the analog

IF-PLL (TDA9886) and the digital IF-PLL (TDA9889). The CVBS (video) and AUD (audio,

mono) output signals of the analog IF-PLL can be routed to one of the video inputs and

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PCI video broadcast decoder

the audio (left or right) input of the SAA7130HL for analog video decoding and direct audio

streaming to the sound card. On the other hand, the 2nd IF signal of the digital IF-PLL is

fed directly to the interface of the channel decoder (TDA10045), which decodes the signal

into a digital DVB-T Transport Stream (TS).

The SAA7130HL captures this TS via the dedicated peripheral interface into the

conﬁgurable internal FIFO for DMA into the PCI memory space.

The packet structure as decoded by the TDA10045 is maintained in a well-deﬁned buffer

structure in the system memory, and therefore can easily be sorted (de-multiplexed) by

the CPU for proper MPEG decoding.

The Broadcast Driver Architecture (BDA) for Windows operating systems supports this

type of hybrid TV capture application, sharing one capture board for analog and digital

TV reception.

HYBRID TV CAPTURE PCI CARD

ATV cable

or terrestrial

and

IF

DIGITAL

IF-PLL

TV TUNER

DVB terrestrial

IF

DVB-T

CHANNEL

DECODER

ANALOG IF-PLL

CVBS

AF

TS

CVBS

S-video

audio

analog audio

loopback

cable

DECODER FOR

TV VIDEO

SOUND

CARD

2

line-in

I C-bus

DMA MASTER

INTO PCI

2

I C-BUS EEPROM

SYSTEM

VENDOR ID

SAA7130HL

PCI-bus:

digital video, raw VBI, TS

AGP

SOUTH

BRIDGE

NORTH

BRIDGE

VGA AND

LOCAL MEMORY

ISA

SYSTEM

MEMORY

CPU AND

CACHE MEMORY

FSB

mhc173

Fig 6. Hybrid TV capture board for digital TV (DVB-T) and analog TV reception

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PCI video broadcast decoder

6.3 Software support

6.3.1 Device driver

A complex and powerful software packet is provided for the SAA7130HL. This packet

includes plug-and-play driver and capture driver installations for all commonly used 32-bit

Windows platforms.

All platform related drivers support the following:

• Video preview and capture interfaces

Table 11: Microsoft Operation System (MOS) support

MOS

Driver support

Windows 98

Device access is contained in a kernel-mode Windows Driver Model (WDM)

driver. The capture driver interface is based on Microsoft DirectShow technology.

Windows 2000 The driver is binary-compatible with the Windows 98 driver and validated for

passing the Microsoft WHQL test for getting the Win2000 driver signature.

Windows XP

The driver is binary-compatible with the Windows 98 driver and validated for

passing the Microsoft WHQL test for getting the WinXP driver signature.

6.3.2 Supporting WDM

The Windows driver is implemented as an AV-streaming class-driver and provides a

‘DirectShow’ (DS) ﬁlter with output pins for video preview, video capture and VBI, together

with a crossbar for input sources selection.

The TV tuner ﬁlter is a separate child driver and supports the control of all common Philips

CAN and Silicon tuners. The typical ﬁlter structure is shown in Figure 7.

TV TUNER

SAA7130HL

XBAR

video preview

video capture

VBI

external video inputs

audio inputs

CAPTURE

DRIVER

transport stream in

mhc174

Fig 7. WDM capture driver ﬁlters

6.4 PCI interface

6.4.1 PCI conﬁguration registers

The PCI interface of the SAA7130HL complies with the PCI speciﬁcation 2.2 and supports

power management and Advanced Conﬁguration and Power Interface (ACPI) as required

by the PC Design Guide 2001.

The PCI speciﬁcation deﬁnes a structure of the PCI conﬁguration space that is

investigated during the boot-up of the system. The conﬁguration registers (see Table 12)

hold information essential for plug-and-play, to allow system enumeration and basic

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PCI video broadcast decoder

device setup without depending on the device driver, and support association of the

proper software driver. Some of the conﬁguration information is hard-wired in the device;

some information is loaded during the system start-up.

Table 12: PCI conﬁguration registers

[1]

Function

Register address Value

(hexadecimal)

Remark

Device vendor ID

Device ID

00 and 01

02 and 03

08

1131h

7130h

00h

for Philips

for SAA7130HL

or higher

Revision ID

Class code

09 to 0B

10 to 13

04 8000h

multimedia

Memory address

space required

XXXX XXXX XXXX XXXX 1 kB

XXXX XX00 0000 0000b

System (board)

vendor ID

2C and 2D

2E and 2F

loaded from EEPROM

Sub-system (board

version) ID

loaded from EEPROM

[1] X = don’t care.

The device vendor ID is hard coded to 1131h, which is the code for Philips as registered

with PCI-SIG.

The device ID is hard coded to 7130h.

During power-up, initiated by PCI reset, the SAA7130HL fetches additional system

information via the I²C-bus from the on-board EEPROM, to load actual board-type speciﬁc

codes for the system vendor ID, sub-system ID (board version) and ACPI related

parameters into the conﬁguration registers.

6.4.2 ACPI and power states

The PCI speciﬁcation 2.2 requires support of Advanced Conﬁguration and Power

Interface speciﬁcation 1.0 (ACPI); more details are deﬁned in the PCI Power Management

Speciﬁcation 1.0.

The power management capabilities and power states are reported in the extended

conﬁguration space. The main purpose of ACPI and PCI power management is to tailor

the power consumption of the device to the actual needs.

The SAA7130HL supports all four ACPI device power states (see Table 13).

The pin PROP_RST_N of the peripheral interface is switched active LOW during the PCI

reset procedure, and for the duration of the D3-hot state. Peripheral devices on board of

the add-on card should use the level of this signal PROP_RST_N to switch themselves in

any Power-save mode (e.g. disable device) and reset to default settings on the rising edge

of signal PROP_RST_N.

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PCI video broadcast decoder

Table 13: Power management table

Power state Description

D0

Normal operation: all functions accessible and programmable. The default setting

after reset and before driver interaction (D0 un-initialized) switches most of the

circuitry of the SAA7130HL into the Power-down mode, effectively such as

D3-hot.

D1

First step of reduced power consumption: no functional operation. Program

registers are not accessible, but content is maintained. Most of the circuitry of the

SAA7130HL is disabled with exception of the crystal and real-time clock

oscillators, so that a quick recovery from D1 to D0 is possible.

D2

Second step of reduced power consumption: no functional operation. Program

registers are not accessible, but content is maintained. All functional circuitry of

the SAA7130HL is disabled, including the crystal and clock oscillators.

D3-hot

Lowest power consumption: no functional operation. The content of the

programming registers gets lost and is set to default values when returning to D0.

6.4.3 DMA and conﬁgurable FIFO

The SAA7130HL supports seven DMA channels to master-write captured active video,

raw VBI and DTV/DVB Transport Streams (TS) into the PCI memory. Each DMA channel

contains inherently the deﬁnition of two buffers, e.g. for odd and even ﬁelds in case of

interlaced video.

The DMA channels share in time and space one common FIFO pool of 256 Dwords

(1024 bytes) total. It is freely conﬁgurable how much FIFO capacity can be associated

with which DMA channel. Furthermore, a preferred minimum burst length can be

programmed, i.e. the amount of data to be collected before the request for the PCI-bus is

issued. This means that latency behavior per DMA channel can be tailored and optimized

for a given application.

In the event that a FIFO of a certain channel overﬂows due to latency conﬂict on the bus,

graceful overﬂow recovery is applied. The amount of data that gets lost because it could

not be transmitted, is monitored (counted) and the PCI-bus address pointer is

incremented accordingly. Thus new data will be written to the correct memory place, after

the latency conﬂict is resolved.

6.4.4 Virtual and physical addressing

Most operating systems allocate memory to requesting applications for DMA as

continuous ranges in virtual address space. The data ﬂow over the PCI-bus points to

physical addresses, usually not continuous and split in pages of 4 kB (Intel architecture,

most UNIX systems, Power PC).

The association between the virtual (logic) address space and the fragmented physical

address space is deﬁned in page tables (system ﬁles); see Figure 8.

The SAA7130HL incorporates hardware support (MMU) to translate virtual to physical

addresses on the ﬂy, by investigating the related page table information. This hardware

support reduces the demand for real-time software interaction and interrupt requests, and

therefore saves system resources.

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PCI video broadcast decoder

physical memory

00000h

real-time streams

FIFO

POOL

00007h

0000Fh

00017h

0001Fh

DMA

ADDRESS

GENERATION

DMA DEFINITIONS

(VIRTUAL ADDRESS SPACE)

page table

000h

007h

00001000h

00008000h

00009000h

0000A000h

0000D000h

00011000h

00014000h

00016000h

0001E000h

VIRTUAL

TO

PHYSICAL

ADDRESS

TRANSLATION

PCI

TRANSFER AND

CONTROL

015h

physical address

space on PCI

= allocated memory space

= page table

mhb996

Fig 8. MMU implementation (shown bit width indication is valid for 4 kB mode)

6.4.5 Status and interrupts on PCI-bus

The SAA7130HL provides a set of status information about internal signal processing,

video standard detection, peripheral inputs and outputs (pins GPIO) and behavior on the

PCI-bus. This status information can be conditionally enabled to raise an interrupt on the

PCI-bus, e.g. completion of a certain DMA channel or buffer, or change in a detected

TV standard, or the state of peripheral devices.

The cause of an issued interrupt is reported in a dedicated register, even if the original

condition has changed before the system was able to investigate the interrupt.

6.5 Analog TV standards

Analog TV signals are described in three categories of standards:

• Basic TV systems: deﬁning frame rate, number of lines per ﬁeld, levels of

synchronization signals, blanking, black and white, signal bandwidth and the

RF modulation scheme

• Color transmission: deﬁning color coding and modulation method

• Sound and stereo: deﬁning coding for transmission

TV signals that are broadcast usually conform fairly accurately to the standards.

Transmission over the air or through a cable can distort the signal with noise, echoes,

crosstalk or other disturbances.

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PCI video broadcast decoder

Video signals from local consumer equipment, e.g. VCR, camcorder, camera, game

console, or even DVD player, often do not follow the standard speciﬁcation very

accurately.

Playback from video tape cannot be expected to maintain correct timing, especially not

during feature mode (fast forward, etc.).

Table 14 to Table 16 list some characteristics of the various TV standards.

The SAA7130HL decodes all color TV standards and non-standard signals as generated

by video tape recorders e.g. automatic video standard detection can be applied, with

preference options for certain standards, or the decoder can be forced to a dedicated

standard.

Table 14: Overview of basic TV standards

Main

Standard

Unit

parameters

M

N

B

G, H

I

D/K

L

RF channel

width

6

7

8

7

8

MHz

Hz

Video

bandwidth

4.2

5

5.5

6

1st sound

carrier

4.5 FM

5.5 FM

6.0 FM

6.5 FM

6.5 AM

Field rate

59.94006

50

Lines per frame 525

625

Line frequency 15.734

15.625

1728

15.625

1728

15.625

1728

15.625

1728

15.625

1728

15.625

1728

kHz

IRE

ITU clocks per 1716

line

Sync, setup

level

−40, 7.5

−43, 0

2.8

−43, 0

2.8

−43, 0

2.8

−43, 0

2.8

Gamma

2.2

2.8

correction

Associated

color

NTSC, PAL PAL

PAL

SECAM,

PAL

SECAM

TV standards

Associated

stereo

BTSC, EIAJ, BTSC

A2

dual FM,

A2

NICAM

NICAM, A2 NICAM

TV sound

systems

Country

examples

USA,Japan, Argentina

Brazil

part of

Europe,

Australia

Spain,

Malaysia,

Singapore

UK,

Northern

Europe

China,

Eastern

Europe

France,

Eastern

Europe

Table 15: TV system color standards

Main

NTSC M

PAL M

PAL N

PAL BGHID SECAM LDGHK

PAL 4.4 (60 Hz) Unit

parameters

Field rate

59.94

525

59.94

525

50

≈60

Hz

Lines per

frame

625

525

Chrominance 3.580

subcarrier

3.576

3.582

4.434

4.406

4.250

4.434

MHz

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PCI video broadcast decoder

Table 15: TV system color standards…continued

Main

NTSC M

PAL M

PAL N

PAL BGHID SECAM LDGHK

PAL 4.4 (60 Hz) Unit

parameters

f_scto H ratio

227.5

227.25

229.25

50

283.75

50

282

272

n.a.

yes

f_scoffset (PAL)

-

Hz

Alternating

phase

no

yes

Country

examples

USA, Japan,

Asia-Paciﬁc

Brazil

Middle and Europe,

France,

Eastern Europe,

Africa, Middle East

VCR

South

Common-

wealth,

China

transcoding

NTSC-tape to

PAL

America

Table 16: TV stereo sound standards

Main parameters Analog systems

Digital coding

Unit

Mono

BTSC

EIAJ

A2 (dual FM)

NICAM

Stereo coding

scheme

-

internal carrier (mpx)

2-Carrier Systems (2CS)

2nd FM carrier

AM

FM

DQPSK on FM

2nd language

-

mono SAP on

internal FM

as alternative as alternative to stereo mono on 1st carrier

to stereo

Sound IF

M, N

1st

2nd

1st

2nd

4.5 FM

5.5 FM

6.0 FM

6.5 FM

6.5 AM

75

4.5

4.724

5.742

not used

6.742

6.258

5.742

not used

5.850

6.552

5.850

-

MHz

µs

B, G, H

I

not used

-

not used

-

5.5

not used

6.0

DK (1)

6.5

DK (2)

-

DK (3)

-

L

not used

75 dbx-TV

15

not used

50

not used

50 or 75

15

6.5

5.850

De-emphasis

Audio bandwidth

50 or J17

15

kHz

Country examples world-

wide

USA, South

America

Japan

part of Europe, Korea part of Europe, China

6.6 Video processing

6.6.1 Analog video inputs

The SAA7130HL provides ﬁve analog video input pins:

• Composite video signals (CVBS), from tuner or external source

• S-video signals (pairs of Y-C), e.g. from camcorder

• DTV/DVB ‘low-IF’ signal, from an appropriate DTV or combi-tuner

Analog anti-alias ﬁlters are integrated on chip and therefore, no external ﬁlters are

required. The device also contains automatic clamp and gain control for the video input

signals, to ensure optimum utilization of the ADC conversion range. The nominal video

signal amplitude is 1 V (p-p) and the gain control can adapt deviating signal levels in the

range of +3 dB to −6 dB. The video inputs are digitized by two ADCs of 9-bit resolution,

with a sampling rate of nominal 27 MHz (the line-locked clock) for analog video signals.

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PCI video broadcast decoder

6.6.2 Video synchronization and line-locked clock

The SAA7130HL recovers horizontal and vertical synchronization signals from the

selected video input signal, even under extremely adverse conditions and signal

distortions. Such distortions are ‘noise’, static or dynamic echoes from broadcast over air,

crosstalk from neighboring channels or power lines (hum), cable reﬂections, time base

errors from video tape play-back and non-standard signal levels from consumer type

video equipment (e.g. cameras, DVD).

The heart of this TV synchronization system is the generation of the Line-Locked Clock

(LLC) of nominal 27 MHz, as deﬁned by ITU-R BT.601. The LLC ensures orthogonal

sampling, and always provides a regular pattern of synchronization signals, that is a ﬁxed

and well deﬁned number of clock pulses per line. This is important for further video

processing devices connected to the peripheral video port (pins GPIO). It is very effective

to run under the LLC of 27 MHz, especially for on-board hardware MPEG encoding

devices, since MPEG is deﬁned on this clock and sampling frequency.

6.6.3 Video decoding and automatic standard detection

The SAA7130HL incorporates color decoding for any analog TV signal. All color

TV standards and ﬂavors of NTSC, PAL, SECAM and non-standard signals (VCR) are

automatically recognized and decoded into luminance and chrominance components, i.e.

Y-C_B-C_R, also known as YUV.

The video decoder of the SAA7130HL incorporates an automatic standard detection, that

does not only distinguish between 50 Hz and 60 Hz systems, but also determines the

color standard of the video input signal. Various preferences (‘look ﬁrst’) for automatic

standard detection can be chosen, or a selected standard can be forced directly.

6.6.4 Adaptive comb ﬁlter

The SAA7130HL applies adaptive comb ﬁlter techniques to improve the separation of

luminance and chrominance components in comparison to the separation by a chroma

notch ﬁlter, as used in traditional TV color decoder technology. The comb ﬁlter compares

the signals of neighboring lines, taking into account the phase shift of the chroma

subcarrier from line to line. For NTSC the signal from three adjacent lines are investigated,

and in the event of PAL the comb ﬁlter taps are spread over four lines.

Comb ﬁltering achieves higher luminance bandwidth, resulting in sharper picture and

detailed resolution. Comb ﬁltering further minimizes color crosstalk artifacts, which would

otherwise produce erroneous colors on detailed luminance structures.

The comb ﬁlter as implemented in the SAA7130HL is adaptive in two ways:

• Adaptive to transitions in the picture content

• Adaptive to non-standard signals (e.g. VCR)

The integrated digital delay lines are always exactly correct, due to the applied unique

line-locked sampling scheme (LLC). Therefore the comb ﬁlter does not need to be

switched off for non-standard signals and remains operating continuously.

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PCI video broadcast decoder

6.6.5 Copy protection detection

The SAA7130HL detects if the decoded video signal is copy protected by the Macrovision

system. The detection logic distinguishes the three levels of the copy protection as

deﬁned in rev. 7.01, and are reported as status information. The decoded video stream is

not effected directly, but application software and Operation System (OS) has to ensure

that this video stream maintains the ‘copy protected’ tag, and the video signal should

leave the system only with the reinforced copy protection. The multi-level Macrovision

detection on the video capture side supports proper TV re-encoding at the output point,

e.g. by Philips TV encoders SAA712x or SAA7102.

6.6.6 Video scaling

The SAA7130HL incorporates a ﬁlter and processing unit to downscale or upscale the

video picture in the horizontal and vertical dimension, and in frame rate

(see Figure 9 and Figure 10). The phase accuracy of the re-sampling process is ¹⁄₆₄of the

original sample distance. This is equivalent to a clock jitter of less than 1 ns. The ﬁlter

depth of the anti-alias ﬁlter adapts to the scaling ratio, from 10 taps horizontally for scaling

ratios close to 1 : 1, to up to 74 taps for an icon sized video picture.

Most video capture applications will typically require downscaling. But some zooming is

required for conversion of ITU sampling to SQuare Pixel (SQP), or to convert the 240 lines

of an NTSC ﬁeld to 288 lines to comply with ITU-T video phone formats.

The scaling acquisition deﬁnition also includes cropping, frame rate reduction, and deﬁnes

the amount of pixels and lines to be transported through DMA over the PCI-bus.

Two programming pages are available to enable re-programming of the scaler in the

‘shadow’ of the running processing, without holding or disturbing the ﬂow of the video

stream. Alternatively, the two programming pages can be applied to support two video

destinations or applications with different scaler settings, e.g. ﬁrstly to capture video to

CPU for compression (storage, video phone), and secondly to preview the picture on the

monitor screen. A separate scaling region is dedicated to capture raw VBI samples, with a

speciﬁc sampling rate, and to write it into its own DMA channel.

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PCI video broadcast decoder

VBI first sample

VBI last sample

1st field (odd, FID = 0)

sample rate

VBI DMA

VBI first line

VBI last line

1st buffer (A)

2nd buffer (A)

VBI region, raw samples

video region

- cropped

- scaled

scaling

active video area

2nd field (even, FID = 1)

sample rate

video DMA (A)

e.g. interlaced

VBI region, raw samples

1st buffer (upper field)

2nd buffer (lower field)

video first line

video last line

video region

- cropped

- scaled

scaling

active video area

video first pixel

mhb997

video last pixel

The capture acquisition for scaling and DMA has separate programming parameters for VBI and video region and

associated DMA channels.

Fig 9. Scaler processing with DMA interfacing

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PCI video broadcast decoder

1st field (odd, FID = 0)

VBI region, raw samples

VBI DMA

sample rate

1st buffer (A)

2nd buffer (A)

video region (A) - cropped

scaling

3rd buffer (B)

4th buffer (B)

active video area

2nd field (even, FID = 1)

VBI region, raw samples

sample rate

video DMA (A)

e.g. interlaced

video region (A) - cropped

1st buffer (upper field)

2nd buffer (lower field)

scaling

active video area

3rd field (odd, FID = 0)

VBI region, raw samples

sample rate

video region (B)

- skipped for field rate reduction

video DMA (B)

e.g. single FID

1st buffer

active video area

4th field (even, FID = 1)

VBI region, raw samples

sample rate

2nd buffer

(next frame)

video region - scaled down CIF

scaling

mhb998

active video area

alternating processing task A/B

Two video capture tasks can be processed in an alternating manner, without the need to re-program any scaling

parameters or DMA deﬁnition.

Fig 10. Scaler task processing with DMA interfacing

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6.6.7 VBI data

PCI video broadcast decoder

The Vertical Blanking Interval (VBI) is often utilized to transport data over analog video

broadcast. Such data can closely relate to the actual video stream, or just be general data

(e.g. news). Some examples for VBI data types are:

• Closed Caption (CC) for the hearing impaired (CC, on line 21 of ﬁrst ﬁeld)

• Intercast data in US coded in North-American Broadcast Text System (NABTS)

format, in Europe in World Standard Teletext (WST), to transmit internet related

services, optionally associated with actual video program content

• Teletext, transporting news services and broadcast related information, Electronic

Program Guide (EPG), widely used in Europe (coded in WST format)

• EPG, broadcaster speciﬁc program and schedule information, sometimes with

proprietary coding scheme (pay service), usually carried on NABTS, WST, Video

Programming Service (VPS), or proprietary data coding format

• Video Time Codes (VTC) as inserted in camcorders e.g. used for video editing

• Copy Guard Management System (CGMS) codes, to indicate copy protected video

material, sometimes combined with format information, Wide Screen Signalling

(WSS)

This information is coded in the unused lines of the vertical blanking interval, between the

vertical sync pulse and the active visible video picture. So-called full-ﬁeld data

transmission is also possible, utilizing all video lines for data coding.

The SAA7130HL supports capture of VBI data by the deﬁnition of a VBI region to be

captured as raw VBI samples, that will be sliced and decoded by software on the host

CPU. The raw sample stream is taken directly from the ADC and is not processed or

ﬁltered by the video decoder. The sampling rate of raw VBI can be adjusted to the needs

of the data slicing software.

6.6.8 Signal levels and color space

Analog TV video signals are decoded into their component luminance and color difference

signals (YUV), or in their digital form Y-C_B-C_R. ITU-R BT.601 deﬁnes 720 pixels along the

line (corresponding to a sampling rate of 27 MHz divided by two), and a certain

relationship from level to number range; see Figure 11.

The video components do not use the entire number range, but leave some margin for

overshoots and intermediate values during processing. For the raw VBI samples there is

no ofﬁcial speciﬁcation how to code, but it is common practice to reserve the lower quarter

of the number range for the sync, and to leave some room for overmodulation beyond the

nominal white amplitude; see Figure 12.

The automatic clamp and gain control at the video input, together with the automatic

chroma gain control of the SAA7130HL, ensures that the video component stream at the

output complies with the standard levels. Beyond that additional brightness, contrast,

saturation and hue control can be applied to satisfy special needs of a given application.

The raw VBI samples can be adjusted independent of the active video.

The SAA7130HL incorporates the YUV-to-RGB matrix (optional), the RGB-to-YUV matrix

and a three channel look-up table in between; see Figure 13. Under nominal settings, the

RGB space will use the same number range as deﬁned by the ITU and shown in

Figure 11 for luminance, between 16 and 235. As graphic related applications are based

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Philips Semiconductors

PCI video broadcast decoder

on full-scale RGB, i.e. 0 to 255, the range can be stretched by applying appropriate

brightness, contrast and saturation values. The look-up table supports gamma correction

(freely deﬁnable), and allows other non-linear signal transformation such as black

stretching.

The analog TV signal applies a quite strong gamma pre-compensation (2.2 for NTSC and

2.8 for PAL). As computer monitors exhibit a gamma (around 2.5), the difference between

gamma pre-compensation and actual screen gamma has to be corrected, to achieve best

contrast and color impression.

The SAA7130HL offers a multitude of formats to write video streams over the PCI-bus:

YUV and RGB color space, 15-bit, 16-bit, 24-bit and 32-bit representation, packed and

planar formats. For legacy requirements a clipping procedure is implemented, that allows

the deﬁnition of eight overlay rectangles. This process can alternatively be used to

associate ‘alpha’ values to the video pixels.

+255

+235

+255

+240

+255

+240

blue 100 %

blue 75 %

red 100 %

red 75 %

white

+212

+128

colorless

+128

colorless

LUMINANCE 100 %

U-COMPONENT

V-COMPONENT

+44

+16

0

yellow 75 %

+44

+16

0

cyan 75 %

black

yellow 100 %

cyan 100 %

+16

0

001aae766

a. Y output range

b. U output range (C_B)

c. V output range (C_R)

Fig 11. Nominal digital levels for YUV (Y, C_Band C_R) in accordance with ITU-R BT.601

+255

+209

+255

+199

white

LUMINANCE

black

black shoulder

+71

+60

black shoulder = black

+60

SYNC

1

sync bottom

mgd700

a. For sources containing 7.5 IRE black

level offset (e.g. NTSC M)

b. For sources not containing black level

offset

Fig 12. Nominal digital levels for CVBS and raw VBI samples

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Philips Semiconductors

PCI video broadcast decoder

three channel non-linear transformation

Y

U

V

R

G

B

R

G

B

Y

U

V

YUV

to

RGB

to

RGB

matrix

YUV

matrix

mhb999

Fig 13. Color space conversion and look-up table

6.6.9 Video port, ITU and VIP codes

The decoded and/or scaled video stream can be captured via PCI-DMA to the system

memory, and/or can be made available locally through the video side port (VP), using

some of the GPIO pins. Two types of applications are intended:

• Streaming real-time video to a video side port at the VGA card, e.g. via ribbon cable

over the top

• Feeding video stream to a local MPEG compression device on the same PCI board,

e.g. for time-shift viewing applications

The video port of the SAA7130HL supports the following 8-bit and 16-bit wide YUV video

signalling standards (see Table 9):

• VMI: 8-bit wide data stream, clocked by LLC = 27 MHz, with discrete sync signals

HSYNC, VSYNC and VACTIVE

• ITU-R BT.656, parallel: 8-bit wide data stream, clocked by LLC = 27 MHz,

synchronization coded in SAV and EAV codes

• VIP 1.1 and 2.0: 8-bit or 16-bit wide data stream, clocked by LLC = 27 MHz,

synchronization coded in SAV and EAV codes (with VIP extensions)

• Zoom Video (ZV): 16-bit wide pixel stream, clocked by LLC/2 = 13.5 MHz, with

discrete sync signals HSYNC and VSYNC

• ITU-R BT.601 direct (DMSD): 16-bit wide pixel stream, clocked by LLC = 27 MHz, with

discrete sync signals HSYNC, VSYNC/FID and CREF

• Raw DTV/DVB sample stream: 9-bit wide data, clocked with a copy of

signal X_CLK_IN

The VIP standard can transport scaled video and discontinuous data stream by allowing

the insertion of ‘00’ as a marker for empty clock cycles. For the other video port standards,

a data valid ﬂag or gated clock can be applied.

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PCI video broadcast decoder

6.7 Analog audio pass-through and loopback cable

Most operating systems are prepared to deal with audio input at only one single entry

point, namely at the sound card function. Therefore the sound associated with video has

to get routed through the sound card.

The SAA7130HL supports analog audio pass-through and the loopback cable on chip. No

external components are required. The audio signal, that was otherwise connected to the

sound card line-in, e.g. analog sound from a CD-ROM drive, has to be connected to one

of the inputs of the SAA7130HL. By default, after a system reset and without involvement

of any driver, this audio signal is passed through to the analog audio output pins, that will

feed the loopback cable to the sound card line-in connector. The AV capture driver has to

open the default pass-through and switch in the TV sound signal by will.

6.8 DTV/DVB channel decoding and TS capture

The SAA7130HL is optimally equipped to support the application extension to capture

digital TV signals, e.g. for VSB (ATSC) or DVB (T/C/S). A hybrid TV tuner for analog and

digital TV broadcast reception usually provides a DTV signal on low IF, i.e. down

converted into a frequency range from 0 MHz to 10 MHz. Such signals can be fed to one

of the 5 video inputs of the SAA7130HL for digitizing. The digital raw DTV is output at the

video port, and is sent to the peripheral channel decoder, e.g. TDA8961 for VSB-8

decoding. The channel decoder provides the sampling clock via the external clock input

pin X_CLK_IN (up to 36 MHz input clock frequency), and adjusts the signal gain in the

tuner or in the video input path in front of the ADC. Alternatively, the low IF DTV/DVB

signal could be fed directly to the channel decoder, depending on the capability for

digitizing the selected device.

The peripheral channel decoder circuitry decodes the digital transmission into bits and

bytes, applies error correction etc., and outputs a packed Transport Stream (TS)

accompanied by a clock and handshake signals. The SAA7130HL captures the TS in

parallel or serial protocol, synchronized by Start Of Packet (SOP), and pumps it via the

dedicated DMA into the PCI memory space. The DMA deﬁnition supports automatic

toggling between two buffers.

6.9 Control of peripheral devices

6.9.1 I²C-bus master

The SAA7130HL incorporates an I²C-bus master to setup and control peripheral devices

such as tuner, DTV/DVB channel decoder, audio DSP co-processors, etc. The I²C-bus

interface itself is controlled from the PCI-bus on a command level, reading and writing

byte by byte. The actual I²C-bus status is reported (status register) and, as an option, can

raise error interrupts on the PCI-bus.

At PCI reset time, the I²C-bus master receives board-speciﬁc information from the

on-board EEPROM to update the PCI conﬁguration registers.

The I²C-bus interface is multi-master capable and can assume slave operation too. This

allows application of the device in the stand-alone mode, i.e. with the PCI-bus not

connected. Under the slave mode, all internal programming registers can be reached via

the I²C-bus with exception of the PCI conﬁguration space.

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PCI video broadcast decoder

6.9.2 Propagate reset

The PCI system reset and ACPI power management state D3 is propagated to peripheral

devices by the dedicated pin PROP_RST_N. This signal is switched to active LOW by

reset and D3, and is only switched HIGH under control of the device driver ‘by will’. The

intention is that peripheral devices will use signal PROP_RST_N as Chip-Enable (CE).

The peripheral devices should enter a low power consumption state if

pin PROP_RST_N = LOW, and reset into default setting at the rising edge.

6.9.3 GPIO

The SAA7130HL offers a set of General Purpose Input/Output (GPIO) pins, to interface to

on-board peripheral circuits. These GPIOs are intended to take over dedicated functions:

• Digital video port output: 8-bit or 16-bit wide (including raw DTV)

• Transport stream input: parallel or serial (also applicable as I²S-bus input)

• Peripheral interrupt input: four GPIO pins of the SAA7130HL can be enabled to raise

an interrupt on the PCI-bus. By this means, peripheral devices can directly intercept

the device driver on changed status or error conditions

Any GPIO pin that is not used for a dedicated function is available for direct read and write

access via the PCI-bus. Any GPIO pin can be selected individually as input or output

(masked write). By these means, very tailored interfacing to peripheral devices can be

created via the SAA7130HL capture driver running on Windows operating systems.

At system reset (PCI reset) all GPIO pins will be set to 3-state and input, and the logic

level present on the GPIO pins at that moment will be saved into a special ‘strap’ register.

All GPIO pins have an internal pull-down resistor (LOW-level), but can be strapped

externally with a 4.7 kΩ resistor to the supply voltage (HIGH-level). The device driver can

investigate the strap register for information about the hardware conﬁguration of a given

board.

7. Limiting values

Table 17: Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). All ground pins connected

together and grounded (0 V); all supply pins connected together.

Symbol Parameter

Conditions

Min Max

−0.5 +4.6

Unit

V

V_DDD

V_DDA

∆V_SS

digital supply voltage

analog supply voltage

V

voltage difference

between

-

100

mV

pins V_SSAand V_SSD

V_IA

input voltage at

analog inputs

−0.5 +4.6

V

V_I(n)

input voltage at

pins XTALI, SDA and

SCL

−0.5 V_DDD+ 0.5

V_ID

input voltage at digital outputs in 3-state

−0.5 +4.6

−0.5 +5.5

V

I/O stages

outputs in 3-state;

3.0 V < V_DDD< 3.6 V

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PCI video broadcast decoder

Table 17: Limiting values…continued

In accordance with the Absolute Maximum Rating System (IEC 60134). All ground pins connected

together and grounded (0 V); all supply pins connected together.

Symbol Parameter

Conditions

Min Max

Unit

°C

V

T_stg

storage temperature

−65

+150

70

T_amb

V_esd

ambient temperature

0

-

[1]

[2]

electrostatic

human body model

machine model

±2000

±200

discharge voltage

-

V

[1] Class 2 according to EIA/JESD22-114-B.

[2] Class B according to EIA/JESD22-115-A.

8. Thermal characteristics

Table 18: Thermal characteristics

Symbol

Parameter

Conditions

Typ

30^[1]

Unit

K/W

R_th(j-a)

thermal resistance from junction in free air

to ambient

[1] The overall R_th(j-a)value can vary depending on the board layout. To minimize the effective R_th(j-a)all power

and ground pins must be connected to the power and ground layers directly. An ample copper area directly

under the SAA7130HL with a number of through-hole plating, which connect to the ground layer (four-layer

board: second layer), can also reduce the effective R_th(j-a). Do not use any solder-stop varnish under the

chip. In addition the usage of soldering glue with a high thermal conductance after curing is recommended.

9. Characteristics

Table 19: Characteristics

V_DDD= 3.0 V to 3.6 V; V_DDA= 3.0 V to 3.6 V; T_amb= 25 °C; unless otherwise speciﬁed.

Symbol

Supplies

V_DDD

Parameter

Conditions

Min

Typ

Max

Unit

digital supply voltage

analog supply voltage

power dissipation

3.0

3.3

3.6

V

V_DDA

P

power state

D0 for typical

application

-

1.0

-

W

D0 after reset

-

0.1

0.2

0.1

-

W

D1

-

D2

-

D3-hot

0.02

Crystal oscillator

f_xtal

oscillator frequency

24

-

33

MHz

range

f_xtal(nom)

nominal crystal

frequency

crystal 1; see Table 20

crystal 2; see Table 20

-

32.11

24.576

-

MHz

-

∆f_xtal(n)

permissible nominal

frequency deviation

±70 × 10⁻⁶

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Product data sheet

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SAA7130HL

Philips Semiconductors

PCI video broadcast decoder

Table 19: Characteristics…continued

V_DDD= 3.0 V to 3.6 V; V_DDA= 3.0 V to 3.6 V; T_amb= 25 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

P_drive

crystal power level of

drive at pin XTALO

-

0.5

-

mW

t_j

oscillator clock jitter

-

±100

ps

V

V_IH(XTALI)

HIGH-level input voltage

at pin XTALI

2

V_DDD+ 0.3

V_IL(XTALI)

LOW-level input voltage

at pin XTALI

−0.3

-

+0.8

V

PCI-bus inputs and outputs

V_IH

V_IL

I_LIH

HIGH-level input voltage

2

-

5.75

+0.8

10

V

LOW-level input voltage

−0.5

V

[1]

HIGH-level input

leakage current

V_I= 2.7 V

-

µA

I_LIL

V_OH

V_OL

C_i

LOW-level input leakage V_I= 0.5 V

current

-

−10

-

µA

V

HIGH-level output

voltage

I_O= −2 mA

2.4

-

[2]

LOW-level output

voltage

I_O= 3 mA or 6 mA

0.55

V

input capacitance at

pin PCI_CLK

5

-

12

8

pF

pin IDSEL

pF

other input pins

output rise slew rate

output fall slew rate

-

10

5

pF

[3]

[4]

SR_r

SR_f

t_val

0.4 V to 2.4 V

2.4 V to 0.4 V

1

V/ns

5

CLK to signal valid delay see Figure 14

bused signals

2

-

11

12

-

ns

point-to-point signals

see Figure 14

[5]

[4]

t_on

t_off

t_su

ﬂoat-to-active delay

active-to-ﬂoat delay

28

input setup time to CLK see Figure 14

bused signals

7

-

ns

µs

point-to-point signals

10 (12)

0

t_h

input hold time from CLK see Figure 14

[6]

t_rst(CLK)

reset active time after

CLK stable

100

[5] [6] [7]

t_rst(off)

reset active to output

ﬂoat delay

-

40

ns

I²C-bus interface, compatible to 3.3 V and 5 V signalling (pins SDA and SCL)

f_bit

bit frequency rate

0

-

400

kbit/s

[8]

V_IL

V_IH

V_OL

LOW-level input voltage

HIGH-level input voltage

−0.5

+0.3 × V_DD(I2C)

V_DD(I2C)+ 0.5

0.4

V

0.7 × V_DD(I2C)

LOW-level output

voltage

I_o(sink)= 3 mA

-

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Philips Semiconductors

PCI video broadcast decoder

Table 19: Characteristics…continued

V_DDD= 3.0 V to 3.6 V; V_DDA= 3.0 V to 3.6 V; T_amb= 25 °C; unless otherwise speciﬁed.

Symbol

Analog video inputs

Inputs (pins CV0-Y, CV1-Y, CV2-C, CV3-C and CV4)

Parameter

Conditions

Min

Typ

Max

Unit

I_clamp

V_i(p-p)

C_i

clamping current

DC input voltage

V_I= 0.9 V

-

±8

0.75

-

µA

V

[9]

input voltage

(peak-to-peak value)

0.375

-

1.07

10

input capacitance

pF

9-bit analog-to-digital converters

α_cs

B

channel crosstalk

analog bandwidth

differential phase

f_i< 5 MHz

-

−50

dB

[10]

at −3 dB; ADC only

7

2

-

MHz

deg

φ_dif

ampliﬁer plus anti-alias

ﬁlter bypassed

G_dif

differential gain

ampliﬁer plus anti-alias

ﬁlter bypassed

-

2

-

%

LE_DC(d)

LE_DC(i)

S/N

DC differential linearity

error

1.4

2

LSB

dB

DC integral linearity

error

signal-to-noise ratio

f_i= 4 MHz; anti-alias

ﬁlter bypassed;

AGC = 0 dB

50

ENOB

effective number of bits f_i= 4 MHz; anti-alias

ﬁlter bypassed;

-

8

-

bit

AGC = 0 dB

Analog audio inputs (pins LEFT1, RIGHT1, LEFT2 and RIGHT2) and outputs (pins OUT_LEFT and OUT_RIGHT)

[11]

V_i(nom)(rms)nominal input voltage

(RMS value)

-

200

-

mV

[12]

V_i(max)(rms)maximum input voltage THD < 3%

(RMS value)

1

2

-

V

V_o(max)(rms)maximum output voltage THD < 3%

(RMS value)

1

V

R_i

input resistance

V_i(max)= 1 V (RMS)

V_i(max)= 2 V (RMS)

-

145

48

250

-

kΩ

Ω

-

R_o

output resistance

150

375

-

R_L(AC)

C_L

AC load resistance

output load capacitance

10

-

kΩ

nF

mV

%

-

12

30

0.3

V_offset(DC)static DC offset voltage

-

10

0.1

THD + N

total harmonic

distortion-plus-noise

V_i= V_o= 1 V (RMS);

f_i= 1 kHz; bandwidth

B = 20 Hz to 20 kHz

-

S/N

signal-to-noise ratio

reference voltage

V_o= 1 V (RMS);

f_i= 1 kHz;

70

75

-

dB

ITU-R BS.468

weighted; quasi peak

SAA7130HL_4

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SAA7130HL

Philips Semiconductors

PCI video broadcast decoder

Table 19: Characteristics…continued

V_DDD= 3.0 V to 3.6 V; V_DDA= 3.0 V to 3.6 V; T_amb= 25 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

α_ct

crosstalk attenuation

between any analog

input pairs; f_i= 1 kHz

60

-

dB

α_cs

channel separation

between left and right

of each input pair

60

-

dB

All digital I/Os: GPIO pins and BST test pins (5 V tolerant)

Pins GPIO0 to GPIO23, V_CLK, GPIO25 to GPIO27, TDI, TDO, TMS, TCK and TRST_N

V_IH

V_IL

HIGH-level input voltage

LOW-level input voltage

input leakage current

I/O leakage current

2.0

-

5.5

+0.8

1

V

−0.3

V

I_LI

-

µA

I_L(I/O)

3.3 V signal levels at

_DDD≥ 3.3 V

10

V

C_i

input capacitance

pull-down resistance

pull-up resistance

I/O at high-impedance

V_I= V_DDD

-

8

pF

kΩ

V

R_pd

R_pu

V_OH

-

50

-

V_I= 0 V

-

HIGH-level output

voltage

I_O= −2 mA

2.4

V_DDD+ 0.5

V_OL

LOW-level output

voltage

I_O= 2 mA

0

-

0.4

V

Video port outputs (digital video stream from comb ﬁlter decoder or scaler)

LLC and LLC2 clock output on pin V_CLK; see Figure 15

C_L

load capacitance

cycle time

15

35

70

-

50

39

78

pF

ns

T_cy

LLC active

LLC2 active

C_L= 40 pF

LLC active

LLC2 active

0.4 V to 2.4 V

2.4 to 0.4 V

[13]

δ

duty factor

35

-

65

5

%

ns

t_r

t_f

rise time

fall time

-

5

Video data output (with respect to signal V_CLK) on pins GPIO0 to GPIO17, GPIO22 and GPIO23; see Figure 15

C_L

t_h

load capacitance

data hold time

15

-

50

pF

[14] [15]

LLC active

5

-

ns

LLC2 active

15

[14] [15]

t_PD

propagation delay from

positive edge of

signal V_CLK

LLC active

-

28

55

ns

LLC2 active

SAA7130HL_4

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SAA7130HL

Philips Semiconductors

PCI video broadcast decoder

Table 19: Characteristics…continued

V_DDD= 3.0 V to 3.6 V; V_DDA= 3.0 V to 3.6 V; T_amb= 25 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Raw DTV/DVB outputs (reuse of video ADCs in DVB/TV applications with TDA8960 and TDA8961 for VSB reception)

Clock input signal X_CLK_IN on pin GPIO18

T_cy

δ

cycle time

duty factor

rise time

fall time

27.8

37

50

-

333

60

5

ns

%

[13]

40

-

t_r

0.8 V to 2.0 V

2.0 V to 0.8 V

ns

t_f

-

5

Clock output signal ADC_CLK on pin V_CLK

C_L

T_cy

δ

load capacitance

cycle time

duty factor

rise time

-

25

-

pF

ns

%

27.8

C_L= 40 pF

40

-

60

5

t_r

0.4 V to 2.4 V

2.4 V to 0.4 V

ns

t_f

fall time

-

5

VSB data output signals with respect to signal ADC_CLK

C_L

t_h

load capacitance

data hold time

25

5

-

50

-

pF

ns

[14]

inverted and not

delayed

[14] [16]

t_PD

propagation delay from inverted and not

-

23

ns

positive edge of

signal ADC_CLK

delayed

TS capture inputs with parallel transport streaming (TS-P); e.g. DVB applications

Clock input signal TS_CLK on pin GPIO20; see Figure 16

T_cy

δ

cycle time

duty factor

rise time

fall time

-

333

-

ns

%

[13]

40

-

60

5

t_r

0.8 V to 2.0 V

2.0 V to 0.8 V

ns

t_f

-

5

Data and control input signals on TS-P port (with respect to signal TS_CLK) on pins GPIO0 to GPIO7, GPIO16, GPIO19 to

GPIO22; see Figure 16

t_su(D)

t_h(D)

input data setup time

input data hold time

2

5

-

ns

TS capture inputs with serial transport streaming (TS-S); e.g. DVB applications

Clock input signal TS_CLK on pin GPIO20; see Figure 16

T_cy

δ

cycle time

duty factor

rise time

fall time

37

40

-

ns

%

[13]

60

5

t_r

0.8 V to 2.0 V

2.0 V to 0.8 V

ns

t_f

-

5

Data and control input signals on TS-S port (with respect to signal TS_CLK) on pins GPIO16, GPIO19, GPIO21 and

GPIO22; see Figure 16

t_su(D)

t_h(D)

input data setup time

input data hold time

2

5

-

ns

[1] Input leakage currents include high-impedance output leakage for all bidirectional buffers with 3-state outputs.

[2] Pins without pull-up resistors must have a 3 mA output current. Pins requiring pull-up resistors must have 6 mA; these are

pins FRAME#, TRDY#, IRDY#, DEVSEL#, SERR#, PERR#, INT_A and STOP#.

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PCI video broadcast decoder

[3] This parameter is to be interpreted as the cumulative edge rate across the speciﬁed range, rather than the instantaneous rate at any

point within the transition range.

[4] REQ# and GNT# are point-to-point signals and have different output valid delay and input setup times than bused signals. GNT# has a

setup time of 10 ns. REQ# has a setup time of 12 ns.

[5] For purposes of active or ﬂoat timing measurements, the high-impedance or ‘off’ state is deﬁned to be when the total current delivered

through the device is less than or equal to the leakage current speciﬁcation.

[6] RST_N is asserted and de-asserted asynchronously with respect to CLK.

[7] All output drivers ﬂoated asynchronously when RST_N is active.

[8] V_DD(I2C)is the extended pull-up voltage of the I²C-bus (3.3 V or 5 V bus).

[9] Nominal analog video input signal is to be terminated by 75 Ω that results in 1 V (p-p) amplitude. This termination resistor should be split

into 18 Ω and 56 Ω, and the dividing tap should feed the video input pin, via a coupling capacitor of 47 nF, to achieve a control range

from −3 dB (attenuation) to +6 dB (ampliﬁcation) for the internal automatic gain control. See also Application note SAA7130HL/34HL.

[10] See User Manual SAA7130HL/34HL for Anti-Alias Filter (AAF).

[11] Deﬁnition of levels and level setting:

The full-scale level for analog audio signals V_FS= 0.8 V (RMS). The nominal level at the digital crossbar switch is deﬁned at

−15 dB (FS).

Nominal audio input levels: external, mono, V_i= 280 mV (RMS); −9 dB (FS).

[12] The analog audio inputs (pins LEFT1, RIGHT1, LEFT2 and RIGHT2) are supported by two input levels: 1 V (RMS) and 2 V (RMS),

selectable independently per stereo input pair, LEFT1, RIGHT1 and LEFT2, RIGHT2.

t_H

[13] The deﬁnition of the duty factor: δ =

-------

T_cy

[14] The output timing must be measured with the load of a 30 pF capacitor to ground and a 500 Ω resistor to 1.4 V.

[15] Signal V_CLK inverted; not delayed (default setup).

[16] t_PD= 6 ns + 0.6 × T_{ADC_CLK}in ns (T_{ADC_CLK}= 28 ns).

2.4 V

CLK

1.5 V

0.4 V

t

val

OUTPUT

DELAY

1.5 V

3-STATE

OUTPUT

t

on

t

off

t

h

su

2.4 V

INPUT

1.5 V

input valid

1.5 V

0.4 V

mgg280

Fig 14. PCI I/O timing

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Philips Semiconductors

PCI video broadcast decoder

t

PD

t

h

video data and

control output

(pins GPIO0 to GPIO17,

GPIO22 and GPIO23)

2.4 V

0.4 V

t

H

L

2.4 V

1.5 V

0.4 V

clock output

(pin V_CLK)

t

r

f

mhc002

Fig 15. Data output timing (video data, control outputs and raw DTV/DVB)

TS data and

control input

(pins GPIO0 to GPIO7,

GPIO16, GPIO19,

GPIO21 and GPIO22)

2.0 V

0.8 V

t

h(D)

su(D)

2.0 V

1.5 V

0.8 V

TS_CLK

(pin GPIO20)

t

f

mhc003

r

Fig 16. Data input timing (TS data and control inputs)

[1]

Table 20: Speciﬁcation of crystals and related applications (examples)

Standard

Crystal frequency

32.11 MHz

Unit

24.576 MHz

Fundamental

3rd harmonic

1A

Fundamental

3rd harmonic

1B

1C

2B

2C

2A

Crystal speciﬁcation

Typical load capacitance 20

8

20

30

8

10

80

pF

Maximum series

30

20

7

60

50

60

Ω

resonance resistance

Typical motional

capacitance

13.5

1.5

4.3

20

7

1

1.5

3.5

fF

Maximum parallel

capacitance

3 ± 1

3.3

pF

Maximum permissible

deviation

±30 × 10⁻⁶±30 × 10⁻⁶±30 × 10⁻⁶

±30 × 10⁻⁶±30 × 10⁻⁶±50 × 10⁻⁶

±30 × 10⁻⁶±30 × 10⁻⁶±20 × 10⁻⁶

Maximum temperature

deviation

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Philips Semiconductors

PCI video broadcast decoder

[1]

Table 20: Speciﬁcation of crystals and related applications (examples) …continued

Standard

Crystal frequency

32.11 MHz

Unit

24.576 MHz

Fundamental

3rd harmonic

1A

Fundamental

3rd harmonic

2A

1B

1C

2B

2C

External components

Typical load capacitance 33

at pin XTALI

10

15

1

27

5.6

n.a.

18

1

pF

nF

µH

Typical load capacitance 33

at pin XTALO

10

27

Typical capacitance of

LC ﬁlter

n.a.

Typical inductance of

LC ﬁlter

n.a.

4.7

[1] For oscillator application, see the Application note of the SAA7130HL/34HL.

10. Test information

10.1 Boundary scan test

The SAA7130HL has built-in logic and ﬁve dedicated pins to support boundary scan

testing which allows board testing without special hardware (nails).

The SAA7130HL follows the IEEE Std. 1149.1 - Standard Test Access Port and Boundary

- Scan Architecture set by the Joint Test Action Group (JTAG) chaired by Philips.

The 5 special pins are: Test Mode Select (TMS), Test Clock (TCK), Test Reset (TRST_N),

Test Data Input (TDI) and Test Data Output (TDO).

The Boundary Scan Test (BST) functions BYPASS, EXTEST, SAMPLE, CLAMP and

IDCODE are all supported (see Table 21). Details about the JTAG BST-test can be found

in the speciﬁcation IEEE Std. 1149.1. A ﬁle containing the detailed Boundary Scan

Description Language (BSDL) description of the SAA7130HL is available on request.

10.1.1 Initialization of boundary scan circuit

The Test Access Port (TAP) controller of an IC should be in the reset state

(TEST_LOGIC_RESET) when the IC is in the functional mode. This reset state also

forces the instruction register into a functional instruction such as IDCODE or BYPASS.

To solve the power-up reset, the standard speciﬁes that the TAP controller will be forced

asynchronously to the TEST_LOGIC_RESET state by setting pin TRST_N to LOW-level.

10.1.2 Device identiﬁcation codes

When the IDCODE instruction is loaded into the BST instruction register, the identiﬁcation

register will be connected internally between pins TDI and TDO of the IC. The

identiﬁcation register will load a component speciﬁc code during the

CAPTURE_DATA_REGISTER state of the TAP controller and this code can subsequently

be shifted out. At board level, this code can be used to verify component manufacturer,

SAA7130HL_4

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PCI video broadcast decoder

type and version number. The device identiﬁcation register contains 32 bits, numbered

31 to 0, where bit 31 is the most signiﬁcant bit (nearest to TDI) and bit 0 is the least

signiﬁcant bit (nearest to TDO); see Figure 17.

A device identiﬁcation register is speciﬁed in IEEE Std. 1149.1b-1994. It is a 32-bit

register which contains ﬁelds for the speciﬁcation of the IC manufacturer, the IC part

number and the IC version number. Its biggest advantage is the possibility to check for the

correct ICs mounted after production and determination of the version number of ICs

during ﬁeld service.

Table 21: BST instructions supported by the SAA7130HL

Instruction Description

BYPASS

EXTEST

SAMPLE

This mandatory instruction provides a minimum length serial path (1 bit) between

pins TDI and TDO when no test operation of the component is required.

This mandatory instruction allows testing of off-chip circuitry and board level

interconnections.

This mandatory instruction can be used to take a sample of the inputs during

normal operation of the component. It can also be used to preload data values into

the latched outputs of the boundary scan register.

CLAMP

This optional instruction is useful for testing when not all ICs have BST. This

instruction addresses the bypass register while the boundary scan register is in

external test mode.

IDCODE

This optional instruction will provide information on the components manufacturer,

part number and version number.

MSB

31

LSB

28 27

12 11

1

0

TDI

TDO

0001

1

0111 0001 0011 0000

16-bit part number

000 0001 0101

4-bit

version

code

11-bit manufacturer

identification

mandatory

mhc175

Fig 17. 32-bit identiﬁcation code

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PCI video broadcast decoder

11. Package outline

LQFP128: plastic low profile quad flat package; 128 leads; body 14 x 20 x 1.4 mm

SOT425-1

y

X

A

102

103

65

64

Z

E

e

H

A

E

2

A

E

(A )

3

A

1

θ

w M

p

L

p

b

pin 1 index

detail X

39

38

128

1

v

M

A

Z

w M

D

b

p

e

D

B

H

v

M

B

D

0

5

10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

v

w

y

Z

E

θ

1

2

3

p

E

p

D

max.

7^o

0^o

0.15 1.45

0.05 1.35

0.27 0.20 20.1 14.1

0.17 0.09 19.9 13.9

22.15 16.15

21.85 15.85

0.75

0.45

0.81 0.81

0.59 0.59

mm

1.6

0.25

1

0.2 0.12 0.1

0.5

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-01-19

03-02-20

SOT425-1

136E28

MS-026

Fig 18. Package outline SOT425-1 (LQFP128)

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PCI video broadcast decoder

12. Soldering

12.1 Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology. A more in-depth account of

soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface mount IC packages. Wave

soldering can still be used for certain surface mount ICs, but it is not suitable for ﬁne pitch

SMDs. In these situations reﬂow soldering is recommended.

12.2 Reﬂow soldering

Reﬂow soldering requires solder paste (a suspension of ﬁne solder particles, ﬂux and

binding agent) to be applied to the printed-circuit board by screen printing, stencilling or

pressure-syringe dispensing before package placement. Driven by legislation and

environmental forces the worldwide use of lead-free solder pastes is increasing.

Several methods exist for reﬂowing; for example, convection or convection/infrared

heating in a conveyor type oven. Throughput times (preheating, soldering and cooling)

vary between 100 seconds and 200 seconds depending on heating method.

Typical reﬂow peak temperatures range from 215 °C to 270 °C depending on solder paste

material. The top-surface temperature of the packages should preferably be kept:

• below 225 °C (SnPb process) or below 245 °C (Pb-free process)

– for all BGA, HTSSON..T and SSOP..T packages

– for packages with a thickness ≥ 2.5 mm

– for packages with a thickness < 2.5 mm and a volume ≥ 350 mm³so called

thick/large packages.

• below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with a

thickness < 2.5 mm and a volume < 350 mm³so called small/thin packages.

Moisture sensitivity precautions, as indicated on packing, must be respected at all times.

12.3 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices

(SMDs) or printed-circuit boards with a high component density, as solder bridging and

non-wetting can present major problems.

To overcome these problems the double-wave soldering method was speciﬁcally

developed.

If wave soldering is used the following conditions must be observed for optimal results:

• Use a double-wave soldering method comprising a turbulent wave with high upward

pressure followed by a smooth laminar wave.

• For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be

parallel to the transport direction of the printed-circuit board;

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PCI video broadcast decoder

– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the

transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

• For packages with leads on four sides, the footprint must be placed at a 45° angle to

the transport direction of the printed-circuit board. The footprint must incorporate

solder thieves downstream and at the side corners.

During placement and before soldering, the package must be ﬁxed with a droplet of

adhesive. The adhesive can be applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C

or 265 °C, depending on solder material applied, SnPb or Pb-free respectively.

A mildly-activated ﬂux will eliminate the need for removal of corrosive residues in most

applications.

12.4 Manual soldering

Fix the component by ﬁrst soldering two diagonally-opposite end leads. Use a low voltage

(24 V or less) soldering iron applied to the ﬂat part of the lead. Contact time must be

limited to 10 seconds at up to 300 °C.

When using a dedicated tool, all other leads can be soldered in one operation within

2 seconds to 5 seconds between 270 °C and 320 °C.

12.5 Package related soldering information

Table 22: Suitability of surface mount IC packages for wave and reﬂow soldering methods

Package ^[1]

Soldering method

Wave

Reﬂow^[2]

BGA, HTSSON..T^[3], LBGA, LFBGA, SQFP,

SSOP..T^[3], TFBGA, VFBGA, XSON

not suitable

suitable

DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP,

HSQFP, HSSON, HTQFP, HTSSOP, HVQFN,

HVSON, SMS

not suitable^[4]

suitable

PLCC^[5], SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended^{[5] [6]}

not recommended^[7]

not suitable

suitable

SSOP, TSSOP, VSO, VSSOP

CWQCCN..L^[8], PMFP^[9], WQCCN..L^[8]

suitable

not suitable

[1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026);

order a copy from your Philips Semiconductors sales ofﬁce.

[2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the

maximum temperature (with respect to time) and body size of the package, there is a risk that internal or

external package cracks may occur due to vaporization of the moisture in them (the so called popcorn

effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit

Packages; Section: Packing Methods.

[3] These transparent plastic packages are extremely sensitive to reﬂow soldering conditions and must on no

account be processed through more than one soldering cycle or subjected to infrared reﬂow soldering with

peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reﬂow oven. The package

body peak temperature must be kept as low as possible.

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PCI video broadcast decoder

[4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the

solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink

on the top side, the solder might be deposited on the heatsink surface.

[5] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave

direction. The package footprint must incorporate solder thieves downstream and at the side corners.

[6] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is

deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

[7] Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger

than 0.65 mm; it is deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

[8] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered

pre-mounted on ﬂex foil. However, the image sensor package can be mounted by the client on a ﬂex foil by

using a hot bar soldering process. The appropriate soldering proﬁle can be provided on request.

[9] Hot bar soldering or manual soldering is suitable for PMFP packages.

SAA7130HL_4

Product data sheet

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SAA7130HL

Philips Semiconductors

PCI video broadcast decoder

13. Revision history

Table 23: Revision history

Document ID

SAA7130HL_4

Modiﬁcations:

SAA7130HL_3

SAA7130HL_2

SAA7130HL_1

Release date Data sheet status

20060411 Product data sheet

Change notice Doc. number

Supersedes

-

SAA7130HL_3

• Table 1: deleted rows “Dolby Pro Logic” and “virtual Dolby Surround” at TV parameter Audio.

20050503

20021217

20020423

Product data sheet

Product speciﬁcation

-

9397 750 14308 SAA7130HL_2

9397 750 10358 SAA7130HL_1

9397 750 08669

-

SAA7130HL_4

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SAA7130HL

Philips Semiconductors

PCI video broadcast decoder

14. Data sheet status

Level Data sheet status^[1]Product status^{[2] [3]}

Deﬁnition

I

Objective data

Development

This data sheet contains data from the objective speciﬁcation for product development. Philips

Semiconductors reserves the right to change the speciﬁcation in any manner without notice.

II

Preliminary data

Qualiﬁcation

This data sheet contains data from the preliminary speciﬁcation. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in

order to improve the design and supply the best possible product.

III

Product data

Production

This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

[1]

[2]

Please consult the most recently issued data sheet before initiating or completing a design.

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3]

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

performance. When the product is in full production (status ‘Production’),

15. Deﬁnitions

relevant changes will be communicated via a Customer Product/Process

Change Notiﬁcation (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no

license or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are

free from patent, copyright, or mask work right infringement, unless otherwise

speciﬁed.

Short-form speciﬁcation — The data in a short-form speciﬁcation is

extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Limiting values deﬁnition — Limiting values given are in accordance with

the Absolute Maximum Rating System (IEC 60134). Stress above one or

more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any

other conditions above those given in the Characteristics sections of the

speciﬁcation is not implied. Exposure to limiting values for extended periods

may affect device reliability.

ICs with MPEG-2 functionality — Use of this product in any manner that

complies with the MPEG-2 Standard is expressly prohibited without a license

under applicable patents in the MPEG-2 patent portfolio, which license is

available from MPEG LA, L.L.C., 250 Steele Street, Suite 300, Denver,

Colorado 80206.

ICs with MPEG-audio/AC-3/DTS audio functionality — Purchase of a

Philips IC with an MPEG-audio and/or AC-3 and/or DTS audio functionality

does not convey an implied license under any patent right to use this IC in

any MPEG-audio or AC-3 or DTS audio application. A license for

Application information — Applications that are described herein for any

of these products are for illustrative purposes only. Philips Semiconductors

makes no representation or warranty that such applications will be suitable for

the speciﬁed use without further testing or modiﬁcation.

MPEG-audio needs to be obtained via Sisvel S.p.a. - Società per lo Sviluppo

dell'Elettronica Via Castagnole, 59 . 10060 None (TO) Italy. A license for AC-3

and/or DTS needs to be obtained via Philips Intellectual Property and

Standards (www.ip.philips.com), e-mail: info.licensing@philips.com.

16. Disclaimers

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors

customers using or selling these products for use in such applications do so

at their own risk and agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

17. Trademarks

Notice — All referenced brands, product names, service names and

trademarks are the property of their respective owners.

I²C-bus — logo is a trademark of Koninklijke Philips Electronics N.V.

Right to make changes — Philips Semiconductors reserves the right to

make changes in the products - including circuits, standard cells, and/or

software - described or contained herein in order to improve design and/or

18. Contact information

For additional information, please visit: http://www.semiconductors.philips.com

For sales ofﬁce addresses, send an email to: sales.addresses@www.semiconductors.philips.com

SAA7130HL_4

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PCI video broadcast decoder

19. Contents

1

General description . . . . . . . . . . . . . . . . . . . . . . 1

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Overview of TV decoders with PCI bridge . . . . 2

Related documents. . . . . . . . . . . . . . . . . . . . . . 3

7

8

9

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 30

Thermal characteristics . . . . . . . . . . . . . . . . . 31

Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 31

1.1

1.2

1.3

10

10.1

10.1.1

10.1.2

Test information. . . . . . . . . . . . . . . . . . . . . . . . 38

Boundary scan test . . . . . . . . . . . . . . . . . . . . 38

Initialization of boundary scan circuit . . . . . . . 38

Device identiﬁcation codes. . . . . . . . . . . . . . . 38

2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

PCI and DMA bus mastering . . . . . . . . . . . . . . 4

TV video decoder and video scaling. . . . . . . . . 4

TV audio I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Peripheral interface. . . . . . . . . . . . . . . . . . . . . . 4

General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.1

2.2

2.3

2.4

2.5

11

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 40

12

12.1

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Introduction to soldering surface mount

packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 41

Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 41

Manual soldering . . . . . . . . . . . . . . . . . . . . . . 42

Package related soldering information. . . . . . 42

3

4

Ordering information. . . . . . . . . . . . . . . . . . . . . 5

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5

12.2

12.3

12.4

12.5

5

Pinning information. . . . . . . . . . . . . . . . . . . . . . 6

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7

Pin type description . . . . . . . . . . . . . . . . . . . . 11

5.1

5.2

5.2.1

13

14

15

16

17

18

Revision history . . . . . . . . . . . . . . . . . . . . . . . 44

Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 45

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Contact information . . . . . . . . . . . . . . . . . . . . 45

6

6.1

6.2

6.3

6.3.1

6.3.2

6.4

6.4.1

6.4.2

6.4.3

6.4.4

6.4.5

6.5

Functional description . . . . . . . . . . . . . . . . . . 12

Overview of internal functions. . . . . . . . . . . . . 12

Application examples . . . . . . . . . . . . . . . . . . . 13

Software support . . . . . . . . . . . . . . . . . . . . . . 16

Device driver. . . . . . . . . . . . . . . . . . . . . . . . . . 16

Supporting WDM . . . . . . . . . . . . . . . . . . . . . . 16

PCI interface. . . . . . . . . . . . . . . . . . . . . . . . . . 16

PCI conﬁguration registers . . . . . . . . . . . . . . . 16

ACPI and power states . . . . . . . . . . . . . . . . . . 17

DMA and conﬁgurable FIFO. . . . . . . . . . . . . . 18

Virtual and physical addressing . . . . . . . . . . . 18

Status and interrupts on PCI-bus . . . . . . . . . . 19

Analog TV standards . . . . . . . . . . . . . . . . . . . 19

Video processing . . . . . . . . . . . . . . . . . . . . . . 21

Analog video inputs . . . . . . . . . . . . . . . . . . . . 21

Video synchronization and line-locked clock . 22

Video decoding and automatic standard

6.6

6.6.1

6.6.2

6.6.3

detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Adaptive comb ﬁlter . . . . . . . . . . . . . . . . . . . . 22

Copy protection detection. . . . . . . . . . . . . . . . 23

Video scaling . . . . . . . . . . . . . . . . . . . . . . . . . 23

VBI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Signal levels and color space . . . . . . . . . . . . . 26

Video port, ITU and VIP codes. . . . . . . . . . . . 28

Analog audio pass-through and loopback

6.6.4

6.6.5

6.6.6

6.6.7

6.6.8

6.6.9

6.7

cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

DTV/DVB channel decoding and TS capture . 29

Control of peripheral devices . . . . . . . . . . . . . 29

I²C-bus master . . . . . . . . . . . . . . . . . . . . . . . . 29

Propagate reset . . . . . . . . . . . . . . . . . . . . . . . 30

GPIO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.8

6.9

6.9.1

6.9.2

6.9.3

All rights are reserved. Reproduction in whole or in part is prohibited without the prior

written consent of the copyright owner. The information presented in this document does

not form part of any quotation or contract, is believed to be accurate and reliable and may

be changed without notice. No liability will be accepted by the publisher for any

consequence of its use. Publication thereof does not convey nor imply any license under

patent- or other industrial or intellectual property rights.

Date of release: 11 April 2006

Document number: SAA7130HL_4

Published in The Netherlands


型号：	SAA7130HL/V1,518
厂家：	NXP
描述：	IC SPECIALTY CONSUMER CIRCUIT, PQFP128, 14 X 20 MM, 1.4 MM HEIGHT, MS-026, SOT-425-1, LQFP-128, Consumer IC:Other 商用集成电路
文件：	总46页 (文件大小：198K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SAA7130HL/V1,518 [NXP]

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