SAA7167 [NXP]
YUV-to-RGB Digital-to-Analog Converter DAC; YUV到RGB的数字 - 模拟转换器DAC的
| 型号： | SAA7167 |
| 厂家： | 
NXP |
| 描述： | YUV-to-RGB Digital-to-Analog Converter DAC |
| 文件： | 总20页 (文件大小：147K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
SAA7167
YUV-to-RGB Digital-to-Analog
Converter (DAC)
1995 Nov 03
Preliminary specification
Supersedes data of 1995 Jun 13
File under Integrated Circuits, IC22
Philips Semiconductors
Preliminary specification
YUV-to-RGB Digital-to-Analog
Converter (DAC)
SAA7167
FEATURES
• On-chip mixing of digital video data and analog
RGB signals
• Supports video input format of YUV 4 : 2 : 2, 4 : 1 : 1,
2 : 1 : 1 andRGB 5 : 6 : 5
• Video input rate up to 50 MHz
voltage output amplifier, capable of converting digital video
data to analog RGB video, and then mixing video and
external analog RGB inputs.
• Allows for both binary and two’s complement video
input data
• Triple 8-bit DACs for video output
• Built-in voltage output amplifier
The video data path contains a data re-formatter,
YUV-to-RGB colour space matrix as well as triple DACs for
video data processing. An analog mixer performs
multiplexing between DAC outputs of the video path and
external analog RGB inputs.
• Provide keying control with external key and internal
8-bit, 2 × 8-bit and 3 × 8-bit pixel colour key
• Programmable via the I2C-bus
• 5 V CMOS device; LQFP48 package.
The final analog outputs are buffered with built-in voltage
output amplifiers to provide the direct driving capability for
a 150 Ω load. Figure 1 shows the overall block diagram.
GENERAL DESCRIPTION
The operation of SAA7167 is controlled via the I2C-bus.
The SAA7167 is a mixed-mode designed IC containing a
video data path, keying control block, analog mixer, and a
QUICK REFERENCE DATA
SYMBOL
VDDD
PARAMETER
MIN.
4.75
MAX.
5.25
UNIT
digital supply voltage
analog supply voltage
V
V
VDDA
Tamb
4.75
0
5.25
70
operating ambient temperature
°C
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
SAA7167
LQFP48 plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm
SOT313-2
1995 Nov 03
2
Philips Semiconductors
Preliminary specification
YUV-to-RGB Digital-to-Analog
Converter (DAC)
SAA7167
BLOCK DIAGRAM
C
ref(h)
Bin Gin Rin
29 31 33
36
MIXER
MIXER
MIXER
Rout
Gout
Bout
OPAMP
OPAMP
OPAMP
32
30
28
YUV7 to
YUV0
38 to
45
YUV
TO
RGB
MATRIX
8-BIT
DAC
(3×)
RE-
FORMATTER
UV7 to
UV0
MUX
46 to 48,
1 to 5
HREF
9
22
23
24
SDA
SCL
RES
2
I C-BUS
CLOCK
GENERATOR
KEYING CONTROL
8
SAA7167
CONTROL
6
10
PCLK
21
13 to 20
MGB743
VCLK
EXTKEY
P7 to P0
Fig.1 Block diagram.
1995 Nov 03
3
Philips Semiconductors
Preliminary specification
YUV-to-RGB Digital-to-Analog
Converter (DAC)
SAA7167
PINNING
SYMBOL PIN
DESCRIPTION
I/O
UV4
UV3
UV2
UV1
UV0
1
2
3
4
5
digital video UV (of YUV format 4 : 1 : 1 and 4 : 2 : 2) input data, or digital G and R
input data
I
I
I
I
I
digital video UV (of YUV format 4 : 1 : 1 and 4 : 2 : 2) input data, or digital G and R
input data
digital video UV (of YUV format 4 : 1 : 1 and 4 : 2 : 2) input data, or digital G and R
input data
digital video UV (of YUV format 4 : 1 : 1 and 4 : 2 : 2) input data, or digital G and R
input data
digital video UV (of YUV format 4 : 1 : 1 and 4 : 2 : 2) input data, or digital G and R
input data
VCLK
VDDD
VSSD
HREF
PCLK
AP
6
video clock input
I
7
digital supply voltage
I/O
8
digital ground
I/O
9
horizontal reference input signal
pixel clock input
I
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
I
test pins, normally connected to ground
test pins, normally connected to ground
pixel bus input 7 (for keying control)
pixel bus input 6 (for keying control)
pixel bus input 5 (for keying control)
pixel bus input 4 (for keying control)
pixel bus input 3 (for keying control)
pixel bus input 2 (for keying control)
pixel bus input 1 (for keying control)
pixel bus input 0 (for keying control)
external key signal input
I
SP
I
P7
I
P6
I
P5
I
P4
I
P3
I
I
P2
P1
I
P0
I
EXTKEY
SDA
SCL
RES
n.c.
I
I2C-bus data line
I2C-bus clock line
set to LOW to reset the I2C-bus
I/O
I
I
not connected
−
VSSA2
VDDA2
Bout
Bin
analog ground 2
I/O
I/O
O
I
analog supply voltage 2
analog Blue signal output
analog Blue signal input
Gout
Gin
analog Green signal output
analog Green signal input
analog Red signal output
analog Red signal input
O
I
Rout
Rin
O
I
VSSA1
VDDA1
Cref(h)
analog ground 1
I/O
I/O
I/O
analog supply voltage 1
capacitor for reference high voltage output (2.25 V)
1995 Nov 03
4
Philips Semiconductors
Preliminary specification
YUV-to-RGB Digital-to-Analog
Converter (DAC)
SAA7167
SYMBOL PIN
DESCRIPTION
I/O
n.c.
37
38
39
40
41
42
43
44
45
46
not connected
−
YUV7
YUV6
YUV5
YUV4
YUV3
YUV2
YUV1
YUV0
UV7
digital video Y or UV (of YUV format 2 : 1 : 1) input data, or digital G and B input data
digital video Y or UV (of YUV format 2 : 1 : 1) input data, or digital G and B input data
digital video Y or UV (of YUV format 2 : 1 : 1) input data, or digital G and B input data
digital video Y or UV (of YUV format 2 : 1 : 1) input data, or digital G and B input data
digital video Y or UV (of YUV format 2 : 1 : 1) input data, or digital G and B input data
digital video Y or UV (of YUV format 2 : 1 : 1) input data, or digital G and B input data
digital video Y or UV (of YUV format 2 : 1 : 1) input data, or digital G and B input data
digital video Y or UV (of YUV format 2 : 1 : 1) input data, or digital G and B input data
I
I
I
I
I
I
I
I
I
digital video UV (of YUV format 4 : 1 : 1 and 4 : 2 : 2) input data, or digital G and R
input data
UV6
UV5
47
48
digital video UV (of YUV format 4 : 1 : 1 and 4 : 2 : 2) input data, or digital G and R
input data
I
I
digital video UV (of YUV format 4 : 1 : 1 and 4 : 2 : 2) input data, or digital G and R
input data
index
corner
C
V
1
2
36
35
34
33
UV4
UV3
ref(h)
DDA1
SSA1
V
UV2
3
4
UV1
Rin
UV0
5
32 Rout
31 Gin
6
VCLK
SAA7167
V
7
Gout
30
DDD
V
29 Bin
8
SSD
HREF
PCLK
AP
9
Bout
28
27
26
V
V
10
11
12
DDA2
SSA2
SP
25 n.c.
MGB744
Fig.2 Pin configuration.
5
1995 Nov 03
Philips Semiconductors
Preliminary specification
YUV-to-RGB Digital-to-Analog
Converter (DAC)
SAA7167
FUNCTIONAL DESCRIPTION
Table 2 Pixel byte sequence of 4 : 1 : 1
The SAA7167 contains a video data path, 3 analog mixers
and voltage output amplifiers for the RGB channels
respectively, a keying control block as well as an I2C-bus
control block.
INPUT
YUV0
YUV1
YUV2
YUV3
YUV4
YUV5
YUV6
YUV7
UV0
PIXEL BYTE SEQUENCE OF 4 : 1 : 1
Y0 Y0 Y0 Y0 Y0 Y0 Y0 Y0
Y1 Y1 Y1 Y1 Y1 Y1 Y1 Y1
Y2 Y2 Y2 Y2 Y2 Y2 Y2 Y2
Y3 Y3 Y3 Y3 Y3 Y3 Y3 Y3
Y4 Y4 Y4 Y4 Y4 Y4 Y4 Y4
Y5 Y5 Y5 Y5 Y5 Y5 Y5 Y5
Y6 Y6 Y6 Y6 Y6 Y6 Y6 Y6
Y7 Y7 Y7 Y7 Y7 Y7 Y7 Y7
Video data path
The video data path includes a video data re-formatter, a
YUV-to-RGB colour space conversion matrix, and triple
8-bit DACs.
RE-FORMATTER
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
The re-formatter de-multiplexes the different video formats
YUV 4 : 1 : 1, 4 : 2 : 2 or 2 : 1 : 1 to internal YUV 4 : 4 : 4,
which can then be processed by the RGB matrix. The pixel
byte sequences of those video input formats are shown in
Tables 1 to 4.
UV1
UV2
UV3
UV4
V6 V4 V2 V0 V6 V4 V2 V0
V7 V5 V3 V1 V7 V5 V3 V1
U6 U4 U2 U0 U6 U4 U2 U0
U7 U5 U3 U1 U7 U5 U3 U1
UV5
Table 1 Pixel byte sequence of 4 : 2 : 2
UV6
PIXEL BYTE SEQUENCE OF
UV7
INPUT
4 : 2 : 2
Y data
UV data
0
1
2
3
4
5
6
7
YUV0 (LSB)
YUV1
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
U0
U1
U2
U3
U4
U5
U6
U7
0
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
V0
V1
V2
V3
V4
V5
V6
V7
1
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
U0
U1
U2
U3
U4
U5
U6
U7
2
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
V0
V1
V2
V3
V4
V5
V6
V7
3
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
U0
U1
U2
U3
U4
U5
U6
U7
4
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
V0
V1
V2
V3
V4
V5
V6
V7
5
0
4
YUV2
Table 3 Pixel byte sequence of 2 : 1 : 1
YUV3
INPUT
YUV0
YUV1
YUV2
YUV3
YUV4
YUV5
YUV6
YUV7
Y data
UV data
PIXEL BYTE SEQUENCE OF 2 : 1 : 1
YUV4
U0 Y0 V0 Y0 U0 Y0 V0 Y0
U1 Y1 V1 Y1 U1 Y1 V1 Y1
U2 Y2 V2 Y2 U2 Y2 V2 Y2
U3 Y3 V3 Y3 U3 Y3 V3 Y3
U4 Y4 V4 Y4 U4 Y4 V4 Y4
U5 Y5 V5 Y5 U5 Y5 V5 Y5
U6 Y6 V6 Y6 U6 Y6 V6 Y6
U7 Y7 V7 Y7 U7 Y7 V7 Y7
YUV5
YUV6
YUV7 (MSB)
UV0 (LSB)
UV1
UV2
UV3
UV4
X
0
0
X
0
2
X
4
4
X
4
6
UV5
X
X
X
X
UV6
UV7 (MSB)
Y data
UV data
0
2
4
1995 Nov 03
6
Philips Semiconductors
Preliminary specification
YUV-to-RGB Digital-to-Analog
Converter (DAC)
SAA7167
Table 4 Pixel byte sequence of 5 : 6 : 5
Analog mixers and keying control
The analog mixers are controlled to switch between the
outputs from the video DACs and analog RGB inputs by a
keying signal. The analog RGB inputs need to interface
with analog mixers in the way of DC-coupling, also these
RGB inputs are limited to RGB signals without a sync level
pedestal. The keying control can be enabled by setting I2C
bit KEN = 1. Two kinds of keying are possible to generate:
one is external key (from EXTKEY pin when
KMOD2 to KMOD0 are logic 0), and the other is the
internal pixel colour key (when KMOD2 to KMOD0 are not
logic 0) generated by comparing the input pixel data with
the internal I2C-bus register value KD7 to KD0. Controlled
by KMOD2 to KMOD0 bits, there are 4 ways to compare
the pixel data (see Table 5).
PIXEL BYTE SEQUENCE OF RGB
INPUT
5 : 6 : 5
UV7
G0
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
B4
B3
B2
B1
B0
0
G0
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
B4
B3
B2
B1
B0
1
G0
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
B4
B3
B2
B1
B0
2
G0
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
B4
B3
B2
B1
B0
3
UV6
UV5
UV4
UV3
UV2
UV1
UV0
YUV7
YUV6
YUV5
YUV4
YUV3
YUV2
YUV1
YUV0
RGB data
Table 5 KMOD2 to KMOD0
KMOD2
to
PIXEL TYPE
REMARK
KMOD0
100
101
8-bit pixel
pseudo colour mode
2 × 8-bit pixel
high colour mode 1 with
pixels given at both rising
and falling edges of PCLK
110
111
2 × 8-bit pixel
3 × 8-bit pixel
high colour mode 2 with
pixels given only at rising
edges of PCLK
For RGB 5 : 6 : 5 video inputs, the video data are just
directly bypassed to triple DACs.
The input video data can be selected to either two’s
complement (I2C-bus DRP-bit = 0) or binary offset
(DRP-bit = 1). The video input format is selected by
I2C-bus bits FMTC1 and FMTC0.
true colour mode
Since only one control register KD7 to KD0 provides the
data value for pixel data comparison, when at 2 × 8-bit or
3 × 8-bit pixel input modes, it is presumed that all input
bytes (lower, middle, or higher) of each pixel must be same
as KD7 to KD0 in order to make graphics colour key
active.
The rising edge of HREF input defines the start of active
video data. When HREF is inactive, the video output will be
blanked.
YUV-TO-RGB MATRIX
The polarity of EXTKEY can be selected with KINV. With
KINV = 0, EXTKEY = HIGH switches analog mixers to
select DAC outputs. Before the internal keying signal
switches the analog multiplexers, it can be further delayed
up to 7 PCLK cycles with the control bits
The matrix converts YUV data, in accordance with
CCIR-601, to RGB data with approximately 1.5 LSB
deviation to the theoretical values for 8-bit resolution.
TRIPLE 8-BIT DACS
KDLY2 to KDLY0.
Three identical DACs for R, G and B video outputs are
designed with voltage-drive architecture to provide
high-speed operation of up to 50 MHz conversion data
rate. A Cref(h) pin is provided to allow for one external
de-coupling capacitor to be connected between the
internal reference voltage source and ground.
1995 Nov 03
7
Philips Semiconductors
Preliminary specification
YUV-to-RGB Digital-to-Analog
Converter (DAC)
SAA7167
With the digital input YUV video data in accordance with
CCIR-601, the RGB output of 8-bit DAC actually ranges
from the 16th step (black) to the 235th step (white).
Therefore, after the voltage divider with external serial
resistor and monitor load resistor, the output voltage range
to monitor is approximately 0.7 V (peak-to-peak).
Voltage output amplifiers
Before the analog input enters the analog mixers, it passes
through voltage output amplifiers. Level shifters are used
internally to provide an offset of 0.2 V and an amplifier gain
of 2 for analog inputs to match with the output levels from
DACs. After buffering with voltage output amplifiers, the
final RGB outputs can drive a 150 Ω load directly (25 Ω
internal resistor, 50 Ω external serial resistor, and 75 Ω
load resistor at monitor side (see Fig.9).
I2C-bus control
Only one control byte is needed for the SAA7167.
The I2C-bus format is shown in Table 6.
The output voltage level of DAC ranges from the lowest
level 0.2 V (zero code) to the highest level 1.82 V (all one
code).
Table 6 I2C-bus format
S
slave address
A
subaddress
A
data
A
P
Notes
1. S = START condition.
2. Slave address = 1011 111X; this slave address is identical to the one for the SAA9065; X = R/W control bit:
a) X = 0; order to write.
b) X = 1; order to read (not used for SAA7167).
3. A = acknowledge; generated by the slave.
4. Subaddress = subaddress byte.
5. Data = data byte.
6. P = STOP condition.
Table 7 Control data byte
SUBADDRESS
D7
KMOD2
0
D6
KMOD1
0
D5
KMOD0
0
D4
DRP
0
D3
KEN
0
D2
KINV
KDLY2
KD2
D1
D0
00
01
02
FMTC1
KDLY1
KD1
FMTC0
KDLY0
KD0
KD7
KD6
KD5
KD4
KD3
1995 Nov 03
8
Philips Semiconductors
Preliminary specification
YUV-to-RGB Digital-to-Analog
Converter (DAC)
SAA7167
Table 8 Bit functions in data byte; notes 1 and 2
BIT
DESCRIPTION
FMTC1 and FMTC0
video format control:
00; YUV 4 : 2 : 2
01; YUV 4 : 1 : 1
10; YUV 2:1:1/CCIR 656
11; RGB 5 : 6 : 5
key polarity:
KINV
KEN
KINV = 0: EXTKEY = HIGH for analog mixer to select DAC outputs
KINV = 1: EXTKEY = HIGH for analog mixer to select analog RGB inputs
key enable:
0 = disable
1 = enable
DRP
UV input data code: 0 = two’s complement; 1 = binary offset
keying mode:
KMOD2 to KMOD0
000; external key
100; 8-bit pixel colour key
101; 2 × 8-bit pixel colour key (with two-edge clock latching for pixel input)
110; 2 × 8-bit pixel colour key (with one-edge clock latching for pixel input)
111; 3 × 8-bit pixel colour key (with one-edge clock latching for pixel input)
all other combinations are reserved
KDLY2 to KDLY0
KD7 to KD0
added keying delay cycles (from 0 to 7 PCLK)
the data value compared for 8, 16 or 24-bit pixel colour key
Notes
1. All I2C-bus control bits are initialized to logic 0 after RES is activated.
2. PCLK should be active in any event to allow for correct operation of I2C-bus programming.
DC CHARACTERISTICS
Tamb = 0 to 70 °C.
SYMBOL
VDDD
PARAMETER
digital supply voltage
MIN.
4.75
TYP.
5.0
MAX.
5.25
UNIT
V
V
VDDA
IDDtot
VIH
analog supply voltage
4.75
5.0
100
−
5.25
total supply current (fclk = 50 MHz)
HIGH level input voltage (pin SDA)
LOW level input voltage (pin SDA)
HIGH level digital input voltage
−
−
mA
V
3
VDDD + 0.5
VIL
−0.5
2
−
+1.5
−
V
VIH
−
V
VIL
LOW level digital input voltage
−
−
0.8
−
V
Vin
full-scale analog RGB inputs
−
0.7
1.4
−
V
Vout
DNL
INL
full scale analog RGB outputs (for 150 Ω load)
differential non-linearity error of video output
integral non-linearity error of video output
−
−
V
−
1
LSB
LSB
−
−
1
1995 Nov 03
9
Philips Semiconductors
Preliminary specification
YUV-to-RGB Digital-to-Analog
Converter (DAC)
SAA7167
AC CHARACTERISTICS
Tamb = 0 to 70 °C.
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
50
UNIT
MHz
fclk
video clock rate
−
−
−
−
−
δ
duty factor of VCLK
50
−
−
%
PCLK
pixel clock rate (8-bit pixel colour key); see Fig.4
50
40
MHz
MHz
pixel clock rate (2 × 8-bit pixel colour key; mode 1);
−
see Fig.5
pixel clock rate (2 × 8-bit pixel colour key; mode 2);
−
−
80
MHz
see Fig.6
pixel clock rate (3 × 8-bit pixel colour key); see Fig.7
duty factor of PCLK
−
40
3
−
75
60
−
MHz
%
50
−
tsu1
th1
tsu2
th2
tsu3
th3
digital input set-up time to VCLK rising edge
digital input hold time to VCLK rising edge
digital input set-up time to PCLK rising edge
digital input hold time to PCLK rising edge
digital input set-up time to PCLK falling edge
digital input hold time to PCLK falling edge
ns
ns
ns
ns
ns
ns
ns
3
−
−
3
−
−
3
−
−
3
−
−
3
−
−
tsw
switching time between video DAC/analog inputs;
note 1
−
−
15
Tgroup
overall group delay from digital video inputs to analog
outputs (see Fig.8):
YUV video input mode
−
−
−
−
−
−
20TVCLK + tPD
−
ns
ns
ns
ns
ns
ns
RGB video input mode
12TVCLK + tPD
−
tr
DAC analog output rise time (see Fig.8); note 2
DAC analog output fall time (see Fig.8); note 2
DAC analog output settling time (see Fig.8); note 3
5
−
tf
5
−
ts
−
15
−
tPD
DAC analog output propagation delay (see Fig.8);
note 4
15
Analog outputs from analog inputs
Gv
B
voltage gain
bandwidth (−3 dB)
slew rate
−
−
−
2.0
75
90
−
−
−
MHz
SR
V/µs
Notes
1. Switching time measured from the 50% point of the EXTKEY transition edge to the 50% point of the selected analog
output transition.
2. DAC output rise/fall time measured between the 10% and 90% points of full scale transition.
3. DAC settling time measured from the 50% point of full-scale transition to the output remaining within ±1 LSB.
4. DAC analog output propagation delay measured from the 50% point of the rising edge of VCLK to the 50% point of
full-scale transition.
1995 Nov 03
10
Philips Semiconductors
Preliminary specification
YUV-to-RGB Digital-to-Analog
Converter (DAC)
SAA7167
VCLK
t
su1
HREF
t
h1
YUV
t
su1
UV
MGB745
Fig.3 Video data input timing.
h
PCLK
t
su2
t
h2
P7 to P0
pixel 1
pixel 2
pixel 3
pixel 4
pixel 5
pixel 6
pixel 7
MGB746
Fig.4 Pixel data timing; 8-bit pixel colour key.
11
1995 Nov 03
Philips Semiconductors
Preliminary specification
YUV-to-RGB Digital-to-Analog
Converter (DAC)
SAA7167
PCLK
t
t
su2
su3
t
t
h2
h3
P7 to P0
pixel 1
pixel 2
pixel 3
MGB747
Fig.5 Pixel data input timing; 2 × 8-bit pixel colour key; mode 1.
h
PCLK
t
su2
t
h2
P7 to P0
pixel 1
pixel 2
pixel 3
MGB748
Fig.6 Pixel data input timing; 2 × 8-bit pixel colour key; mode 2.
1995 Nov 03
12
Philips Semiconductors
Preliminary specification
YUV-to-RGB Digital-to-Analog
Converter (DAC)
SAA7167
h
PCLK
t
su2
t
h2
P7 to P0
MGB749
pixel 1
pixel 2
Fig.7 Pixel data input timing; 3 × 8-bit pixel colour key.
h
VCLK
T
group
YUV and UV
(full-scale transition)
t
s
t
PD
Rout, Bout and Gout
MGB750
t ; t
r
f
Fig.8 DAC output timing.
13
1995 Nov 03
Philips Semiconductors
Preliminary specification
YUV-to-RGB Digital-to-Analog
Converter (DAC)
SAA7167
APPLICATION INFORMATION
digital YUV video data inputs
8
38 to 45
C
ref(h)
36
YUV7 to YUV0
UV7 to UV0
8
0.1 µF
46 to 48,
1 to 5
to PC monitor
47 Ω
analog inputs from VGA
Rin
Gin
Bin
32
30
28
33
Rout
75 Ω
75 Ω
75 Ω
75 Ω
SAA7167
47 Ω
Gout
31
29
75 Ω
75 Ω
47 Ω
Bout
cable
monitor side
MGB751
Fig.9 Typical application diagram for analog circuits.
1995 Nov 03
14
Philips Semiconductors
Preliminary specification
YUV-to-RGB Digital-to-Analog
Converter (DAC)
SAA7167
PACKAGE OUTLINE
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
SOT313-2
c
y
X
36
25
A
E
37
24
Z
E
Q
e
H
E
A
2
A
(A )
3
A
1
w M
p
θ
pin 1 index
b
L
p
L
13
48
detail X
1
12
Z
v M
D
A
e
w M
b
p
D
B
H
v M
B
D
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
Q
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.20 1.45
0.05 1.35
0.27 0.18 7.1
0.17 0.12 6.9
7.1
6.9
9.15 9.15
8.85 8.85
0.75 0.69
0.45 0.59
0.95 0.95
0.55 0.55
1.60
mm
0.25
0.5
1.0
0.2 0.12 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
93-06-15
94-12-19
SOT313-2
1995 Nov 03
15
Philips Semiconductors
Preliminary specification
YUV-to-RGB Digital-to-Analog
Converter (DAC)
SAA7167
If wave soldering cannot be avoided, the following
conditions must be observed:
SOLDERING
Introduction
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
Even with these conditions, do not consider wave
soldering LQFP packages LQFP48 (SOT313-2),
LQFP64 (SOT314-2) or LQFP80 (SOT315-1).
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011). During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Reflow soldering
Reflow soldering techniques are suitable for all LQFP
packages.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Repairing soldered joints
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
Wave soldering
Wave soldering is not recommended for LQFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
1995 Nov 03
16
Philips Semiconductors
Preliminary specification
YUV-to-RGB Digital-to-Analog
Converter (DAC)
SAA7167
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1995 Nov 03
17
Philips Semiconductors
Preliminary specification
YUV-to-RGB Digital-to-Analog
Converter (DAC)
SAA7167
NOTES
1995 Nov 03
18
Philips Semiconductors
Preliminary specification
YUV-to-RGB Digital-to-Analog
Converter (DAC)
SAA7167
NOTES
1995 Nov 03
19
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SCD45
© Philips Electronics N.V. 1995
All rights are reserved. Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation
or contract, is believed to be accurate and reliable and may be changed without
notice. No liability will be accepted by the publisher for any consequence of its
use. Publication thereof does not convey nor imply any license under patent- or
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KARACHI 75600, Tel. (021)587 4641-49,
Fax. (021)577035/5874546
483061/1100/01/pp20
Date of release: 1995 Nov 03
9397 750 00416
Document order number:
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