SAA7712 [NXP]
Sound effects DSP; 音效DSP
| 型号： | SAA7712 |
| 厂家： | 
NXP |
| 描述： | Sound effects DSP |
| 文件： | 总44页 (文件大小：182K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
SAA7712H
Sound effects DSP
Preliminary specification
1999 Aug 05
File under Integrated Circuits, IC02
Philips Semiconductors
Preliminary specification
Sound effects DSP
SAA7712H
CONTENTS
9
I2C-BUS FORMAT
Addressing
Slave address (pin A0)
Write cycles
Read cycles
I2C-bus memory map summary
I2C-bus memory map details
9.1
9.2
9.3
9.4
9.5
9.6
1
FEATURES
1.1
1.2
Hardware features
Software features
2
3
4
5
6
7
8
APPLICATIONS
GENERAL DESCRIPTION
QUICK REFERENCE DATA
ORDERING INFORMATION
BLOCK DIAGRAM
10
11
12
13
14
15
16
17
18
19
19.1
LIMITING VALUES
THERMAL CHARACTERISTICS
DC CHARACTERISTICS
ANALOG OUTPUTS CHARACTERISTICS
OSCILLATOR CHARACTERISTICS
I2S-BUS TIMING CHARACTERISTICS
I2C-BUS TIMING CHARACTERISTICS
APPLICATION INFORMATION
PACKAGE OUTLINE
PINNING INFORMATION
FUNCTIONAL DESCRIPTION
8.1
Analog outputs
8.1.1
8.1.2
8.1.3
8.1.4
8.1.5
8.1.6
8.1.7
8.1.8
8.1.9
8.1.10
8.2
8.2.1
8.2.2
8.2.3
8.3
8.3.1
8.3.2
8.3.3
8.4
Analog output circuit
DAC frequency
DACs
Upsample filter
Performance
Power-On Mute (POM)
Power-off plop suppression
Pin VREFDA
Internal DAC current reference
Supply of the analog outputs
I2S-bus inputs and outputs
Digital data stream formats
Slave I2S-bus inputs
Master I2S-bus inputs and outputs
Equalizer accelerator
Introduction
Configuration of equalizer sections
Overflow detection
Clock circuit and oscillator
General description
SOLDERING
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
19.2
19.3
19.4
19.5
Suitability of surface mount IC packages for
wave and reflow soldering methods
20
21
22
DEFINITIONS
LIFE SUPPORT APPLICATIONS
PURCHASE OF PHILIPS I2C COMPONENTS
8.4.1
8.4.2
8.5
Supply of the crystal oscillator
Programmable phase-locked loop circuit
I2C-bus control
8.6
8.6.1
8.6.2
8.6.3
8.6.4
8.6.5
8.6.6
8.6.7
Introduction
Characteristics of the I2C-bus
Bit transfer
Start and stop conditions
Data transfer
Acknowledge
State of the I2C-bus interface during and after
Power-on reset
8.7
8.8
8.9
8.10
External control pins
Reset pin
Power supply connection and EMC
Test mode connections
1999 Aug 05
2
Philips Semiconductors
Preliminary specification
Sound effects DSP
SAA7712H
1
FEATURES
1.1
Hardware features
• Digital Signal Processor (DSP) core:
– 18 bits data width, 12 bits coefficient width
– Separate X, Y and P memories (both 384 bytes word
XRAM and YRAM, 3 kbytes word PROM)
1.2
Software features
– 1 kbytes delay line memory suited for Dolby Pro
Logic Surround.
• Dolby Pro Logic Surround/Dolby 3 stereo:
Trademark of Dolby Laboratories Licensing Corporation
• Inputs:
• Noise generation: A pink noise generator is included
for installation of the Dolby Pro Logic/Dolby 3 stereo
mode
– 2 slave 18-bit digital stereo inputs: I2S-bus and
LSB-justified serial formats
• Hall/Matrix Surround: When no Dolby Pro Logic
Surround source material is available then this mode
can be used to produce a signal in the surround channel
– 2 master 18-bit digital stereo inputs: I2S-bus and
LSB-justified serial formats.
• Outputs:
• Incredible Surround (222-IS): This algorithm expands
the stereo width (stereo expander). This is intended to
be used when the 2 speakers are placed close together
(TV set and Midi set).
– 4 DACs with 4-times oversampling and noise
shaping, fed to 4 output pins and configurable from
the DSP program, as left, right, front and surround
channels of a Dolby Pro Logic Surround system
– 2 master 18-bit digital stereo outputs: I2S-bus and
LSB-justified serial formats.
• Robust Incredible Surround (222-RIS): Same as
incredible surround only an alternative algorithm
• 3D Surround (422) or Incredible Virtual Surround:
Dolby Pro Logic Surround reproduced by 2 speakers
(L and R)
• 4-channel 5-band or 2-channel 10-band
I2C-bus controlled parametric equalizer
• I2C-bus microcontroller interface for:
• IS-3D Surround (422-IS): Same as 3D Surround (422)
– Access to full X and Y memory space
only with extra stereo width expander on left and right
– Control of hardware settings: selectors,
programmable clock generations, etc.
• RIS-3D Surround (422-RIS): Same as IS-3D Surround
(422) with alternative algorithm
• Controllable Phase-Locked Loop (PLL) to generate the
high frequency DSP clock from common fundamental
oscillator crystal
• 3D Surround (423) or Incredible Virtual Surround:
Dolby Pro Logic Surround reproduced by 3 speakers
(L, C and R)
• 3.3 V process with 3.3 or 5 V digital periphery:
• IS-3D Surround (423-IS): Same as 3D Surround (423)
– 3.3 or 5 V I2S-bus and I2C-bus microcontroller
interfacing.
only with extra stereo width expander on left and right
• RIS-3D Surround (423-RIS): Same as IS-3D Surround
(423-IS) with alternative algorithm
• Operating temperature range from 0 to 70 °C.
1999 Aug 05
3
Philips Semiconductors
Preliminary specification
Sound effects DSP
SAA7712H
• Voice cancelling (karaoke): Rejects voice out of
source material, mainly intended to be used with
karaoke. Several karaoke modes available in stereo
mode and in Dolby Pro Logic mode, such as (auto) voice
cancel, (auto) centre voice cancel, (auto) multi left and
(auto) multi right.
3
GENERAL DESCRIPTION
The SAA7712H provides for digital signal processing
power in TV systems and home theatre systems.
A DSP core is equipped with digital inputs and outputs, a
5-band parametric equalizer accelerator, a digital
co-processor interface and a delay line memory. This
architecture accommodates on-chip standard sound
processing, incredible surround, Dolby Pro Logic Surround
and other surround sound processing algorithms.
The architecture also supports co-processing, e.g. to add
to the processing power of the internal DSP core or for
multi-channel surround decoding.
• Microphone mix modes (karaoke): Mono microphone
mixed to left, right and centre channel
• Spectrum analysis: 3-band spectrum analyser is
provided
• Dolby B: Both a Dolby B encoder as well as a Dolby B
decoder is implemented
• 2 Room solution: In all modes not requiring more than
2 output channels (stereo and karaoke incredible
surround) it is also possible to feed the source signal to
the other 2 output channels (with same processed or
not processed signal)
All settings and parameters are controlled by an I2C-bus
interface. The available interfaces support a high
application flexibility.
The DSP core communicates over 32 dedicated registers.
The selected digital input is master for the data rate of the
DSP core. This input can be selected among 2 slave
I2S-bus inputs. The 4 outputs from the core are passed
through 4 DACs and then routed to 4 output pins.
• Dynamic Bass Enhancement (DBE): Dynamic bass
enhancement generates a sub-woofer channel, which is
either a separate output or is added to the front channels
• Volume processing: Independent volume processing
of all 4 output channels
Two master I2S-bus outputs and two master I2S-bus
inputs can serve as an I2S-bus co-processor interface.
• AC-3/MPEG-2: Inputs available intended to be used
with an AC-3/MPEG-2 co-processor. In this mode the
SAA7712H can be used as post-processor.
Eight of the remaining registers are used for
communication with the hardware equalizer, and eight for
communication with the delay line memory.
• Output redirection: Several output configurations are
possible (normal 4 channel, special 4 + 2 channel,
record 2 + 2 channel, 6 or 6 + 2 channel).
All I2S-bus inputs and outputs support the Philips I2S-bus
format as well as 16, 18 and 20-bit LSB-justified formats.
Depending on the sample frequency several combinations
of the above mentioned features are possible.
2
APPLICATIONS
The SAA7712H can be used in TV sets with:
• Dolby Pro Logic Surround, incredible surround,
3D Surround and advanced acoustics processing
• Multi-channel sound decoding (AC-3 and MPEG-2) on a
co-processor. The SAA7712H can be used for
post-processing.
1999 Aug 05
4
Philips Semiconductors
Preliminary specification
Sound effects DSP
SAA7712H
4
QUICK REFERENCE DATA
SYMBOL
VDD3V
PARAMETER
CONDITION
MIN.
TYP.
3.3
MAX.
3.6
UNIT
supply voltage 3.3 V analog
and digital
with respect to VSS
3
V
V
VDD5V
IDDD3V
supply voltage 5 V periphery
with respect to VSS
3
3.3 or 5 5.5
DC supply current of the 3.3 V at fDSP18; maximum activity
digital core part
−
−
80
mA
mA
mA
mA
W
of the DSP
IDDD5V
DC supply current of the 5 V
digital periphery part
at fDSP18; maximum activity
of the DSP; VDD5 = 5 V
−
−
−
−
−
−
5
at fDSP18; maximum activity
of the DSP; VDD5 = 3.3 V
−
5
IDDA
Ptot
DC supply current of the
analog part
at zero input and output
signal
−
10
0.4
−60
total power dissipation
at fDSP18; maximum activity
of the DSP
−
(THD + N)/S DAC total harmonic
RL > 5 kΩ; f = 1 kHz;
−75
dBA
distortion-plus-noise to output A-weighted
signal
DRDAC
DSDAC
DAC dynamic range
f = 1 kHz; −60 dB;
A-weighted
90
96
−
dBA
dBA
DAC digital silence
f = 20 Hz to 17 kHz;
A-weighted
−
−107
−102
fxtal
crystal frequency
10.000
−
−
−
19.456 MHz
32.256 MHz
32.544 MHz
fDSP16
fDSP18
DSP clock frequency
DSP clock frequency
fxtal = 16.384 MHz
fxtal = 18.432 MHz
−
−
5
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
SAA7712H
QFP80
plastic quad flat package; 80 leads (lead length 1.95 mm);
SOT318-1
body 14 × 20 × 2.7 mm; high stand-off height
1999 Aug 05
5
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g
VREFDA POM
15
8
SAA7712H
SURROUND
CHANNEL
DELAY
18
19
OUT0_I
3D
2-CHANNEL
10-BAND
EQUALIZER
OUT0_V
27
29
28
2
I S_IN1_WS
SURROUND
from
audio
source 1
INCREDIBLE
SURROUND
(IS, RIS)
17
16
2
I S_IN1_BCK
OUT1_I
2
I S_IN1_DATA
2
OUT1_V
I S-BUS
VOLUME
PROCESSING
QUAD
DAC
IS-3D
SURROUND
INPUT
SWITCH
DOLBY PRO LOGIC
11
12
24
26
25
or
DOLBY 3 STEREO
or
2
OUT2_I
I S_IN2_WS
from
audio
source 2
2
OUT2_V
I S_IN2_BCK
4-CHANNEL
5-BAND
EQUALIZER
HALL/MATRIX
2
RIS-3D
SURROUND
I S_IN2_DATA
10
9
OUT3_I
CENTRE
VOICE
OUT3_V
21
CANCELLING
SYS_CLK
2
44
I C-BUS
OSCILLATOR
AND PLL
HOST I/O
TEST
A0
INTERFACE
62
63 47 48 31 32 30 33 36 37
60 59 58 20 40 41 38 39 57
76 77
46
45
SDA SCL
MGS206
Fig.1 Block diagram.
Philips Semiconductors
Preliminary specification
Sound effects DSP
SAA7712H
7
PINNING INFORMATION
SYMBOL
n.c.
PIN
DESCRIPTION
PIN TYPE
1
2
3
4
5
6
7
8
9
not connected
not connected
not connected
not connected
not connected
not connected
not connected
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
POM
power-on mute; timing determined by external capacitor
analog voltage output 3
AP2D
AP2D
AP2D
AP2D
AP2D
APVSS
APVDD
AP2D
AP2D
AP2D
AP2D
AP2D
B4CR
BT4CR
VDD5
VSS5
OUT3_V
OUT3_I
OUT2_I
OUT2_V
VSSA2
10 analog current output 3
11 analog current output 2
12 analog voltage output 2
13 analog ground supply 2
VDDA2
14 analog supply voltage 2 (3 V)
15 voltage reference of the analog part
16 analog voltage output 1
VREFDA
OUT1_V
OUT1_I
OUT0_I
OUT0_V
EQOV
SYS_CLK
VDDD5V1
VSSD5V1
I2S_IN2_WS
17 analog current output 1
18 analog current output 0
19 analog voltage output 0
20 equalizer overflow line output
21 test pin output
22 digital supply voltage 1; peripheral cells only (3 or 5 V)
23 digital ground supply 1; peripheral cells only (3 or 5 V)
24 I2S-bus or LSB-justified format word select input from a digital audio source 2 IBUFD
I2S_IN2_DATA 25 I2S-bus or LSB-justified format left-right data input from a digital audio
source 2
IBUFD
I2S_IN2_BCK
I2S_IN1_WS
26 I2S-bus clock or LSB-justified format input from a digital audio source 2
27 I2S-bus or LSB-justified format word select input from a digital audio source 1 IBUFD
IBUFD
I2S_IN1_DATA 28 I2S-bus or LSB-justified format left-right data input from a digital audio
source 1
IBUFD
I2S_IN1_BCK
I2S_IO_BCK
I2S_IO_IN1
I2S_IO_IN2
I2S_IO_WS
VDDD5V2
29 I2S-bus clock or LSB-justified format input from a digital audio source 1
30 I2S-bus bit clock output for interface with DSP co-processor chip
31 I2S-bus input data channel 1 from DSP co-processor chip
32 I2S-bus input data channel 2 from DSP co-processor chip
33 I2S-bus word select output for interface with DSP co-processor chip
34 digital supply voltage 2; peripheral cells only (3 or 5 V)
35 digital ground supply 2; peripheral cells only (3 or 5 V)
36 I2S-bus output data channel 1 to DSP co-processor chip
37 I2S-bus output data channel 2 to DSP co-processor chip
38 digital input 1 of the DSP core (F0 of the status register)
IBUFD
BT4CR
IBUFD
IBUFD
BT4CR
VDD5
VSSD5V2
VSS5
I2S_IO_OUT1
I2S_IO_OUT2
DSP_IN1
BT4CR
BT4CR
IBUFD
1999 Aug 05
7
Philips Semiconductors
Preliminary specification
Sound effects DSP
SAA7712H
SYMBOL
DSP_IN2
PIN
DESCRIPTION
PIN TYPE
39 digital input 2 of the DSP-core (F1 of the status register)
40 digital output 1 of the DSP-core (F2 of the status register)
41 digital output 2 of the DSP-core (F3 of the status register)
42 digital supply voltage 3; peripheral cells only (3 or 5 V)
43 digital ground supply 3; peripheral cells only (3 or 5 V)
44 I2C-bus slave subaddress selection input
45 I2C-bus serial clock input
IBUFD
B4CR
DSP_OUT1
DSP_OUT2
VDDD5V3
VSSD5V3
A0
B4CR
VDD5
VSS5
IBUFD
SCHMITCD
BD4SCI4
BD4CR
BT4CR
VSS3S
VSS3S
VSS3S
VDD3
SCL
SDA
46 I2C-bus serial data input/output
TEST1
47 test pin 1
TEST2
48 test pin 2
VSSD3V1
VSSD3V2
VSSD3V3
VDDD3V1
VDDD3V2
VSSD3V4
VSSD3V5
VSSD3V6
DSP_RESET
RTCB
49 digital ground supply 1 of 3 V core only
50 digital ground supply 2 of 3 V core only
51 digital ground supply 3 of 3 V core only
52 digital supply voltage 1 of 3 V core only
53 digital supply voltage 2 of 3 V core only
54 digital ground supply 4 of 3 V core only
55 digital ground supply 5 of 3 V core only
56 digital ground supply 6 of 3 V core only
57 reset (active LOW)
VDD3
VSS3S
VSS3S
VSS3S
IBUFU
IBUFD
IBUFD
IBUFD
VSS3S
58 asynchronous reset test control block (active LOW)
59 shift clock test control block
SHTCB
TSCAN
VSS_OSC
OSC_IN
60 scan control
61 ground supply crystal oscillator circuit
62 crystal oscillator input; crystal oscillator sense for gain control or forced input OSC
in slave mode
OSC_OUT
VDD_OSC
n.c.
63 crystal oscillator output; drive output to 11.2896 MHz crystal
64 3 V supply voltage crystal oscillator circuit
65 not connected
OSC
VDD3
n.c.
66 not connected
n.c.
67 not connected
n.c.
68 not connected
n.c.
69 not connected
n.c.
70 not connected
n.c.
71 not connected
n.c.
72 not connected
n.c.
73 not connected
n.c.
74 not connected
n.c.
75 not connected
VDACP1
VDACN1
76 not used
77 not used
1999 Aug 05
8
Philips Semiconductors
Preliminary specification
Sound effects DSP
SAA7712H
SYMBOL
n.c.
PIN
DESCRIPTION
PIN TYPE
78 not connected
79 not connected
80 not connected
n.c.
n.c.
Table 1 Pin types
PIN NAME
PIN DESCRIPTION
4 mA slew rate controlled digital output
B4CR
BD4CR
BD4CRD
BT4CR
IBUF
4 mA slew rate controlled digital I/O
4 mA slew rate controlled digital I/O with pull-down resistor
4 mA slew rate controlled 3-state digital output
digital input
IBUFU
IBUFD
BD4SCI4
SCHMITCD
AP2D
digital input with pull-up resistor
digital input with pull-down resistor
I2C-bus input/output with open-drain NMOS 4 mA output
Schmitt trigger input
analog input/output
OSC
analog input/output
VDD5
5 V VDD internal
VDD3
3 V VDD internal
VSS3S
VSS5
3 or 5 V VSS internal substrate
5 V VSS external
APVDD
APVSS
analog VDD
analog VSS
1999 Aug 05
9
Philips Semiconductors
Preliminary specification
Sound effects DSP
SAA7712H
V
64
n.c.
n.c.
1
2
3
4
5
6
7
8
9
DD_OSC
63 OSC_OUT
62 OSC_IN
n.c.
V
n.c.
61
SS_OSC
n.c.
60 TSCAN
n.c.
SHTCB
RTCB
59
58
n.c.
POM
OUT3_V
57 DSP_RESET
V
56
55
54
53
52
51
50
49
SSD3V6
SSD3V5
SSD3V4
DDD3V2
DDD3V1
V
V
V
V
OUT3_I 10
OUT2_I 11
OUT2_V 12
SAA7712H
V
V
13
14
SSA2
V
V
V
DDA2
SSD3V3
SSD3V2
SSD3V1
VREFDA 15
OUT1_V 16
OUT1_I 17
OUT0_I 18
OUT0_V 19
EQOV 20
48 TEST2
TEST1
47
46 SDA
45 SCL
44 A0
V
SYS_CLK 21
V
22
23
43
42
DDD5V1
SSD5V3
DDD5V3
V
V
SSD5V1
2
I S_IN2_WS 24
41 DSP_OUT2
MGS207
Fig.2 Pin configuration.
10
1999 Aug 05
Philips Semiconductors
Preliminary specification
Sound effects DSP
SAA7712H
8
FUNCTIONAL DESCRIPTION
Analog outputs
8.1.3
DACS
8.1
Each of the four low noise high dynamic range DACs
consists of a signed-magnitude DAC with current output,
followed by a buffer operational amplifier.
8.1.1
ANALOG OUTPUT CIRCUIT
Depending on the configuration of the equalizer sections,
the SAA7712H has 2 or 4 analog outputs which are
supplied by the same power supply. Each of these outputs
has a voltage and a current pin (see Fig.3). The signals are
available on 2 outputs (OUT0 and OUT1), or 4 outputs
(OUT0, OUT1, OUT2 and OUT3).
8.1.4
UPSAMPLE FILTER
To reduce spectral components above the audio band, a
fixed 4 times oversampling and interpolating digital filter is
used. The filters give an out-of-audio-band attenuation of
at least 29 dB. The filter is followed by a first-order noise
shaper to expand the dynamic range to more than 105 dB.
The band around multiples of the sample frequency of the
DAC (4fs) is not affected by the digital filter. A capacitor
must be added in parallel with the DAC output amplifier to
attenuate this out-of-band noise further to an acceptable
level.
handbook, halfpage
OUT0_I
(OUT1_I)
OUT0_V
(OUT1_V)
In Fig.4 the overall frequency spectrum at the DAC audio
output without external capacitor or low-pass filter for the
audio sampling frequencies of 38 kHz is shown. In Fig.5
the detailed spectrum around fs is shown for an fs of
38, 44.1 and 48 kHz. The pass band bandwidth (−3 dB) is
1⁄2fs.
MSB
V
ref
BIT 0 to 13
DAC
MGS208
Fig.3 Analog output circuit.
8.1.2
DAC FREQUENCY
The sample rate (fs) of the selected source is the frame
rate of the DSP. The word clock for the upsample filter and
the clock for the DACs, at 4fs, are derived internally from
the word select of the selected audio source.
1999 Aug 05
11
Philips Semiconductors
Preliminary specification
Sound effects DSP
SAA7712H
MGS209
0
α
(dB)
−10
−20
−30
−40
−50
−60
0
100
200
300
400
500
f
= 38000 Hz
f (kHz)
s
Fig.4 Overall frequency spectrum audio output.
MGS210
0
α
(dB)
−10
−20
−30
−40
−50
0
10000
20000
23211
25263
30000
f
f
f
= 38000 Hz
= 44100 Hz
= 48000 Hz
s
s
s
0
0
11605
12632
34816
37895
f (Hz)
Fig.5 Detailed frequency spectrum audio output.
12
1999 Aug 05
Philips Semiconductors
Preliminary specification
Sound effects DSP
SAA7712H
8.1.5
PERFORMANCE
8.1.6
POWER-ON MUTE (POM)
The signed-magnitude noise-shaped DAC has a dynamic
range in excess of 100 dB. The signal-to-noise ratio of the
audio output at full-scale is determined by the word length
of the converter. The noise at low outputs is fully
determined by the noise performance of the DAC. Since it
is a signed-magnitude type, the noise at digital silence is
also low. As a disadvantage, the total THD is higher than
conventional DACs. The typical total harmonic
To avoid any uncontrolled noise at the audio outputs after
power-on of the IC, the reference current source of the
DAC is switched off. The capacitor on pin POM
determines the time after which this current has a soft
switch-on. So at power-on the current audio signal outputs
are always muted. The loading of the external capacitor is
done in two stages via two different current sources.
The loading starts at a current level that is 9 times lower
than the current loading after the voltage on pin POM has
passed the 1 V level. This results in an almost dB linear
behaviour.
distortion-plus-noise to signal ratio as a function of the
output level is shown in Fig.6.
8.1.7
POWER-OFF PLOP SUPPRESSION
Power should still be provided to the analog part of the
DAC, while the digital part is switching off. As a result, the
output voltage will decrease gradually allowing the power
amplifier some extra time to switch-off without audible
plops. If a 5 V power supply is present, the supply voltage
of the analog part of the DAC can be fed from the 5 V
power supply via a 1.8 V zener diode. A capacitor,
connected to the 3.3 V power supply, provides power to
the analog part when the 5 V power supply is switching off
fast.
MGS211
−20
handbook, halfpage
(THD
+ N)/S
(dB)
−40
−60
−80
−80
−60
−40
−20
0
output level (dB)
Fig.6 Typical (THD + N)/S curve as a function of
the output level.
1999 Aug 05
13
Philips Semiconductors
Preliminary specification
Sound effects DSP
SAA7712H
I2S-bus inputs and outputs
8.1.8
PIN VREFDA
8.2
With two internal resistors half the supply voltage (VDDA2
is obtained and coupled to an internal buffer. This
reference voltage is used as DC voltage for the output
operational amplifiers and as reference for the DAC.
In order to obtain the lowest noise and to have the best
)
8.2.1
DIGITAL DATA STREAM FORMATS
For communication with external digital sources a serial
3-line bus is used. This I2S-bus has one line for data, one
line for clock and one line for the word select.
ripple rejection, a filter capacitor has to be added between
this pin and ground.
See Fig.7 for the general waveform formats of the four
possible formats.
The serial digital inputs (and outputs) of the SAA7712H are
capable of handling multiple formats: Philips I2S-bus and
LSB-justified formats of 16, 18 and 20 bits word sizes.
8.1.9
INTERNAL DAC CURRENT REFERENCE
As a reference for the internal DAC current and for the
DAC current source output, a current is drawn from the
level on pin VREFDA to pin VSSA2 (ground) via an internal
resistor. The absolute value of this resistor also
determines the absolute current of the DAC. This means
that the absolute value of the current is not that fixed due
to the spread of the current reference resistor value. This,
however, does not influence the absolute output voltages
because these voltages are also derived from a
conversion of the DAC current to the actual output voltage
via internal resistors.
In Philips I2S-bus format, the number of bit clock (BCK)
pulses may vary in the application. When the transmitter
word length is smaller than the receiver word length, the
receiver will fill in zeroes at the LSB side. When the
transmitter word length exceeds the receiver word length,
the LSBs are skipped. For correct operation of the DACs,
there should be a minimum of 16 bit clocks per word
select.
In the LSB-justified formats, the transmitter and receiver
must be set to the same format. Be aware that a format
switch between 20, 18 and 16 bits LSB-justified formats is
done by changing the relative timing of the word select
edges. The data bits remain unchanged. In the 20 bits
format, the 2 LSBs are zeroes. In the 16 bits format, the
2 data bits following the word select edge are not zero, but
undefined. In fact, these are the LSBs of the 18-bit word.
8.1.10 SUPPLY OF THE ANALOG OUTPUTS
All the analog circuitry of the DACs and the operational
amplifiers are fed by 2 supply pins, VDDA2 and VSSA2
Pin VDDA2 must have sufficient decoupling to prevent THD
degradation and to ensure a good power supply rejection
ratio.
.
The timing specification for the waveforms of the serial
digital inputs and outputs are given in Fig.17.
The digital part of the DAC is fully supplied from the chip
core supply.
1999 Aug 05
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WS
BCK
LEFT
3
RIGHT
3
1
2
1
2
DATA
MSB B2
MSB B2
MSB
2
INPUT FORMAT I S-BUS
WS
RIGHT
16
LEFT
16
15
2
1
15
2
1
BCK
DATA
MSB B2
B15 LSB
MSB B2
B15 LSB
LSB-JUSTIFIED FORMAT 16 BITS
WS
RIGHT
LEFT
18
17
16
B3
15
2
1
18
17
16
15
2
1
BCK
DATA
LSB
LSB
MSB B2
B4
B17
MSB B2
B3
B4
B17
LSB-JUSTIFIED FORMAT 18 BITS
WS
LEFT
RIGHT
20
19
18
17
B4
16
B5
15
B6
2
1
20
19
18
B3
17
16
15
B6
2
1
BCK
LSB
LSB
DATA
MSB B2
B3
B19
MSB B2
B4
B5
B19
MGS212
LSB-JUSTIFIED FORMAT 20 BITS
Fig.7 All serial data I/O formats.
ahdnbok,uflapegwidt
Philips Semiconductors
Preliminary specification
Sound effects DSP
SAA7712H
8.2.2
SLAVE I2S-BUS INPUTS
Table 3 I2C-bus audio_source mode bit (0FF9H,
see Table 13)
The SAA7712H has two slave I2S-bus inputs, I2S_IN1 and
I2S_IN2 with respective data lines I2S_IN1_DATA and
I2S_IN2_DATA, word select lines I2S_IN1_WS and
I2S_IN2_WS and bit clock lines I2S_IN1_BCK and
I2S_IN2_BCK. The external source is master and supplies
the bit clock and word select. The I2C-bus bits
AUDIO_SOURCE
OUTPUT
Bit 5
0
1
I2S_IN1 (default)
I2S_IN2
audio_format(2 to 0) allow for selection of the desired
I2S-bus format (see Table 13). The bits, needed for
selecting a certain format, are explained in Table 2.
8.2.3
MASTER I2S-BUS INPUTS AND OUTPUTS
For the co-processor I/O interface, the SAA7712H acts as
a master. The SAA7712H supplies both the bit clock and
word select. The I2C-bus bits host_io_format(1 and 0)
allow for selection of the desired I2S-bus format (see
Table 13).
The input circuitry is limited in handling the number of BCK
pulses per WS period. If the word rate of the selected
digital input source is fs, the bit clock must be a continuous
clock in the range of 16fs ≤ fbit(CLK) ≤ 256fs. The minimum
limit of the audio sample frequency is determined by
1⁄18fSCL. The maximum limit of the audio sample frequency
is determined by DSP_clock/481 Hz.
The bits needed for selecting a certain format are given in
Table 4.
All I2S-bus output lines, I2S_IO_WS, I2S_IO_BCK,
I2S_IO_OUT1 and I2S_IO_OUT2, can be 3-stated with
I2C-bus bit en_host_io (see Table 13).
Table 2 I2C-bus audio_format mode bits (0FF9H,
see Table 13)
The word select and bit clock of the co-processor I/O
interface are derived from the word select and bit clock of
the audio source selected according to Table 3.
The incoming bit clock can be divided by 1, 2, 4 or 8
depending on the needs of an external connected
co-processor. These selections can be done with I2C-bus
bits cloop_mode(2 to 0) (see Table 13). The meaning of
these bits is shown in Table 5.
AUDIO_FORMAT
OUTPUT
BIT 9 BIT 8 BIT 7
0
0
0
internal format (for test
purposes only)
−
−
−
1
0
1
1
0
1
0
1
0
LSB-justified, 16 bits
LSB-justified, 18 bits
LSB-justified, 20 bits
standard I2S-bus (default)
The selection of the DSP input among the decimated
analog input and the I2S-bus inputs I2S_IN1 and I2S_IN2
is controlled with I2C-bus bit audio_source (see Table 13).
The meaning of this bit can be found in Table 3.
1999 Aug 05
16
Philips Semiconductors
Preliminary specification
Sound effects DSP
SAA7712H
Table 4 I2C-bus host_io_format bits (0FF9H, see Table 13)
HOST_IO_FORMAT
OUTPUT
standard I2S-bus (default)
BIT 11
BIT 10
0
0
1
1
0
1
0
1
LSB-justified format, 16 bits
LSB-justified format, 18 bits
LSB-justified format, 20 bits
Table 5 I2C-bus cloop_mode bits (0FF9H, see Table 13)
CLOOP_MODE
OUTPUT
BIT 15
BIT 14
BIT 13
0
1
−
−
−
−
−
−
0
0
1
1
−
−
0
1
0
1
bypass WS (default)
WS 50% duty factor
bypass BCLK (default)
divide BCLK by 2
divide BCLK by 4
divide BCLK by 8
8.3
Equalizer accelerator
If the gain setting causes the audio signal to exceed the
maximum level in one of the filter sections, the signal will
be clipped and the equalizer overflow output (pin EQOV)
will be set HIGH until the end of the next audio sample
period.
8.3.1
INTRODUCTION
The equalizer accelerator is a hardware accelerator to the
DSP core. Both its inputs and outputs are stored in
registers of the DSP core.
8.3.2
CONFIGURATION OF EQUALIZER SECTIONS
The equalizer cannot be used and cannot be programmed
if no word select and bit clock signal are present on a
selected digital source input; see audio_source bit in
Table 3 (I2S_IN1 or I2S_IN2). The minimum required
DSP_clock is 481fs.
The equalizer accelerator can make a 2-channel equalizer
of 10 second-order sections per channel or a 4-channel
equalizer of 5 second-order sections per channel.
The sections of one channel can be chained one after the
other. Depending on the I2C-bus control bit two_four
(see Table 11), the 20 filter sections are combined for the
appropriate configuration, as illustrated in Fig.8.
The equalizer accelerator contains one second-order filter
data path that is 20 times multiplexed. With this circuit, a
2-channel equalizer of 10 second-order sections per
channel or a 4-channel equalizer of 5 second-order
sections per channel can be realised. The centre
frequency, gain and Q-factor of all 20 second-order
sections can be set independently from each other. Every
section is followed by a selectable attenuation of 0 or 6 dB.
Per section, 4 bytes of the I2C-bus register are needed to
store the settings. The equalizer settings can be updated
during normal operation. An application program supports
the programming of the equalizer.
1999 Aug 05
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Philips Semiconductors
Preliminary specification
Sound effects DSP
SAA7712H
1
2
3
4
5
A
B
C
D
IN0
IN1
IN2
IN3
OUT0
2 channel
OUT1
OUT2
OUT3
2 channel
MGS213
Fig.8 Configurations of the equalizer sections.
8.3.3
OVERFLOW DETECTION
The gain of the oscillator is internally controlled by the
AGC block. A sine wave with a peak-to-peak voltage close
to the oscillator power supply voltage is generated.
The AGC block prevents clipping of the sine wave and
therefore the higher harmonics are as low as possible.
At the same time, the voltage of the sine wave is as high
as possible so reducing the jitter going from sine wave to
clock signal. The sinusoidal output is converted into a
CMOS compatible clock by the comparator.
The equalizer has an overflow flag. This flag is fed to
output pin EQOV. If an overflow is detected in one of the
filter sections, the signal is clipped to the maximum
allowed level. The overflow flag is immediately set.
It remains at a HIGH-level during the remaining part of the
current audio sample period and for the whole next sample
period. If no overflow is detected during this next sample
period, the overflow flag goes to a LOW-level at the
beginning of the sample period after that. Otherwise, the
overflow flag remains at a HIGH-level for at least one other
audio sample period.
The second mode of operation shown in Fig.10, is the
slave mode which is driven by a master clock directly.
The signal to pin OSC_IN can be driven to the power
supply voltages VDD_OSC and VSS_OSC
.
8.4
Clock circuit and oscillator
8.4.2
SUPPLY OF THE CRYSTAL OSCILLATOR
8.4.1
GENERAL DESCRIPTION
The power supply connections of the oscillator are
separate from the other supply lines. This is to minimize
the feedback from the ground bounce of the chip to the
oscillator circuit. Pin VSS_OSC is used as the ground supply
and pin VDD_OSC as the positive supply.
The chip has a crystal clock oscillator. It can use a crystal
at either fxtal = 16.384 MHz = 512 × 32 kHz or
fxtal = 18.432 MHz = 576 × 32 kHz in fundamental mode.
The block diagram of this Pierce oscillator is shown in
Fig.9. The active element needed to compensate for the
loss resistance of the crystal is the block Gm. This block is
placed between the external pins OSC_IN
and OSC_OUT.
1999 Aug 05
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Philips Semiconductors
Preliminary specification
Sound effects DSP
SAA7712H
0.5V
DD_OSC
Gm
AGC
clock out
100 kΩ
R
bias
on chip
off chip
62
63
OSC_OUT
64
V
61
V
OSC_IN
DD_OSC
SS_OSC
MGS214
C1
10 pF
C2
10 pF
Fig.9 Block diagram of the crystal oscillator circuit.
0.5V
DD_OSC
Gm
AGC
clock out
100 kΩ
R
bias
on chip
off chip
62
63
64
V
61
V
OSC_IN
OSC_OUT
DD_OSC
SS_OSC
MGS215
C3
5 pF
C1
10 pF
C2
10 pF
slave input
Fig.10 Block diagram of the oscillator in slave mode.
19
1999 Aug 05
Philips Semiconductors
Preliminary specification
Sound effects DSP
SAA7712H
8.5
Programmable phase-locked loop circuit
The clock of the DSP is generated with a programmable PLL.
To select the required DSP clock see Table 6. The N factor (ranging from 93 to 181) can be selected with I2C-bus bits
PLL_div(14 to 11), see Table 10. Depending on the crystal and the required DSP clock the I2C-bus bits pll_fs_sel and
bits dsp_turbo must be set. The maximum limit of the audio sample frequency is determined by DSP_clock/481 Hz.
Table 6 I2C-bus bits PLL_div and dividing factors N of the programmable DSP clock
DSP CLOCK FREQUENCY (MHz)
PLL_DIV(14 to 11)
0000
N
TDA9875(1)
MSP3410D(2)
93 (default)
99
23.808(3)
25.344(3)
27.136
26.784
28.512
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
106
30.528
113
28.928
32.544
121
30.976
34.848(3)
36.288(3)
38.016(3)
39.456(3)
41.184(3)
42.624(3)
44.352(3)
45.792(3)
47.520(3)
48.960(3)
50.688(3)
52.128(3)
126
32.256
132
33.792(3)
35.072(3)
36.608(3)
37.888(3)
39.424(3)
40.704(3)
42.240(3)
43.520(3)
45.056(3)
46.336(3)
137
143
148
154
159
165
170
176
181
Notes
1. fxtal = 16.384 MHz; pll_fs_sel = 1 and dsp_turbo = 1, see Table 11.
2. fxtal = 18.432 MHz; pll_fs_sel = 1 and dsp_turbo = 1, see Table 11.
3. Usable frequency.
1999 Aug 05
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Philips Semiconductors
Preliminary specification
Sound effects DSP
SAA7712H
8.6
I2C-bus control
8.6.2
CHARACTERISTICS OF THE I2C-BUS
8.6.1
INTRODUCTION
The I2C-bus is for 2-way, 2-line communication between
different ICs or modules. The two lines are a serial data
line (SDA) and a serial clock line (SCL). Both lines must
be connected to VDD via a pull-up resistor when
connected to the output stages of a microcontroller. For a
400 kHz I2C-bus the recommendation from Philips
Semiconductors must be followed (e.g. up to loads of
200 pF on the bus a pull-up resistor can be used, between
200 to 400 pF a current source or switched resistor must
be used). Data transfer can only be initiated when the bus
is not busy.
A general description of the I2C-bus format can be
obtained from Philips Semiconductors, International
Marketing and Sales Communications (IMSC).
For the external control of the SAA7712H a fast I2C-bus
is implemented. This is a 400 kHz bus which is downward
compatible with the standard 100 kHz bus.
There are different types of control instructions:
• Instructions to control the DSP program, program the
coefficient RAM and read the values of parameters
8.6.3
BIT TRANSFER
• Instructions to control the equalizer, program the
equalizer coefficient RAM to be able to change the
centre frequency, gain and Q-factor of the equalizer
sections
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH period of the clock pulse as changes in the data line
at this time will be interpreted as control signals
• Instructions to control the source selection and
programmable parts, e.g. PLL clock speed.
(see Fig.11). The maximum clock frequency is 400 kHz.
To be able to run on this high frequency all the inputs and
outputs connected to this bus must be designed for this
high speed I2C-bus according to the Philips specification.
The detailed description of the I2C-bus and commands is
given in the following sections. The description of the
different bits in the memory map is given in Section 9.6.
The equalizer cannot be used and cannot be
programmed if there is no word select and bit clock signal
present on a selected digital source input; see
audio_source bit in Table 3 (I2S_IN1 and I2S_IN2).
The minimum limit of the audio sample frequency is
determined by 1⁄18fSCL
.
SDA
SCL
MGS216
data line
stable;
change
of data
data valid
allowed
Fig.11 Bit transfer on the I2C-bus.
1999 Aug 05
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Philips Semiconductors
Preliminary specification
Sound effects DSP
SAA7712H
8.6.4
START AND STOP CONDITIONS
Both data and clock lines will remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while
the clock is HIGH, is defined as a START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH
is defined as a STOP condition (P) (see Fig.12).
SDA
SCL
S
P
START condition
STOP condition
MGS217
Fig.12 START and STOP conditions.
8.6.5
DATA TRANSFER
A device generating a message is a ‘transmitter’ and a device receiving a message is the ‘receiver’. The device that
controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’.
SDA
MSB
acknowledgement
signal from receiver
acknowledgement
signal from receiver
byte complete
interrupt within receiver
clock line held LOW while
interrupts are serviced
SCL
1
2
7
8
9
1
2
3 to 8
9
ACK
ACK
S
MGS218
START condition
Fig.13 Data transfer on the I2C-bus.
1999 Aug 05
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Philips Semiconductors
Preliminary specification
Sound effects DSP
SAA7712H
8.6.6
ACKNOWLEDGE
Set-up and hold times must be taken into account.
The number of data bits transferred between the START
and STOP conditions from the transmitter to the receiver
is not limited. Each byte of eight bits is followed by one
acknowledge bit (see Fig.13). The acknowledge bit is a
HIGH-level left on the bus by the transmitter whereas the
master generates an extra acknowledge related clock
pulse.
A master receiver must signal an end of data to the
transmitter by not generating an acknowledge on the last
byte that has been clocked out of the slave. In this event
the transmitter must leave the data line HIGH to enable the
master to generate a STOP condition (see Fig.14).
8.6.7
STATE OF THE I2C-BUS INTERFACE DURING AND
AFTER POWER-ON RESET
A slave receiver which is addressed must generate an
acknowledge after the reception of each byte. Also a
master must generate an acknowledge after the reception
of each byte that has been clocked out of the slave
transmitter. The device that acknowledges has to pull
down the SDA line (left HIGH by the transmitter) during the
acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related
clock pulse.
During reset (see Section 8.8), the internal SDA line is kept
HIGH and pin SDA is therefore high-impedance. The SDA
line remains HIGH until a master pulls it down to initiate
communication.
data output
by transmitter
not acknowledge
data output
by receiver
acknowledge
SCL from
master
1
2
7
8
9
S
MGS219
clock pulse for
acknowledgement
START condition
Fig.14 Acknowledge on the I2C-bus.
1999 Aug 05
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Philips Semiconductors
Preliminary specification
Sound effects DSP
SAA7712H
8.7
External control pins
A more or less fixed relationship between the
DSP_RESET time constant and the POM time constant is
obligatory. The voltage on pin POM determines the current
flowing in the DACs. For 0 V on pin POM, the DAC
currents are zero and so also the DACs output voltages.
When a 3 V supply voltage (VDDA2) is supplied to pin POM,
the DAC currents are at their nominal (maximum) value.
For external control two input pins are implemented.
The status of these pins can be changed by applying a
logic level. The status of these pins is recorded in the
internal status register. The function of each input pin is
determined by the DSP software.
Pin DSP_IN1:
Long before the DAC outputs get their nominal output
voltages, the DSP must be in normal operating mode to
reset the output register. Therefore, the time constant of
DSP_RESET must be shorter than the time constant of
POM. For advised capacitors see the application diagram.
•
Logic 0 or left open-circuit means volume coefficients
updates are possible (default)
•
Logic 1 means no updates of volume coefficients are
possible.
The reset has the following function:
Pin DSP_IN2:
• All I2C-bus registers are reset to their default values
• If the 3-band spectrum analyser is used:
• The DSP algorithm is re-started
–
–
Logic 1 will reset the band registers of the analyser
• The external control output pins are reset
(see Section 8.7)
Logic 0 or left open-circuit means no reset of the
band registers will be done (default).
• Pin SDA is high-impedance.
• If the 3-band spectrum analyser is not used:
– The state of pin DSP_IN2 can be read via an I2C-bus
command.
When the level on the reset pin is HIGH, the DSP algorithm
starts to run.
To control external devices two output pins are
implemented. The status of these pins is controlled by the
DSP program. The functions of these pins are determined
by the DSP software.
In addition to the reset pin, there is also a software reset;
bit PC_reset (bit 15, 0FFDH, see Table 11). This reset has
the following function:
• The DSP algorithm is re-started
Pin DSP_OUT1:
• The external control output pins are reset
• To drive pin DSP_OUT1 via an I2C-bus command.
(see Section 8.7).
Pin DSP_OUT2:
• To drive pin DSP_OUT2 via an I2C-bus command.
8.8
Reset pin
The reset signal on pin DSP_RESET is active LOW and
has an internal pull-up resistor. Between this pin and
ground a capacitor should be connected to allow a proper
switch-on of the supply voltage. The capacitor value is
such that the chip is in the reset state as long as the power
supply is not stabilized.
1999 Aug 05
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Philips Semiconductors
Preliminary specification
Sound effects DSP
SAA7712H
8.9
Power supply connection and EMC
9.3
Write cycles
The digital part of the chip has in total 5 positive supply line
connections and 8 ground connections. To minimise
radiation the chip should be put on a double layer PCB with
a large ground plane on one side. The ground supply lines
should have a short connection to this ground plane. A coil
and capacitor network in the positive supply line can be
used as high frequency filter.
The I2C-bus configuration for a write cycle is shown in
Fig.15. The write cycle is used to write the bytes to control
the PLL for the DSP clock generation, the format of the
I2S-bus and some other settings. More details can be
found in the I2C-bus memory map (see Table 8).
The data length is 2 or 3 bytes, depending on the
accessed memory. The slave receiver detects the address
and adjusts the number of bytes accordingly. For XRAM,
the data word length is 18 bits and 3 bytes are sent over
the I2C-bus. The upper 6 bits (i.e. bit 7 to bit 2) of the first
byte DATA H are don’t care. For YRAM, the data word
length is 12 bits and 2 bytes are sent over the I2C-bus. The
left nibble (i.e. bit 7 to bit 4) of the first byte DATA H is don’t
care.
8.10 Test mode connections
Pins TSCAN, RTCB and SHTCB are used to put the chip
in test mode and to test the internal connections. Each pin
has an internal pull-down resistor to ground. In the
application these pins can be left open-circuit or connected
to ground.
9.4
Read cycles
9
I2C-BUS FORMAT
Addressing
The I2C-bus configuration for a read cycle is shown in
Fig.16. The read cycle is used to read the data values from
XRAM or YRAM. The master starts with a START
condition (S), the SAA7712H address ‘0011110’ and a
logic 0 (write) for the read/write bit. This is followed by an
acknowledge of the SAA7712H. The master then writes
the memory high address and memory low address where
the reading of the memory content of the SAA7712H must
start. The SAA7712H acknowledges these addresses
both.
9.1
Before any data is transmitted on the I2C-bus, the device
which should respond is addressed first. The addressing is
always done with the first byte transmitted after the START
procedure.
9.2
Slave address (pin A0)
The SAA7712H acts as a slave receiver or a slave
transmitter. Therefore, the clock signal SCL is only an
input signal. The data signal SDA is a bidirectional line.
The slave address is shown in Table 7.
The master than generates a repeated START and again
the SAA7712H address ‘0011110’ but this time followed
by a logic 1 (read) of the read/write bit. From this moment
on, the SAA7712H will send the memory content in groups
of 2 (YRAM) or 3 (XRAM) bytes to the I2C-bus, each time
acknowledged by the master. The master stops this cycle
by generating a negative acknowledge, then the
SAA7712H frees the I2C-bus and the master can generate
a STOP condition (P).
Table 7 Slave address
MSB
LSB
R/W
0
0
1
1
1
1
A0
The subaddress bit A0 corresponds to the hardware
address pin A0 which allows the device to have two
addresses. This allows the control of two SAA7712Hs via
the same I2C-bus.
1999 Aug 05
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A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
0
0
1
1
1
0
0
0
ADDR H
ADDR L
DATA H
DATA M
P
DATA L
S
auto increment if repeated n-groups of 3 (2) bytes
address
MGD568
R/W
S = START condition.
ACK = acknowledge from DSP (SDA LOW).
ADDR H and ADDR L = address DSP register.
DATA H, DATA M and DATA L = data of XRAM or registers.
DATA H and DATA M = data of YRAM.
P = STOP condition.
Fig.15 Master transmitter writes to the DSP registers.
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
0
0
1
1
1
0
0
0
ADDR H
ADDR L
0
S
0
1
1
1
0
0
1
DATA H
P
DATA M
DATA L
S
auto increment if repeated n-groups of 3 (2) bytes
address
MGA808 - 1
R/W
R/W
S = START condition.
ACK = acknowledge from DSP (SDA LOW).
ADDR H and ADDR L = address DSP register.
DATA H, DATA M and DATA L = data of XRAM or registers.
DATA H and DATA M = data of YRAM.
P = STOP condition.
Fig.16 Master transmitter reads from the DSP registers.
Philips Semiconductors
Preliminary specification
Sound effects DSP
SAA7712H
9.5
I2C-bus memory map summary
The I2C-bus memory map contains all defined I2C-bus bits. The map is split into two different sections: hardware memory
registers and the RAM definitions. The preliminary memory map is given in Table 8.
Table 8 I2C-bus memory map
SUBADDRESSES
FUNCTION
various settings (see Table 9)
SIZE
0FF9H to 0FFFH
0F80H to 0FA7H
0800H to 097FH
0000H to 017FH
4 × 16 bits
equalizer
YRAM
40 × 16 bits
384 × 12 bits
384 × 18 bits
XRAM
Table 9 I2C-bus memory map: overview of various settings
REGISTER NAME
SUBADDRESS
0FFFH (see Table 10)
0FFDH (see Table 11)
0FFAH (see Table 12)
0FF9H (see Table 13)
I2C_DCS_CTR
I2C_ADDA
I2C_SEL
I2C_HOST
9.6
I2C-bus memory map details
Table 10 I2C_DCS_CTR register (0FFFH)
SIZE
NAME
DESCRIPTION
DEFAULT
BIT POSITION
(BITS)
−
10
1
reserved
pin SYS_CLK output enable: on (logic 1) or off (logic 0) off
9 to 0
10
loopo_on_off
PLL_div
−
4
PLL clock division factor for DSP_clock (see Table 6)
reserved
93
14 to 11
15
1
1999 Aug 05
27
Philips Semiconductors
Preliminary specification
Sound effects DSP
SAA7712H
Table 11 I2C_ADDA register (0FFDH)
SIZE
NAME
BIT
POSITION
DESCRIPTION
DEFAULT
(BITS)
−
10
1
reserved
9 to 0
10
pll_fs_sel
dsp_turbo
two_four
divide oscillator by 2 (logic 1)
double DSP_clock (logic 1)
division
1
doubling
11
1
2-channel 10-band (logic 1) or 4-channel 5-band (logic 0) 4-channel
12
equalizer configuration
5-band
−
2
1
reserved
14 and 13
15
pc_reset
re-start DSP algorithm (logic 1) or DSP running (logic 0)
DSP running
Table 12 I2C_SEL register (0FFAH)
SIZE
NAME
BIT
POSITION
DESCRIPTION
DEFAULT
(BITS)
−
8
1
reserved
7 to 0
8
bypass_pll
bypass PLL used for DSP_clock (logic 1) or use PLL for
DSP_clock (logic 0)
use PLL
−
4
1
2
reserved
12 to 9
13
inv_host_ws
inverting (logic 1) or non-inverting (logic 0) word select
reserved
non-inverting
−
15 and 14
Table 13 I2C_HOST register (0FF9H)
SIZE
NAME
BIT
POSITION
DESCRIPTION
DEFAULT
(BITS)
−
5
1
1
3
2
1
3
reserved
4 to 0
audio_source
−
input source is I2S_IN1 or I2S_IN2 (see Table 3)
I2S_IN1
5
6
reserved
audio_format
host_io_format
en_host_io
cloop_mode
format of selected input source (see Table 2)
host input/output data format (see Table 4)
enable (logic 1) or disable (logic 0) co-processor I2S-bus disable
standard I2S-bus 9 to 7
standard I2S-bus 11 and 10
12
cloop mode (see Table 5) bypass WS
15 to 13
1999 Aug 05
28
Philips Semiconductors
Preliminary specification
Sound effects DSP
SAA7712H
10 LIMITING VALUES
In accordance with the Absolute Maximum Ratings system (IEC 134).
SYMBOL
VDD3V
PARAMETER
CONDITION
MIN.
−0.5
MAX.
+5
UNIT
supply voltage 3.3 V analog and
digital
V
V
VDD5V
supply voltage 5 V periphery
only valid for the voltages in
connection with the 5 V I/Os
−0.5
+6.5
550
∆VDD
voltage difference between two
VDDx pins
−
mV
IIK
input clamping diode current
Vi < −0.5 V or Vi > VDD + 0.5 V
−0.5 V < Vo < VDD + 0.5 V
−
−
10
20
mA
mA
IO(sink/source)
output sink or source current,
output type 4 mA
IDD,ISS
VDD or VSS current per supply
pin
−
750
mA
Tamb
Tstg
Ves
ambient temperature
storage temperature
0
70
°C
°C
V
−65
−3000
−300
100
−
+150
+3000
+300
−
electrostatic handling voltage for note 1
all pins
note 2
V
Ilu(prot)
P/out
Ptot
latch-up protection
CIC specification/test method
mA
mW
mW
power dissipation per output
total power dissipation
100
400
−
Notes
1. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ resistor.
2. Machine model: equivalent to discharging a 200 pF capacitor through a 2.5 µH inductance and a 0 Ω series resistor.
11 THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
Note
1. Printed-circuit board mounting.
PARAMETER
CONDITION
VALUE
UNIT
thermal resistance from junction to ambient
in free air; note 1
45
K/W
1999 Aug 05
29
Philips Semiconductors
Preliminary specification
Sound effects DSP
SAA7712H
12 DC CHARACTERISTICS
Digital I/O at Tamb = 0 to 70 °C; VDD5V = 4.5 to 5.5 V; VDD3V = 3 to 3.6 V; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDD3V
supply voltage 3.3 V analog
and digital
all VDD pins of the type VDD3
and APVVD referenced to VSS
3
3.3
3.6
V
VDD5V
supply voltage 5 V periphery all VDD pins of the type VDD5 4.5
5
5.5
3.6
80
V
referenced to VSS
3.0
3.3
33
V
IDDD3V
IDDD5V
supply current of the 3.3 V
digital core part
at fDSP18; maximum activity of
the DSP
−
−
mA
supply current of the 5 V
digital periphery part
at fDSP18; maximum activity of
the DSP
2
5
mA
IDAC
supply current of the DACs
at zero input and output signal
at fDSP18; functional mode
−
−
4
7
3
mA
mA
IDD_OSC
supply current of the crystal
oscillator
3.5
Ptot
total power dissipation
at fDSP18; maximum activity of
the DSP
−
135
400
mW
Logic
VIH
HIGH-level input voltage of all
digital inputs and I/Os on
pins 24 to 29, 38, 39,
44 to 47, 57 to 60
0.7VDDD5V
−
−
V
VIL
LOW-level input voltage of all
digital inputs and I/Os on
pins 24 to 29, 38, 39,
44 to 47, 57 to 60
−
−
0.3VDDD5V
V
Vhys
VOH
hysteresis voltage on pin 45
(SCL)
1
1.3
−
−
V
V
HIGH-level output voltage of IO = −4 mA
digital outputs on pins 20, 21,
V
DDD5V − 0.4 −
30, 33, 36, 37, 40, 41, 47, 48
VOL
LOW-level output voltage of
digital outputs on pins 20, 21,
30, 33, 36, 37, 40, 41, 47, 48
VDDD5V = 4.5 V; IO = 4 mA
−
−
−
−
0.4
0.4
V
V
VDDD5V = 3.0 V; IO = 4 mA
VOL(I2C)
LOW-level output voltage of
digital I2C-bus data output on
pin 46 (SDA)
IO = 4 mA
−
−
0.4
V
IO
output leakage current
3-state outputs on pins 21,
30, 33, 36, 37, 46 to 48
VO = 0 or VDD
−
−
5
µA
kΩ
Rpu
internal pull-up resistance to
VDDD on pin 57
23
50
80
(DSP_RESET)
1999 Aug 05
30
Philips Semiconductors
Preliminary specification
Sound effects DSP
SAA7712H
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
50
MAX.
UNIT
Rpd
internal pull-down resistance
to VSSD on pins 24 to 29, 38,
39, 44, 58 to 60
23
80
kΩ
ti(r), ti(f)
input rise and fall times
VDDD5V = 5.5 V
−
−
5
6
6
−
200
200
−
ns
ns
ns
VDDD5V = 3.6 V
VDDD5V = 5.5 V;
tLH5
output rise time on pins 20,
21, 30, 33, 36, 37, 40, 41, 47, VDDD3V = 3.6 V; Tj = −40 °C;
48
CL = 60 pF
VDDD5V = 4.5 V; VDDD3V = 3 V;
Tj = 125 °C; CL = 60 pF
−
−
−
25
ns
ns
tLH3
output rise time on pins 20,
VDDD5V = 3.6 V;
7.5
−
21, 30, 33, 36, 37, 40, 41, 47, VDDD3V = 3.6 V; Tj = −40 °C;
48
CL = 60 pF
V
DDD5V = 3.0 V; VDDD3V = 3 V;
−
−
−
5
−
−
−
−
30
−
ns
ns
ns
ns
Tj = 125 °C; CL = 60 pF
tLH(I2C5)
tLH(I2C3)
tHL5
output rise time on pin 46
(SDA)
CL and Rpu are application
specific
output rise time on pin 46
(SDA)
CL and Rpu are application
specific
−
output fall time on pins 20,
21, 30, 33, 36, 37, 40, 41, 47,
48
VDDD5V = 5.5 V;
−
V
DDD3V = 3.6 V; Tj = −40 °C;
CL = 60 pF
DDD5V = 4.5 V; VDDD3V = 3 V;
V
−
−
−
25
ns
ns
Tj = 125 °C; CL = 60 pF
tHL3
output fall time on pins 20,
VDDD5V = 3.6 V;
7.5
−
21, 30, 33, 36, 37, 40, 41, 47, VDDD3V = 3.6 V; Tj = −40 °C;
48
CL = 60 pF
V
DDD5V = 3.0 V; VDDD3V = 3 V;
−
−
−
30
ns
ns
Tj = 125 °C; CL = 60 pF
tHL(I2C5)
output fall time on pin 46
(SDA)
VDDD5V = 5.5 V;
30
−
VDDD3V = 3.6 V; Tj = −40 °C;
CL = 200 pF
V
DDD5V = 4.5 V; VDDD3V = 3 V;
−
−
−
300
ns
ns
Tj = 125 °C; CL = 200 pF
tHL(I2C3)
output fall time on pin 46
(SDA)
VDDD5V = 3.6 V;
40
−
VDDD3V = 3.6 V; Tj = −40 °C;
CL = 200 pF
VDDD5V = 3.0 V; VDDD3V = 3 V;
−
−
400
ns
Tj = 125 °C; CL = 200 pF
1999 Aug 05
31
Philips Semiconductors
Preliminary specification
Sound effects DSP
SAA7712H
13 ANALOG OUTPUTS CHARACTERISTICS
Tamb = 25 °C; VDDA2 = 3.3 V; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
47
TYP. MAX. UNIT
VVREFDA
ZVREFDA
voltage on pin VREFDA
with respect to VDDA2 − VSSA2
with respect to VDDA2
50
37
37
0.7
53
−
%
impedance on pin VREFDA
−
kΩ
kΩ
V
with respect to VSSA2
maximum I2S-bus signal;
RL > 5 kΩ
−
−
Vo(rms)
AC output voltage of operational
amplifiers (RMS value)
0.62
0.82
VO(AV)
average DC output voltage of
operational amplifiers
RL > 5 kΩ
1.5
3.3
50
1.65
−
1.8
5
V
Ipu(POML)
Ipu(POMH)
PSRRDAC
∆Io(max)
low pull-up current to VDDA2 on
pin POM
voltage on pin POM < 0.6 V
voltage on pin POM > 0.8 V
µA
µA
dB
dB
high pull-up current to VDDA2 on
pin POM
−
75
−
power supply ripple rejection DACs fripple = 1 kHz; Vripple = 100 mV 45
(input via I2S-bus)
(peak value); CVREFDA = 22 µF
maximum deviation in output level with respect to the average of
60
−
−
0.38
(plus or minus) of the 4 DAC
current outputs
the 4 outputs; full-scale output
αct
crosstalk between all outputs in
the audio band
one output digital silence, other
three maximum volume
−
−
−
−69
dB
Io(sc)
output short-circuit current
DAC resolution
output short-circuited to ground
−
20
mA
bits
dBA
RESDAC
18
−75
(THD + N)/S total harmonic
distortion-plus-noise to signal ratio
f = 1 kHz;
−
−60
Vo(ref) = 0.72 V (RMS);
A-weighted
DRDAC
DSDAC
dynamic range of DAC
digital silence of DAC
Vo(ref) = 0.72 V (RMS);
f = 1 kHz; −60 dB; A-weighted
90
96
−
dBA
f = 20 Hz − 17 kHz;
Vo(ref) = 0.72 V (RMS);
A-weighted
−
−107 −102 dBA
Vn(o)(rms)
d
digital silence noise level at output A-weighted
(RMS value)
−
−
3
8
µV
intermodulation
f = 60 Hz and 7 kHz, ratio 4 : 1
−70
−55
dB
distortion/comparator
fs(max)
BDAC
CL(DAC)
RL(DAC)
maximum sample frequency
bandwidth DAC
48
−
−
1⁄2fs
−
kHz
kHz
nF
at −3 dB
−
load capacitance on DAC outputs
−
−
2.5
−
load resistance on DAC voltage
outputs
DC decoupled
5
−
kΩ
1999 Aug 05
32
Philips Semiconductors
Preliminary specification
Sound effects DSP
SAA7712H
14 OSCILLATOR CHARACTERISTICS
SYMBOL
fxtal
∆fxtal(adj)
PARAMETER
crystal frequency
CONDITIONS
MIN.
TYP.
MAX.
UNIT
10.000
−
−
19.456 MHz
crystal frequency variation with
adjustment
Tamb = 25 °C
−30
+30
+30
ppm
ppm
∆fxtal(T)
crystal frequency variation with
temperature
−30
−
αf
spurious frequency attenuation
20
−
−
dB
V
Vxtal(M)
voltage across the crystal
(absolute peak value)
1.6
2.6
3.6
gm(start)
gm(oper)
CL
transconductance at start-up
transconductance when operating
capacitive load of clock output
number of cycles during start-up
10.5
3.6
−
19
32
38
−
mS
−
mS
15
pF
Ncy(start)
depends on quality of the
external crystal
−
1000
−
cycles
Ixtal
supply current
at start-up
−
−
−
−
3
−
7
15
mA
mA
mA
mW
V
at oscillation
in slave mode
at oscillation
in slave mode
Cp = 5 pF(1); C1 = 10 pF;
C2 = 10 pF; see Fig.9
0.6
0.65
0.4
3.3
20
2
0.9
0.5
3.6
100
Pxtal
Vi(clk)
Rxtal
drive level
external clock input voltage
allowed loss resistance of the
crystal
Ω
Ro
output resistance
at start-up;
750
1300
2800
Ω
fxtal = 18.432 MHz;
VDD_OSC = 3.3 V
Note
1. Cp is the parasitic parallel capacitance of the crystal.
1999 Aug 05
33
Philips Semiconductors
Preliminary specification
Sound effects DSP
SAA7712H
15 I2S-BUS TIMING CHARACTERISTICS
Timing of the serial digital data inputs and outputs (see Fig.17).
SYMBOL
Tcy
tsu(D)
PARAMETER
MIN.
MAX.
UNIT
ns
bit clock cycle time
70
32
10
5
−
−
−
−
−
−
−
data set-up time (host)
data set-up time (I2S-bus)
data hold time (host)
data hold time (I2S-bus)
ns
ns
ns
ns
ns
ns
ns
ns
th(D)
10
10
10
−
tsu(WS)
th(WS)
td(D)
word select set-up time (I2S-bus)
word select hold time (I2S-bus)
data delay time (host)
20
15
td(WS)
word select delay time (host)
−
WS OUT
left
WS IN
right
t
t
d(WS)
t
h(WS)
su(WS)
t
t
BCK(L)
BCK(H)
t
t
t
f
d(D)
r
BCK
t
h(D)
t
T
su(D)
cy
DATA IN
LSB
MSB
DATA OUT
MGS220
Fig.17 Timing definitions of the serial digital inputs and outputs.
1999 Aug 05
34
Philips Semiconductors
Preliminary specification
Sound effects DSP
SAA7712H
16 I2C-BUS TIMING CHARACTERISTICS
Timing of the I2C-bus (see Fig.18); all values referred to VIH and VIL (see Section 12).
SYMBOL
fSCL
PARAMETER
SCL clock frequency
CONDITIONS
MIN.
MAX.
400
UNIT
kHz
0
tBUF
bus free time between a STOP and
START condition
1.3
−
µs
tHD;STA
hold time (repeated) START
condition; after this period, the first
clock pulse is generated
0.6
−
µs
tLOW
LOW period of the SCL clock
HIGH period of the SCL clock
1.3
0.6
0.6
−
−
−
µs
µs
µs
tHIGH
tSU;STA
set-up time for a repeated START
condition
tHD;DAT
tSU;DAT
data hold time
0
0.9
µs
data set-up time
for standard mode I2C-bus 100
system tSU;DAT > 250 ns
−
ns
(1)
(1)
(1)
tr
tf
rise time of both SDA and SCL
signals
fSCL = 400 kHz
SCL = 100 kHz
20 + 0.1Cb
20 + 0.1Cb
20 + 0.1Cb
300
ns
ns
ns
f
1000
300
fall time of both SDA and SCL
signals
tSU;STO
Cb
set-up time for STOP condition
capacitive load for each bus line
0.6
−
−
µs
pF
ns
400
50
tSP
maximum pulse width for spike
suppression
−
Note
1. Cb is the bus line capacitance in pF.
1999 Aug 05
35
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SDA
t
t
t
t
t
t
SP
r
BUF
LOW
HD;STA
f
SCL
t
t
SU;STO
HD;STA
t
t
t
t
SU;DAT
SU;STA
HD;DAT
HIGH
P
S
P
Sr
MBC611
Fig.18 Timing definition of the I2C-bus.
ahdnbok,uflapegwidt
Philips Semiconductors
Preliminary specification
Sound effects DSP
SAA7712H
17 APPLICATION INFORMATION
The application diagram (see Fig.19) must be considered as one of the examples of a (limited) application of the chip
e.g. in this case the I2S-bus inputs are not used. For the real application set-up the information of the application report
and application support by Philips are necessary on issues such as EMC, kappa reduction of the package,
DSP programming, etc.
+3 V
+5 V +5 V
BLM32A07
+3 V
22
nF
22
nF
22
nF
27 29 28 24 26 25
37 36 30
31
32 33
14 53 52 34 42
22
V
DDD5V1
+5 V
HOST I/O
22 nF
100 Ω
19 OUT0_V
18 OUT0_I
16 OUT1_V
17 OUT1_I
OUT0
OUT1
1.8 nF
1.8 nF
100 Ω
2
I S-BUS
INPUT
10 nF
10 nF
SWITCH
100 Ω
12 OUT2_V
11 OUT2_I
DSP
QUAD DAC
OUT2
1.8 nF
100 Ω
9
OUT3_V
OUT3
SYS_CLK 21
10 OUT3_I
10 nF
10 nF
1.8 nF
8
POM
15 VREFDA
2
BLM32A07
100 nF
V
DD_OSC 64
22 µF
4.7 µF
+3 V
PLL
OSCILLATOR
V
SS_OSC 61
38 DSP_IN1
39 DSP_IN2
40 DSP_OUT1
41 DSP_OUT2
20 EQOV
2
I C-BUS
EQUALIZER
RTCB 58
SHTCB 59
TSCAN 60
INTERFACE
SAA7712H
62
63
47 48 55 54 51 50 49 43
57
56 35 23 13
46 45 44
4.7 kΩ
4.7 kΩ
11.2896 MHz
10 pF
1 µF
10 pF
MGS222
+5 V
Fig.19 Application diagram.
37
1999 Aug 05
Philips Semiconductors
Preliminary specification
Sound effects DSP
SAA7712H
18 PACKAGE OUTLINE
QFP80: plastic quad flat package;
80 leads (lead length 1.95 mm); body 14 x 20 x 2.7 mm; high stand-off height
SOT318-1
y
X
A
64
65
41
40
Z
E
e
A
2
H
A
E
(A )
3
E
A
1
w M
p
θ
pin 1 index
L
p
b
L
25
80
detail X
1
24
w M
Z
D
v
M
A
b
p
e
D
B
H
v
M
B
D
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
θ
1
2
3
p
E
p
D
E
max.
7o
0o
0.36 2.87
0.10 2.57
0.45 0.25 20.1 14.1
0.30 0.13 19.9 13.9
24.2 18.2
23.6 17.6
1.0
0.6
1.0
0.6
1.2
0.8
mm
3.3
0.25
0.8
1.95
0.2
0.2
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-02-04
97-08-01
SOT318-1
1999 Aug 05
38
Philips Semiconductors
Preliminary specification
Sound effects DSP
SAA7712H
19 SOLDERING
If wave soldering is used the following conditions must be
observed for optimal results:
19.1 Introduction to soldering surface mount
packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
19.2 Reflow soldering
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
19.4 Manual soldering
19.3 Wave soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
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SAA7712H
19.5 Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
WAVE
REFLOW(1)
BGA, SQFP
not suitable
suitable
suitable
suitable
suitable
suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable(2)
PLCC(3), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
not recommended(3)(4)
not recommended(5)
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
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Preliminary specification
Sound effects DSP
SAA7712H
20 DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
21 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
22 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1999 Aug 05
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Philips Semiconductors
Preliminary specification
Sound effects DSP
SAA7712H
NOTES
1999 Aug 05
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Philips Semiconductors
Preliminary specification
Sound effects DSP
SAA7712H
NOTES
1999 Aug 05
43
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© Philips Electronics N.V. 1999
SCA67
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
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Printed in The Netherlands
545004/25/01/pp44
Date of release: 1999 Aug 05
Document order number: 9397 750 04868
相关型号：
SAA7715AH
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NXP
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