SAA7824_技术文档

INTEGRATED CIRCUITS

DATA SHEET

SAA7824

CD audio decoder, digital servo and

filterless DAC with integrated

pre-amp and laser control (PhonIC)

Product speciﬁcationSupersedes data of 2003 Aug 07

2003 Oct 01

Philips Semiconductors

Product speciﬁcation

CD audio decoder, digital servo and ﬁlterless DAC

with integrated pre-amp and laser control (PhonIC)

SAA7824

CONTENTS

7.15.3

7.15.4

7.16

Loop characteristics

FIFO overflow

Servo part

1

2

3

4

5

6

7

FEATURES

7.16.1

7.16.2

7.16.3

7.16.4

7.16.5

7.16.6

7.16.7

7.16.8

7.16.9

7.16.10

7.16.11

7.17

Diode signal processing

Signal conditioning

Focus servo system

Radial servo system

Off-track counting

Track counting modes

Defect detection

Off-track detection

High-level features

Driver interface

GENERAL DESCRIPTION

ORDERING INFORMATION

QUICK REFERENCE DATA

BLOCK DIAGRAM

PINNING

FUNCTIONAL DESCRIPTION

7.1

7.2

Data acquisition and HF data path

Decoder part

7.2.1

7.2.2

7.2.3

7.2.4

7.3

Principle operating modes of the decoder

Decoder speed and crystal frequency

Lock-to-disc mode

Standby modes

Crystal oscillator

Laser interface

Microcontroller interface

7.17.1

7.17.2

7.17.3

7.17.4

Microcontroller interface (4-wire bus mode)

Microcontroller interface (I²C-bus mode)

Decoder and shadow registers

Summary of functions controlled by decoder

registers 0 to F

Summary of functions controlled by shadow

registers

Summary of servo commands

Summary of servo command parameters

7.4

7.5

7.5.1

7.5.2

7.6

Data slicer and bit clock regenerator

DC offset cancellation

Offset cancellation

Reading back the DC offset value

Demodulator

7.17.5

7.17.6

7.17.7

7.6.1

7.6.2

7.7

7.7.1

7.7.2

Frame sync protection

EFM demodulation

Subcode data processing

Q-channel processing

EIAJ 3 and 4-wire subcode (CD graphics)

interface

8

SUMMARY OF SERVO COMMAND

PARAMETERS VALUES

9

LIMITING VALUES

10

11

CHARACTERISTICS

7.7.3

7.7.4

7.8

7.8.1

7.9

V4 subcode interface

CD text interface

FIFO and error correction

Flags output (CFLG)

Audio functions

OPERATING CHARACTERISTICS

(SUBCODE INTERFACE TIMING)

OPERATING CHARACTERISTICS (I²S-BUS

TIMING)

12

13

OPERATING CHARACTERISTICS

(MICROCONTROLLER INTERFACE TIMING)

7.9.1

7.9.2

7.9.3

7.9.4

7.9.5

7.10

7.10.1

De-emphasis and phase linearity

Digital oversampling filter

Concealment

Mute, full-scale, attenuation and fade

Peak detector

14

APPLICATION INFORMATION

PACKAGE OUTLINE

SOLDERING

15

16

Audio DAC interface

Internal dynamic element matching

digital-to-analog converter

External DAC interface

EBU interface

16.1

Introduction to soldering surface mount

packages

Reflow soldering

Wave soldering

Manual soldering

7.10.2

7.11

16.2

16.3

16.4

16.5

7.11.1

7.12

Format

KILL features

Suitability of surface mount IC packages for

wave and reflow soldering methods

7.12.1

7.12.2

7.13

The KILL circuit

Silence injection

Audio features off

17

18

19

20

DATA SHEET STATUS

DEFINITIONS

7.14

7.15

7.15.1

7.15.2

The versatile pins interface

Spindle motor control

Motor output modes

DISCLAIMERS

PURCHASE OF PHILIPS I²C COMPONENTS

Spindle motor operating modes

2003 Oct 01

2

Philips Semiconductors

Product speciﬁcation

CD audio decoder, digital servo and ﬁlterless

DAC with integrated pre-amp and laser control

SAA7824

1

FEATURES

• Decoder and servo parts are based upon the SAA732X

design (the original features are maintained)

• Software compatibility is maintained with the SAA732X

by using a similar register structure (new features are

controlled from new shadow registers)

• 1×, 2× and 4× speed

• Dedicated 4 MHz or 12 MHz clock output for

• LF (servo) signals converted to digital representations

microcontroller (configurable)

by 6 oversampling bitstream ADCs

• Configured for N-sub monitor diode

• HF part summed from signals D1 to D4 and converted

into a digital signal by a data slicer

• On-chip clock multiplier allows the use of an

8.4672 MHz crystal or ceramic resonator

• On-chip buffering and filtering of the diode signals from

the mechanism for signal optimization

• The M1 version has an EBU mute function which allows

independent muting of data being transmitted over the

EBU interface whilst maintaining the SPDIF frame

structure.

• Selectable DC offset cancellation of quiescent

mechanism voltages and dark currents

• On-chip laser power control (up to 120 mA)

• Laser on/off control, including ‘soft’ start control (zero to

nominal power in 1 ms)

2

GENERAL DESCRIPTION

• Monitor control and feedback circuit to maintain nominal

output power throughout laser life

This document covers versions M0 and M1 of the CD

audio decoder IC.

• Dynamic element matching DAC with minimum external

components

The SAA7824 is a CD audio decoder IC which combines

the function of the SAA732X IC with the pre-amplifier and

laser control functions previously found in the TZA102X

IC. The design is intended to reduce the external

• DAC performance of −80 dB Total Harmonic

Distortion + Noise (THD + N) and 90 dB Signal-to-Noise

Ratio (S/N) A-weighted

component count and hence the Bill Of Material (BOM).

• Separate left and right channel digital silence detection

available on the KILL pins

Supply of this Compact Disc IC does not convey an

implied license under any patent right to use this IC in any

Compact Disc application.

• Digital silence detection on internal data and loopback

(external) data

• 5 versatile pins, 2 inputs and 3 outputs

• Integrated CD text decoder with separate

microcontroller interface

2003 Oct 01

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Philips Semiconductors

Product speciﬁcation

CD audio decoder, digital servo and ﬁlterless

DAC with integrated pre-amp and laser control

SAA7824

3

ORDERING INFORMATION

TYPE

PACKAGE

NUMBER

NAME

DESCRIPTION

VERSION

SAA7824HL

LQFP80

plastic low proﬁle quad ﬂat package; 80 leads;

SOT315-1

body 12 × 12 × 1.4 mm

4

QUICK REFERENCE DATA

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

1.8

MAX.

1.95

UNIT

V_DDD

V_DDA

digital supply voltage

analog supply voltage

total supply current

1.65

3.0

−

V

3.3

38

3.6

−

I_DD(tot)

n = 1 mode

mA

MHz

°C

n = 2 mode

n = 4 mode

−

39

−

40

−

f_xtal

crystal frequency

−

8.4672

−

T_amb

T_stg

ambient temperature

0

70

+125

−

storage temperature

−55

−

°C

S/N_DAC

onboard DAC signal-to-noise ratio

90

dB

2003 Oct 01

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Philips Semiconductors

Product speciﬁcation

CD audio decoder, digital servo and ﬁlterless

DAC with integrated pre-amp and laser control

SAA7824

5

BLOCK DIAGRAM

V

handbook, full pagewidth

SSA2

V

SENSE

SSA1

SSA3

D1 D2 D3 D4 R1 R2

MONITOR

EXFILTER

2

LPOWER

1

9

10 11 12 13 14

5

17 20

3

4

DC OFFSET COMPENSATION

LASER POWER

CONTROL LOGIC

MONITOR

ADC

80

LASER

7

V

DDA1

16

V

DDA2

VOLTAGE

BUFFER

ANTI ALIAS

HF AND LF CAPTURE

64

6

8

RA

I

REF

BIAS

GENERATOR

D1 TO D4

SUM

DISC ADC

65

OUTPUT

STAGES

V

REFO

FO

66

SL

CONTROL

PART

HIGH-PASS FILTER

CONTROL FUNCTION

53

52

54

55

15

SCL

SDA

RAB

SILD

CSLICE

MICROCONTROLLER

INTERFACE

67

DATA SLICER AND

THRESHOLD

CONTROL

MOTO1

MOTOR

CONTROL

68

MOTO2

76

77

78

79

TEST1

TEST2

TEST3

TEST4

ERROR

CORRECTOR

DIGITAL

PLL

TEST

39

CFLAG

FLAGS

19

18

49

50

EFM

DEMODULATOR

OSCIN

OSCOUT

CLK16

AUDIO

PROCESSOR

TIMING

CLK4/12

SRAM

62

EBU

INTERFACE

DOBM

36

37

38

CDTRDY

CDTDATA

CDTCLK

CD TEXT

INTERFACE

45

48

RAM

ADDRESSER

EF

SCLK

SERIAL

DATA

47

WCLK

46

INTERFACE

59

58

57

SFSY

SUB

RCK

DATA

INTERFACE

CONTROL

44

SERIAL

DATA

(LOOPBACK)

INTERFACE

SCLI

43

WCLI

SUBCODE

PROCESSOR

60

42

SBSY

SDI

PEAK

DETECT

27

22

23

26

25

24

21

DACV

pos

DACRP

DACRN

DACLP

DACLN

DACV

SAA7824

DEM

DAC

ref

DECODER

MICRO-

DACGND

56

51

STATUS

RESET

CONTROLLER

INTERFACE

29

32

30

31

VERSATILE PINS

INTERFACE

BUFINR

BUFINL

BUFOUTR

BUFOUTL

KILL

HEADPHONE

BUFFERS

40 61 69 41 63 70

71 72 73 74 75

V1 V2 V3 V4 V5

34

35

33

28

MBL436

V

LKILL RKILL

BUFV

SSD1

V

SSD3

V

DDD2

V

DDD3

pos

BUFGND

SSD2

DDD1

Fig.1 Block diagram.

5

2003 Oct 01

Philips Semiconductors

Product speciﬁcation

CD audio decoder, digital servo and ﬁlterless

DAC with integrated pre-amp and laser control

SAA7824

6

PINNING

SYMBOL

I/O

DESCRIPTION

LFPOWER

EXFILTER

MONITOR

SENSE

V_SSA1

1

I

laser power supply

2

O

10 nF capacitor for laser start-up control

laser monitor diode

3

I

4

I

OPU ground reference point for MONITOR measurement

analog ground 1

5

SUP

I_REF

6

O

reference current output (24 kΩ resistor connected to analog ground)

analog supply voltage 1

V_DDA1

7

SUP

V_REFO

8

I/O

servo reference voltage

D1

9

I

diode voltage/current input (central diode signal input)

diode voltage/current input (satellite diode signal input)

10 nF capacitor for adaptive HF data slicer

analog supply voltage 2

D2

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

I

D3

I

D4

I

R1

I

R2

I

CSLICE

V_DDA2

I/O

SUP

V_SSA2

SUP

analog ground 2

OSCOUT

OSCIN

V_SSA3

O

crystal/resonator output

I

SUP

I

crystal/resonator input

analog ground 3

DACGND

DACRP

DACRN

DACV_ref

DACLN

DACLP

DACV_pos

BUFV_pos

BUFINR

BUFOUTR

BUFOUTL

BUFINL

BUFGND

LKILL

audio DAC ground

O

I/O

O

I

audio DAC right channel differential positive output

audio DAC right channel differential negative output

audio DAC decoupling point (10 µF or 100 nF to ground

audio DAC left channel differential negative output

audio DAC left channel differential positive output

audio DAC positive supply voltage

I

audio buffer positive supply voltage

audio buffer right input

I

O

I

audio buffer right output

audio buffer left output

audio buffer left input

I

audio buffer ground

O

I

KILL output for left channel (conﬁgurable as open-drain)

KILL output for right channel (conﬁgurable as open-drain)

CD text output to microcontroller ready ﬂag

CD text output data to microcontroller

CD text microcontroller clock input

correction ﬂag output (open-drain)

RKILL

CDTRDY

CDTDATA

CDTCLK

CFLAG

V_SSD1

O

SUP

digital ground 1

2003 Oct 01

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Philips Semiconductors

Product speciﬁcation

CD audio decoder, digital servo and ﬁlterless

DAC with integrated pre-amp and laser control

SAA7824

SYMBOL

I/O

DESCRIPTION

V_DDD1

SDI

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

SUP

digital supply voltage 1

I

serial data input (loopback)

word clock input (loopback)

WCLI

SCLI

I

serial bit clock input (loopback)

C2 error ﬂag output

EF

O

I

DATA

WCLK

SCLK

CLK16

CLK4/12

RESET

SDA

serial data output

word clock output

serial clock output

16 MHz clock output

conﬁgurable 4 MHz or 12 MHz clock output

power-on reset input (active LOW)

microcontroller interface data input/output (open-drain)

microcontroller interface clock input

I/O

I

SCL

RAB

I

microcontroller interface R/W and load control input (4-wire)

SILD

I

STATUS

O

servo interrupt request line/decoder status register/DC offset value

readback output

RCK

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

I

subcode clock input

P to W subcode output

subcode frame sync output

subcode block sync output

digital ground 2

SUB

O

SFSY

SBSY

V_SSD2

DOBM

V_DDD2

RA

O

SUP

O

bi-phase mark output (externally buffered)

digital supply voltage 2

radial actuator output

focus actuator output

sledge actuator output

motor output 1 output

motor output 2 output

digital ground 3

SUP

O

FO

O

SL

O

MOTO1

MOTO2

V_SSD3

V_DDD3

V1

O

SUP

digital supply voltage 3

versatile pin 1 input

versatile pin 2 input

versatile pin 3 output

versatile pin 4 output

versatile pin 5 output

test pin 1 input

I

V2

V3

O

I

V4

V5

TEST1

TEST2

TEST3

TEST4

LASER

I

test pin 2 input

I

test pin 3 input

I

test pin 4 input

O

laser drive output

2003 Oct 01

7

Philips Semiconductors

Product speciﬁcation

CD audio decoder, digital servo and ﬁlterless

DAC with integrated pre-amp and laser control

SAA7824

handbook, full pagewidth

LFPOWER

EXFILTER

MONITOR

SENSE

1

2

3

4

5

6

7

8

9

60 SBSY

59 SFSY

58 SUB

57 RCK

V

56 STATUS

55 SILD

54 RAB

SSA1

I

REF

V

DDA1

V

53 SCL

REFO

D1

52 SDA

D2 10

D3 11

51 RESET

50 CLK4/12

49 CLK16

48 SCLK

47 WCLK

46 DATA

45 EF

SAA7824HL

D4 12

R1 13

R2 14

CSLICE 15

V

16

17

DDA2

V

44 SCLI

43 WCLI

42 SDI

SSA2

OSCOUT 18

OSCIN 19

V

20

41 V

DDD1

SSA3

MBL437

Fig.2 Pin configuration.

2003 Oct 01

8

Philips Semiconductors

Product speciﬁcation

CD audio decoder, digital servo and ﬁlterless

DAC with integrated pre-amp and laser control

SAA7824

7

FUNCTIONAL DESCRIPTION

7.1

Data acquisition and HF data path

The SAA7824 removes the need for an external diode signal pre-amplifier.

A simplified diagram of the HF data path is illustrated in Fig.3. The high-pass filter, equalizing filter HF gain and adaptive

slicer are all register programmable, thus enabling the SAA7824 to be optimized for the intended application.

handbook, full pagewidth

hf_gain 5:0

adaptive slicer

67.7 MHz

summing amplifier

d1_hf

d2_hf

bypass

d3_hf

d4_hf

sliced

data

comp

op-amp

V

ref

THRESHOLD

CONTROL

op-amp

V

op-amp

ana

equalising

filter

high-pass filter

MBL438

Fig.3 Simplified block diagram of the HF data path and adaptive slicer.

7.2

Decoder part

7.2.3

LOCK-TO-DISC MODE

7.2.1

PRINCIPLE OPERATING MODES OF THE DECODER

For electronic shock absorption applications, the SAA7824

can be put into lock-to-disc mode. This allows Constant

Angular Velocity (CAV) disc playback with varying input

data rates from the inside-to-outside of the disc.

The decoding part supports a full audio specification and

can operate at single-speed (n = 1), double-speed (n = 2)

and quad-speed (n = 4). The factor ‘n’ is called the

overspeed factor. A simplified data flow through the

decoder part is illustrated in Fig.7 for the M0 version and

Fig.8 for the M1 version.

In the lock-to-disc mode, the FIFO is blocked and the

decoder will adjust its output data rate to the disc speed.

Hence, the frequency of the I²S-bus (WCLK and SCLK)

clocks are dependent on the disc speed. In the lock-to-disc

mode there is a limit on the maximum variation in disc

speed that the SAA7824 will follow. Disc speeds must

always be within 25% to 100% range of their nominal

value. The lock-to-disc mode is enabled or disabled by

decoder register E.

7.2.2

DECODER SPEED AND CRYSTAL FREQUENCY

The SAA7824 is a 1×, 2× and 4× (three-speed) decoding

device, with an internal Phase-Locked Loop (PLL) clock

multiplier. Table 1 gives the playback speeds that are

achievable in conjunction with crystal frequency,

mechanism, and internal clock settings (selectable via

decoder register B).

2003 Oct 01

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Philips Semiconductors

Product speciﬁcation

CD audio decoder, digital servo and ﬁlterless

DAC with integrated pre-amp and laser control

SAA7824

7.2.4

STANDBY MODES

Table 1 Playback speeds

The SAA7824 may be placed in two standby modes,

selected by decoder register B (it should be noted that the

device core is still active):

REGISTER B

REGISTER E

f

_xtal= 8.4672 MHz

0XXX

1XXX

0XXX

n = 1

n = 2; voltage mode

only

• Standby 1: CD STOP mode; most I/O functions are

switched off

0XXX

1XXX

n = 4; voltage mode

only

• Standby 2: CD PAUSE mode; audio output features are

switched off, but the motor loop, the motor output and

the subcode interfaces remain active; this is also called

a ‘Hot Pause’.

7.3

Crystal oscillator

The crystal oscillator is a conventional 2-pin design which

can also operate with ceramic resonators. The external

components used around the crystal are illustrated in Fig.4

together with component values (C1 and C2) for a given

crystal type given in Table 2. Oscillator frequencies that is

used with the SAA7824 is 8.4672 MHz.

In the standby modes the various pins will have the

following values:

• MOTO1 and MOTO2: put in to high-impedance, PWM

mode (Standby 1 and RESET: operating in Standby 2);

put in high-impedance, PDM mode (Standby 1 and

RESET: operating in Standby 2)

• Pins SCL and SDA: no interaction; normal operation

continues

^{handbook, halfpage}SAA7824

• Pins SCLK, WCLK, DATA, EF and DOBM: 3-state in

both standby modes; normal operation continues after

reset

OSCILLATOR

• Pins OSCIN, OSCOUT, CLK16 and CLK4/12: no

interaction; normal operation continues

OSCIN

C1

OSCOUT

C2

XTAL

• Pins V1 to V5 and CFLAG: no interaction; normal

operation continues.

MBL439

Fig.4 Crystal configuration.

Table 2 External capacitor selection based upon the crystal type

MAXIMUM SERIES

CRYSTAL RESISTANCE

EXTERNAL LOAD CAPACITORS

CRYSTAL LOAD

CAPACITANCE (C_L)

(R_S)

8 MHz

C1

C2

10 pF

20 pF

30 pF

<300 Ω

8 pF

27 pF

47 pF

8 pF

27 pF

47 pF

2003 Oct 01

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Philips Semiconductors

Product speciﬁcation

CD audio decoder, digital servo and ﬁlterless

DAC with integrated pre-amp and laser control

SAA7824

7.4

Data slicer and bit clock regenerator

7.5

DC offset cancellation

The SAA7824 has an integrated adaptive data slicer which

is clocked at 67 MHz. The slice level is controlled by

internal current sources which are switched onto and

integrated by the external capacitor connected to the

CSLICE pin. The currents are switched under the control

of a Digital Phase-Locked loop (DPLL).

Unwanted DC offsets can exist within the photo-diode

signals and are defined as the DC present in the system

when the laser diode is switched off. They arise from

various sources of imperfection within the system such as

leakage in the photo diodes and offsets in the Optical

Pick-Up (OPU) circuitry. The SAA7824 is capable of

measuring these offsets and minimizing them.

Regeneration of the bit clock is achieved with an internal

fully digital PLL. No external components are required and

the bit clock is not output. The PLL has two registers

(8 and 9) for selecting bandwidth and equalization. The

PLL loop response is illustrated in Fig.5.

7.5.1

OFFSET CANCELLATION

A number of registers are associated with the DC offset

cancellation function; these registers are given in Table 3.

For certain applications an off-track input is necessary.

This is internally connected from the servo part (its polarity

can be changed by the foc_parm1 parameter), but may be

input via pin V1 if selected by register C. If this flag is

HIGH, the SAA7824 will assume that its servo part is

following the wrong track, and will flag all incoming HF data

as incorrect.

The measurement time of the DC offset is regulated by

new shadow register C (bank 2). A longer time will yield

more accurate results but will result in greater

measurement durations.

New shadow register 3 (bank 3) is used to select which

diode is to be measured.

7.5.2

READING BACK THE DC OFFSET VALUE

The microcontroller needs to be able to read the DC offset

measurements in order to calculate the correct

cancellation value [for writing back to new shadow

register 7 (bank 3)].

handbook, halfpage

This is achieved by using the STATUS pin and setting

decoder register 7 to XX10. Shadow register C (bank 3)

can then be used to control the STATUS pin output; the

register settings are given in Table 20.

PLL

loop

response

Once the measurement time has been set and the diode

selected, the STATUS pin should be set to read the DC

offset ready flag [new shadow register C

3. PLL, LPF

f

(bank 3) = X01X]. This signal will toggle HIGH after the

prescribed measurement time. Changing the diode

selection will result in the measurement timer being

automatically reset.

2. PLL bandwidth

1. PLL integrator

MGS178

The microcontroller can read back the measurement by

setting the STATUS pin to output the DC offset value [new

shadow register C (bank 3) = X10X].

Points 1, 2 and 3 are all programmable via decoder register 8.

The offset value is repeatedly streamed out through the

STATUS pin and is UART compatible. It should be noted

that the MSB is inverted and will require re-inverting after

the offset value has been captured. Timing information for

this signal is illustrated in Fig.6.

Fig.5 Digital PLL loop response.

The final DC cancellation value (as calculated by the

microcontroller) can then be written to new shadow

register 7 (bank 3). This is a multiple write register

containing the cancellation values for all six diodes.

2003 Oct 01

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Philips Semiconductors

Product speciﬁcation

CD audio decoder, digital servo and ﬁlterless

DAC with integrated pre-amp and laser control

SAA7824

Table 3 Registers relating to the DC offset cancellation

SHADOW

REGISTER

SHADEN BITS

ADDRESS

DATA

FUNCTION

INITIAL

10

(bank 2)

C

1100

XX00

XX01

XX10

XX11

0000

0001

0010

0011

0100

0101

0110

0111

X00X

settling time = 354 µs

settling time = 1 ms

settling time = 2 ms

settling time = 10 ms

select D1

reset

DC offset

measurement

times

−

11

(bank 3)

3

0011

reset

diode selection

for DC offset

measurement

select D1

−

select D2

−

select D3

−

select D4

select R1

−

select R2

−

select D1

−

C

1100

0111

STATUS pin outputs

decoder status register

information

reset

STATUS pin

control

X01X

X10X

STATUS pin outputs DC

offset ready ﬂag

−

STATUS pin outputs DC

offset value

7

multi-write

(9 × 4 bits)

DC cancellation values for

diodes D1 to D4 and R1

and R2; see Table 20

−

DC cancellation

levels

handbook, full pagewidth

2.19/n µs

D1 D0

D7

D6

D5

D4

D3

D2

D1

D0

MBL440

272.1/n µs

Fig.6 Serial data format for DC offset data.

2003 Oct 01

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Philips Semiconductors

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DAC with integrated pre-amp and laser control

SAA7824

7.6

Demodulator

7.7.3

V4 SUBCODE INTERFACE

7.6.1

FRAME SYNC PROTECTION

Data of subcode channels, Q-to-W, may be read via pin V4

if selected via decoder register D. The format is similar to

RS232 and is illustrated in Fig.10. The subcode sync word

is formed by a pause of (200/n) µs minimum. Each

subcode byte starts with a logic 1 followed by 7 bits

(Q-to-W). The gap between bytes is variable between

(11.3/n) µs and (90/n) µs.

A double timing system is used to protect the demodulator

from erroneous sync patterns in the serial data. The

master counter is only reset if:

• A sync coincidence is detected; sync pattern occurs

588 ±1 EFM clocks after the previous sync pattern

• A new sync pattern is detected within ±6 EFM clocks of

its expected position.

The subcode data is also available in the EBU output

(DOBM) in a similar format.

The sync coincidence signal is also used to generate the

PLL lock signal, which is active HIGH after 1 sync

coincidence is found, and reset LOW if during 61

consecutive frames no sync coincidence is found. The PLL

lock signal can be accessed via the SDA or STATUS pins

selected by decoder registers 2, 7 and new shadow

register C (bank 3).

7.7.4

CD TEXT INTERFACE

R-to-W subcode data is captured and stored until a

complete CD text PACK is formed. The least significant

16 bits of the PACK are used for a CRC.

The behaviour of the CD text interface is controlled by new

shadow register 7 (bank 2). The interface can either flag

all data (i.e. passed or failed CRC) or it can flag good data

only.

Also incorporated in the demodulator is a Run Length 2

(RL2) correction circuit. Every symbol detected as RL2 will

be pushed back to RL3. To do this, the phase error of both

edges of the RL2 symbol are compared and the correction

is executed at the side with the highest error probability.

The data ready flag is monitored via pin CDTRDY and is

active LOW. The pulse width varies from 73/n µs, for the

first three packs, to 317/n µs for the fourth pack.

7.6.2

EFM DEMODULATION

When a PACK becomes available, the initial value of the

CDTDATA pin indicates the CRC result (HIGH = passed;

LOW = failed). The microcontroller can fetch the data by

applying a clock signal (maximum frequency = 5 MHz) to

pin CDTCLK and reading the subsequent bitstream on pin

CDTDATA.

The 14-bit EFM data and subcode words are decoded into

8-bit symbols.

7.7

Subcode data processing

7.7.1

Q-CHANNEL PROCESSING

The 128 data bits are streamed out LSB first. A complete

CD text PACK consists of 4 header bytes, 12 data bytes,

and 2 CRC bytes although the latter 2 bytes are dropped

internally once the CRC calculation is complete. Please

refer to the “Red Book” for further details relating to the

format of a CD text PACK

The 96-bit Q-channel word is accumulated in an internal

buffer. The last 16 bits are used internally to perform a

Cyclic Redundancy Check (CRC). If the data is good, the

SUBQREADY-I signal will go LOW. SUBQREADY-I can

be read via the SDA or STATUS pins, selected via decoder

registers 2, 7 and new shadow register C (bank 3). Good

Q-channel data may be read from pin SDA.

The timing diagram for the CD text interface is illustrated in

Fig.11.

7.7.2

EIAJ 3 AND 4-WIRE SUBCODE (CD GRAPHICS)

INTERFACE

Data from all the subcode channels (P-to-W) may be read

via the subcode interface, which conforms to

EIAJ CP-2401. The interface is enabled and configured as

either a 3 or 4-wire interface via decoder register F.

The subcode interface output formats are illustrated in

Fig.9, where the RCK signal is supplied by another device

such as a CD graphics decoder.

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SAA7824

SF0

SF1

SF2

SF3

SF97

SF0

SF1

handbook, full pagewidth

SBSY

SFSY

RCK

P-W

SUB

EIAJ 4-wire subcode interface

SF0

SF1

SF2

SF3

SF97

P-W

SF0

SF1

SFSY

RCK

P-W

SUB

EIAJ 3-wire subcode interface

SFSY

RCK

SUB

P

Q

R

S

T

U

V

W

MBG410

Fig.9 EIAJ subcode (CD graphics) interface format.

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DAC with integrated pre-amp and laser control

SAA7824

11.3/n

µs

200/n µs

min

11.3/n µs min

90/n µs max

W96

1

Q

R

S

T

U

V

W

1

Q

MBG401

Where n = disc speed.

Fig.10 Subcode format and timing on pin V4.

73/n µs to 317/n µs

handbook, full pagewidth

CDTRDY

CDTCLK

CRC flag

D0

D1

D2

D3

D126 D127

CDTDATA

MBL441

~1/n ns

200 ns (min)

Where n = disc speed.

Fig.11 CD text interface format and timing.

7.8

FIFO and error correction

7.8.1

FLAGS OUTPUT (CFLG)

The SAA7824 has a ±8 frame FIFO. The error corrector is

a t = 2, e = 4 type, with error corrections on both C1

(32 symbol) and C2 (28 symbol) frames. Four symbols are

used from each frame as parity symbols. This error

corrector can correct up to two errors on the C1 level and

up to four errors on the C2 level.

The flags output pin CFLG shows the status of the error

corrector and interpolator and is updated every frame

(7.35 × n kHz). In the SAA7824, 8 × 1-bit flags are present

on the CFLG pin as illustrated in Fig.12. This signal shows

the status of the error corrector and interpolator.

The first flag bit, F1, is the absolute time sync signal, the

FIFO-passed subcode sync and relates the position of the

subcode sync to the audio data (DAC output). This flag

may also be used in a super FIFO or in the synchronization

of different players. The output flags can be made

available at bit 4 of the EBU data format (LSB of the 24-bit

data word), if selected by decoder register A.

The error corrector also contains a flag processor. Flags

are assigned to symbols when the error corrector cannot

ascertain if the symbols are definitely good. C1 generates

output flags which are read after de-interleaving by C2, to

help in the generation of C2 output flags.

The C2 output flags are used by the interpolator for

concealment of uncorrectable errors. They are also output

via the EBU signal (DOBM). The EF output will flag bytes

in error in both audio and CD-ROM modes.

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SAA7824

handbook, full pagewidth

11.3/n

µs

33.9/n µs

F8

F1

F2

F3

F4

F5

F6

F7

F8

F1

MBG425

Where n = disc speed.

Fig.12 Flag output timing diagram.

Table 4 Output ﬂags

F1

F2

F3

F4

F5

F6

F7

F8

DESCRIPTION

no absolute time sync

0

1

X

0

X

0

X

0

X

0

X

0

X

0

X

0

absolute time sync

X

C1 frame contained no errors

C1 frame contained 1 error

C1 frame contained 2 errors

C1 frame uncorrectable

0

1

0

1

X

C2 frame contained no errors

C2 frame contained 1 error

C2 frame contained 2 errors

C2 frame contained 3 errors

C2 frame contained 4 errors

C2 frame uncorrectable

0

1

0

1

0

1

0

1

X

no interpolations

0

1

at least one 1-sample interpolation

at least one hold and no interpolations

at least one hold and one 1-sample interpolation

1

0

1

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DAC with integrated pre-amp and laser control

SAA7824

7.9

Audio functions

7.9.3

CONCEALMENT

7.9.1

DE-EMPHASIS AND PHASE LINEARITY

A 1-sample linear interpolator becomes active if a single

sample is flagged as erroneous but cannot be corrected.

The erroneous sample is replaced by a level midway

between the preceding and following samples. Left and

right channels have independent interpolators. If more

than one consecutive non-correctable sample is found, the

last good sample is held. A 1-sample linear interpolation is

then performed before the next good sample; see Fig.13.

When pre-emphasis is detected in the Q-channel

subcode, the digital filter automatically includes a

de-emphasis filter section. When de-emphasis is not

required, a phase compensation filter section controls the

phase of the digital oversampling filter to ≤ ±1° within the

band 0 to 16 kHz. With de-emphasis the filter is not phase

linear.

In CD-ROM modes (i.e. the external DAC interface is

selected to be in a CD-ROM format) concealment is not

executed.

If the de-emphasis signal is set to be available at pin V5,

selected via decoder register D, then the de-emphasis

filter is bypassed.

7.9.4

MUTE, FULL-SCALE, ATTENUATION AND FADE

7.9.2

DIGITAL OVERSAMPLING FILTER

A digital level controller is present on the SAA7824 which

performs the functions of soft mute, full-scale, attenuation

and fade; these are selected via decoder register 0:

For optimizing performance with an external DAC, the

SAA7824 contains a 2 to 4 times oversampling IIR filter.

The filter specification of the 4 times oversampling filter is

given in Table 5.

• Mute: signal reduced to 0 in a maximum of 128 steps;

3/n ms

These attenuations do not include the sample-and-hold at

the external DAC output or the DAC post filter. When using

the oversampling filter, the output level is scaled −0.5 dB

down to avoid overflow on full-scale sine wave inputs

(0 to 20 kHz).

• Attenuation: signal scaled by −12 dB

• Full-scale: ramp signal back to 0 dB level; from mute it

takes 3/n ms

• Fade: activates a 128 stage counter which allows the

signal to be scaled up or down in 0.07 dB steps

Table 5 Filter speciﬁcation

– 128 = full-scale

PASS BAND

STOP BAND

ATTENUATION

– 120 = −0.5 dB (i.e. full-scale if oversampling filter is

used)

0 to 9 kHz

−

≤0.001 dB

≤0.03 dB

≥25 dB

≥38 dB

≥40 dB

≥50 dB

≥31 dB

≥35 dB

≥40 dB

– 32 = −12 dB

19 to 20 kHz

−

– 0 = mute.

−

24 kHz

24 to 27 kHz

27 to 35 kHz

35 to 64 kHz

64 to 68 kHz

68 kHz

7.9.5

PEAK DETECTOR

The peak detector measures the highest audio level

(absolute value) on positive peaks for left and right

channels. The 8 most significant bits are output in the

Q-channel data in place of the CRC bits. Bits 81 to 88

contain the left peak value (bit 88 = MSB) and bits 89 to 96

contain the right peak value (bit 96 = MSB). The values

are reset after reading Q-channel data via pin SDA.

69 to 88 kHz

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SAA7824

Interpolation

Hold

Interpolation

OK

Error

OK

Error

OK

MGA372

Fig.13 Concealment mechanism.

7.10 Audio DAC interface

7.10.1 INTERNAL DYNAMIC ELEMENT MATCHING DIGITAL-TO-ANALOG CONVERTER

The onboard audio DEM DAC operates at an oversampling rate of 96f_sand is designed for operation with an audio input

at 1f_s. The DAC is equipped with two pairs of stereo outputs for driving medium impedance line outputs and for directly

driving low impedance headphones. A pair of analog inputs are provided to enable external audio sources to make use

of the headphone output buffers.

Audio data from the decoder part of the SAA7824 can be routed as described in Sections 7.10.1.1 and 7.10.1.2.

Table 6 Shadow register

SHADOW

REGISTER

SHADEN BITS

ADDRESS

DATA

FUNCTION

RESET

01

(bank 1)

7

0111

0000

use external DAC or route audio data

back into onboard DAC (loopback

mode)

reset

control of

onboard DAC

0010

route audio data directly into onboard

DAC (non-loopback mode)

−

7.10.1.1 Use of internal DAC

Setting shadow register 7 to 0010 will route audio data from the decoder into the internal DAC. To enable the on-board

DAC, the DAC interface format (set by register 3) must be set to 16-bit 1f_smode, either I²S-bus or EIAJ format. CD-ROM

mode can also be used if interpolation is not required. The serial data output pins for interfacing with an external DAC

(SCLK, WCLK, DATA and EF) are set to high-impedance.

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SAA7824

7.10.1.2 Loopback external data into onboard DAC

The SAA7824 is compatible with a wide range of external

DACs. Eleven formats are supported and are given in

Table 7. Figures 14 and 15 show the Philips I²S-bus and

the EIAJ data formats respectively. When the decoder is

operated in lock-to-disc mode, the SCLK frequency is

dependent on the disc speed factor ‘d’.

The onboard DAC can also be set to accept serial data

inputs from an external source, e.g. an Electronic Shock

Absorption (ESA) IC. This is known as loopback mode and

is enabled by setting shadow register 7 to 0000. This

enables the serial data output pins (SCLK, WCLK, DATA

and EF) so that data can be routed from the SAA7824 to

an external ESA system (or external DAC).

All formats are MSB first and 1f_sis 44.1 kHz. The polarity

of the WCLK and the data can be inverted; selectable by

decoder register 7. It should be noted that EF is only a

defined output in CD-ROM and 1f_smodes.

The serial data from an external ESA IC can then also be

input to the onboard DAC on the SAA7824 by utilising the

serial data input interface (SCLI, SDI and WCLI).

When using an external DAC (or when using the onboard

DAC in non-loopback mode), the serial data inputs to the

onboard DAC (SCLI, SDI and WCLI) should be tied to

ground.

In this mode, a wide range of data formats to the external

ESA IC can be programmed as shown in Table 7.

However, the serial input on the SAA7824 will always

expect the input data from the ESA IC to be 16-bit 1f_sand

the same data format, either I²S-bus or EIAJ, as the serial

output format (set by decoder register 3).

7.10.2 EXTERNAL DAC INTERFACE

Audio data from the SAA7824 can be sent to an external

DAC, identical to the SAA732x series, in ‘loopback’ mode

(i.e. shadow register 7 is set to 0000).

Table 7 DAC interface formats

SAMPLE

FREQUENCY

NUMBER OF

BITS

REGISTER 3

SCLK (MHz)

FORMAT

INTERPOLATION

1010

f_s

16

2.1168 × n

CD-ROM

(I²S-bus)

no

1011

1110

f_s

16

16/18⁽¹⁾

2.1168 × n

CD-ROM (EIAJ)

Philips I²S-bus

16/18 bits⁽¹⁾

no

yes

0010

0110

0000

0100

1100

f_s

16

18

16

18

2.1168 × n

8.4672 × n

EIAJ 16 bits

EIAJ 18 bits

EIAJ 16 bits

EIAJ 18 bits

Philips I²S-bus

18 bits

yes

f_s

4f_s

0011

0111

1111

2f_s

16

18

4.2336 × n

EIAJ 16 bits

EIAJ 18 bits

Philips I²S-bus

18 bits

yes

Note

1. In this mode the first 16 bits contain data, but if any of the fade, attenuate or de-emphasis filter functions are activated

then the first 18 bits contain data.

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7.11 EBU interface

• Soft mute: 3 ms ramp up or ramp down of the audio

samples in the 1× audio mode

The bi-phase mark digital output signal at pin DOBM is in

accordance with the format defined by the IEC 60958

specification. Three different modes can be selected via

decoder register A:

• Bypass: switches the EBU mute function out of the EBU

signal path.

7.11.1 FORMAT

• DOBM pin held LOW

The digital audio output consists of 32-bit words

(‘subframes’) transmitted in bi-phase mark code (two

transitions for a logic 1 and one transition for a logic 0).

Words are transmitted in blocks of 384. The EBU frame

format is given in Table 8.

• Data taken before concealment, mute and fade (must

always be used for CD-ROM modes)

• Data taken after concealment, mute and fade.

An additional mute function is available via shadow

register 7 (bank 1) and decoder register 0 and C. They

provide the following:

• Hard mute: immediate mute of the audio sample in the

ROM mode at 1×, 2× or 4×

Table 8 EBU frame format; see also Table 9

FUNCTION

Sync

BITS

DESCRIPTION

0 to 3

4 to 7

4

−

Auxiliary

not used; normally zero

Error ﬂags

CFLG error and interpolation ﬂags when selected by register A

ﬁrst 4 bits not used (always zero); twos complement; LSB = bit 12, MSB = bit 27

valid = logic 0

Audio sample

Validity ﬂag

User data

8 to 27

28

29

used for subcode data (Q-to-W)

Channel status

30

control bits and category code

Table 9 Description of EBU frame function

FUNCTION

DESCRIPTION

Sync

The sync word is formed by violation of the bi-phase rule and therefore does not contain any data.

Its length is equivalent to 4 data bits. The 3 different sync patterns indicate the following situations:

sync B; start of a block (384 words), word contains left sample; sync M; word contains left sample

(no block start) and sync W; word contains right sample.

Audio sample

Validity ﬂag

Left and right samples are transmitted alternately.

Audio samples are ﬂagged (bit 28 = 1) if an error has been detected but was uncorrectable. This

ﬂag remains the same even if data is taken after concealment.

User data

Subcode bits Q-to-W from the subcode section are transmitted via the user data bit. This data is

asynchronous with the block rate.

Channel status The channel status bit is the same for left and right words. Therefore a block of 384 words contains

192 channel status bits. The category code is always CD. The bit assignment is given in Table 10.

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SAA7824

Table 10 Bit assignment

FUNCTION

Control

BITS

DESCRIPTION

0 to 3

copy of CRC checked Q-channel control bits 0 to 3; bit 2 is logic 1 when copy

permitted; bit 3 is logic 1 when recording has pre-emphasis

Reserved mode

Category code

Clock accuracy

Remaining

4 to 7

8 to 15

28 to 29

always zero

CD: bit 8 = logic 1, all other bits = logic 0

set by register A; 10 = level I; 00 = level II; 01 = level III

always zero

6 to 27 and

30 to 191

7.12 KILL features

7.13 Audio features off

7.12.1 THE KILL CIRCUIT

The audio features can be turned off (selected by decoder

register E) and will affect the following functions:

The KILL circuit detects digital silence by testing for an

all-zero or all-ones data word in the left and right channels.

This occurs in two places; prior to the digital filter (internal

KILL), and in the digital DAC (loopback/external KILL).

Programming bit 3 of new shadow register A (bank 2)

determines whether internal or external data is used. The

output is switched to active HIGH when silence has been

detected for at least 270 ms, or if mute is active, or in

CD-ROM mode. Two KILL modes are available which can

be selected by decoder register C:

• Digital filter, fade, peak detector, internal KILL circuit

(although RKILL and LKILL outputs still active) are

disabled

• V5 (if selected to be the de-emphasis flag output) and

the EBU outputs become undefined.

The EBU output should be set LOW prior to switching the

audio features off and after switching the audio features

back on, a full-scale command should be given.

• Mono KILL: LKILL and RKILL are both active HIGH

when silence is detected on left and right channels

simultaneously

7.14 The versatile pins interface

The SAA7824 has five pins that can be reconfigured for

different applications.

• Stereo KILL: LKILL and RKILL are active HIGH

independently of each other when silence is detected on

either channel.

The functions of these versatile pins are identical to the

SAA732x series and can be programmed by decoder

registers C, D and shadow register 3 (bank 1) as shown in

Table 11.

7.12.2 SILENCE INJECTION

The silence inject function monitors the left and right KILL

signals and forces the analog DAC into silence when KILL

is asserted. This improves the internal Signal-to-Noise

Ratio (SNR) by preventing any spurious noise from

reaching the DAC. The silence inject function can be

enabled or disabled by programming bit 2 of the new

shadow register A (bank 2).

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SAA7824

Table 11 Pin applications

NAME

NUMBER

REGISTER REGISTER

TYPE

FUNCTION

ADDRESS

DATA

V1

71

input

1100

XXX1

XXX0

external off-track signal input

−

internal off-track signal used input may be read

via decoder status bit; selected via register 2

V2

V3

72

73

input

−

input may be read via decoder status bit;

selected via register 2

output

1100

00XX

01XX

0000

XX01

XX10

XX11

01XX

10XX

11XX

output = 0

−

output = 1

V4

74

output

1101

4-line motor drive (using V4 and V5)

Q-to-W subcode output

output = 0

−

output = 1

V5

75

1101

−

de-emphasis output (active HIGH)

output = 0

−

output = 1

7.15 Spindle motor control

7.15.1.1 Pulse density output mode

7.15.1 MOTOR OUTPUT MODES

In the pulse density mode the motor output pin (MOTO1)

is the pulse density modulated motor output signal.

The spindle motor speed is controlled by a fully integrated

digital servo. Address information from the internal ±8

frame FIFO and disc speed information are used to

calculate the motor control output signals. Several output

modes, selected by decoder register 6, are supported:

A 50% duty factor corresponds with the motor not

actuated, higher duty factors mean acceleration, lower

duty factors means braking. In this mode, the MOTO2

signal is the inverse of the MOTO1 signal. Both signals

change state only on the edges of a (1 × n) MHz internal

clock signal.

• Pulse density, 2-line (true complement output),

(1 × n) MHz sample frequency

• PWM output, 2-line, (22.05 × n) kHz modulation

frequency

7.15.1.2 PWM output mode (2-line)

In the PWM mode the motor acceleration signal is put in

pulse-width modulation form on the MOTO1 output. The

motor braking signal is pulse-width modulated on the

MOTO2 output. The timing is illustrated in Fig 16. A typical

application diagram is illustrated in Fig 17.

• PWM output, 4-line, (22.05 × n) kHz modulation

frequency

• CDV motor mode.

t

240 ns

t

= 45 µs

dead

rep

MOTO1

MOTO2

MGA366

Accelerate

Brake

Fig.16 2-line PWM mode timing.

25

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+

M

10 Ω

100 nF

MOTO1

MOTO2

V

MGA365 - 2

SS

Fig.17 Motor 2-line PWM mode application diagram.

7.15.1.3 PWM output mode (4-line)

Using two extra outputs from the versatile pins interface, it is possible to use the SAA7824 with a 4-input motor bridge.

The timing is illustrated in Fig 18. A typical application diagram is illustrated in Fig 19.

t

= 45 µs

t

240 ns

rep

dead

MOTO1

MOTO2

V4

V5

MGA367 - 1

t

= 240 ns

ovl

Accelerate

Brake

Fig.18 4-line PWM mode timing.

26

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+

V4

V5

M

10 Ω

100 nF

MOTO1

MOTO2

V

SS

MGA364 - 2

Fig.19 Motor 4-line PWM mode application diagram.

7.15.2.1 Motor OV ﬂag

7.15.1.4 CDV/CAV output mode

In the CDV motor mode, the FIFO position will be put in

pulse-width modulated form on the MOTO1 pin [carrier

frequency (300 × d) Hz], where ‘d’ is the disc speed factor.

The PLL frequency signal will be put in pulse-density

modulated form (carrier frequency 4.23 × n MHz) on the

MOTO2 pin. The integrated motor servo is disabled in this

mode.

The SAA7824 contains a servo loop that is used to

regulate the spindle speed. The motor OV flag is provided

to indicate when the motor output has overloaded. During

a large change in disc speed i.e. by a long jump or x-factor

change, the motor OV flag will be asserted due to the full

and longer duration required to attain the new desired

speed.

The PWM signal on MOTO1 corresponds to a total

memory space of 20 frames, therefore the nominal FIFO

position (half full) will result in a PWM output of 60%.

The OV flag indicates when the internal processes of the

modulator have overflowed and not necessarily when the

output power has reached 100%. Similarly, the flag does

not fall at a specific output power level but at a specific

speed error level. The error level at which the flag falls is

determined by the selected servo gain, and will be

internally equivalent to +3 × gain or −3 × gain.

In the lock-to-disc (CAV) mode the CDV motor mode is the

only mode that can be used to control the motor.

7.15.2 SPINDLE MOTOR OPERATING MODES

The operating modes of the motor servo are controlled by

decoder register 1; see Table 12.

7.15.2.2 Power limit

In start mode 1, start mode 2, stop mode 1 and stop

mode 2, a fixed positive or negative voltage is applied to

the motor.

In the SAA7824 decoder there is an anti-windup mode for

the motor servo, selected via decoder register 1. When the

anti-windup mode is activated the motor servo integrator

will hold if the motor output saturates.

This voltage can be programmed as a percentage of the

maximum possible voltage, via register 6, to limit current

drain during start and stop.

The following power limits are possible:

• 100% (no power limit), 75%, 50% or 37% of maximum.

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7.15.3 LOOP CHARACTERISTICS

It should be noted that the crossover frequencies f₃and f₄

are scaled with the overspeed factor ‘n’ whereas the gains

are not.

The gain and crossover frequencies of the motor control

loop can be programmed via decoder registers 4 and 5.

The following parameter values are possible:

7.15.4 FIFO OVERFLOW

• Gains: 3.2, 4.0, 6.4, 8.0, 12.8, 16, 25.6 and 32

If FIFO overflow occurs during Play mode (e.g. as a result

of motor rotational shock), the FIFO will be automatically

reset to 50% and the audio interpolator will conceal as

much as possible to minimize the effect of data loss.

• Crossover frequency f₄: 0.5 × n Hz, 0.7 × n Hz,

1.4 × n Hz and 2.8 × n Hz

• Crossover frequency f₃: 0.85 × n Hz, 1.71 × n Hz and

3.42 × n Hz.

Table 12 Operating modes

MODE

DESCRIPTION

Start mode 1

The disc is accelerated by applying a positive voltage to the spindle motor. No decisions are

involved and the PLL is reset. No disc speed information is available for the microcontroller.

Start mode 2

The disc is accelerated as in start mode 1, however the PLL will monitor the disc speed. When the

disc reaches 75% of its nominal speed, the controller will switch to jump mode. The motor status

signals selectable via register 2 are valid.

Jump mode

Motor servo enabled but FIFO kept reset at 50%, integrator is held. The audio is muted but it is

possible to read the subcode. It should be noted that in the CD-ROM modes the data, on EBU and

the I²S-bus, is not muted.

Jump mode 1

Similar to jump mode but motor integrator is kept at zero. It is used for long jumps where there is a

large change in disc speed.

Play mode

FIFO released after resetting to 50% and the audio mute is released.

Stop mode 1

Stop mode 2

Disc is braked by applying a negative voltage to the motor; no decisions are involved.

The disc is braked as in stop mode 1 but the PLL will monitor the disc speed. As soon as the disc

reaches 12% (or 6%, depending on the programmed brake percentage, via register E) of its

nominal speed, the MOTSTOP status signal will go HIGH and switch the motor servo to off mode.

Off mode

Motor not steered.

MGA362 - 2

G

f

BW

f

4

3

Fig.20 Motor servo mode diagram.

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7.16 Servo part

The low frequency content of the six (five if single

Foucault) photo diode inputs are converted to digital Pulse

Density Modulated (PDM) bitstreams by six Sigma-delta

ADCs. These support a range of OPUs by interfacing to

Voltage mode mechanisms and by having 16 selectable

gain ranges in two sets, one set for D1-to-D4 and the other

for R1 and R2.

7.16.1 DIODE SIGNAL PROCESSING

The photo detector in conventional two-stage three-beam

Compact Disc systems normally contains six discrete

diodes. Four of these diodes (three for single foucault

systems) carry the Central Aperture signal (CA) while the

other two diodes (satellite diodes) carry the radial tracking

information. The CA signals are summed into an HF signal

for the decoder function and are also differentiated (after

analog-to-digital conversion) to produce the low frequency

focus control signals.

Table 13 Shadow register settings to control diode voltage ranges

SHADOW

REGISTER

SHADEN BITS

01

ADDRESS

DATA

VOLTAGE (mV)

INITIAL

A

1010

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

20

25

−

(bank 1)

signal magnitude

control for diodes

D1 to D4

30

−

40

−

(LF only)

60

−

75

−

100

120

150

200

270

350

450

600

720

960

−

reset

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SHADOW

REGISTER

SHADEN BITS

ADDRESS

DATA

VOLTAGE (mV)

INITIAL

01

(bank 1)

C

1100

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

20

25

−

signal magnitude

control for diodes

R1 and R2 (LF

only)

30

−

40

−

60

−

75

−

100

120

150

200

270

350

450

600

720

960

−

reset

7.16.2 SIGNAL CONDITIONING

The radial or tracking error signal is generated by the

satellite detector signals R1 and R2. The radial error

signal can be formulated as follows:

The digital codes retrieved from the ADCs are applied to

logic circuitry to obtain the various control signals. The

signals from the central aperture diodes are processed to

obtain a normalised focus error signal:

RE_s= (R1 − R2) × re_gain + (R1 + R2) × re_offset.

Where the index ‘s’ indicates the automatic scaling

operation which is performed on the radial error signal.

This scaling is necessary to avoid non-optimum dynamic

range usage in the digital representation and reduces the

radial bandwidth spread. Furthermore, the radial error

signal will be made free from offset during start-up of the

disc.

D1 – D2 D3 – D4

D1 + D2 D3 + D4

FE_n

=

–

---------------------- ----------------------

Where the detector set-up is assumed to be as shown in

Fig.21.

In the event of single Foucault focusing method, the signal

conditioning can be switched under software control such

that the signal processing is as follows:

The four signals from the central aperture detectors,

together with the satellite detector signals generate a

Track Position signal (TPI) which can be formulated as

follows:

D1 – D2

D1 + D2

FE_n= 2 ×

----------------------

TPI = sign [(D1 + D2 + D3 + D4) − (R1 + R2) × sum_gain]

The error signal, FE_n, is further processed by a

Where the weighting factor sum_gain is generated

internally by the SAA7824 during initialization.

Proportional Integral and Differential (PID) filter section.

A Focus OK (FOK) flag is generated by the central

aperture signal and an adjustable reference level. This

signal is used to provide extra protection for the

Track-Loss (TL) generation, the focus start-up procedure

and the dropout detection.

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SATELLITE

DIODE R1

SATELLITE

DIODE R1

SATELLITE

DIODE R1

D1

D2

D3

D4

D1

D3

D2

D4

D1

D3

D2

SATELLITE

DIODE R2

SATELLITE

DIODE R2

SATELLITE

DIODE R2

single Foucault

astigmatic focus

double Foucault

MBG422

Fig.21 Detector arrangement.

7.16.3 FOCUS SERVO SYSTEM

7.16.3.1 Focus start-up

These coefficients influence the integrating (foc_int),

proportional (foc_lead_length, part of foc_parm3) and

differentiating (foc_pole_lead, part of foc_parm1) action of

the PID and a digital low-pass filter (foc_pole_noise, part

of foc_parm2) following the PID. The fifth coefficient

foc_gain influences the loop gain.

Five initially loaded coefficients influence the start-up

behaviour of the focus controller. The automatically

generated triangular voltage can be influenced by

3 parameters; for height (ramp_height) and DC offset

(ramp_offset) of the triangle and its steepness

(ramp_incr).

7.16.3.3 Dropout detection

This detector can be influenced by one parameter

(CA_drop). The FOK signal will become false and the

integrator of the PID will hold if the CA signal drops below

this programmable absolute CA level. When the FOK

signal becomes false it is assumed, initially, to be caused

by a black dot.

For protection against false focus point detections two

parameters are available which are an absolute level on

the CA signal (CA_start) and a level on the FE_nsignal

(FE_start). When this CA level is reached the FOK signal

becomes true.

If the FOK signal is true and the level on the FE_nsignal is

reached, the focus PID is enabled to switch-on when the

next zero crossing is detected in the FE_nsignal.

7.16.3.4 Focus loss detection and fast restart

Whenever FOK is false for longer than approximately

3 ms, it is assumed that the focus point is lost. A fast

restart procedure is initiated which is capable of restarting

the focus loop within 200 to 300 ms depending on the

programmed coefficients of the microcontroller.

7.16.3.2 Focus position control loop

The focus control loop contains a digital PID controller

which has 5 parameters that are available to the user.

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7.16.3.5 Focus loop gain switching

Both modes of S-curve extension make use of a

track-count mechanism. In this mode, track counting

The gain of the focus control loop (foc_gain) can be

multiplied by a factor of 2 or divided by a factor of 2 during

normal operation. The integrator value of the PID is

corrected accordingly. The differentiating (foc_pole_lead)

action of the PID can be switched at the same time as the

gain switching is performed.

results in an ‘automatic return-to-zero track’, to avoid

major disturbances in the audio output and providing

improved shock resistance. The sledge is continuously

controlled, or provided with step pulses to reduce power

consumption using the filtered value of the radial PID

output. Alternatively, the microcontroller can read the

average voltage on the radial actuator and provide the

sledge with step pulses to reduce power consumption.

Filter coefficients of the continuous sledge control can be

preset by the user.

7.16.3.6 Focus automatic gain control loop

The loop gain of the focus control loop can be corrected

automatically to eliminate tolerances in the focus loop.

This gain control injects a signal into the loop which is used

to correct the loop gain. Since this decreases the optimum

performance, the gain control should only be activated for

a short time (for example, when starting a new disc).

7.16.4.4 Access

The access procedure is divided into two different modes

(see Table 14), depending on the requested jump size.

7.16.4 RADIAL SERVO SYSTEM

7.16.4.1 Level initialization

Table 14 Access modes

ACCESS

TYPE

ACCESS

SPEED

JUMP SIZE⁽¹⁾

During start-up an automatic adjustment procedure is

activated to set the values of the radial error gain (re_gain),

offset (re_offset) and satellite sum gain (sum_gain) for TPI

level generation. The initialization procedure runs in a

radial open loop situation and is ≤300 ms. This start-up

time period may coincide with the last part of the motor

start-up time period:

Actuator jump 1 − brake_distance

decreasing

velocity

Sledge jump brake_distance −32768 maximum

power to

sledge⁽¹⁾

• Automatic gain adjustment: as a result of this

initialization the amplitude of the RE signal is adjusted to

within ±10% around the nominal RE amplitude

Note

1. The microcontroller can be preset.

• Offset adjustment: the additional offset in RE due to the

limited accuracy of the start-up procedure is less than

±50 nm

The access procedure makes use of a track counting

mechanism, a velocity signal based on a fixed number of

tracks passed within a fixed time interval, a velocity set

point calculated from the number of tracks to go and a user

programmable parameter indicating the maximum sledge

performance.

• TPI level generation: the accuracy of the initialization

procedure is such that the duty factor range of TPI

becomes 0.4 < duty factor < 0.6 (default duty

factor = TPI HIGH/TPI period).

If the number of tracks remaining is greater than the

brake_distance then the sledge jump mode should be

activated or, the actuator jump should be performed. The

requested jump size together with the required sledge

breaking distance at maximum access speed defines the

brake_distance value.

7.16.4.2 Sledge control

The microcontroller can move the sledge in both directions

via the steer sledge command.

7.16.4.3 Tracking control

During the actuator jump mode, velocity control with a PI

controller is used for the actuator. The sledge is then

continuously controlled using the filtered value of the radial

PID output. All filter parameters (for actuator and sledge)

are user programmable.

The actuator is controlled using a PID loop filter with user

defined coefficients and gain. For stable operation

between the tracks, the S-curve is extended over 75% of

the track. On request from the microcontroller, S-curve

extension over 2.25 tracks is used, automatically changing

to access control when exceeding those 2.25 tracks.

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In the sledge jump mode maximum power (user

3. Fast counting state: used in high velocity track jump

situations. Highest obtainable velocity is the most

important feature in this state.

programmable) is applied to the sledge in the correct

direction while the actuator becomes idle (the content of

the actuator integrator leaks to zero just after the sledge

jump mode is initiated). The actuator can be electronically

damped during sledge jump. The gain of the damping loop

is controlled via the hold_mult parameter.

7.16.6 TRACK COUNTING MODES

Fast counting mode is auto-selected for a track crossing

speed above 1200 tracks/s. In this case the off-track

counting decrements occur only for effect of the RP signal,

and the direction of the jump is already known because the

Slow counting mode occurs before going into Fast

counting mode.

The fast track jumping circuitry can be enabled or disabled

via the xtra_preset parameter.

7.16.4.5 Radial automatic gain control loop

The loop gain of the radial control loop can be corrected

automatically to eliminate tolerances in the radial loop.

This gain control injects a signal into the loop which is used

to correct the loop gain. Since this decreases the optimum

performance, the gain control should only be activated for

a short time (for example, when starting a new disc).

When the Slow counting mode is selected, the maximum

track crossing speed that can be reached is 12 kHz

(providing that the maximum value for rad_pole_lead is

used). In this case the direction of the jump is given by the

phase shift between RP and TL (+90 degrees for outward

jumps, −90 degrees for inward jumps). The number of

pulses in the TL signal gives the number of tracks crossed.

This gain control differs from the level initialization. The

level initialization should be performed first. The

disadvantage of using the level initialization without the

gain control is that only tolerances from the front-end are

reduced.

When the Fast counting mode is enabled, whenever the

track crossing speed goes below 12 kHz, the counting

mode is automatically changed to Slow.

7.16.7 DEFECT DETECTION

7.16.5 OFF-TRACK COUNTING

A defect detection circuit is incorporated into the

SAA7824. If a defect is detected, the radial and focus error

signals may be zeroed, resulting in better playability. The

defect detector can be switched off, applied only to focus

control or applied to both focus and radial controls under

software control (part of foc_parm1).

The Track Position signal (TPI) is a flag which is used to

indicate whether the radial spot is positioned on the track,

with a margin of ±0.25 of the track pitch. In combination

with the Radial Polarity flag (RP) the relative spot position

over the tracks can be determined.

These signals can have uncertainties caused by:

The defect detector (see Fig 22) has programmable set

points selectable by the parameter defect_parm.

• Disc defects such as scratches and fingerprints

• The HF information on the disc, which is considered as

noise by the detector signals.

7.16.8 OFF-TRACK DETECTION

During active radial tracking, off-track detection has been

realised by continuously monitoring the off-track counter

value. The off-track flag becomes valid whenever the

off-track counter value is not equal to zero. Depending on

the type of extended S-curve, the off-track counter is reset

after 0.75 extend or at the original track in the 2.25 track

extend mode.

In order to determine the spot position with sufficient

accuracy, extra conditions are necessary to generate a

Track Loss signal (TL) and an off-track counter value.

These extra conditions influence the maximum speed and

this implies that, internally, one of the following three

counting states is selected:

1. Protected state: used in normal play situations. A good

protection against false detection caused by disc

defects is important in this state.

2. Slow counting state: used in low velocity track jump

situations. In this state a fast response is important

rather than the protection against disc defects (if the

phase relationship between TL and RP of 0.5π radians

is affected too much, the direction cannot then be

determined accurately).

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+

defect

output

DECIMATION

FILTER

FAST

FILTER

SLOW

FILTER

DEFECT

GENERATION

PROGRAMMABLE

HOLD-OFF

sat1

sat2

−

MBG421

Fig.22 Block diagram of the defect detector.

7.16.9 HIGH-LEVEL FEATURES

It should be noted that if the STATUS pin is configured to

output decoder status information [decoder register

7 = XX10 and new shadow register C (bank 3) = X00X]

and either the microcontroller writes a different value to

decoder register 2 or the decoder interface is enabled then

the STATUS output will change.

7.16.9.1 Interrupt mechanism and STATUS pin

The STATUS pin is an output which can be configured by

decoder register 7 and new shadow register C (bank 3) for

one of three different modes of operation. These are:

• Output the interrupt signal generated by the servo part

(it should be noted that the selection of this mode will

override all other modes)

7.16.9.2 Decoder interface

The decoder interface allows decoder and shadow

registers to be programmed and subcode Q-channel data

to be read via servo commands. The interface is enabled

or disabled by the preset latch command (and the

xtra_preset parameter).

• Output the decoder status bit (active LOW) selected by

decoder register 2 (only available in 4-wire bus mode)

• Output DC offset information (it should be noted that this

mode is used in conjunction with the decoder status

mode; see Section 7.5).

7.16.9.3 Automatic error handling

Three Watchdogs are present:

Eight signals from the interrupt status register are

selectable from the servo part via the interrupt_mask

parameter. The interrupt is reset by sending the read

high-level status command. The 8 signals are as follows:

• Focus: detects focus dropout of longer than 3 ms, sets

focus lost interrupt, switches off radial and sledge

servos and disables the drive-to-disc motor

• Focus lost: dropout of longer than 3 ms

• Subcode ready

• Radial play: started when radial servo is in on-track

mode and a first subcode frame is found; detects when

the maximum time between two subcode frames

exceeds the time set by the playwatchtime parameter; it

then sets the radial error interrupt, switches radial and

sledge servos off and puts the disc motor into jump

mode

• Subcode absolute seconds changed

• Subcode discontinuity detected: new subcode time

before previous subcode time, or more than 10 frames

later than previous subcode time

• Radial error: during radial on-track, no new subcode

frame occurs within the time defined by the

‘playwatchtime’ parameter; during radial jump, less than

4 tracks have been crossed during the time defined by

the ‘jumpwatchtime’ parameter

• Radial jump: active when radial servo is in long jump or

short jump modes; detects when the off-track counter

value decreases by less than 4 tracks between two

readings (the time interval is set by the jumpwatchtime

parameter); it then sets the radial jump error, switches

radial and sledge servos off to cancel jump.

• Autosequencer state change

• Autosequencer error

The focus Watchdog is always active, the radial

Watchdogs are selectable via the radcontrol parameter.

• Subcode interface blocked: the internal decoder

interface is being used.

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7.16.9.4 Automatic sequencers and timer interrupts

During reset (i.e. RESET pin is held LOW) the RA, FO and

SL pins are high-impedance. At all other times, when the

laser is switched off, the RA and FO pins output a 2 MHz

50% duty factor signal.

Two automatic sequencers are implemented (and must be

initialized after Power-on):

• Auto-start sequencer: controls the start-up of focus,

radial and motor

7.16.11 LASER INTERFACE

• Auto-stop sequencer: brakes the disc and shuts down

the servos.

The laser diode pre-amplifier function is built into the

SAA7824 and is illustrated in Fig.24. The current can be

regulated, up to 120 mA in four steps ranging from 58% up

to full power. New shadow register A (bank 2) and new

shadow register 3 (bank 3) are used to select the step

values.

When the automatic sequencers are not used it is possible

to generate timer interrupts, defined by the

time_parameter coefficient.

7.16.9.5 High-level status

The voltage derived from the monitor diode is maintained

at a steady state by the laser drive circuitry, regulating the

current through the laser diode. The type of monitor diode

being used (150 mV or 180 mV) must be selected by new

shadow register 7 (bank 2) (reset state = 150 mV).

The read high-level status command can be used to obtain

the interrupt, decoder, autosequencer status registers and

the motor start time. Use of the read high-level status

command clears the interrupt status register, and

re-enables the subcode read via a servo command.

The laser can be switched on or off by the xtra_preset

parameter; it is automatically driven if the focus control

loop is active.

7.16.10 DRIVER INTERFACE

The control signals (pins RA, FO and SL) for the

mechanism actuators are pulse density modulated. The

modulating frequency can be set to either 1.0584 or

2.1168 MHz; controlled via the xtra_preset parameter.

An analog representation of the output signals can be

achieved by connecting a 1st-order low-pass filter to the

outputs.

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7.17 Microcontroller interface

• I²C-bus mode: I²C-bus protocol where the SAA7824

behaves as slave device, activated by setting

RAB = HIGH and SILD = LOW where:

Communication on the microcontroller interface can be

set-up in three different modes:

– I²C-bus slave address (write mode) = 30H

• 4-wire bus mode: where:

– SCL = serial clock

– SDA = serial data

–

I²C-bus slave address (read mode) = 31H

– Maximum data transfer rate = 400 kbits/s.

It should be noted that when using the I²C-bus mode, only

servo commands can be used. Therefore, writing to

decoder registers 0 to F, reading decoder status and

reading Q-channel subcode data must be performed by

servo commands.

– RAB = R/W control and data strobe (active HIGH) for

writing to decoder registers 0 to F, reading status bit

selected via decoder register 2 and reading

Q-channel subcode

– SILD = R/W control and data strobe (active LOW) for

servo commands

The 3-wire mode is very similar to the 4-wire mode, except

that all communication to the decoder is via the servo.

• 3-wire bus mode: where:

– SCL = serial clock

Communication to the servo uses the same hardware

protocol and timing as the 4-wire mode.

– SDA = serial data

Extra servo commands exist for read and write access to

the decoder via the internal decoder interface. The internal

interface must be enabled by using the xtra_preset

command. RAB is not used and must be tied LOW;

see Fig.23

– RAB = not used, pulled LOW

– SILD = R/W control and data strobe (active LOW) for

servo commands

handbook, halfpage

MICROCONTROLLER

INTERFACE

MICROCONTROLLER

INTERFACE

(DECODER)

SAA7824

RAB = LOW

SDA

SCL

SILD

MDB502

Fig.23 Microcontroller interface for the 3-wire mode.

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floating reference

V

DDA

laser power control [register A (bank 2) and register 3 (bank 3)]

error amplifier

power amplifier

mech_sel

g

m

power-down or

laser off

V

MONITOR

EXFILTER

LASER

SENSE

laser

diode

47 nF

monitor diode

MBL442

Fig.24 Simplified block diagram of the laser driver.

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7.17.1 MICROCONTROLLER INTERFACE (4-WIRE BUS MODE)

7.17.1.1 Writing data to registers 0 to F

• V1: follows input on pin V1

• V2: follows input on pin V2

• MOTOR-OV: HIGH if the motor servo output stage

saturates.

The sixteen 4-bit programmable configuration registers,

0 to F (see Table 15), can be written to via the

microcontroller interface using the protocol shown in

Fig.25. It should be noted that SILD must be held HIGH;

A3 to A0 identifies the register number and D3 to D0 is the

data. The data is latched into the register on the

LOW-to-HIGH transition of RAB.

The status read protocol is illustrated in Fig.27. It should be

noted that SILD must be held HIGH.

7.17.1.5 Reading Q-channel subcode

To read the Q-channel subcode direct in the 4-wire bus

mode, the SUBQREADY-I signal should be selected as

the status signal. The subcode read protocol is illustrated

in Fig.28.

7.17.1.2 Writing repeated data to registers 0 to F

The same data can be repeated several times (e.g. for a

fade function) by applying extra RAB pulses as shown in

Fig.26. It should be noted that SCL must stay HIGH

between RAB pulses.

It should be noted that SILD must be held HIGH; after

subcode read starts, the microcontroller may take as long

as it wants to terminate the read operation. When enough

subcode has been read (1 to 96 bits), the reading can be

terminated by pulling RAB LOW.

7.17.1.3 Multiple writes to the new shadow registers

Some of the new shadow registers are a multiple of four

bits in length and require a number of write operations to

fill them up; see Section 7.17.5. They must be completely

filled before writing to another register, otherwise

unpredictable behaviour may result.

Alternatively, the Q-channel subcode can be read using a

servo command as follows:

• Use the read high-level status command to monitor the

subcode ready signal

• Send the read subcode command and read the required

number of bytes (up to 12)

The protocol for writing to these registers is exactly the

same as the decoder registers; see Fig.25. The write

command must be executed multiple times with the same

address content. The first four bits of data in a sequence

of write commands represent the most significant nibble of

the register, while the last four represent the least

significant nibble. The data content can change from one

write to the next without consequence.

• Send the read high-level status command; to re-enable

the decoder interface.

7.17.1.6 Behaviour of the SUBQREADY-I signal

When the CRC of the Q-channel word is good, and no

subcode is being read, the SUBQREADY-I status signal

will react as illustrated in Fig.29. When the CRC is good

and the subcode is being read, the timing in Fig.30 applies.

7.17.1.4 Reading decoder status information on SDA

There are several internal status signals, selected via

register 2, which can be made available on the SDA line:

If t₁(SUBQREADY-I status LOW to end of subcode read)

is below 2.6/n ms, then t₂= 13.1/n ms (i.e. the

microcontroller can read all subcode frames if it completes

the read operation within 2.6/n ms after the subcode is

ready). If these criteria are not met, it is only possible to

guarantee that t₃will be below 26.2/n ms (approximately).

• SUBQREADY-I: LOW if new subcode word is ready in

Q-channel register

• MOTSTART1: HIGH if motor is turning at 75% or more

of nominal speed

• MOTSTART2: HIGH if motor is turning at 50% or more

of nominal speed

If subcode frames with failed CRCs are present, the t₂

and t₃times will be increased by 13.1/n ms for each

defective subcode frame.

• MOTSTOP: HIGH if motor is turning at 12% or less of

nominal speed; can be set to indicate 6% or less

(instead of 12% or less) via register E

It should be noted that in the lock-to-disc mode ‘n’ is

replaced by ‘d’, which is the disc speed factor.

• PLL lock: HIGH if sync coincidence signals are found

2003 Oct 01

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DAC with integrated pre-amp and laser control

SAA7824

7.17.1.7 Write servo commands

The sequence for a write data command (that requires

3 data bytes) is as follows:

A write data command is used to transfer data (a number

of bytes) from the microcontroller, using the protocol

illustrated in Fig.31. The first of these bytes is the

command byte and the following are data bytes; the

number (between 1 and 7) depends on the command

byte.

1. Send START condition.

2. Send address 30H (write).

3. Write command byte.

4. Write data byte 1.

5. Write data byte 2.

It should be noted that RAB must be held LOW; the

command or data is interpreted by the SAA7824 after the

HIGH-to-LOW transition of SILD; there must be a

minimum time of 70 µs between SILD pulses.

6. Write data byte 3.

7. Send STOP condition.

It should be noted that more than one command can be

sent in one write sequence.

7.17.1.8 Writing repeated data in servo commands

The sequence for a read data command (that reads 2 data

bytes) is as follows:

The same data byte can be repeated by applying extra

SILD pulses as illustrated in Fig.32. SCL must be HIGH

between the SILD pulses.

1. Send START condition.

2. Send address 30H (write).

3. Write command byte.

4. Send STOP condition.

5. Send START condition.

6. Send address 31H (read).

7. Read data byte 1.

7.17.1.9 Read servo commands

A read data command is used to transfer data (status

information) to the microcontroller, using the protocol

shown in Fig.33. The first byte written determines the type

of command. After this byte a variable number of bytes can

be read. It should be noted that RAB must be held LOW;

after the end of the command byte (LOW-to-HIGH

transition on SILD) there must be a delay of 70 µs before

data can be read (i.e. the next HIGH-to-LOW transition on

SILD) and there must be a minimum time of 70 µs between

SILD pulses.

8. Read data byte 2.

9. Send STOP condition.

It should be noted that the timing constraints specified for

the read and write servo commands must still be adhered

to.

7.17.2 MICROCONTROLLER INTERFACE (I²C-BUS MODE)

Bytes are transferred over the interface in groups (i.e.

servo commands) of which there are two types: write data

commands and read data commands.

RAB

(microcontroller)

handbook, full pagewidth

SCL

(microcontroller)

SDA

(microcontroller)

A3

A2

A1

A0

D3

D2

D1

D0

SDA

(SAA782X)

high-impedance

MBL445

Fig.25 Microcontroller write protocol for registers 0 to F.

39

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DAC with integrated pre-amp and laser control

SAA7824

RAB

handbook, full pagewidth

(microcontroller)

SCL

(microcontroller)

SDA

(microcontroller)

A3

A2

A1

A0

D3

D2

D1

D0

SDA

(SAA782X)

high-impedance

MBL446

Fig.26 Microcontroller write protocol for registers 0 to F (repeat mode).

RAB

(microcontroller)

handbook, full pagewidth

SCL

(microcontroller)

SDA

(microcontroller)

high-impedance

STATUS

SDA

(SAA782X)

MBL443

Fig.27 Microcontroller read protocol for decoder status on SDA.

RAB

handbook, full pagewidth

(microcontroller)

SCL

(microcontroller)

CRC

OK

SDA

(SAA782X)

Q1

Q2

Q3

Qn–2 Qn–1 Qn

MBL444

STATUS

Fig.28 Microcontroller protocol for reading Q-channel subcode.

40

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DAC with integrated pre-amp and laser control

SAA7824

RAB

handbook, full pagewidth

(microcontroller)

SCL

(microcontroller)

high

CRC OK

SDA

(SAA782X)

impedance

MBL447

10.8/n ms

15.4/n ms

2.3/n

ms

READ start allowed

Fig.29 SUBQREADY-I status timing when no subcode is read.

t

2

handbook, full pagewidth

t

3

1

RAB

(microcontroller)

SCL

(microcontroller)

SDA

(SAA782X)

Q1

Q2

Q3

Qn

MBL448

Fig.30 SUBQREADY-I status timing when subcode is read.

41

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DAC with integrated pre-amp and laser control

SAA7824

handbook, full pagewidth

SILD

(microcontroller)

SCL

(microcontroller)

SDA

(microcontroller)

D7

D6

D5

D4

D3

D2

D1

D0

command or data byte

SDA

(SAA782X)

high-impedance

microcontroller write (one byte: command or data)

SILD

(microcontroller)

SDA

(microcontroller)

COMMAND

DATA1

DATA2

DATA3

MBL449

microcontroller write (full command)

Fig.31 Microcontroller protocol for write servo commands.

handbook, full pagewidth

SILD

(microcontroller)

SDA

(microcontroller)

COMMAND

DATA1

MBG413

microcontroller write (full command)

Fig.32 Microcontroller protocol for repeated data in write servo commands.

42

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CD audio decoder, digital servo and ﬁlterless

DAC with integrated pre-amp and laser control

SAA7824

SILD

handbook, full pagewidth

(microcontroller)

SCL

(microcontroller)

SD

(SAA782X)

D7

D6

D5

D1

D0

D4

D3

D2

data byte

microcontroller read (one data byte)

SILD

(microcontroller)

SD

(SAA782X)

DATA1

DATA2

DATA3

SDA

(microcontroller)

COMMAND

MBL450

microcontroller read (full command)

Fig.33 Microcontroller protocol for read servo commands.

7.17.3 DECODER AND SHADOW REGISTERS

When SHADEN1 and SHADEN2 are both set to logic 0

(decoder register F set to XX00) all subsequent addresses

are decoded by the main decoder registers again.

To maintain compatibility with the SAA732x series,

decoder registers 0 to F and the shadow registers are

largely unchanged. However, to control the extra

functionality of SAA7824, the shadow registers have been

extended to include new shadow registers.

Access to decoder register F is always enabled so that

SHADEN1 and SHADEN2 can be set or reset as required.

The SHADEN bits and subsequent shadow registers are

programmed identically to the main decoder registers,

i.e. they can be directly programmed when using the

SAA7824 in 4-wire mode or programmed via the servo

interface when using 3-wire or I²C-bus modes. The main

decoder registers are given in Table 16 and the shadow

registers in Table 18. Details of the new shadow registers

can be found in Tables 19 to 22.

All shadow registers are accessed by using the two LSBs

(bits 0 and 1) of decoder register F. These bits are called

SHADEN1 and SHADEN2 respectively. These bits are

decoded according to Table 15.

This two bit encoding allows the use of three shadow

register banks; bank 1 (SAA732X shadow registers), and

banks 2 and 3 (new shadow registers). Only the four

addresses 3, 7, A and C are implemented in any one

bank. Any other addresses sent while accessing any of the

shadow register banks are invalid and have no effect.

2003 Oct 01

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DAC with integrated pre-amp and laser control

SAA7824

Table 15 Shadow register accessibility

SHADEN2

SHADEN1

FUNCTION

access decoder registers 0 to F

INITIAL

0

1

0

1

0

1

reset

access SAA732X shadow registers (bank 1)

access new shadow registers (bank 2)

access new shadow registers (bank 3)

−

7.17.4 SUMMARY OF FUNCTIONS CONTROLLED BY DECODER REGISTERS 0 TO F

Table 16 Registers 0 to F

REGISTER

ADDRESS

DATA

FUNCTION

INITIAL⁽¹⁾

0

0000

X000

X010

X001

X100

X101

0XXX

1XXX

mute

reset

(Fade and

attenuation)

attenuate

full-scale

step-down

step-up

−

0

EBU mute inactive

EBU mute active

reset

−

EBU mute (for

M1 version

only)

1

0001

X000

X001

X010

X011

X100

X101

X111

X110

1XXX

0XXX

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

motor off mode

reset

(Motor mode)

motor stop mode 1

motor stop mode 2

motor start mode 1

motor start mode 2

motor jump mode

−

motor play mode

−

motor jump mode 1

anti-windup active

anti-windup off

−

reset

2

0010

status = SUBQREADY-I

status = MOTSTART1

status = MOTSTART2

status = MOTSTOP

status = PLL lock

reset

(Status control)

−

status = V1

status = V2

status = MOTOR-OV

status = FIFO overﬂow

status = shock detect

status = latched shock detect

status = latched shock detect reset

unavailable via

the I²C-bus or

3-wire mode

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DAC with integrated pre-amp and laser control

SAA7824

REGISTER

ADDRESS

DATA

FUNCTION

I²S-bus; CD-ROM mode

INITIAL⁽¹⁾

3

0011

1010

1011

1100

1111

1110

0000

0011

0010

0100

0111

0110

0000

0001

0010

0011

0100

0101

0110

0111

XX00

XX01

XX10

XX11

00XX

01XX

10XX

XX00

XX01

XX10

XX11

00XX

01XX

10XX

11XX

−

(DAC output)

EIAJ; CD-ROM mode

I²S-bus; 18-bit; 4f_smode

I²S-bus; 18-bit; 2f_smode

I²S-bus; 16-bit; f_smode

EIAJ; 16-bit; 4f_s

−

reset

−

EIAJ; 16-bit; 2f_s

−

EIAJ; 16-bit; f_s

−

EIAJ; 18-bit; 4f_s

−

EIAJ; 18-bit; 2f_s

−

EIAJ; 18-bit; f_s

−

4

0100

motor gain G = 3.2

reset

(Motor gain)

motor gain G = 4.0

−

motor gain G = 6.4

−

motor gain G = 8.0

−

motor gain G = 12.8

motor gain G = 16.0

motor gain G = 25.6

motor gain G = 32.0

motor f₄= 0.5 × n Hz

motor f₄= 0.7 × n Hz

motor f₄= 1.4 × n Hz

motor f₄= 2.8 × n Hz

motor f₃= 0.85 × n Hz

motor f₃= 1.71 × n Hz

motor f₃= 3.42 × n Hz

motor power maximum 37%

motor power maximum 50%

motor power maximum 75%

motor power maximum 100%

MOTO1, MOTO2 pins 3-state

motor PWM mode

−

5

0101

reset

(Motor

bandwidth)

−

reset

−

6

0110

reset

(Motor output

conﬁguration)

−

reset

−

motor PDM mode

−

motor CDV mode

−

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DAC with integrated pre-amp and laser control

SAA7824

REGISTER

ADDRESS

DATA

FUNCTION

INITIAL⁽¹⁾

7

0111

XX00

interrupt signal from servo only at STATUS

reset

(DAC output

and STATUS pin

control)

XX10

status bit from decoder status register or DC

offset information at STATUS pin [see also

new shadow register C (bank 3)]

−

X0XX

X1XX

0XXX

1XXX

DAC data normal value

reset

DAC data inverted value

−

reset

−

left channel ﬁrst at DAC (WCLK normal)

right channel ﬁrst at DAC (WCLK inverted)

see Table 16

8

−

(PLL loop ﬁlter

bandwidth)

9

(PLL

equalization)

1001

1010

0011

0001

0010

0100

0101

XX0X

XX1X

X0X0

X0X1

X1X0

X1X1

0XXX

1XXX

X000

X010

X011

00XX

10XX

XXX1

XXX0

PLL loop ﬁlter equalization

PLL 30 ns over-equalization

PLL 15 ns over-equalization

PLL 15 ns under-equalization

PLL 30 ns under-equalization

EBU data before concealment

EBU data after concealment and fade

Level II clock accuracy (<1000 ppm)

Level I clock accuracy (<50 ppm)

Level III clock accuracy (>1000 ppm)

EBU off - output LOW

reset

−

A

(EBU output)

reset

−

ﬂags in EBU off

reset

−

ﬂags in EBU on

B

1011

1100

standby 1: ‘CD-STOP’ mode

standby 2: ‘CD-PAUSE’ mode

operating mode

reset

−

(speed control)

−

single-speed mode

reset

−

double-speed mode

C

external off-track signal input at V1

−

(versatile pins

interface and

KILL function)

internal off-track signal used (V1 may be

read via status)

reset

XX0X

XX1X

00XX

01XX

0XXX

stereo KILL

mono KILL

V3 = 0

−

reset

−

V3 = 1

EBU mute

mute type = soft mute audio; only available

reset

mode (for M1

version only)

at 1× speed

1XXX

mute type = ROM hard mute; available at 1×,

2× and 4× speed

−

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DAC with integrated pre-amp and laser control

SAA7824

REGISTER

ADDRESS

DATA

FUNCTION

INITIAL⁽¹⁾

D

1101

0000

XX01

XX10

XX11

01XX

4-line motor (using V4 and V5)

Q-to-W subcode at V4

V4 = 0

−

(versatile pins

interface)

−

V4 = 1

reset

−

de-emphasis signal at V5, no internal

de-emphasis ﬁlter

10XX

11XX

XXX0

XXX1

XX0X

XX1X

X0XX

X1XX

0XXX

1XXX

X0XX

X1XX

0XXX

1XXX

XX00

V5 = 0

−

reset

−

V5 = 1

E

1110

motor brakes to 12%

motor brakes to 6%

lock-to-disc mode disabled

lock-to-disc mode enabled

audio features disabled

audio features enabled

quad-speed mode disabled

quad-speed mode enabled

subcode interface off

subcode interface on

4-wire subcode

reset

−

reset

−

F

1111

reset

−

(subcode

interface and

shadow register

enable)

reset

−

3-wire subcode

SHADEN bits = 00; shadow registers not

reset

enabled; addresses will be decoded by main

decoder registers

XX01

SHADEN bits = 01; SAA732X shadow

registers (bank 1) enabled; all subsequent

addresses will be decoded by shadow

register (bank 1), not decoder registers

−

XX10

XX11

SHADEN bits = 10; new shadow registers

(bank 2) enabled; all subsequent addresses

will be decoded by shadow register (bank 2)

−

SHADEN bits = 11; new shadow registers

(bank 3) enabled; all subsequent addresses

will be decoded by shadow register (bank 3)

Note

1. The initial column shows the Power-on reset state.

2003 Oct 01

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DAC with integrated pre-amp and laser control

SAA7824

Table 17 Loop ﬁlter bandwidth

FUNCTION

LOOP

BANDWIDTH

(Hz)

INTERNAL

BANDWIDTH

(Hz)

LOW-PASS

BANDWIDTH

(Hz)

REGISTER ADDRESS

DATA

INITIAL⁽¹⁾

8

1000

0000

0001

0010

0100

0101

0110

1000

1001

1010

1100

1101

1110

1640 × n

3279 × n

6560 × n

1640 × n

3279 × n

6560 × n

1640 × n

3279 × n

6560 × n

1640 × n

3279 × n

6560 × n

525 × n

263 × n

8400 × n

16800 × n

33600 × n

8400 × n

16800 × n

33600 × n

8400 × n

16800 × n

33600 × n

8400 × n

16800 × n

33600 × n

−

(PLL loop

ﬁlter

bandwidth)

131 × n

−

1050 × n

525 × n

−

263 × n

−

2101 × n

1050 × n

525 × n

−

reset

−

4200 × n

2101 × n

1050 × n

−

Note

1. The initial column shows the Power-on reset state.

7.17.5 SUMMARY OF FUNCTIONS CONTROLLED BY SHADOW REGISTERS

Table 18 Bank 1 shadow register settings (single write)

SHADEN

BITS

SHADOW

REGISTER

ADDRESS

DATA

FUNCTION

INITIAL

01

(bank 1)

3

0011

XX00

XX01

X0XX

X1XX

select CLK4 on CLK4/12 output

select CLK12 on CLK4/12 output

enable CLK16 output pin

reset

−

control of

versatile and

clock pins

reset

−

set CLK16 output pin to

high-impedance

0XXX

1XXX

0000

set V3 output pin to high-impedance

enable V3 output pin

reset

−

7

0111

use external DAC or route audio data

back into onboard DAC

(loopback mode)

reset

control of

onboard

DAC

0010

route audio data directly into onboard

DAC (non-loopback mode)

−

7

XXX0

XXX1

EBU mute function not bypassed

EBU mute function bypassed

reset

EBU mute

bypass

control (for

M1 version

only)

−

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SAA7824

SHADEN

BITS

SHADOW

REGISTER

ADDRESS

DATA

FUNCTION

voltage mode: 20 mV

INITIAL

01

(bank 1)

A

signal

magnitude

control for

diodes D1

to D4

1010

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

−

voltage mode: 25 mV

voltage mode: 30 mV

voltage mode: 40 mV

voltage mode: 60 mV

voltage mode: 75 mV

voltage mode: 100 mV

voltage mode: 120 mV

voltage mode: 150 mV

voltage mode: 200 mV

voltage mode: 270 mV

voltage mode: 350 mV

voltage mode: 450 mV

voltage mode: 600 mV

voltage mode: 720 mV

voltage mode: 960 mV

voltage mode: 20 mV

voltage mode: 25 mV

voltage mode: 30 mV

voltage mode: 40 mV

voltage mode: 60 mV

voltage mode: 75 mV

voltage mode: 100 mV

voltage mode: 120 mV

voltage mode: 150 mV

voltage mode: 200 mV

voltage mode: 270 mV

voltage mode: 350 mV

voltage mode: 450 mV

voltage mode: 600 mV

voltage mode: 720 mV

voltage mode: 960 mV

−

(LF only)

−

reset

−

01

(bank 1)

C

signal

magnitude

control for

diodes

1100

−

R1 and R2

−

(LF only)

−

reset

2003 Oct 01

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DAC with integrated pre-amp and laser control

SAA7824

Table 19 Bank 2 new shadow register settings (single write)

SHADEN

BITS

SHADOW

REGISTER

ADDRESS

DATA

FUNCTION

INITIAL

10

(bank 2)

3

0011

XXX0

XXX1

analog front-end active

reset

Power-down

control

analog front-end powered

down

−

XX0X

XX1X

buffer ampliﬁer on

reset

buffer ampliﬁer off (power

saving)

−

X0XX

X1XX

0XXX

1XXX

DAC active

reset

−

DAC powered down

normal mode

3

reset

−

DAC output

mode

current mode (bypass

internal I-to-V converters)

7

0111

XX10

voltage mechanism:

reset

mechanism and

voltage

reference

selection

1.65 × V_DDA

-------------------------------

3.3 V

XX11

Voltage mechanism:

−

2.5 × V_DDA

----------------------------

3.3 V

X0XX

X1XX

0XXX

150 mV mechanism

180 mV mechanism

reset

−

7

ﬂag all data (CRC pass and

fail)

reset

CD-text control

1XXX

ﬂag only data that passes

the CRC

−

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SAA7824

SHADEN

BITS

SHADOW

REGISTER

ADDRESS

DATA

FUNCTION

INITIAL

10

(bank 2)

A

1010

XXX0

approximately 58% (laser

power control 2 = 0)

reset

laser power

control 1

approximately 72% (laser

power control 2 = 1)

see shadow register 3

(bank 3)

XXX1

XX0X

approximately 86% (laser

power control 2 = 0)

−

approximately 100% (laser

power control 2 = 1)

see shadow register 3

(bank 3)

A

bypass PLL (external clock

source)

−

clock source

XX1X

X0XX

X1XX

0XXX

1XXX

XX00

XX01

XX10

XX11

00XX

01XX

10XX

11XX

select and enable PLL

disable silence injection

enable silence injection

internal KILL

reset

A

reset

KILL control

−

reset

loop-back KILL

−

C

1100

settling time = 354 µs

settling time = 1 ms

settling time = 2 ms

settling time = 10 ms

no dither selected

AC dither only

reset

DC offset

measurement

times

−

C

−

upsampler

dither selection

−

DC dither only

−

AC and DC dither selected

reset

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SAA7824

Table 20 Bank 3 new shadow register settings (single write)

SHADEN

BITS

SHADOW

REGISTER

ADDRESS

DATA

FUNCTION

select D1

INITIAL

11

(bank 3)

3

0011

X000

X001

X010

X011

X100

X101

X110

X111

0XXX

reset

diode selection

for DC offset

measurement

select D1

select D2

select D3

select D4

select R1

select R2

select D1

−

3

60% (laser power control

1 = 0)

reset

laser power

control 2

87% (laser power control

1 = 1)

see shadow register A

(bank 2)

1XXX

73% (laser power control

1 = 0)

−

100% (laser power control

1 = 1)

see shadow register A

(bank 2)

C

1100

XXX0

equalizer disabled and

powered-down

reset

enable

equalizer

XXX1

000X

equalizer enabled

−

C

STATUS pin outputs

decoder status register

information

reset

STATUS pin

control

001X

010X

STATUS pin outputs DC

offset ready ﬂag

−

STATUS pin outputs DC

offset value

Table 21 Bank 3 new shadow register settings (multiple write)

SHADOW

REGISTER

SIZE (DATA

NIBBLES)

SHADEN BITS

ADDRESS

REGISTER ELEMENTS⁽¹⁾

11

(bank 3)

7

0111

9

<r2_off> <r1_off> <d4_off> <d3_off>

<d2_off> <d1_off>

DC cancellation

levels

A

1010

4

<hp_ﬁlter_sel> <eq_speed_sel>

<slicer_slew> <hf_gain>

analog FE

control

Note

1. Register elements are described in Tables 26 and 27.

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Product speciﬁcation

CD audio decoder, digital servo and ﬁlterless

DAC with integrated pre-amp and laser control

SAA7824

Table 22 Multiple write register element description

SHADOW

ELEMENT NAME BIT NUMBERS

REGISTER

DESCRIPTION

7

<d1_off>

<d2_off>

<5:0>

<11:6>

<17:12>

<23:18>

<29:24>

<35:30>

<3:0>

DC offset level for D1 (reset value = 000000)

DC offset level for D2 (reset value = 000000)

DC offset level for D3 (reset value = 000000)

DC offset level for D4 (reset value = 000000)

DC offset level for R1 (reset value = 000000)

DC offset level for R2 (reset value = 000000)

see Table 23

(bank 3)

<d3_off>

<d4_off>

<r1_off>

<r2_off>

A

<hf_gain>

(bank 3)

<slicer_slew>

<eq_speed_sel>

<hp_ﬁlter_sel>

<7:4>

see Table 24

<9:8>

equaliser operating speed: 00 = 1× (reset); 01 = 2×; 10 = 4×

see Table 25

<15:10>

Table 23 HF gain

Table 24 Slicer threshold tracking slew rate (ISlice code

to current conversion)

DATA

DESCRIPTION

DATA

CURRENT (µA)

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

voltage mode = 1.11 V

voltage mode = 952 mV

voltage mode = 588 mV

voltage mode = 392 mV

voltage mode = 1.11 V

voltage mode = 952 mV

voltage mode = 588 mV

voltage mode = 392 mV

voltage mode = 303 mV

voltage mode = 200 mV

voltage mode = 157 mV

voltage mode = 107 mV

voltage mode = 79 mV

voltage mode = 54 mV

voltage mode = 39 mV

voltage mode = 27 mV

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

10 (reset)

10

20

30

50

60

70

80

100

110

120

130

150

160

170

180

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DAC with integrated pre-amp and laser control

SAA7824

Table 25 High-pass ﬁlter frequency cut-off level (lowest roll-off)

NOMINAL FREQUENCY

(kHz)

PERCENTAGE

DEVIATION

ACTUAL FREQUENCY

(kHz)

DATA

000000

010000

001000

011000

000100

010100

001100

000010

010010

001010

011010

000110

010110

001110

000001

010001

001001

011001

000101

010101

001101

000011

010011

001011

011011

000111

010111

001111

10

20

30

40

−37.5%

−28.2%

−17.6%

−9.2%

0%

6.367 (reset)

7.31

8.395

9.247

10.186

11.066

12.023

12.706

14.588

16.520

18.45

+8.6%

+18%

−37.5%

−28.2%

−17.6%

−9.2%

0%

20.324

22.080

23.988

18.967

21.777

24.660

27.542

30.339

32.961

35.318

25.003

29.107

32.961

36.307

39.994

43.451

47.206

+8.6%

+18%

−37.5%

−28.2%

−17.6%

−9.2%

0%

+8.6%

+18%

−37.5%

−28.2%

−17.6%

−9.2%

0%

+8.6%

+18%

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DAC with integrated pre-amp and laser control

SAA7824

7.17.6 SUMMARY OF SERVO COMMANDS

A list of the servo commands is given in Table 26. These are fully compatible with the SAA732X.

Table 26 Servo commands

COMMANDS

CODE

BYTES

PARAMETERS

Write commands

Write_focus_coefs1

17H

27H

7

<foc_parm3> <foc_int> <ramp_incr> <ramp_height>

<ramp_offset> <FE_start> <foc_gain>

Write_focus_coefs2

<defect_parm> <rad_parm_jump> <vel_parm2>

<vel_parm1> <foc_parm1> <foc_parm2> <CA_drop>

Write_focus_command

Focus_gain_up

33H

42H

62H

57H

3

2

7

<foc_mask> <foc_stat> <FFH>

<foc_gain> <foc_parm1>

Focus_gain_down

Write_radial coefs

<rad_length_lead> <rad_int> <rad_parm_play>

<rad_pole_noise> <rad_gain> <sledge_parm2>

<sledge_parm_1>

Preset_Latch

Radial_off

81H

C1H

C3H

C5H

1

3

5

<chip_init>

‘1CH’

Radial_init

Short_jump

Long_jump

‘3CH’

<tracks_hi> <tracks_lo> <rad_stat>

<brake_dist> <sledge_U_max> <tracks_hi>

<tracks_lo> <rad_stat>

Steer_sledge

B1H

93H

D1H

A2H

1

3

1

2

<sledge_level>

Preset_init

Write_decoder_reg⁽¹⁾

<re_offset> <re_gain> <sum_gain>

<decoder_reg_data>

Write_parameter

<param_ram_addr> <param_data>

Read commands

Read_Q_subcode⁽¹⁾⁽²⁾

Read_status

0H

up to 12

up to 5

<Q_sub1 to 10> <peak_l> <peak_r>

70H

<foc_stat> <rad_stat> <rad_int_lpf> <tracks_hi>

<tracks_lo>

Read_hilevel_status⁽³⁾

Read_aux_status

E0H

F0H

up to 4

up to 3

<re_offset> <re_gain> <sum_gain>

Notes

1. These commands are only available when the decoder interface is enabled.

2. <peak_I> and <peak_r> bytes are clocked out LSB first.

3. Decoder status flag information in, <dec_stat> is only valid when the internal decoder interface is enabled.

2003 Oct 01

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DAC with integrated pre-amp and laser control

SAA7824

7.17.7 SUMMARY OF SERVO COMMAND PARAMETERS

Table 27 Servo command parameters

RAM

PARAMETER

AFFECTS

POR VALUE

DETERMINES

end of focus lead

ADDRESS

foc_parm_1

−

focus PID

−

defect detector enabling

focus low-pass

foc_parm_2

foc_parm_3

−

focus PID

−

focus error normalizing

focus lead length

minimum light level

foc_int

14H

15H

12H

16H

18H

−

focus PID

focus ramp

radial PID

radial jump

−

70H

−

focus integrator crossover frequency

focus PID loop gain

foc_gain

CA_drop

sensitivity of dropout detector

asymmetry of focus ramp

peak-to-peak value of ramp voltage

slope of ramp voltage

ramp_offset

ramp_height

ramp_incr

−

FE_start

19H

28H

29H

1CH

1EH

2AH

27H

1FH

32H

48H

49H

−

minimum value of focus error

end of radial lead

rad_parm_play

rad_pole_noise

rad_length_lead

rad_int

−

radial low-pass

−

length of radial lead

−

radial integrator crossover frequency

radial loop gain

rad_gain

70H

−

rad_parm_jump

vel_parm1

vel_parm2

speed_threshold

hold_mult

ﬁlter during jump

−

PI controller crossover frequencies

jump pre-deﬁned proﬁle

maximum speed in fastrad mode

electronic damping

−

00H

sledge bandwidth during jump

brake_dist_max

21H

radial jump

−

maximum sledge distance allowed in

fast actuator steered mode

sledge_long_brake

sledge_Umax

58H

−

radial jump

sledge

FFH

brake distance of sledge

voltage on sledge during long jump

voltage on sledge when steered

sledge integrator crossover frequency

sledge low-pass frequencies

sledge gain

−

sledge_level

−

sledge

sledge_parm_1

sledge_parm_2

36H

17H

sledge

sledge operation mode

pulse width

sledge_pulse1

sledge_pulse2

defect_parm

46H

64H

−

pulsed sledge

defect detector

Watchdog

−

pulse height

defect detector setting

playwatchtime

jumpwatchtime

54H

57H

radial on-track Watchdog time

radial jump Watchdog time-out

Watchdog

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DAC with integrated pre-amp and laser control

SAA7824

RAM

ADDRESS

PARAMETER

radcontrol

AFFECTS

POR VALUE

DETERMINES

59H

Watchdog

−

enable/disable automatic radial off

feature

chip_init

−

set-up

−

enable/disable decoder interface

laser on/off

xtra_preset

4AH

38H

RA, FO and SL PDM modulating

frequency

fast jumping circuit on/off

decoder part commands

cd6cmd

4DH

decoder

interface

−

interrupt_mask

seq_control

53H

42H

5EH

5FH

60H

61H

62H

63H

68H

STATUS pin

autosequencer

−

enabled interrupts

autosequencer control

focus start time

focus_start_time

motor_start_time1

motor_start_time2

radial_init_time

brake_time

motor start 1 time

motor start 2 time

radial initialization time

brake time

RadCmdByte

osc_inc

radial command byte

AGC control

focus/radial

AGC

frequency of injected signal

phase shift of injected signal

phase_shift

level1

67H

69H

6AH

6CH

focus/radial

AGC

focus/radial

AGC

−

amplitude of signal injected

focus/radial gain

level2

focus/radial

AGC

agc_gain

focus/radial

AGC

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DAC with integrated pre-amp and laser control

SAA7824

8

SUMMARY OF SERVO COMMAND PARAMETERS

VALUES

Table 29 foc_parm2 parameter: focus low-pass start

frequency, focusing system

Table 28 foc_parm1 parameter: focus end lead

foc_parm2

Focus low-pass start

frequency, defect detector, offtrack detector

foc_pole_noise value

frequency f₄kHz

foc_parm1

(binary)

Focus end lead

xxx1 1100

xxx1 1000

xxx0 0000

xxx0 1000

xxx0 1100

xxx1 1101

xxx1 1001

xxx0 0001

xxx0 1001

xxx0 1101

xxx1 1110

xxx1 1010

xxx0 0010

xxx0 1010

xxx0 1110

xxx1 1111

xxx1 1011

xxx0 0011

xxx0 1011

detector_arr

xx1x xxxx

xx0x xxxx

3.90

4.55

foc_pole_lead value

frequency f₃kHz

(binary)

xxx1 1100

xxx1 1000

xxx0 0000

xxx0 1000

xxx0 1100

xxx1 1101

xxx1 1001

xxx0 0001

xxx0 1001

xxx0 1101

xxx1 1110

xxx1 1010

xxx0 0010

xxx0 1010

xxx0 1110

xxx1 1111

xxx1 1011

xxx0 0011

xxx0 1011

defect_det_sw

x11x xxxx

1.97

2.29

5.19

5.82

2.61

6.46

2.94

7.72

3.26

8.98

3.90

10.22

4.55

11.46

5.19

12.69

5.82

15.13

6.46

17.54

7.72

19.93

8.98

22.28

10.22

11.46

12.69

15.13

17.54

19.93

22.28

Defect detector

25.40

30.26

35.08

39.86

44.56

Focusing system

single foucault

double foucault

defect detector does not

inﬂuence focus and radial

x10x xxxx

x00x xxxx

focus hold on defect

detector

focus and radial hold on

defect detector

x01x xxxx

otd_select

0xxx xxxx

1xxx xxxx

undeﬁned, reserved

Offtrack detector

ON track active 1

ON track active 0

2003 Oct 01

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Philips Semiconductors

Product speciﬁcation

CD audio decoder, digital servo and ﬁlterless

DAC with integrated pre-amp and laser control

SAA7824

Table 30 foc_parm3 parameter: focus lead length, CA

Table 32 FE_start parameter: minimum threshold for

start level for focus acquisition

focus start

foc_parm3

Minimum threshold for

FE_start value (decimal)

(d₁− d₂)/(d₁+ d₂)

Focus lead length f₃/f₂

foc_lead_length value

0

always

1/127

(binary)

1

0000 xxx1

1000 xxx1

0100 xxx1

1100 xxx1

0010 xxx1

1010 xxx1

0110 xxx1

1110 xxx1

0001 xxx1

1001 xxx1

0101 xxx1

1101 xxx1

0011 xxx1

1011 xxx1

0111 xxx1

1111 xxx1

CA_start value (binary)

xxxx 000x

64

32

2

i

2/127

i/127

21.3

16

64

64/127

65...127

127

65 to 127/127

continuous ramping

not allowed

12.8

10.7

9.1

128...255

8

Table 33 foc_int_strength parameter: focus integrator

7.1

strength

6.4

foc_int_strength value

(decimal)

Focus integrator

strength f₅Hz

5.8

5.3

0

integrator hold

4.9

1

1.2

2.4

4.6

2

4.3

i

1.2 × i

25

4

21

CA_min

0.0225

0.03

0.045

0.06

0.09

0.125

0.18

1.0

22...255

undeﬁned

xxxx 001x

Table 34 foc_gain parameter: focus gain

xxxx 010x

foc_gain value (decimal)

G

xxxx 011x

1

2

2048

1024

xxxx 100x

xxxx 101x

3

i

2048/3

2048/i

xxxx 110x

xxxx 111x

255

0

2048/255

undeﬁned

Table 31 CA_drop parameter: CA level for dropout

detection

CA_drop value (binary)

CA_min

xxx0 0000

xxx0 0100

xxx0 1000

xxx0 1100

xxx1 0000

xxx1 0100

xxx1 1000

xxx1 1100

0.0225

0.03

0.045

0.06

0.09

0.125

0.18

1.0

2003 Oct 01

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DAC with integrated pre-amp and laser control

SAA7824

Table 35 rad_pole_noise parameter: radial low-pass start

Table 36 rad_lead_length parameter: radial lead length

frequency

rad_lead_length rad_lead_length

Radial lead

length f₃/f₂

rad_pole_noise value

(binary)

Radial low-pass start

frequency f₄kHz

value (binary)

value (hex)

0000 xxxx

1000 xxxx

0100 xxxx

1100 xxxx

0010 xxxx

1010 xxxx

0110 xxxx

1110 xxxx

0001 xxxx

1001 xxxx

0101 xxxx

1101 xxxx

0011 xxxx

1011 xxxx

0111 xxxx

1111 xxxx

0x

8x

4x

Cx

2x

Ax

6x

Ex

1x

9x

5x

Dx

3x

Bx

7x

Fx

128

64

1101 1100

1011 1000

1010 0000

1010 1000

1000 1100

1001 1101

1001 1001

0100 0001

0100 1001

0100 1101

0101 1110

0101 1010

0100 0010

0100 1010

xxx0 1110

xxx1 1111

xxx1 1011

xxx0 0011

xxx0 1011

3.90

4.55

42.7

32

5.19

5.82

25.6

21.3

18.3

16

6.46

7.72

8.98

10.22

11.46

12.69

15.13

17.54

19.93

22.28

25.40

30.26

35.08

39.86

44.56

14.2

12.8

11.6

10.7

9.8

9.1

8.5

8

2003 Oct 01

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DAC with integrated pre-amp and laser control

SAA7824

Table 37 rad_parm_play, rad_parm_jump parameters:

Table 39 rad_int_strength parameter: radial integrator

radial end lead frequency

strength

rad_parm_play rad_parm_play Radial end lead

rad_int_strength value

(decimal)

Radial integrator

strength f₅Hz

rad_parm_jump rad_parm_jump

frequency f₃

kHz

value (binary)

value (hex)

0

1

integrator hold

0.3

1101 1100

1101 1000

1100 0000

1100 1000

1100 1100

1101 1101

1001 1001

1010 0001

1010 1001

1010 1101

1001 1110

0101 1010

0100 0010

0100 1010

1000 1110

0101 1111

0101 1011

0100 0011

0100 1011

DC

D8

C0

C8

CC

DD

99

1.97

2.29

2

0.6

2.61

i

0.31 × i

79.05

2.94

255

3.26

Table 40 Sledge_parm1 parameter: sledge integrator

bandwidth, shock ﬁlter (low-pass, high-pass

selection); RAM address 36H

3.90

4.55

A1

A9

AD

9E

5A

42

5.19

sledge_parm1

Sledge integrator f₁Hz

sledge_int

5.82

6.46

x00x xxxx

x10x xxxx

x01x xxxx

x11x xxxx

integrator disabled

7.72

0.15

0.31

0.45

8.98

10.22

11.46

12.69

15.13

17.54

19.93

22.28

4A

8E

5F

5B

43

4B

Table 38 rad_gain parameter: radial PID gain

Radial PID gain

rad_gain value (decimal)

G

1

2

256

256/2

3

256/3

i

256/i

255

0

256/255

undeﬁned

2003 Oct 01

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CD audio decoder, digital servo and ﬁlterless

DAC with integrated pre-amp and laser control

SAA7824

Table 41 sledge_parm2 parameter: sledge gain,

low-pass frequencies, operation mode; RAM

address 17H

Table 42 sledge_pulse1 parameter: sledge pulse high

time, low time; RAM address 46H

sledge_pulse1

Hex

Time low ms

sledge_parm2

Sledge gain G_S

sledge_gain

time_lo

0000 xxxx

0001 xxxx

0010 xxxx

0011 xxxx

0100 xxxx

0101 xxxx

0110 xxxx

0111 xxxx

1000 xxxx

1001 xxxx

1010 xxxx

1011 xxxx

1100 xxxx

1101 xxxx

1110 xxxx

1111 xxxx

time_hi

0x

1x

2x

3x

4x

5x

6x

7x

8x

9x

Ax

Bx

Cx

Dx

Ex

Fx

0

0xxx x000

0xxx x001

0xxx x010

0xxx x011

0xxx x100

0xxx x101

0xxx x110

0xxx x111

1xxx x000

1xxx x001

1xxx x010

1xxx x011

1xxx x100

1xxx x101

1xxx x110

1xxx x111

sledge_low_pass

0.218

0.281

0.436

0.562

0.875

1.125

1.750

2.250

3.500

4.500

7.000

9.000

14.00

18.00

28.00

36.00

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

Time high ms

Sledge low-pass

frequency f₂Hz

xxxx 0000

xxxx 0001

xxxx 0010

xxxx 0011

xxxx 0100

xxxx 0101

xxxx 0110

xxxx 0111

xxxx 1000

xxxx 1001

xxxx 1010

xxxx 1011

xxxx 1100

xxxx 1101

xxxx 1110

xxxx 1111

x0

x1

x2

x3

x4

x5

x6

x7

x8

x9

xA

xB

xC

xD

xE

xF

0

2

x00x 0xxx

x10x 0xxx

5.0

4

10.1

6

x01x 0xxx

15.3

8

x11x 0xxx

20.5

10

12

14

16

18

20

22

24

26

28

30

x00x 1xxx

0.3

x10x 1xxx

0.6

x01x 1xxx

0.9

1.2

x11x 1xxx

sledge_op_mode

xxx0 0xxx

Sledge operation mode

PI mode operation

xxx0 1xxx

pulsed mode operation,

microcontroller controlled

xxx1 1xxx

pulsed mode operation,

automatic mode

2003 Oct 01

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DAC with integrated pre-amp and laser control

SAA7824

Table 43 sledge_pulse2 parameter: sledge pulse height;

vel_parm1

Gain constant

for short jump

K_v

RAM address 64H

Hex

vel_prop

sledge_pulse2

Hex

Pulse height

xxxx 0011

x3

30.0/K_v

i × 10.0/K_v

150.0/K_v

0111 1111

78

full-scale,

positive

i

....

40

xxxx 1111

xF

0100 0000

half-scale,

positive

Table 45 vel_parm2 parameter: time constant during

sledge access/actuator access, minimum jump

speed during short jump; RAM address 32H

a

level = a/7F,

positive

vel_parm2

Deceleration

time fast

actuator

0000 0000

....

00

....

80

zero

Deceleration

time sledge

steered ms

Hex

vel_setp

(binary)

1000 0000

full-scale,

negative

steered ms

0000 xxxx

1000 xxxx

0100 xxxx

1100 xxxx

0010 xxxx

1010 xxxx

0110 xxxx

1110 xxxx

0001 xxxx

1001 xxxx

0101 xxxx

1101 xxxx

0011 xxxx

1011 xxxx

0111 xxxx

1111 xxxx

vel_min

0x

8x

4x

Cx

2x

Ax

6x

Ex

1x

9x

5x

Dx

3x

Bx

7x

Fx

7.5

8.2

7.5

8.2

Table 44 vel_parm1 parameter: gain constant for short

jump, integrator cross-over frequency during

jump; RAM address 1FH

9

9.7

vel_parm1

vel_prop

Gain constant

for short jump

K_v

10.5

11.2

12.5

14

10.5

11.2

12.5

14

Hex

0000 xxxx

1000 xxxx

0100 xxxx

1100 xxxx

0010 xxxx

1010 xxxx

0110 xxxx

1110 xxxx

0001 xxxx

1001 xxxx

0101 xxxx

1101 xxxx

0011 xxxx

1011 xxxx

0111 xxxx

1111 xxxx

vel_int

0x

8x

4x

Cx

2x

Ax

6x

Ex

1x

9x

5x

Dx

3x

Bx

7x

Fx

0.1875

0.4375

0.6875

0.9375

1.1875

1.4375

1.6875

1.9375

2.1875

2.4375

2.6875

2.9375

3.1875

3.4375

3.6875

3.9375

15.5

16.5

20.7

25

15.5

16.5

20.7

25

31.2

41

31.2

41

63

128

V₁minimum jump speed

kHz

xxxx 0000

xxxx 0001

xxxx 0010

xxxx 0011

xxxx 0100

xxxx 0101

xxxx 0110

xxxx 0111

xxxx 1xxx

x0

x1

x2

x3

x4

x5

x6

x7

0.0

1.0

2.0

3.0

4.0

Integrator

cross-over

frequency

5.0

6.0

7.0

during jump f₀

undeﬁned

xxxx 0000

xxxx 0001

xxxx 0010

x0

x1

x2

integrator hold

10.0/K_v

20.0/K_v

2003 Oct 01

63

Philips Semiconductors

Product speciﬁcation

CD audio decoder, digital servo and ﬁlterless

DAC with integrated pre-amp and laser control

SAA7824

Table 46 brake_dist_max parameter: maximum sledge

distance allowed in fast actuator steered mode;

RAM address 21H

Table 49 jumpwatchtime parameter: radial jump

watchdog readout time difference; RAM

address 57H

Maximum sledge

Radial jump watchdog

readout time difference

ms

brake_dist_max value

(decimal)

distance allowed in fast

actuator steered mode,

number of tracks

jumpwatchtime

80H to FFH

none

0

0...127

−1

not allowed

1 × 16

2 × 16

....

0H

1H

i

0.25

i × 0.25

32

−2

....

7FH

−i

i × 16

Table 50 playwatchtime parameter: radial play watchdog

....

maximum time-out; RAM address 54H

−127

−128

127 × 16

128 × 16

Radial play watchdog

playwatchtime

maximum time-out ms

Table 47 sledge_Umax parameter: voltage on sledge

80H

81H

82H

i

0

during long jump

0.5

sledge_Umax (decimal)

voltage on sledge

1

(i − 80H) × 0.5

64

127

i

255/256 × V_DD

(i + 128)/256 × V_DD

0.5 × V_DD

00H

j

0

(j + 80H) × 0.5

128

−1

−i

(128 − 1)/256 × V_DD

(−i + 128)/256 × V_DD

0

7fH

Table 51 radcontrol parameter: automatic radial servo

−128

switch-off control; RAM address 59H

Table 48 sledge_level parameter: voltage on sledge

Automatic

when steered

radial servo

switch-off

control

radcontrol

Hex

sledge_level (decimal)

voltage on sledge

127/256 × V_DD

i/256 × V_DD

127

i

0000 0000

00

radial servo not

inﬂuenced by

watchdog

0

−1

−i

−1/256 × V_DD

−i/256 × V_DD

−128/256 × V_DD

0100 0000

0010 0000

0110 0000

40

20

60

switch-off radial

servo on jump

error; no action

on play error

−128

switch-off radial

servo on play

error; no action

on jump error

switch-off radial

servo on play or

jump error

2003 Oct 01

64

Philips Semiconductors

Product speciﬁcation

CD audio decoder, digital servo and ﬁlterless

DAC with integrated pre-amp and laser control

SAA7824

Table 52 hold_mult parameter: velocity proportional part

during long jump, sledge gain in steered sledge

mode; RAM address 49H

Table 53 speed_threshold parameter: maximum sledge

speed allowed in fast actuator steered mode;

RAM address 48H

hold_mult

Velocity

proportional

part during long

jump K_p

Maximum sledge speed

speed_threshold value

(decimal)

allowed in fast actuator

steered mode, number of

tracks (x 1000 tracks/sec)

Hex

vel_prop1

(binary)

0000 xxxx

1000 xxxx

0100 xxxx

1100 xxxx

0010 xxxx

1010 xxxx

0110 xxxx

1110 xxxx

0001 xxxx

1001 xxxx

0101 xxxx

1101 xxxx

0011 xxxx

1011 xxxx

0111 xxxx

1111 xxxx

vel_prop2

0x

8x

4x

Cx

2x

Ax

6x

Ex

1x

9x

5x

Dx

3x

Bx

7x

Fx

0

0...127

−1

not allowed

0.015625

0.031250

0.046875

0.062500

0.078125

0.093750

0.109375

0.125000

0.140625

0.156250

0.171875

0.187500

0.203125

0.218750

0.234375

1

2

−2

−3...−127

−128

−64

3...127

128

reset value

Table 54 sledge_long_brake parameter: maximum

sledge distance allowed in sledge steered

mode; RAM address 58H

Maximum sledge

sledge_long_brake

(decimal)

distance allowed in

sledge steered mode,

number of tracks

−1...−128

test always true

1 × 128

1

2

2 × 128

Sledge gain in

steered mode

G_S

3...62

63

3 × 128...62 × 128

63 × 128

−1

reset value

xxxx x000

xxxx x001

xxxx x010

xxxx x011

xxxx x100

xxxx x101

xxxx x110

xxxx x111

x0

x1

x2

x3

x4

x5

x6

x7

2

3

4

6

8

12

16

24

2003 Oct 01

65

Philips Semiconductors

Product speciﬁcation

CD audio decoder, digital servo and ﬁlterless

DAC with integrated pre-amp and laser control

SAA7824

Table 55 defect_parm parameter: defect detector control

Table 57 time_parameter: timer interrupt values

defect_parm

Fast ﬁlter bandwidth

time_parameter value

(decimal)⁽¹⁾

Timer interrupt values

wait time (ms)

xxxx xx00

xxxx xx01

3500 Hz

7000 Hz

129 ≤ i ≤ 143

144 ≤ i ≤ 159

160 ≤ i ≤ 175

176 ≤ i ≤ 191

192 ≤ i ≤ 207

208 ≤ i ≤ 223

224 ≤ i ≤ 239

2402 ≤ i ≤ 55

0 ≤ i ≤ 15

4.26 × (i − 128)

68.2 + 4.57 × (i − 144)

141.4 + 4.92 × (i − 160)

224.1 + 5.33 × (i − 176

305.4 + 5.82 × (i − 192

398.5 + 6.40 × (i − 208)

500.8 + 7.11 × (i − 224

614.6 + 8.00 × (i − 240)

742.6 + 9.11 × i

xxxx xx10

14000 Hz

xxxx xx11

reserved for future use

defect_parm

Slow ﬁlter time

Alpha value

constant

16 ms

8 ms

xxxx 10xx

xxxx 11xx

xxxx 00xx

xxxx 01xx

0.00006

0.00012

0.00024

0.00048

4 ms

2 ms

Coefﬁcient β value

16 ≤ i ≤ 31

32 ≤ i ≤ 47

48 ≤ i ≤ 63

64 ≤ i ≤ 79

80 ≤ i ≤ 95

96 ≤ i ≤ 111

111

888.9 + 10.6 × (i − 16)

1059 + 12.8 × (i − 32)

1263 + 16.0 × (i − 48)

1519 + 21.2 × (i − 64)

1860 + 32.0 × (i − 80)

2372 + 64.0 × (i − 96)

3398.0

defect_parm

xx00 xxxx

xx01 xxxx

xx10 xxxx

xx11 xxxx

defect_parm

00xx xxxx

01xx xxxx

10xx xxxx

11xx xxxx

0.25

0.125

0.0625

reserved for future use

Defect detector maximum ON time

1.0 ms

1.5 ms

2.0 ms

2.5 ms

112...127

inﬁnite

Note

1. The time_parameter values are also used for

focus_start_time, motor_start_time1,

Table 56 interrupt_mask parameter: mask to enable

interrupt in interrupt status register; RAM

address 53H

motor_start_time2, radial_init_time and brake_time.

Table 58 phase_shift parameter: focus/radial AGC

detection phase shift; RAM address 67H

interrupt_mask

0000 0000

xxxx xxx1

Interrupt enabled

no interrupt

Focus/radial AGC detection phase

phase_shift

shift

focus lost

(decimal)

(µs)

(deg)

xxxx xx1x

subcode ready

0

xxxx x1xx

subcode absolute seconds

changed

1 × a⁽¹⁾

2 × a

i × a

60.47

180 × (a/128)

180 × (2 × a/128)

180 × (i × a/128)

180

xxxx 1xxx

xxx1 xxxx

xx1x xxxx

subcode discontinuity

radial error

120.94

i × 60.47

autosequencer state

changes

128

−1 × a

−2 × a

−i × a

128

−60.47

−120.94

−i × 60.47

−180 × (a/128)

−180 × (2 × a/128)

−180 × (i × a/128)

180

x1xx xxxx

autosequencer error

Note

1. The value a is the value programmed in Table 60 as

the 6 LSBs of osc_inc.

2003 Oct 01

66

Philips Semiconductors

Product speciﬁcation

CD audio decoder, digital servo and ﬁlterless

DAC with integrated pre-amp and laser control

SAA7824

Table 59 level1, level2 parameter: amplitude of signal

injected into focus/radial AGC; RAM address

level1 = 69H, level2 = 6AH

Table 62 re_gain parameter: initial value setting

re_gain

Value

−128

−127

−i

not allowed

1/256

Amplitude of injected

level1, level2 (decimal)

signal

(−i + 128)/256

127/256

0

−1

0

1 to 126

127

higher

128/256

highest

not allowed

1

129/256

128 to 255

i

(i + 128)/256

255/256

127

Table 60 osc_inc parameter: focus/radial AGC system

control, oscillator frequency; RAM address 68H

Table 63 sum_gain parameter: initial value setting

osc_inc

Oscillator frequency Hz

sum_gain

Value

xx00 0000

xx00 0001

xx00 0010

xx00 0011

a

0

−128

−127

−i

not allowed

1/256

64.6

129.2

(−i + 128)/256

127/256

193.8

−1

0

a × 64.6

128/256

xx11 1111

4069.8

1

129/256

AGC control

AGC system off

focus AGC active

radial AGC active

i

(i + 128)/256

255/256

00xx xxxx

11xx xxxx

01xx xxxx

127

Table 61 re_offset parameter: initial value setting

re_offset

Value

127

128/256

i/256

i

0

−i

−i/256

−128/256

−128

2003 Oct 01

67

Philips Semiconductors

Product speciﬁcation

CD audio decoder, digital servo and ﬁlterless

DAC with integrated pre-amp and laser control

SAA7824

9

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134).

SYMBOL

V_DDD

PARAMETER

CONDITIONS

internal rail

MIN.

−0.5

MAX.

UNIT

digital supply voltage

+2.5

+4.6

V

external rail

−0.5

V_I(max)

maximum input voltage

any input

notes 1, 2 and 3

−0.5

−

V

_DDD+ 0.5

V

5 V tolerant pins

any output voltage

+6.0

V_DDD

20

V

V_O

V

I_DDD

digital supply current per

supply pin

note 4

mA

I_SSD

V_es

digital ground current per

supply pin

−

20

mA

electrostatic handling

voltage

note 5

note 6

−2000

−200

0

+2000

+200

70

V

T_amb

T_stg

ambient temperature

storage temperature

°C

−55

+125

Notes

1. Must not exceed 4.2 V.

2. Including voltage on outputs in 3-state mode.

3. Only valid when both supply voltages are present.

4. The peak current is limited to 25 times the corresponding maximum current.

5. Human body model.

6. Machine model.

2003 Oct 01

68

Philips Semiconductors

Product speciﬁcation

CD audio decoder, digital servo and ﬁlterless

DAC with integrated pre-amp and laser control

SAA7824

10 CHARACTERISTICS

V_DDD= 1.65 to 1.95 V; V_DDA= 3.0 to 3.6 V; V_SS= 0 V; T_amb= 0 to 70 °C; unless otherwise speciﬁed.

SYMBOL

Supplies

V_DDD

I_DDD

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

digital supply voltage

digital supply current

1.65

1.8

1.95

V

n = 1 mode

−

4.0

5.0

6.0

3.3

34

−

mA

V

n = 2 mode

n = 4 mode

−

V_DDA

I_DDA

analog supply voltage

analog supply current

3.0

−

3.6

−

n = 1 mode

n = 2 mode

n = 4 mode

mA

−

34

−

34

−

DEM DAC output (V_pos= 3.3 V, V_SS= 0 V, V_neg= 0 V and T_amb= 25 °C)

DIFFERENTIAL OUTPUTS: PINS DACLN, DACLP, DACRN AND DACRP

S/N

signal-to-noise ratio

note 1

note 2

−

90

−

dB

(THD + N)/S

total harmonic distortion

plus noise-to-signal ratio

−

−80

Headphone buffer (V_pos= 3.3 V, V_SS= 0 V, V_neg= 0 V and T_amb= 25 °C)

OUTPUTS: PINS BUFOUTR AND BUFOUTL

S/N

signal-to-noise ratio

−

85

−

dB

(THD + N)/S

total harmonic distortion

plus noise-to-signal ratio

note 3

−

−80

INPUTS: PINS BUFINR AND BUFINL

Z_iinput impedance

−

47

−

kΩ

Servo and decoder analog functions (V_DDA= 3.3 V, V_SSA= 0 V and T_amb= 25 °C)

REFERENCE GENERATOR: PIN I_REF

V_IREF

reference voltage level

input reference current

external resistance

1.16

−

1.26

50

1.36

−

V

I_REF

µA

kΩ

R_IREF(ext)

−

24

−

DIODE VOLTAGE INPUT: PINS D1 TO D4, R1 AND R2

V_i(D)(max)

V_i(R)(max)

V_ref(int)

maximum input voltage for voltage mode

central diode input signal

0

−

960

mV

maximum input voltage for voltage mode

satellite diode input signal

internally generated

reference voltage

V_{ref_sel}= 10

V_{ref_sel}= 11

−

5

note 4

note 5

−

V

B_HF

high frequency bandwidth at 0 dB

(D1 to D4)

MHz

G_tol(HF)

high frequency gain

tolerance

−20

−

+20

%

2003 Oct 01

69

Philips Semiconductors

Product speciﬁcation

CD audio decoder, digital servo and ﬁlterless

DAC with integrated pre-amp and laser control

SAA7824

SYMBOL

B_LF

PARAMETER

CONDITIONS

at 0 dB

MIN.

TYP.

MAX.

UNIT

kHz

low frequency bandwidth

(D1 to D4, R1 and R2)

20

−

(THD + N)/S_LF

low frequency total

at 0 dB

−

−50

−40

dB

harmonic distortion plus

noise-to-signal ratio

S/N_LF

low frequency

signal-to-noise ratio

55

−

dB

%

G_tol(LF)

∆G_v(LF)

α_cs(LF)

low frequency gain

tolerance

−20

−3

−

+20

+3

−

low frequency variation of

gain between channels

−

%

low frequency channel

separation

60

dB

Laser drive circuit (V_DDA= 3.3 V; V_SSA= 0 V; T_amb= 25 °C; R_IREF= 30 kΩ)

I_o(LASER)

output current

V_LASER= 1 V −

(V_DDA− 0.6 V)

10

50

120

mA

SNR

signal-to-noise ratio

I_o= 50 mA; B = 20 MHz

I_o= 120 mA

−

40

−

dB

I_LFPOWER(max)

maximum laser supply

current

−

140

mA

V_MONITOR1

V_MONITOR2

monitor diode voltage 1

maximum power;

sel180 = 0

140

170

150

180

160

190

mV

monitor diode voltage 2

maximum power;

sel180 = 1

R_i

input resistance

10

−100

43

−

MΩ

mV

%

V_sense

P_step

I_pd

sense voltage

+100

100

10

laser output power range

power-down supply current

laser off current

µA

_mA

I_LASER(off)

−

30

Digital inputs

PIN RESET (5 V TOLERANT; TTL INPUTS WITH PULL-UP RESISTOR AND HYSTERESIS)

V_IH

V_IL

HIGH-level input voltage

LOW-level input voltage

hysteresis voltage

2.0

−

V

0.8

−

V

V_hys

I_PU

0.3

−31

V

pull-up current

V_i= 0 to V_DDD

;

−68

µA

notes 6 and 7

t_W(L)

pulse width (active LOW)

RESET only

1

−

µs

PINS V1 AND V2 (CMOS INPUTS)

V_IH

V_IL

HIGH-level input voltage

LOW-level input voltage

2.0

−

V

−

0.8

2003 Oct 01

70

Philips Semiconductors

Product speciﬁcation

CD audio decoder, digital servo and ﬁlterless

DAC with integrated pre-amp and laser control

SAA7824

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

PINS TEST1 TO TEST4 (5 V TOLERANT; TTL INPUTS WITH PULL-DOWN RESISTORS)

V_IH

V_IL

I_PD

HIGH-level input voltage

LOW-level input voltage

pull-down current

2.0

−

V

0.8

75

V_i= 0 to V_DDD

;

20

50

µA

notes 6 and 7 (V_i= 5 V;

note 8)

PINS RCK, WCLI, SDI AND SCLI (5 V TOLERANT; TTL INPUTS)

V_IH

V_IL

I_IL

HIGH-level input voltage

LOW-level input voltage

LOW-level input current

HIGH-level input current

2.0

−

V

0.8

1

V

V_i= 0; no pull-up

−

µA

I_IH

V_i= V_DDD; no pull-down

−

1

PINS SCL, SILD, RAB AND CDTCLK (5 V TOLERANT TTL INPUTS WITH HYSTERESIS)

V_IH

V_IL

I_IL

HIGH-level input voltage

LOW-level input voltage

LOW-level input current

HIGH-level input current

hysteresis voltage

2.0

−

V

0.8

1

V

V_i= 0; no pull-up

−

µA

V

I_IH

V_i= V_DDE; no pull-down

−

1

V_hys

0.3

−

3-state outputs

PINS SCLK, WCLK, DATA, CLK16, RA, FO, SL, SBSY, SFSY, CLK4/12, STATUS, MOTO1 AND MOTO2 (5 V TOLERANT

CMOS OUTPUTS; 10 ns SLEW RATE LIMITED)

V_OL

V_OH

I_OL

LOW-level output voltage

I_OL= 4 mA

−

V

4

−

0.4

−

V

HIGH-level output voltage I_OH= −4 mA

_DDD− 0.4

V

LOW-level output current

V_OL= 0.4 V; note 9

−

mA

I_OH

HIGH-level output current V_OL= V_DDD− 0.4 V;

−4

10.2

−

note 9

t_tran(L-H)

I_OZ

LOW-to-HIGH transition

time

C_L= 30 pF

−

14.5

1

ns

3-state leakage current

V_i= 0; no pull-up or

pull-down

µA

PINS DOBM, V4 AND V5 (5 V TOLERANT CMOS OUTPUTS; 5 ns SLEW RATE LIMITED)

V_OL

V_OH

I_OL

LOW-level output voltage

I_OL= 4 mA

−

V

4

−

0.4

−

V

HIGH-level output voltage I_OH= −4 mA

_DDD− 0.4

V

LOW-level output current

V_OL= 0.4 V; note 9

−

mA

I_OH

HIGH-level output current V_OL= V_DDD− 0.4 V;

−4

−

note 9

t_tran(L-H)

I_OZ

LOW-to-HIGH transition

time

C_L= 30 pF

−

10

13.8

1

ns

3-state leakage current

V_i= 0; no pull-up or

pull-down

−

µA

2003 Oct 01

71

Philips Semiconductors

Product speciﬁcation

CD audio decoder, digital servo and ﬁlterless

DAC with integrated pre-amp and laser control

SAA7824

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Digital inputs and outputs

PIN V3 (5 V TOLERANT; TTL INPUT; 3-STATE OUTPUT)

V_IH

V_IL

I_IL

HIGH-level input voltage

LOW-level input voltage

LOW-level input current

HIGH-level input current

LOW-level output voltage

2.0

−

V

0.8

1

V_i= 0; no pull-up

V_i= V_DDD; no pull-down

I_OL= 4 mA

−

µA

V

I_IH

−

1

V_OL

V_OH

I_OL

I_OH

−

0.4

−

HIGH-level output voltage I_OH= −4 mA

V_DDD− 0.4

V

LOW-level output current

V_OL= 0.4 V; note 9

4

−

mA

HIGH-level output current V_OL= V_DDD− 0.4 V;

−4

2.6

−

note 9

t_tran(L-H)

LOW-to-HIGH transition

time

C_L= 30 pF

−

6.3

1

ns

I_OZ

3-state leakage current

V_i= 0

−

µA

PINS LKILL, RKILL AND CFLAG (5 V TOLERANT; TTL INPUT WITH PULL-UP; 3-STATE OPEN-DRAIN OUTPUT; 10 ns SLEW RATE

LIMITED)

V_IH

V_IL

I_PU

HIGH-level input voltage

LOW-level input voltage

pull-up current

2.0

−

V

0.8

−36

V

V_i= 0 to V_DDD

;

−13

µA

notes 6 and 7

V_OL

V_OH

I_OL

LOW-level output voltage

I_OL= 4 mA

−

0.4

−

V

HIGH-level output voltage I_OH= −4 mA

LOW-level output current V_OL= 0.4 V; note 9

V

_DDD− 0.4

V

4

−

mA

I_OH

HIGH-level output current V_OL= V_DDD− 0.4 V;

−4

−

note 9

t_tran(L-H)

I_OZ

LOW-to-HIGH transition

time

C_L= 30 pF

8.6

10

13.8

1

ns

3-state leakage current

V_i= 0

−

µA

PINS CDTRDY, CDTDATA, EF AND SUB (5 V TOLERANT; TTL INPUT; 3-STATE OUTPUT; 10 ns SLEW RATE LIMITED)

V_IH

V_IL

I_IL

HIGH-level input voltage

LOW-level input voltage

LOW-level input current

HIGH-level input current

LOW-level output voltage

2.0

−

V

0.8

1

V

V_i= 0

−

µA

V

I_IH

V_i= V_DDD

I_OL= 4 mA

−

1

V_OL

V_OH

I_OL

I_OH

−

0.4

−

HIGH-level output voltage I_OH= −4 mA

V_DDD− 0.4

V

LOW-level output current

V_OL= 0.4 V; note 9

4

−

mA

HIGH-level output current V_OL= V_DDD− 0.4 V;

−4

−

note 9

t_tran(L-H)

I_OZ

LOW-to-HIGH transition

time

C_L= 30 pF

V_i= 0

8.6

10

13.8

1

ns

3-state leakage current

−

µA

2003 Oct 01

72

Philips Semiconductors

Product speciﬁcation

CD audio decoder, digital servo and ﬁlterless

DAC with integrated pre-amp and laser control

SAA7824

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

PIN SDA (5 V TOLERANT; 400 kHZ I²C-BUS PAD)

V_IH

V_IL

V_hys

V_OL

t_f

HIGH-level input voltage

LOW-level input voltage

hysteresis voltage

0.7V_TOL

−

V

V_TOL= 5 V; note 10

I_OL= 3 mA

−

0.3V_TOL

−

0.05V_TOL

−

LOW-level output voltage

0.4

output fall time from V_IHto bus capacitance, C_b,

V_ILfrom 10 pF to 400 pF)

20 + 0.1C_b

250

ns

I_ikg

steady-state current input V_i= V_DDD; note 11

−

2

4

µA

signal

V_i= 5 V; note 11

10

22

Crystal oscillator

INPUT: PIN OSCIN (EXTERNAL CLOCK)

V_IH

V_IL

HIGH-level input voltage

LOW-level input voltage

−

0.2V_DDD

V

0.8V_DDD

−

OUTPUT: PIN OSCOUT; see Fig.4

V_OL

V_OH

f_xtal

g_m

LOW-level output voltage

−

0.4

−

V

HIGH-level output voltage

crystal frequency

0.85V_DDD

−

V

±100 ppm

−

8.4672

−

MHz

mA/V

mutual conductance at

start-up

19.1

−

23.0

Notes

1. Assumes use of external components as shown in the application diagram; see Fig.38.

2. R_L= 10 kΩ.

3. R_L= 1 kΩ.

1.65 × 3.3

4. The typical value is as follows:

5. The typical value is as follows:

-------------------------

V_DDA

2.5 × 3.3

----------------------

V_DDA

6. Pull-up/down devices are protected by a pass-gate and do not behave as a normal resistor for external applications

7. Pull-up/down resistors are connected to external power supply (V_DDE/GND).

8. Minimum condition for V_i= 4.5 V, maximum condition for V_i= 5.5 V.

9. Accounts for 100 mV voltage drop in both supply lines.

10. Minimum condition for V_TOL= 4.5 V, maximum condition for V_TOL= 5.5 V.

11. Leakage path from pad to ground.

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11 OPERATING CHARACTERISTICS (SUBCODE INTERFACE TIMING)

V_DDD= 1.65 to 1.95 V; V_SS= 0 V; T_amb= 0 to 70 °C; unless otherwise speciﬁed.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Subcode interface timing (single speed × n); see Fig.34; note 1

INPUT: PIN RCK

t_CLKH

input clock HIGH time

input clock LOW time

input clock rise time

input clock fall time

2/n

4/n

6/n

µs

t_CLKL

2/n

−

4/n

−

6/n

µs

ns

µs

t_r

80/n

20/n

t_f

−

t_d(SFSY-RCK)

delay time SFSY to RCK

10/n

−

OUTPUTS: PINS SBSY, SFSY AND SUB (C_L= 20 pF)

T_cy(block)

t_W(SBSY)

T_cy(frame)

t_W(SFSY)

t_SFSYH

block cycle time

SBSY pulse width

frame cycle time

SFSY pulse width

SFSY HIGH time

SFSY LOW time

12.0/n

13.3/n

14.7/n

300/n

150/n

366/n

66/n

ms

µs

−

122/n

136/n

3-wire mode

−

t_SFSYL

84/n

t_d(SFSY-SUB)

delay time SFSY to SUB

(P data) valid

1/n

t_d(RCK-SUB)

delay time RCK falling to

SUB

−

0

µs

t_h(RCK-SUB)

hold time RCK to SUB

0.7/n

Note

1. In the normal operating mode the subcode timing is directly related to the overspeed factor ‘n’. In the lock-to-disc

mode ‘n’ is replaced by the disc speed factor ‘d’,

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DAC with integrated pre-amp and laser control

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t

handbook, full pagewidth

T

cy(block)

W(SBSY)

SBSY

t

SFSYH

SFSY

(4-wire mode)

t

T

W(SFSY)

cy(frame)

SFSY

(3-wire mode)

t

SFSYL

SFSY

0.8 V

t

d(SFSY−RCK)

t

f

r

V

– 0.8 V

DD

RCK

0.8 V

t

d(SFSY−SUB)

h(RCK−SUB)

t

d(RCK−SUB)

V

– 0.8 V

DD

SUB

0.8 V

MGL718

Fig.34 Subcode interface timing diagram.

75

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12 OPERATING CHARACTERISTICS (I²S-BUS TIMING)

V_DDD= 1.65 to 1.95 V; V_SS= 0 V; T_amb= 0 to 70 °C; unless otherwise speciﬁed.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

I²S-bus timing (single speed × n); see Fig.35; note 1

CLOCK OUTPUT: PIN SCLK (C_L= 20 pF)

T_cy

t_CH

t_CL

output clock period

clock HIGH time

clock LOW time

sample rate = f_s

sample rate = 2f_s

sample rate = 4f_s

sample rate = f_s

sample rate = 2f_s

sample rate = 4f_s

sample rate = f_s

sample rate = 2f_s

sample rate = 4f_s

−

472.4/n

−

ns

236.2/n

ns

118.1/n

166/n

83/n

42/n

166/n

83/n

42/n

−

OUTPUTS: PINS WCLK, DATA AND EF (C_L= 20 pF)

t_su

set-up time

sample rate = f_s

sample rate = 2f_s

sample rate = 4f_s

sample rate = f_s

sample rate = 2f_s

sample rate = 4f_s

95/n

48/n

24/n

95/n

48/n

24/n

−

ns

t_h

hold time

Note

1. In the normal operating mode the I²S-bus timing is directly related to the overspeed factor ‘n’. In the lock-to-disc mode

‘n’ is replaced by the disc speed factor ‘d’.

clock period T

cy

t

CH

CL

V

– 0.8 V

DD

SCLK

0.8 V

t

su

t

h

V

– 0.8 V

DD

WCLK

DATA

EF

0.8 V

MBG407

Fig.35 I²S-bus timing diagram.

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13 OPERATING CHARACTERISTICS (MICROCONTROLLER INTERFACE TIMING)

V_DD= 1.65 to 1.95 V; V_SS= 0 V; T_amb= 0 to 70 °C; unless otherwise speciﬁed.

NORMAL MODE

MIN. MAX.

LOCK-TO-DISC MODE

SYMBOL

PARAMETER

CONDITIONS

UNIT

MAX.

MIN.

Microcontroller interface timing (4-wire bus mode; writing to decoder registers 0 to F; reading Q-channel

subcode and decoder status); see Figs.36 and 37; note 1

INPUTS SCL AND RAB

t_CL

t_CH

t_r

input clock LOW time

input clock HIGH time

input rise time

480/n + 20

−

2400/n + 20

−

ns

480/n + 20

−

2400/n + 20

−

480/n

−

480/n

t_f

input fall time

READ MODE (C_L= 20 pF)

t_dRDdelay time RAB to

−

50

−

50

ns

SDA valid

t_PD

propagation delay

SCL to SDA

720/n − 20 960/n + 20 720/n + 20

4800/n + 20

50

t_dRZ

delay time RAB to

−

50

−

ns

SDA high-impedance

WRITE MODE (C_L= 20 pF)

t_suD

set-up time SDA to

note 2

20 − 720/n

−

20 − 720/n

−

SCL

t_hD

hold time SCL to SDA

−

960/n + 20 −

4800/n + 20 ns

t_suCR

set-up time SCL to

RAB

240/n + 20

−

1200/n + 20

−

ns

t_dWZ

delay time SDA to

0

−

0

−

ns

RAB high-impedance

Microcontroller interface timing (4-wire bus mode; servo commands); see Figs.36 and 38; note 2

INPUTS SCL AND SILD

t_L

t_H

t_r

input LOW time

input HIGH time

input rise time

input fall time

710

−

710

−

ns

−

240

t_f

−

READ MODE (C_L= 20 pF)

t_dLDdelay time SILD to

−

25

950

50

−

25

950

50

−

ns

SDA valid

t_PD

propagation delay

SCL to SDA

−

t_dLZ

delay time SILD to

−

SDA high-impedance

t_suCLR

set-up time SCL to

SILD

480

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DAC with integrated pre-amp and laser control

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NORMAL MODE

MIN. MAX.

830

LOCK-TO-DISC MODE

MIN. MAX.

SYMBOL

t_hCLR

PARAMETER

CONDITIONS

UNIT

hold time SILD to

SCL

−

830

−

ns

WRITE MODE (C_L= 20 pF)

t_sD

set-up time SDA to

0

−

0

−

ns

SCL

t_hD

hold time SCL to SDA

950

480

−

950

480

−

ns

t_sCL

set-up time SCL to

SILD

t_hCL

hold time SILD to

SCL

120

70

0

−

120

70

0

−

ns

t_dPLP

t_dWZ

delay between two

SILD pulses

delay time SDA to

SILD high-impedance

Notes

1. The 4-wire bus mode microcontroller interface timing for writing to decoder registers 0 to F, and reading Q-channel

subcode and decoder status, is a function of the overspeed factor ‘n’. In the lock-to-disc mode the maximum data

rate is lower.

2. Negative set-up time means that the data may change after clock transition.

t

r

f

V

– 0.8 V

DD

RAB

SCL

t

r

f

0.8 V

t

CH

V

– 0.8 V

DD

t

dRD

0.8 V

t

dRZ

t

CL

t

PD

V

– 0.8 V

DD

SDA (SAA782X)

high-impedance

0.8 V

MBL451

Fig.36 4-wire microcontroller timing; read mode (Q-channel subcode and decoder status information).

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DAC with integrated pre-amp and laser control

SAA7824

t

f

CH

r

handbook, full pagewidth

V

– 0.8 V

t

DD

suCR

RAB

0.8 V

t

CL

t

r

CH

f

V

– 0.8 V

DD

0.8 V

SCL

t

dWZ

CL

hD

t

suD

V

– 0.8 V

DD

SDA

(microcontroller)

high-impedance

0.8 V

MBG405

Fig.37 4-wire bus microcontroller timing; write mode (decoder registers 0 to F).

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DAC with integrated pre-amp and laser control

SAA7824

V

– 0.8 V

handbook, full pagewidth

SILD

DD

0.8 V

t

hCLR

t

suCLR

V

– 0.8 V

DD

SCL

SDA

0.8 V

t

PD

dLD

dLZ

V

– 0.8 V

0.8 V

DD

(SAA782X)

MBL452

Fig.38 4-wire bus microcontroller timing; read mode (servo commands).

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DAC with integrated pre-amp and laser control

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handbook, full pagewidth

V

- 0.8 V

DD

SILD

0.8 V

sCL

t

L

t

H

dPLP

– 0.8 V

V

DD

SCL

SDA

0.8 V

t

hCL

t

L

sD

t

dWZ

t

hD

V

– 0.8 V

0.8 V

DD

(microcontroller)

MBG416

Fig.39 4-wire bus microcontroller timing; write mode (servo commands).

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14 APPLICATION INFORMATION

C30 220 µF (50 V)

handbook, full pagewidth

A

V

3.3 V

1.8 V

CC

out

FB

out

FB

1

28

27

26

25

24

23

22

30

21

20

19

18

17

16

15

B

C

D

E

F

RAD−

FOC+

RADO−

FOCO+

GND

2

X1

1

2

3

TZA1048

4

FOC-

FOCO-

RADO+

MUTE

RA1

5

X1

3

4

RAD+

6

G

H

V

FO1

CC

7

29

8

EARTH

V

CC

SL1

J

B SLEDGE+

SLO+

VB

out

X2

5

6

9

SLO−

GND

WH SLEDGE−

10

11

12

13

14

GND

1.65 V

out

G MOTOR+

Y MOTOR−

MOTO−

MOTO+

mute

X2

3

4

MOTO1

MOTO2

K

V

CC

L

C32

C33

C28

C27

C26

C25

HOME_SW

BL

0.47 µF

(50 V)

470 pF

(50 V)

470 pF

(50 V)

470 pF

(50 V)

470 pF

(50 V)

470 pF

(50 V)

X2

2

1

V

SSD

M

N

O

to

TRAY_SW

X3

1

2

CD mechanism

(VAM220X)

3.3 V

C6

10 µF

(15 V)

DD

V

SSD

LD

LFPOWER

EXFILTER

MONITOR

SENSE

C7 10 nF

(50 V)

X1 10

1

2

MON

X1

X1 15

X1

9

3

4

V

SSA1

5

R8

I

3.3 V

REF

C8 10 µF

(50 V)

DD

6

V

SSD

DD

V

24 kΩ (0.5 W)

DDA1

3.0 V

7

REFO

D1

X1 12

X1

X1 14

X1

8

D1

D2

6

9

D2

D3

10

11

12

13

14

15

16

17

18

19

20

SAA7824HL

8

D4

X1 11

X1 13

R1

R2

X1

7

CSLICE

C24

100 nF

(50 V)

V

3.0 V

DDA2

DD

V

SSA2

8.4672 MHz

OSCOUT

OSCIN

V

SSD

V

SSA3

C23

1 nF

(50 V)

C22

C21

33 pF

(100 V)

C20

33 pF

(100 V)

10 µF

(50 V)

V

SSD

33 µF

(16 V)

C17

P

22 µF (35 V)

3.3 V

C18

DD

audio in R

audio in L

C18

C19

88 µF

C17 (16 V)

3.3 nF

22 µF (38 V)

C15

3.3 nF

R

S

R9

47 kΩ

(0.6 W)

R15

R7

47 kΩ

(0.6 W)

R10

(100 V)

100 kΩ

(0.4 W)

100 kΩ

(0.4 W)

V

SSD

R6

R8

TR4

TR3

BC337

47 kΩ

(0.4 W)

47 kΩ

(0.4 W)

V

SSD

MBL453

Fig.40 Typical application diagram incorporating a voltage mechanism (continued in Fig.41).

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DAC with integrated pre-amp and laser control

SAA7824

A

X4

1

2

3

4

5

6

V

IN (12 V)

IN (5 V)

handbook, full pagewidth

CC

5 V

B

C

CC

C1

100 nF

(50 V)

TR1

BC337

D

E

F

V

SSD

V

SSD

audio out (R)

audio out (L)

audio_R

V

G

H

SSD

3.3 V

DD

audio_L

J

C2

33 µF

(16 V)

TR2

BC337

V

SSD

1.8 V

DD

K

L

C8

33 µF

(16 V)

3.3 V

DD

R11

10 Ω

(0.6 W)

R16

24 kΩ

(0.6 W)

R4

24 kΩ

R3

24 kΩ

R2

24 kΩ

R1

24 kΩ

V

SSD

(0.6 W) (0.6 W) (0.6 W) (0.6 W)

C5

100 nF

(50 V)

R13

10 kΩ

(0.6 W)

R14

10 kΩ

(0.6 W)

1.8 V

DD

V

SSD

M

N

O

C4

100 nF

(50 V)

V

SSD

SBSY

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

SFSY

SUB

RCK

to mini micro

MUTE

3.3 V

DD

X5

1

2

3

4

5

6

7

8

9

STATUS

SILD

STATUS

TRAY 5 W

RAB

V

SSD

SCL

SDA

RESET

CLK4/12

CLK16

SCLK

WCLK

DATA

EF

RESET

SAA7824HL

CDTCLK

CDTDATA

CDTRDY

X5 10

X5 11

X5 12

V

SSD

3.3 V

for playability test

WCLK

SCLI

DD

WCLI

SDI

R12

10 Ω

(0.6 W)

X6

1

2

3

4

5

6

SCLK

V

CFLAG

DDD1

5 V

C9

100 nF

(50 V)

DATA

V

SSD

V

SSD

P

to headphone

O BMD

V

SSD

33 µF

(16 V)

10 Ω

(0.6 W)

D

F

B

C11

C10

R

S

R23

R22

C36

10 nF

(50 V)

C37

10 nF

(50 V)

10 Ω

(0.6 W)

B POLB stereo

3.5 µs

33 µF

(16 V)

audio R

audio L

2

1

C14

R10

10 kΩ

C16

3

4

V

SSD

MBL454

10 µF (50 V)

5

10 µF (50 V)

V

SSD

Fig.41 Typical application diagram incorporating a voltage mechanism (continued from Fig.40).

83

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DAC with integrated pre-amp and laser control

SAA7824

15 PACKAGE OUTLINE

LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm

SOT315-1

y

X

A

60

41

Z

61

40

E

e

H

A

E

2

E

A

(A )

3

A

1

w M

p

θ

b

L

p

L

pin 1 index

80

21

detail X

1

20

Z

D

v

M

A

e

w M

b

p

D

B

H

v

M

B

D

0

5

10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

L

v

w

y

Z

θ

1

2

3

p

D

E

p

D

E

max.

7^o

0^o

0.16 1.5

0.04 1.3

0.27 0.18 12.1 12.1

0.13 0.12 11.9 11.9

14.15 14.15

13.85 13.85

0.75

0.30

1.45 1.45

1.05 1.05

mm

1.6

0.25

0.5

1

0.2 0.15 0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-01-19

03-02-25

SOT315-1

136E15

MS-026

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SAA7824

16 SOLDERING

• Use a double-wave soldering method comprising a

turbulent wave with high upward pressure followed by a

smooth laminar wave.

16.1 Introduction to soldering surface mount

packages

• For packages with leads on two sides and a pitch (e):

This text gives a very brief insight to a complex technology.

A more in-depth account of soldering ICs can be found in

our “Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).

– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the

transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the

printed-circuit board.

There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering can still be used for

certain surface mount ICs, but it is not suitable for fine pitch

SMDs. In these situations reflow soldering is

recommended.

The footprint must incorporate solder thieves at the

downstream end.

• For packages with leads on four sides, the footprint must

be placed at a 45° angle to the transport direction of the

printed-circuit board. The footprint must incorporate

solder thieves downstream and at the side corners.

16.2 Reﬂow soldering

Reflow soldering requires solder paste (a suspension of

fine solder particles, flux and binding agent) to be applied

to the printed-circuit board by screen printing, stencilling or

pressure-syringe dispensing before package placement.

During placement and before soldering, the package must

be fixed with a droplet of adhesive. The adhesive can be

applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the

adhesive is cured.

Several methods exist for reflowing; for example,

convection or convection/infrared heating in a conveyor

type oven. Throughput times (preheating, soldering and

cooling) vary between 100 and 200 seconds depending

on heating method.

Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal

of corrosive residues in most applications.

Typical reflow peak temperatures range from

215 to 250 °C. The top-surface temperature of the

packages should preferable be kept below 220 °C for

thick/large packages, and below 235 °C for small/thin

packages.

16.4 Manual soldering

Fix the component by first soldering two

diagonally-opposite end leads. Use a low voltage (24 V or

less) soldering iron applied to the flat part of the lead.

Contact time must be limited to 10 seconds at up to

300 °C.

16.3 Wave soldering

Conventional single wave soldering is not recommended

for surface mount devices (SMDs) or printed-circuit boards

with a high component density, as solder bridging and

non-wetting can present major problems.

When using a dedicated tool, all other leads can be

soldered in one operation within 2 to 5 seconds between

270 and 320 °C.

To overcome these problems the double-wave soldering

method was specifically developed.

If wave soldering is used the following conditions must be

observed for optimal results:

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16.5 Suitability of surface mount IC packages for wave and reﬂow soldering methods

SOLDERING METHOD

PACKAGE⁽¹⁾

WAVE

not suitable

REFLOW⁽²⁾

BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA

suitable

HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, not suitable⁽³⁾

HVSON, SMS

suitable

PLCC⁽⁴⁾, SO, SOJ

LQFP, QFP, TQFP

SSOP, TSSOP, VSO

suitable

not recommended⁽⁴⁾⁽⁵⁾suitable

not recommended⁽⁶⁾

suitable

Notes

1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy

from your Philips Semiconductors sales office.

2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with respect to time) and body size of the package, there is a risk that internal or external package

cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the

Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.

3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder

cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,

the solder might be deposited on the heatsink surface.

4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.

5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not

suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

2003 Oct 01

86

Philips Semiconductors

Product speciﬁcation

CD audio decoder, digital servo and ﬁlterless

DAC with integrated pre-amp and laser control

SAA7824

17 DATA SHEET STATUS

DATA SHEET

STATUS⁽¹⁾

PRODUCT

STATUS⁽²⁾⁽³⁾

LEVEL

DEFINITION

I

Objective data

Development This data sheet contains data from the objective speciﬁcation for product

development. Philips Semiconductors reserves the right to change the

speciﬁcation in any manner without notice.

II

Preliminary data Qualiﬁcation

This data sheet contains data from the preliminary speciﬁcation.

Supplementary data will be published at a later date. Philips

Semiconductors reserves the right to change the speciﬁcation without

notice, in order to improve the design and supply the best possible

product.

III

Product data

Production

This data sheet contains data from the product speciﬁcation. Philips

Semiconductors reserves the right to make changes at any time in order

to improve the design, manufacturing and supply. Relevant changes will

be communicated via a Customer Product/Process Change Notiﬁcation

(CPCN).

Notes

1. Please consult the most recently issued data sheet before initiating or completing a design.

2. The product status of the device(s) described in this data sheet may have changed since this data sheet was

published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.

3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

18 DEFINITIONS

19 DISCLAIMERS

Short-form specification

The data in a short-form

Life support applications

These products are not

specification is extracted from a full data sheet with the

same type number and title. For detailed information see

the relevant data sheet or data handbook.

designed for use in life support appliances, devices, or

systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips

Semiconductors customers using or selling these products

for use in such applications do so at their own risk and

agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

Limiting values definition Limiting values given are in

accordance with the Absolute Maximum Rating System

(IEC 60134). Stress above one or more of the limiting

values may cause permanent damage to the device.

These are stress ratings only and operation of the device

at these or at any other conditions above those given in the

Characteristics sections of the specification is not implied.

Exposure to limiting values for extended periods may

affect device reliability.

Right to make changes

Philips Semiconductors

reserves the right to make changes in the products -

including circuits, standard cells, and/or software -

described or contained herein in order to improve design

and/or performance. When the product is in full production

(status ‘Production’), relevant changes will be

Application information

Applications that are

communicated via a Customer Product/Process Change

Notification (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these

products, conveys no licence or title under any patent,

copyright, or mask work right to these products, and

makes no representations or warranties that these

products are free from patent, copyright, or mask work

right infringement, unless otherwise specified.

described herein for any of these products are for

illustrative purposes only. Philips Semiconductors make

no representation or warranty that such applications will be

suitable for the specified use without further testing or

modification.

2003 Oct 01

87

Philips Semiconductors

Product speciﬁcation

CD audio decoder, digital servo and ﬁlterless

DAC with integrated pre-amp and laser control

SAA7824

20 PURCHASE OF PHILIPS I²C COMPONENTS

Purchase of Philips I²C components conveys a license under the Philips’ I²C patent to use the

components in the I²C system provided the system conforms to the I²C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

2003 Oct 01

88

Philips Semiconductors – a worldwide company

Contact information

For additional information please visit http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

For sales ofﬁces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.

SCA75

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed

without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license

under patent- or other industrial or intellectual property rights.

Printed in The Netherlands

R04/03/pp89

Date of release: 2003 Oct 01

Document order number: 9397 750 12009


型号：	SAA7824
厂家：	NXP
描述：	CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control (PhonIC) CD音频解码器，数字伺服和无滤波器DAC集成前置放大器和激光控制（音）解码器放大器 CD
文件：	总89页 (文件大小：372K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SAA7824 [NXP]

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