SAA7893HL [NXP]
Super audio media player; 超级音频媒体播放器
| 型号： | SAA7893HL |
| 厂家： | 
NXP |
| 描述： | Super audio media player |
| 文件： | 总66页 (文件大小：952K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SAA7893HL
Super audio media player
Rev. 02 — 26 February 2003
Product data
1. General description
Thanks to the superior sound quality and multichannel capability of Super Audio CD
(SACD) technology, multimedia devices such as DVD players and home cinema
systems are incorporating SACD functionality. Philips' Super Audio Media Player
(SA-MP) provides a flexible, state-of-the-art solution for SACD playback on DVD
architectures.
Built around the SAA7893HL SACD processor, SA-MP system solution delivers
complete SACD functionality, avoiding the need for continual redesign and
re-integration of SACD into various applications. The system is completed with a
single 64 Mbit SDRAM and has extensive software processing options, resulting in
low total system cost (see Figure 1).
With integrated support for multiple loaders, the SAA7893 supports a variety of DVD
platforms. High level and standard software interfaces – optimized for easy design-in
– further enhance adaptability, enabling designers to build SACD players on many
different hardware and software platforms. This ensures that the SA-MP can be left
unchanged even if the SACD playback hardware is altered, again minimizing
development effort.
DVD HOST IC
DVD SW STACK
ANNEX J+ PLAYBACK API
SACD TEXT AND DATA API
SPEAKER SETUP API
SW
PSP DECODER
SACD DEMUX
DST DECODER
BE SWITCH
DSD POSTPROCESSOR
PCM CONVERTER
DSD CONVERTER
DAC SWITCH
D/A
HW
HW
SAA7893HL
SA-MP
MGU724
64 Mbit
SDRAM
DVD host
DVD host
DAC out
Fig 1. General block diagram.
SAA7893HL
Super audio media player
Philips Semiconductors
1.1 Hardware
The SA-MP hardware consists of the SAA7893HL device. A typical HW block
diagram of a DVD system incorporating the SAA7893HL is shown in Figure 2.
The SAA7893HL takes sector data from the front-end. The front-end is controlled by
the DVD host via the SA-MP software stack. The SAA7893HL uses one 64 Mbit
SDRAM for audio data buffering and storage of SACD TOCs. The front-end timing
can be fully asynchronous from all clocks.
The 6-channel DAC outputs of the DVD host are routed via the SAA7893HL which
provides a DAC switch function between SACD mode and DVD mode. The audio
outputs of the SAA7893HL operate on the system audio clock.
The DVD back-end communicates with the SAA7893HL via a host bus. The system
clock and the system audio clock are allowed to be asynchronous.
NVRAM
SDRAM
control
video
DVD BACK-END
27 MHz
audio
clock
FRONT-
END
data
host
bus
ROM
PLL
audio
SAA7893HL
EFM
audio
SDRAM
MGU726
Fig 2. Hardware block diagram.
1.2 Software
The SA-MP software is delivered in the form of a library in the development
environment of the DVD host. The SA-MP software has been developed in ANSI-C
using conventional software technology to allow easy integration into any
development environment. A typical software block diagram of a DVD system
incorporating SA-MP is shown in Figure 3.
At the device driver and HW-level, SA-MP interfaces with the SAA7893HL and a
front-end driver. At the infrastructure level, SA-MP interfaces with an Operating
System Abstraction layer (OSA). At the application level, SA-MP provides a high-level
playback and post-processing interface which is easy to integrate into typical
applications.
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Product data
Rev. 02 — 26 February 2003
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SAA7893HL
Super audio media player
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APPLICATION LAYER - "SACD PLAYER BEHAVIOUR"
Annex J+
UI SUBSYSTEM
"LOOK-AND-FEEL"
INFRASTRUCTURE
(OSA)
MEDIA
PLAYERS
SA-MP
POSTPROCESSING
LOADER
etc.
DEVICE
DRIVERS
DEVICE
DRIVERS
UI DEVICE
DRIVERS
MGU725
SAA7893HL
HW
HW
I/O PERIPHERALS
Fig 3. Software block diagram.
2. Features
2.1 Components
■ SAA7893HL second generation SACD processor IC
■ SA-MP Annex J+ level software stack.
2.2 HW interfaces
■ Front-end, supports 3 types:
◆ UDE
◆ FEC
◆ I2S-bus
■ Flexible PSP detection from EFM signal with AGC, without EFM clock (digital PLL)
■ (DVD-)host bus, supports 3 types:
◆ Separate address/data bus (SAD16) with 16-bit data bus (3 different modes)
◆ Multiplexed address/data bus (MAD16) with 16-bit data bus (2 different
modes)
◆ Separate address/data bus (SAD08) with 8-bit data bus (1 mode)
■ 16-bit 100 MHz SDRAM interface supports one 64 Mbit device
■ 6-channel I2S-PCM audio input 44.1, 48, 88.2, 96, 176.4 or 192 kHz at
16-bit or 24-bit
■ 6-channel DSD or I2S-PCM (2fs or 4fs) output with programmable pinning
configuration
■ 2-channel DSD or I2S-PCM (2fs or 4fs) output with programmable pinning
configuration
■ Audio clock reference 256fs, 384fs, 512fs or 768fs
■ System clock 27 to 35 MHz.
2.3 SW interfaces
■ Annex J+ level playback interface
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Product data
Rev. 02 — 26 February 2003
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Super audio media player
Philips Semiconductors
■ High-level audio post-processing control
■ SACD data interface
■ System configuration
2.4 System
■ Full SACD Menu TOC and Area TOC storage in VBR
■ Front-end clock asynchronous to other clocks
2.5 System configuration
■ D/A converters:
◆ DSD and PCM selectable pin sharing configuration
◆ DSD clock polarity
■ Audio and system clock asynchronous
■ Front-end type
2.6 SACD playback
■ SACD playback:
◆ Multi-channel
◆ 2-channel
■ PSP processing
■ Decrypting and demultiplexing
■ VBR management
■ DST decoding
■ Fade processing
■ Annex J+ level software interface:
◆ Stop
◆ Pause
◆ Play
◆ Fast forward
◆ Fast reverse
◆ Next/previous track
◆ Program and play playlist
◆ Repeat (Track, All or AB)
◆ Shuffle
◆ Introscan
◆ Time search
2.7 Audio postprocessing
■ DSD Bass Management with support of:
◆ Dolby® configuration 0 (LLL1)
◆ Dolby® configuration 1 (SSS1)
◆ Dolby® configuration 2 (LSS0)
■ Programmable bass filter frequency and slope:
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Product data
Rev. 02 — 26 February 2003
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Super audio media player
Philips Semiconductors
◆ 60, 80, 100, 120 Hz
◆ 12, 18, 24 dB/Oct
(other frequencies or slopes are possible on customer request)
■ DSD down mixing:
◆ 2/2
◆ 3/0
◆ 2/0
◆ separate 2/0
■ DSD attenuation function 0 to −90 dB, programmable per channel
■ DSD delay function total 65 ms (approximately 20 meters), programmable per
channel
■ 6-channel PCM input:
◆ 44.1, 88.2, 176.4, 48, 96 or 192 kHz at 16-bit or 24-bit
◆ PCM to DSD upsampling with 3 programmable Sigma-Delta and anti-aliasing
filter modes
◆ Attenuation and delay as with DSD
■ DSD to PCM conversion 88.2, 176.4 kHz at 24-bit.
2.8 SACD data and text
■ Album info
■ Disc info
■ Album or disc text
■ Area text
■ Track data
■ Track text.
2.9 General
■ E-JTAG for board test and debug
■ 3.3 V pad supply voltage
■ 1.8 V core supply voltage
■ 1.8 V analog supply voltage
■ LQFP128 package
■ 0.18 µm CMOS process.
3. Applications
■ Consumer DVD players
■ Home cinema
■ Car audio systems.
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Super audio media player
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4. Ordering information
Table 1:
Ordering information
Type number
Package
Name
Description
plastic low profile quad flat package; 128 leads; body 14 × 20 × 1.4 mm2
Version
SAA7893HL
LQFP128
SOT425-1
5. Block diagram
Figure 4 shows the block diagram of the SAA7893HL with all defined functions.
to host
host_sel
HF
HOST
ADC
AGC
INTERFACE
REGISTER
HOST
SAA7893HL
INTERFACE
MEMORY
MANAGER
FRONT-
END
INTERFACE
PSP-KEY
DECODER
PI-bus
key
control
8-CHANNEL
DSD2PCM
CONVERSION
data-bus
DECRYPTION/
SECTOR
PROCESSOR
DEMUX
SACD
AUDIO
INTERFACE
2, 5 or 6-channel
LOSSLESS
DECODER
SPEAKER SETUP
VOLUME CONTROL
DELAY
to
PI-BUS
CONTROL
DSD/PCM
DAC
SWITCH
MATRIX
SDRAM
INTERFACE
MBL615
to 64 Mbit
SDRAM
sys_clk
27-35 MHz
aud_clk
256/384/512/768*fs
external PCM
Fig 4. Block diagram.
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Product data
Rev. 02 — 26 February 2003
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Super audio media player
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6. Pinning information
6.1 Pinning
H_A[1]
H_DQ[15]
H_DQ[14]
GND_IO1
H_DQ[13]
H_DQ[12]
H_DQ[11]
H_DQ[10]
H_DQ[9]
1
2
3
4
5
6
7
8
9
102 D_DQ[13]
101 D_DQ[2]
100 D_DQ[12]
99 GND_IO5
98 D_DQ[3]
97 D_DQ[11]
96 D_DQ[4]
95 D_DQ[10]
94 D_DQ[9]
VCC_IO1 10
H_DQ[8] 11
H_DQ[7] 12
H_DQ[6] 13
H_DQ[5] 14
H_DQ[4] 15
H_DQ[3] 16
GND_IO2 17
H_procclock 18
VCC_Core1 19
GND_Core1 20
sys_clk 21
93 D_DQ[6]
92 VCC_IO4
91 D_DQ[8]
90 D_DQ[7]
89 D_LDQM
88 D_UDQM
87 D_DQ[5]
86 D_clk
85 VCC_Core2
84 GND_Core2
83 GND_IO4
82 D_CASn
SAA7893HL
H_DQ[2] 22
H_DQ[1] 23
H_CSn 24
81 D_RASn
80 D_Wen
79 D_ADDR[11]
78 D_ADDR[12]
77 D_ADDR[9]
76 VCC_IO3
75 D_ADDR[13]
74 D_ADDR[8]
73 D_ADDR[10]
72 D_ADDR[7]
71 D_ADDR[0]
70 D_ADDR[6]
69 GND_IO3
68 D_ADDR[1]
67 D_ADDR[5]
66 D_ADDR[2]
65 D_ADDR[4]
H_DQ[0] 25
H_RWn 26
H_WAIT 27
H_IRQn 28
aud_clk 29
PCM_dclk_in 30
PCM_wclk_in 31
V
32
33
DDA
V
SSA
biasin 34
Agcinp 35
Adcrefl 36
VCC_IO7 37
GND_IO7 38
MCE016
Fig 5. Pin configuration.
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Product data
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Super audio media player
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6.2 Pin description
Table 2:
Pin description
Symbol
Pin
1
Type[1]
IN
Description
address bus
data bus
H_A[1]
H_DQ[15]
H_DQ[14]
GND_IO1
H_DQ[13]
H_DQ[12]
H_DQ[11]
H_DQ[10]
H_DQ[9]
VCC_IO1
H_DQ[8]
H_DQ[7]
H_DQ[6]
H_DQ[5]
H_DQ[4]
H_DQ[3]
GND_IO2
2
I/O10
I/O10
GND_IO
I/O10
I/O10
I/O10
I/O10
I/O10
VCC_IO
I/O10
I/O10
I/O10
I/O10
I/O10
I/O10
GND_IO
IN
3
data bus
4
GND I/O pads
data bus
5
6
data bus
7
data bus
8
data bus
9
data bus
10
11
12
13
14
15
16
17
VCC I/O pads
data bus
data bus
data bus
data bus
data bus
data bus
GND I/O pads
H_procclock
VCC_Core1
GND_Core1
sys_clk
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
host processor EMI interface clock
VCC_core core supply voltage
GND_core core ground
IN
system clock
H_DQ[2]
H_DQ[1]
H_CSn
I/O10
I/O10
IN
data bus
data bus
host chip select; active LOW
data bus
H_DQ[0]
H_RWn
I/O10
IN
read = 1; write = 0
wait signal
H_WAIT
H_IRQn
O10
O10
interrupt request; active LOW
DSD audio clock
aud_clk
IN
PCM_dclk_in
PCM_wclk_in
VDDA
IN
PCM data clock
IN
PCM word clock
VDDCO
VSSCO
APIO
APIO
APIO
VCC_IO
GND_IO
IN
VDD of ADC
VSSA
VSS of AGC and ADC; connected to substrate
bias current input
AGC positive input signal; HF in
ADC decoupling
biasin
Agcinp
Adcrefl
VCC_IO7
GND_IO7
PCM_CeLf_in
VCC I/O pads
GND I/O pads
PCM data center or LFE
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Super audio media player
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Table 2:
Pin description…continued
Symbol
Pin
40
41
42
43
44
Type[1]
Description
PCM_LeRi_in
PCM_LsRs_in
B_FLAG/SERR
B_SYNC/Sync
B_WCLK/SENB
IN
IN
IN
IN
IN
PCM data left or right
PCM data left or right surround
I2S-bus flag (EDC flag)
sector sync or absolute time sync
I2S-bus word clock or UDE data sense from
host
B_DATA/Be_dat(0) 45
IN
IN
IN
I2S-bus data or LSB data of parallel interface
I2S-bus bit clock
B_BCLK/SDCLK
UDE_req
46
47
host request data from front-end; routed via
the SAA7893HL
Data_req
Be_dat(1)
Be_dat(2)
Be_dat(3)
Be_dat(4)
Be_dat(5)
Be_dat(6)
Be_dat(7)
TRST
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
O10
IN
data request for UDE
front-end parallel data interface
front-end parallel data interface
front-end parallel data interface
front-end parallel data interface
front-end parallel data interface
front-end parallel data interface
front-end parallel data interface
boundary scan reset
IN
IN
IN
IN
IN
IN
IN1
IN1
VCC_IO
O10
IN1
IN
TMS
boundary scan mode select
VCC I/O pads
VCC_IO2
TDO
output
TDI
boundary scan data input
boundary scan clock
TCK
H_sel[0]
IN
host select signals: SAD16, MAD16 and
SAD08
H_sel[1]
63
IN
host select signals: SAD16, MAD16 and
SAD08
D_ADDR[3]
D_ADDR[4]
D_ADDR[2]
D_ADDR[5]
D_ADDR[1]
GND_IO3
64
65
66
67
68
69
70
71
72
73
74
75
76
77
O10
SDRAM address bus
SDRAM address bus
SDRAM address bus
SDRAM address bus
SDRAM address bus
GND I/O pads
O10
O10
O10
O10
GND_IO
O10
D_ADDR[6]
D_ADDR[0]
D_ADDR[7]
D_ADDR[10]
D_ADDR[8]
D_ADDR[13]
VCC_IO3
SDRAM address bus
SDRAM address bus
SDRAM address bus
SDRAM address bus
SDRAM address bus
SDRAM address bus
VCC I/O pads
O10
O10
O10
O10
O10
VCC_IO
O10
D_ADDR[9]
SDRAM address bus
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Super audio media player
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Table 2:
Pin description…continued
Symbol
Pin
78
Type[1]
Description
D_ADDR[12]
D_ADDR[11]
D_Wen
O10
SDRAM address bus
SDRAM address bus
read or write
79
O10
80
O10
D_RASn
81
O10
row address select; active LOW
column address select; active LOW
GND I/O pads
D_CASn
82
O10
GND_IO4
GND_Core2
VCC_Core2
D_clk
83
GND_IO
84
GND_core core ground
85
VCC_core core supply voltage
86
O10
clock signal needed for SDRAM
D_DQ[5]
87
I/O10
O10
data bus
D_UDQM
D_LDQM
88
DQ mask enable (upper)
DQ mask enable (lower)
data bus
89
O10
D_DQ[7]
90
I/O10
I/O10
VCC_IO
I/O10
I/O10
I/O10
I/O10
I/O10
I/O10
GND_IO
I/O10
I/O10
I/O10
I/O10
I/O10
I/O10
VCC_IO
I/O10
O10
D_DQ[8]
91
data bus
VCC_IO4
D_DQ[6]
92
VCC I/O pads
data bus
93
D_DQ[9]
94
data bus
D_DQ[10]
D_DQ[4]
95
data bus
96
data bus
D_DQ[11]
D_DQ[3]
97
data bus
98
data bus
GND_IO5
D_DQ[12]
D_DQ[2]
99
GND I/O pads
data bus
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
data bus
D_DQ[13]
D_DQ[1]
data bus
data bus
D_DQ[14]
D_DQ[0]
data bus
data bus
VCC_IO5
D_DQ[15]
DSD_PCM_0
DSD_PCM_1
DSD_PCM_2
DSD_PCM_3
GND_IO6
DSD_PCM_4
DSD_PCM_5
DSD_PCM_6
DSD_PCM_7
DSD_PCM_8
VCC_IO6
VCC I/O pads
data bus
6-channel data output
6-channel data output
6-channel data output
6-channel data output
GND I/O pads
6-channel data output
6-channel data output
6-channel clock/control
6-channel clock/control
2-channel clock/control
VCC I/O pads
O10
O10
O10
GND_IO
O10
O10
O10
O10
O10
VCC_IO
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Table 2:
Pin description…continued
Symbol
Pin
119
120
121
122
123
124
125
126
127
128
Type[1]
Description
DSD_PCM_10
DSD_PCM_9
DSD_PCM_11
RESETn
H_A_sel
H_A[6]
O10
O10
O10
IN
2-channel data output
2-channel clock or control
2-channel data output
asynchronous reset; active LOW
address select
IN
IN
address bus
H_A[5]
IN
address bus
H_A[4]
IN
address bus
H_A[3]
IN
address bus
H_A[2]
IN
address bus
[1] Explanation of input and output ports:
IN: digital input port; all dedicated inputs are TTL tolerant.
IN1: digital input port with internal pull-up resistor.
I/O10: bidirectional port with 10 ns slew rate.
O10: 3-state (in test mode) output port with 10 ns slew rate.
APIO: analog input port.
VDDCO: analog VDD port (1.8 V).
VSSCO: analog VSS port.
GND_IO: ground for I/O pads.
VCC_IO: VCC for I/O pads (3.3 V).
GND_core: ground for core.
VCC_core: VCC for core (1.8 V).
7. Interfaces
7.1 Host interface
Different types of host busses are supported:
• Separate address/data bus with 16-bit data bus (3 different modes)
• Multiplexed address/data bus with 16-bit data bus (2 different modes)
• Separate address/data bus with 8-bit data bus (1 mode).
The host interface type is set via the dedicated pins H_sel and sys_clk. The
SAA7893HL has a dedicated interrupt output pin.
7.2 Front-end interface
7.2.1 Data input interface
The SAA7893HL supports three different front-end interfaces which are selectable
via the host interface:
• I2S-bus interface: the front-end interface is in essence an I2S-bus interface and
therefore, it has to conform to the I2S-bus specification.
• FEC interface
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• Parallel interface (UDE data interface part): a parallel front-end interface with a
handshake protocol.
7.2.2 Analog HF input
The analog HF input, coming from the optical pickup unit, is also fed to the
SAA7893HL to extract the copy protection information PSP.
7.3 Audio interface
7.3.1 Audio input
The audio input is a 6-channel PCM-I2S input.
7.3.2 DAC interface
The audio output is a 6-channel output and a separate stereo output. Both outputs
can be set in DSD and in PCM-I2S mode.
7.4 SDRAM interface
The SDRAM interface forms a glueless interface to one 64 Mbit SDRAM device.
Supported devices are only PC100 compliant or faster SDRAM devices:
• Organization: 64 Mbit (1M × 16 × 4 banks)
• Refresh period: 4096 cycles per 64 ms
• Clock frequency: fclk ≥ 100 MHz
• Refresh cycle: trcar ≤ 70 ns
• Command period: trc ≤ 70 ns.
7.5 Clock and reset input
Different processing clocks are needed in the SAA7893HL:
• sys_clk: system clock for data processing part; frequency can be between
27 and 35 MHz; see Figure 6 and Table 3
• aud_clk: audio clock reference; can be 256/384/512/768 × fs (fs = 44.1 to 48 kHz);
see Figure 7 and Table 4
• proc_clk: host processor clock (only used in SAD16_01/02 mode)
• B_BCLK: front-end bit/byte clock.
It is not required that these clocks are locked.
RESETn is an asynchronous reset and should be kept LOW for at least 10 periods of
sys_clk.
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Product data
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7.5.1 System clock (sys_clk) definitions
T
clk
t
t
clk(l)
clk(h)
MDB146
t
t
f
r
Fig 6. Sys_clk characteristics
Table 3:
Definitions of sys_clk
Symbol Parameter
Conditions
clock frequency from 27 to 35 MHz
Min
28.5
11.4
11.4
-
Max
37.4
22.4
22.4
4
Unit
ns
ns
ns
ns
ns
%
Tclk
tclk(l)
tclk(h)
tf
clock cycle time
clock time low
clock time high
fall time
tr
rise time
-
4
δclk
clock duty cycle
40
60
7.5.2 Audio clock (aud_clk) definitions
T
clk
t
t
clk(l)
clk(h)
MDB146
t
t
r
f
Fig 7. Aud_clk characteristics
Table 4:
Definitions of aud_clk
Symbol Parameter
Conditions
Min
Max
Unit
Tclk
clock cycle time
clock frequency from 256 × 44.1 kHz 27
to 768 × 48 kHz
88.6
ns
tclk(l)
tclk(h)
tf
clock time low
clock time high
fall time
10.8
53.1
53.1
4
ns
ns
ns
ns
%
10.8
-
tr
rise time
-
4
δclk
clock duty cycle
40
60
7.6 Test inputs
Standard BST functionality is provided. Device data:
Version: B0010
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Manufacturer ID: B000 0001 0101
Part no: B0011 0101 0110 0100.
8. Host interface
8.1 General description
The SAA7893HL is capable to communicate with the hosts (families) via their own
busses as given in Table 5.
Table 5:
Name
Host communications
Description
SAD16_01
Separate Address/Data on 16-bit data bus with wait signal, based on
proc_clk
SAD16_02
Separate Address/Data on 16-bit data bus with wait signal, based on
sys_clk and proc_clk
SAD16_03
MAD16_01
MAD16_02
SAD08
Separate Address/Data on 16-bit data bus without wait signal
Multiplexed Address/Data on 16-bit data bus mode 01
Multiplexed Address/Data on 16-bit data bus mode 02
Separate Address/Data on 8-bit data bus
The type of host is selected via two input pins H_sel[1] and H_sel[0] and the proc_clk
signal. In Table 6 the settings for the different host modes are given with the expected
input clock(s).
Table 6:
Clock selection
Mode
H_sel[1:0]
External provided clocks
Internal used
system clock
sys_clk
no
proc_clk
yes
00
10
01
11
11
01
SAD16_01
SAD16_02
SAD16_03
MAD16_01
MAD16_02
SAD08
proc_clk/2
sys_clk
sys_clk
sys_clk
sys_clk
sys_clk
yes
yes
yes
logic 1
logic 0
logic 1
logic 0
yes
yes
yes
In all modes the range of the required internal system clock is between
27 and 35 MHz.
The pin mapping in the different modes is shown in Table 7.
Table 7:
Host communication data mapping
SAA7893HL name Type SAD16_01;
SAD16_02
SAD08
MAD16_01
MAD16_02
SAD16_03
H_A_sel
H_A[3:1]
H_A[4]
IN
IN
IN
IN
I/O
CPU_A(7)
A(11)
A(3:1)
A(4)
ALE
ALE
LA(7)
CPU_A(4:1)
CPU_A(4:1)
CPU_A(6:5)
CPU_D(7:0)
LA(2:0)
LA(3)
addr[3:1]
n.c.
LA(3:1)
LA(4)
H_A[6:5]
H_DQ[7:0]
A(6:5)
D(7:0)
AD(21:20)
AD(11:4)
n.c.
LA(6:5)
LD(7:0)
data(7:0)
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Table 7:
Host communication data mapping…continued
SAA7893HL name Type SAD16_01;
SAD16_02
SAD08
MAD16_01
MAD16_02
SAD16_03
H_DQ[11:8]
H_DQ[12]
H_DQ[13]
H_DQ[14]
H_DQ[15]
H_IRQn
I/O
I/O
I/O
I/O
I/O
O
CPU_D(11:8)
CPU_D(12)
CPU_D(13)
CPU_D(14)
CPU_D(15)
IRQN
A(10:7)
n.c.
AD(1512)
AD(16)
AD(17)
AD(18)
AD(19)
IRQN
data(11:8)
data(12)
data(13)
data(14)
data(15)
IRQN
LD(11:8)
LD(12)
LD(13)
LD(14)
LD(15)
IRQN
ASn
DSn
A(0)
IRQn
logic 0
PCI-clk
R/Wn
DSACKn
CS
H_procclock
sys_clk
IN
IN
IN
O
CPU_procclk
n.c.; sysclk
CPU_RWn
CPU_wait
CPU_CSn
0
logic 0
Sclk
logic 1
logic 1
sys_clk
RD_
sys_clk
RD_
H_RWn
RD_
H_WAITn
H_CSn
ACK
HDTACKn
CSn
n.c.
IN
IN
IN
XIO
CSn
H_sel[0]
logic 1
logic 1
logic 1
logic 1
logic 1
logic 0
H_sel[1]
logic 0: mode 1; logic 0
logic 1: mode 2
logic 1
The internal SAA7893HL address is differently composed in the different modes.
8.2 SAD16_01/02 mode
Reading and writing is always done on 16 bits (Hword) base. To save physical pins on
the SAA7893HL, the data bus is used to write the 16 MSB address bits, hereafter
called ‘the base address’ into the SAA7893HL. Therefore, to access an address
inside the SAA7893HL first these 16 MSB bits of the address must be written as a
base address for the SAA7893HL indicated by the H_A_sel line. Pin H_A_sel can be
mapped to a physical address pin of the host device.
indication of an access to
the base address
H_CSn
H_A_sel
H_RWn
H_A[6:1]
A(6:1)
A(6:1)
H_DQ[15:0]
A(22:7)
D(15:0)
D(15:0)
MCE038
write base address
Fur_base = A(22:7)
write/read on SAA7893HL address
locations Fur_A[22:1] = Fur_base&A(6:1)
Fig 8. Write to or read from the SAA7893HL.
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In Figure 8 the principle of first writing the base address indicated by H_A_sel is here
visualized. Pin H_A_sel is mapped on address pin H_A[7] of the host. The timing is,
of course, not to scale. When the base address is written, multiple accesses can be
done whereby the different LSB addresses are mapped on pins H_A[6:1]. In this way
a burst of 64 Hwords can be read or written to the same address. The 16 bits base
address can be read when H_A_sel is logic 1 and the signal H_RWn indicates a read
operation.
Remark: The H_waitn signal is synchronized to H_procclock (pin 18). So it depends
on the host used which H_procclock is provided. When the host can accept an
asynchronous H_waitn signal, the clock signal connected to the sys_clk input (pin 21)
can also be used as the clock signal to the H_procclock input.
8.2.1 Write mode: minimum cycle
t
tot
H_CSn
t
t
h
su
H_RWn
H_DQ[15:0]
H_A[6:1]
H_A_sel
H_WAITn
MBL622
Fig 9. Timing diagram of writing registers with no wait cycles.
Table 8:
Timing numbers of writing registers with no wait cycles
Symbol Parameter
Min
14
-
Typ
Max Unit
ttot
tsu
total CSn time
-
-
-
sys_clk
ns
set-up time from CS to host control/address
lines
30
th
hold time from CS to host control/address lines
0
-
-
ns
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8.2.2 Read mode: minimum cycle
t
tot
H_CSn
H_RWn
t
t
h
su
H_A[6:1]
H_A_sel
t
tri
t
h(D)
Z
Z
undefined
data
H_DQ[15:0]
H_WAITn
t
set
MBL633
Fig 10. Timing diagram of reading registers with no wait cycles.
Table 9:
Timing numbers of reading registers with no wait cycles
Conditions
Symbol Parameter
Min
14
0
Typ
Max Unit
ttot
tsu
total CSn time
-
-
-
sys_clk
ns
set-up time from CS to host control/address
lines
30
th
hold time from CS to host control/address lines maximum time is not
needed; can be forever
0
-
-
ns
ttri
time that data bus is set from 3-state to output
time that data is valid before CS is set to logic 1
hold time from CS to data bus
1
-
-
-
3
-
sys_clk
ns
tset
th(D)
60
0
-
ns
8.2.3 Write mode: cycles extended using wait protocol
t
tot
H_CSn
t
t
h
su
H_RWn
H_DQ[15:0]
H_A[6:1]
H_A_sel
t
wt
t
t
wt(en)
wt(st)
H_WAITn
MBL635
Fig 11. Timing diagram of writing registers with wait cycles.
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Table 10: Timing numbers of writing registers with wait cycles
Symbol Parameter
Conditions
Min
14
0
Typ
Max Unit
ttot
tsu
total CSn time
-
-
-
sys_clk
set-up time from CS to host control/address
lines
30
ns
th
hold time from CS to host control/address lines
0
3
-
-
ns
twt
active time of H_WAIT when Pi registers are
accessed
speed is dependent on load
on PI-bus
8
11
sys_clk
active time of H_WAIT when external SDRAM is speed is dependent on load
3
11
17
sys_clk
accessed
on PI-bus
twt(st)
time from CS until wait becomes active
time H_WAIT inactive until CS becomes inactive
5[1]
10
-
-
6[1]
-
sys_clk
ns
twt(en)
[1] When the SAA7893HL SAD16 interface is programmed to generate always a H_WAIT signal, the minimum time will be 2 sys_clk cycles
and the maximum time will be 3 sys_clk cycles.
8.2.4 Read mode: cycles extended using wait protocol
t
tot
H_CSn
t
t
h
su
H_RWn
H_A[6:1]
H_A_sel
t
t
h(D)
tri
t
set
data
Z
Z
undefined
H_DQ[15:0]
H_WAITn
t
wt
t
t
wt(st)
wt(en)
MBL636
Fig 12. Timing diagram of reading registers via PI-bus.
Table 11: Timing numbers of reading registers via PI-bus
Symbol Parameter
Conditions
Min
Typ
Max Unit
ttot
tsu
total CSn time
14[1]
-
-
-
sys_clk
ns
set-up time from CS to host control/address
lines
0
30
th
hold time from CS to host control/address lines
0
3
-
-
ns
twt
active time of H_WAIT when Pi registers are
accessed
speed is dependent on load
on PI-bus
8
11
sys_clk
active time of H_WAIT when external SDRAM is speed is dependent on load
3
11
-
17
sys_clk
sys_clk
accessed
on PI-bus
twt(st)
time from CS until wait becomes active
5[2]
6[2]
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Table 11: Timing numbers of reading registers via PI-bus…continued
Symbol Parameter
twt(en) time from H_WAIT negative slope to data set-up
ttri
Conditions
Min
-
Typ
Max Unit
-
-
-
-
0
3
-
ns
time that data bus is set from 3-state to output
time that data is valid before CS is set to logic 1
hold time from CS to H_data bus
1
sys_clk
ns
tset
30
0
th(D)
-
ns
[1] When the SAA7893HL SAD16 interface is programmed to generate always a H_WAIT signal of at least 7 sys_clk cycles, then it is no
longer required that the minimum time of ttot is 14 sys_clk cycles. The data at the H_DQ output is always available at the negative edge
of the H_WAIT signal. The host can deactivate the H_CS signal after the negative edge of the H_WAIT signal and when it has read the
data at the H_DQ lines. When a H_WAIT signal is always generated then the timing diagrams in Figure 9 and Figure 10 are no longer
applicable.
[2] When the SAA7893HL SAD16 interface is programmed to generate always a H_WAIT signal, the minimum time will be 2 sys_clk cycles
and the maximum time will be 3 sys_clk cycles.
8.2.5 Host interface connection
SAD16_01
mode
SAA7893HL
26
24
27
CPU_RW
H_RWn
CE2n
H_CSn
CPU_WAIT
H_WAIT
10
kΩ
123
CPU_ADDR(7)
H_A_sel
H_A[6:1]
124, 125, 126,
127, 128, 1
CPU_ADDR(6:1)
2, 3, 5, 6, 7, 8, 9,
11, 12, 13, 14,
15, 16, 22, 23, 25
CPU_ADDR(15:0)
CPU_PROCCLK
IRQ_x
H_DQ[15:0]
H_procclk
H_IRQn
18
28
21
GND_IO
sys_clk
H_sel[0]
H_sel[1]
62
GND_IO
63
GND_IO
MCE039
Fig 13. Host interface connection.
8.3 SAD16_03 mode
To save physical pins on the SAA7893HL, the data bus is used to write the 16 MSB
address bits, hereafter called ‘the base address’, into the SAA7893HL. Therefore, to
access an address inside the SAA7893HL first this 16 MSB bits of the address must
be written as a base address for the SAA7893HL indicated by the H_A_sel line.
Pin H_A_sel can be mapped to a physical address pin of the host device.
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indication of an access to
the base address
H_CSn
H_A_sel
H_RWn
H_A[6:1]
A(6:1)
A(6:1)
H_DQ[15:0]
A(22:7)
D(15:0)
D(15:0)
MCE038
write base address
Fur_base = A(22:7)
write/read on SAA7893HL address
locations Fur_A[22:1] = Fur_base&A(6:1)
Fig 14. Write to or read from the SAA7893HL.
In Figure 14 the principle of first writing the base address indicated by H_A_sel is
here visualized. Pin H_A_sel is mapped on address pin H_A[7] of the host. The
timing is of course not to scale. When the base address is written, multiple accesses
can be done whereby the different LSB addresses are mapped on pins H_A[6:1]. In
this way a burst of 64 Hwords can be read or written to the same address. The 16 bits
base address can be read when H_A_sel is logic 1 and the signal H_RWn indicates a
read operation. In SAD16_03 mode there is in principle no handshake available.
Therefore, to read data a double read must be done.
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8.3.1 Read mode
indication of an access to
the base address
H_CSn
t
wt
H_A_sel
H_RWn
H_A[6:1]
A(6:1)
undefined
H_DQ[15:0]
A(22:7)
undefined
D(15:0)
MCE040
write base address
Fur_base = A(22:7)
data is read indicated by H_A_sel
read ’indication’ on SAA7893HL address
locations Fur_A[22:1] = Fur_base&A(6:1)
Fig 15. Read from the SAA7893HL.
First the 16 bits of the base address are set indicated by the H_A_sel line. Then a
read access is started. In SAD16_03 mode there is no handshake line on which the
SAA7893HL can indicate that internal read operation is ready. Therefore, to be sure
that the requested data is read correctly, an extra read is needed indicated by the
H_A_sel line. In this read the data is presented as read by the previous read access.
The maximum time that the host must wait before this extra read is started is
approximately 30 sys_clk cycles. If in this time a new access is activated this access
can be lost.
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8.3.2 Write mode
indication of an access to
the base address
H_CSn
t
wt
H_A_sel
H_RWn
H_A[6:1]
undefined
A(6:1)
H_DQ[15:0]
A(22:7)
D(15:0)
write base address
Fur_base = A(22:7)
write on SAA7893HL address locations
Fur_A[22:1] = Fur_base&A(6:1)
MCE041
Fig 16. Write to the SAA7893HL.
When a write operation is issued the same wait time twt must be taken into account
before a next access may start, but here no double write has to be done.
8.3.3 Writing of base address
t
t
wt
tot
H_CSn
H_RWn
t
t
h
su(rw)
H_A_sel
H_A[6:1]
t
su(ad)
undefined
address[22:7]
H_DQ[15:0]
MCE042
Fig 17. Timing diagram of writing the base address.
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Table 12: Timing numbers of base address writing
Symbol Parameter
Conditions
Min
Max Unit
ttot
twt
total LOW time of H_CSn
270
-
-
ns
ns
wait time before next cycle may start
if in this time a new cycle is started, 100
the new access cycle could be
neglected
tsu(rw)
tsu(ad)
set-up time of H_RWn
set-up time for address
-
-
0
ns
ns
10
8.3.4 Writing data to the SAA7893HL
t
t
wt
tot
H_CSn
t
t
h
su(rw)
H_RWn
H_A_sel
t
su(ad)
H_A[6:1]
address[6:1]
data[15:0]
H_DQ[15:0]
MCE043
Fig 18. Writing data to the SAA7893HL.
Table 13: Timing numbers of writing data
Symbol Parameter
Conditions
Min
Max Unit
ttot
twt
total LOW time of H_CSn
270
-
-
ns
ns
wait time before next cycle may start
if in this time a new cycle is started, 700
the new access cycle could be
neglected
tsu(rw)
tsu(ad)
th
set-up time of H_RWn
set-up time for address
-
0
ns
ns
ns
-
10
-
hold time of H_RWn/address/data with respect
to H_CSn
0
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8.3.5 Reading data from the SAA7893HL
t
t
t
tot
wt
tot
H_CSn
H_RWn
t
t
su(rw)
h
H_A_sel
H_address(6:1)
H_data
t
su(ad)
H_a(6:1)
don’t care
t
t
h(D)
d(tri)
Z
Z
undefined
data
MCE044
Fig 19. Reading data from the SAA7893HL.
Table 14: Timing numbers of reading data
Symbol Parameter
Conditions
Min
Max Unit
ttot
twt
total LOW time of H_CSn
270
-
-
ns
ns
wait time before next cycle may start
if in this time a new cycle is started, 700
the new access cycle could be
neglected
tsu(rw)
tsu(ad)
ttri
set-up time of H_RWn
-
-
0
ns
set-up time for address
time that data bus is enabled
10
3
ns
time dependent on system clock
1
sys_clk
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8.3.6 Host interface connection
SAD16_03
mode
SAA7893HL
26
24
27
RD_
CSn
H_RWn
H_CSn
n.c.
H_WAIT
123
LA(7)
H_A_sel
H_A[6:1]
124, 125, 126,
127, 128, 1
LA(6:1)
2, 3, 5, 6, 7, 8, 9,
11, 12, 13, 14,
15, 16, 22, 23, 25
H_DQ[15:0]
H_IRQn
LD(15:0)
IRQ_x
28
18
VCC_IO
H_procclk
21
sys_clk
H_sel[0]
H_sel[1]
62
VCC_IO
sys_clk or
video clock
63
GND_IO
MCE045
Fig 20. Host interface connection.
8.4 MAD16_01 mode
Data communication is here always done on a 16-bit data bus. The address is
mapped on 6 separate address pins and 16 address/data pins of the SAA7893HL.
Therefore, in this mode the complete address is transferred directly in each access
cycle.
In Table 7 the internal SAA7893HL address is mapped as follows to the SAA7893HL
pins: Fur_H_A[22:1] = H_A[6:5] & H_DQ[15:0] & H_A[4:1].
This address mapping is the default setting, the following address is also possible:
Fur_H_A[22:1] = H_A[6:1] & H_DQ[15:0].
The system clock provided in the MAD16_01 mode must be synchronized to the host
interface timing.
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8.4.1 Write mode: minimum cycle
sys_clk
t
tot
H_CSn
t
rd
H_A_sel
H_RWn
H_WAIT
t
su
t
h
addr
H_A[6:1]
addr
data
H_DQ[15:0]
MBL637
t
dw
Fig 21. Timing diagram writing to the SAA7893HL.
Table 15: Timing numbers of writing registers
Symbol Parameter
Min
8
Max
Unit
ttot
tsu
total H_CSn time
-
sys_clk
ns
set-up time H_A_sel
5
-
th
hold time of H_A_sel with respect to sys_clk
time H_RWn can change from H_CSn signal
data set-up time after H_CSn
5
-
ns
trd
-
1
1
sys_clk
sys_clk
tsu(D)
0
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8.4.2 Read mode: minimum cycle
sys_clk
H_CSn
t
rd
H_A_sel
H_RWn
H_WAIT
t
su
t
h
addr
H_A[6:1]
addr
data
H_DQ[15:0]
MBL638
t
dr
Fig 22. Timing diagram reading from the SAA7893HL.
Table 16: Timing numbers of reading registers
Symbol Parameter
Conditions
Min
5
Max
Unit
ns
tsu
th
set-up time H_A_sel
-
-
hold time of H_A_sel with respect to
sys_clk
5
ns
trd
time H_RWn can change from H_CSn
signal
-
1
sys_clk
tdr
data set-up time after CSn
data hold time before CSn
time dependent on system clock used
6
-
8
-
sys_clk
ns
tdc
not important data is sample after
detecting H_CSn = logic 0
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8.4.3 Write mode: cycles extended using wait protocol
sys_clk
t
tot
H_CSn
t
rd
H_A_sel
H_RWn
H_WAIT
t
su
t
h
addr
H_A[6:1]
addr
data
H_DQ[15:0]
MBL639
t
t
t
wt
dw1
dw2
Fig 23. Timing diagram writing to the SAA7893HL (with wait cycles).
Table 17: Timing numbers of writing registers (with wait cycles)
Symbol Parameter
Conditions
Min
8
Max
Unit
sys_clk
ns
ttot
tsu
th
total H_CSn time
-
-
-
set-up time H_A_sel
5
hold time of H_A_sel with respect to
sys_clk
5
ns
trd
time H_RWn can change from H_CSn
signal
-
1
sys_clk
tdw1
tdw2
data set-up time after H_CSn
time dependent on system clock used
1
2
3
6
sys_clk
sys_clk
time H_WAIT is activated after H_CSn dependent on SAA7893HL settings
is activated
twt
total time wait can be active
2
24
sys_clk
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8.4.4 Read mode: cycles extended using wait protocol
sys_clk
H_CSn
t
rd
H_A_sel
H_RWn
H_WAIT
t
su
t
h
addr
H_A[6:1]
addr
data
H_DQ[15:0]
MBL640
t
t
t
ac
dw
wt
Fig 24. Timing diagram reading from the SAA7893HL (with wait cycles).
Table 18: Timing numbers of reading registers (with wait cycles)
Symbol Parameter
Min
8
Max
Unit
sys_clk
ns
ttot
tsu
th
total H_CSn time
-
-
-
set-up time H_A_sel
5
hold time of H_A_sel with respect to
sys_clk
5
ns
trd
time H_RWn can change from H_CSn
signal
-
1
5
sys_clk
sys_clk
tdw
time H_WAIT is activated after H_CSn is
activated
dependent on SAA7893HL settings 2
twt
tac
total time wait can be active
2
1
24
-
sys_clk
sys_clk
data active until H_CSn is deactivated
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8.4.5 Host interface connection
MAD16_01
mode
SAA7893HL
26
24
XIO_x
H_RWn
XIO_x
H_CSn
VCC_IO
10
kΩ
27
X_ACK
ALE
H_WAIT
H_A_sel
123
124, 125, 126,
127, 128, 1
AD(21:16)
H_A[6:1]
2, 3, 5, 6, 7, 8, 9,
11, 12, 13, 14,
15, 16, 22, 23, 25
AD(15:0)
H_DQ[15:0]
sys_clk
21
28
SCLK
IRQ_x
H_IRQn
18
GND_IO
H_procclk
H_sel[0]
H_sel[1]
62
VCC_IO
63
VCC_IO
MCE046
Fig 25. Host interface connection.
8.5 MAD16_02 mode
In the MAD16_02 mode there is a 16-bit combined address/data bus and a dedicated
3-bit address bus.
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H_CSn
H_A_sel
H_RWn
ha[22:20]
ha[3:1]
H_A[3:1]
H_WAITn
H_DQ[15:0]
ha[19:4]
Z
undefined
data[15:0]
Z
MCE047
Fig 26. Principle read.
The multiplexing of the address/data pins is done as a regular host communication,
meaning that during a read or write the host must automatically generate the timing
according to Figure 26. It is not needed that the provided system clock is a
synchronous clock with respect to the H_A_sel line.
8.5.1 Write mode
t
tot
H_CSn
t
t
h(cs)
su
H_A_sel
t
h(ad)
H_RWn
ha[3:1]
ha[22:20]
ha[19:4]
H_A[3:1]
H_DQ[15:0]
data[15:0]
t
dw1
t
wt
H_WAITn
MCE048
Fig 27. Timing diagram writing to the SAA7893HL.
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Table 19: Timing numbers of MAD16_02 write
Symbol Parameter
Min
Max
Unit
ns
ttot
th
total LOW time of H_CSn
300 + twt
10
-
-
hold time of address/data with respect to
H_A_sel
ns
tdw1
twt
wait time until H_WAIT is activated
time of H_WAIT signal
2
2
-
5
sys_clk
sys_clk
ns
24
10
tsu
set-up time of H_RWn/address with respect to
H_CSn
8.5.2 Read mode
t
tot
H_CSn
H_A_sel
t
h
H_RWn
H_A[3:1]
ha[22:20]
ha[3:1]
t
t
wt
su
t
H_WAITn
H_DQ[15:0]
t
dw1
t
tri
set(D)
ha[19:4]
Z
undefined
data[15:0]
MCE049
Fig 28. Timing diagram reading from the SAA7893HL.
Table 20: Timing numbers of MAD16_02 read
Symbol Parameter
Min
8 + twt
-
Typ
Max
Unit
ns
ttot
tsu
total H_CSn time
-
-
-
set-up time of address/data/H_RWn with
respect to H_CSn
0
ns
th
hold time of address with respect to
H_A_sel falling edge
10
-
-
-
-
ns
tdw1
time H_WAIT is activated after H_CSn is
activated
4
sys_clk
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Table 20: Timing numbers of MAD16_02 read…continued
Symbol Parameter
Min
Typ
Max
Unit
ttri
time data bus becomes active after
H_CSn
-
2
-
sys_clk
tset(D)
twt
time data available with respect to
H_WAIT signal
15
2
-
-
-
ns
time H_WAIT can be active
24
sys_clk
8.5.3 Host interface connection
MAD16_02
mode
SAA7893HL
26
24
27
RD_
H_RWn
CSn
H_CSn
HDTACKn
H_WAIT
123
ALE
H_A_sel
H_A[6:4]
H_A[3:1]
124, 125, 126
n.c.
127, 128, 1
ADDR(3:1)
2, 3, 5, 6, 7, 8, 9,
11, 12, 13, 14,
15, 16, 22, 23, 25
H_DQ[15:0]
H_IRQn
DATA(15:0)
IRQ_x
28
18
VCC_IO
H_procclk
21
sys_clk
H_sel[0]
H_sel[1]
62
VCC_IO
sys_clk or
video clock
63
VCC_IO
MCE050
Fig 29. Host interface connection.
8.6 SAD08 mode
Here the reading and writing is always done on 8-bit. From pin mapping it can be
seen that the byte indication is done via bit A(0) which is mapped on H_DQ(15) of the
SAA7893HL. The internal SAA7893HL communication stays on 16-bit. Therefore, the
host interface block ‘translates’ the 8 bits external communication to the 16 bits
internal. To save physical pins on the SAA7893HL device, the data bus and 4 address
bits are used to write the 12 MSB address bits, hereafter called ‘the base address’,
into the SAA7893HL device. Therefore, to access an address inside the SAA7893HL
first this 12 MSB bits of the address must be written as a base address for the
SAA7893HL indicated by the H_A_sel line. Pin H_A_sel can be mapped to a physical
address pin of the host.
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8.6.1 Writing base address
indication of an access to
the base address
H_CSn
H_RWn
H_A_sel
H_A[6:1]
A(6:1)
LSB write/read
D(7:0)
A(6:1)
H_DQ[15]
H_DQ[7:0]
MSB write/read
D(15:8)
A(22:15)
H_DQ[11:8]
A(14:11)
A(10:7)
A(10:7)
MCE051
write base address
Fur_base = A(22:11)
write/read on SAA7893HL address
locations Fur_A[22:1] = Fur_base&A(10:1)
Fig 30. Base address writing.
In Figure 30 the writing of the base address and a Hword to the host is given in
SAD08 mode. First, the 12 bits base address is written indicated by H_A_sel line.
The SAA7893HL samples the base address on H_DQ(7:0) and H_DQ(11:8). After
that the normal write operation is performed as explained in Section 8.6.2.
8.6.2 Writing to the SAA7893HL
A write to address N of 16 bits to the SAA7893HL will be translated to two byte
accesses. First the LSB byte is written to address N [so A(0) = logic 0] and stored in
cache. Then the MSB byte is written to address N+1 [so A(0) = logic 1]. When the
SAA7893HL receives a write command at an odd address [A(0) = logic 1] always
16 bits are internally written whereby the Hword is composed of LSB byte in cache
and the MSB byte received at present write command. The SAA7893HL can be set to
big and little endian, whereby the described situation is the power-on state. Byte read
or write operations are not supported in SAD08 mode.
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sys_clk
t
h
t
su
H_CSn
H_DQ[11:8]
H_A[7:0]
address
t
h
H_RWn
t
d(as)
H_DQ[13]
data
H_DQ[7:0]
t
d(ds)
H_DQ[14]
H_WAIT
t
d
MBL641
M clock cycles
Fig 31. Timing diagram SAD08 write to SAA7893HL.
Table 21: Timing numbers of SAD08 write
Symbol Parameter
Conditions
Min
Max
Unit
tsu
set-up time from H_CSn, H_RWn and
5
-
ns
H_DQ(13) to sys_clk
th
hold time from clk to H_CSn, H_RWn
and H_DQ(13)
5
-
-
ns
td(as)
td(ds)
M
delay from H_CSn to negative slope of
H_DQ(13)
1
sys_clk
sys_clk
sys_clk
ns
delay from H_CSn to negative slope of
H_DQ(14) and data
-
2
number of clock cycles
dependent on access type and traffic
on PI-bus
4
2
15
12
td
delay from clk to DSACKn
8.6.3 Reading from the SAA7893HL
When the LSB is read [A(0) = logic 0], the host interface will read an Hword on the
address location A(22:1). The LSB byte is set on the output bus and the read MSB
byte is stored internally. When a read action is now started whereby the MSB byte is
selected to read [A(0) = logic 1] the stored byte is available on the output independent
on the other address bits A(22:1).
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sys_clk
t
h
t
su
H_CSn
H_DQ[11:8]
H_A[7:0]
address
t
h
H_RWn
H_DQ[13]
H_DQ[7:0]
data
t
dat
H_DQ[14]
H_WAIT
t
d
MBL623
N clock cycles
Fig 32. Timing diagram SAD08 read from the SAA7893HL.
Table 22: Timing numbers of SAD08 read
Symbol Parameter
Conditions
Min
Max
Unit
tsu set-up time from H_CSn, H_RWn
5
ns
and H_DQ[13] to sys_clk
th
hold time from clk to H_CSn, H_RWn
and H_DQ[13]
5
5
ns
N
number of clock cycles
dependent on access type and traffic
on PI-bus.
20
sys_clk
td
delay from clk to H_WAIT
2
-
12
0
ns
ns
tdat
data available before H_WAIT is
asserted
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8.6.4 Host interface connection
SAD08
mode
SAA7893HL
26
24
CPU_RW
H_RWn
CE2n
H_CSn
VCC_IO
10
kΩ
27
CPU_WAIT
XIO_ADDR(11)
XIO_ADDR(10:7)
H_WAIT
123
H_A_sel
7, 8, 9, 11
H_DQ[11:8]
124, 125, 126,
127, 128, 1
XIO_ADDR(6:1)
H_A[6:1]
2
H_DQ[15]
H_DQ[14]
H_DQ[13]
XIO_ADDR(0)
3
5
DS
AS
12, 13, 14, 15,
16, 22, 23, 25
H_DQ[7:0]
sys_clk
XIO_DATA(7:0)
21
28
18
PCI_CLK
IRQ_x
H_IRQn
H_procclk
H_sel[0]
H_sel[1]
GND_IO
62
63
VCC_IO
GND_IO
MCE052
Fig 33. Host interface connection.
8.7 Interrupt
The interrupt output is a LOW level interrupt which must be connected to the interrupt
input of the DVD host.
9. Front-end interface
First the SACD sector structure is explained and how to connect the SAA7893HL in
the different modes. For these different modes the interface timing figures will be
given.
The supported sector format interface is sketched in Figure 34.
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Byte 0 to 11
HEADER
12
Byte 12 to 2059
MAIN DATA
Byte 2060 to 2063
EDC
4
2048 stored in VBR
sector format
Byte 0
Byte 1 to 3
NUMBER
Byte 4 to 5
IED
Byte 6 to 11
CPSI
INFORMATION
MBL616
ID[31...24]
ID[23...0]
Fig 34. SACD sector format.
The SAA7893HL supports a data input bit rate of maximal 40 Mbits/s.
The connections to the SAA7893HL in the different front-end modes are given in
Table 23.
Table 23: Connection of different front-end interfaces
SAA7893HL
name
Type
I2S_mode
FEC
Parallel mode
B_FLAG
B_SYNC
B_WCLK
B_BCLK
B_DATA
IN
IN
IN
IN
IN
IN
IN
O
I2S_err
I2S_sync
I2S_wclk
I2S_bclk
I2S_data
n.c.[1]
n.c.[1]
SERR
OUT_SYNC
OUT_DVALID
OUT_CLK
OUT_DATA0
n.c.[1]
SYNC
SENB
SDCLK
MPEG(0)
MPEG(7:1)
UDE_req
REQ
Be_dat(7:1)
UDE_req
Data_req
n.c.[1]
n.c.[1]
n.c.
n.c.
[1] The n.c. input pins must be connected to VCC or GND.
9.1 I2S-bus interface
9.1.1 Input timing
In Figure 35 the functional input timing is given. Note that B_SYNC, B_FLAG are
sampled simultaneously with D11. Since B_FLAG indicates the error in a byte, it is
also sampled simultaneously with D3. The sampling moment during D11 for the high
byte (D15 to D8), sampling moment D3 for the low byte (D7 to D0).
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2
I S-bus half word
B_DATA
D1
D0
D15 D14 D13 D12 D11 D10
D9 D8 D7
D6
D5
D4
D3
D2
D1
D0
B_BCLK
B_WCLK
B_SYNC
B_FLAG
MBL617
Fig 35. Front-end input timing.
When the B_SYNC signal is set to logic 1 between bit position D15 and D11 the
SAA7893HL accepts this word as the start of a sector. The SAA7893HL does not
perform EDC checking on the main data, but is dependent on the B_FLAG. A sector
is set to erroneous if B_FLAG is set to logic 1.
9.1.2 Interface timing
B_BCLK
B_SYNC
B_FLAG
B_WCLK
B_DATA
MBL624
t
su
t
h
Fig 36. Timing in I2S-bus interface.
Table 24: Timing in I2S-bus interface
Symbol Parameter
Min
5
Unit
ns
tsu
th
set-up time to rising edge of the clock
hold time after rising edge of the clock
5
ns
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9.1.3 Interface connection
2
I S-BUS
SAA7893HL
front-end IC
46
44
43
42
45
B_BCLK
I2S_clk
I2S_wclk
I2S_sync
I2S_err
B_WCLK
B_SYNC
B_FLAG
B_DATA
I2S_dat
49-55
Be_dat(7:1)
UDE_req
Data_req
47
48
open
MCE053
Not used input pins must be connected to VCC or GND.
Fig 37. Front-end interface connection.
9.2 UDE data interface
In the SA-MP the synchronous parallel mode is supported. There are three types of
parallel data transfer modes supported:
• Synchronous mode (see Section 9.2.1)
• Asynchronous mode:
– Handshake to enable data transfer
– Handshake for every byte transfer.
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9.2.1 Parallel mode
t
t
clk(l)
clk(h)
B_BCLK
Data_req
t
h
t
h
t
su
B_WCLK
B_FLAG
B_SYNC
t
su
Be_dat(7:0)
MCE054
Fig 38. Timing diagram for UDE interface with level sync mode.
Polarity of Data_req, B_WCLK, B_FLAG and B_SYNC is programmable.
The UDE transmitter must react on the Data_req signal within 5 B_BCLK cycles. The
SAA7893HL samples the data on the positive slope of B_BCLK when the B_WCLK
signal is active.
When B_FLAG signal is active for one byte of the sector, the total sector will be
treated as erroneous.
The maximum clock frequency of B_BCLK is 20 MHz.
The Data_req line generated by the SAA7893HL is synchronized to the internal
sys_clk signal. Therefore, the Data_req line is asynchronous with respect to BCLK
line.
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B_BCLK
Data_req
t
h
t
h
t
su
B_WCLK
B_FLAG
B_SYNC
t
su
Be_dat(7:0)
MCE055
Fig 39. Timing diagram for UDE interface with sync edged triggered mode.
Polarity of Data_req, B_WCLK, B_FLAG and B_SYNC is programmable.
Table 25: Timing in synchronous parallel mode
Symbol Parameter
Conditions
Min
Max
Unit
tclk(h)(l)
HIGH/LOW time of the B_BCLK signal maximum clock frequency of B_BCLK 20
-
ns
is 20 MHz
tsu
th
set-up time to rising edge of the clock
data/control must be stable during tsu
before positive slope of B_BCLK
10
5
-
ns
ns
ns
hold time after rising edge of the clock data/control must be kept at least
during th after positive slope of B_BCLK
-
to
output delay from the clock
2
15
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9.2.2 Interface connection
UDE
front-end IC
SAA7893HL
46
44
43
42
B_BCLK
sdclk
senb
sync
serr
B_WCLK
B_SYNC
B_FLAG
B_DATA
Be_dat(7:1)
Data_req
UDE_req
45
data
req
49-55
48
47
DVD
back-end IC
with UDE
req
sdclk
senb
sync
serr
data
MCE056
Fig 40. Front-end interface connection.
9.3 FEC interface
This is a serial interface for communication to a special front-end IC.
bclk/
ser_bclk
be_dat(0)/
ser_data
bit
1
bit
2
bit
3
bit
4
bit
5
bit
6
bit
7
bit
8
bit
9
bit
10
bit
11
bit
12
bit
13
bit
14
bit
15
bit
16
wclk/
ser_valid
sync/
ser_sync
MBL619
Fig 41. FEC interface.
The timing diagram of the FEC interface is given in Figure 41. The first bit of a sector
is indicated by the sync signal; this is the MSB bit of the first byte of the header. The
sector error indication is in FEC mode indicated by two extra bytes at the end of the
sector. This means that the sector length is increased to 2066 bytes. The indication of
errors is as follows:
FF = error; 00 = no error.
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9.3.1 Timing
B_BCLK
B_SYNC
B_FLAG
B_WCLK
B_DATA
MBL624
t
su
t
h
Fig 42. Timing in FEC interface.
Table 26: Timing in FEC interface
Symbol Parameter
Min
10
5
Unit
ns
tsu
th
set-up time to rising edge of the clock
hold time after rising edge of the clock
ns
9.3.2 Interface connection
FEC
front-end IC
SAA7893HL
46
44
43
42
45
B_BCLK
ser_clk
ser_valid
ser_sync
B_WCLK
B_SYNC
B_FLAG
B_DATA
GND_IO
ser_dat
49-55
Be_dat(7:1)
UDE_req
Data_req
47
48
open
MCE057
Fig 43. Front-end interface connection.
10. HF input
10.1 General
On every SACD disc a PSP signal must be recorded. The player is only allowed to
play a disc if a valid PSP signal is detected. This PSP key is recorded via a special
mechanism in the EFM signal on disc. The EFM+ signal must be fed to the
SAA7893HL as shown in Figure 44.
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+1.8 V
V
DDA
10 nF
100 nF
12 kΩ
EFM+
Agcinp
Adcrefl
biasin
V
SSA
MBL620
Fig 44. Connection of EFM+ input.
The detection of the PSP key is dependent of the polarity of the EFM+ signal. The
SA-MP settings are that a pit on the disc must have a higher output voltage than the
land. The EFM+ input signal has no timing requirements with respect to the digital
input of the front-end interface of the SAA7893HL.
The SAA7893HL supports also an inversion of the EFM+ signal.
10.2 HF input specification
The AGC circuit must be able to handle the following signal characteristics of the
HF input signal.
Table 27: HF signal characteristics
HF
Value
Remark
Input range
Bandwidth
0.2 to 0.8 V (p-p)
9 MHz
HF input voltage
front-end running on
maximum speed needed for
SACD
The HF is AC-coupled via a capacitor of 10 nF to pin Agcinp. The internal resistance
of pin Agcinp is 1 MΩ.
Table 28: Signal connections
Pin name Description
Agcinp
biasin
Adcrefl
VSSA
HF output from pickup unit connected via a 10 nF couple capacitor
bias current; connect a 12 kΩ resistor to VSS (ground)
reference voltage for internal resistor trap; decouple with 100 nF to VSS (ground)
analog ground
VDDA
1.8 V analog power supply
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10.3 HF-input application diagram
+1.8 V
≥4.7
µF
100
nF
32
DDA
V
10 nF
100 nF
12 kΩ
EFM+
(0.2-0.8 V)
35
36
34
Agcinp
SAA7893HL
Adcrefl
biasin
V
SSA
33
MCE058
Fig 45. EFM input interface connection.
11. Audio interfaces
11.1 Audio input interface
The PCM-I2S audio input signals can be either directly couple, without any
processing to the DSD_PCM output lines, or further processed inside the
SAA7893HL. When directly coupled, only a combinatorial delay must be taken into
account; no dependency on any clock signal (see Section 11.1.1). The input signal
characteristics, when audio processing must be performed, are given in
Section 11.1.2.
11.1.1 Audio input directly coupled
When no processing is done inside the SAA7893HL with respect to the I2S-PCM
input stream, this input stream is sent via a multiplexer to the I2S-bus output paths. So
no clocking is done on this signal, meaning that also no locked audio clock needs to
be present.
input pin
t
d(as)
output pin
MBL627
Fig 46. Delay from input to output pin.
Table 29: Timing numbers in PCM audio
Symbol Parameter
Min
Typ
Max
Unit
td(as)
asynchronous delay
8
13
18
ns
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11.1.2 Audio input ‘with processing’
right channel
right surround
LFE
left channel
left surround
center
PCM_wclk_in
PCM_dclk_in
16/24/32/48 clock cycles
t
su
t
h
t
h
t
su
PCM_LeRi_in
PCM_LsRs_in
PCM_CeLf_in
MSB
1
2
3
22 LSB
MSB
1
2
3
MBL628
24 data bits
Fig 47. Audio I2S-bus input timing.
Table 30: Timing numbers in PCM audio
Symbol Parameter
Conditions
Min
Unit
tsu
set-up time to rising edge to the
pcm_dclk_in signal
in PCM-I2S mode, the data is always outputted on
the negative edge of the bit clock; so here data is
sampled on positive edge of the clock
8
ns
th
hold time after rising edge of the
pcm_dclk_in signal
in PCM-I2S mode, the data is always outputted on
the negative edge of the bit clock; so here data is
sampled on positive edge of the clock
5
ns
11.1.3 Interface connection
audio clock
256/384/512/768 x f
s
DVD
back-end IC
SAA7893HL
29
aud_clk
aud_clk_in
30
I2S_clk
PCM_dclk_in
31
I2S_wclk
I2S_leri
PCM_wclk_in
40
PCM_LeRi_in
39
I2S_Celfe
PCM_CeLf_in
41
PCM_LsRs_in
I2S_Isrs
MCE059
Fig 48. Audio I2S-PCM input interface connection.
11.2 Audio output interface
The 6-channel outputs can be either DSD format or PCM-I2S format. The
connections are given in Table 31.
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The SAA7893HL has 12 output lines: 8 lines are allocated for connection to a
6-channel DAC and 4 are for connection to a 2-channel DAC or a 75 Hz reference
signal. The DSD data on the MCH output lines are outputted 6412 clocks after the
positive edge of the 75 Hz signal, if no additional post-processing is done.
DSD_PCM_0
SA-MP
DSD_PCM_1
DSD_PCM_2
DSD_PCM_3
to 6-channel DAC
DSD_PCM_4
DSD_PCM_5
DSD_PCM_6
DSD_PCM_7
DSD_PCM_8
DSD_PCM_9
to 2-channel DAC
DSD_PCM_10
DSD_PCM_11
MBL621
Fig 49. SA-MP output line allocation.
The SA-MP delivers extra flexibility when connecting to different DAC types, which
can be: DSD only, PCM only or multi standard (DSD + PCM)]. In Table 31 the signal
allocation is given for the 6-channel output in DSD and in PCM-I2S mode.
Table 31: Connection to a 6-channel DAC
Output line
Pin
Mode = DSD
Mode = PCM
number
DSD_PCM_0
DSD_PCM_1
DSD_PCM_2
DSD_PCM_3
DSD_PCM_4
DSD_PCM_5
DSD_PCM_6
DSD_PCM_7
108
109
110
111
113
114
115
116
left channel
Lf + Rf; Ls + Rs; C + LFE; 0 or 1;
PCM data/word clock
right channel
center channel
LFE channel
left surround
right surround
Lf + Rf; Ls + Rs; C + LFE; 0 or 1;
PCM data/word clock
Lf + Rf; Ls + Rs; C + LFE; 0 or 1;
PCM data/word clock
Lf + Rf; Ls + Rs; C + LFE; 0 or 1;
PCM data/word clock
Lf + Rf; Ls + Rs; C + LFE; 0 or 1;
PCM data/word clock
Lf + Rf; Ls + Rs; C + LFE; 0 or 1;
PCM data/word clock
DSD clock or
0 or 1
PCM data/word clock
DSD clock or
0 or 1
PCM data/word clock
In Table 32 the signal allocation is given for the DSD/PCM signals to be connected to
the stereo DAC.
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Table 32: Connection to a 4-channel DAC
Output line
Pin
Mode = DSD
Mode = PCM
Mode = 75 Hz
number
DSD_PCM_8
DSD_PCM_9
DSD_PCM_10
DSD_PCM_11
117
120
119
121
DSD clock
0 or 1
PCM data/word clock 0 or 1
PCM data/word clock 0 or 1
left channel
right channel
Lf + Rf; 0 or 1
Lf + Rf; 0 or 1
75 Hz
0 or 1
Both tables show that DSD has a fixed allocation while PCM outputs are selectable.
The I2S-bus bit stream, generated by the SAA7893HL decimation filter, is in the
Philips format as can be seen in the timing diagrams. The number of data bits is
always 24.
Table 33: Serial bit clock frequency
Audio input
clock
I2S output ‘wclk’ DCLK (data bit)
Remark
frequency
frequency
256fs
2fs
4fs
2fs
4fs
128fs
256fs
384fs
128fs
no symmetrical bit clock
384fs
48 clocks for a word
identification
512fs
768fs
2fs
4fs
2fs
4fs
128fs
256fs
128fs
256fs
The wclk identification is always active for 32 clocks for each left and right sample,
except when the input clock is 384fs and the output sample frequency is 4fs; then the
wclk is 48 samples active.
11.2.1 DSD output
aud_clk
t
d(o)
dsd_clk (= 64f )
s
dsd_pcm-data
SAMPLE N
SAMPLE N + 1
MBL629
Fig 50. Audio I2S-bus output timing.
Remark: in this example timing of the aud_clk is 256 × fs and DSD clock phase is set
to logic 0. If phase is set to logic 1, the dsd_clk signal will be inverted.
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Table 34: Timing numbers in DSD audio
Symbol Parameter
Min
Max
Unit
td(o)
output delay time with respect to the audio clock
4
20
ns
11.2.2 I2S-PCM generated by the SAA7893HL
In Figure 51 and Figure 52 the timing diagrams are given when the internal PCM
generator of the SAA7893HL generates the I2S-PCM output signals.
right channel
right surround
LFE
left channel
left surround
center
pcm_wclk_out
pcm_dclk_out
t
wclk
32 pcm_dclk_out clock cycles
t
data
pcm_LeRi_out
pcm_LsRs_out
pcm_CeLf_out
MSB
1
2
3
22 LSB
MSB
1
2
3
MBL630
24 data bits
Fig 51. Audio I2S-bus output timing in Philips format.
left channel
left surround
center
right channel
right surround
LFE
t
wclk
32 clock cycles
t
data
MSB
1
2
3
22 LSB
MSB
1
2
3
MBL631
24 data bits
Fig 52. Audio I2S-bus output timing in left justified format.
Table 35: Timing numbers for PCM-I2S output
Symbol Parameter
Min
Max
Unit
twclk
pcm_wclk_out timing with respect to negative
−10
+10
ns
edge of pcm_dclk_out
tdata
pcm_data_out timing with respect to negative
edge of pcm_dclk_out
−10
+10
ns
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11.3 Audio output application diagrams
11.3.1 Hybrid DAC connection
hybrid
MCA DAC
dsd_left/
i2s_lfrf
SAA7893HL
108
sdata_ifrf
M_x
DSD_PCM_0
all slew rate
dsd_right/
’0’
controlled
109
output pins
(no serial
resistors needed)
DSD_PCM_1
DSD_PCM_2
DSD_PCM_3
DSD_PCM_4
dsd_centre/
i2s_celfe
110
111
113
114
115
116
sdata_celfe
M_x
dsd_lfe/
’0’
dsd_left_sur/
i2s_lsrs
sdata_Isrs
M_x
dsd_right_sur/
’0’
DSD_PCM_5
DSD_PCM_6
DSD_PCM_7
dsd_clk/
i2s_dclk
sclk
’0’/
i2s_wclk
mclk
wclk
dsd_clk/
i2s_dclk
117
120
119
121
sclk
hybrid
stereo DAC
DSD_PCM_8
DSD_PCM_9
DSD_PCM_10
DSD_PCM_11
’0’/
i2s_wclk
wclk
dsd_left_mix/
i2s_lmrm
sdata_Ifrf
M_x
dsd_right_mix/
’0’
mclk
aud_clk
MCE060
29
audio clock
Fig 53. Hybrid DAC interface connection.
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11.3.2 DSD DAC connection
DSD
MCA DAC
SAA7893HL
dsd_left
108
109
110
111
113
114
115
116
dsd_left
dsd_right
dsd_centre
dsd_lfe
dsd_ls
DSD_PCM_0
dsd_right
dsd_centre
dsd_lfe
DSD_PCM_1
DSD_PCM_2
DSD_PCM_3
DSD_PCM_4
dsd_left_sur
dsd_right_sur
dsd_rs
DSD_PCM_5
DSD_PCM_6
DSD_PCM_7
dsd_clk
sclk
n.c.
mclk
dsd_clk
117
120
119
121
dsd_clk
DSD
stereo DAC
DSD_PCM_8
DSD_PCM_9
DSD_PCM_10
DSD_PCM_11
n.c.
dsd_left_mix
dsd_left
dsd_right_mix
dsd_right
mclk
aud_clk
MCE061
audio clock
29
Fig 54. DSD DAC interface connection.
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11.3.3 PCM DAC connection
PCM
MCA DAC
SAA7893HL
i2s_lfrf
i2s_celfe
i2s_lsrs
108
109
110
111
113
114
115
116
sdata_lfrf
DSD_PCM_0
n.c.
n.c.
n.c.
DSD_PCM_1
DSD_PCM_2
DSD_PCM_3
DSD_PCM_4
sdata_celfe
sdata_lsrs
DSD_PCM_5
DSD_PCM_6
DSD_PCM_7
i2s_dclk
i2s_wclk
sclk
wclk
mclk
i2s_dclk
i2s_wclk
117
120
119
121
sclk
PCM
stereo DAC
DSD_PCM_8
DSD_PCM_9
DSD_PCM_10
DSD_PCM_11
wclk
i2s_lmrm
sdata_lfrf
n.c.
mclk
aud_clk
MCE062
audio clock
29
Fig 55. PCM DAC interface connection.
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12. SDRAM interface
12.1 Writing
clk
t
d
D_clk
t
t
cmd
D_RASn
D_CASn
D_Wen
nop
XX
active
write
precharge
XX
addr
D_ADDR[13:0]
address
address
t
dqm
D_UDQM
D_LDQM
upper/lower
byte
t
data
D_DQ[15:0]
ZZZZ
data
ZZZZ
MBL632
Fig 56. SDRAM interface writing.
Table 36: Timing numbers of SDRAM interface writing
Symbol Parameter Conditions
Min
3
Max
9
Unit
ns
td
delay from clk to D_clk of SDRAM interface D_clk is clock of SDRAM
delay from clk to control signals
tcmd
taddr
tdqm
1
15
15
12
ns
delay from clk to address lines
1
ns
delay from clk to D_UDQM and D_LDQM
signals
1
ns
tdata
delay from clk to data output signals
1
12
ns
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12.2 Reading
clk
t
d
D_clk
t
t
cmd
D_RASn
D_CASn
D_Wen
nop
active
read
nop
nop
nop
precharge
addr
D_ADDR[13:0]
address
address
t
dqm
D_UDQM
D_LDQM
upper/lower
byte
t
su
t
h
data to
SAA7893HL
D_DQ[15:0]
MBL634
Fig 57. SDRAM interface reading.
Table 37: Timing numbers of SDRAM interface reading
Symbol Parameter Conditions
Min
3
Max
9
Unit
ns
td
delay from clk to D_clk of SDRAM interface D_clk is clock of SDRAM
delay from clk to control signals
tcmd
taddr
tdqm
1
15
15
12
ns
delay from clk to address lines
1
ns
delay from clk to D_UDQM and D_LDQM
signals
1
ns
tsu
th
set-up time of data to clk
hold time of data from clk
3
3
-
-
ns
ns
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12.3 Interface connection
+3.3 V
64 Mbit SDRAM
CKE
SAA7893HL
D_DQ[15:0]
DQ(15:0)
A(11:0)
BA0
D_ADDR[11:0]
D_ADDR[12]
D_ADDR[13]
78
75
81
82
80
86
88
89
BA1
RAS_
CAS_
WE_
D_RASn
D_CASn
D_Wen
CLK
D_clk
D_UDQM
D_LDQM
DQMH
DQML
CS_
MCE063
Fig 58. SDRAM interface connection.
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13. Power supply connections
SAA7893HL
10
VCC_IO1
100
nF
4.7
µF
100
nF
4
GND_IO1
VCC_IO7
37
100
nF
38
58
GND_IO7
VCC_IO2
100
nF
17
76
GND_IO2
VCC_IO3
100
nF
69
92
3.3 V
GND_IO3
VCC_IO4
100
nF
83
GND_IO4
VCC_IO5
106
100
nF
99
GND_IO5
VCC_IO6
118
100
nF
112
19
GND_IO6
100 MHz
coil
3.3 to 1.8 V
VCC_Core1
CONVERTOR
(LF18CD)
100
nF
4.7
µF
4.7
µF
100
nF
20
85
GND_Core1
VCC_Core2
100
nF
84
32
100 MHz
coil
GND_Core2
3.3 to 1.8 V
CONVERTOR
(LF18CD)
V
DDA
100
nF
4.7
µF
4.7
µF
100
nF
33
V
SSA
MCE064
Fig 59. Power supply connections.
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14. Software API
14.1 API provided by SA-MP
Table 38: API provided by SA-MP
Name
Description
Playback API
NAV_AreaSwitch
NAV_PlayTrack
NAV_PlayAtTimecode
NAV_Stop
Switch SACD Area
Start playing at the index of the track
Start playing at the given time
Stop playback
NAV_Pause
Pause playback
NAV_ResumePlay
NAV_NextTrack
NAV_PreviousTrack
NAV_Repeat
Resume playback at normal speed
Continue with next track
Continue with previous track
Set the repeat mode for playback
Set the repeat AB mode
NAV_RepeatAB
NAV_Shuffle
Play tracks in random order
Play only intro part of each track
Start scanning forward – fast playback with burst sound
NAV_IntroScan
NAV_ForwardScan
NAV_BackwardScan
Start scanning backward – fast playback with burst
sound
NAV_SetPlaySequence
NAV_SetProgramList
NAV_GetState
Set play sequence mode
Set program list
Returns navigator states
Returns navigator play list
NAV_GetPlayList
Post-processing API
APM_SetSpeakers
APM_SetInputMode
APM_SetOutputMode
APM_Set6chDownMix
APM_Set2chDownMix
APM_SetBassFilters
APM_SetAttenuation
APM_SetDelay
Select speaker configuration
Select between DSD or PCM as APM input
Select APM output mode (DSD or PCM)
Set the downmix of six-channel output stream
Set the downmix of two-channel output stream
Select the bass management frequency and slope
Set attenuation of an output channel
Set delay of a channel of output stream
Set Sigma Delta modulator filter mode
Set the PCM upsampling mode
APM_SetFilterMode
APM_SetPcmUpsampling
APM_SetPIO
Set the DAC PIO pins
Text and Data API
SDI_SetAvailableCharSets
SDI_SetLanguagePreference
SDI_GetAlbumInfo
Set a list of character sets, application can handle
Set a list of preferred languages
Retrieve information about the album of active disc
Retrieve album text items
SDI_GetAlbumText
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Table 38: API provided by SA-MP…continued
Name Description
SDI_GetNumberOfIndices
SDI_GetDiscInfo
Retrieve number of indices for specified track
Retrieve information about the active disc
Retrieve disc text items
SDI_GetDiscText
SDI_GetAreaText
Retrieve area text items
SDI_GetTrackInfo
Retrieve information about the specified track
Retrieve track text items
SDI_GetTrackText
System configuration API
SDM_SetBeType
Select the front-end interface attached to SA-MP
Configure the DAC pins
SDM_SetDacPinnning
SDM_SetAudioClock
Configure the audio clock for different input stream
modes
SDM_SetMemoryConfig
SDM_GetHandler
SDM_SetDsdClockPolarity
SDM_SetSystemClock
SDM_SetBurstLength
General API
Configure the SDRAM attached to the SAA7893HL
Return the pointer to SA-MP interrupt handler
Configure the DSD clock polarity
Inform SA-MP about the system clock
Configure the burst length for fast play
SAMP_Init
Initialize SA-MP
SAMP_Term
Terminate SA-MP
Activate SA-MP
SAMP_Activate
SAMP_Reactivate
SAMP_Deactivate
SAMP_SACDDiscReq
Reactivate SA-MP
Deactivate SA-MP
SACD disc recognition
14.2 API required by SA-MP
Software to be provided by the DVD host:
• For the front-end: Seek, GetDataArea, TransferRate (optional)
• For the operating system: Tasks, Interrupts, Semaphores, Mailboxes, Timers.
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15. Limiting values
Table 39: Absolute maximum ratings
In accordance with the Absolute Maximum Rating System (IEC 60134). Note 1.
Symbol
Parameter
Min
−0.5
−0.5
−0.5
−0.5
0
Max
+2.1
+3.8
+2.1
+5.5
70
Unit
V
VCC_Core digital core supply voltage
VCC_IO
VDDA
VI
IO pins supply voltage
analog supply voltage
DC input voltage
V
V
V
Tamb
Tstg
ambient temperature
storage temperature
junction temperature
°C
°C
°C
−25
−150
+125
+150
Tj
[1] Stresses above the absolute maximum ratings may cause permanent damage to the device. Exposure to absolute maximum ratings for
extended periods may effect device reliability.
16. Characteristics
Table 40: Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
Power supply: VCC_Core (digital core supply voltage)
VCC_Core digital core supply voltage
1.65
90
1.8
1.95
150
V
P
power dissipation
110
mW
Power supply: VDDA (analog supply voltage)
VDDA
P
analog supply voltage
1.65
-
1.8
40
1.95
60
V
power dissipation during disc recognition only
mW
Power supply: VCC_IO (I/O pins supply voltage)
VCC_IO
P
I/O pins supply voltage
3.0
-
3.3
70
3.6
V
power dissipation during disc recognition only
100
mW
Digital inputs and outputs
VIH
VIL
VOH
VOL
Ci
HIGH-level input voltage
2.0
-
-
-
VCC_IO + 0.5
V
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
input capacitance
0.8
-
V
VCC_IO − 0.4 -
V
-
-
-
-
-
-
-
-
-
-
0.4
10
V
pF
pF
µA
mA
Co
output capacitance
10
ILI
input leakage current
±10
±10
Ii(n)
input current on any pin except supplies
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17. Package outline
LQFP128: plastic low profile quad flat package; 128 leads; body 14 x 20 x 1.4 mm
SOT425-1
y
X
A
102
103
65
64
Z
E
e
H
A
E
2
A
E
(A )
3
A
1
θ
w M
p
L
p
b
L
pin 1 index
detail X
39
38
128
1
v
M
A
Z
w M
D
b
p
e
D
B
H
v
M
B
D
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.15 1.45
0.05 1.35
0.27 0.20 20.1 14.1
0.17 0.09 19.9 13.9
22.15 16.15
21.85 15.85
0.75
0.45
0.81 0.81
0.59 0.59
mm
1.6
0.25
1.0
0.2 0.12 0.1
0.5
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
99-12-27
00-01-19
SOT425-1
136E28
MS-026
Fig 60. LQFP128 (SOT425-1) package outline.
9397 750 10925
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Product data
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18. Soldering
18.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account
of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit
Packages (document order number 9398 652 90011).
There is no soldering method that is ideal for all surface mount IC packages. Wave
soldering can still be used for certain surface mount ICs, but it is not suitable for fine
pitch SMDs. In these situations reflow soldering is recommended.
18.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and
binding agent) to be applied to the printed-circuit board by screen printing, stencilling
or pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example, convection or convection/infrared
heating in a conveyor type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending on heating method.
Typical reflow peak temperatures range from 215 to 250 °C. The top-surface
temperature of the packages should preferably be kept:
• below 220 °C for all the BGA packages and packages with a thickness ≥ 2.5mm
and packages with a thickness <2.5 mm and a volume ≥350 mm3 so called
thick/large packages
• below 235 °C for packages with a thickness <2.5 mm and a volume <350 mm3 so
called small/thin packages.
18.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices
(SMDs) or printed-circuit boards with a high component density, as solder bridging
and non-wetting can present major problems.
To overcome these problems the double-wave soldering method was specifically
developed.
If wave soldering is used the following conditions must be observed for optimal
results:
• Use a double-wave soldering method comprising a turbulent wave with high
upward pressure followed by a smooth laminar wave.
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be
parallel to the transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the
transport direction of the printed-circuit board.
The footprint must incorporate solder thieves at the downstream end.
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• For packages with leads on four sides, the footprint must be placed at a 45° angle
to the transport direction of the printed-circuit board. The footprint must
incorporate solder thieves downstream and at the side corners.
During placement and before soldering, the package must be fixed with a droplet of
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the adhesive is cured.
Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the
need for removal of corrosive residues in most applications.
18.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low
voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time
must be limited to 10 seconds at up to 300 °C.
When using a dedicated tool, all other leads can be soldered in one operation within
2 to 5 seconds between 270 and 320 °C.
18.5 Package related soldering information
Table 41: Suitability of surface mount IC packages for wave and reflow soldering
methods
Package[1]
Soldering method
Wave
Reflow[2]
suitable
suitable
BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA not suitable
DHVQFN, HBCC, HBGA, HLQFP, HSQFP,
HSOP, HTQFP, HTSSOP, HVQFN, HVSON,
SMS
not suitable[3]
PLCC[4], SO, SOJ
suitable
suitable
suitable
suitable
LQFP, QFP, TQFP
not recommended[4][5]
not recommended[6]
SSOP, TSSOP, VSO, VSSOP
[1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note
(AN01026); order a copy from your Philips Semiconductors sales office.
[2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the
maximum temperature (with respect to time) and body size of the package, there is a risk that internal
or external package cracks may occur due to vaporization of the moisture in them (the so called
popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated
Circuit Packages; Section: Packing Methods.
[3] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom
side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with
the heatsink on the top side, the solder might be deposited on the heatsink surface.
[4] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave
direction. The package footprint must incorporate solder thieves downstream and at the side corners.
[5] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it
is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
[6] Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
9397 750 10925
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19. Revision history
Table 42: Revision history
Rev Date
CPCN
-
Description
02 20030226
Product data (9397 750 10925)
Modifications:
• The value of the capacitor to pin Adcrefl in Figure 44 is changed from 10 nF to 100 nF
• The system clock definitions are added in Section 7.5.1
• The audio clock definitions are added in Section 7.5.2
• A remark is added at the end of Section 8.2.
• A note is added to Table 11.
01 20021014
-
Product data (9397 750 10341)
9397 750 10925
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20. Data sheet status
Level Data sheet status[1]
Product status[2][3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
[2]
Please consult the most recently issued data sheet before initiating or completing a design.
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
21. Definitions
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
23. Trademarks
Dolby — Available only to licensees of Dolby Laboratories Licensing
Corporation, San Francisco, CA94111, USA, from whom licensing and
application information must be obtained. Dolby is a registered trade-mark of
Dolby Laboratories Licensing Corporation.
22. Disclaimers
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
Contact information
For additional information, please visit http://www.semiconductors.philips.com.
For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.
Fax: +31 40 27 24825
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
65 of 66
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Product data
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Contents
1
1.1
1.2
General description . . . . . . . . . . . . . . . . . . . . . . 1
Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
12.1
12.2
12.3
Writing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Interface connection. . . . . . . . . . . . . . . . . . . . 56
13
Power supply connections. . . . . . . . . . . . . . . 57
2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Components . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
HW interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . 3
SW interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . 3
System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
System configuration . . . . . . . . . . . . . . . . . . . . 4
SACD playback. . . . . . . . . . . . . . . . . . . . . . . . . 4
Audio postprocessing . . . . . . . . . . . . . . . . . . . . 4
SACD data and text . . . . . . . . . . . . . . . . . . . . . 5
General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
14
14.1
14.2
Software API . . . . . . . . . . . . . . . . . . . . . . . . . . 58
API provided by SA-MP . . . . . . . . . . . . . . . . . 58
API required by SA-MP . . . . . . . . . . . . . . . . . 59
15
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 60
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 60
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 61
16
17
18
18.1
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Introduction to soldering surface mount
packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 62
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 62
Manual soldering . . . . . . . . . . . . . . . . . . . . . . 63
Package related soldering information. . . . . . 63
3
4
5
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Ordering information. . . . . . . . . . . . . . . . . . . . . 6
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 6
18.2
18.3
18.4
18.5
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 7
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8
19
20
21
22
23
Revision history . . . . . . . . . . . . . . . . . . . . . . . 64
Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 65
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
7
Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Host interface . . . . . . . . . . . . . . . . . . . . . . . . . 11
Front-end interface . . . . . . . . . . . . . . . . . . . . . 11
Audio interface . . . . . . . . . . . . . . . . . . . . . . . . 12
SDRAM interface . . . . . . . . . . . . . . . . . . . . . . 12
Clock and reset input . . . . . . . . . . . . . . . . . . . 12
Test inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.1
7.2
7.3
7.4
7.5
7.6
8
Host interface. . . . . . . . . . . . . . . . . . . . . . . . . . 14
General description. . . . . . . . . . . . . . . . . . . . . 14
SAD16_01/02 mode . . . . . . . . . . . . . . . . . . . . 15
SAD16_03 mode . . . . . . . . . . . . . . . . . . . . . . 19
MAD16_01 mode . . . . . . . . . . . . . . . . . . . . . . 25
MAD16_02 mode . . . . . . . . . . . . . . . . . . . . . . 30
SAD08 mode . . . . . . . . . . . . . . . . . . . . . . . . . 33
Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8.1
8.2
8.3
8.4
8.5
8.6
8.7
9
Front-end interface . . . . . . . . . . . . . . . . . . . . . 37
I2S-bus interface . . . . . . . . . . . . . . . . . . . . . . . 38
UDE data interface . . . . . . . . . . . . . . . . . . . . . 40
FEC interface . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.1
9.2
9.3
10
HF input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
HF input specification . . . . . . . . . . . . . . . . . . . 45
HF-input application diagram . . . . . . . . . . . . . 46
10.1
10.2
10.3
11
Audio interfaces. . . . . . . . . . . . . . . . . . . . . . . . 46
Audio input interface . . . . . . . . . . . . . . . . . . . . 46
Audio output interface. . . . . . . . . . . . . . . . . . . 47
Audio output application diagrams . . . . . . . . . 51
11.1
11.2
11.3
12
SDRAM interface . . . . . . . . . . . . . . . . . . . . . . . 54
© Koninklijke Philips Electronics N.V. 2003.
Printed in The Netherlands
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 26 February 2003
Document order number: 9397 750 10925
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