SAA8122AEL [NXP]
Digital Still Camera Processor ImagIC family; 数码相机处理器锜家庭
| 型号： | SAA8122AEL |
| 厂家： | 
NXP |
| 描述： | Digital Still Camera Processor ImagIC family |
| 文件： | 总26页 (文件大小：841K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SAA8122A
Digital Still Camera Processor (ImagIC family)
Rev. 01 — 20 April 2000
Objective specification
1. Description
The DSC SAA8122A is a high performance, low power, single-chip Million
Instructions Per Second (MIPS) based signal processor, part of the ImagIC family,
which is dedicated to image processing, compression, formatting and storage. The
DSC SAA8122A is optimized for use with Philips range of CCDs (e.g: FXA1022,
2 Mpixels CCD), V-driver (TDA9991), CDS/PGA/ADC (TDA9952), allowing easy
implementation of a complete system solution and fast development of high
performance consumer digital still cameras.
The SAA8122A is designed as a single-chip device, able to perform all treatments
and connections required for a wide range of Digital Still Cameras. Its embedded
RISC CPU, for which the development environment is available, enables shorter
development and validation cycles, as well as faster feature upgrade. Since one of
the main objectives of the SAA8122A is addressing a wide range of CCD sensors, a
DSP (with advanced embedded algorithm) for camera signal processing is integrated
with a high level of programmability for pulses generation.
The JPEG core is hardware based in order to allow high-speed image data
compression.
c
c
2. Features
2.1 General
■ Supports a wide range of progressive CCDs (VGA, SVGA, QGA, XGA, EQGA),
with RGB Bayer filters up to 2 Mpixels
■ Performs an advanced RGB to YUV conversion
■ Includes a smart measurement unit to speed up the control loop (focus, auto white
balance, etc.)
■ Supports a wide range of LCD and TV formats (both NTSC and PAL) with text
insertion features
■ Includes an embedded JPEG encoder/decoder unit
■ Includes a MIPS PR3001 CPU, running at a frequency in a range from
12 to 28 MHz
■ PRISC compatible PI-bus architecture, interrupt, power management, clock and
reset architectures
■ Includes a dedicated video bus supporting SDRAM memory for picture storage
SAA8122A
Digital Still Camera Processor (ImagIC family)
Philips Semiconductors
■ Interface to ROM, DRAM, SRAM, flash and PC Card [Compact Flash and SSFDC
(SmartMedia)]
■ Integrated general purpose peripheral units like a UART, timers, an I2C-bus
transceiver, ADC converters, RTC and I/O ports
■ Includes USB and RS-232C communication interfaces.
2.2 External interfaces
■ Two UART (RS-232) data ports with DMA capabilities (≤187.5 kbit/s) including
hardware flow control RxD, TxD, RTS, CTS for modem support
■ 32 general purpose, bidirectional I/O interface pins, the first 8 bits may also be
used as interrupt inputs
■ Two PWM outputs (8-bit resolution).
2.3 CPU related features
■ 32-bit PR3001 core
■ 1-kbyte data cache and 4-kbyte instruction cache
■ Programmable low-power mode, including wake-up on interrupt
■ Memory management unit [Translation Lookaside Buffer (TLB)]
■ Two built in 24-bit general purpose timers and one 24-bit watchdog timer
■ Real-time clock unit (active in sleep mode)
■ On-chip 8-kbyte SRAM for storing code which needs fast execution
■ Platform software based on real-time pSOS (plug-in Silicon Operating System).
2.4 DSP features
■ Advanced colour reconstruction
■ Programmable digital filters for noise reduction and contour enhancement
■ 16 programmable measurement windows allowing to perform the measurements
necessary for exposure, white balance and focus adjustment in a DSC system;
available measurement outputs for exposure, white balance and focus control.
2.5 Pulse pattern generator features
■ Programmable through dedicated PC-software, allowing to drive all CCDs
currently present in the market, as well as CDS/AGC/ADC chips: up to
8 × 8 kpixels.
2.6 JPEG
■ Fully ISO10918 compliant
■ Supports Tiff, Exif 2.1, DCF & DPOF
■ Quick compression (4 images/s for a 1.3 Mpixels resolution).
2.7 USB interface
■ Fully compatible with USB.
9397 750 07048
© Philips Electronics N.V. 2000. All rights reserved.
Objective specification
Rev. 01 — 20 April 2000
2 of 26
SAA8122A
Digital Still Camera Processor (ImagIC family)
Philips Semiconductors
2.8 Card interfaces
■ Compatible with all SSFDC/CF cards on the market.
2.9 Bus
■ Bus structure allows for parallel processing depending on software
implementation, allowing easy system optimization.
2.10 SDRAM interface features
■ Supports up to 128 Mbyte of SDRAM and 16-bit wide addressses
■ Bus speed: 1 or 2 times CCD pixel clock
■ 32-bit bus width.
3. Quick reference data
Table 1: Quick reference data
Symbol
VDDD
VDDA
IP
Parameter
Conditions
Min
3
Typ
3.3
Max
3.6
Unit
V
[1]
[2]
digital supply voltage
analog supply current
total supply current
input voltage
3
3.3
3.6
V
fclk = 25 MHz
−
360
560
mA
VI
general
0
0
0
0
−
−
VDDD
5.5
V
[3]
5 V tolerant cells only
output voltage
−
V
VO
output active
−
VDDD
70
V
Tamb
fclk
ambient temperature
clock frequency
25
25
°C
MHz
27
[1] The supplies considered as digital supply (VDDD) are: VDDD, VDDD(RTC)
[2] The supplies considered as analog supply (VDDA) are: VDDA(SPLL), VDDA(PLL), VDDA(BG), VDDA(PPG1)
VDDA(ADC), VDDA(OUTPUT1), VDDA(OUTPUT2), VDDA(LCDR), VDDA(LCDG), VDDA(LCDB), VDDA(DLL)
[3] Including voltage on outputs in 3-state mode; only valid when supply voltage is present.
.
,
.
4. Ordering information
Table 2: Ordering information
Type number
Package
Name
Description
Version
SAA8122AEL
LFBGA324 plastic low profile fine-pitch ball grid array package; 324 balls;
SOT571-1
body 16 × 16 × 1.2 mm
9397 750 07048
© Philips Electronics N.V. 2000. All rights reserved.
Objective specification
Rev. 01 — 20 April 2000
3 of 26
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TCB
DRAM
MEMORY
CONTROLLER CONTROLLER
STATIC
MEMORY
PC-CARD
CONTROLLER
PERIPHERAL
CONTROLLER
JPEG
CODEC
INTERUPT
CONTROLLER
PR3001
CPU
INTERUPT
CONTROLLER
PLL
CCD
USB
UART
EBIU
PI
BCU
SAA8122A
SLAVE GROUP INTERFACE
VDO
BCU
8K
SRAM
CAMDSP
2
I C
TRANSCIEVER
POWER
MANAGEMENT
CONTROLLER
ANALOG
DIGITAL
CONTROLLER
GPIO
FOUR
GPIO
TIMER
TIMER
TIMER
RTC
+
INT
FCE686
Fig 1. Block diagram.
SAA8122A
Digital Still Camera Processor (ImagIC family)
Philips Semiconductors
to LCD
to TV
lens
10
CCD
FXA1022
to cards
(SSFDC, CF)
SAA8122A
TDA9952
USB
IRDA
to PC
V-DRIVER
TDA9991
FCE687
Fig 2. System block diagram.
6. Pinning information
6.1 Pinning
handbook, halfpage
V
U
R
N
L
T
P
M
K
H
F
SAA8122AEL
J
G
E
C
A
D
B
2
4
6
8
10 12 14 16 18
9 11 13 15 17
1
3
5
7
FCE677
Fig 3. Pin configuration (bottom view).
6.2 Pin description
Table 3: Pin description
Symbol
Pin
A1
A2
A3
A4
A5
A6
A7
Type
Description
VDDD
-
digital supply voltage
VSSA(DLL)
-
analog ground for DLL of PPG
VDDA(DLL)
-
analog supply voltage for DLL of PPG
digital vertical synchronization signal
I/O port 0 bit 1 or interrupt request 17
analog supply voltage for DAC component G
analog supply voltage for DAC video output 2
DISP_VSYNC
IO1/IRQ17
VDDA(LCDG)
VDDA(OUTPUT2)
O
I/O
P
P
9397 750 07048
© Philips Electronics N.V. 2000. All rights reserved.
Objective specification
Rev. 01 — 20 April 2000
5 of 26
SAA8122A
Digital Still Camera Processor (ImagIC family)
Philips Semiconductors
Table 3: Pin description…continued
Symbol
CREF_BG1
VSS(BG)
Pin
A8
Type
-
Description
band-gap 1
A9
P
I
ground for BG of video DAC
system reset input/output; active LOW
ground for RTC
SYSRSTIN
VSS(RTC)
T0_CAP0
CNT2
A10
A11
A12
A13
A14
A15
A16
A17
A18
B1
P
I
timer 0 capture input 0
I
timer 2 count pulse input
CNT1
I
timer 1 count pulse input
PWM0
O
I
timer 0 PWM output
ADC0
analog input signal 0 for level measurement
analog input signal 3 for level measurement
ground for ADC
ADC3
I
VSS(ADC)
ANPPG1
IO6/IRQ22
IO3/IRQ19
LCD_G
P
O
I/O
I/O
O
O
O
I
PPG analog signal 1
B4
I/O port 0 bit 6 or interrupt request 22
I/O port 0 bit 3 or interrupt request 19
analog green signal
B5
B6
VIDEO_OUT2
VSSA(ref)
B7
video output signal 2
B8
analog reference ground
SC_TCK
TCK
B9
test clock input for surround scan chains
test clock input
B10
B11
B12
B13
B14
B15
B16
B17
B18
C1
I
XTALCCDIN
VDDA(SPLL)
VSS(PLL)
-
oscillator input from a specific CCD crystal
analog supply voltage for SPLL
ground for PLL
P
P
I
CNT0
timer 0 count pulse input
VSSA(ref)(ADC)
ADC2
O
I
analog reference ground for ADC
analog input signal 2 for level measurement
analog supply voltage for ADC
I/O port 2 bit 7
VDDA(ADC)
IO23
P
I/O
P
P
P
I/O
I/O
O
O
P
P
I
VDDA(PPG1)
VDDA(PPG0)
VDDA(DLL)
IO7/IRQ23
IO4/IRQ20
LCD_R
analog supply voltage for PPG
analog supply voltage for PPG
analog supply voltage for DLL of PPG
I/O port 0 bit 7 or interrupt request 23
I/O port 0 bit 4 or interrupt request 20
analog red signal
C2
C3
C4
C5
C6
LCD_B
C7
analog blue signal
VDDA(OUTPUT1)
VDDA(BG)
TMS
C8
analog supply voltage for DAC video output 1
analog supply voltage for BG of video DAC
test mode select input
C9
C10
C11
C12
C13
C14
XTAL32KIN
XTAL10IN
GATE2
-
oscillator input from a 32 kHz crystal
oscillator input from a 10 MHz crystal
timer 2 gate input
-
I
VDDA(PLL)
P
analog supply voltage for PLL
9397 750 07048
© Philips Electronics N.V. 2000. All rights reserved.
Objective specification
Rev. 01 — 20 April 2000
6 of 26
SAA8122A
Digital Still Camera Processor (ImagIC family)
Philips Semiconductors
Table 3: Pin description…continued
Symbol
PWM1
ADC1
Pin
C15
C16
C17
C18
D1
Type
O
I
Description
timer 1 PWM output
analog input signal 1 for level measurement
I/O port 2 bit 6
IO22
I/O
I/O
O
P
IO16
I/O port 2 bit 0
ANPPG7
VSSA(PPG1)
PPG analog signal 7
D2
analog ground for PPG
digital horizontal synchronization signal
I/O port 0 bit 5 or interrupt request 21
I/O port 0 bit 0 or interrupt request 16
analog ground for display RGB
ground for DAC video output
band-gap 2
DISP_HSYNC D3
O
I/O
I/O
P
IO5/IRQ21
IO0/IRQ16
VSSA(LCD)
VSS(OUTPUT)
CREF_BG2
TDO
D4
D5
D6
D7
P
D8
-
D9
O
I
test data output
TDI
D10
D11
D12
D13
D14
D15
D16
D17
D18
E1
test data input
XTAL32KOUT
XTAL10OUT
T0_CAP1
GATE0
-
oscillator output from a 32 kHz crystal
oscillator output from a 10 MHz crystal
timer 0 capture input 1
timer 0 gate input
-
I
I
PWM2
O
I/O
I/O
I/O
O
O
O
P
timer 2 PWM output
IO17
I/O port 2 bit 1
IO15
I/O port 1 bit 7
IO11
I/O port 1 bit 3
PPG1
PPG digital signal 0
PPG2
E2
PPG digital signal 1
ANPPG8
VDDA(PPG0)
IO2/IRQ18
VDDA(LCDR)
VDDA(LCDB)
VIDEO_OUT1
SYSRST
TRST
E3
PPG analog signal 8
E4
analog supply voltage for PPG
I/O port 0 bit 2 or interrupt request 18
analog supply voltage for DAC component R
analog supply voltage for DAC component B
video output signal 1
E5
I/O
P
E6
E7
P
E8
O
O
I
E9
system reset output; active LOW
test reset input
E10
E11
VDDD(RTC)
P
digital supply voltage for RTC
oscillator output from a specific CCD crystal
timer 1 gate input
XTALCCDOUT E12
-
GATE1
IO18
E14
E15
E16
E17
E18
F1
I
I/O
I/O
I/O
I
I/O port 2 bit 2
IO10
I/O port 1 bit 2
IO9
I/O port 1 bit 1
UA_CLK
PPG5
PPG6
UART external clock
O
O
PPG digital signal 4
F2
PPG digital signal 5
9397 750 07048
© Philips Electronics N.V. 2000. All rights reserved.
Objective specification
Rev. 01 — 20 April 2000
7 of 26
SAA8122A
Digital Still Camera Processor (ImagIC family)
Philips Semiconductors
Table 3: Pin description…continued
Symbol
PPG3
ANPPG5
ANPPG3
VSS
Pin
F3
Type
O
O
O
-
Description
PPG digital signal 2
PPG analog signal 5
PPG analog signal 3
ground
F4
F5
F6
VSS
F7
-
ground
VDD
F8
-
supply voltage
supply voltage
supply voltage
supply voltage
supply voltage
I/O port 2 bit 4
I/O port 2 bit 3
I/O port 1 bit 4
UART clear to send
UART receive input
UART transmit output
PPG digital signal 17
PPG digital control signal 1
PPG digital signal 8
PPG digital signal 3
PPG analog signal 6
PPG analog signal 2
supply voltage
ground
VDD
F9
-
VDD
F10
F11
F12
F13
F14
F15
F16
F17
F18
G1
-
VDD
-
VDD
-
IO20
I/O
I/O
I/O
I
IO19
IO12
CTS
RXD
I
TXD
O
O
O
O
O
O
O
-
PPG10
PPG12
PPG8
PPG4
ANPPG6
ANPPG2
VDD
G2
G3
G4
G5
G6
G7
VSS
G8
-
VSS
G9
-
ground
VSS
G10
G11
G12
G13
G14
G15
G16
G17
G18
H1
-
ground
VSS
-
ground
VDD
-
supply voltage
I/O port 2 bit 5
I/O port 1 bit 5
UART request to send
I2C-bus data
IO21
I/O
I/O
O
I/O
I/O
-
IO13
RTS
SDA
SCL
I2C-bus clock
n.c.
not connected
HDHREF
VDVS
PPG13
PPG7
PPG14
ANPPG4
VDD
I/O
I/O
O
O
O
O
-
PPG horizontal synchronization signal
PPG vertical synchronization signal
PPG digital control signal 2
PPG digital control signal 6
PPG digital control signal 3
PPG analog signal 4
H2
H3
H4
H5
H6
H7
supply voltage
9397 750 07048
© Philips Electronics N.V. 2000. All rights reserved.
Objective specification
Rev. 01 — 20 April 2000
8 of 26
SAA8122A
Digital Still Camera Processor (ImagIC family)
Philips Semiconductors
Table 3: Pin description…continued
Symbol
VSS
Pin
H8
Type
Description
ground
-
VSS
H9
-
ground
VSS
H10
H11
H12
H13
H14
H15
H16
H17
H18
J1
-
ground
VSS
-
ground
VDD
-
supply voltage
I/O port 1 bit 6
USB
IO14
I/O
RXVPI
n.c.
I
-
not connected
USB
RXVMI
TXVPO
RXDATA
CCD_IM2
CCD_IM3
CCD_IM4
PPG11
PPG9
VDD
I/O
O
USB
I
USB
I
digital image signal 2
digital image signal 3
digital image signal 4
PPG digital signal 18
PPG digital signal 8
supply voltage
supply voltage
ground
J2
I
J3
I
J4
O
J5
O
J6
-
VDD
J7
-
VSS
J8
-
VSS
J9
-
ground
VSS
J10
J11
J12
J13
J14
J15
J16
J17
J18
K1
-
ground
VSS
-
ground
VDD
-
supply voltage
I/O port 1 bit 0
USB
IO8
I/O
SUSPEND
TXOE
D2
O
O
USB
I/O
EBIU D2
D3
I/O
EBIU D3
D0
I/O
EBIU D0
CCD_IM10
CCD_IM9
CCD_IM8
CCD_IM1
CCD_IM0
VDD
I
digital image signal 10
digital image signal 9
digital image signal 8
digital image signal 1
digital image signal 0
supply voltage
supply voltage
ground
K2
I
K3
I
K4
I
K5
I
K6
-
-
-
-
-
-
-
VDD
K7
VSS
K8
VSS
K9
ground
VSS
K10
K11
K12
ground
VSS
ground
VDD
supply voltage
9397 750 07048
© Philips Electronics N.V. 2000. All rights reserved.
Objective specification
Rev. 01 — 20 April 2000
9 of 26
SAA8122A
Digital Still Camera Processor (ImagIC family)
Philips Semiconductors
Table 3: Pin description…continued
Symbol
TXVMO
D1
Pin
K13
K14
K15
K16
K17
K18
L1
Type
O
I/O
I/O
I/O
I/O
I/O
O
O
O
I
Description
USB
EBIU D1
EBIU D4
EBIU D6
EBIU D7
EBIU D8
D4
D6
D7
D8
SD_A[0]
SD_A[3]
SD_A[2]
CCD_IM6
CCD_IM7
CCD_IM5
VDD
SDRAM controller address bus bit 0
L2
SDRAM controller address bus bit 3
L3
SDRAM controller address bus bit 2
L4
digital image signal 6
L5
I
digital image signal 7
L6
I
digital image signal 5
L7
-
supply voltage
VSS
L8
-
ground
VSS
L9
-
ground
VSS
L10
L11
L12
L13
L14
L15
L16
L17
L18
M1
-
ground
VSS
-
ground
VDD
-
supply voltage
D5
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
I
EBIU D5
D9
EBIU D9
D11
EBIU D11
D14
EBIU D14
D13
EBIU D13
D12
EBIU D12
SD_A[7]
SD_A[8]
SD_A[9]
SD_A[4]
SD_A[1]
CCD_IM11
VDD
SDRAM controller address bus bit 7
M2
SDRAM controller address bus bit 8
M3
SDRAM controller address bus bit 9
M4
SDRAM controller address bus bit 4
M5
SDRAM controller address bus bit 1
M6
digital image signal 11
M7
-
supply voltage
VSS
M8
-
ground
VSS
M9
-
ground
VSS
M10
M11
M12
M13
M14
M15
M16
M17
-
ground
VSS
-
ground
VDD
-
supply voltage
D10
I/O
O
I/O
I
EBIU D10
SC_SE
D15
EBIU controller SE signal for SSFDC card; active LOW
EBIU D15
PC_WAIT2
SC_CE
EBIU controller WAIT signal for PC card 2; active LOW
EBIU controller CE signal for SSFDC card; active LOW
O
9397 750 07048
© Philips Electronics N.V. 2000. All rights reserved.
Objective specification
Rev. 01 — 20 April 2000
10 of 26
SAA8122A
Digital Still Camera Processor (ImagIC family)
Philips Semiconductors
Table 3: Pin description…continued
Symbol
SC_CLE
SD_A[12]
SD_A[13]
SD_A[14]
SD_A[10]
SD_A[6]
SD_A[5]
VDD
Pin
M18
N1
Type
O
O
O
O
O
O
O
-
Description
EBIU controller CLE signal for SSFDC card
SDRAM controller address bus bit 12
SDRAM controller address bus bit 13
SDRAM controller address bus bit 14
SDRAM controller address bus bit 10
SDRAM controller address bus bit 6
SDRAM controller address bus bit 5
supply voltage
N2
N3
N4
N5
N6
N7
VDD
N8
-
supply voltage
VDD
N9
-
supply voltage
VDD
N10
N11
N12
N13
N14
N15
N16
N17
N18
P1
-
supply voltage
VDD
-
supply voltage
SC_ALE
PC2_CE1
PC2_CE2
PC_REG
PC_WAIT1
IOWR_WE
IORD_RE
SD_CLKOUT
SD_CLKIN
SD_CS2
SD_CLKEN
SD_A[11]
VDD
O
O
O
O
O
O
O
O
I
EBIU controller ALE signal for SSFDC card
EBIU controller CE1 signal for PC card 2; active LOW
EBIU controller CE2 signal for PC card 2; active LOW
EBIU controller REG signal for PC cards; active LOW
EBIU controller WAIT signal for PC card 1; active LOW
EBIU controller IORD signal for PC cards; active LOW
EBIU controller IORD signal for PC cards; active LOW
SDRAM controller clock output
SDRAM controller clock input
P2
P3
O
O
O
-
SDRAM controller chip select for memory 2; active LOW
SDRAM controller clock enable
SDRAM controller address bus bit 11
supply voltage
P4
P5
P6
SD_D[7]
IO25
P7
I/O
I/O
I/O
I/O
I/O
-
SDRAM controller data bus bit 7
I/O port 3 bit 1
P8
IO38
P9
I/O port 4 bit 6
A25
P10
P11
P12
P13
P14
P15
P16
EBIU A25 (Strapin[0] during boot sequence)
EBIU A21 (Strapin[4] during boot sequence)
supply voltage
A21
VDD
A14
I/O
O
I/O
O
EBIU A14
SCLK
EBIU controller clock signal for external peripherals
EBIU A9
A9
CAS0
EBIU controller CAS signal for DRAM memory for lower byte; used as data
strobe signal for lower byte for general chip select; active LOW
PC1_CE1
PC1_CE2
SD_CS0
SD_CS1
SD_CS3
P17
P18
R1
O
O
O
O
O
EBIU controller CE1 signal for PC card 1; active LOW
EBIU controller CE2 signal for PC card 1; active LOW
SDRAM controller chip select for memory 0; active LOW
SDRAM controller chip select for memory 1; active LOW
SDRAM controller chip select for memory 3; active LOW
R2
R3
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SAA8122A
Digital Still Camera Processor (ImagIC family)
Philips Semiconductors
Table 3: Pin description…continued
Symbol
SD_D[4]
SD_RAS
SD_D[6]
SD_D[13]
IO30
Pin
R4
Type
I/O
O
Description
SDRAM controller data bus bit 4
SDRAM controller row address strobe; active LOW
SDRAM controller data bus bit 6
SDRAM controller data bus bit 13
I/O port 3 bit 6
R5
R6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
R7
R8
IO37
R9
I/O port 4 bit 5
A24
R10
R11
R12
R13
R14
R15
R16
EBIU A24 (Strapin[1] during boot sequence)
EBIU A19 (Strapin[6] and Strapin[9] during boot sequence)
EBIU A18 (Strapin[10] during boot sequence)
EBIU A13
A19
A18
A13
A5
EBIU A5
CS6
O
EBIU controller chip select 6; active LOW
CAS1
O
EBIU controller CAS signal for DRAM memory for upper byte; used as data
strobe signal for upper byte for general chip select; active LOW
OE
R17
R18
T1
O
EBIU controller output enable signal; active LOW
EBIU controller RAS signal for DRAM memory; active LOW
SDRAM controller column address strobe; active LOW
SDRAM controller write enable; active LOW
SDRAM controller data bus bit 3
SDRAM controller data bus bit 8
SDRAM controller data bus bit 10
SDRAM controller data bus bit 14
I/O port 3 bit 2
RAS
O
SD_CAS
SD_WE
SD_D[3]
SD_D[8]
SD_D[10]
SD_D[14]
IO26
O
T2
O
T3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
T4
T5
T6
T7
IO29
T8
I/O port 3 bit 5
IO33
T9
I/O port 4 bit 1
IO36
T10
T11
T12
T13
T14
T15
T16
T17
T18
U1
I/O port 4 bit 4
A23
EBIU A23 (Strapin[2] during boot sequence)
EBIU A16
A16
A12
EBIU A12
A3
EBIU A3
CS7
O
EBIU controller chip select 7; active LOW
EBIU controller chip select 4; active LOW
EBIU controller write enable signal; active LOW
EBIU controller wait signal for chip selects; active LOW
SDRAM controller DQ mask enable for byte 0; active LOW
SDRAM controller DQ mask enable for byte 1; active LOW
SDRAM controller data bus bit 2
SDRAM controller data bus bit 9
SDRAM controller data bus bit 11
SDRAM controller data bus bit 15
I/O port 3 bit 3
CS4
O
WE
O
CS_WAIT
SD_DQM0
SD_DQM1
SD_D[2]
SD_D[9]
SD_D[11]
SD_D[15]
IO27
O
O
U2
O
U3
I/O
I/O
I/O
I/O
I/O
U4
U5
U6
U7
9397 750 07048
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Objective specification
Rev. 01 — 20 April 2000
12 of 26
SAA8122A
Digital Still Camera Processor (ImagIC family)
Philips Semiconductors
Table 3: Pin description…continued
Symbol
IO32
IO34
A22
Pin
U8
Type
I/O
I/O
I/O
I/O
I/O
I/O
O
Description
I/O port 4 bit 0
I/O port 4 bit 2
U9
U10
U11
U12
U13
U14
U15
U16
U17
U18
V1
EBIU A22 (Strapin[3] during boot sequence)
EBIU A17 (Strapin[11] during boot sequence)
EBIU A11
A17
A11
A8
EBIU A8
A4
EBIU A4
A2
O
EBIU A2
CS5
CS3
CS0
SD_D[0]
SD_D[1]
SD_D[5]
SD_D[12]
IO24
IO28
IO31
IO35
IO39
A20
O
EBIU controller chip select 5; active LOW
EBIU controller chip select 3; active LOW
EBIU controller chip select 0; active LOW
SDRAM controller data bus bit 0
SDRAM controller data bus bit 1
SDRAM controller data bus bit 5
SDRAM controller data bus bit 12
I/O port 3 bit 0
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
V2
V3
V4
V5
V6
I/O port 3 bit 4
V7
I/O port 3 bit 7
V8
I/O port 4 bit 3
V9
I/O port 4 bit 7
V10
V11
V12
V13
V14
V15
V16
V17
V18
EBIU A20 (Strapin[5] and Strapin[8] during boot sequence)
EBIU A15
A15
A10
EBIU A10
A7
EBIU A7
A6
EBIU A6
A1
EBIU A1
A0
O
EBIU A0
CS2
CS1
O
EBIU controller chip select 2; active LOW
EBIU controller chip select 1; active LOW
O
9397 750 07048
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Objective specification
Rev. 01 — 20 April 2000
13 of 26
SAA8122A
Digital Still Camera Processor (ImagIC family)
Philips Semiconductors
7. Limiting values
Table 4: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDDD
VDDA
VI
Parameter
Conditions
Min
−0.5
−0.5
−0.5
Max
4
Unit
V
digital supply voltage
analog supply voltage
DC input voltage
4
V
[1]
[2]
general
VDD + 0.5 V
[2]
[3]
5 V tolerant
cells only
−0.5
−0.5
60
V
[4]
[4]
[5]
IDD
ISS
DC supply current per
supply pin
−
−
0
mA
mA
°C
DC ground current per
ground pin
60
Tstg
storage temperature
125
[1] Value may not exceed 4 V.
[2] Including voltage on outputs in 3-state mode.
[3] Only valid when supply voltage is present.
[4] The peak current is limited to 10 times the corresponding maximum current.
[5] Dependent of package and not yet determined.
8. Characteristics
Table 5: General supply characteristics
Symbol
Parameter
Conditions
Min
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
Typ
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
Max
Unit
VDDD
digital supply voltage
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VDDA(DLL)
VDDA(LCDR)
VDDA(LCDG)
VDDA(LCDB)
analog supply voltage for DLL
analog supply voltage for LCDR output of DAC
analog supply voltage for LCDG output of DAC
analog supply voltage for LCDB
VDDA(OUTPUT1) analog supply voltage for video output 1 of DAC
VDDA(OUTPUT2) analog supply voltage for video output 2 of DAC
VDDA(ADC)
VDDA(PPG1)
VDDA(PPG0)
VDDA(BG)
analog supply voltage for ADC
analog supply voltage for PPG
analog supply voltage for PPG
analog supply voltage for bandgap
analog supply voltage for PLL
analog supply voltage for SPLL
digital supply voltage for RTC
VDDA(PLL)
VDDA(SPLL)
VDDD(RTC)
[1]
[1] VDDD(RTC) is the single supply which may be on when the others are off. In this case the I/Os of the SAA8122A have to be at 0 V.
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Objective specification
Rev. 01 — 20 April 2000
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SAA8122A
Digital Still Camera Processor (ImagIC family)
Philips Semiconductors
Table 6: Operating characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA(LCDR)
analog supply voltage for LCDR
output of DAC
3.0
3.3
3.6
V
VDDA(LCDG)
VDDA(LCDB)
analog supply voltage for LCDG
output of DAC
3.0
3.0
3.0
3.0
3.3
3.3
3.3
3.3
3.6
3.6
3.6
3.6
V
V
V
V
analog supply voltage for LCDB
output of DAC
VDDA(OUTPUT1) analog supply voltage for video
output 1 of DAC
VDDA(OUTPUT2) analog supply voltage for video
output 2 of DAC
VDDA(BG)
VBG
analog supply voltage for bandgap
bandgap reference voltage
LOW-level output voltage
3.0
3.3
3.6
V
V
V
V
(4σ)
1.18
1.22
0.225
1.625
1.26
VOL
code 0
code 511
-
-
-
-
VOH
HIGH-level output voltage
LCD channels (1 kΩ buffer)
RL
load resistance
load capacitance
resolution
-
-
-
1
-
-
kΩ
pF
bit
CL
5
-
RES
8
LCD channels (75 Ω mode)
RL
load resistance
load capacitance
resolution
-
-
-
75
5
-
Ω
CL
100
-
pF
bit
RES
9
VIDEO_OUT channels (1 kΩ buffer)
RL
load resistance
load capacitance
resolution
-
-
-
1
-
-
kΩ
pF
bit
CL
5
-
RES
8
VIDEO_OUT channels (1 kΩ mode)
RL
load resistance
load capacitance
resolution
-
-
-
1
-
-
kΩ
pF
bit
CL
5
-
RES
ADC
VDDA(ADC)
9
analog supply voltage for analog
ADC
3.0
-
3.3
-
3.6
0.2
V
V
∆VDD
supply voltage difference between
VDDA and VDDA(ADC)
RES
Ci
resolution
8
-
-
10
-
bit
pF
V
input capacitance
input voltage
2
-
Vi
0
0
3.3
100
fsample
PLL
VDDA(PLL)
sample frequency
8-bit
-
kHz
analog supply voltage for analog
PLL
3.0
3.3
3.6
V
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Objective specification
Rev. 01 — 20 April 2000
15 of 26
SAA8122A
Digital Still Camera Processor (ImagIC family)
Philips Semiconductors
Table 6: Operating characteristics…continued
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
∆VDD
supply voltage difference between
VDDA and VDDA(PLL)
-
-
0.2
V
fclk
clock frequency
-
96
-
MHz
SPLL
VDDA(SPLL)
analog supply voltage for analog
SPLL
3.0
-
3.3
-
3.6
0.2
V
V
∆VDD
supply voltage difference between
VDDA and VDDA(SPLL)
Power-on reset
Vtrip
trip level of power-on reset
1.5
-
2.07
-
2.65
2
V
tHIGH
time that VDDA has to be above
2.65 V before internal reset signal is
asserted
µs
tLOW
time that VDDA has to be above
2.65 V before internal reset signal is
de-asserted
-
-
8
µs
Analog PPG
VDDA(DLL)
analog supply voltage for analog
DLL
3.0
-
3.3
-
3.6
0.2
3.6
0.2
V
V
V
V
∆VDD-DDA(DLL) supply voltage difference between
VDDA and VDDA(DLL)
VDDA(PPG1)
VDDA(PPG0)
;
analog supply voltage for analog
PPG
3.0
-
3.3
-
∆VDD-DDA(PPG) supply voltage difference between
VDDA and VDDA(PPG1) or VDDA(PPG0)
I/Os (VDDD = VDDA, Tamb = 0 to 60 °C)
Data and control inputs
SD_CLKIN
VIL
VIH
Ci
LOW-level digital input voltage
HIGH-level digital input voltage
input capacitance
0
-
0.3VDDD
V
0.7VDDD
-
VDDD
V
-
1.14
-
pF
µA
µA
mA
IIL
LOW-level input current
HIGH-level input current
I/O latch-up current
VI = 0 V
-
-
-
-
1
1
-
IIH
VI = VDDD
-
Ilu(I/O)
−0.5 < VDDD + 0.5
100
CS_WAIT, PC_WAIT1, PC_WAIT2, SC_TCK, TCK, TDI, TMS, TRST, CCD_IM0 to CCD_IM11, CNT0 to CNT2,
GATE0 to GATE2, T0_CAP0, T0_CAP1, CTS, RXD, UA_CLK, RXDATA, RXVMI, RXVPI
VIL
LOW-level digital input voltage
HIGH-level digital input voltage
input capacitance
0
-
0.8
5.5
-
V
VIH
2.0
-
V
Ci
-
1.2
pF
µA
µA
mA
IIL
LOW-level input current
HIGH-level input current
I/O latch-up current
VI = 0 V
-
-
-
-
1
IIH
VI = VDDD
-
1
Ilu(I/O)
SYSRSTIN
VIL
−0.5 < VDDD < 5.5
100
-
LOW-level digital input voltage
0
-
0.8
V
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Objective specification
Rev. 01 — 20 April 2000
16 of 26
SAA8122A
Digital Still Camera Processor (ImagIC family)
Philips Semiconductors
Table 6: Operating characteristics…continued
Symbol
VIH
Parameter
Conditions
Min
2.0
0.4
-
Typ
Max
Unit
V
HIGH-level digital input voltage
hysteresis voltage
-
5.5
-
Vhys
Ci
-
V
input capacitance
1.2
-
pF
µA
µA
mA
IIL
LOW-level input current
HIGH-level input current
I/O latch-up current
VI = 0 V
-
-
-
-
1
1
-
IIH
VI = VDDD
-
Ilu(I/O)
−0.5 < VDDD < 5.5
100
Data and control outputs
ANPPG1 to ANPPG8
VOL
LOW-level digital output voltage
IOL = 4 mA
IOH = 4 mA
0
-
0.4
VDDA
100
-
V
VOH
HIGH-level digital output voltage
maximum output load capacitance
LOW-level output current
V
-
DDA − 0.4 -
V
[1]
Co(L)(max)
IOL
-
-
pF
mA
VOL = 0.4 V;
4
VOH = VDDA − 0.4
IOH
HIGH-level output current
VOH = VDDA − 0.4
−4
-
-
mA
SCLK, SD_A[0] to SD_A[14], SD_CAS, SD_CLKEN, SD_CLKOUT, SD_CS0 to SD_CS3, SD_DQM0 to SD_DQM1,
SD_RAS, SD_WE
VOL
VOH
Ci
LOW-level digital output voltage
HIGH-level digital output voltage
input capacitance
IOL = 4 mA
0
V
-
-
0.4
V
IOH = −4 mA
DDD − 0.4
VDDD
V
-
1
-
-
pF
pF
µA
mA
µA
[1]
Co(L)(max)
IOL
maximum output load capacitance
LOW-level output current
-
-
100
VOL = 0.4 V
-
-
-
IOH
HIGH-level output current
3-state output leakage current
VOH = VDDD − 0.4
−4
-
-
IOZ
VO = 0;
-
-
1
VO = VDDD
TDO, SYSRST, PWM0 to PWM2, RTS, TXD, SUSPEND, TXOE, TXVMO, TXVPO, DISP_HSYNC, DISP_VSYNC
VOL
LOW-level digital output voltage
HIGH-level digital output voltage
input capacitance
IOL = 2 mA
0
V
-
-
0.4
V
VOH
Ci
IOH = −2 mA
DDD − 0.4 -
VDDD
V
-
-
2.2
-
pF
pF
mA
[1]
Co(L)(max)
IOL
maximum output load capacitance
LOW-level output current
-
-
-
30
-
VOL = 0.4 V;
2
VOH = VDDD − 0.4
IOH
IOZ
HIGH-level output current
VOH = VDDD − 0.4
−2
-
-
-
mA
3-state output leakage current
VO = 0;
-
1
µA
VO = VDD
CAS0, CAS1, CS0 to CS7, IORD_RE, IOWR_WE, OE, PC_REG, PC1_CE1, PC1_CE2, RAS, SC_ALE, SC_SE, WE,
PPG1 to PPG14
VOL
LOW-level digital output voltage
HIGH-level digital output voltage
input capacitance
IOL = 4 mA
0
V
-
-
0.4
V
VOH
Ci
IOH = −4 mA
DDD − 0.4 -
VDDD
V
-
-
2.4
-
pF
pF
mA
[1]
Co(L)(max)
IOL
maximum output load capacitance
LOW-level output current
-
-
-
30
-
VOL = 0.4 V;
4
VOH = VDDD − 0.4
IOH
HIGH-level output current
VOH = VDDD − 0.4
−4
-
-
mA
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Objective specification
Rev. 01 — 20 April 2000
17 of 26
SAA8122A
Digital Still Camera Processor (ImagIC family)
Philips Semiconductors
Table 6: Operating characteristics…continued
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IOZ
3-state output leakage current
VO = 0;
-
-
1
µA
VO = VDDD
Data and control I/Os
SD_D[0] to SD_D[15]
VIL
LOW-level digital input voltage
-
0
-
-
-
0.3VDDD
VDDD
0.4
V
VIH
HIGH-level digital input voltage
LOW-level digital output voltage
HIGH-level digital output voltage
input capacitance
-
0.7VDDD
0
V
VOL
VOH
Ci
IOL = 4 mA
V
IOH = −4 mA
V
-
DDD − 0.4 -
VDDD
-
V
-
-
1.2
pF
pF
mA
[1]
Co(L)(max)
IOL
maximum output load capacitance
LOW-level output current
-
-
-
100
-
VOL = 0.4 V;
4
VOH = VDDD − 0.4
IOH
IOZ
HIGH-level output current
VOH = VDDD − 0.4
−4
-
-
-
mA
3-state output leakage current
VO = 0;
-
1
µA
VO = VDDD
IIL
LOW-level input current
HIGH-level input current
VI = 0
-
-
-
-
1
1
µA
µA
IIH
VI = VDDD
A0 to A15, IO8 to IO15, HDHREF, VDVS
VIL
LOW-level digital input voltage
HIGH-level digital input voltage
LOW-level digital output voltage
HIGH-level digital output voltage
input capacitance
-
0
-
-
-
0.6VDDD
V
VIH
-
0.7VDDD
0
VDDD
0.4
VDDD
-
V
VOL
VOH
Ci
IOL = 4 mA
V
IOH = −4 mA
V
-
DDD − 0.4 -
V
-
-
2.5
pF
pF
mA
[1]
Co(L)(max)
IOL
maximum output load capacitance
LOW-level output current
-
-
-
30
VOL = 0.4 V;
4
-
VOH = VDDD − 0.4
IOH
IOZ
HIGH-level output current
VOH = VDDD − 0.4
−4
-
-
-
mA
3-state output leakage current
VO = 0;
-
1
µA
VO = VDDD
IIL
LOW-level input current
HIGH-level input current
VI = 0
-
-
-
-
1
1
µA
µA
IIH
VI = VDDD
IO16 to IO23, IO0/IRQ16, IO1/IRQ17, IO2/IRQ18, IO3/IRQ19, IO4/IRQ20, IO5/IRQ21, IO6/IRQ22, IO7/IRQ23
VIL
LOW-level digital input voltage
HIGH-level digital input voltage
LOW-level digital output voltage
HIGH-level digital output voltage
input capacitance
-
0
-
-
-
0.3VDDD
V
VIH
-
0.7VDDD
0
VDDD
V
VOL
VOH
Ci
IOL = 2 mA
0.4
V
IOH = −2 mA
V
-
DDD − 0.4 -
-
V
-
-
2.3
-
pF
pF
mA
Co(L)(max)
IOL
maximum output load capacitance
LOW-level output current
-
-
-
30
-
VOL = 0.4 V;
2
VOH = VDDD − 0.4
IOH
HIGH-level output current
VOH = VDDD − 0.4
−2
-
-
mA
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Objective specification
Rev. 01 — 20 April 2000
18 of 26
SAA8122A
Digital Still Camera Processor (ImagIC family)
Philips Semiconductors
Table 6: Operating characteristics…continued
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IOZ
3-state output leakage current
VO = 0;
-
-
1
µA
VO = VDDD
IIL
LOW-level input current
HIGH-level input current
VI = 0
-
-
-
-
1
1
µA
µA
IIH
VI = VDDD
IO4 to IO31
VIL
LOW-level digital input voltage
HIGH-level digital input voltage
LOW-level digital output voltage
HIGH-level digital output voltage
input capacitance
-
0
-
-
-
0.8
5.5
0.4
VDDD
-
V
VIH
-
2.0
-
V
VOL
VOH
Ci
IOL = 2 mA
V
IOH = −2 mA
V
-
DDD − 0.4 -
V
-
-
1.5
pF
pF
mA
Co(L)(max)
IOL
maximum output load capacitance
LOW-level output current
-
-
-
30
-
VOL = 0.4 V;
2
VOH = VDDD − 0.4
IOH
IOZ
HIGH-level output current
VOH = VDDD − 0.4
−2
-
-
-
mA
3-state output leakage current
VO = 0;
-
1
µA
VO = VDDD
IIL
LOW-level input current
HIGH-level input current
VI = 0
-
-
-
-
1
1
µA
µA
IIH
VI = VDDD
IO32 to IO39
VIL
LOW-level digital input voltage
HIGH-level digital input voltage
LOW-level digital output voltage
HIGH-level digital output voltage
input capacitance
-
0
-
-
-
0.8
5.5
0.4
VDDD
-
V
VIH
-
2.0
0
V
VOL
VOH
Ci
IOL = 1 mA
V
IOH = −1 mA
V
-
DDD − 0.4 -
V
-
-
1.4
pF
pF
mA
Co(L)(max)
IOL
maximum output load capacitance
LOW-level output current
-
-
-
30
-
VOL = 0.4 V;
1
VOH = VDDD − 0.4
IOH
IOZ
HIGH-level output current
VOH = VDDD − 0.4
−1
-
-
-
mA
3-state output leakage current
VO = 0;
-
1
µA
VO = VDDD
IIL
LOW-level input current
HIGH-level input current
VI = 0
-
-
-
-
1
1
µA
µA
IIH
VI = VDDD
I2C-bus I/Os
SCL and SDA
VIL
LOW-level digital input voltage
HIGH-level digital input voltage
hysteresis voltage
-
0
-
0.3VDDD
V
VIH
-
0
-
0.3VDDD
V
Vhys
VOL
-
0.005VDDD
-
-
V
LOW-level digital output voltage
input capacitance
IOL = 3 mA
-
-
-
-
0.4
-
V
Ci
-
-
3.2
-
pF
pF
[1]
Co(L)(max)
maximum output load capacitance
400
9397 750 07048
© Philips Electronics N.V. 2000. All rights reserved.
Objective specification
Rev. 01 — 20 April 2000
19 of 26
SAA8122A
Digital Still Camera Processor (ImagIC family)
Philips Semiconductors
Table 6: Operating characteristics…continued
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IOZ
3-state output leakage
VO = 0;
-
-
1
µA
VO = VDDD
IIL
LOW-level input current
HIGH-level input current
VI = 0
-
-
-
-
1
1
µA
µA
IIH
VI = VDDD
[1] The maximum capacitance value given does not take into account the signal frequency. For critical signals the maximum capacitance
has to be weighted according to the signal frequency and external devices constraints.
9397 750 07048
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Objective specification
Rev. 01 — 20 April 2000
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9. Package outline
LFBGA324: plastic low profile fine-pitch ball grid array package; 324 balls; body 16 x 16 x 1.2 mm SOT571-1
B
A
D
ball A1
index area
A
2
A
E
A
1
detail X
C
D
1
v M
B
b
y
y
C
1
e
w M
v M
A
V
T
U
R
N
L
e
P
M
K
H
F
E
1
J
G
E
C
A
D
B
2
4
6
8
10 12 14 16 18
11 13 15 17
1
3
5
7
9
X
5
10 mm
0
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
1
A
2
b
E
1
e
y
D
D
E
v
w
y
1
1
max.
0.45 1.35 0.55 16.1
0.35 1.05 0.45 15.9
16.1
15.9
mm 1.70
0.12 0.10
13.6
13.6
0.8
0.15
0.1
REFERENCES
JEDEC
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
EIAJ
00-01-20
SOT571-1
MO-205
Fig 4. SOT571-1.
9397 750 07048
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Objective specification
Rev. 01 — 20 April 2000
21 of 26
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10. Soldering
10.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account
of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit
Packages (document order number 9398 652 90011).
There is no soldering method that is ideal for all surface mount IC packages. Wave
soldering is not always suitable for surface mount ICs, or for printed-circuit boards
with high population densities. In these situations reflow soldering is often used.
10.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and
binding agent) to be applied to the printed-circuit board by screen printing, stencilling
or pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example, infrared/convection heating in a
conveyor type oven. Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating method.
Typical reflow peak temperatures range from 215 to 250 °C. The top-surface
temperature of the packages should preferable be kept below 230 °C.
10.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices
(SMDs) or printed-circuit boards with a high component density, as solder bridging
and non-wetting can present major problems.
To overcome these problems the double-wave soldering method was specifically
developed.
If wave soldering is used the following conditions must be observed for optimal
results:
Use a double-wave soldering method comprising a turbulent wave with high
upward pressure followed by a smooth laminar wave.
•
•
For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be
parallel to the transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the
transport direction of the printed-circuit board.
The footprint must incorporate solder thieves at the downstream end.
For packages with leads on four sides, the footprint must be placed at a 45° angle
to the transport direction of the printed-circuit board. The footprint must
incorporate solder thieves downstream and at the side corners.
•
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Objective specification
Rev. 01 — 20 April 2000
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During placement and before soldering, the package must be fixed with a droplet of
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the adhesive is cured.
Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the
need for removal of corrosive residues in most applications.
10.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low
voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time
must be limited to 10 seconds at up to 300 °C.
When using a dedicated tool, all other leads can be soldered in one operation within
2 to 5 seconds between 270 and 320 °C.
10.5 Package related soldering information
Table 7: Suitability of surface mount IC packages for wave and reflow soldering
methods
Package
Soldering method
Wave
Reflow[1]
suitable
suitable
BGA, LFBGA, SQFP, TFBGA
not suitable
not suitable[2]
HBCC, HLQFP, HSQFP, HSOP, HTQFP,
HTSSOP, SMS
PLCC[3], SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
suitable
suitable
suitable
not recommended[3] [4]
not recommended[5]
[1] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the
maximum temperature (with respect to time) and body size of the package, there is a risk that internal
or external package cracks may occur due to vaporization of the moisture in them (the so called
popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated
Circuit Packages; Section: Packing Methods.
[2] These packages are not suitable for wave soldering as a solder joint between the printed-circuit board
and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top
version).
[3] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave
direction. The package footprint must incorporate solder thieves downstream and at the side corners.
[4] Wave soldering is only suitable for LQFP, QFP and TQFP packages with a pitch (e) equal to or larger
than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
[5] Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
11. Revision history
Table 8: Revision history
Rev Date
CPCN
-
Description
01 20000420
Objective specification; initial version
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Objective specification
Rev. 01 — 20 April 2000
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Philips Semiconductors
12. Data sheet status
[1]
Datasheet status
Product status Definition
Development
Objective specification
This data sheet contains the design target or goal specifications for product development. Specification may
change in any manner without notice.
Preliminary specification Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design and
supply the best possible product.
Product specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any
time without notice in order to improve design and supply the best possible product.
[1]
Please consult the most recently issued data sheet before initiating or completing a design.
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
13. Definitions
Short-form specification — The data in
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
a short-form specification is
Right to make changes — Philips Semiconductors reserves the right to
make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve
design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products
are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
15. Licenses
Purchase of Philips I2C components
Purchase of Philips I2C components conveys a license
under the Philips’ I2C patent to use the components in the
I2C system provided the system conforms to the I2C
specification defined by Philips. This specification can be
ordered using the code 9398 393 40011.
14. Disclaimers
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
9397 750 07048
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Objective specification
Rev. 01 — 20 April 2000
24 of 26
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Philips Semiconductors - a worldwide company
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Yugoslavia: Tel. +381 11 3341 299, Fax. +381 11 3342 553
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For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications,
Building BE, P.O. Box 218, 5600 MD EINDHOVEN,
The Netherlands, Fax. +31 40 272 4825
Internet: http://www.semiconductors.philips.com
(SCA69)
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Objective specification
Rev. 01 — 20 April 2000
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Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
External interfaces . . . . . . . . . . . . . . . . . . . . . . 2
CPU related features . . . . . . . . . . . . . . . . . . . . 2
DSP features . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pulse pattern generator features . . . . . . . . . . . 2
JPEG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
USB interface . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Card interfaces . . . . . . . . . . . . . . . . . . . . . . . . . 3
Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
SDRAM interface features . . . . . . . . . . . . . . . . 3
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
3
4
5
Quick reference data . . . . . . . . . . . . . . . . . . . . . 3
Ordering information. . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
7
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 14
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 14
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 21
8
9
10
10.1
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Introduction to soldering surface mount
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 22
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 22
Manual soldering . . . . . . . . . . . . . . . . . . . . . . 23
Package related soldering information . . . . . . 23
10.2
10.3
10.4
10.5
11
12
13
14
15
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 23
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 24
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
© Philips Electronics N.V. 2000.
Printed in The Netherlands
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 20 April 2000
Document order number: 9397 750 07048
相关型号：
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