SAA9750H [NXP]
Camera Digital Signal Processor CAMDSP; 摄像机数字信号处理器CAMDSP
| 型号： | SAA9750H |
| 厂家： | 
NXP |
| 描述： | Camera Digital Signal Processor CAMDSP |
| 文件： | 总24页 (文件大小：114K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
SAA9750H
Camera Digital Signal Processor
(CAMDSP)
1996 Feb 16
Preliminary specification
File under Integrated Circuits, IC02
Philips Semiconductors
Preliminary specification
Camera Digital Signal Processor
(CAMDSP)
SAA9750H
• Sync Signal Generator (SSG) to generate all necessary
FEATURES
timing signals
• Y/C separator for mosaic filter colour CCD which can be
used with PAL or NTSC CCDs with horizontal resolution
of 510, 670, 720 or 768 pixels
• Serial interface for microprocessor control of CAMDSP
settings
• Y and C signals accessible to incorporate digital
features
• Line sequential colour processing (R−Y) and (B−Y)
• 9 bit input signal (the internal processing is 10-bit)
• Digital feedback clamp control for Y/C separation
• Two 768 × 9 line memories for Y/C separation
• Aperture correction using phase linear filters
• Coring of LOW level signals to reduce noise
• Including digital feature functions (mosaic, sepia,
solarization, slice and negative/positive inversion).
GENERAL DESCRIPTION
The Camera Digital Signal Processor (CAMDSP) is
intended for use with a mosaic filter colour CCD. The IC
generates luminance and chrominance signals from the
CCD signal. The device consists of a luminance and colour
• Colour encoder in accordance with the PAL or NTSC
system. Colour subcarrier is made by a discrete time
oscillator (DTO) operating on system clock
• Slew rate controlled outputs for reduction of digital noise separator employing two 768 × 9 line memories, a
PAL/NTSC encoder, a dual 8-bit video DAC, a Sync Signal
Generator (SSG) and a simple serial interface to control
many settings.
• RGB inputs for title mix
• High accuracy 8 bit DAC outputs for luminance and
chrominance signals
QUICK REFERENCE DATA
SYMBOL
VDDA1
PARAMETER
MIN.
TYP.
MAX.
3.3
UNIT
Y-DAC analog supply voltage (pin 1)
C-DAC analog supply voltage (pin 2)
digital supply voltage (pin 41)
digital supply voltage (pin 53)
digital supply voltage (pin 65)
HIGH level digital input voltage
LOW level digital input voltage
HIGH level digital output voltage
LOW level digital output voltage
operating ambient temperature
2.7
2.7
2.7
2.7
2.7
3.0
3.0
3.0
3.0
3.0
−
V
V
V
V
V
V
V
V
V
°C
VDDA2
VDDD1
VDDD2
VDDD3
VIH
3.3
3.3
3.3
3.3
0.7VDDD
0
VDDD
0.3VDDD
−
VIL
−
VOH
V
DDD − 0.5
−
VOL
−
−
0.5
Tamb
−20
−
+70
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
SAA9750H
LQFP80 plastic low profile quad flat package; 80 leads; body 12 × 12 × 1.4 mm
SOT315-1
1996 Feb 16
2
UV to
0
R
B
V
V
V
UV
V
V
UV
WCLIP TSW
G
LSW
DDD2
65
DDD3 DDD1
SEL
29
DDA1
DDA2
2
7
53
41
21 to 28 20
8
9 10 11 7
1
8
8
3
A
SAA9750H
C
V
ENCODER
C PROCESSING
OUT
D
5
CDS to
0
UV
title mix
8
X2H
9
X0H
ENC
refC
X1H
CDS
FIFO
768 × 9
FIFO
+
8
68 to 76
62
CLAMP
12 to 19
43 to 50
UV
to
ENC0
ENC7
768 × 9
CPOB
UV
TITLE
SWITCH
61
8
Y
to
ENC7
CLAMP
Y
CLAMP
settings
ENC0
Y PROCESSING
Y settings C settings
Y
title mix
8
ENC
ENCODER
settings
80
78
A
30
31
32
Y
V
DELAY
sync
CS
CK
DI
OUT
MICROPROCESSOR
INTERFACE
D
SSG
settings
refY
51
52
66
67
VRST
HRST
CLK1
CLK2
SYNC SIGNAL
GENERATOR
CLOCK
8
64
54
42
58
Y
33 to 40
60
4
79
77
6
59 55 56 63 57
MHA302
V
V
V
TEST1 TEST2 CSYNC
HD
FLD
to Y
SYNCI
V
V
SSA2
SSD2
SSD3 SSD1
0
7
SSA1
VD
CP2
HSYNC
ahdnbok,uflapegwidt
Fig.1 Block diagram.
Philips Semiconductors
Preliminary specification
Camera Digital Signal Processor
(CAMDSP)
SAA9750H
PINNING
SYMBOL
VDDA1
PIN
INPUT/OUTPUT ANALOG/DIGITAL
DESCRIPTION
1
supply
supply
output
supply
−
−
analog supply voltage 1 for Y-DAC
analog supply voltage 2 for C-DAC
C-DAC output
VDDA2
COUT
VSSA1
VrefC
TEST2
LSW
TSW
R
2
−
3
analog
−
4
analog ground 1 for C-DAC
C-DAC decoupling voltage
test 2 pin
5
−
6
input
digital
digital
digital
digital
digital
digital
digital
digital
digital
digital
digital
digital
digital
digital
digital
digital
digital
digital
digital
digital
digital
digital
digital
digital
digital
digital
digital
digital
digital
digital
digital
digital
digital
digital
digital
7
input
line switch for SECAM
8
input
title memory switch
9
input
title memory colour (red)
G
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
input
title memory colour (green)
title memory colour (blue)
B−Y and R−Y signal to encoder (LSB)
B−Y and R−Y signal to encoder
B−Y and R−Y signal to encoder
B−Y and R−Y signal to encoder
B−Y and R−Y signal to encoder
B−Y and R−Y signal to encoder
B−Y and R−Y signal to encoder
B−Y and R−Y signal to encoder (MSB)
white-clip
B
input
UVENC0
UVENC1
UVENC2
UVENC3
UVENC4
UVENC5
UVENC6
UVENC7
WCLIP
UV7
input
input
input
input
input
input
input
input
output
output
output
output
output
output
output
output
output
output
input
time multiplexed B−Y and R−Y (MSB)
time multiplexed B−Y and R−Y
time multiplexed B−Y and R−Y
time multiplexed B−Y and R−Y
time multiplexed B−Y and R−Y
time multiplexed B−Y and R−Y
time multiplexed B−Y and R−Y
time multiplexed B−Y and R−Y (LSB)
B−Y or R−Y active at UV output
microprocessor interface (chip select)
microprocessor interface (clock)
microprocessor interface (data input)
luminance signal (LSB)
UV6
UV5
UV4
UV3
UV2
UV1
UV0
UVSEL
CS
CK
input
DI
input
Y0
output
output
output
output
output
output
output
output
Y1
luminance signal
Y2
luminance signal
Y3
luminance signal
Y4
luminance signal
Y5
luminance signal
Y6
luminance signal
Y7
luminance signal (MSB)
1996 Feb 16
4
Philips Semiconductors
Preliminary specification
Camera Digital Signal Processor
(CAMDSP)
SAA9750H
SYMBOL
VDDD1
PIN
INPUT/OUTPUT ANALOG/DIGITAL
DESCRIPTION
digital supply voltage 1
digital ground 1
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
supply
supply
input
−
VSSD1
YENC7
YENC6
YENC5
YENC4
YENC3
YENC2
YENC1
YENC0
VRST
HRST
VDDD3
VSSD3
VD
−
digital
digital
digital
digital
digital
digital
digital
digital
digital
digital
−
luminance signal to encoder (MSB)
luminance signal to encoder
luminance signal to encoder
luminance signal to encoder
luminance signal to encoder
luminance signal to encoder
luminance signal to encoder
luminance signal to encoder (LSB)
external VD (vertical drive)
external HD (horizontal drive)
digital supply voltage 3
digital ground 3
input
input
input
input
input
input
input
input
input
supply
supply
output
output
output
output
output
input
−
digital
digital
digital
digital
digital
digital
digital
digital
digital
−
VD timing for PPG IC
HD timing for PPG IC
field pulse output
HD
FLD
HSYNC
CSYNC
SYNCI
CLAMP
CPOB
CP2
horizontal timing for YC processing
composite sync pulse
sync input for bypass mode
clamp voltage control
optical black pulse
output (3-state)
input
output
supply
supply
input
clamping pulse
VSSD2
VDDD2
CLK1
CLK2
CDS0
CDS1
CDS2
CDS3
CDS4
CDS5
CDS6
CDS7
CDS8
TEST1
VrefY
digital ground 2
−
digital supply voltage 2
clock 1
digital
digital
digital
digital
digital
digital
digital
digital
digital
digital
digital
digital
−
input
clock 2
input
CDS signal (LSB)
input
CDS signal
input
CDS signal
input
CDS signal
input
CDS signal
input
CDS signal
input
CDS signal
input
CDS signal
input
CDS signal (MSB)
input
test 1 pin
−
Y-DAC decoupling voltage
analog ground 2 for Y-DAC
Y-DAC output
VSSA2
YOUT
supply
output
−
analog
1996 Feb 16
5
Philips Semiconductors
Preliminary specification
Camera Digital Signal Processor
(CAMDSP)
SAA9750H
V
V
1
2
60 SYNCI
59 CSYNC
58 HSYNC
57 FLD
DDA1
DDA2
C
3
OUT
V
4
SSA1
V
5
56 HD
refC
TEST2
LSW
TSW
R
6
55 VD
7
54
53
V
V
SSD3
DDD3
8
9
52 HRST
51 VRST
G
10
11
12
13
14
15
16
17
18
19
SAA9750H
B
50
49
48
47
46
45
44
43
42
41
Y
Y
Y
Y
Y
Y
Y
Y
V
V
ENC0
ENC1
ENC2
ENC3
ENC4
ENC5
ENC6
ENC7
SSD1
DDD1
UV
ENC0
ENC1
ENC2
ENC3
ENC4
ENC5
ENC6
ENC7
UV
UV
UV
UV
UV
UV
UV
WCLIP 20
MHA301
Fig.2 Pin configuration.
6
1996 Feb 16
Philips Semiconductors
Preliminary specification
Camera Digital Signal Processor
(CAMDSP)
SAA9750H
The encoded signal is output via separate 8-bit
FUNCTIONAL DESCRIPTION
digital-to-analog converters (DACs) for luminance and
chrominance. In the event of SECAM the output is a line
sequential −(R−Y)/(B−Y) signal. A line memory interface
allows for mixing of RGB signals in the main signal.
The encoder can be bypassed completely, in this event
only the title mix is carried out before digital-to-analog
conversion.
The Camera Digital Signal Processor (CAMDSP) is
intended for use with a mosaic filter colour CCD.
The input signal is an 8-bit or 9-bit digitized CCD signal.
After AGC and gamma correction, clamping of the input
signal is achieved by feedback clamp level control.
In the luminance processing, symmetrical horizontal and
vertical aperture correction are carried out. Coring is also
carried out to reduce noise at LOW signal levels. In the
chrominance processing, white balance control and matrix
control is adjustable. A false colour correction circuit
reduces aliasing of high frequency input signals.
The SSG generates all necessary timing signals. Timing
signals for external devices NTSC, PAL and SECAM are
also made. The SSG can be locked to an external video
source.
CAMDSP can operate with 510H, 670H, 720H and 768H
colour mosaic CCDs both PAL and NTSC type. In the
510H CCD application the upsampling clock is used for the
encoder part, therefore two clock frequencies (fs and 2fs)
are required.
A white-clip makes the colour white at highlights.
In the encoder part, the colour encoder subcarrier is made
by the discrete time oscillator thus eliminating the use of an
extra crystal. The subcarrier frequency for PAL or NTSC is
selectable. The encoding can be in PAL or NTSC format.
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VDDD
PARAMETER
CONDITIONS
MIN.
−0.5
MAX.
+5.0
UNIT
digital supply voltage
analog supply voltage
total power dissipation
digital input voltage
V
V
VDDA
Ptot
VI
−0.5
−
+5.0
500
mW
V
−0.5
−0.5
−65
−20
−2000
100
VDDD + 0.5
VDDD + 0.5
+150
VO
digital output voltage
storage temperature
V
Tstg
Tamb
Ves
°C
°C
V
operating ambient temperature
electrostatic handling
latch-up protection current
+70
note 1
+2000
−
Ilatch
mA
Note
1. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor.
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
PARAMETER
VALUE
UNIT
thermal resistance from junction to ambient in free air
57
K/W
1996 Feb 16
7
Philips Semiconductors
Preliminary specification
Camera Digital Signal Processor
(CAMDSP)
SAA9750H
DC CHARACTERISTICS
V
DD = 2.7 to 3.3 V; Tamb = −20 to +70 °C; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS
IDD supply current note 1
MIN.
TYP.
60
MAX.
150
UNIT
mA
−
Inputs: LSW, TSW, R, G, B, UVENC0 to UVENC7, CS, CK, DI, YENC0 to YENC7, VRST, HRST, SYNCI, CPOB, CLK1,
CLK2, CDS0 to CDS7, TEST1 and TEST2
VIH
VIL
IIH
HIGH level input voltage
LOW level input voltage
HIGH level input current
LOW level input current
0.7VDD
−
−
−
−
−
V
−
−
−
0.3VDD
V
VIH = VDD
VIL = VSS
1
µA
µA
IIL
−1
Outputs: WCLIP, UV0 to UV7, UVSEL, Y0 to Y7, VD, HD, FLD, HSYNC, CSYNC and CP2
VOH
HIGH level output voltage
IOH = −20 µA
OH = −2 mA
V
V
−
−
DD − 0.1 −
−
V
V
V
V
I
DD − 0.5 −
−
VOL
LOW level output voltage
IOL = +20 µA
−
−
0.1
0.5
IOL = +2 mA
Output: CLAMP (3-state output)
VOH
HIGH level output voltage
LOW level output voltage
3-state leakage current
IOH = −20 µA
V
V
−
−
−
DD − 0.1 −
−
V
I
OH = −8 mA
DD − 0.5 −
−
V
VOL
IOL = +20 µA
−
−
−
0.1
0.5
±5
V
IOL = +8 mA
V
ITL
VIH = VDD; VIL = VSS
µA
Note
1. 510H PAL; VDD = 3 V; DAC RL = 2 kΩ.
DAC CHARACTERISTICS
VDD = 3.0 V; Tamb = +25 °C; RL = open-circuit; unless otherwise specified.
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
Outputs: YOUT and COUT
fCmax
INL
conversion frequency speed
DC integral linearity error
20
−
−
−
−
MHz
LSB
LSB
V
−0.5
−0.5
1.61
−
+0.5
+0.5
1.72
−
DNL
VO(p-p)
RO
DC differential linearity error
full scale output except sync (peak-to-peak value)
internal series output resistance
1.66
75
Ω
1996 Feb 16
8
Philips Semiconductors
Preliminary specification
Camera Digital Signal Processor
(CAMDSP)
SAA9750H
AC CHARACTERISTICS
Microprocessor interface
VDD = 2.7 to 3.3 V; VIL = 0 V; VIH = VDD; Vref = 0.5VDD; Tamb = −20 to +70 °C; input tr and tf = 30 ns; unless otherwise
specified.
SYMBOL
tCSs
PARAMETER
CS set-up time
MIN.
TYP.
MAX.
UNIT
0.4
0.4
0.2
0.4
0.4
−
−
−
−
−
−
−
−
−
−
−
−
µs
µs
µs
µs
µs
tCSh
tCSd
tDs
CS hold time
−
CS deselection time
DI set-up time
−
−
tDh
DI hold time
−
fCK
CK frequency
0.5
−
MHz
µs
tWCKH
tWCKL
tr
HIGH level pulse width of CK
LOW level pulse width of CK
rise time of CK
1.0
1.0
−
−
µs
100
100
ns
tf
fall time of CK
−
ns
t
t
CSd
CSs
V
IH
CS
V
ref
V
IL
t
t
CSh
WCKH
t
WCKL
V
IH
90%
90%
CK
V
ref
10%
10%
V
IL
t
t
f
r
t
t
Dh
Ds
V
IH
V
DI
ref
V
IL
MHA305
Fig.3 Microprocessor interface timing.
9
1996 Feb 16
Philips Semiconductors
Preliminary specification
Camera Digital Signal Processor
(CAMDSP)
SAA9750H
Data input/output timing (CLK1 and CLK2)
VDD = 2.7 to 3.3 V; VIL = 0 V; VIH = VDD; Vref = 0.5VDD;Tamb = −20 to +70 °C; tr and tf = 6 ns; output load
capacitance = 20 pF; unless otherwise specified.
SYMBOL
PARAMETER
data input set-up time
data input hold time
CONDITIONS
note 1
MIN.
TYP.
MAX.
UNIT
ns
tDIs
tDIh
5
8
−
−
−
−
−
−
−
−
−
note 1
ns
ns
ns
%
tDOd
tDOh
tduty
data output delay time
data output hold time
duty factor of CLK1 and CLK2
notes 2 and 3
notes 2 and 3
50
50
−
50
Notes
1. Data inputs: SYNCI, CPOB, CDS0 to CDS8, VRST, HRST, R, G, B, TSW, YENC0 to YENC7, LSW and
UVENC0 to UVENC7
.
2. Data outputs: UVSEL, UV0 to UV7, Y0 to Y7, WCLIP, CSYNC, HSYNC, FLD, HD, VD and CP2.
3. Tamb = +25 °C; VDD = 3.0 V.
t
t
r
f
V
IH
90%
90%
CLK1 and
CLK2
V
ref
10%
10%
V
IL
t
t
DIh
DIs
V
IH
90%
10%
90%
10%
data inputs
V
IL
t
t
DOh
DOd
V
OH
90%
90%
10%
data outputs
10%
V
OL
MHA306
Fig.4 Data input/output timing (CLK1 and CLK2).
10
1996 Feb 16
Philips Semiconductors
Preliminary specification
Camera Digital Signal Processor
(CAMDSP)
SAA9750H
SSG TIMING
Clock count for NTSC and PAL mode
1H
606 (618) clocks
596 (603)
CCD 510H
0
−10 (−15)
50 (45)
SHD
60 (60)
HD
24 (24)
75 (75)
CP2
33 (33)
139 (151)
Y
to Y
0
7
48 (48)
93 (93)
HSYNC
57 (57)
165 (177)
YDA and CDA
62 (62)
107 (107)
SYNC
1H
806 (824) clocks
CCD 670H
SHD
0
80 (80)
80 (80)
HD
32 (32)
100 (100)
CP2
168 (184)
28 (28)
Y
to Y
7
0
48 (48)
108 (108)
HSYNC
195 (203)
51 (51)
YDA and CDA
61 (61)
121 (121)
SYNC
MHA307
Fig.5 SSG timing (continued in Fig.6).
11
1996 Feb 16
Philips Semiconductors
Preliminary specification
Camera Digital Signal Processor
(CAMDSP)
SAA9750H
1H
CCD 720H
0
858 (864) clocks
83 (83)
SHD
83 (83)
HD
36 (36)
104 (104)
CP2
34 (34)
172 (182)
Y
to Y
7
0
50 (50)
113 (113)
HSYNC
63 (63)
209 (229)
YDA and CDA
67 (67)
130 (130)
SYNC
1H
910 (908) clocks
CCD 768H
SHD
0
89 (89)
89 (89)
HD
36 (36)
108 (108)
CP2
191 (203)
33 (33)
Y
to Y
7
0
54 (54)
121 (121)
HSYNC
223 (235)
65 (63)
YDA and CDA
71 (71)
138 (138)
SYNC
MHA308
Fig.6 SSG timing (continued from Fig.5).
SHD: HD output can be changed by microprocessor to SHD outputs.
HD: For timing of input CDS signal for PPG IC.
HSYNC: For output luminance signal Y7 to Y0 and chrominance signal UV7 to UV0 of CAMDSPs YC processing.
SYNC: Composite SYNC pulse of DACs output.
Output of CSYNC (pin 59): SYNC + 1 clock (see Figs 5 and 6).
1996 Feb 16
12
Philips Semiconductors
Preliminary specification
Camera Digital Signal Processor
(CAMDSP)
SAA9750H
Clock
Table 1 Clock frequency
MODE
CCD
CLK1 (MHz)
CLK2 (MHz)
NTSC
510H
670H
720H
768H
510H
670H
720H
768H
9.5350
19.0699
12.7132
13.5000
14.3182
9.6563
−
−
−
PAL
SECAM
19.3125
12.8750
13.5000
14.1875
−
−
−
Table 2 Clock used for each block
MODE SSG BLOCK
510H NTSC/PAL CLK1
Other modes CLK1
ENCODER
BLOCK
Y/C BLOCK
Y-DAC BLOCK
C-DAC BLOCK
CLK1
CLK1
CLK1 and CLK2
(upsampling)
CLK1
CLK2
CLK1
CLK1
CLK1
MICROPROCESSOR INTERFACE FORMAT
CS
CK
DI
MSB
LSB MSB
(1)
LSB MSB
LSB
MHA304
slave address
subaddress
data
(1) Slave address 001.
Fig.7 Microprocessor interface format.
1996 Feb 16
13
Philips Semiconductors
Preliminary specification
Camera Digital Signal Processor
(CAMDSP)
SAA9750H
Table 3 Microprocessor interface format
DATA
FUNCTION
Field delay
SUBADDRESS
MSB
LSB
00000
00000
00000
00000
00000
00000
00000
00001
00010
00011
00011
00100
00101
00110
00110
00111
01000
01001
01010
01010
01010
01010
01011
01101
01110
01110
01110
01110
01110
01111
01111
01111
01111
10000
10001
10010
10011
X
X
X
X
X
X
X
X
X
X
X
X
−
−
−
−
−
−
−
−
FD
−
Title enable
Title polarity
False colour +6 dB
UV +6 dB
Y +6 dB
−
−
−
−
TE
−
−
−
−
TP
−
−
−
−
−
FCU
−
−
−
−
CUP
−
−
−
−
−
−
YUP
−
−
−
−
−
Y clear
YCL
X
−
−
−
−
−
HAP LOW clip
VAP LOW clip
AP HIGH clip
AP gain
HA5
VA5
−
HA4
VA4
−
HA3
VA3
AP3
−
HA2
VA2
AP2
−
HA1
VA1
AP1
−
HA0
VA0
AP0
−
X
−
AG2
X
AG1
YG5
YP5
X
AG0
YG4
YP4
−
Y gain
YG3
YP3
−
YG2
YP2
−
YG1
YP1
SLI
−
YG0
YP0
SNP
−
Y pedestal
Slice
YP7
X
YP6
X
Mosaic
X
X
X
MOS
SLL4
S4
S12
−
PX1
SLL3
S3
S11
S19
−
PX0
SLL2
S2
S10
S18
−
Slice level
Subcarrier
SLL7
S7
S15
−
SLL6
S6
S14
−
SLL5
S5
S13
−
SLL1
S1
S9
S17
−
SLL0
S0
S8
S16
−
UV polarity
SYNCI
−
−
−
UVP
−
−
−
SYN
−
−
−
−
−
Encoder mode
Burst level
HRST delay
EM1
X
EM0
BL6
D6
−
−
−
−
−
−
BL5
D5
−
BL4
D4
−
BL3
D3
−
BL2
D2
−
BL1
D1
D9
−
BL0
D0
D8
−
D7
−
CCD type
−
−
−
−
H1
−
H0
−
525/625 line
Master/slave
ADC delay
Solarization
−
−
−
LL
−
−
−
−
MS
−
−
−
−
−
−
AD1
X
AD0
X
−
−
−
−
−
X
−
−
−
TR1
−
TR0
−
X
X
X
−
−
SOL
−
Sepia
X
X
X
−
SEP
−
−
−
Negative/positive
R gain
X
X
X
NP
RG4
BG4
UGP4
UGN4
−
−
−
X
RG6
BG6
X
RG5
BG5
UGP5
UGN5
RG3
BG3
UGP3
UGN3
RG2
BG2
UGP2
UGN2
RG1
BG1
UGP1
UGN1
RG0
BG0
UGP0
UGN0
B gain
X
U gain
X
X
X
1996 Feb 16
14
Philips Semiconductors
Preliminary specification
Camera Digital Signal Processor
(CAMDSP)
SAA9750H
DATA
FUNCTION
V gain
SUBADDRESS
MSB
LSB
10100
10101
10110
10111
11000
11001
11010
11010
11010
11010
11010
11011
11100
11101
11101
X
X
X
X
X
X
X
X
X
X
X
X
VGP5
VGN5
UM5
UN5
VM5
VN5
X
VGP4
VGN4
UM4
UN4
VM4
VN4
−
VGP3
VGP2
VGN2
UM2
UN2
VM2
VN2
−
VGP1
VGN1
UM1
UN1
VM1
VN1
−
VGP0
VGN0
UM0
UN0
VM0
VN0
SPP
−
X
VGN3
UM3
UN3
VM3
VN3
−
U matrix 1 gain
U matrix 2 gain
V matrix 1 gain
V matrix 2 gain
SP polarity
X
X
X
X
X
FH2 polarity
Colour filter
HD, VD polarity
Sub LPF
X
X
−
−
−
FHP
−
X
X
−
−
LPF
−
−
X
X
−
SHV
−
−
−
X
X
JGM
TH4
WC4
X
−
−
−
False colour
White-clip level
Y delay
TH7
WC7
X
TH6
WC6
X
TH5
WC5
X
TH3
WC3
−
TH2
WC2
−
TH1
WC1
YDL1
−
TH0
WC0
YDL0
−
C delay
X
X
X
X
CDL1
CDL0
Table 4 Explanation of functions of Table 3
SYMBOL
DESCRIPTION
FD
field delay control
title enable control
title polarity control
false colour plus 6 dB up
UV +6 dB up
TE
TP
FCU
CUP
YUP
Y gain +6 dB up
Y clear control
YCL
HA0 to HA5
VA0 to VA5
AP0 to AP3
AG0 to AG2
YG0 to YG5
YP0 to YP7
SNP
horizontal aperture LOW clip level control
vertical aperture LOW clip level control
aperture HIGH clip level control
aperture gain control
Y gain control
Y pedestal control
slice effect polarity
SLI
slice ON/OFF
PX0 and PX1
MOS
mosaic effect pixels control
mosaic ON/OFF
SLL0 to SLL7
S0 to S19
UVP
slice level control
subcarrier control
UVSEL polarity control
SYNC signal selection
SYN
1996 Feb 16
15
Philips Semiconductors
Preliminary specification
Camera Digital Signal Processor
(CAMDSP)
SAA9750H
SYMBOL
DESCRIPTION
EM0 and EM1
BL0 to BL6
D0 to D9
encoder mode control
burst level control
HRST and VRST preset control
CCD type selection
H0 and H1
LL
525/625 line control
MS
master/slave control
AD0 and AD1
TR0 and TR1
SOL
ADC delay control
solarization effect control
solarization ON/OFF
SEP
sepia ON/OFF
NP
negative/positive ON/OFF
red gain control
RG0 to RG6
BG0 to BG6
UGP0 to UGP5
UGN0 to UGN5
VGP0 to VGP5
VGN0 to VGN5
UM0 to UM5
UN0 to UN5
VM0 to VM5
VN0 to VN5
SPP
blue gain control
U gain control for positive side
U gain control for negative side
V gain control for positive side
V gain control for negative side
U matrix 1 gain control
U matrix 2 gain control
V matrix 1 gain control
V matrix 2 gain control
SP polarity control
FHP
FH2 polarity control
LPF
colour filter control
SHV
HD and VD polarity control
sub LPF control for false colour
JGM
TH0 to TH7
WC0 to WC7
YDL0 and YDL1
CDL0 and CDL1
threshold control for false colour suppression
white-clip level control
Y delay control
C delay control
1996 Feb 16
16
Philips Semiconductors
Preliminary specification
Camera Digital Signal Processor
(CAMDSP)
SAA9750H
Horizontal aperture LOW clip level control = HA5 to HA0.
Vertical aperture LOW clip level control = VA5 to VA0.
Aperture HIGH clip level control = AP3 to AP0.
MICROPROCESSOR SETTING
Table 5 Field delay control
FIELD DELAY CONTROL
Normal
FD
0
AG [2:0]
Aperture gain control =
------------------------
8
One field delay
1
YG [5:0]
Y gain control =
------------------------
32
Table 6 Title enable control
TITLE ENABLE CONTROL
Title insertion OFF
TE
0
Y pedestal level control = YP7 to YP0.
Table 12 Slice effect polarity
Title insertion ON
1
SLICE EFFECT POLARITY
SNP
Table 7 Title polarity control
Negative
Positive
0
1
TITLE POLARITY CONTROL
TP
0
Negative
Positive
Table 13 Slice ON/OFF
1
SLICE ON/OFF
SLI
Table 8 False colour +6 dB up
OFF normal
ON slice
0
1
FALSE COLOUR +6 dB UP
FCU
0 dB gain
0
1
Table 14 Mosaic effect pixels control
+6 dB gain
MOSAIC EFFECT PIXELS CONTROL PX1
PX0
Table 9 UV +6 dB up
4 × 4 pixels
0
0
1
1
0
1
0
1
UV +6 dB UP
CUP
8 × 8 pixels
0 dB gain
0
1
16 × 16 pixels
32 × 32 pixels
+6 dB gain
Table 10 Y gain +6 dB up
Table 15 Mosaic ON/OFF
Y GAIN +6 dB UP
YUP
MOSAIC ON/OFF
MOS
0 dB gain
0
1
OFF normal
ON mosaic
0
1
+6 dB gain
Table 11 Y clear control
Slice level control = SLL7 to SLL0.
Y CLEAR CONTROL
YCL
S [19:0] × fencoder
Normal
Clear
0
1
Subcarrier frequency control =
------------------------------------------------
1048576
1996 Feb 16
17
Philips Semiconductors
Preliminary specification
Camera Digital Signal Processor
(CAMDSP)
SAA9750H
Table 16 UVSEL polarity control
Table 21 Master/slave control
MASTER/SLAVE CONTROL
MS
UVSEL POLARITY
UVP
CONTROL
Master
Slave
0
1
Normal
Invert
0 HIGH: U(B−Y) LOW: V(R−Y)
1 HIGH: V(R−Y) LOW: U(B−Y)
Table 22 AD converter delay control
Table 17 SYNC signal selection
ADC DELAY CONTROL
(CAMDSP DELAY)
AD1
AD0
SYNC SIGNAL SELECTION
SYN
3Ts
4Ts
5Ts
6Ts
0
0
1
1
0
1
0
1
Internal SYNC
0
1
External SYNC (from SYNCI pin 60)
Table 18 Encoder mode control
ENCODER MODE CONTROL
EM1
EM0
Table 23 Solarization effect control
PAL
0
0
1
1
0
1
0
1
SOLARIZATION EFFECT CONTROL
(SLICE OF BITS)
NTSC
SECAM
Bypass
TR1
TR0
3 bits (LSB)
4 bits (LSB)
5 bits (LSB)
6 bits (LSB)
0
0
1
1
0
1
0
1
BL [6:0]
Burst level control =
(of full-scale DAC output).
----------------------
128
HRST and VRST preset control = D9 to D0, preset
horizontal counter to count D9 to D0.
Table 24 Solarization ON/OFF
SOLARIZATION ON/OFF
SOL
Table 19 CCD type selection
Normal
0
1
Solarization ON
CCD TYPE SELECTION
H1
H0
510H
670H
720H
768H
0
0
1
1
0
1
0
1
Table 25 Sepia ON/OFF
SEPIA ON/OFF
SEP
Normal
0
1
Sepia ON
Table 20 525/625 line control
525/625 LINE CONTROL
Table 26 Negative/positive ON/OFF
LL
0
NEGATIVE/POSITIVE ON/OFF
NP
1
525 line
625 line
Normal
1
Negative
0
1996 Feb 16
18
Philips Semiconductors
Preliminary specification
Camera Digital Signal Processor
(CAMDSP)
SAA9750H
Table 29 Colour filter control
RG [6:0]
------------------------ (1)
128
R channel gain control = 1 +
B channel gain control = 1 +
COLOUR FILTER
CONTROL
LPF
BG [6:0]
------------------------ (1)
128
LPF1
LPF2
0
1
[1,1,3,3,4,4,4,4,3,3,1,1]/32
[−1,0,4,8,10,8,4,0,−1]/32
UGP [5:0]
-----------------------------
16
U gain control for positive side =
U gain control for negative side =
V gain control for positive side =
V gain control for negative side =
Table 30 HD and VD polarity control
UGN [5:0]
-----------------------------
16
HD AND VD POLARITY CONTROL
SHV
Normal
Invert
0
1
VGP [5:0]
----------------------------
16
Table 31 Sub LPF control for false colour
VGN [5:0]
-----------------------------
16
SUB LPF CONTROL FOR FALSE COLOUR
JGM
Normal
0
1
UM [5:0]
------------------------ (1)
32
U matrix 1 gain control =
U matrix 2 gain control =
V matrix 1 gain control =
V matrix 2 gain control =
Sub LPF
UN [5:0]
------------------------ (1)
32
Threshold control for false colour suppress = TH7 to TH0.
White clip level control = 2 × WC7 to WC0.
VM [5:0]
------------------------ (1)
32
Table 32 Y delay control
VN [5:0]
----------------------- (1)
32
Y DELAY CONTROL
0 clock period
YDL1
YDL0
0
0
1
1
0
1
0
1
+1 clock period
+2 clock periods
+3 clock periods
Table 27 SP polarity control
SP POLARITY CONTROL
SPP
Normal
H: Ye + Mg or Ye + Gr
L: Cy + Gr or Cy + Mg
H: Cy + Gr or Cy + Mg
L: Ye + Mg or Ye + Gr
0
1
Table 33 C delay control
Invert
C DELAY CONTROL
CDL1
CDL0
0 clock period
0
0
1
1
0
1
0
1
+1 clock period
+2 clock periods
+3 clock periods
Table 28 FH2 polarity control
FH2 POLARITY CONTROL
Normal
FHP
H: 2B-G
L: 2R-G
H: 2R-G
L: 2B-G
0
1
Invert
(1) RG, BG, UM, UN, VM and VN are twos complement.
1996 Feb 16
19
CAMERA
Y
C
zoom
encoder
focus
sensor
hall
sensor
LPF
BPF
CCD
CLAMP
8-bit
CAMDSP
SIGNAL
PROCESSOR
Y/C SEPARATION
SSG
Y (8-bit)
CDS
AGC, GAMMA
ADC
AGC
UV (8-bit)
serial
data bus
ENCODER
HD/VD
UV
SAA9750H
zoom
lens
focus
lens
ADC
iris
SEL
UV(8)
Y(5)
HSYNC
WCLIP
PPG
DAC
MICRO-
PROCESSOR
high speed
shuffle control
I/F(8)
3
A2CF
AF/AE/AWB
MOTOR
DRIVER
MOTOR
DRIVER
IRIS
DRIVER
CDS(8)
SAA9750H
MHA303
Fig.8 Camera block diagram (SAA9750H and SAA9740H).
Philips Semiconductors
Preliminary specification
Camera Digital Signal Processor
(CAMDSP)
SAA9750H
PACKAGE OUTLINE
LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm
SOT315-1
y
X
A
60
41
Z
61
40
E
e
H
A
E
2
E
A
(A )
3
A
1
w M
p
θ
b
L
p
L
pin 1 index
80
21
detail X
1
20
Z
D
v M
A
e
w M
b
p
D
B
H
v M
B
D
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
θ
1
2
3
p
E
p
D
E
max.
7o
0o
0.16 1.5
0.04 1.3
0.27 0.18 12.1 12.1
0.13 0.12 11.9 11.9
14.15 14.15
13.85 13.85
0.75
0.30
1.45 1.45
1.05 1.05
mm
1.6
0.25
0.5
1.0
0.2 0.15 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-12-19
97-07-15
SOT315-1
1996 Feb 16
21
Philips Semiconductors
Preliminary specification
Camera Digital Signal Processor
(CAMDSP)
SAA9750H
If wave soldering cannot be avoided, the following
conditions must be observed:
SOLDERING
Introduction
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
Even with these conditions, do not consider wave
soldering LQFP packages LQFP48 (SOT313-2),
LQFP64 (SOT314-2) or LQFP80 (SOT315-1).
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011). During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Reflow soldering
Reflow soldering techniques are suitable for all LQFP
packages.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Repairing soldered joints
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
Wave soldering
Wave soldering is not recommended for LQFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
1996 Feb 16
22
Philips Semiconductors
Preliminary specification
Camera Digital Signal Processor
(CAMDSP)
SAA9750H
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1996 Feb 16
23
Philips Semiconductors – a worldwide company
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Indonesia: Philips House, Jalan H.R. Rasuna Said Kav. 3-4,
P.O. Box 4252, JAKARTA 12950,
Tel. (02)70-4044, Fax. (02)92 0601
Tel. (021)5201 122, Fax. (021)5205 189
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. (01)7640 000, Fax. (01)7640 200
Italy: PHILIPS SEMICONDUCTORS S.r.l.,
Piazza IV Novembre 3, 20124 MILANO,
Tel. (0039)2 6752 2531, Fax. (0039)2 6752 2557
Japan: Philips Bldg 13-37, Kohnan2-chome, Minato-ku, TOKYO 108,
Tel. (03)3740 5130, Fax. (03)3740 5077
Korea: Philips House, 260-199 Itaewon-dong,
Internet: http://www.semiconductors.philips.com/ps/
For all other countries apply to: Philips Semiconductors,
International Marketing and Sales, Building BE-p,
P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands,
Telex 35000 phtcnl, Fax. +31-40-2724825
Yongsan-ku, SEOUL, Tel. (02)709-1412, Fax. (02)709-1415
SCDS47
© Philips Electronics N.V. 1996
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA,
SELANGOR, Tel. (03)750 5214, Fax. (03)757 4880
Mexico: 5900 Gateway East, Suite 200, EL PASO, TX 79905,
Tel. 9-5(800)234-7381, Fax. (708)296-8556
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. (040)2783749, Fax. (040)2788399
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
All rights are reserved. Reproduction in whole or in part is prohibited without the
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The information presented in this document does not form part of any quotation
or contract, is believed to be accurate and reliable and may be changed without
notice. No liability will be accepted by the publisher for any consequence of its
use. Publication thereof does not convey nor imply any license under patent- or
other industrial or intellectual property rights.
Tel. (09)849-4160, Fax. (09)849-7811
Norway: Box 1, Manglerud 0612, OSLO,
Tel. (022)74 8000, Fax. (022)74 8341
Printed in The Netherlands
Pakistan: Philips Electrical Industries of Pakistan Ltd.,
Exchange Bldg. ST-2/A, Block 9, KDA Scheme 5, Clifton,
KARACHI 75600, Tel. (021)587 4641-49,
Fax. (021)577035/5874546
537021/1100/01/pp24
Date of release: 1996 Feb 16
9397 750 00641
Document order number:
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