SAF3560EL/V1102_技术文档

SAF3560

Terrestrial digital radio processor

Rev. 5 — 8 February 2013

Product short data sheet

1. General description

The SAF3560 is a digital radio processor that demodulates and processes digital

terrestrial baseband signals, such as HD Radio signals, into audio signals and digital data

signals.

OPTIONAL AUDIO POST

blended

audio (analog)

PROCESSING

AND STEREO

AUDIO DAC

TUNER1

IF PROCESSING

baseband blend digital

2

I S

audio

interface

SERIAL NOR-FLASH

MEMORY

SPI2

SAF3560

SDRAM

2

I C-bus or SPI1

2

baseband I S

interface

RENDERING

OF DATA:

TUNER2

IF PROCESSING

MICROPROCESSOR

LIVE TRAFFIC REPORTS

WEATHER

SPORTS SCORES

STOCK TICKER

001aal423

(1) The second input is only supported by specific types (see Table 3)

Fig 1. System block diagram

Major benefits of terrestrial radio processor systems with SAF3560 are:

• Compatibility with conventional baseband radio reception ICs

• Dramatically improved reception and sound quality

• CD-sound quality without noise, interference and multipath fading for FM

• Providing new data services

• HD Radio reception including audio processing

• Voltage partitioning of I/Os

• Available in both LFBGA and HLQFP packages

SAF3560

NXP Semiconductors

Terrestrial digital radio processor

System designers can add digital terrestrial radio capability in a simple and inexpensive

way through the SAF3560. The SAF3560 decodes digital radio input to provide digital

audio and also processes digital data. Multiple interfaces give flexibility while integrating

the SAF3560 into the receiver system.

2. Features and benefits

2.1 HD Radio technology

 HD Radio signal decoding for AM and FM digital audio

 Dual HD Radio support for support of second station for background scanning and

data service

 Front end to baseband interface support through serial baseband I²S-bus type

interface

 Secondary baseband interface for dual tuner applications

 Metadata support for HD Radio reception

 Data services support for HD Radio reception

 Advanced HD Radio feature support, such as¹:

 Conditional Access (CA)

 Store and replay

 Apple ID3 tag

 Multicasting

 Electronic Program Guide (EPG)

2.2 Digital audio

 Up to 6 channel (5.1) audio support through I²S-bus serial audio interface

 Optional SRC (8 kHz to 48 kHz) for up to 6 channels of I²S-bus audio output

 I²S-bus serial audio input for auxiliary processing

 Optional SRC (8 kHz to 48 kHz) for I²S-bus input

 Optional restricted support for 96 kHz input and output sample-rate conversion

 Optional digital audio output through S/PDIF (without SRC)

 Basic audio processing for external digital audio sources

 Advanced audio processing (contact NXP Semiconductors for a list of supported audio

processing features: Section 14 “Contact information”)

2.3 Memory

 Supports SDR-SDRAM controller (up to 512 Mbit in 16-bit configuration)

 Supports serial NOR-Flash memory with various sizes depending on the actual

application

1. Contact NXP Semiconductors for a detailed list of supported feature sets: Section 14 “Contact information”.

SAF3560_SDS

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Product short data sheet

Rev. 5 — 8 February 2013

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SAF3560

NXP Semiconductors

Terrestrial digital radio processor

2.4 Other peripheral interfaces

 Two I²C-bus interfaces

 Three Serial Peripheral Interfaces (SPI)

 One UART interface

 Five individual GPIO pins for applications and diagnostics

 One JTAG interface for diagnostics

2.5 Miscellaneous

 One internal clock oscillator and two internal Phase-Locked Loops (PLL)

 Can run on external crystal or reference clock from an external IC

 Powerful signal and audio processing core architecture

 Qualified in accordance with AEC-Q100

3. Quick reference data

Table 1.

Power supply characteristics

After power-up the SAF3560 needs a reset pulse for at least 2 ms.

Symbol

Parameter

Conditions

Min

Typ

Max Unit

Supply voltages

V_{DDA(OSC)(1V2)}

V_{DDA(PLL)(1V2)}

V_DDD(C)(1V2)

oscillator analog supply voltage (1.2 V)

PLL analog supply voltage (1.2 V)

1.14 1.2

1.32

3.6

V

core digital supply voltage (1.2 V)

V_DDD(GP)(3V3)

V_{DDD(DSP)(3V3)}

V_{DDD(JTAG)(3V3)}

V_DDD(MC)(3V3)

V_{DDD(MEM)(1V2)}

general purpose digital supply voltage (3.3 V)

DSP digital supply voltage (3.3 V)

3.0

3.3

3.6

JTAG digital supply voltage (3.3 V)

microcontroller digital supply voltage (3.3 V)

memory digital supply voltage (1.2 V)

3.6

1.14 1.2

1.32

3.6

V_{DDD(SDRAM)(3V3)}SDRAM digital supply voltage (3.3 V)

3.0

3.3

Supply currents

[1]

[2]

I_DD

supply current

all core related blocks

all I/O related blocks

-

90

28

116

37

mA

Power dissipation

P_tot

total power dissipation

-

0.2

0.5

W

[1] Through pins V_{DDA(OSC)(1V2)}, V_{DDA(PLL)(1V2)}, V_DDD(C)(1V2)and V_{DDD(MEM)(1V2)}

.

[2] Through pins V_DDD(GP)(3V3), V_{DDD(DSP)(3V3)}, V_{DDD(JTAG)(3V3)}, V_DDD(MC)(3V3)and V_{DDD(SDRAM)(3V3)}

.

SAF3560_SDS

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Product short data sheet

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SAF3560

NXP Semiconductors

Terrestrial digital radio processor

4. Ordering information

Table 2.

Ordering information

Type number

Package

Name

Description

Version

SAF3560HV/V110x

SAF3560EL/V110x

HLQFP144 plastic thermal enhanced low profile quad flat package; 144 leads;

SOT612-4

body 20  20  1.4 mm; exposed die pad

LFBGA170 plastic low profile fine pitch ball grid array package; 170 balls

SOT1315-1

Table 3.

Subtypes and main applications

Type number

SAF3560xx/V1100

Main application

Option

HLQFP144 LFBGA170

HD Radio 1.0, supporting external clock from NXP

radio/audio DSPs^[1]

single tuner

yes

SAF3560xx/V1101

SAF3560xx/V1102

HD Radio 1.0 + Conditional Access (CA)

single tuner

dual tuner

yes

no

HD Radio 1.5, supporting external clock from NXP

radio/audio DSPs^[1]

yes

SAF3560xx/V1103

SAF3560xx/V1104

HD Radio 1.5 + Conditional Access (CA)

dual tuner

yes

no

HD Radio 1.0 + Conditional Access (CA), supporting

external clock from NXP radio/audio DSPs^[1]

single tuner

yes

SAF3560xx/V1105

HD Radio 1.5 + Conditional Access (CA), supporting

external clock from NXP radio/audio DSPs^[1]

dual tuner

yes

[1] Contact NXP Sales regarding supported radio/audio DSPs: Section 14 “Contact information”.

SAF3560_SDS

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Product short data sheet

Rev. 5 — 8 February 2013

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SAF3560

NXP Semiconductors

Terrestrial digital radio processor

6. Pinning information

6.1 Pinning

SAF3560

1

108

36

73

001aah072

Fig 3. Pin configuration (HLQFP144)

Table 4.

Pin allocation table (HLQFP144)

Pin Symbol

1

CLKOUT

2

RESET_N

3

I2C1_SCL

I2C2_SCL

SPI1_SI

4

I2C1_SDA

I2C2_SDA

SPI1_SCLK

SPI2_MI

5

I2C1_DA

6

V_DDD(MC)(3V3)

SPI1_SO

V_DDD(C)(1V2)

SPI2_SCLK

SPI2_SS3_N

UART_RTS

SPI3_MISO

V_DDD(GP)(3V3)

GPIO2

7

8

9

I2C2_DA

10

14

18

22

26

30

34

38

42

46

50

54

58

62

66

70

74

11

15

19

23

27

31

35

39

43

47

51

55

59

63

67

71

75

12

16

20

24

28

32

36

40

44

48

52

56

60

64

68

72

76

13

17

21

25

29

33

37

41

45

49

53

57

61

65

69

73

SPI1_SS_N

SPI2_MO

V_DDD(MC)(3V3)

UART_RD

UART_CTS

SPI3_SS1_N

GPIO1

V_DDD(MC)(3V3)

SPI2_SS1_N

SPI2_SS4_N

V_DDD(C)(1V2)

SPI3_MOSI

SPI3_SS2_N

GPIO3

SPI2_SS2_N

UART_TD

V_DDD(MC)(3V3)

SPI3_SCLK

GPIO0

GPIO4

[1]

-

V_DDD(GP)(3V3)

-

BB1_I2S_BCK

BB2_I2S_BCK

V_DDD(C)(1V2)

I2S1_O_WS

V_{DDD(DSP)(3V3)}

I2S_I_BCK

BB1_I2S_WS

BB2_I2S_WS

V_{DDD(DSP)(3V3)}

I2S1_O_SD

I2S2_O_SD

I2S_I_SD

BB1_I2S_I

BB2_I2S_I

HBCKOUT

BLEND

BB1_I2S_Q

BB2_I2S_Q

I2S1_O_BCK

V_{DDD(MEM)(1V2)}

I2S_I_WS

I2S3_O_SD/

SPDIF_O

77

81

85

89

SDRAM_DIO0

SDRAM_DIO3

78

82

SDRAM_DIO1

SDRAM_DIO4

SDRAM_DIO7

79

83

87

SDRAM_DIO2

SDRAM_DIO5

SDRAM_DIO8

V_DDD(C)(1V2)

80

84

88

92

V_{DDD(SDRAM)(3V3)}

SDRAM_DIO6

SDRAM_DIO9

SDRAM_DIO11

V_{DDD(SDRAM)(3V3)}86

SDRAM_DIO10 90

V_{DDD(SDRAM)(3V3)}91

SAF3560_SDS

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Product short data sheet

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SAF3560

NXP Semiconductors

Terrestrial digital radio processor

Table 4.

Pin allocation table (HLQFP144) …continued

Pin Symbol Pin Symbol

SDRAM_DIO12 94 SDRAM_DIO13 95 SDRAM_DIO14 96

SDRAM_DIO15 98 SDRAM_WE_N 99 SDRAM_DQM0 100 SDRAM_DQM1

103 SDRAM_BA0 104 SDRAM_BA1

106 SDRAM_RAS_N 107 V_{DDD(SDRAM)(3V3)}108 SDRAM_CAS_N

Pin Symbol

V_{DDD(SDRAM)(3V3)}

93

97

101 V_{DDD(SDRAM)(3V3)}102 V_{DDD(MEM)(1V2)}

105 SDRAM_CS_N

109 SDRAM_CLKE

113 SDRAM_AO2

117 SDRAM_AO5

121 SDRAM_AO9

125 SDRAM_AO11

110 SDRAM_AO0

114 SDRAM_AO3

118 SDRAM_AO6

111 SDRAM_AO1

115 SDRAM_AO4

119 SDRAM_AO7

112 V_{DDD(SDRAM)(3V3)}

116 V_{DDD(SDRAM)(3V3)}

120 SDRAM_AO8

124 V_DDD(C)(1V2)

128 SDRAM_CLKIN

132 TCK

122 V_{DDD(SDRAM)(3V3)}123 SDRAM_AO10

126 SDRAM_AO12

127 SDRAM_CLK

131 TRST_N

[2]

129 V_{DDD(SDRAM)(3V3)}130 V_SS

133 TMS

134 V_DDD(C)(1V2)

135 TDI

136 TDO

[2]

137 V_SS

138 V_{DDD(JTAG)(3V3)}

142 XTALO

139 V_{DDA(PLL)(1V2)}

143 V_{DDD(MEM)(1V2)}

140 V_{DDA(OSC)(1V2)}

[2]

141 XTALI

144 V_SS

[1] See Table 15 for unused pins.

[2] Global V_SSpin at backside contact.

ball A1

index area

SAF3560EL

1

2

3

4

5

6

7

8

9 10 11 12 13 14

A

B

C

D

E

F

G

H

J

K

L

M

N

P

aaa-001870

Transparent top view

Fig 4. Pin configuration (LFBGA170)

Table 5. Pin allocation table (LFBGA170)

Pin Symbol

Row A

Pin Symbol

A3 XTALI

A4 XTALO

A5 V_{DDA(PLL)(1V2)}

A9 V_DDD(C)(1V2)

A12 V_{DDD(SDRAM)(3V3)}A13 SDRAM_AO4

A6 TDI

A7 SDRAM_CLKIN A8 SDRAM_CLK

A11 SDRAM_AO5

A10 SDRAM_AO8

SAF3560_SDS

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Product short data sheet

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SAF3560

NXP Semiconductors

Terrestrial digital radio processor

Table 5.

Pin allocation table (LFBGA170)

Pin Symbol

Row B

Pin Symbol

B1 RESET_N

B5 V_{DDD(JTAG)(3V3)}

B9 SDRAM_AO10

B13 SDRAM_AO2

Row C

B2 CLKOUT

B3 V_{DDD(MEM)(1V2)}

B7 TRST_N

B11 V_SS

B4 V_SS

B6 V_DDD(C)(1V2)

B10 SDRAM_AO7

B14 V_{DDD(SDRAM)(3V3)}

B8 V_SS

B12 SDRAM_AO3

C1 I2C1_DA

C5 V_SS

C2 I2C1_SDA

C6 TMS

C3 I2C1_SCL

C7 V_SS

C4 V_{DDA(OSC)(1V2)}

C8 SDRAM_AO12

C12 SDRAM_AO0

C9 V_{DDD(SDRAM)(3V3)}C10 V_SS

C11 SDRAM_AO1

C13 V_SS

C14 SDRAM_CLKE

Row D

D1 I2C2_DA

D5 TDO

D2 I2C2_SDA

D6 TCK

D3 I2C2_SCL

D4 V_DDD(MC)(3V3)

D7 V_{DDD(SDRAM)(3V3)}D8 SDRAM_AO11

D9 SDRAM_AO9

D10 SDRAM_AO6

D11 SDRAM_CS_N

D12 SDRAM_RAS_N

D13 V_{DDD(SDRAM)(3V3)}D14 SDRAM_CAS_N

Row E

E1 SPI1_SS_N

E11 V_{DDD(MEM)(1V2)}

Row F

E2 SPI1_SCLK

E12 SDRAM_BA0

E3 SPI1_SI

E4 SPI1_SO

E14 V_SS

E13 SDRAM_BA1

F1 SPI2_SCLK

F6 V_SS

F2 SPI2_MO

F7 V_SS

F3 SPI2_MI

F8 V_SS

F4 V_DDD(C)(1V2)

F9 V_SS

F11 V_SS

F12 SDRAM_DIO14 F13 SDRAM_DQM1 F14 V_{DDD(SDRAM)(3V3)}

Row G

G1 SPI2_SS4_N

G6 V_SS

G2 SPI2_SS3_N

G7 V_SS

G3 SPI2_SS2_N

G8 V_SS

G4 SPI2_SS1_N

G9 V_SS

G11 SDRAM_DQM0 G12 V_{DDD(SDRAM)(3V3)}G13 SDRAM_DIO15 G14 SDRAM_DIO11

Row H

H1 UART_CTS

H6 V_SS

H2 UART_RTS

H7 V_SS

H3 UART_RD

H8 V_SS

H4 UART_TD

H9 V_SS

H11 SDRAM_WE_N H12 SDRAM_DIO12 H13 V_SS

H14 SDRAM_DIO13

Row J

J1

J6

V_DDD(C)(1V2)

V_SS

J2

J7

V_DDD(MC)(3V3)

V_SS

J3

J8

V_DDD(MC)(3V3)

V_SS

J4

J9

V_DDD(MC)(3V3)

V_SS

J11 V_SS

J12 SDRAM_DIO10 J13 V_{DDD(SDRAM)(3V3)}J14 V_DDD(C)(1V2)

Row K

K1 SPI3_SS1_N

K11 I2S_I_SD

K2 SPI3_SCLK

K3 SPI3_MOSI

K4 SPI3_MISO

K12 V_{DDD(SDRAM)(3V3)}K13 SDRAM_DIO6

K14 SDRAM_DIO9

SAF3560_SDS

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Product short data sheet

Rev. 5 — 8 February 2013

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SAF3560

NXP Semiconductors

Terrestrial digital radio processor

Table 5.

Pin allocation table (LFBGA170)

Pin Symbol

Row L

Pin Symbol

L1

L5

L9

GPIO0

L2

L6

GPIO1

-

L3

L7

V_DDD(GP)(3V3)

L4

L8

SPI3_SS2_N

BB2_I2S_BCK

[1]

-

BB1_I2S_BCK

BLEND

L10 V_{DDD(DSP)(3V3)}

L14 SDRAM_DIO8

L11 I2S_I_BCK

L12 SDRAM_DIO2

L13 SDRAM_DIO5

Row M

M1 V_DDD(GP)(3V3)

M2 GPIO2

M3 GPIO3

M4 GPIO4

M5

-

M6

-

M7 BB1_I2S_WS

M11 I2S_I_WS

M8 BB2_I2S_WS

M12 SDRAM_DIO1

M9 I2S1_O_WS

M13 V_SS

M10 HBCKOUT

M14 SDRAM_DIO7

Row N

N1

N5

-

N2

N6

-

N3

-

N4

-

N7 BB1_I2S_I

N8 BB2_I2S_I

N12 V_SS

N9 I2S1_O_SD

N10 V_{DDD(MEM)(1V2)}

N11 I2S3_O_SD/

SPDIF_O

N13 SDRAM_DIO4

N14 V_{DDD(SDRAM)(3V3)}

Row P

P3

-

P4

-

P5

-

P6 V_DDD(C)(1V2)

P7 BB1_I2S_Q

P11 I2S2_O_SD

P8 BB2_I2S_Q

P9 I2S1_O_BCK

P13 SDRAM_DIO3

P10 V_{DDD(DSP)(3V3)}

P12 SDRAM_DIO0

[1] See Table 15 for unused pins.

6.2 Pin description

Table 6.

Pin description overview

Pin category

Details

Table number

Table 7

Power supply pins

Baseband interface pins

Generic interface pins

SDRAM interface pins

Serial NOR-Flash interface pins

analog and digital supply pins

baseband and audio pins (I²S-bus)

GPIO and SPI3 pins

Table 8

Table 9

data, address and control pins

SPI2 pins

Table 10

Table 11

Table 12

External host microcontroller

interface pins

SPI1, I2C1, I2C2, UART, CLKOUT

and RESET_N pins

JTAG interface pins

Crystal oscillator pins

JTAG pins

Table 13

Table 14

XTALI and XTALO pins

SAF3560_SDS

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Product short data sheet

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SAF3560

NXP Semiconductors

Terrestrial digital radio processor

Table 7.

Symbol

Pin description (power supplies)

Type^[1]Description

HLQFP144

LFBGA170

Global ground supply

V_SS

130, 137, 144 and B4, B8, B11, C5, C7, C10,

G

analog and digital global ground supply

backside contact

C13, E14, F6 to F9, F11,

G6 to G9, H6 to H9, H13,

J6 to J9, J11, N12 and M13

Analog supplies

V_{DDA(OSC)(1V2)}

V_{DDA(PLL)(1V2)}

Digital supplies

V_DDD(C)(1V2)

140

139

C4

A5

P

oscillator analog supply voltage (1.2 V)

PLL analog supply voltage (1.2 V)

14, 27, 63, 91, 124 A9, B6, F4, J1, J14 and P6

and 134

P

core digital supply voltage (1.2 V)

V_DDD(GP)(3V3)

V_{DDD(DSP)(3V3)}

V_{DDD(JTAG)(3V3)}

V_DDD(MC)(3V3)

34 and 42

64 and 71

138

L3 and M1

P

general purpose digital supply voltage (3.3 V)

DSP digital supply voltage (3.3 V)

L10 and P10

B5

JTAG digital supply voltage (3.3 V)

6, 15, 21 and 28

D4, J2, J3 and J4,

microcontroller digital supply voltage (3.3 V)

SDRAM digital supply voltage (3.3 V)

V_{DDD(SDRAM)(3V3)}80, 85, 90, 96,

A12, B14, C9, D7, D13, F14,

101, 107, 112, 116, G12, J13, K12 and N14,

122 and 129

V_{DDD(MEM)(1V2)}

70, 102 and 143

B3, E11 and N10

P

memory digital supply voltage (1.2 V)

[1] Table 16 defines the pin type.

Table 8.

Symbol

Pin description (baseband interface)

Type^[1]Description

HLQFP144

LFBGA170

Baseband interface

BB1_I2S_BCK

BB1_I2S_I

BB1_I2S_Q

BB1_I2S_WS

BLEND

55

L7

N7

P7

M7

L9

IOZU-H bit clock input and output of first baseband interface

57

58

56

69

IZU-H

I data input line of first baseband interface

Q data input line of first baseband interface

IOZU-H word select input and output line of first baseband interface

OL

blend indicator output,

HIGH = digital audio / LOW = analog radio^[2]

BB2_I2S_BCK

BB2_I2S_I

59

61

62

60

L8

IOZU-H bit clock input and output of second baseband interface

N8

P8

M8

IZU-H

I data input line of second baseband interface

Q data input line of second baseband interface

BB2_I2S_Q

BB2_I2S_WS

Audio interface

HBCKOUT

IOZU-H word select input and output line of second baseband interface

65

75

76

74

73

M10

L11

IOZU

IOZU-H bit clock input and output line of I²S-bus input interface

IZU-H

serial data input line of I²S-bus input interface

IOZU-H word select input and output line of I²S-bus input interface

high-speed bit clock output^[3]

I2S_I_BCK

I2S_I_SD

K11

M11

N11

I2S_I_WS

I2S3_O_SD/

SPDIF_O

OL

serial data output line of third I²S-bus output interface;

in alternative Sony/Philips digital output interface

SAF3560_SDS

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Product short data sheet

Rev. 5 — 8 February 2013

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SAF3560

NXP Semiconductors

Terrestrial digital radio processor

Table 8.

Symbol

Pin description (baseband interface) …continued

Type^[1]Description

HLQFP144

LFBGA170

I2S2_O_SD

I2S1_O_BCK

I2S1_O_SD

I2S1_O_WS

72

66

68

67

P11

P9

OL

IOZU-H bit clock input and output line of first I²S-bus output interface

OL

serial data output line of first I²S-bus output interface

IOZU-H word select input and output line of first I²S-bus output

interface

serial data output line of second I²S-bus output interface

N9

M9

[1] Table 16 defines the pin type.

[2] Required for seamless switching between digital and analog AM/FM modes in HD Radio applications under bad reception conditions.

[3] 256  f_Soutput, required by some external DACs.

Table 9.

Symbol

Pin description (generic tuner interface)

Type^[1]Description

HLQFP144

LFBGA170

GPIO interface

GPIO4

40

39

38

37

36

M4

M3

M2

L2

IOZU

general-purpose input and output port 4

general-purpose input and output port 3

general-purpose input and output port 2

general-purpose input and output port 1

general-purpose input and output port 0

GPIO3

GPIO2

GPIO1

GPIO0

L1

SPI3 interface

SPI3_MISO

SPI3_MOSI

SPI3_SCLK

SPI3_SS1_N

30

31

32

33

K4

K3

K2

K1

IOZU-H master input, slave output of third SPI interface

IOZU-H master output, slave input of third SPI interface

IOZU-H serial clock input and output of third SPI interface

IOZU-H slave select 1 input and output of third SPI interface

(active LOW)

SPI3_SS2_N

35

L4

OZU

slave select 2 output of third SPI interface (active LOW)

[1] Table 16 defines the pin type.

Table 10. Pin description (SDRAM interface)

Symbol

Type^[1]Description

HLQFP144

LFBGA170

Data input and output interface

SDRAM_DIO15

SDRAM_DIO14

SDRAM_DIO13

SDRAM_DIO12

SDRAM_DIO11

SDRAM_DIO10

SDRAM_DIO9

SDRAM_DIO8

SDRAM_DIO7

97

95

94

93

92

89

88

87

86

G13

F12

H14

H12

G14

J12

IOL

data input and output bit 15

data input and output bit 14

data input and output bit 13

data input and output bit 12

data input and output bit 11

data input and output bit 10

data input and output bit 9

data input and output bit 8

data input and output bit 7

K14

L14

M14

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Table 10. Pin description (SDRAM interface) …continued

Symbol

Type^[1]Description

HLQFP144

LFBGA170

K13

SDRAM_DIO6

SDRAM_DIO5

SDRAM_DIO4

SDRAM_DIO3

SDRAM_DIO2

SDRAM_DIO1

SDRAM_DIO0

84

83

82

81

79

78

77

IOL

data input and output bit 6

data input and output bit 5

L13

N13

data input and output bit 4

data input and output bit 3

data input and output bit 2

data input and output bit 1

data input and output bit 0

P13

L12

M12

P12

Address output interface

SDRAM_AO12

SDRAM_AO11

SDRAM_AO10

SDRAM_AO9

SDRAM_AO8

SDRAM_AO7

SDRAM_AO6

SDRAM_AO5

SDRAM_AO4

SDRAM_AO3

SDRAM_AO2

SDRAM_AO1

SDRAM_AO0

Control interface

SDRAM_BA1

SDRAM_BA0

126

125

123

121

120

119

118

117

115

114

113

111

110

C8

OZU

address output bit 12

address output bit 11

address output bit 10

address output bit 9

address output bit 8

address output bit 7

address output bit 6

address output bit 5

address output bit 4

address output bit 3

address output bit 2

address output bit 1

address output bit 0

D8

B9

D9

A10

B10

D10

A11

A13

B12

B13

C11

C12

104

103

E13

E12

D14

A8

OZU

IZU

bit 1 of bank address output

bit 0 of bank address output

SDRAM_CAS_N 108

column address selector output (active LOW)

clock output

SDRAM_CLK

127

109

128

105

100

99

SDRAM_CLKE

SDRAM_CLKIN

SDRAM_CS_N

SDRAM_DQM1

SDRAM_DQM0

C14

A7

clock enable output

clock input for resynchronization

chip select output (active LOW)

MSByte of data qualifier mask output

LSByte of data qualifier mask output

row address selector output (active LOW)

write enable output (active LOW)

D11

F13

G11

D12

H11

OZU

OL

SDRAM_RAS_N 106

SDRAM_WE_N 98

OZU

[1] Table 16 defines the pin type.

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Table 11. Pin description (serial NOR-Flash interface)

Symbol

Type^[1]Description

HLQFP144

LFBGA170

SPI2 interface

SPI2_MI

16

17

18

19

20

22

23

F3

F2

F1

G4

G3

G2

G1

IZU

master input of second SPI interface

master output of second SPI interface

SPI2_MO

OZD

OZU

SPI2_SCLK

SPI2_SS1_N

SPI2_SS2_N

SPI2_SS3_N

SPI2_SS4_N

serial clock output of second SPI interface

slave select 1 output of second SPI interface (active LOW)

slave select 2 output of second SPI interface (active LOW)

slave select 3 output of second SPI interface (active LOW)

slave select 4 output of second SPI interface (active LOW)

[1] Table 16 defines the pin type.

Table 12. Pin description (external host microcontroller interface)

Symbol

Type^[1]Description

HLQFP144

LFBGA170

CLKOUT

1

B2

OL

clock output; clock source and clock frequency are

programmable through software

RESET_N

2

B1

IZU-H

master reset input from host microcontroller (active LOW)

I²C-bus interface (master and slave)

I2C2_DA

9

7

8

5

3

4

D1

D3

D2

C1

C3

C2

IOZD-H data acknowledge input and output of the I²C-bus interface 2

I2C2_SCL

I2C2_SDA

I2C1_DA

IOZU

serial clock input and output of the I²C-bus interface 2

serial data input and output of the I²C-bus interface 2

IOZU

IOZD-H data acknowledge input and output of the I²C-bus interface 1

IOZU

serial clock input and output of the I²C-bus interface 1

IOZU-H serial data input and output of the I²C-bus interface 1

I2C1_SCL

I2C1_SDA

SPI1 interface

SPI1_SCLK

SPI1_SI

12

11

10

13

E2

E3

E4

E1

IZU-H

OL

serial clock input of first SPI interface

slave input of first SPI interface

SPI1_SO

slave output of first SPI interface

SPI1_SS_N

UART interface

UART_CTS

UART_RD

UART_RTS

UART_TD

IZU-H

slave select input of first SPI interface (active LOW)

29

25

26

24

H1

H3

H2

H4

IZU

OH

UART clear-to-send signal input

UART receive data input

UART ready-to-send signal output

UART transmit data output

[1] Table 16 defines the pin type.

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Table 13. Pin description (JTAG interface)

Symbol

Type^[1]Description

HLQFP144

132

LFBGA170

TCK

D6

A6

D5

C6

B7

IZU

OL

test clock input

TDI

135

test serial data input

test serial data output

test mode select input

TDO

136

TMS

133

IZU

TRST_N

131

test reset input; drive LOW for normal operating

[1] Table 16 defines the pin type.

Table 14. Pin description (crystal oscillator)

Symbol

Type^[1]Description

HLQFP144

141

LFBGA170

XTALI

A3

A4

AI

crystal oscillator analog input

crystal oscillator analog output

XTALO

142

AO

[1] Table 16 defines the pin type.

Table 15. Pin description (internally connected pins)

Symbol

Type

Description

HLQFP144

LFBGA170

i.c.

41,

43 to 54

L5, L6, M5, M6, N1 to N6,

P3 to P5

-

internally connected; leave open

Table 16. Pin type description

Type Description

Generic pin types

Unused pins^[1]

AI

analog input pin

always connect to quartz crystal

AO

G

analog output pin

ground pin

always connect to quartz crystal

use all ground pins

IOL

IOZD

IOZU

IZU

OH

OL

digital input and output; drives LOW after reset

can be left open

digital input and output pin with weak pull-down can be left open

digital input and output pin with weak pull-up

digital input pin with weak pull-up

digital output; drives HIGH after reset

digital output; drives LOW after reset

digital output pin with weak pull-down

digital output pin with weak pull-up

power supply pin

can be left open

use all power supply pins

OZD

OZU

P

Specific pin types

-H pins with hysteresis

see generic types

[1] Applications, which do not need all pins from SAF3560, can treat unused pins as indicated without damage

or malfunction of the device.

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7. Limiting values

Table 17. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

0.5

40

65

-

Max

+1.7

+3.9

+1.7

+85

Unit

V

V_{DDA(OSC)(1V2)}

V_{DDA(PLL)(1V2)}

V_DDD(C)(1V2)

V_DDD(GP)(3V3)

V_{DDD(DSP)(3V3)}

V_{DDD(JTAG)(3V3)}

V_DDD(MC)(3V3)

oscillator analog supply voltage (1.2 V)

PLL analog supply voltage (1.2 V)

core digital supply voltage (1.2 V)

general purpose digital supply voltage (3.3 V)

DSP digital supply voltage (3.3 V)

JTAG digital supply voltage (3.3 V)

microcontroller digital supply voltage (3.3 V)

V

V_{DDD(SDRAM)(3V3)}SDRAM digital supply voltage (3.3 V)

V

V_{DDD(MEM)(1V2)}

T_amb

memory digital supply voltage (1.2 V)

ambient temperature

V

C

V

T_stg

storage temperature

+150

2000

[1]

[2]

V_ESD

electrostatic discharge voltage

human body model

charged device model

corner pins

-

750

500

+100

V

other pins

-

V

[2]

I_lu

latch-up current

all supply voltages

below the maximum

values listed in this

table

100

mA

[1] Class 2 according to JEDEC JESD22-A114.

[2] According to AEC-Q100-G.

8. Thermal characteristics

The SAF3560 has no special thermal requirements. The backside contact of the

HLQFP144 package is needed for electrical reasons. For soldering considerations, see

Section 10.

Table 18. Thermal characteristics

Symbol

Parameter

Conditions

Typ

Unit

R_th(j-a)

thermal resistance from junction to ambient

in free air

[1][2]

[1]

HLQFP144

26.3

30

K/W

LBGA170 four-layer board

[1] The overall R_th(j-a)is based on JEDEC conditions and can vary depending on the board layout. To minimize the effective R_th(j-a), all

power and ground pins must be connected to the power and ground layers directly. An ample amount of copper area directly under the

SAF3560 with a number of through-hole plating, which connect to the ground layer (four-layer board: second layer), can also reduce the

effective R_th(j-a). In addition, the use of soldering glue with a high thermal conductance after curing is recommended.

[2] Do not use any solder-stop varnish under the chip.

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9. Package outline

HLQFP144: plastic thermal enhanced low profile quad flat package; 144 leads;

body 20 x 20 x 1.4 mm; exposed die pad

SOT612-4

c

y

exposed die pad

X

D

h

A

108

109

73

72

Z

E

e

A

2

E

H

E

A

E

(A )

3

h

A

1

θ

M

w

L

p

b

p

detail X

pin 1 index

L

144

37

1

36

M

v

A

Z

M

w

D

e

b

p

D

B

H

D

M

v

B

0

5

10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

2

A

3

b

c

D

h

E

e

H

D

H

E

L

v

w

y

Z

E

θ

1

p

h

p

D

max

°

0.12 1.45

0.05 1.35

0.27 0.20 20.1 4.3 20.1 4.3

0.17 0.09 19.9 4.1 4.1

22.15 22.15

21.85

0.75

0.45

1.4

1.1

1.4

1.1

7

0

mm

1.6

0.25

0.5

1

0.2 0.08 0.08

19.9

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

JEDEC JEITA

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

07-12-11

08-01-18

SOT612-4

MS-026

Fig 5. Package outline SOT612-4 (HLQFP144)

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LFBGA170: plastic low profile fine-pitch ball grid array package; 170 balls

SOT1315-1

D

B

A

ball A1

index area

A

2

A

1

E

detail X

C

e

1

y

C

1

Ø v

C

A

B

e

1/2 e

Ø w

P

N

M

L

e

K

J

H

G

F

E

D

C

B

A

e

2

1/2 e

ball A1

index area

1

2 3 4 5 6 7 8 9 10 11 12 13 14

X

0

10 mm

scale

Dimensions (mm are the original dimensions)

Unit

A

1

A

2

b

D

E

e

1

e

2

v

w

y

1

max 1.50 0.40 1.10 0.50 12.1 12.1

mm nom 1.35 0.35 1.00 0.45 12.0 12.0 0.80 10.4 10.4 0.15 0.08 0.12 0.10

min

1.25 0.30 0.95 0.40 11.9 11.9

sot1315-1_po

References

Outline

version

European

projection

Issue date

IEC

JEDEC

MO-205

JEITA

11-09-05

11-11-01

SOT1315-1

Fig 6. Package outline SOT1315-1 (LFBGA170)

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10. Soldering

Footprint information for reflow soldering of HLQFP144 package

SOT612-4

Hx

Gx

(0.125)

P2

P1

SPx

nSPx

SPy

SLy

Hy Gy

By

Ay

nSPy

SPx tot

SLx

C

D2 (8×)

D1

Bx

Ax

Generic footprint pattern

Refer to the package outline drawing for actual layout

solder land

solder paste

nSPx nSPy

occupied area

4

DIMENSIONS in mm

P1 P2 Ax

Ay

Bx

By

C

D1

D2

Gx

Gy

Hx

Hy

SLx SLy SPx tot SPy tot SPx SPy

0.500 0.560 23.300 23.300 20.300 20.300 1.500 0.280 0.400 20.500 20.500 23.550 23.550 4.500 4.500 4.400

4.400 0.750 0.750

Fig 7. Soldering footprint SOT612-4 (HLQFP144)

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Footprint information for reflow soldering of HLQFP144 package

SOT612-4

Hx

Gx

(0.125)

P2

P1

SPx

nSPx

SPy

SLy

Hy Gy

By

Ay

nSPy

SPx tot

SLx

C

D2 (8×)

D1

Bx

Ax

Generic footprint pattern

Refer to the package outline drawing for actual layout

solder land

solder paste

nSPx nSPy

occupied area

4

DIMENSIONS in mm

P1 P2 Ax

Ay

Bx

By

C

D1

D2

Gx

Gy

Hx

Hy

SLx SLy SPx tot SPy tot SPx SPy

0.500 0.560 23.300 23.300 20.300 20.300 1.500 0.280 0.400 20.500 20.500 23.550 23.550 4.500 4.500 4.400

4.400 0.750 0.750

Fig 8. Soldering footprint SOT1315-1 (LFBGA170)

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11. Abbreviations

Table 19. Abbreviations

Acronym

AEC

AM

Description

Automotive Electronics Council

Amplitude Modulation

BaseBand Interface

Bit Clock

BBI

BCK

CA

Conditional Access

Compact Disc

CD

CGU

CTS

DAC

DSP

EPG

FM

Clock Generation Unit

Clear To Send

Digital-to-Analog Converter

Digital Signal Processor

Electronic Program Guide

Frequency Modulation

General Purpose

GP

GPIO

HPPI

HPSI

IC

General-Purpose Input and Output

Host Processor Primary Interface

Host Processor Secondary Interface

Integrated Circuit

IF

Intermediate Frequency

Inter-IC bus

I²C-bus

I²S

Inter-IC Sound

I/O

Input/Output

JEDEC

JTAG

MUX

PCB

PLL

Joint Electronic Device Engineering Council

Joint Test Action Group

MUltipleXer

Printed-Circuit Board

Phase-Locked Loop

PROM

RAM

ROM

RS232

RTS

RXD

SD

Programmable ROM

Random Access Memory

Read-Only Memory

Recommended Standard 232^[1]

Ready To Send

Receive Data^[2]

Secure Digital memory card

Single Data Rate

SDR

SDRAM

SPI

Synchronous Dynamic RAM

Serial Peripheral Interface

Sony/Philips Digital InterFace

Sample-Rate Converter

S/PDIF

SRC

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Table 19. Abbreviations …continued

Acronym

Description

TXD

UART

WS

Transmit Data^[2]

Universal Asynchronous Receiver Transmitter

Word Select

[1] A serial interface.

[2] In this context, the X has no specific meaning.

12. Revision history

Table 20. Revision history

Document ID

Release date

20130208

Data sheet status

Change notice

Supersedes

SAF3560_SDS v.5

Modifications:

Product short data sheet

-

SAF3560_SDS v.4

• New package added (SOT1315-AA1)

• Order pin list SAF3560EL

SAF3560_SDS v.4

Modifications:

20111129

Product short data sheet

-

SAF3560_SDS v.3

• Two new types added (V1104/V1105)

• Minor text changes

SAF3560_SDS v.3

Modifications:

20100915

Product short data sheet

SAF3560_SDS v.2

• The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

• Legal texts have been adapted where appropriate.

• Minor text changes

SAF3560_SDS v.2

20100503

Product short data sheet

-

SAF3560_SDS

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13. Legal information

13.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use in automotive applications — This NXP

13.2 Definitions

Semiconductors product has been qualified for use in automotive

applications. Unless otherwise agreed in writing, the product is not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer's own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

13.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

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No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

13.4 Licenses

ICs with HD Radio functionality

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

NXP Semiconductors ICs with HD Radio functionality are manufactured

under license from iBiquity Digital Corporation. Sale or distribution of

equipment that includes this device requires a license, which may be

obtained at: iBiquity Digital Corporation, 6711 Columbia Gateway Drive,

Suite 500, Columbia MD 21046, USA. Telephone: +1 (443) 539 4290, fax:

+1 (443) 539 4291, e-mail: info@ibiquity.com.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

13.5 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

I²C-bus — logo is a trademark of NXP B.V.

HD Radio — is a trademark of iBiquity Digital Corporation.

HD Radio — logo is a registered trademark of iBiquity Digital Corporation.

14. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

SAF3560_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 5 — 8 February 2013

23 of 24

SAF3560

NXP Semiconductors

Terrestrial digital radio processor

15. Contents

1

General description. . . . . . . . . . . . . . . . . . . . . . 1

2

Features and benefits . . . . . . . . . . . . . . . . . . . . 2

HD Radio technology . . . . . . . . . . . . . . . . . . . . 2

Digital audio . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Other peripheral interfaces. . . . . . . . . . . . . . . . 3

Miscellaneous. . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.1

2.2

2.3

2.4

2.5

3

4

5

Quick reference data . . . . . . . . . . . . . . . . . . . . . 3

Ordering information. . . . . . . . . . . . . . . . . . . . . 4

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 6

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 9

7

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 15

Thermal characteristics . . . . . . . . . . . . . . . . . 15

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 20

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 21

8

9

10

11

12

13

Legal information. . . . . . . . . . . . . . . . . . . . . . . 22

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 22

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 23

13.1

13.2

13.3

13.4

13.5

14

15

Contact information. . . . . . . . . . . . . . . . . . . . . 23

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 8 February 2013

Document identifier: SAF3560_SDS


型号：	SAF3560EL/V1102
厂家：	NXP
描述：	IC SPECIALTY CONSUMER CIRCUIT, Consumer IC:Other 商用集成电路
文件：	总24页 (文件大小：320K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SAF3560EL/V1102 [NXP]

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