SC16C2552BIA44_技术文档

SC16C2552B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte

FIFOs

Rev. 03 — 12 February 2009

Product data sheet

1. General description

The SC16C2552B is a two channel Universal Asynchronous Receiver and Transmitter

(UART) used for serial data communications. Its principal function is to convert parallel

data into serial data, and vice versa. The UART can handle serial data rates up to

5 Mbit/s.

The SC16C2552B is pin compatible with the PC16552 and ST16C2552. The

SC16C2552B provides enhanced UART functions with 16-byte FIFOs, modem control

interface, DMA mode data transfer and concurrent writes to control registers of both

channels. The DMA mode data transfer is controlled by the FIFO trigger levels and the

RXRDY and TXRDY signals. On-board status registers provide the user with error

indications and operational status. System interrupts and modem control features may be

tailored by software to meet speciﬁc user requirements. An internal loopback capability

allows on-board diagnostics. Independent programmable baud rate generators are

provided to select transmit and receive baud rates.

The SC16C2552B operates at 5 V, 3.3 V and 2.5 V and the industrial temperature range,

and is available in a plastic PLCC44 package.

2. Features

I Industrial temperature range (−40 °C to +85 °C)

I 5 V, 3.3 V and 2.5 V operation

I Pin-to-pin compatible to PC16C552, ST16C2552

I Up to 5 Mbit/s data rate at 5 V and 3.3 V, and 3 Mbit/s at 2.5 V

I 5 V tolerant on input only pins¹

I 16-byte transmit FIFO

I 16-byte receive FIFO with error ﬂags

I Independent transmit and receive UART control

I Four selectable receive FIFO interrupt trigger levels; ﬁxed transmit FIFO interrupt

trigger level

I Modem control functions (CTS, RTS, DSR, DTR, RI, CD)

I DMA operation and DMA monitoring via package I/O pins, TXRDY/RXRDY

I UART internal register sections A and B may be written to concurrently

I Multi-function output allows more package functions with fewer I/O pins

I Programmable character lengths (5, 6, 7, 8), with even, odd, or no parity

1. For data bus pins D7 to D0, see Table 23 “Limiting values”.

SC16C2552B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

3. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

SC16C2552BIA44

PLCC44

plastic leaded chip carrier; 44 leads

SOT187-2

4. Block diagram

SC16C2552B

TRANSMIT

FIFO

TRANSMIT

SHIFT

TXA, TXB

REGISTERS

REGISTER

D0 to D7

IOR

IOW

RESET

DATA BUS

AND

CONTROL

LOGIC

RECEIVE

FIFO

RECEIVE

SHIFT

RXA, RXB

REGISTERS

REGISTER

A0 to A2

CS

CHSEL

REGISTER

SELECT

LOGIC

DTRA, DTRB

RTSA, RTSB

MFA, MFB

MODEM

CONTROL

LOGIC

CTSA, CTSB

RIA, RIB

CDA, CDB

DSRA, DSRB

INTA, INTB

TXRDYA, TXRDYB

RXRDYA, RXRDYB

CLOCK AND

BAUD RATE

GENERATOR

INTERRUPT

CONTROL

LOGIC

002aaa487

XTAL1

XTAL2

Fig 1. Block diagram of SC16C2552B

SC16C2552B_3

Product data sheet

Rev. 03 — 12 February 2009

2 of 38

SC16C2552B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

5. Pinning information

5.1 Pinning

7

39

38

37

36

35

34

33

32

31

30

29

D5

D6

RXA

8

TXA

9

D7

DTRA

RTSA

MFA

INTA

10

11

12

13

14

15

16

17

A0

XTAL1

GND

XTAL2

A1

SC16C2552BIA44

V

CC

TXRDYB

RIB

A2

CHSEL

INTB

CDB

DSRB

002aaa488

Fig 2. Pin conﬁguration for PLCC44

5.2 Pin description

Table 2.

Symbol

A0

Pin description

10

14

15

42

30

Type

Description

I

Register select. A0 to A2 are used during read and write operations to select the UART

register to read from or write to.

A1

A2

CDA

CDB

Carrier detect A, B (active LOW). These inputs are associated with individual UART

channels A through B. A logic 0 on this pin indicates that a carrier has been detected by the

modem for that channel.

CHSEL

16

I

Channel select. UART channel A or B is selected by the logic state of this pin when CS is a

logic 0. A logic 0 on CHSEL selects the UART channel B, while a logic 1 selects UART

channel A. Bit 0 of AFR register can temporarily override CHSEL function, allowing user to

write to both channel registers simultaneously with one write cycle.

CTSA

CTSB

40

28

I

Clear to Send A, B (active LOW). These inputs are associated with individual UART

channels A through B. A logic 0 on the CTSn pin indicates the modem or data set is ready to

accept transmit data from the SC16C2552B. Status can be tested by reading MSR[4].

CS

18

I

Chip select (active LOW). This function selects channel A or channel B in accordance with

the logical state of the CHSEL pin. This allows data to be transferred between the user CPU

and the SC16C2552B.

SC16C2552B_3

Product data sheet

Rev. 03 — 12 February 2009

3 of 38

SC16C2552B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

Table 2.

Symbol

D0

Pin description …continued

2

Type

I/O

I

Description

Data bus (bidirectional). These pins are the 8-bit, 3-state data bus for transferring

information to or from the controlling CPU.

D1

3

D2

4

D3

5

D4

6

D5

7

D6

8

D7

9

DSRA

DSRB

41

29

Data Set Ready A, B (active LOW). These inputs are associated with individual UART

channels A through B. A logic 0 on this pin indicates the modem or data set is powered-on

and is ready for data exchange with the UART.

I

DTRA

DTRB

37

27

O

Data Terminal Ready A, B (active LOW). These outputs are associated with individual

UART channels A through B. A logic 0 on this pin indicates that the SC16C2552B is

powered-on and ready. This pin can be controlled via the modem control register. Writing a

logic 1 to MCR[0] will set the DTRn output to logic 0, enabling the modem. This pin will be a

logic 1 after writing a logic 0 to MCR[0], or after a reset.

GND

INTA

INTB

12, 22

34

I

Signal and power ground.

O

Interrupt A, B (active HIGH). This function is associated with individual channel interrupts.

Interrupts are enabled in the Interrupt Enable Register (IER). Interrupt conditions include:

receiver errors, available receiver buffer data, transmit buffer empty, or when a modem

status ﬂag is detected.

17

IOR

24

20

I

Read strobe (active LOW). A logic 0 transition on this pin will load the contents of an

internal register deﬁned by address bits A[2:0] onto the SC16C2552B data bus (D[7:0]) for

access by external CPU.

IOW

Write strobe (active LOW). A logic 0 transition on this pin will transfer the contents of the

data bus (D[7:0]) from the external CPU to an internal register that is deﬁned by address bits

A[2:0].

MFA

MFB

35

19

O

Multi-function A, B. This function is associated with an individual channel function, A or B.

User programmable bits 2:1 of the Alternate Function Register (AFR) selects a signal

function or output on these pins. OP2 (interrupt enable), BAUDOUT, and RXRDY are signal

functions that may be selected by the AFR. These signal functions are described as follows:

OP2. When OP2 is selected, the MFn pin is a logic 0 when MCR[3] is set to a logic 1.

A logic 1 is the default signal condition that is available following a master reset or

power-up.

BAUDOUT. When BAUDOUT function is selected, the 16× baud rate clock output is

available at this pin.

RXRDY. RXRDY is primarily intended for monitoring DMA mode 1 transfers for the receive

data FIFOs. A logic 0 indicates there is receive data to read/unload, i.e., receive ready

status with one or more RX characters available in the FIFO/RHR. This pin is a logic 1

when the FIFO/RHR is empty or when the programmed trigger level has not been

reached. This signal can also be used for single mode transfers (DMA mode 0).

RESET

21

I

Reset (active HIGH). A logic 1 on this pin will reset the internal registers and all the outputs.

The UART transmitter output and the receiver input will be disabled during reset time. See

Section 7.11 “SC16C2552B external reset condition” for initialization details.

RIA

RIB

43

31

I

Ring Indicator A, B (active LOW). These inputs are associated with individual UART

channels A through B. A logic 0 on this pin indicates the modem has received a ringing

signal from the telephone line. A logic 1 transition on this input pin will generate an interrupt

if modem status interrupt is enabled.

SC16C2552B_3

Product data sheet

Rev. 03 — 12 February 2009

4 of 38

SC16C2552B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

Table 2.

Symbol

RTSA

Pin description …continued

36

Type

O

Description

Request to Send A, B (active LOW). These outputs are associated with individual UART

channels A through B. A logic 0 on the RTSn pin indicates the transmitter is ready to

transmit data. Writing a logic 1 in the modem control register MCR[1] will set this pin to a

logic 0, indicating that the transmitter is ready to transmit data. After a reset, this pin will be

set to a logic 1.

RTSB

23

O

RXA

RXB

39

25

I

Receive data A, B. These inputs are associated with individual serial channel data to the

SC16C2552B receive input circuits A through B. The RXn signal will be a logic 1 during

reset, idle (no data). During the local Loopback mode, the RXn input pin is disabled and TXn

data is connected to the UART RXn input, internally.

TXA

TXB

38

26

O

Transmit data A, B. These outputs are associated with individual serial transmit channel

data from the SC16C2552B. The TXn signal will be a logic 1 during reset, idle (no data), or

when the transmitter is disabled. During the local Loopback mode, the TXn output pin is

disabled and TXn data is internally connected to the UART RXn input.

TXRDYA

TXRDYB

1

O

Transmit Ready A, B (active LOW). These outputs provide the TX FIFO/THR status for

individual transmit channels (A, B). TXRDYn is primarily intended for monitoring

DMA mode 1 transfers for the transmit data FIFOs. An individual channel’s TXRDYA,

TXRDYB buffer ready status is indicated by logic 0, i.e., at least one location is empty and

available in the FIFO or THR. This signal can also be used for single mode transfers (DMA

mode 0).

32

V_CC

33, 44

11

I

Power supply input.

XTAL1

Crystal or external clock input. Functions as a crystal input or as an external clock input.

A crystal can be connected between this pin and XTAL2 to form an internal oscillator circuit.

Alternatively, an external clock can be connected to this pin to provide custom data rates.

See Section 6.5 “Programmable baud rate generator”.

XTAL2

13

O

Output of the crystal oscillator or buffered clock. (See also XTAL1.) Crystal oscillator

output or buffered clock output. Should be left open if an external clock is connected to

XTAL1.

SC16C2552B_3

Product data sheet

Rev. 03 — 12 February 2009

5 of 38

SC16C2552B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

6. Functional description

The SC16C2552B provides serial asynchronous receive data synchronization,

parallel-to-serial and serial-to-parallel data conversions for both the transmitter and

receiver sections. These functions are necessary for converting the serial data stream into

parallel data that is required with digital data systems. Synchronization for the serial data

stream is accomplished by adding start and stop bits to the transmit data to form a data

character. Data integrity is ensured by attaching a parity bit to the data character. The

parity bit is checked by the receiver for any transmission bit errors. The SC16C2552B is

fabricated with an advanced CMOS process.

The SC16C2552B is an upward solution that provides a dual UART capability with

16 bytes of transmit and receive FIFO memory, instead of none in the 16C450. The

SC16C2552B is designed to work with high speed modems and shared network

environments that require fast data processing time. Increased performance is realized in

the SC16C2552B by the transmit and receive FIFOs. This allows the external processor to

handle more networking tasks within a given time. In addition, the four selectable receive

FIFO trigger interrupt levels are uniquely provided for maximum data throughput

performance, especially when operating in a multi-channel environment. The FIFO

memory greatly reduces the bandwidth requirement of the external controlling CPU,

increases performance, and reduces power consumption.

The SC16C2552B is capable of operation up to 1.5 Mbit/s with a 24 MHz crystal. With a

crystal or external clock input of 7.3728 MHz, the user can select data rates up to

460.8 kbit/s.

The rich feature set of the SC16C2552B is available through internal registers. Selectable

receive FIFO trigger levels, selectable TX and RX baud rates, and modem interface

controls are all standard features.

6.1 UART A-B functions

The UART provides the user with the capability to bidirectionally transfer information

between an external CPU, the SC16C2552B package, and an external serial device. A

logic 0 on chip select pin CS and a logic 1 on CHSEL allows the user to conﬁgure, send

data, and/or receive data via UART channel A. A logic 0 on chip select pin CS and a

logic 0 on CHSEL allows the user to conﬁgure, send data, and/or receive data via UART

channel B. Individual channel select functions are shown in Table 3.

Table 3.

Chip select

CS = 1

Serial port selection

UART select

none

CS = 0

UART channel selected as follows:

CHSEL = 1: UART channel A

CHSEL = 0: UART channel B

During a write mode cycle, the setting of AFR[0] to a logic 1 will override the CHSEL

selection and allow a simultaneous write to both UART channel sections. This functional

capability allows the registers in both UART channels to be modiﬁed concurrently, saving

individual channel initialization time. Caution should be considered, however, when using

this capability. Any in-process serial data transfer may be disrupted by changing an active

channel’s mode.

SC16C2552B_3

Product data sheet

Rev. 03 — 12 February 2009

6 of 38

SC16C2552B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

6.2 Internal registers

The SC16C2552B provides two sets of internal registers (A and B) consisting of

13 registers each for monitoring and controlling the functions of each channel of the

UART. These registers are shown in Table 4. The UART registers function as data holding

registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control

register (FCR), line status and control registers (LCR/LSR), modem status and control

registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM), a

user accessible scratchpad register (SPR), and an Alternate Function Register (AFR).

Table 4.

A2

Internal registers decoding

A0 Read mode

A1

Write mode

General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LCR/LSR, SPR)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Receive Holding Register

Interrupt Enable Register

Interrupt Status Register

Line Control Register

Modem Control Register

Line Status Register

Transmit Holding Register

Interrupt Enable Register

FIFO Control Register

Line Control Register

Modem Control Register

n/a

Modem Status Register

n/a

Scratchpad Register

Baud rate register set (DLL/DLM, AFR)^[1]

0

1

0

1

0

LSB of Divisor Latch

MSB of Divisor Latch

Alternate Function Register

MSB of Divisor Latch

Alternate Function Register

[1] The baud rate register and AFR register sets are accessible only when CS is a logic 0 and LCR[7] is a

logic 1 for the register set (A/B) being accessed.

6.3 FIFO operation

The 16 byte transmit and receive data FIFOs are enabled by the FIFO Control Register

(FCR) bit 0. The user can set the receive trigger level via FCR[7:6], but not the transmit

trigger level. The receiver FIFO section includes a time-out function to ensure data is

delivered to the external CPU. A time-out interrupt is generated whenever the Receive

Holding Register (RHR) has not been read following the loading of a character, or the

receive trigger interrupt is generated when RX FIFO level is equal to the program RX

trigger value.

6.4 Time-out interrupts

The interrupts are enabled by IER[3:0]. Care must be taken when handling these

interrupts. Following a reset, if the transmitter interrupt is enabled, the SC16C2552B will

issue an interrupt to indicate that the Transmit Holding Register is empty. The ISR register

provides the current singular highest priority interrupt only. A condition can exist where a

higher priority interrupt may mask the lower priority interrupt(s). Only after servicing the

higher pending interrupt will the lower priority interrupt(s) be reﬂected in the status

register. Servicing the interrupt without investigating further interrupt conditions can result

in data errors.

SC16C2552B_3

Product data sheet

Rev. 03 — 12 February 2009

7 of 38

SC16C2552B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

When two interrupt conditions have the same priority, it is important to service these

interrupts correctly. Receive Data Ready and Receive Time-Out have the same interrupt

priority (when enabled by IER[0]). The receiver issues an interrupt after the number of

characters have reached the programmed trigger level. In this case, the SC16C2552B

FIFO may hold more characters than the programmed trigger level. Following the removal

of a data byte, the user should re-check LSR[0] for additional characters. A Receive

Time-Out will not occur if the receive FIFO is empty. The time-out counter is reset at the

center of each stop bit received or each time the receive holding register (RHR) is read.

The actual time-out value is 4 character time.

6.5 Programmable baud rate generator

The SC16C2552B supports high speed modem technologies that have increased input

data rates by employing data compression schemes. For example, a 33.6 kbit/s modem

that employs data compression may require a 115.2 kbit/s input data rate. A 128.0 kbit/s

ISDN modem that supports data compression may need an input data rate of 460.8 kbit/s.

A baud rate generator is provided for each UART channel, allowing independent TX/RX

channel control. The programmable Baud Rate Generator (BRG) is capable of accepting

an input clock up to 80 MHz, as required for supporting a 5 Mbit/s data rate. The

SC16C2552B can be conﬁgured for internal or external clock operation. For internal clock

oscillator operation, an industry standard microprocessor crystal is connected externally

between the XTAL1 and XTAL2 pins. Alternatively, an external clock can be connected to

the XTAL1 pin to clock the internal baud rate generator for standard or custom rates (see

Table 5).

The generator divides the input 16× clock by any divisor from 1 to (2¹⁶− 1). The

SC16C2552B divides the basic external clock by 16. The basic 16× clock provides table

rates to support standard and custom applications using the same system design. The

rate table is conﬁgured via the DLL and DLM internal register functions. Customized baud

rates can be achieved by selecting the proper divisor values for the MSB and LSB

sections of baud rate generator.

Programming the baud rate generator registers DLM (MSB) and DLL (LSB) provides a

user capability for selecting the desired ﬁnal baud rate. The example in Table 5 shows the

selectable baud rate table available when using a 1.8432 MHz external clock input.

XTAL1

XTAL2

X1

1.8432 MHz

C1

22 pF

C2

33 pF

002aab325

Fig 3. Crystal oscillator connection

SC16C2552B_3

Product data sheet

Rev. 03 — 12 February 2009

8 of 38

SC16C2552B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

Table 5.

Baud rate generator programming table using a 1.8432 MHz clock

Output

DLM

DLL

baud rate

16× clock divisor

(decimal)

16× clock divisor

(HEX)

program value

(HEX)

program value

(HEX)

50

2304

1536

768

384

192

96

900

600

300

180

C0

60

09

06

03

01

00

80

C0

60

30

18

10

0C

06

03

02

01

75

150

300

600

1200

2400

4800

7200

9600

19.2 k

38.4 k

57.6 k

115.2 k

48

30

24

18

16

10

12

0C

06

6

3

03

2

02

1

01

6.6 DMA operation

The SC16C2552B FIFO trigger level provides additional ﬂexibility to the user for block

mode operation. LSR[6:5] provide an indication when the transmitter is empty or has an

empty location(s). The user can optionally operate the transmit and receive FIFOs in the

DMA mode (FCR[3]). When the transmit and receive FIFOs are enabled and the DMA

mode is de-activated (DMA Mode 0), the SC16C2552B activates the interrupt output pin

for each data transmit or receive operation. When DMA mode is activated (DMA Mode 1),

the user takes the advantage of block mode operation by loading or unloading the FIFO in

a block sequence determined by the receive trigger level and the transmit FIFO. In this

mode, the SC16C2552B sets the interrupt output pin when characters in the transmit

FIFO is below 16, or the characters in the receive FIFOs are above the receive trigger

level.

6.7 Loopback mode

The internal loopback capability allows on-board diagnostics. In the Loopback mode, the

normal modem interface pins are disconnected and reconﬁgured for loopback internally.

MCR[3:0] register bits are used for controlling loopback diagnostic testing. In the

Loopback mode, INT enable and MCR[2] in the MCR register (bits 3:2) control the modem

RI and CD inputs, respectively. MCR signals DTR (bit 0) and RTS (bit 1) are used to

control the modem DSR and CTS inputs, respectively. The transmitter output (TX) and the

receiver input (RX) are disconnected from their associated interface pins, and instead are

connected together internally (see Figure 4). The CTS, DSR, CD, and RI are

disconnected from their normal modem control inputs pins, and instead are connected

internally to RTS, DTR, OP2 and OP1. Loopback test data is entered into the transmit

holding register via the user data bus interface, D0 to D7. The transmit UART serializes

the data and passes the serial data to the receive UART via the internal loopback

connection. The receive UART converts the serial data back into parallel data that is then

SC16C2552B_3

Product data sheet

Rev. 03 — 12 February 2009

9 of 38

SC16C2552B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

made available at the user data interface D0 to D7. The user optionally compares the

received data to the initial transmitted data for verifying error-free operation of the UART

TX/RX circuits.

In this mode, the receiver and transmitter interrupts are fully operational. The Modem

Control Interrupts are also operational. However, the interrupts can only be read using

lower four bits of the Modem Status Register (MSR[3:0]) instead of the four Modem Status

Register bits 7:4. The interrupts are still controlled by the IER.

SC16C2552B

TRANSMIT

FIFO

TRANSMIT

SHIFT

TXA, TXB

REGISTERS

REGISTER

D0 to D7

IOR

DATA BUS

AND

IOW

RESET

CONTROL

LOGIC

MCR[4] = 1

RECEIVE

FIFO

REGISTERS

RECEIVE

SHIFT

REGISTER

RXA, RXB

REGISTER

SELECT

LOGIC

A0 to A2

CS

CHSEL

RTSA, RTSB

CTSA, CTSB

DTRA, DTRB

MODEM

CONTROL

LOGIC

DSRA, DSRB

(OP1A, OP1B)

INTA, INTB

TXRDYA, TXRDYB

RXRDYA, RXRDYB

INTERRUPT

CONTROL

LOGIC

CLOCK AND

BAUD RATE

GENERATOR

RIA, RIB

(OP2A, OP2B)

CDA, CDB

002aaa489

XTAL2

XTAL1

Fig 4. Internal Loopback mode diagram

SC16C2552B_3

Product data sheet

Rev. 03 — 12 February 2009

10 of 38

SC16C2552B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

7. Register descriptions

Table 6 details the assigned bit functions for the SC16C2552B internal registers. The

assigned bit functions are further deﬁned in Section 7.1 through Section 7.11.

Table 6.

SC16C2552B internal registers

A2 A1 A0 Register Default^[1]Bit 7

General register set^[2]

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

1

RHR

THR

IER

XX

00

bit 7

0

bit 6

0

bit 5

0

bit 4

0

bit 3

bit 2

bit 1

bit 0

modem receive transmit receive

status line holding holding

interrupt status register register

interrupt interrupt

0

1

0

1

0

1

FCR

ISR

00

01

00

60

RCVR

trigger

(MSB)

RCVR

trigger

(LSB)

0

DMA

mode

select

XMIT RCVR

FIFO FIFO

FIFOs

enable

reset

FIFOs

enabled enabled

FIFOs

INT

priority

bit 2

INT

status

priority

bit 1

priority

bit 0

LCR

MCR

LSR

divisor

latch

enable

set break set parity even

parity

enable

stop bits word

length

word

length

bit 0

bit 1

0

loopback OP2

OP1

RTS

DTR

output

control

FIFO

data

error

THR and THR

TSR

empty

break

interrupt error

framing parity

overrun receive

empty

error

data

ready

1

0

1

MSR

SPR

X0

FF

CD

RI

DSR

bit 5

CTS

bit 4

∆CD

∆RI

∆DSR

∆CTS

bit 7

bit 6

bit 3

bit 2

bit 1

bit 0

Special register set^[3]

0

1

0

1

0

DLL

DLM

AFR

XX

00

bit 7

bit 15

bit 7

bit 6

bit 14

bit 6

bit 5

bit 13

bit 5

bit 4

bit 12

bit 4

bit 3

bit 11

bit 3

bit 2

bit 10

bit 2

bit 1

bit 9

bit 1

bit 0

bit 8

bit 0

[1] The value shown represents the register’s initialized hexadecimal value; X = not applicable.

[2] The ‘General register set’ registers are accessible only when CS is a logic 0 and LCR[7] is logic 0.

[3] The Baud rate register and AFR register sets are accessible only when CS is a logic 0 and LCR[7] is a logic 1.

Set A is accessible when CHSEL is a logic 1, and Set B is accessible when CHSEL is a logic 0.

SC16C2552B_3

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SC16C2552B

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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

7.1 Transmit Holding Register (THR) and Receive Holding Register (RHR)

The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and

Transmit Shift Register (TSR). The status of the THR is provided in the Line Status

Register (LSR). Writing to the THR transfers the contents of the data bus (D7 through D0)

to the TSR and UART via the THR, providing that the THR is empty. The THR empty ﬂag

in the LSR[5] register will be set to a logic 1 when the transmitter is empty or when data is

transferred to the TSR.

The serial receive section also contains an 8-bit Receive Holding Register (RHR) and a

Receive Serial Shift Register (RSR). Receive data is removed from the SC16C2552B and

receive FIFO by reading the RHR register. The receive section provides a mechanism to

prevent false starts. On the falling edge of a start or false start bit, an internal receiver

counter starts counting clocks at the 16× clock rate. After 7¹⁄₂clocks, the start bit time

should be shifted to the center of the start bit. At this time the start bit is sampled, and if it

is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver

from assembling a false character. Receiver status codes will be posted in the LSR.

7.2 Interrupt Enable Register (IER)

The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter

empty, line status and modem status registers. These interrupts would normally be seen

on the INTA, INTB output pins.

Table 7.

Interrupt Enable Register bits description

Bit

7:4

3

Symbol

Description

IER[7:4]

IER[3]

not used; initialized to logic 0

Modem Status Interrupt. This interrupt will be issued whenever there is a

modem status change as reﬂected in MSR[3:0].

logic 0 = disable the Modem Status Register interrupt (normal default

condition)

logic 1 = enable the Modem Status Register interrupt

2

1

IER[2]

IER[1]

Receive Line Status interrupt. This interrupt will be issued whenever a receive

data error condition exists as reﬂected in LSR[4:1].

logic 0 = disable the receiver line status interrupt (normal default condition)

logic 1 = enable the receiver line status interrupt

Transmit Holding Register interrupt. In the 16C450 mode, this interrupt will be

issued whenever the THR is empty and is associated with LSR[5]. In the FIFO

modes, this interrupt will be issued whenever the FIFO and THR are empty.

logic 0 = disable the Transmit Holding Register Empty (TXRDY) interrupt

(normal default condition)

logic 1 = enable the TXRDY (ISR level 3) interrupt

0

IER[0]

Receive Holding Register. In the 16C450 mode, this interrupt will be issued

when the RHR has data, or is cleared when the RHR is empty. In the FIFO

mode, this interrupt will be issued when the FIFO has reached the

programmed trigger level or is cleared when the FIFO drops below the trigger

level.

logic 0 = disable the receiver ready (ISR level 2, RXRDY) interrupt (normal

default condition)

logic 1 = enable the RXRDY (ISR level 2) interrupt

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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

7.2.1 IER versus Transmit/Receive FIFO interrupt mode operation

When the receive FIFO (FCR[0] = logic 1) and receive interrupts (IER[0] = logic 1) are

enabled, the receive interrupts and register status will reﬂect the following:

• The receive RXRDY interrupt (Level 2 ISR interrupt) is issued to the external CPU

when the receive FIFO has reached the programmed trigger level. It will be cleared

when the receive FIFO drops below the programmed trigger level.

• Receive FIFO status will also be reﬂected in the user accessible ISR register when

the receive FIFO trigger level is reached. Both the ISR register receive status bit and

the interrupt will be cleared when the FIFO drops below the trigger level.

• The receive data ready bit (LSR[0]) is set as soon as a character is transferred from

the shift register (RSR) to the receive FIFO. It is reset when the FIFO is empty.

• When the Transmit FIFO and interrupts are enabled, an interrupt is generated when

the transmit FIFO is empty due to the unloading of the data by the TSR and UART for

transmission via the transmission media. The interrupt is cleared either by reading the

ISR register or by loading the THR with new data characters.

7.2.2 IER versus Receive/Transmit FIFO polled mode operation

When FCR[0] = logic 1, resetting IER[3:0] enables the SC16C2552B in the FIFO polled

mode of operation. In this mode, interrupts are not generated and the user must poll the

LSR register for TX and/or RX data status. Since the receiver and transmitter have

separate bits in the LSR either or both can be used in the polled mode by selecting

respective transmit or receive control bit(s).

• LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.

• LSR[4:1] will provide the type of receive errors or a receive break, if encountered.

• LSR[5] will indicate when the transmit FIFO is empty.

• LSR[6] will indicate when both the transmit FIFO and transmit shift register are empty.

• LSR[7] will show if any FIFO data errors occurred.

SC16C2552B_3

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SC16C2552B

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7.3 FIFO Control Register (FCR)

This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger

levels and select the DMA mode.

7.3.1 DMA mode

7.3.1.1 Mode 0 (FCR bit 3 = 0)

Set and enable the interrupt for each single transmit or receive operation and is similar to

the 16C450 mode. Transmit Ready (TXRDY) will go to a logic 0 whenever an empty

transmit space is available in the Transmit Holding Register (THR). Receive Ready

(RXRDY) at the MFn pin will go to a logic 0 whenever the Receive Holding Register (RHR)

is loaded with a character and AFR[2:1] is set to the RXRDY mode.

7.3.1.2 Mode 1 (FCR bit 3 = 1)

Set and enable the interrupt in a block mode operation. The transmit interrupt is set when

the transmit FIFO has at least one empty location. TXRDY remains a logic 0 as long as

one empty FIFO location is available. The receive interrupt is set when the receive FIFO

ﬁlls to the programmed trigger level. However, the FIFO continues to ﬁll regardless of the

programmed level until the FIFO is full. RXRDY at the MFn pin remains a logic 0 as long

as the FIFO ﬁll level is above the programmed trigger level, and AFR[2:1] is set to the

RXRDY mode.

7.3.2 FIFO mode

Table 8.

FIFO Control Register bits description

Bit

Symbol

Description

7:6

FCR[7:6]

RCVR trigger. These bits are used to set the trigger level for the receive

FIFO interrupt.

An interrupt is generated when the number of characters in the FIFO

equals the programmed trigger level. However, the FIFO will continue to

be loaded until it is full. Refer to Table 9.

5:4

3

FCR[5:4]

FCR[3]

Not used; initialized to logic 0.

DMA mode select.

logic 0 = set DMA mode ‘0’ (normal default condition)

logic 1 = set DMA mode ‘1’

Transmit operation in mode ‘0’: When the SC16C2552B is in the

16C450 mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode

(FIFOs enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there

are no characters in the transmit FIFO or Transmit Holding Register, the

TXRDYn pin will be a logic 0. Once active, the TXRDYn pin will go to a

logic 1 after the ﬁrst character is loaded into the Transmit Holding

Register.

Receive operation in mode ‘0’: When the SC16C2552B is in 16C450

mode, or in the FIFO mode (FCR[0] = logic 1; FCR[3] = logic 0) and

there is at least one character in the receive FIFO, the RXRDY signal at

the MFn pin will be a logic 0. Once active, the RXRDY signal at the

MFn pin will go to a logic 1 when there are no more characters in the

receiver. Note that the AFR register must be set to the RXRDY mode

prior to any possible reading of the RXRDY signal.

SC16C2552B_3

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SC16C2552B

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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

Table 8.

FIFO Control Register bits description …continued

Bit

Symbol

Description

3

Transmit operation in mode ‘1’: When the SC16C2552B is in FIFO

mode (FCR[0] = logic 1; FCR[3] = logic 1), the TXRDYn pin will be a

logic 1 when the transmit FIFO is completely full. It will be a logic 0 if

one or more FIFO locations are empty.

(continued)

Receive operation in mode ‘1’: When the SC16C2552B is in FIFO

mode (FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been

reached, or a Receive Time-out has occurred, the RXRDY signal at the

MFn pin will go to a logic 0. Once activated, it will go to a logic 1 after

there are no more characters in the FIFO. Note that the AFR register

must be set to the RXRDY mode prior to any possible reading of the

RXRDY signal.

2

1

0

FCR[2]

FCR[1]

FCR[0]

XMIT FIFO reset.

logic 0 = no FIFO transmit reset (normal default condition)

logic 1 = clears the contents of the transmit FIFO and resets the FIFO

counter logic (the Transmit Shift Register is not cleared or altered).

This bit will return to a logic 0 after clearing the FIFO.

RCVR FIFO reset.

logic 0 = no FIFO receive reset (normal default condition)

logic 1 = clears the contents of the receive FIFO and resets the FIFO

counter logic (the Receive Shift Register is not cleared or altered).

This bit will return to a logic 0 after clearing the FIFO.

FIFOs enabled.

logic 0 = disable the transmit and receive FIFO (normal default

condition)

logic 1 = enable the transmit and receive FIFO. This bit must be a ‘1’

when other FCR bits are written to or they will not be

programmed.

Table 9.

RCVR trigger levels

FCR[7]

FCR[6]

RX FIFO trigger level

0

1

0

1

0

1

01

04

08

14

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SC16C2552B

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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

7.4 Interrupt Status Register (ISR)

The SC16C2552B provides four levels of prioritized interrupts to minimize external

software interaction. The Interrupt Status Register (ISR) provides the user with four

interrupt status bits. Performing a read cycle on the ISR will provide the user with the

highest pending interrupt level to be serviced. No other interrupts are acknowledged until

the pending interrupt is serviced. Whenever the interrupt status register is read, the

interrupt status is cleared. However, it should be noted that only the current pending

interrupt is cleared by the read. A lower level interrupt may be seen after re-reading the

interrupt status bits. Table 10 shows the data values (bits 3:0) for the four prioritized

interrupt levels and the interrupt sources associated with each of these interrupt levels.

Table 10. Interrupt source

Priority ISR[3] ISR[2] ISR[1] ISR[0] Source of the interrupt

level

1

2

3

4

0

1

0

1

0

1

0

1

0

LSR (Receiver Line Status Register)

RXRDY (Received Data Ready)

RXRDY (Receive Data Time-out)

TXRDY (Transmitter Holding Register empty)

MSR (Modem Status Register)

Table 11. Interrupt Status Register bits description

Bit

Symbol

Description

7:6

ISR[7:6]

FIFOs enabled. These bits are set to a logic 0 when the FIFOs are not being

used in the 16C450 mode. They are set to a logic 1 when the FIFOs are

enabled in the SC16C2552B mode.

logic 0 or cleared = default condition

not used; initialized to a logic 0

5:4

3:1

ISR[5:4]

ISR[3:1]

INT priority bits. These bits indicate the source for a pending interrupt at

interrupt priority levels 1, 2 and 3 (see Table 10).

0

ISR[0]

INT status.

logic 0 = an interrupt is pending and the ISR contents may be used as a

pointer to the appropriate interrupt service routine

logic 1 = no interrupt pending (normal default condition)

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SC16C2552B

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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

7.5 Line Control Register (LCR)

The Line Control Register is used to specify the asynchronous data communication

format. The word length, the number of stop bits and the parity are selected by writing the

appropriate bits in this register.

Table 12. Line Control Register bits description

Bit

Symbol

Description

7

LCR[7]

Divisor latch enable. The internal baud rate counter latch and Enhanced

Feature mode enable.

logic 0 = divisor latch disabled (normal default condition)

logic 1 = divisor latch enabled

6

LCR[6]

Set break. When enabled, the Break control bit causes a break condition

to be transmitted (the TX output is forced to a logic 0 state). This

condition exists until disabled by setting LCR[6] to a logic 0.

logic 0 = no TX break condition (normal default condition)

logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the

remote receiver to a line break condition

5:3

2

LCR[5:3]

LCR[2]

Programs the parity conditions (see Table 13)

Stop bits. The length of stop bit is speciﬁed by this bit in conjunction with

the programmed word length (see Table 14).

logic 0 or cleared = default condition

1:0

LCR[1:0]

Word length bits 1, 0. These two bits specify the word length to be

transmitted or received (see Table 15).

logic 0 or cleared = default condition

Table 13. LCR[5:3] parity selection

LCR[5]

LCR[4]

LCR[3]

Parity selection

no parity

X

0

1

X

0

1

0

1

0

1

odd parity

even parity

forced parity ‘1’

forced parity ‘0’

Table 14. LCR[2] stop bit length

LCR[2]

Word length (bits)

Stop bit length (bit times)

0

1

5, 6, 7, 8

5

1

1¹⁄₂

6, 7, 8

2

Table 15. LCR[1:0] word length

LCR[1]

LCR[0]

Word length (bits)

0

1

0

1

0

1

5

6

7

8

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SC16C2552B

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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

7.6 Modem Control Register (MCR)

This register controls the interface with the modem or a peripheral device.

Table 16. Modem Control Register bits description

Bit

7:5

4

Symbol

MCR[7:5]

MCR[4]

Description

reserved; initialized to a logic 0

Loopback. Enable the local Loopback mode (diagnostics). In this mode the

transmitter output (TX) and the receiver input (RX), CTS, DSR, CD and RI

are disconnected from the SC16C2552B I/O pins. Internally the modem

data and control pins are connected into a loopback data conﬁguration

(see Figure 4). In this mode, the receiver and transmitter interrupts remain

fully operational. The modem control interrupts are also operational, but

the interrupts’ sources are switched to the lower four bits of the Modem

Control. Interrupts continue to be controlled by the IER register.

logic 0 = disable Loopback mode (normal default condition)

logic 1 = enable local Loopback mode (diagnostics)

3

MCR[3]

OP2. Used to control the modem CD signal in the Loopback mode.

logic 0 = sets OP2 to a logic 1 (normal default condition). In the

Loopback mode, sets CD internally to a logic 1.

logic 1 = sets OP2 to a logic 0. In the Loopback mode, sets CD internally

to a logic 0.

2

1

MCR[2]

MCR[1]

OP1. This bit is used in the Loopback mode only. In the Loopback mode,

this bit is used to write the state of the modem RI interface signal.

RTS

logic 0 = force RTS output to a logic 1 (normal default condition)

logic 1 = force RTS output to a logic 0

0

MCR[0]

DTR

logic 0 = force DTR output to a logic 1 (normal default condition)

logic 1 = force DTR output to a logic 0

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SC16C2552B

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7.7 Line Status Register (LSR)

This register provides the status of data transfers between the SC16C2552B and

the CPU.

Table 17. Line Status Register bits description

Bit Symbol Description

7

LSR[7]

FIFO data error.

logic 0 = no error (normal default condition)

logic 1 = at least one parity error, framing error or break indication is in the

current FIFO data. This bit is cleared when RHR register is read.

6

LSR[6]

THR and TSR empty. This bit is the Transmit Empty indicator. This bit is set to a

logic 1 whenever the Transmit Holding Register and the Transmit Shift Register

are both empty. It is reset to logic 0 whenever either the THR or TSR contains a

data character. In the FIFO mode, this bit is set to logic 1 whenever the Transmit

FIFO and Transmit Shift Register are both empty.

5

LSR[5]

THR empty. This bit is the Transmit Holding Register Empty indicator. This bit

indicates that the UART is ready to accept a new character for transmission. In

addition, this bit causes the UART to issue an interrupt to CPU when the THR

interrupt enable is set. The THR bit is set to a logic 1 when a character is

transferred from the Transmit Holding Register into the Transmit Shift Register.

The bit is reset to a logic 0 concurrently with the loading of the Transmit Holding

Register by the CPU. In the FIFO mode, this bit is set when the transmit FIFO is

empty; it is cleared when at least 1 byte is written to the transmit FIFO.

4

3

2

1

LSR[4]

LSR[3]

LSR[2]

LSR[1]

Break interrupt.

logic 0 = no break condition (normal default condition)

logic 1 = the receiver received a break signal (RX was a logic 0 for one

character frame time). In the FIFO mode, only one break character is loaded

into the FIFO.

Framing error.

logic 0 = no framing error (normal default condition)

logic 1 = framing error. The receive character did not have a valid stop bit(s). In

the FIFO mode, this error is associated with the character at the top of the

FIFO.

Parity error.

logic 0 = no parity error (normal default condition

logic 1 = parity error. The receive character does not have correct parity

information and is suspect. In the FIFO mode, this error is associated with the

character at the top of the FIFO.

Overrun error.

logic 0 = no overrun error (normal default condition)

logic 1 = overrun error. A data overrun error occurred in the Receive Shift

Register. This happens when additional data arrives while the FIFO is full. In

this case, the previous data in the shift register is overwritten. Note that under

this condition, the data byte in the Receive Shift Register is not transferred into

the FIFO, therefore the data in the FIFO is not corrupted by the error.

0

LSR[0]

Receive data ready.

logic 0 = no data in Receive Holding Register or FIFO (normal default

condition)

logic 1 = data has been received and is saved in the Receive Holding Register

or FIFO

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SC16C2552B

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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

7.8 Modem Status Register (MSR)

This register provides the current state of the control interface signals from the modem or

other peripheral device to which the SC16C2552B is connected. Four bits of this register

are used to indicate the changed information. These bits are set to a logic 1 whenever a

control input from the modem changes state. These bits are set to a logic 0 whenever the

CPU reads this register.

Table 18. Modem Status Register bits description

Bit

Symbol

Description

7

MSR[7]

Carrier Detect, CD. During normal operation, this bit is the complement of the

CD input. Reading this bit in the Loopback mode produces the state of

MCR[3] (OP2A/OP2B).

6

5

4

3

MSR[6]

MSR[5]

MSR[4]

MSR[3]

Ring Indicator, RI. During normal operation, this bit is the complement of the

RI input. Reading this bit in the Loopback mode produces the state of

MCR[2] (OP1A/OP2A).

Data Set Ready, DSR. During normal operation, this bit is the complement of

the DSR input. During the Loopback mode, this bit is equivalent to MCR[0]

(DTR).

Clear To Send, CTS. During normal operation, this bit is the complement of

the CTS input. During the Loopback mode, this bit is equivalent to MCR[1]

(RTS).

∆CD ^[1]

logic 0 = no CD change (normal default condition)

logic 1 = the CD input to the SC16C2552B has changed state since the

last time it was read. A modem Status Interrupt will be generated.

2

1

0

MSR[2]

MSR[1]

MSR[0]

∆RI ^[1]

logic 0 = no RI change (normal default condition)

logic 1 = the RI input to the SC16C2552B has changed from a logic 0 to a

logic 1. A modem Status Interrupt will be generated.

∆DSR ^[1]

logic 0 = no DSR change (normal default condition)

logic 1 = the DSR input to the SC16C2552B has changed state since the

last time it was read. A modem Status Interrupt will be generated.

∆CTS ^[1]

logic 0 = no CTS change (normal default condition)

logic 1 = the CTS input to the SC16C2552B has changed state since the

last time it was read. A modem Status Interrupt will be generated.

[1] Whenever any MSR bit 3:0 is set to logic 1, a Modem Status Interrupt will be generated.

SC16C2552B_3

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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

7.9 Scratchpad Register (SPR)

The SC16C2552B provides a temporary data register to store 8 bits of user information.

7.10 Alternate Function Register (AFR)

This is a read/write register used to select speciﬁc modes of MF operation and to allow

both UART register’s sets to be written concurrently.

Table 19. Alternate Function Register bit description

Bit

7:3

2:1

Symbol

AFR[7:3]

AFR[2:1]

Description

Not used. All are initialized to logic 0.

Selects a signal function for output on the MFA, MFB pins. These signal

functions are described as: OP2 (interrupt enable), BAUDOUT, or RXRDY.

Only one signal function can be selected at a time. See Table 20.

0

AFR[0]

When this bit is set, CPU can write concurrently to the same register in both

UARTs. This function is intended to reduce the dual UART initialization time.

It can be used by CPU when both channels are initialized to the same state.

The external CPU can set or clear this bit by accessing either register set.

When this bit is set, the Channel Select pin, CHSEL, still selects the channel

to be accessed during read operation. Setting or clearing this bit has no

effect on read operations. The user should ensure that LCR[7] of both

channels are in the same state before executing a concurrent write to the

registers at address 0, 1, or 2.

logic 0 = no concurrent write (normal default condition)

logic 1 = register set A and B are written concurrently with a single external

CPU I/O write operation.

Table 20. MFA, MFB function selection

AFR[2]

AFR[1]

MF function

OP2

0

1

0

1

0

1

BAUDOUT

RXRDY

reserved

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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

7.11 SC16C2552B external reset condition

Table 21. Reset state for registers

Register

IER

Reset state

IER[7:0] = 0

ISR

ISR[7:1] = 0; ISR[0] = 1

LCR[7:0] = 0

LCR

MCR

LSR

MCR[7:0] = 0

LSR[7] = 0; LSR[6:5] = 1; LSR[4:0] = 0

MSR[7:4] = input signals; MSR[3:0] = 0

FCR[7:0] = 0

MSR

FCR

AFR

AFR[7:0] = 0

Table 22. Reset state for outputs

Output

Reset state

HIGH

TXA, TXB

OP2A, OP2B

RTSA, RTSB

DTRA, DTRB

INTA, INTB

HIGH

LOW

TXRDYA, TXRDYB

LOW

8. Limiting values

Table 23. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_CC

Parameter

Conditions

Min

Max

Unit

V

supply voltage

-

7

V_n

voltage on any other pin

at D7 to D0 pins

at input only pins

GND − 0.3 V_CC+ 0.3

GND − 0.3 5.3

V

T_amb

operating temperature

storage temperature

−40

−65

-

+85

°C

mW

T_stg

+150

500

P_tot/pack

total power dissipation

per package

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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

9. Static characteristics

Table 24. Static characteristics

T_amb= −40 °C to +85 °C; tolerance of V_CC± 10 %; unless otherwise speciﬁed.

Symbol Parameter

Conditions

V_CC= 2.5 V

V_CC= 3.3 V

V_CC= 5.0 V

Unit

Min

Max

Min

Max

Min

Max

V_IL(clk)

V_IH(clk)

clock LOW-level input

voltage

−0.3

+0.45

−0.3

+0.6

−0.5

+0.6

V

clock HIGH-level input

voltage

1.8

V_CC

2.4

V_CC

3.0

V_CC

V_IL

LOW-level input voltage

except X1 clock

−0.3

+0.65

-

−0.3

+0.8

-

−0.5

+0.8

-

V

V_IH

V_OL

HIGH-level input voltage except X1 clock

LOW-level output voltage on all outputs^[1]

1.6

2.0

2.2

I_OL= 5 mA

(data bus)

-

0.4

V

I_OL= 4 mA

(other outputs)

-

0.4

-

0.4

-

I_OL= 2 mA

(data bus)

-

I_OL= 1.6 mA

(other outputs)

-

V_OH

HIGH-level output voltage I_OH= −5 mA

-

2.4

(data bus)

I_OH= −1 mA

(other outputs)

-

2.0

-

I_OH= −800 µA

(data bus)

1.85

-

I_OH= −400 µA

(other outputs)

-

I_LIL

LOW-level input leakage

current

±10

±10 µA

±30 µA

I_L(clk)

I_CC

C_i

clock leakage current

-

±30

3.5

5

-

±30

4.5

5

-

supply current

f = 5 MHz

4.5

5

mA

pF

input capacitance

[1] Except XTAL2, V_OL= 1 V typical.

SC16C2552B_3

Product data sheet

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SC16C2552B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

10. Dynamic characteristics

Table 25. Dynamic characteristics

T_amb= −40 °C to +85 °C; tolerance of V_CC± 10 %; unless otherwise speciﬁed.

Symbol Parameter

Conditions

V_CC= 2.5 V

V_CC= 3.3 V

V_CC= 5.0 V

Unit

Min

Max

Min

Max

Min

Max

t_WH

t_WL

f_XTAL1

t_6s

pulse width HIGH

10

-

6

-

6

-

ns

pulse width LOW

ns

[1][2]

frequency on pin XTAL1

address set-up time

address hold time

48

-

80

-

80

-

MHz

ns

0

t_6h

0

-

0

-

ns

t_7d

IOR delay from chip select

IOR strobe width

10

77

0

-

10

26

0

-

10

23

0

-

ns

t_7w

25 pF load

-

ns

t_7h

chip select hold time from

IOR

-

ns

t_9d

read cycle delay

25 pF load

20

-

77

15

-

20

-

26

15

-

20

-

23

15

-

ns

t_12d

t_12h

t_13d

t_13w

t_13h

delay from IOR to data

data disable time

-

IOW delay from chip select

IOW strobe width

10

20

0

10

20

0

10

15

0

-

chip select hold time from

IOW

-

t_15d

t_16s

t_16h

t_17d

t_18d

write cycle delay

data set-up time

25

20

15

-

25

20

5

-

20

15

5

-

ns

data hold time

-

delay from IOW to output

25 pF load

100

-

33

24

-

29

23

delay to set interrupt from 25 pF load

Modem input

-

t_19d

t_20d

t_21d

t_22d

t_23d

t_24d

t_25d

t_26d

t_27d

delay to reset interrupt from 25 pF load

IOR

-

100

T_RCLK

100

-

24

T_RCLK

29

-

23

T_RCLK

28

ns

s

[3]

delay from stop to set

interrupt

delay from IOR to reset

interrupt

25 pF load

ns

s

delay from start to set

interrupt

100

45

40

[3]

delay from IOW to transmit

start

8T_RCLK24T_RCLK8T_RCLK24T_RCLK8T_RCLK24T_RCLK

delay from IOW to reset

interrupt

-

100

T_RCLK

100

-

45

T_RCLK

45

-

40

T_RCLK

40

ns

s

delay from stop to set

RXRDY

delay from IOR to reset

RXRDY

ns

delay from IOW to set

TXRDY

100

45

40

SC16C2552B_3

Product data sheet

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SC16C2552B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

Table 25. Dynamic characteristics …continued

T_amb= −40 °C to +85 °C; tolerance of V_CC± 10 %; unless otherwise speciﬁed.

Symbol Parameter

Conditions

V_CC= 2.5 V

V_CC= 3.3 V

V_CC= 5.0 V

Unit

Min

Max

Min

Max

Min

Max

[3]

[4]

t_28d

delay from start to reset

TXRDY

-

8T_RCLK

-

8T_RCLK

-

8T_RCLK

s

t_RESET

N

RESET pulse width

baud rate divisor

200

1

-

40

1

-

40

1

-

ns

(2¹⁶− 1)

[1] Applies to external clock, crystal oscillator max 24 MHz.

1

[2] Maximum frequency =

--------------

t_w(clk)

[3] RCLK is an internal signal derived from divisor latch LSB (DLL) and divisor latch MSB (DLM) divisor latches.

[4] Reset pulse must happen when these signals are inactive: CS, IOW, IOR.

10.1 Timing diagrams

t

6h

valid

address

A0 to A2

CHSEL

CS

t

13h

6s

active

t

15d

13d

13w

IOW

active

t

16h

16s

D0 to D7

data

002aaa128

Fig 5. General write timing

SC16C2552B_3

Product data sheet

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SC16C2552B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

t

6h

valid

address

A0 to A2

CHSEL

t

7h

6s

active

CS

t

9d

7d

7w

IOR

active

t

12h

12d

D0 to D7

data

002aaa127

Fig 6. General read timing

active

IOW

t

17d

RTSA, RTSB

DTRA, DTRB

change of state

CDA, CDB

CTSA, CTSB

DSRA, DSRB

change of state

t

18d

INTA, INTB

active

t

19d

IOR

t

18d

change of state

RIA, RIB

002aaa352

Fig 7. Modem input/output timing

SC16C2552B_3

Product data sheet

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SC16C2552B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

t

WH

WL

external clock

t

w(clk)

002aac357

1

f _XTAL1

=

--------------

t_w(clk)

Fig 8. External clock timing

start

bit

parity stop start

bit

data bits (0 to 7)

D3 D4

RXA, RXB

D0

D1

D2

D5

D6

D7

5 data bits

6 data bits

7 data bits

t

20d

active

INTA, INTB

t

21d

active

IOR

16 baud rate clock

002aae287

Fig 9. Receive timing

SC16C2552B_3

Product data sheet

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SC16C2552B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

start

bit

parity stop start

bit

data bits (0 to 7)

D3 D4

D0

D1

D2

D5

D6

D7

RXA, RXB

t

25d

active data

ready

RXRDYA, RXRDYB

t

26d

active

IOR

002aae288

Fig 10. Receive ready timing in non-FIFO mode

start

bit

parity stop

bit bit

data bits (0 to 7)

D3 D4

D0

D1

D2

D5

D6

D7

RXA, RXB

first byte that

reaches the

trigger level

t

25d

active data

ready

RXRDYA, RXRDYB

t

26d

active

IOR

002aae289

Fig 11. Receive ready timing in FIFO mode

SC16C2552B_3

Product data sheet

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SC16C2552B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

start

bit

parity stop start

bit

data bits (0 to 7)

TXA, TXB

D0

D1

D2

D3

D4

D5

D6

D7

5 data bits

6 data bits

7 data bits

active

INTA, INTB

transmitter ready

t

22d

t

24d

t

23d

active

IOW

16 baud rate clock

002aae290

Fig 12. Transmit timing

start

bit

parity stop start

bit bit bit

data bits (0 to 7)

D3 D4

TXA, TXB

D0

D1

D2

D5

D6

D7

active

IOW

D0 to D7

byte #1

t

28d

t

27d

active

transmitter ready

transmitter

not ready

TXRDYA, TXRDYB

002aae291

Fig 13. Transmit ready timing in non-FIFO mode

SC16C2552B_3

Product data sheet

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29 of 38

SC16C2552B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

start

bit

parity stop

bit

data bits (0 to 7)

D3 D4

D0

D1

D2

D5

D6

D7

TXA, TXB

5 data bits

6 data bits

7 data bits

IOW

active

t

28d

D0 to D7

byte #16

t

27d

TXRDYA, TXRDYB

FIFO full

002aae292

Fig 14. Transmit ready timing in FIFO mode (DMA mode ‘1’)

SC16C2552B_3

Product data sheet

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30 of 38

SC16C2552B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

11. Package outline

PLCC44: plastic leaded chip carrier; 44 leads

SOT187-2

e

E

D

y

X

A

39

29

b

p

Z

E

28

40

b

1

w

M

44

1

H

E

pin 1 index

A

1

A

4

e

(A )

3

6

18

β

L

p

k

detail X

7

17

v

M

A

e

Z

D

B

H

v

M

B

D

0

5

10 mm

scale

DIMENSIONS (mm dimensions are derived from the original inch dimensions)

(1)

A

Z

E

4

1

(1)

D

UNIT

mm

A

b

D

E

e

H

k

L

p

v

w

y

β

b

3

1

D

E

D

E

p

max.

min.

max. max.

4.57

4.19

0.81 16.66 16.66

0.66 16.51 16.51

16.00 16.00 17.65 17.65 1.22 1.44

14.99 14.99 17.40 17.40 1.07 1.02

0.53

0.33

0.51 0.25 3.05

0.02 0.01 0.12

1.27

0.05

0.18 0.18

0.1

2.16 2.16

o

45

0.180

0.165

0.032 0.656 0.656

0.026 0.650 0.650

0.63 0.63 0.695 0.695 0.048 0.057

0.59 0.59 0.685 0.685 0.042 0.040

0.021

0.013

inches

0.007 0.007 0.004 0.085 0.085

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

99-12-27

VERSION

IEC

JEDEC

JEITA

SOT187-2

112E10

MS-018

EDR-7319

01-11-14

Fig 15. Package outline SOT187-2 (PLCC44)

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Product data sheet

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SC16C2552B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

12. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reﬂow

soldering description”.

12.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

12.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

• Board speciﬁcations, including the board ﬁnish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

12.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath speciﬁcations, including temperature and impurities

SC16C2552B_3

Product data sheet

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32 of 38

SC16C2552B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

12.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 16) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 26 and 27

Table 26. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

235

≥ 350

220

< 2.5

≥ 2.5

220

Table 27. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 16.

SC16C2552B_3

Product data sheet

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33 of 38

SC16C2552B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 16. Temperature proﬁles for large and small components

For further information on temperature proﬁles, refer to Application Note AN10365

“Surface mount reﬂow soldering description”.

13. Abbreviations

Table 28. Abbreviations

Acronym

CPU

Description

Central Processing Unit

Divisor Latch LSB

DLL

DLM

Divisor Latch MSB

DMA

FIFO

ISDN

LSB

Direct Memory Access

First In, First Out

Integrated Service Digital Network

Least Signiﬁcant Bit

MSB

Most Signiﬁcant Bit

UART

Universal Asynchronous Receiver and Transmitter

SC16C2552B_3

Product data sheet

Rev. 03 — 12 February 2009

34 of 38

SC16C2552B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

14. Revision history

Table 29. Revision history

Document ID

SC16C2552B_3

Modiﬁcations:

Release date

Data sheet status

Change notice

Supersedes

20090212

Product data sheet

-

SC16C2552B-02

• The format of this data sheet has been redesigned to comply with the new identity guidelines of

NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• Section 2 “Features”:

–

added (new) 5^thbullet item

added Footnote 1

–

• Figure 1: changed signal names from “MFA, MFB” to “MFA, MFB”

• Section 7.3.1 “DMA mode”:

–

1^stparagraph, last sentence: changed from “MF register” to “AFR[2:1]”

2^ndparagraph, last sentence: changed from “MF register” to “AFR[2:1]”

–

• Table 18 “Modem Status Register bits description”:

–

description of bit 7: changed from “(OPA/OPB)” to “(OP2A/OP2B)”

–

description of bit 6: changed from “(OP1)” to “(OP1A/OP2A)”

• Table 23 “Limiting values”:

–

symbol V_nsplit to show 2 separate conditions: “at D7 to D0 pins” and “at input only pins”

–

changed symbol “P_tot(pack)” to “P_tot/pack”

• Table 24 “Static characteristics”:

–

descriptive line below table title changed from “V_CC= 2.5 V, 3.3 V or 5.0 V ± 10 %” to

“tolerance of V_CC± 10 %”

changed symbol/parameter from “V_IL(CK), LOW-level clock input voltage” to “V_IL(clk), clock

LOW-level input voltage”

changed symbol/parameter from “V_IH(CK), HIGH-level clock input voltage” to “V_IH(clk), clock

HIGH-level input voltage”

–

changed symbol/parameter from “I_CL, clock leakage” to “I_L(clk), clock leakage current”

Table note [1]: changed from “Except x₂” to “Except XTAL2”

• Table 25 “Dynamic characteristics”:

–

descriptive line below table title changed from “V_CC= 2.5 V, 3.3 V or 5.0 V ± 10 %” to

“tolerance of V_CC± 10 %”

–

changed symbol “t_1w, t_2w” to 2 separate symbols “t_WH” and “t_WL”

changed symbol/parameter “t_3w, clock frequency” to “f_XTAL1, frequency on pin XTAL1”

added Table note [2]

symbols t_20d, t_23d, t_25dand t_28d: Unit changed from “R_clk” to “s” (second)

symbols t_20d, t_23d, t_25dand t_28d: appended “T_RCLK” to Min and Max values

added Table note [3]

symbol N: removed “R_clk” from Unit column (N is a number)

added Table note [4] and its reference at t_RESET

SC16C2552B_3

Product data sheet

Rev. 03 — 12 February 2009

35 of 38

SC16C2552B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

Table 29. Revision history …continued

Document ID

Release date

Data sheet status

Change notice

Supersedes

Modiﬁcations:

(continued)

• Section 10.1 “Timing diagrams”:

–

Figure 7, Figure 9, Figure 10, Figure 11, Figure 12, Figure 13, Figure 14: appended

(channel) “A” and/or “B” to signal names

Figure 8 “External clock timing”: changed symbols “t_1w, t_2w, t_3w” to “t_WH, t_WL, t_w(clk)”,

respectively

–

Figure 8 “External clock timing”: added equation

Figure 10, Figure 11, Figure 13, Figure 14: at the top of these drawings, changed phrase

from “DATA BITS (5-8)” to “data bits (0 to 7)”

• updated soldering information

• added Section 13 “Abbreviations”

SC16C2552B-02

(9397 750 14442)

20041213

20040330

Product data

-

SC16C2552B-01

-

SC16C2552B-01

(9397 750 11966)

SC16C2552B_3

Product data sheet

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SC16C2552B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

15. Legal information

15.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

malfunction of an NXP Semiconductors product can reasonably be expected

15.2 Deﬁnitions

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

15.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

16. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

SC16C2552B_3

Product data sheet

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SC16C2552B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

17. Contents

1

2

3

4

General description . . . . . . . . . . . . . . . . . . . . . . 1

13

14

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 34

Revision history . . . . . . . . . . . . . . . . . . . . . . . 35

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2

15

Legal information . . . . . . . . . . . . . . . . . . . . . . 37

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 37

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 37

15.1

15.2

15.3

15.4

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

16

17

Contact information . . . . . . . . . . . . . . . . . . . . 37

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

6

Functional description . . . . . . . . . . . . . . . . . . . 6

UART A-B functions . . . . . . . . . . . . . . . . . . . . . 6

Internal registers. . . . . . . . . . . . . . . . . . . . . . . . 7

FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . . 7

Time-out interrupts . . . . . . . . . . . . . . . . . . . . . . 7

Programmable baud rate generator . . . . . . . . . 8

DMA operation . . . . . . . . . . . . . . . . . . . . . . . . . 9

Loopback mode . . . . . . . . . . . . . . . . . . . . . . . . 9

6.1

6.2

6.3

6.4

6.5

6.6

6.7

7

7.1

Register descriptions . . . . . . . . . . . . . . . . . . . 11

Transmit Holding Register (THR) and Receive

Holding Register (RHR) . . . . . . . . . . . . . . . . . 12

Interrupt Enable Register (IER) . . . . . . . . . . . 12

IER versus Transmit/Receive FIFO

7.2

7.2.1

interrupt mode operation. . . . . . . . . . . . . . . . . 13

IER versus Receive/Transmit FIFO

7.2.2

polled mode operation . . . . . . . . . . . . . . . . . . 13

FIFO Control Register (FCR) . . . . . . . . . . . . . 14

DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Mode 0 (FCR bit 3 = 0). . . . . . . . . . . . . . . . . . 14

Mode 1 (FCR bit 3 = 1). . . . . . . . . . . . . . . . . . 14

FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Interrupt Status Register (ISR) . . . . . . . . . . . . 16

Line Control Register (LCR) . . . . . . . . . . . . . . 17

Modem Control Register (MCR) . . . . . . . . . . . 18

Line Status Register (LSR). . . . . . . . . . . . . . . 19

Modem Status Register (MSR). . . . . . . . . . . . 20

Scratchpad Register (SPR) . . . . . . . . . . . . . . 21

Alternate Function Register (AFR) . . . . . . . . . 21

SC16C2552B external reset condition . . . . . . 22

7.3

7.3.1

7.3.1.1

7.3.1.2

7.3.2

7.4

7.5

7.6

7.7

7.8

7.9

7.10

7.11

8

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 22

Static characteristics. . . . . . . . . . . . . . . . . . . . 23

Dynamic characteristics . . . . . . . . . . . . . . . . . 24

Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . 25

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 31

9

10

10.1

11

12

Soldering of SMD packages . . . . . . . . . . . . . . 32

Introduction to soldering . . . . . . . . . . . . . . . . . 32

Wave and reﬂow soldering . . . . . . . . . . . . . . . 32

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 32

Reﬂow soldering . . . . . . . . . . . . . . . . . . . . . . . 33

12.1

12.2

12.3

12.4

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 12 February 2009

Document identifier: SC16C2552B_3


型号：	SC16C2552BIA44
厂家：	NXP
描述：	5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs 5 V ， 3.3 V和2.5 V双UART ， 5兆比特/秒（最大），与16字节FIFO 微控制器和处理器串行IO控制器通信控制器外围集成电路先进先出芯片数据传输 PC 时钟
文件：	总38页 (文件大小：179K)
中文：	中文翻译
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