SC16C650BIB48,157_技术文档

SC16C650B

5 V, 3.3 V and 2.5 V UART with 32-byte FIFOs and infrared

(IrDA) encoder/decoder

Rev. 04 — 14 September 2009

Product data sheet

1. General description

The SC16C650B is a Universal Asynchronous Receiver and Transmitter (UART) used for

serial data communications. Its principal function is to convert parallel data into serial

data, and vice versa. The UART can handle serial data rates up to 3 Mbit/s.

The SC16C650B is pin compatible with the ST16C650A and it will power-up to be

functionally equivalent to the 16C450. Programming of control registers enables the

added features of the SC16C650B. Some of these added features are the 32-byte receive

and transmit FIFOs, automatic hardware or software ﬂow control and infrared

encoding/decoding. The selectable auto-ﬂow control feature signiﬁcantly reduces software

overload and increases system efﬁciency while in FIFO mode by automatically controlling

serial data ﬂow using RTS output and CTS input signals. The SC16C650B also provides

DMA mode data transfers through FIFO trigger levels and the RXRDY and TXRDY

signals. On-board status registers provide the user with error indications, operational

status, and modem interface control. System interrupts may be tailored to meet user

requirements. An internal loopback capability allows on-board diagnostics.

The SC16C650B operates at 5 V, 3.3 V and 2.5 V, and the industrial temperature range,

and is available in plastic PLCC44, LQFP48, and HVQFN32 packages.

2. Features

I Single channel

I 5 V, 3.3 V and 2.5 V operation

I 5 V tolerant on input only pins¹

I Industrial temperature range (−40 °C to +85 °C)

I After reset, all registers are identical to the typical 16C450 register set

I Capable of running with all existing generic 16C450 software

I Pin compatibility with the industry-standard ST16C450/550, TL16C450/550,

PC16C450/550. Software compatible with ST16C650.

I Up to 3 Mbit/s transmit/receive operation at 5 V, 2 Mbit/s at 3.3 V, and 1 Mbit/s at 2.5 V

I 32 byte transmit FIFO

I 32 byte receive FIFO with error ﬂags

I Programmable auto-RTS and auto-CTS

N In auto-CTS mode, CTS controls transmitter

N In auto-RTS mode, RX FIFO contents and threshold control RTS

I Automatic software/hardware ﬂow control

1. For data bus pins D7 to D0, see Table 26 “Limiting values”.

SC16C650B

NXP Semiconductors

UART with 32-byte FIFOs and IrDA encoder/decoder

I Programmable Xon/Xoff characters

I Software selectable baud rate generator

I Supports IrDA version 1.0 (up to 115.2 kbit/s)

I Four selectable Receive and Transmit FIFO interrupt trigger levels

I Standard modem interface or infrared IrDA encoder/decoder interface

I Sleep mode

I Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun Break)

I Independent receiver clock input

I Transmit, Receive, Line Status, and Data Set interrupts independently controlled

I Fully programmable character formatting:

N 5, 6, 7, or 8-bit characters

N Even, odd, or no-parity formats

N 1, 1¹⁄₂, or 2-stop bit

N Baud generation (DC to 3 Mbit/s)

I False start-bit detection

I Complete status reporting capabilities

I 3-state output TTL drive capabilities for bidirectional data bus and control bus

I Line break generation and detection

I Internal diagnostic capabilities:

N Loopback controls for communications link fault isolation

I Prioritized interrupt system controls

I Modem control functions (CTS, RTS, DSR, DTR, RI, DCD)

3. Ordering information

Table 1.

Ordering information

Industrial: V_CC= 2.5 V, 3.3 V or 5 V ± 10 %; T_amb= −40 °C to +85 °C.

Type number

Package

Name

Description

Version

SC16C650BIA44 PLCC44

SC16C650BIB48 LQFP48

plastic leaded chip carrier; 44 leads

plastic low proﬁle quad ﬂat package; 48 leads; body 7 × 7 × 1.4 mm

SOT187-2

SOT313-2

SOT617-1

SC16C650BIBS

HVQFN32 plastic thermal enhanced very thin quad ﬂat package; no leads;

32 terminals; body 5 × 5 × 0.85 mm

SC16C650B_4

Product data sheet

Rev. 04 — 14 September 2009

2 of 48

SC16C650B

NXP Semiconductors

UART with 32-byte FIFOs and IrDA encoder/decoder

4. Block diagram

SC16C650B

TRANSMIT

FIFO

TRANSMIT

SHIFT

TX

REGISTERS

REGISTER

D0 to D7

IOR, IOR

IOW, IOW

RESET

DATA BUS

AND

CONTROL

LOGIC

FLOW

CONTROL

LOGIC

IR

ENCODER

RECEIVE

FIFO

RECEIVE

SHIFT

RX

REGISTERS

REGISTER

FLOW

CONTROL

LOGIC

IR

DECODER

REGISTER

SELECT

LOGIC

A0 to A2

CS0, CS1, CS2

AS

DDIS

DTR

RTS

OUT1, OUT2

MODEM

CONTROL

LOGIC

INT

TXRDY

RXRDY

CTS

RI

DCD

DSR

INTERRUPT

CONTROL

LOGIC

CLOCK AND

BAUD RATE

GENERATOR

002aaa602

XTAL1

RCLK

XTAL2

BAUDOUT

Fig 1. Block diagram

SC16C650B_4

Product data sheet

Rev. 04 — 14 September 2009

3 of 48

SC16C650B

NXP Semiconductors

UART with 32-byte FIFOs and IrDA encoder/decoder

5. Pinning information

5.1 Pinning

7

39

38

37

36

35

34

33

32

31

30

29

D5

D6

RESET

OUT1

DTR

RTS

OUT2

n.c.

8

9

D7

10

11

12

13

14

15

16

17

RCLK

RX

n.c.

SC16C650BIA44

TX

INT

CS0

RXRDY

A0

CS1

CS2

A1

BAUDOUT

A2

002aaa603

Fig 2. Pin conﬁguration for PLCC44

1

2

36

35

34

33

32

31

30

29

28

27

26

25

n.c.

D5

n.c.

RESET

OUT1

DTR

RTS

OUT2

INT

3

D6

4

D7

5

RCLK

n.c.

6

SC16C650BIB48

7

RX

8

TX

RXRDY

A0

9

CS0

10

11

12

CS1

A1

CS2

A2

BAUDOUT

n.c.

002aaa604

Fig 3. Pin conﬁguration for LQFP48

SC16C650B_4

Product data sheet

Rev. 04 — 14 September 2009

4 of 48

SC16C650B

NXP Semiconductors

UART with 32-byte FIFOs and IrDA encoder/decoder

terminal 1

index area

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

D5

RESET

OUT

DTR

RTS

INT

D6

D7

RCLK

RX

SC16C650BIBS

TX

RXRDY

A0

CS

BAUDOUT

A1

002aaa947

Transparent top view

Fig 4. Pin conﬁguration for HVQFN32

5.2 Pin description

Table 2.

Symbol

Pin description

Type

Description

PLCC44 LQFP48 HVQFN32

A0

A1

A2

31

30

29

28

27

26

18

17

16

I

Register select. A0 to A2 are sued during read and write

operations to select the UART register to read from or write to.

Refer to Table 3 for register addresses and refer to signal AS

description.

AS

28

24

-

I

Address strobe. When AS is active (LOW), A0, A1 and A2 and

CS0 CS1 and CS2 drive the internal select logic directly. When AS

is HIGH, the register select and chip select signals are held at the

logic levels they were in when the LOW-to-HIGH transition of AS

occurred.

BAUDOUT 17

12

8

O

Baud out. BAUDOUT is a 16× clock signal for the transmitter

section of the UART. The clock rate is established by the reference

oscillator frequency divided by a divisor speciﬁed in the baud

generator divisor latches. BAUDOUT may also be used for the

receiver section by tying this output to RCLK.

CS0

CS1

CS2

CS

14

15

16

-

9

-

I

Chip select. When CS0 and CS1 are HIGH and CS2 is LOW, these

3 inputs select the UART. When any of these inputs are inactive, the

UART remains inactive (refer to AS description).

10

11

-

7

25

CTS

40

38

Clear to send. CTS is a modem status signal. Its condition can be

checked by reading bit 4 (CTS) of the Modem Status Register

(MSR). MSR[0] (∆CTS) indicates that CTS has changed states

since the last read from the MSR. If the modem status interrupt is

enabled when CTS changes levels and the auto-CTS mode is not

enabled, an interrupt is generated. CTS is also used in the

auto-CTS mode to control the transmitter.

SC16C650B_4

Product data sheet

Rev. 04 — 14 September 2009

5 of 48

SC16C650B

NXP Semiconductors

UART with 32-byte FIFOs and IrDA encoder/decoder

Table 2.

Symbol

Pin description …continued

Type

Description

PLCC44 LQFP48 HVQFN32

D0

D1

D2

D3

D4

D5

D6

D7

DCD

2

43

44

45

46

47

2

28

29

30

31

32

1

I/O

I

Data bus. Eight data lines with 3-state outputs provide a

bidirectional path for data, control and status information between

the UART and the CPU.

3

4

5

6

7

8

3

2

9

4

3

42

40

-

Data carrier detect. DCD is a modem status signal. Its condition

can be checked by reading MSR[7] (DCD). MSR[3] (∆DCD)

indicates that DCD has changed states since the last read from the

MSR. If the modem status interrupt is enabled when DCD changes

levels, an interrupt is generated.

DDIS

DSR

26

41

22

39

-

O

I

Driver disable. DDIS is active (LOW) when the CPU is reading

data. When inactive (HIGH), DDIS can disable an external

transceiver.

26

Data set ready. DSR is a modem status signal. Its condition can be

checked by reading MSR[5] (DSR). MSR[1] (∆DSR) indicates DSR

has changed levels since the last read from the MSR. If the modem

status interrupt is enabled when DSR changes levels, an interrupt is

generated.

DTR

INT

37

33

30

22

20

O

Data terminal ready. When active (LOW), DTR informs a modem

or data set that the UART is ready to establish communication. DTR

is placed in the active level by setting the DTR bit of the Modem

Control Register. DTR is placed in the inactive level either as a

result of a Master Reset, during loopback mode operation, or

clearing the DTR bit.

Interrupt. When active (HIGH), INT informs the CPU that the UART

has an interrupt to be serviced. Four conditions that cause an

interrupt to be issued are: a receiver error, received data that is

available or timed out (FIFO mode only), an empty transmitter

holding register or an enabled modem status interrupt. INT is reset

(deactivated) either when the interrupt is serviced or as a result of a

Master Reset.

OUT1

OUT2

OUT

38

35

-

34

31

-

O

Outputs 1 and 2. These are user-designated output terminals that

are set to the active (low) level by setting respective Modem Control

Register (MCR) bits (OUT1 and OUT2). OUT1 and OUT2 are set to

the inactive (HIGH) level as a result of Master Reset, during

loopback mode operations, or by clearing bit 2 (OUT1) or bit 3

(OUT2) of the MCR.

-

23

RCLK

10

5

4

I

Receiver clock. RCLK is the 16× baud rate clock for the receiver

section of the UART.

IOR

25

24

20

19

-

I

Read inputs. When either IOR or IOR is active (LOW or HIGH,

respectively) while the UART is selected, the CPU is allowed to

read status information or data from a selected UART register. Only

one of these inputs is required for the transfer of data during a read

operation; the other input should be tied to its inactive level (i.e.,

IOR tied LOW or IOR tied HIGH).

14

SC16C650B_4

Product data sheet

Rev. 04 — 14 September 2009

6 of 48

SC16C650B

NXP Semiconductors

UART with 32-byte FIFOs and IrDA encoder/decoder

Table 2.

Symbol

Pin description …continued

Type

Description

PLCC44 LQFP48 HVQFN32

RESET

RI

39

35

24

I

Master Reset. When active (HIGH), MR clears most UART

registers and sets the levels of various output signals.

43

41

-

Ring indicator. RI is a modem status signal. Its condition can be

checked by reading MSR[6] (RI). MSR[2] (∆RI) indicates that RI has

changed from a LOW to a HIGH level since the last read from the

MSR. If the modem status interrupt is enabled when this transition

occurs, an interrupt is generated.

RTS

36

32

29

21

19

O

Request to send. When active, RTS informs the modem or data

set that the UART is ready to receive data. RTS is set to the active

level by setting the RTS modem control register bit and is set to the

inactive (HIGH) level either as a result of a Master Reset or during

loopback mode operations or by clearing bit 1 (RTS) of the MCR. In

the auto-RTS mode, RTS is set to the inactive level by the receiver

threshold control logic.

RXRDY

Receiver ready. Receiver direct memory access (DMA) signaling is

available with RXRDY. When operating in the FIFO mode, one of

two types of DMA signaling can be selected using the FIFO Control

Register bit 3 (FCR[3]). When operating in the 16C450 mode, only

DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in

which a transfer is made between CPU bus cycles. Mode 1

supports multi-transfer DMA in which multiple transfers are made

continuously until the receiver FIFO has been emptied. In DMA

mode 0 (FCR[0] = 0 or FCR[0] = 1, FCR[3] = 0), when there is at

least one character in the receiver FIFO or Receive Holding

Register, RXRDY is active (LOW). When RXRDY has been active

but there are no characters in the FIFO or holding register, RXRDY

goes inactive (HIGH). In DMA mode 1 (FCR[0] = 1, FCR[3] = 1),

when the trigger level or the time-out has been reached, RXRDY

goes active (LOW); when it has been active but there are no more

characters in the FIFO or holding register, it goes inactive (HIGH).

RX

TX

11

13

7

8

5

6

I

Serial data input. RX is serial data input from a connected

communications device.

O

Serial data output. TX is composite serial data output to a

connected communication device. TX is set to the marking (HIGH)

level as a result of Master Reset.

TXRDY

27

23

15

O

Transmitter ready. Transmitter DMA signaling is available with

TXRDY. When operating in the FIFO mode, one of two types of

DMA signaling can be selected using FCR[3]. When operating in

the 16C450 mode, only DMA mode 0 is allowed. Mode 0 supports

single-transfer DMA in which a transfer is made between CPU bus

cycles. Mode 1 supports multi-transfer DMA in which multiple

transfers are made continuously until the transmit FIFO has been

ﬁlled.

V_CC

44

22

21

20

42

18

17

16

27

13^[1]

-

power 2.5 V, 3 V or 5 V supply voltage.

power Ground voltage.

GND

IOW

I

Write inputs. When either IOW or IOW is active (LOW or HIGH,

respectively) and while the UART is selected, the CPU is allowed to

write control words or data into a selected UART register. Only one

of these inputs is required to transfer data during a write operation;

the other input should be tied to its inactive level (i.e., IOW tied LOW

or IOW tied HIGH).

11

SC16C650B_4

Product data sheet

Rev. 04 — 14 September 2009

7 of 48

SC16C650B

NXP Semiconductors

UART with 32-byte FIFOs and IrDA encoder/decoder

Table 2.

Symbol

Pin description …continued

Type

Description

PLCC44 LQFP48 HVQFN32

XTAL1

XTAL2^[2]

18

19

14

15

9

I

Crystal connection or external clock input.

10

O

Crystal connection or the inversion of XTAL1 if XTAL1 is

driven.

n.c.

1, 12, 23, 1, 6, 13, 12

-

not connected

34

21, 25,

36, 37,

48

[1] HVQFN32 package die supply ground is connected to both GND pin and exposed center pad. GND pin must be connected to supply

ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be

soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias

need to be incorporated in the PCB in the thermal pad region.

[2] In Sleep mode, XTAL2 is left ﬂoating.

6. Functional description

The SC16C650B provides serial asynchronous receive data synchronization,

parallel-to-serial and serial-to-parallel data conversions for both the transmitter and

receiver sections. These functions are necessary for converting the serial data stream into

parallel data that is required with digital data systems. Synchronization for the serial data

stream is accomplished by adding start and stop bits to the transmit data to form a data

character (character orientated protocol). Data integrity is insured by attaching a parity bit

to the data character. The parity bit is checked by the receiver for any transmission bit

errors. The SC16C650B is fabricated with an advanced CMOS process to achieve low

drain power and high speed requirements.

The SC16C650B is an upward solution that provides 32 bytes of transmit and receive

FIFO memory, instead of none in the 16C450, or 16 bytes in the 16C550. The

SC16C650B is designed to work with high speed modems and shared network

environments that require fast data processing time. Increased performance is realized in

the SC16C650B by the larger transmit and receive FIFOs. This allows the external

processor to handle more networking tasks within a given time. In addition, the four

selectable levels of FIFO trigger interrupt and automatic hardware/software ﬂow control is

uniquely provided for maximum data throughput performance, especially when operating

in a multi-channel environment. The combination of the above greatly reduces the

bandwidth requirement of the external controlling CPU, increases performance, and

reduces power consumption.

The SC16C650B is capable of operation up to 3 Mbit/s with a 48 MHz external clock input

(at 5 V).

The rich feature set of the SC16C650B is available through internal registers. Automatic

hardware/software ﬂow control, selectable transmit and receive FIFO trigger level,

selectable TX and RX baud rates, modem interface controls, and a Sleep mode are some

of these features.

SC16C650B_4

Product data sheet

Rev. 04 — 14 September 2009

8 of 48

SC16C650B

NXP Semiconductors

UART with 32-byte FIFOs and IrDA encoder/decoder

6.1 Internal registers

The SC16C650B provides 17 internal registers for monitoring and control. These registers

are shown in Table 3. Twelve registers are similar to those already available in the

standard 16C550. These registers function as data holding registers (THR/RHR), interrupt

status and control registers (IER/ISR), a FIFO control register (FCR), line status and

control registers (LCR/LSR), modem status and control registers (MCR/MSR),

programmable data rate (clock) control registers (DLL/DLM), and a user accessible

ScratchPad Register (SPR). Beyond the general 16C550 features and capabilities, the

SC16C650B offers an enhanced feature register set (EFR, Xon1/Xoff1, Xon2/Xoff2) that

provides on-board hardware/software ﬂow control. Register functions are more fully

described in the following paragraphs.

Table 3.

A2

Internal registers decoding

A0 Read mode

A1

Write mode

General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LCR/LSR, SPR)^[1]

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Receive Holding Register

Interrupt Enable Register

Interrupt Status Register

Line Control Register

Modem Control Register

Line Status Register

Transmit Holding Register

Interrupt Enable Register

FIFO Control Register

Line Control Register

Modem Control Register

n/a

Modem Status Register

n/a

Scratchpad Register

Baud rate register set (DLL/DLM)^[2]

0

LSB of Divisor Latch

MSB of Divisor Latch

0

1

MSB of Divisor Latch

Enhanced register set (EFR, Xon1, Xoff1, Xon2, Xoff2)^[3]

0

1

0

1

0

1

0

1

Enhanced Feature Register

Xon1 word

Enhanced Feature Register

Xon1 word

Xon2 word

Xoff1 word

Xoff2 word

[1] These registers are accessible only when LCR[7] is a logic 0.

[2] These registers are accessible only when LCR[7] is a logic 1.

[3] Enhanced Feature Register, Xon1, Xon2 and Xoff1, Xoff2 are accessible only when the LCR is set to BFh.

6.2 FIFO operation

The 32-byte transmit and receive data FIFOs are enabled by the FIFO Control Register

bit 0 (FCR[0]). With 16C550 devices, the user can set the receive trigger level, but not the

transmit trigger level. The SC16C650B provides independent trigger levels for both

receiver and transmitter. To remain compatible with SC16C550, the transmit interrupt

trigger level is set to 16 following a reset. It should be noted that the user can set the

transmit trigger levels by writing to the FCR register, but activation will not take place until

EFR[4] is set to a logic 1. The receiver FIFO section includes a time-out function to ensure

SC16C650B_4

Product data sheet

Rev. 04 — 14 September 2009

9 of 48

SC16C650B

NXP Semiconductors

UART with 32-byte FIFOs and IrDA encoder/decoder

data is delivered to the external CPU. An interrupt is generated whenever the Receive

Holding Register (RHR) has not been read following the loading of a character or the

receive trigger level has not been reached.

Table 4.

Flow control mechanism

Selected trigger level

(characters)

INT pin activation

Negate RTS or

send Xoff

Assert RTS or

send Xon

8

0

16

24

28

16

24

28

16

24

28

7

15

23

6.3 Hardware ﬂow control

When automatic hardware ﬂow control is enabled, the SC16C650B monitors the CTS pin

for a remote buffer overﬂow indication and controls the RTS pin for local buffer overﬂows.

Automatic hardware ﬂow control is selected by setting EFR[6] (RTS) and EFR[7] (CTS) to

a logic 1. If CTS changes from a logic 0 to a logic 1 indicating a ﬂow control request,

ISR[5] will be set to a logic 1 (if enabled via IER[6,7]), and the SC16C650B will suspend

TX transmissions as soon as the stop bit of the character in process is shifted out.

Transmission is resumed after the CTS input returns to a logic 0, indicating more data may

be sent.

With the auto-RTS function enabled, an interrupt is generated when the receive FIFO

reaches the programmed trigger level. The RTS pin will not be forced to a logic 1 (RTS

off), until the receive FIFO reaches the next trigger level. However, the RTS pin will return

to a logic 0 after the data buffer (FIFO) is unloaded to the next trigger level below the

programmed trigger level. However, under the above described conditions, the

SC16C650B will continue to accept data until the receive FIFO is full.

6.4 Software ﬂow control

When software ﬂow control is enabled, the SC16C650B compares one or two sequential

receive data characters with the programmed Xon or Xoff character value(s). If received

character(s) match the programmed Xoff values, the SC16C650B will halt transmission

(TX) as soon as the current character(s) has completed transmission. When a match

occurs, the receive ready (if enabled via Xoff IER[5]) ﬂags will be set and the interrupt

output pin (if receive interrupt is enabled) will be activated. Following a suspension due to

a match of the Xoff characters’ values, the SC16C650B will monitor the receive data

stream for a match to the Xon1, Xon2 character value(s). If a match is found, the

SC16C650B will resume operation and clear the ﬂags (ISR[4]).

Reset initially sets the contents of the Xon/Xoff 8-bit ﬂow control registers to a logic 0.

Following reset, the user can write any Xon/Xoff value desired for software ﬂow control.

Different conditions can be set to detect Xon/Xoff characters and suspend/resume

transmissions. When double 8-bit Xon/Xoff characters are selected, the SC16C650B

compares two consecutive receive characters with two software ﬂow control 8-bit values

(Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under the above

described ﬂow control mechanisms, ﬂow control characters are not placed (stacked) in the

user accessible RX data buffer or FIFO. When using a software ﬂow control the Xon/Xoff

characters cannot be used for data transfer.

SC16C650B_4

Product data sheet

Rev. 04 — 14 September 2009

10 of 48

SC16C650B

NXP Semiconductors

UART with 32-byte FIFOs and IrDA encoder/decoder

In the event that the receive buffer is overﬁlling and ﬂow control needs to be executed, the

SC16C650B automatically sends an Xoff message (when enabled) via the serial TX

output to the remote modem. The SC16C650B sends the Xoff1/Xoff2 characters as soon

as received data passes the programmed trigger level. To clear this condition, the

SC16C650B will transmit the programmed Xon1/Xon2 characters as soon as receive data

drops below the next low or programmed trigger level.

6.5 Special feature software ﬂow control

A special feature is provided to detect an 8-bit character when EFR[5] is set. When 8-bit

character is detected, it will be placed on the user-accessible data stack along with normal

incoming RX data. This condition is selected in conjunction with EFR[3:0]. Note that

software ﬂow control should be turned off when using this special mode by setting

EFR[3:0] to a logic 0.

The SC16C650B compares each incoming receive character with Xoff2 data. If a match

exists, the received data will be transferred to the FIFO, and ISR[4] will be set to indicate

detection of a special character. Although Table 8 “SC16C650B internal registers” shows

each X-register with eight bits of character information, the actual number of bits is

dependent on the programmed word length. Line Control Register bits LCR[1:0] deﬁne the

number of character bits, i.e., either 5 bits, 6 bits, 7 bits or 8 bits. The word length selected

by LCR[1:0] also determine the number of bits that will be used for the special character

comparison. Bit 0 in the X-registers corresponds with the LSB bit for the receive character.

6.6 Hardware/software and time-out interrupts

Three special interrupts have been added to monitor the hardware and software ﬂow

control. The interrupts are enabled by IER[7:5]. Care must be taken when handling these

interrupts. Following a reset, the transmitter interrupt is enabled, the SC16C650B will

issue an interrupt to indicate that the Transmit Holding Register is empty. This interrupt

must be serviced prior to continuing operations. The ISR register provides the current

singular highest priority interrupt only. It could be noted that CTS and RTS interrupts have

lowest interrupt priority. A condition can exist where a higher priority interrupt may mask

the lower priority CTS/RTS interrupt(s). Only after servicing the higher pending interrupt

will the lower priority CTS/RTS interrupt(s) be reﬂected in the status register. Servicing the

interrupt without investigating further interrupt conditions can result in data errors.

When two interrupt conditions have the same priority, it is important to service these

interrupts correctly. Receive Data Ready and Receive Time-Out have the same interrupt

priority (when enabled by IER[0]). The receiver issues an interrupt after the number of

characters have reached the programmed trigger level. In this case, the SC16C650B

FIFO may hold more characters than the programmed trigger level. Following the removal

of a data byte, the user should re-check LSR[0] for additional characters. A Receive

Time-Out will not occur if the receive FIFO is empty. The time-out counter is reset at the

center of each stop bit received or each time the Receive Holding Register (RHR) is read.

The actual time-out value is 4 character time.

SC16C650B_4

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SC16C650B

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UART with 32-byte FIFOs and IrDA encoder/decoder

6.7 Programmable baud rate generator

The SC16C650B supports high speed modem technologies that have increased input

data rates by employing data compression schemes. For example, a 33.6 kbit/s modem

that employs data compression may require a 115.2 kbit/s input data rate. A 128.0 kbit/s

ISDN modem that supports data compression may need an input data rate of 460.8 kbit/s.

A single baud rate generator is provided for the transmitter and receiver, allowing

independent TX/RX channel control. The programmable baud rate generator is capable of

accepting an input clock up to 48 MHz, as required for supporting a 3 Mbit/s data rate.

The SC16C650B can be conﬁgured for internal or external clock operation. For internal

clock oscillator operation, an industry standard microprocessor crystal (parallel resonant,

22 pF to 33 pF load) is connected externally between the XTAL1 and XTAL2 pins (see

Figure 5). Alternatively, an external clock can be connected to the XTAL1 pin to clock the

internal baud rate generator for standard or custom rates (see Table 5).

XTAL1

XTAL2

XTAL1

XTAL2

1.5 kΩ

X1

1.8432 MHz

C1

22 pF

C2

33 pF

C1

22 pF

C2

47 pF

002aaa870

Fig 5. Crystal oscillator connection

The generator divides the input 16× clock by any divisor from 1 to (2¹⁶− 1). The

SC16C650B divides the basic crystal or external clock by 16. The frequency of the

BAUDOUT output pin is exactly 16× (16 times) the selected baud rate

(BAUDOUT = 16 × baud rate). Customized baud rates can be achieved by selecting the

proper divisor values for the MSB and LSB sections of baud rate generator.

Setting MCR[7] to a logic 1 provides an additional divide-by-4, whereas setting MCR[7] to

a logic 0 only divides by 1 (see Table 5 and Figure 6).

Programming the baud rate generator registers DLM (MSB) and DLL (LSB) provides a

user capability for selecting the desired ﬁnal baud rate. The example in Table 5 shows

selectable baud rates when using a 1.8432 MHz crystal and setting MCR[7] to a logic 0.

For custom baud rates, the divisor value can be calculated using Equation 1:

XTAL1 clock frequency

serial data rate × 16

divisor (in decimal) =

(1)

----------------------------------------------------------------

SC16C650B_4

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SC16C650B

NXP Semiconductors

UART with 32-byte FIFOs and IrDA encoder/decoder

Table 5.

Baud rates using 1.8432 MHz or 3.072 MHz crystal

Using 3.072 MHz crystal

Using 1.8432 MHz crystal

Desired

baud rate

Divisor for

16× clock

Baud rate

error

Desired

baud rate

Divisor for

16× clock

Baud rate

error

50

2304

1536

1047

857

768

384

192

96

50

3840

2560

1745

1428

1280

640

320

160

107

96

75

110

0.026

0.058

110

0.026

0.034

134.5

150

134.5

150

300

600

1200

1800

2000

2400

3600

4800

7200

9600

19200

38400

56000

1200

1800

2000

2400

3600

4800

7200

9600

19200

38400

64

0.312

58

0.69

48

80

32

53

0.628

1.23

24

40

16

27

12

20

6

10

3

5

2

2.86

MCR[7] = 0

DIVIDE-BY-1

LOGIC

XTAL1

XTAL2

CLOCK

OSCILLATOR

LOGIC

BAUD RATE

GENERATOR

LOGIC

BAUDOUT

002aaa208

DIVIDE-BY-4

LOGIC

MCR[7] = 1

Fig 6. Baud rate generator circuitry

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UART with 32-byte FIFOs and IrDA encoder/decoder

6.8 DMA operation

The SC16C650B FIFO trigger level provides additional ﬂexibility to the user for block

mode operation. The user can optionally operate the transmit and receive FIFOs in the

DMA mode (FCR[3]). The DMA mode affects the state of the RXRDY and TXRDY output

pins. Table 6 and Table 7 show this.

Remark: DMA operation is not supported in the HVQFN32 package.

Table 6.

Effect of DMA mode on state of RXRDY pin

Non-DMA mode

DMA mode

1 = FIFO empty

0-to-1 transition when FIFO empties

1-to-0 transition when FIFO reaches trigger level, or time-out occurs

0 = at least 1 byte in FIFO

Table 7.

Effect of DMA mode on state of TXRDY pin

Non-DMA mode

1 = at least 1 byte in FIFO

0 = FIFO empty

DMA mode

0-to-1 transition when FIFO becomes full

1-to-0 transition when FIFO has 1 empty space

6.9 Sleep mode

The SC16C650B is designed to operate with low power consumption. A special Sleep

mode is included to further reduce power consumption when the chip is not being used.

With EFR[4] and IER[4] enabled (set to a logic 1), the SC16C650B enters the Sleep

mode, but resumes normal operation when a start bit is detected, a change of state on

any of the modem input pins RI, CTS, DSR, DCD, RX pin, or a transmit data is provided

by the user. If the Sleep mode is enabled and the SC16C650B is awakened by one of the

conditions described above, it will return to the Sleep mode automatically after the last

character is transmitted or read by the user. In any case, the Sleep mode will not be

entered while an interrupt(s) is pending. The SC16C650B will stay in the Sleep mode of

operation until it is disabled by setting IER[4] to a logic 0.

6.10 Loopback mode

The internal loopback capability allows on-board diagnostics. In the loopback mode, the

normal modem interface pins are disconnected and reconﬁgured for loopback internally.

MCR[3:0] register bits are used for controlling loopback diagnostic testing. In the loopback

mode, OUT1 (bit 2) and OUT2 (bit 3) in the MCR register control the modem RI and DCD

inputs, respectively. MCR signals DTR (bit 0) and RTS (bit 1) are used to control the

modem DSR and CTS inputs, respectively. The transmitter output (TX) and the receiver

input (RX) are disconnected from their associated interface pins, and instead are

connected together internally (see Figure 7). The CTS, DSR, DCD, and RI are

disconnected from their normal modem control input pins, and instead are connected

internally to DTR, RTS, OUT1 and OUT2. Loopback test data is entered into the Transmit

Holding Register via the user data bus interface, D0 to D7. The transmit UART serializes

the data and passes the serial data to the receive UART via the internal loopback

connection. The receive UART converts the serial data back into parallel data that is then

made available at the user data interface D0 to D7. The user optionally compares the

received data to the initial transmitted data for verifying error-free operation of the UART

TX/RX circuits.

SC16C650B_4

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UART with 32-byte FIFOs and IrDA encoder/decoder

In this mode, the receiver and transmitter interrupts are fully operational. The Modem

Control Interrupts are also operational. However, the interrupts can only be read using

lower four bits of the Modem Status Register (MSR[3:0]) instead of the four Modem Status

Register bits 7:4. The interrupts are still controlled by the IER.

SC16C650B

TRANSMIT

FIFO

TRANSMIT

SHIFT

TX

REGISTERS

REGISTER

D0 to D7

IOR, IOR

IOW, IOW

RESET

DATA BUS

AND

CONTROL

LOGIC

FLOW

CONTROL

LOGIC

IR

ENCODER

MCR[4] = 1

RECEIVE

FIFO

REGISTERS

RECEIVE

SHIFT

REGISTER

RX

FLOW

CONTROL

LOGIC

IR

DECODER

REGISTER

SELECT

LOGIC

A0 to A2

CS0, CS1, CS2

AS

RTS

DDIS

CTS

DTR

MODEM

CONTROL

LOGIC

DSR

OUT1

INT

TXRDY

RXRDY

INTERRUPT

CONTROL

LOGIC

CLOCK AND

BAUD RATE

GENERATOR

RI

OUT2

DCD

002aaa606

XTAL2

BAUDOUT

XTAL1

RCLK

Fig 7. Internal loopback mode diagram

SC16C650B_4

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UART with 32-byte FIFOs and IrDA encoder/decoder

7. Register descriptions

Table 8 details the assigned bit functions for the seventeen SC16C650B internal registers.

The assigned bit functions are more fully deﬁned in Section 7.1 through Section 7.11.

Table 8.

SC16C650B internal registers

A2 A1 A0 Register Default Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

[1]

General register set^[2]

0

1

RHR

THR

IER

XX

00

bit 7

CTS

bit 6

RTS

bit 5

Xoff

bit 4

bit 3

bit 2

bit 1

bit 0

bit 4

bit 2

Sleep

modem

status

interrupt

receive

transmit receive

interrupt interrupt interrupt mode^[3]

linestatus holding holding

interrupt register register

[3]

0

1

0

1

FCR

ISR

00

01

00

RCVR

trigger

(MSB)

RCVR

trigger

(LSB)

TX

trigger

(MSB)^[3](LSB)^[3]

TX

trigger

DMA mode XMIT

RCVR

FIFO

reset

FIFO

enable

select^[4]

FIFO

reset

FIFOs

INT

priority

bit 3

INT priority INT

INT

enabled enabled priority

bit 4

bit 2

priority

bit 1

priority status

bit 0

LCR

divisor

latch

enable

set

break

set parity even

parity

enable

stop bits word

length

word

length

bit 0

bit 1

1

0

1

MCR

LSR

00

60

Clock

IR

INT type loopback OUT2^[5]

OUT1,

OUT^[6]

RTS

DTR

select^[3]enable^[3]select^[3]

FIFO

data

error

trans.

empty

trans.

break

framing

parity

error

overrun receive

error

holding

empty

interrupt error

data

ready

1

0

1

MSR

SPR

X0

FF

DCD

bit 7

RI

DSR

bit 5

CTS

bit 4

∆DCD

∆RI

∆DSR

∆CTS

bit 6

bit 3

bit 2

bit 1

bit 0

Special register set^[7]

0

DLL

XX

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 9

bit 0

bit 8

0

1

DLM

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

Enhanced register set^[8]

0

1

0

EFR

00

Auto

CTS

Auto

RTS

Special

char.

select

Enable

Cont-3

Cont-2

Tx, Rx

control

Cont-1

Tx, Rx

control

Cont-0

Tx, Rx

control

IER[4:7], Tx, Rx

ISR[4,5], control

FCR[4,5],

MCR[5:7]

1

0

1

0

1

0

1

Xon1

Xon2

Xoff1

Xoff2

00

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 9

bit 1

bit 9

bit 0

bit 8

bit 0

bit 8

bit 15

bit 7

bit 14

bit 6

bit 13

bit 5

bit 12

bit 4

bit 11

bit 3

bit 10

bit 2

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

[1] The value shown represents the register’s initialized HEX value; X = n/a.

[2] These registers are accessible only when LCR[7] = 0.

[3] These bits are only accessible when EFR[4] is set.

[4] This function is not supported in the HVQFN32 package, and should not be written.

[5] OUT2 pin is not supported in the HVQFN32 package, and this bit should not be written.

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[6] This bit controls the OUT pin in the HVQFN32 package, and OUT1 in the other packages.

[7] The Special register set is accessible only when LCR[7] is set to a logic 1.

[8] Enhanced Feature Register (EFR), Xon1, Xon2 Xoff1, Xoff2 are accessible only when LCR is set to BFh.

7.1 Transmit Holding Register (THR) and Receive Holding Register (RHR)

The serial transmitter section consists of an 8-bit Transmit Holding Register (THR) and

Transmit Shift Register (TSR). The status of the THR is provided in the Line Status

Register (LSR). Writing to the THR transfers the contents of the data bus (D[7:0]) to the

THR, providing that the THR or TSR is empty. The THR empty ﬂag in the LSR register will

be set to a logic 1 when the transmitter is empty or when data is transferred to the TSR.

Note that a write operation can be performed when the THR empty ﬂag is set

(logic 0 = FIFO full; logic 1 = at least one FIFO location available).

The serial receive section also contains an 8-bit Receive Holding Register (RHR).

Receive data is removed from the SC16C650B and receive FIFO by reading the RHR

register. The receive section provides a mechanism to prevent false starts. On the falling

edge of a start or false start bit, an internal receiver counter starts counting clocks at the

16× clock rate. After 7¹⁄₂clocks, the start bit time should be shifted to the center of the

start bit. At this time the start bit is sampled, and if it is still a logic 0 it is validated.

Evaluating the start bit in this manner prevents the receiver from assembling a false

character. Receiver status codes will be posted in the LSR.

7.2 Interrupt Enable Register (IER)

The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter

empty, line status and modem status registers. These interrupts would normally be seen

on the INT output pin.

Table 9.

Interrupt Enable Register bits description

Description

Bit

Symbol

IER[7]

7

CTS interrupt.

logic 0 = disable the CTS interrupt (normal default condition)

logic 1 = enable the CTS interrupt. The SC16C650B issues an interrupt when

the CTS pin transitions from a logic 0 to a logic 1.

6

5

IER[6]

IER[5]

RTS interrupt.

logic 0 = disable the RTS interrupt (normal default condition)

logic 1 = enable the RTS interrupt. The SC16C650B issues an interrupt when

the RTS pin transitions from a logic 0 to a logic 1.

Xoff interrupt.

logic 0 = disable the software ﬂow control, receive Xoff interrupt (normal

default condition).

logic 1 = enable the software ﬂow control, receive Xoff interrupt. See Section

6.4 “Software ﬂow control” for details.

4

3

IER[4]

IER[3]

Sleep mode.

logic 0 = disable Sleep mode (normal default condition)

logic 1 = enable Sleep mode. See Section 6.9 “Sleep mode” for details.

Modem Status Interrupt.

logic 0 = disable the modem status register interrupt (normal default

condition)

logic 1 = enable the modem status register interrupt

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UART with 32-byte FIFOs and IrDA encoder/decoder

Table 9.

Interrupt Enable Register bits description …continued

Bit

Symbol

Description

2

IER[2]

Receive Line Status interrupt. This interrupt will be issued whenever a fully

assembled receive character is transferred from RSR to the RHR/FIFO, i.e.,

data ready, LSR[0].

logic 0 = disable the receiver line status interrupt (normal default condition)

logic 1 = enable the receiver line status interrupt

1

0

IER[1]

IER[0]

Transmit Holding Register interrupt. This interrupt will be issued whenever the

THR is empty, and is associated with LSR[1].

logic 0 = disable the transmitter empty interrupt (normal default condition)

logic 1 = enable the transmitter empty interrupt

Receive Holding Register interrupt. This interrupt will be issued when the FIFO

has reached the programmed trigger level, or is cleared when the FIFO drops

below the trigger level in the FIFO mode of operation.

logic 0 = disable the receiver ready interrupt (normal default condition)

logic 1 = enable the receiver ready interrupt

7.2.1 IER versus receive FIFO interrupt mode operation

When the receive FIFO (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1) are

enabled, the receive interrupts and register status will reﬂect the following:

• The receive data available interrupts are issued to the external CPU when the FIFO

has reached the programmed trigger level. It will be cleared when the FIFO drops

below the programmed trigger level.

• FIFO status will also be reﬂected in the user accessible ISR register when the FIFO

trigger level is reached. Both the ISR register status bit and the interrupt will be

cleared when the FIFO drops below the trigger level.

• The data ready bit (LSR[0]) is set as soon as a character is transferred from the shift

register to the receive FIFO. It is reset when the FIFO is empty.

7.2.2 IER versus receive/transmit FIFO polled mode operation

When FCR[0] = logic 1, resetting IER[3:0] enables the SC16C650B in the FIFO polled

mode of operation. Since the receiver and transmitter have separate bits in the LSR,

either or both can be used in the polled mode by selecting respective transmit or receive

control bit(s).

• LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.

• LSR[4:1] will provide the type of errors encountered, if any.

• LSR[5] will indicate when the transmit FIFO is empty.

• LSR[6] will indicate when both the transmit FIFO and transmit shift register are empty.

• LSR[7] will indicate any FIFO data errors.

SC16C650B_4

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SC16C650B

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UART with 32-byte FIFOs and IrDA encoder/decoder

7.3 FIFO Control Register (FCR)

This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger

levels, and select the DMA mode.

7.3.1 DMA mode

7.3.1.1 Mode 0 (FCR bit 3 = 0)

Set and enable the interrupt for each single transmit or receive operation, and is similar to

the 16C450 mode. Transmit Ready (TXRDY) will go to a logic 0 whenever an empty

transmit space is available in the Transmit Holding Register (THR). Receive Ready

(RXRDY) will go to a logic 0 whenever the Receive Holding Register (RHR) is loaded with

a character.

7.3.1.2 Mode 1 (FCR bit 3 = 1)

Set and enable the interrupt in a block mode operation. The transmit interrupt is set when

the transmit FIFO is below the programmed trigger level. The receive interrupt is set when

the receive FIFO ﬁlls to the programmed trigger level. However, the FIFO continues to ﬁll

regardless of the programmed level until the FIFO is full. RXRDY remains a logic 0 as long

as the FIFO ﬁll level is above the programmed trigger level.

7.3.2 FIFO mode

Table 10. FIFO Control Register bits description

Bit

Symbol

Description

7:6

FCR[7] (MSB), RCVR trigger. These bits are used to set the trigger level for the receive

FCR[6] (LSB)

FIFO interrupt.

An interrupt is generated when the number of characters in the FIFO

equals the programmed trigger level. However, the FIFO will continue to

be loaded until it is full. Refer to Table 11.

5:4

FCR[5] (MSB), Logic 0 or cleared is the default condition; TX trigger level = 16.

FCR[4] (LSB)

These bits are used to set the trigger level for the transmit FIFO

interrupt. The SC16C650B will issue a transmit empty interrupt when

the number of characters in FIFO drops below the selected trigger level.

Refer to Table 12.

3

FCR[3]

DMA mode select.

logic 0 = set DMA mode ‘0’ (normal default condition)

logic 1 = set DMA mode ‘1’

Transmit operation in mode ‘0’: When the SC16C650B is in the

16C450 mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode

(FIFOs enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there

are no characters in the transmit FIFO or transmit holding register, the

TXRDY pin will be a logic 0. Once active, the TXRDY pin will go to a

logic 1 after the ﬁrst character is loaded into the transmit holding

register.

Receive operation in mode ‘0’: When the SC16C650B is in 16C450

mode, or in the FIFO mode (FCR[0] = logic 1; FCR[3] = logic 0) and

there is at least one character in the receive FIFO, the RXRDY pin will

be a logic 0. Once active, the RXRDY pin will go to a logic 1 when there

are no more characters in the receiver.

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UART with 32-byte FIFOs and IrDA encoder/decoder

Table 10. FIFO Control Register bits description …continued

Bit

Symbol

Description

3

Transmit operation in mode ‘1’: When the SC16C650B is in FIFO

mode (FCR[0] = logic 1; FCR[3] = logic 1), the TXRDY pin will be a

logic 1 when the transmit FIFO is completely full. It will be a logic 0

when FIFO has 1 empty space.

(cont.)

Receive operation in mode ‘1’: When the SC16C650B is in FIFO

mode (FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been

reached, or a Receive Time-Out has occurred, the RXRDY pin will go to

a logic 0. Once activated, it will go to a logic 1 after there are no more

characters in the FIFO.

2

1

0

FCR[2]

FCR[1]

FCR[0]

XMIT FIFO reset.

logic 0 = no FIFO transmit reset (normal default condition)

logic 1 = clears the contents of the transmit FIFO and resets the FIFO

counter logic (the transmit shift register is not cleared or altered). This

bit will return to a logic 0 after clearing the FIFO.

RCVR FIFO reset.

logic 0 = no FIFO receive reset (normal default condition)

logic 1 = clears the contents of the receive FIFO and resets the FIFO

counter logic (the receive shift register is not cleared or altered). This

bit will return to a logic 0 after clearing the FIFO.

FIFO enable.

logic 0 = disable the transmit and receive FIFO (normal default

condition)

logic 1 = enable the transmit and receive FIFO. This bit must be a

logic 1 when other FCR bits are written to, or they will not be

programmed.

Table 11. RCVR trigger levels

FCR[7]

FCR[6]

RX FIFO trigger level (bytes)

0

1

0

1

0

1

8

16

24

28

Table 12. TX FIFO trigger levels

FCR[5]

FCR[4]

TX FIFO trigger level (bytes)

0

1

0

1

0

1

16

8

24

30

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UART with 32-byte FIFOs and IrDA encoder/decoder

7.4 Interrupt Status Register (ISR)

The SC16C650B provides six levels of prioritized interrupts to minimize external software

interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status

bits. Performing a read cycle on the ISR will provide the user with the highest pending

interrupt level to be serviced. No other interrupts are acknowledged until the pending

interrupt is serviced. Whenever the interrupt status register is read, the interrupt status is

cleared. However, it should be noted that only the current pending interrupt is cleared by

the read. A lower level interrupt may be seen after re-reading the interrupt status bits.

Table 13 “Interrupt source” shows the data values (bits 0:5) for the six prioritized interrupt

levels and the interrupt sources associated with each of these interrupt levels.

Table 13. Interrupt source

Priority ISR[5] ISR[4] ISR[3] ISR[2] ISR[1] ISR[0] Source of the interrupt

level

1

0

1

0

LSR (receiver Line Status

Register)

2

3

0

1

0

1

0

1

0

RXRDY (Received Data Ready)

RXRDY (Receive Data time-out)

TXRDY (Transmitter Holding

Register Empty)

4

5

0

1

0

MSR (Modem Status Register)

RXRDY (Received Xoff signal) /

Special character

6

1

0

CTS, RTS change of state

Table 14. Interrupt Status Register bits description

Bit

Symbol

Description

7:6

ISR[7:6]

FIFOs enabled. These bits are set to a logic 0 when the FIFO is not being

used. They are set to a logic 1 when the FIFOs are enabled.

logic 0 or cleared = default condition

5:4

ISR[5:4]

INT priority bits 4:3. These bits are enabled when EFR[4] is set to a logic 1.

ISR[4] indicates that matching Xoff character(s) have been detected. ISR[5]

indicates that CTS, RTS have been generated. Note that once set to a

logic 1, the ISR[4] bit will stay a logic 1 until Xon character(s) are received.

logic 0 or cleared = default condition

3:1

0

ISR[3:1]

ISR[0]

INT priority bits 2:0. These bits indicate the source for a pending interrupt at

interrupt priority levels 1, 2, and 3 (see Table 13).

logic 0 or cleared = default condition

INT status.

logic 0 = an interrupt is pending and the ISR contents may be used as a

pointer to the appropriate interrupt service routine.

logic 1 = no interrupt pending (normal default condition)

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UART with 32-byte FIFOs and IrDA encoder/decoder

7.5 Line Control Register (LCR)

The Line Control Register is used to specify the asynchronous data communication

format. The word length, the number of stop bits, and the parity are selected by writing the

appropriate bits in this register.

Table 15. Line Control Register bits description

Bit

Symbol

Description

7

LCR[7]

Divisor latch enable. The internal baud rate counter latch and Enhanced

Feature mode enable.

logic 0 = divisor latch disabled (normal default condition)

logic 1 = divisor latch and enhanced feature register enabled

6

5

LCR[6]

LCR[5]

Set break. When enabled, the Break control bit causes a break condition to

be transmitted (the TX output is forced to a logic 0 state). This condition exists

until disabled by setting LCR[6] to a logic 0.

logic 0 = no TX break condition (normal default condition)

logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the

remote receiver to a line break condition

Set parity. If the parity bit is enabled, LCR[5] selects the forced parity format.

Programs the parity conditions (see Table 16).

logic 0 = parity is not forced (normal default condition)

LCR[5] = logic 1 and LCR[4] = logic 0: parity bit is forced to a logic 1 for the

transmit and receive data

LCR[5] = logic 1 and LCR[4] = logic 1: parity bit is forced to a logic 0 for the

transmit and receive data

4

LCR[4]

Even parity. If the parity bit is enabled with LCR[3] set to a logic 1, LCR[4]

selects the even or odd parity format.

logic 0 = odd parity is generated by forcing an odd number of logic 1s in the

transmitted data. The receiver must be programmed to check the same

format (normal default condition).

logic 1 = even parity is generated by forcing an even number of logic 1s in

the transmitted data. The receiver must be programmed to check the same

format.

3

LCR[3]

Parity enable. Parity or no parity can be selected via this bit.

logic 0 = no parity (normal default condition)

logic 1 = a parity bit is generated during the transmission, receiver checks

the data and parity for transmission errors

2

LCR[2]

Stop bits. The length of stop bit is speciﬁed by this bit in conjunction with the

programmed word length (see Table 17).

logic 0 or cleared = default condition

1:0

LCR[1:0]

Word length bits 1, 0. These two bits specify the word length to be transmitted

or received (see Table 18).

logic 0 or cleared = default condition

SC16C650B_4

Product data sheet

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SC16C650B

NXP Semiconductors

UART with 32-byte FIFOs and IrDA encoder/decoder

Table 16. LCR[5] parity selection

LCR[5]

LCR[4]

LCR[3]

Parity selection

no parity

X

0

1

X

0

1

0

1

0

1

odd parity

even parity

force parity ‘1’

forced parity ‘0’

Table 17. LCR[2] stop bit length

LCR[2]

Word length

5, 6, 7, 8

5

Stop bit length (bit times)

0

1

1-¹⁄₂

6, 7, 8

2

Table 18. LCR[1:0] word length

LCR[1]

LCR[0]

Word length

0

1

0

1

0

1

5

6

7

8

7.6 Modem Control Register (MCR)

This register controls the interface with the modem or a peripheral device.

Table 19. Modem Control Register bits description

Bit Symbol Description

7

MCR[7]

Clock select.

logic 0 = divide-by-1. The input clock (crystal or external) is divided by 16 and

then presented to the programmable Baud Rate Generator (BGR) without

further modiﬁcation, i.e., divide-by-1 (normal default condition).

logic 1 = divide-by-4. The divide-by-1 clock described in MCR[7] equals a

logic 0, is further divided by four (see also Section 6.7 “Programmable baud

rate generator”).

6

MCR[6]

IR enable.

logic 0 = enable the standard modem receive and transmit input/output

interface (normal default condition)

logic 1 = enable infrared IrDA receive and transmit inputs/outputs. While in this

mode, the TX/RX output/inputs are routed to the infrared encoder/decoder.

The data input and output levels will conform to the IrDA infrared interface

requirement. As such, while in this mode, the infrared TX output will be a

logic 0 during idle data conditions.

SC16C650B_4

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SC16C650B

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UART with 32-byte FIFOs and IrDA encoder/decoder

Table 19. Modem Control Register bits description …continued

Bit Symbol Description

5

MCR[5]

INT type select.

logic 0 = enable interrupt output mode (normal default condition)

logic 1 = enable open source interrupt output mode. Provides shared

interrupts by producing a wire-OR output driver capability for interrupts. This

output appears at the INT pin. When using this option, an external pull-down

resistor of 200 Ω to 500 Ω must be tied from the INT pin to ground to provide

an acceptable logic 0 level

4

MCR[4]

Loopback. Enable the local loopback mode (diagnostics). In this mode the

transmitter output (TX) and the receiver input (RX), CTS, DSR, DCD, and RI are

disconnected from the SC16C650B I/O pins. Internally the modem data and

control pins are connected into a loopback data conﬁguration (see Figure 7). In

this mode, the receiver and transmitter interrupts remain fully operational. The

Modem Control Interrupts are also operational, but the interrupts’ sources are

switched to the lower four bits of the Modem Control. Interrupts continue to be

controlled by the IER register.

logic 0 = disable loopback mode (normal default condition)

logic 1 = enable local loopback mode (diagnostics)

3

2

MCR[3]

MCR[2]

OUT2. In the loopback mode this bit is used to control the modem DCD signal

via OUT2.

logic 0 = OUT2 is at logic 1. In the loopback mode, sets OUT2 (DCD)

internally to a logic 1.

logic 1 = OUT2 is at logic 0. In the loopback mode, sets OUT2 (DCD)

internally to a logic 0.

OUT1, OUT. In the loopback mode, this bit is used to control modem RI interface

signal via OUT1 (OUT in the HVQFN32 package).

logic 0 = OUT1/OUT is at logic 1. In the loopback mode, sets RI internally to

logic 1.

logic 1 = OUT1/OUT is set at logic 0. In the loopback mode, sets RI internally

to logic 0.

1

0

MCR[1]

MCR[0]

RTS

logic 0 = force RTS output to a logic 1 (normal default condition)

logic 1 = force RTS output to a logic 0

DTR

logic 0 = force DTR output to a logic 1 (normal default condition)

logic 1 = force DTR output to a logic 0

SC16C650B_4

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SC16C650B

NXP Semiconductors

UART with 32-byte FIFOs and IrDA encoder/decoder

7.7 Line Status Register (LSR)

This register provides the status of data transfers between the SC16C650B and the CPU.

Table 20. Line Status Register bits description

Bit

Symbol Description

7

LSR[7]

FIFO data error.

logic 0 = no error (normal default condition)

logic 1 = at least one parity error, framing error or break indication is in the

current FIFO data. This bit is cleared when LSR register is read.

6

5

LSR[6]

THR and TSR empty. This bit is the Transmit Empty indicator. This bit is set to a

logic 1 whenever the transmit holding register and the transmit shift register are

both empty. It is reset to logic 0 whenever either the THR or TSR contains a

data character. In the FIFO mode, this bit is set to ‘1’ whenever the transmit

FIFO and transmit shift register are both empty.

LSR[5]

THR empty. This bit is the Transmit Holding Register Empty indicator. This bit

indicates that the UART is ready to accept a new character for transmission. In

addition, this bit causes the UART to issue an interrupt to CPU when the THR

interrupt enable is set. The THR bit is set to a logic 1 when a character is

transferred from the transmit holding register into the transmitter shift register.

The bit is reset to a logic 0 concurrently with the loading of the transmit holding

register by the CPU. In the FIFO mode, this bit is set when the transmit FIFO is

empty; it is cleared when at least 1 byte is written to the transmit FIFO.

4

3

2

1

LSR[4]

LSR[3]

LSR[2]

LSR[1]

Break interrupt.

logic 0 = no break condition (normal default condition)

logic 1 = the receiver received a break signal (RX was a logic 0 for one

character frame time). In the FIFO mode, only one break character is loaded

into the FIFO.

Framing error.

logic 0 = no framing error (normal default condition)

logic 1 = framing error. The receive character did not have a valid stop bit(s).

In the FIFO mode, this error is associated with the character at the top of the

FIFO.

Parity error.

logic 0 = no parity error (normal default condition)

logic 1 = parity error. The receive character does not have correct parity

information and is suspect. In the FIFO mode, this error is associated with

the character at the top of the FIFO.

Overrun error.

logic 0 = no overrun error (normal default condition).

logic 1 = overrun error. A data overrun error occurred in the receive shift

register. This happens when additional data arrives while the FIFO is full. In

this case, the previous data in the shift register is overwritten. Note that under

this condition, the data byte in the receive shift register is not transferred into

the FIFO, therefore the data in the FIFO is not corrupted by the error.

0

LSR[0]

Receive data ready.

logic 0 = no data in receive holding register or FIFO (normal default

condition)

logic 1 = data has been received and is saved in the receive holding register

or FIFO

SC16C650B_4

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SC16C650B

NXP Semiconductors

UART with 32-byte FIFOs and IrDA encoder/decoder

7.8 Modem Status Register (MSR)

This register provides the current state of the control interface signals from the modem, or

other peripheral device to which the SC16C650B is connected. Four bits of this register

are used to indicate the changed information. These bits are set to a logic 1 whenever a

control input from the modem changes state. These bits are set to a logic 0 whenever the

CPU reads this register.

Table 21. Modem Status Register bits description

Bit

Symbol Description

7

MSR[7]

MSR[6]

MSR[5]

MSR[4]

Data Carrier Detect. DCD (active HIGH, logic 1). Normally this bit is the

complement of the DCD input. In the loopback mode this bit is equivalent to the

OUT2 bit in the MCR register.

6

5

4

Ring Indicator. RI (active HIGH, logic 1). Normally this bit is the complement of

the RI input. In the loopback mode this bit is equivalent to the OUT1 bit in the

MCR register.

Data Set Ready. DSR (active HIGH, logic 1). Normally this bit is the

complement of the DSR input. In loopback mode this bit is equivalent to the

DTR bit in the MCR register.

Clear To Send. CTS. CTS functions as hardware ﬂow control signal input if it is

enabled via EFR[7]. Flow control (when enabled) allows starting and stopping

the transmissions based on the external modem CTS signal. A logic 1 at the

CTS pin will stop SC16C650B transmissions as soon as current character has

ﬁnished transmission. Normally MSR[4] is the complement of the CTS input.

However, in the loopback mode, this bit is equivalent to the RTS bit in the MCR

register.

3

2

1

0

MSR[3]

MSR[2]

MSR[1]

MSR[0]

∆DCD ^[1]

logic 0 = no DCD change (normal default condition)

logic 1 = the DCD input to the SC16C650B has changed state since the last

time it was read. A modem Status Interrupt will be generated.

∆RI ^[1]

logic 0 = no RI change (normal default condition)

logic 1 = the RI input to the SC16C650B has changed from a logic 0 to a

logic 1. A modem Status Interrupt will be generated.

∆DSR ^[1]

logic 0 = no DSR change (normal default condition)

logic 1 = the DSR input to the SC16C650B has changed state since the last

time it was read. A modem Status Interrupt will be generated.

∆CTS ^[1]

logic 0 = no CTS change (normal default condition)

logic 1 = the CTS input to the SC16C650B has changed state since the last

time it was read. A modem Status Interrupt will be generated.

[1] Whenever any MSR bit 3:0 is set to logic 1, a Modem Status Interrupt will be generated.

SC16C650B_4

Product data sheet

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SC16C650B

NXP Semiconductors

UART with 32-byte FIFOs and IrDA encoder/decoder

7.9 Scratchpad Register (SPR)

The SC16C650B provides a temporary data register to store 8 bits of user information.

7.10 Enhanced Feature Register (EFR)

Enhanced features are enabled or disabled using this register.

Bits 0 through 4 provide single or dual character software ﬂow control selection. When the

Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double 8-bit words are

concatenated into two sequential numbers.

Table 22. Enhanced Feature Register bits description

Bit

Symbol Description

7

EFR[7]

Automatic CTS ﬂow control.

logic 0 = Automatic CTS ﬂow control is disabled (normal default condition)

logic 1 = enable Automatic CTS ﬂow control. Transmission will stop when

CTS goes to a logic 1. Transmission will resume when the CTS pin returns to

a logic 0.

6

EFR[6]

Automatic RTS ﬂow control. Automatic RTS may be used for hardware ﬂow

control by enabling EFR[6]. When Auto-RTS is selected, an interrupt will be

generated when the receive FIFO is ﬁlled to the programmed trigger level and

RTS will go to a logic 1 at the next trigger level. RTS will return to a logic 0 when

data is unloaded below the next lower trigger level (programmed trigger level 1).

The state of this register bit changes with the status of the hardware ﬂow

control. RTS functions normally when hardware ﬂow control is disabled.

0 = Automatic RTS ﬂow control is disabled (normal default condition)

1 = enable Automatic RTS ﬂow control

5

EFR[5]

Special Character Detect.

logic 0 = special character detect disabled (normal default condition)

logic 1 = special character detect enabled. The SC16C650B compares each

incoming receive character with Xoff2 data. If a match exists, the received

data will be transferred to FIFO and ISR[4] will be set to indicate detection of

special character. Bit 0 in the X-registers corresponds with the LSB bit for the

receive character. When this feature is enabled, the normal software ﬂow

control must be disabled (EFR[3:0] must be set to a logic 0).

4

EFR[4]

Enhanced function control bit. The content of IER[7:4], ISR[5:4], FCR[5:4], and

MCR[7:5] can be modiﬁed and latched. After modifying any bits in the

enhanced registers, EFR[4] can be set to a logic 0 to latch the new values. This

feature prevents existing software from altering or overwriting the SC16C650B

enhanced functions.

logic 0 = disable (normal default condition)

logic 1 = enable

3:0

EFR[3:0] Cont-3:0 Tx, Rx control. Logic 0 or cleared is the default condition.

Combinations of software ﬂow control can be selected by programming these

bits. See Table 23.

SC16C650B_4

Product data sheet

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SC16C650B

NXP Semiconductors

UART with 32-byte FIFOs and IrDA encoder/decoder

Table 23. Software ﬂow control functions^[1]

Cont-3 Cont-2 Cont-1 Cont-0 TX, RX software ﬂow controls

0

1

0

1

X

1

0

1

X

0

X

0

1

0

1

X

0

1

No transmit ﬂow control

Transmit Xon1/Xoff1

Transmit Xon2/Xoff2

Transmit Xon1 and Xon2/Xoff1 and Xoff2

No receive ﬂow control

Receiver compares Xon1/Xoff1

Receiver compares Xon2/Xoff2

Transmit Xon1/Xoff1

Receiver compares Xon1 and Xon2, Xoff1 and Xoff2

Transmit Xon2/Xoff2

0

1

Receiver compares Xon1 and Xon2/Xoff1 and Xoff2

Transmit Xon1 and Xon2/Xoff1 and Xoff2

Receiver compares Xon1 and Xon2/Xoff1 and Xoff2

[1] When using a software ﬂow control the Xon/Xoff characters cannot be used for data transfer.

7.11 SC16C650B external reset conditions

Table 24. Reset state for registers

Register

IER

Reset state

IER[7:0] = 0

ISR

ISR[7:1] = 0; ISR[0] = 1

LCR[7:0] = 0

LCR

MCR

LSR

MCR[7:0] = 0

LSR[7] = 0; LSR[6:5] = 1; LSR[4:0] = 0

MSR[7:4] = input signals; MSR[3:0] = 0

FCR[7:0] = 0

MSR

FCR

EFR

EFR[7:0] = 0

Table 25. Reset state for outputs

Output

TX

Reset state

HIGH

RTS

HIGH

DTR

HIGH

RXRDY

TXRDY

INT

HIGH

LOW

SC16C650B_4

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SC16C650B

NXP Semiconductors

UART with 32-byte FIFOs and IrDA encoder/decoder

8. Limiting values

Table 26. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_CC

Parameter

Conditions

Min

Max

7

Unit

V

supply voltage

-

V_n

voltage on any other pin

at D7 to D0

GND − 0.3

V_CC+ 0.3

5.3

V

at any input only pin

operating in free air

GND − 0.3

V

T_amb

ambient temperature

−40

−65

-

+85

°C

mW

T_stg

storage temperature

+150

500

P_tot/pack

total power dissipation per package

9. Static characteristics

Table 27. Static characteristics

T_amb= −40 °C to +85 °C; tolerance of V_CC± 10 %, unless otherwise speciﬁed.

Symbol Parameter

Conditions

V_CC= 2.5 V

Min Max

−0.3 +0.45 −0.3 +0.6 −0.5 +0.6

V_CC= 3.3 V

V_CC= 5.0 V Unit

Min

Max

Min Max

V_IL(clk)

V_IH(clk)

clock LOW-level input

voltage

V

clock HIGH-level input

voltage

1.8

V_CC

2.4

V_CC

3.0

V_CC

V_IL

LOW-level input voltage

HIGH-level input voltage

LOW-level output voltage

−0.3 +0.65 −0.3 +0.8 −0.5 +0.8

V

V_IH

V_OL

1.6

-

2.0

-

2.2

V_CC

[1]

on all outputs

I_OL= 5 mA (data bus)

-

0.4

-

V

I_OL= 4 mA

0.4

(other outputs)

I_OL= 2 mA (data bus)

-

0.4

-

V

I_OL= 1.6 mA

(other outputs)

V_OH

HIGH-level output voltage

I_OH= −5 mA (data bus)

-

2.4

-

V

I_OH= −1 mA

2.0

(other outputs)

I_OH= −800 µA (data bus)

1.85

-

V

I_OH= −400 µA

(other outputs)

I_LIL

LOW-level input leakage

current

-

±10

-

±10

-

±10 µA

I_L(clk)

clock leakage current

average supply current

-

±30

3.5

50

5

-

±30

4.5

50

5

-

±30 µA

4.5 mA

50 µA

I_CC(AV)

f = 5 MHz

-

[2]

I_CC(sleep)sleep mode supply current f = 5 MHz

-

C_i

input capacitance

5

-

pF

R_pu(int)

internal pull-up resistance

500

-

500

-

500

kΩ

[1] Except for XTAL2, V_OL= 1 V typically.

SC16C650B_4

Product data sheet

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SC16C650B

NXP Semiconductors

UART with 32-byte FIFOs and IrDA encoder/decoder

[2] Sleep current might be higher if there is activity on the data bus during Sleep mode.

10. Dynamic characteristics

Table 28. Dynamic characteristics

T_amb= −40 °C to +85 °C; tolerance of V_CC± 10 %, unless otherwise speciﬁed.

Symbol Parameter

Conditions

V_CC= 2.5 V

V_CC= 3.3 V

V_CC= 5.0 V

Unit

Min

Max

Min

Max

Min

Max

t_WL

t_WH

f_XTAL1

t_4w

t_5s

pulse width LOW

15

-

13

-

10

-

ns

MHz

ns

pulse width HIGH

[1]

frequency on pin XTAL1

address strobe width

address set-up time

address hold time

16

-

32

-

48

-

45

5

35

5

25

1

-

t_5h

5

-

5

-

5

-

t_6s

chip select set-up time to AS

address hold time

10

0

-

5

-

0

-

t_6h

-

0

-

0

-

[2]

t_6s'

t_6h

address set-up time

chip select hold time

IOR delay from chip select

IOR strobe width

10

0

-

10

0

-

5

-

0

-

t_7d

10

77

0

-

10

26

0

-

10

23

0

-

t_7w

t_7h

25 pF load

-

chip select hold time from

IOR

-

[2]

t_7h'

address hold time

5

10

20

-

5

10

20

-

5

10

20

-

ns

t_8d

IOR delay from address

read cycle delay

-

t_9d

25 pF load

-

t_11d

t_12d

t_12h

t_13d

t_13w

t_13h

IOR to DDIS delay

delay from IOR to data

data disable time

100

77

15

-

35

26

15

-

30

23

15

-

IOW delay from chip select

IOW strobe width

10

20

0

10

20

0

10

15

0

-

chip select hold time from

IOW

-

t_14d

t_15d

t_16s

t_16h

t_17d

t_18d

IOW delay from address

write cycle delay

10

25

20

15

-

10

25

20

5

-

10

20

15

5

-

ns

-

data set-up time

-

data hold time

-

delay from IOW to output

25 pF load

100

-

33

24

-

29

23

delay to set interrupt from

Modem input

-

t_19d

t_20d

t_21d

delay to reset interrupt from 25 pF load

IOR

-

100

1T_RCLK

100

-

24

1T_RCLK

29

-

23

1T_RCLK

28

ns

s

[3]

delay from stop to set

interrupt

delay from IOR to reset

interrupt

25 pF load

ns

SC16C650B_4

Product data sheet

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SC16C650B

NXP Semiconductors

UART with 32-byte FIFOs and IrDA encoder/decoder

Table 28. Dynamic characteristics …continued

T_amb= −40 °C to +85 °C; tolerance of V_CC± 10 %, unless otherwise speciﬁed.

Symbol Parameter Conditions V_CC= 2.5 V

V_CC= 3.3 V

V_CC= 5.0 V

Unit

Min

Max

Min

Max

Min

Max

t_22d

t_23d

t_24d

t_25d

t_26d

t_27d

t_28d

delay from start to set

interrupt

-

100

-

45

-

40

ns

s

[3]

delay from IOW to transmit

start

8T_RCLK24T_RCLK8T_RCLK24T_RCLK8T_RCLK24T_RCLK

delay from IOW to reset

interrupt

-

100

1T_RCLK

100

-

45

1T_RCLK

45

-

40

1T_RCLK

40

ns

s

delay from stop to set

RXRDY

delay from IOR to reset

RXRDY

ns

s

delay from IOW to set

TXRDY

100

45

40

[3]

[4]

delay from start to reset

TXRDY

8T_RCLK

t_RESET

N

RESET pulse width

baud rate divisor

100

1

-

40

1

-

40

1

-

ns

2¹⁶− 1

[1] Applies to external clock; crystal oscillator max 24 MHz.

[2] Applicable only when AS is tied LOW.

[3] RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches.

[4] RESET pulse must happen when these signals are inactive: CS, CS0, CS1, CS2, IOR, IOR, IOW, IOW.

SC16C650B_4

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SC16C650B

NXP Semiconductors

UART with 32-byte FIFOs and IrDA encoder/decoder

10.1 Timing diagrams

t

4w

AS

t

5h

5s

valid

address

A0 to A2

t

6s

6h

CS2

CS1, CS0

valid

t

7h

7d

t

7w

t

9d

8d

active

IOR, IOR

t

11d

t

11h

active

DDIS

t

12h

12d

D0 to D7

data

002aaa331

Fig 8. General read timing when using AS signal

t

4w

AS

t

5h

5s

valid

address

A0 to A2

t

6s

6h

CS2

CS1, CS0

valid

t

13d

13h

t

13w

t

15d

14d

active

IOW, IOW

D0 to D7

t

16h

16s

data

002aaa332

Fig 9. General write timing when using AS signal

SC16C650B_4

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SC16C650B

NXP Semiconductors

UART with 32-byte FIFOs and IrDA encoder/decoder

valid

address

valid

address

A0 to A2

t

7h'

t

6s'

7h'

7w

CS

active

t

9d

7w

active

IOR

t

12h

t

12h

12d

D0 to D7

data

002aaa333

Fig 10. General read timing when AS is tied to GND

valid

address

A0 to A2

address

t

7h'

t

6s'

7h'

active

CS

IOW

t

13w

15d

active

t

16h

t

16h

16s

data

D0 to D7

002aaa334

Fig 11. General write timing when AS is tied to GND

SC16C650B_4

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SC16C650B

NXP Semiconductors

UART with 32-byte FIFOs and IrDA encoder/decoder

IOW

RTS

active

t

17d

change of state

DTR

DCD

CTS

DSR

change of state

t

18d

INT

active

t

19d

active

IOR

RI

t

18d

change of state

002aaa347

Fig 12. Modem input/output timing

t

WH

WL

external clock

t

w(clk)

002aac357

1

f _XTAL1

=

--------------

t_w(clk)

Fig 13. External clock timing

SC16C650B_4

Product data sheet

Rev. 04 — 14 September 2009

34 of 48

SC16C650B

NXP Semiconductors

UART with 32-byte FIFOs and IrDA encoder/decoder

start

bit

parity stop start

bit

data bits (0 to 7)

D3 D4

RX

D0

D1

D2

D5

D6

D7

5 data bits

6 data bits

7 data bits

t

20d

active

INT

t

21d

active

IOR

16 baud rate clock

002aaa113

Fig 14. Receive timing

start

bit

parity stop start

bit bit

bit

data bits (0 to 7)

D3 D4

D0

D1

D2

D5

D6

D7

RX

t

25d

active data

ready

RXRDY

IOR

t

26d

active

002aab063

Fig 15. Receive ready timing in non-FIFO mode

SC16C650B_4

Product data sheet

Rev. 04 — 14 September 2009

35 of 48

SC16C650B

NXP Semiconductors

UART with 32-byte FIFOs and IrDA encoder/decoder

start

bit

parity stop

bit

data bits (0 to 7)

D3 D4

D0

D1

D2

D5

D6

D7

RX

first byte that

reaches the

trigger level

t

25d

active data

ready

RXRDY

IOR

t

26d

active

002aab064

Fig 16. Receive ready timing in FIFO mode

start

bit

parity stop start

bit bit

bit

data bits (0 to 7)

TX

D0

D1

D2

D3

D4

D5

D6

D7

5 data bits

6 data bits

7 data bits

active

INT

transmitter ready

t

22d

t

24d

t

23d

active

IOW

16 baud rate clock

002aaa116

Fig 17. Transmit timing

SC16C650B_4

Product data sheet

Rev. 04 — 14 September 2009

36 of 48

SC16C650B

NXP Semiconductors

UART with 32-byte FIFOs and IrDA encoder/decoder

start

bit

parity stop start

bit

data bits (0 to 7)

D3 D4

TX

D0

D1

D2

D5

D6

D7

active

IOW

D0 to D7

byte #1

t

28d

t

27d

active

transmitter ready

transmitter

not ready

TXRDY

002aaa580

Fig 18. Transmit ready timing in non-FIFO mode

start

bit

parity stop

bit bit

data bits (0 to 7)

D3 D4

D0

D1

D2

D5

D6

D7

TX

5 data bits

6 data bits

7 data bits

IOW

active

t

28d

D0 to D7

byte #32

t

27d

TXRDY

FIFO full

002aad685

Fig 19. Transmit ready timing in FIFO mode (DMA mode ‘1’)

SC16C650B_4

Product data sheet

Rev. 04 — 14 September 2009

37 of 48

SC16C650B

NXP Semiconductors

UART with 32-byte FIFOs and IrDA encoder/decoder

UART frame

start

0

data bits

stop

1

0

1

0

1

0

TX data

IrDA TX data

1

/

bit time

2

bit

time

3

/

bit time

16

002aaa212

Fig 20. Infrared transmit timing

IrDA RX data

bit

time

0 to 1 16× clock delay

0

1

0

1

0

1

0

1

RX data

start

data bits

stop

UART frame

002aaa213

Fig 21. Infrared receive timing

SC16C650B_4

Product data sheet

Rev. 04 — 14 September 2009

38 of 48

SC16C650B

NXP Semiconductors

UART with 32-byte FIFOs and IrDA encoder/decoder

11. Package outline

PLCC44: plastic leaded chip carrier; 44 leads

SOT187-2

e

D

E

y

X

A

39

29

b

p

Z

E

28

40

b

1

w

M

44

1

H

E

pin 1 index

A

1

A

4

e

(A )

3

6

18

β

L

p

k

detail X

7

17

v

M

A

e

Z

D

B

H

v

M

B

D

0

5

10 mm

scale

DIMENSIONS (mm dimensions are derived from the original inch dimensions)

(1)

A

Z

E

4

1

(1)

D

UNIT

mm

A

b

D

E

e

H

k

L

p

v

w

y

β

b

3

1

D

E

D

E

p

max.

min.

max. max.

4.57

4.19

0.81 16.66 16.66

0.66 16.51 16.51

16.00 16.00 17.65 17.65 1.22 1.44

14.99 14.99 17.40 17.40 1.07 1.02

0.53

0.33

0.51 0.25 3.05

0.02 0.01 0.12

1.27

0.05

0.18 0.18

0.1

2.16 2.16

o

45

0.180

0.165

0.032 0.656 0.656

0.026 0.650 0.650

0.63 0.63 0.695 0.695 0.048 0.057

0.59 0.59 0.685 0.685 0.042 0.040

0.021

0.013

inches

0.007 0.007 0.004 0.085 0.085

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

01-11-14

SOT187-2

112E10

MS-018

EDR-7319

Fig 22. Package outline SOT187-2 (PLCC44)

SC16C650B_4

Product data sheet

Rev. 04 — 14 September 2009

39 of 48

SC16C650B

NXP Semiconductors

UART with 32-byte FIFOs and IrDA encoder/decoder

LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm

SOT313-2

c

y

X

36

25

A

E

37

24

Z

E

e

H

E

A

2

A

(A )

3

A

1

w M

p

θ

pin 1 index

b

L

p

L

13

48

detail X

1

12

Z

v M

D

A

e

w M

b

p

D

B

H

v

M

B

D

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

v

w

y

Z

E

θ

1

2

3

p

E

p

D

max.

7^o

0^o

0.20 1.45

0.05 1.35

0.27 0.18 7.1

0.17 0.12 6.9

7.1

6.9

9.15 9.15

8.85 8.85

0.75

0.45

0.95 0.95

0.55 0.55

1.6

mm

0.25

0.5

1

0.2 0.12 0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-01-19

03-02-25

SOT313-2

136E05

MS-026

Fig 23. Package outline SOT313-2 (LQFP48)

SC16C650B_4

Product data sheet

Rev. 04 — 14 September 2009

40 of 48

SC16C650B

NXP Semiconductors

UART with 32-byte FIFOs and IrDA encoder/decoder

HVQFN32: plastic thermal enhanced very thin quad flat package; no leads;

32 terminals; body 5 x 5 x 0.85 mm

SOT617-1

B

A

D

terminal 1

index area

A

1

E

c

detail X

C

e

1

y

e

1/2 e

v

M

b

C

A B

C

1

w

9

16

L

17

8

e

E

h

2

1/2 e

1

24

terminal 1

index area

32

25

X

D

h

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

A

(1)

UNIT

A

b

c

E

e

2

y

D

E

L

v

w

y

1

h

1

h

max.

0.05 0.30

0.00 0.18

5.1

4.9

3.25

2.95

5.1

4.9

3.25

2.95

0.5

0.3

mm

0.05 0.1

1

0.2

0.5

3.5

0.1

0.05

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

01-08-08

02-10-18

SOT617-1

- - -

MO-220

- - -

Fig 24. Package outline SOT617-1 (HVQFN32)

SC16C650B_4

Product data sheet

Rev. 04 — 14 September 2009

41 of 48

SC16C650B

NXP Semiconductors

UART with 32-byte FIFOs and IrDA encoder/decoder

12. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reﬂow

soldering description”.

12.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

12.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

• Board speciﬁcations, including the board ﬁnish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

12.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath speciﬁcations, including temperature and impurities

SC16C650B_4

Product data sheet

Rev. 04 — 14 September 2009

42 of 48

SC16C650B

NXP Semiconductors

UART with 32-byte FIFOs and IrDA encoder/decoder

12.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 25) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 29 and 30

Table 29. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

235

≥ 350

220

< 2.5

≥ 2.5

220

Table 30. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 25.

SC16C650B_4

Product data sheet

Rev. 04 — 14 September 2009

43 of 48

SC16C650B

NXP Semiconductors

UART with 32-byte FIFOs and IrDA encoder/decoder

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 25. Temperature proﬁles for large and small components

For further information on temperature proﬁles, refer to Application Note AN10365

“Surface mount reﬂow soldering description”.

13. Abbreviations

Table 31. Abbreviations

Acronym

CPU

DLL

Description

Central Processing Unit

Divisor Latch LSB

DLM

DMA

FIFO

ISDN

LSB

Divisor Latch MSB

Direct Memory Access

First-In, First-Out

Integrated Service Digital Network

Least Signiﬁcant Bit

MSB

TTL

Most Signiﬁcant Bit

Transistor-Transistor Logic

14. Revision history

Table 32. Revision history

Document ID

SC16C650B_4

Modiﬁcations:

Release date

Data sheet status

Change notice

Supersedes

20090914

Product data sheet

-

SC16C650B-03

• The format of this data sheet has been redesigned to comply with the new identity guidelines of

NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• DIP40 package option (type number SC16C650BIN40) removed

SC16C650B_4

Product data sheet

Rev. 04 — 14 September 2009

44 of 48

SC16C650B

NXP Semiconductors

UART with 32-byte FIFOs and IrDA encoder/decoder

Table 32. Revision history …continued

Document ID

Release date

Data sheet status

Change notice

Supersedes

Modiﬁcations:

• Section 2 “Features”, 3rd bullet: changed from “5 V tolerant inputs” to “5 V tolerant on input only

pins”, and added Footnote 1.

• Table 2 “Pin description”:

–

added (new) Table note [1] and its reference at HVQFN32 pin 13 (GND)

–

Description for signal DDIS changed from “DDIS is active (LOW) when the CPU is not reading

data. When active, DDIS can disable an external transceiver.” to “DDIS is active (LOW) when

the CPU is reading data. When inactive (HIGH), DDIS can disable an external transceiver.”

• Section 6.8 “DMA operation”:

–

3

^rdsentence: changed from “... the state of the RXRDY and TXRDY output pins.” to “... the

state of the RXRDY and TXRDY output pins.”

–

added Remark

• Section 7 “Register descriptions”:

–

ﬁrst paragraph: changed from “... for the ﬁfteen SC16C650B internal registers.” to “... for the

seventeen SC16C650B internal registers.”

• Table 8 “SC16C650B internal registers”:

–

descriptive text below table title moved to (new) Table note [3]

removed shading from 9 table cells; added reference to Table note [3]

deleted reference to Table note [4] at MCR[2]

Table note [4] changed from “These functions are not supported ...” to “This function is not

supported ...”

–

added (new) Table note [5] and its reference at MCR[3]

added (new) Table note [6] and its reference at FCR[3] and MCR[2]

MCR bit 2 changed from “OUT1” to “OUT1, OUT”

MCR bit 3 changed from “OUT2, INT enable” to “OUT2”

• Table 19 “Modem Control Register bits description”:

–

description of MCR[5]: removed references to IRQA pin

–

description of MCR[5]: logic 0: changed from “enable active or 3-State interrupt output mode”

to “enable interrupt output mode”

–

description of MCR[5]: logic 1, second sentence changed from “Provides shared interrupts in

the STD mode by producing ...” to “Provides shared interrupts by producing ...”

–

description of MCR[3] re-written

description of MCR[2] re-written

• Table 25 “Reset state for outputs”: deleted “(STD mode)” from the Reset state column for RXRDY,

TXRDY and INT outputs

• Table 26 “Limiting values”:

–

parameter description for symbol V_nchanged from “voltage at any pin” to “voltage on any other

pin”; added separate conditions for “at D7 to D0” and “at any input only pin”

parameter description for symbol T_ambchanged from “operating temperature” to “ambient

temperature”; added condition “operating in free air”

symbol for ‘total power dissipation per package” changed from “P_tot(pack)” to “P_tot/pack”

SC16C650B_4

Product data sheet

Rev. 04 — 14 September 2009

45 of 48

SC16C650B

NXP Semiconductors

UART with 32-byte FIFOs and IrDA encoder/decoder

Table 32. Revision history …continued

Document ID

Release date

Data sheet status

Change notice

Supersedes

Modiﬁcations:

(continued)

• Table 27 “Static characteristics”:

–

table title changed (was “DC electrical characteristics”)

descriptive text below table title changed from “V_CC= 2.5 V, 3.3 V or 5.0 V ±10%” to “tolerance

of V_CC± 10 %”

–

symbol “V_IL(CK)” changed to “V_IL(clk)

”

symbol “V_IH(CK)” changed to “V_IH(clk)

”

parameter description for V_OL: moved “on all outputs” to Conditions column

symbol/parameter “I_CL, clock leakage” changed to “I_L(clk), clock leakage current”

symbol/parameter “I_CC, average power supply current” changed to “I_CC(AV), average supply

current”

–

added I_CC(sleep)speciﬁcation

Table note [1]: changed “x₂” to “XTAL2”

(old) Table note [2] deleted (and its reference at R_pu(int)

)

added (new) Table note [2] and its reference at I_CC(sleep)

• Table 28 “Dynamic characteristics”:

–

table title changed (was “AC electrical characteristics”

–

descriptive text below table title changed from “V_CC= 2.5 V, 3.3 V or 5.0 V ±10%” to “tolerance

of V_CC± 10 %”

–

symbol “t_1w, t_2w, clock pulse duration” is split into two parameters “t_WH, pulse width HIGH” and

“t_WL, pulse width LOW”

–

symbol “t_3w, oscillator/clock frequency” changed to “f_XTAL1, frequency on pin XTAL1”

symbols t_20d, t_23d, t_25d, t_28d: unit changed from “R_clk” to “s”; values are appended with “T_RCLK

”

and referenced to (new) Table note [3]

–

parameter description for t_RESETchanged from “Reset pulse width” to “RESET pulse width”;

added reference to (new) Table note [4]

–

unit for parameter “baud rate divisor”: deleted “R_clk” (N is a number)

• Figure 13 “External clock timing”:

–

symbol changed from “t_1w” to “t_WH

”

symbol changed from “t_2w” to “t_WL

”

symbol changed from “t_3w” to “t_w(clk)

added equation

”

• Figure 15, Figure 16, Figure 18, Figure 19: changed from “DATA BITS (5-8)” to “data bits (0 to 7)”

• Figure 19: in waveform for signals D0 to D7, changed “BYTE #16” to “byte #32”

SC16C650B-03

20041210

Product data

-

SC16C650B-02

(9397 750 14451)

Modiﬁcations:

• There is no modiﬁcation to the data sheet. However, reader is advised to refer to AN10333

(Rev. 02) “SC16CXXXB baud rate deviation tolerance” (9397 750 14411) that was released

together with this revision.

SC16C650B-02

20040603

Product data

-

SC16C650B-01

(9397 750 13317)

SC16C650B-01

20040330

Product data

-

(9397 750 11994)

SC16C650B_4

Product data sheet

Rev. 04 — 14 September 2009

46 of 48

SC16C650B

NXP Semiconductors

UART with 32-byte FIFOs and IrDA encoder/decoder

15. Legal information

15.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

15.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

15.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

SC16C650B_4

Product data sheet

Rev. 04 — 14 September 2009

47 of 48

SC16C650B

NXP Semiconductors

UART with 32-byte FIFOs and IrDA encoder/decoder

17. Contents

1

2

3

4

General description . . . . . . . . . . . . . . . . . . . . . . 1

12.2

12.3

12.4

Wave and reﬂow soldering . . . . . . . . . . . . . . . 42

Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 42

Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 43

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

13

14

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 44

Revision history . . . . . . . . . . . . . . . . . . . . . . . 44

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

15

Legal information . . . . . . . . . . . . . . . . . . . . . . 47

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 47

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 47

15.1

15.2

15.3

15.4

6

Functional description . . . . . . . . . . . . . . . . . . . 8

Internal registers. . . . . . . . . . . . . . . . . . . . . . . . 9

FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . . 9

Hardware ﬂow control. . . . . . . . . . . . . . . . . . . 10

Software ﬂow control . . . . . . . . . . . . . . . . . . . 10

Special feature software ﬂow control . . . . . . . 11

Hardware/software and time-out interrupts. . . 11

Programmable baud rate generator . . . . . . . . 12

DMA operation . . . . . . . . . . . . . . . . . . . . . . . . 14

Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Loopback mode . . . . . . . . . . . . . . . . . . . . . . . 14

6.1

6.2

6.3

6.4

6.5

6.6

6.7

6.8

6.9

6.10

16

17

Contact information . . . . . . . . . . . . . . . . . . . . 47

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

7

7.1

Register descriptions . . . . . . . . . . . . . . . . . . . 16

Transmit Holding Register (THR) and

Receive Holding Register (RHR) . . . . . . . . . . 17

Interrupt Enable Register (IER) . . . . . . . . . . . 17

IER versus receive FIFO interrupt mode

7.2

7.2.1

operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

IER versus receive/transmit FIFO polled

7.2.2

mode operation. . . . . . . . . . . . . . . . . . . . . . . . 18

FIFO Control Register (FCR) . . . . . . . . . . . . . 19

DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Mode 0 (FCR bit 3 = 0). . . . . . . . . . . . . . . . . . 19

Mode 1 (FCR bit 3 = 1). . . . . . . . . . . . . . . . . . 19

FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Interrupt Status Register (ISR) . . . . . . . . . . . . 21

Line Control Register (LCR) . . . . . . . . . . . . . . 22

Modem Control Register (MCR) . . . . . . . . . . . 23

Line Status Register (LSR). . . . . . . . . . . . . . . 25

Modem Status Register (MSR). . . . . . . . . . . . 26

Scratchpad Register (SPR) . . . . . . . . . . . . . . 27

Enhanced Feature Register (EFR) . . . . . . . . . 27

SC16C650B external reset conditions . . . . . . 28

7.3

7.3.1

7.3.1.1

7.3.1.2

7.3.2

7.4

7.5

7.6

7.7

7.8

7.9

7.10

7.11

8

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 29

Static characteristics. . . . . . . . . . . . . . . . . . . . 29

Dynamic characteristics . . . . . . . . . . . . . . . . . 30

Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . 32

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 39

Soldering of SMD packages . . . . . . . . . . . . . . 42

Introduction to soldering . . . . . . . . . . . . . . . . . 42

9

10

10.1

11

12

12.1

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 14 September 2009

Document identifier: SC16C650B_4


型号：	SC16C650BIB48,157
厂家：	NXP
描述：	SC16C650B - 5 V, 3.3 V and 2.5 V UART with 32-byte FIFOs and infrared (IrDA) encoder/decoder QFP 48-Pin 通信时钟数据传输先进先出芯片外围集成电路
文件：	总48页 (文件大小：243K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SC16C650BIB48,157 [NXP]

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