SC16C650BIB48_技术文档

SC16C650B

5 V, 3.3 V and 2.5 V UART with 32-byte FIFOs

and infrared (IrDA) encoder/decoder

Rev. 03 — 10 December 2004

Product data

1. General description

The SC16C650B is a Universal Asynchronous Receiver and Transmitter (UART)

used for serial data communications. Its principal function is to convert parallel data

into serial data, and vice versa. The UART can handle serial data rates up to 3 Mbit/s.

The SC16C650B is pin compatible with the ST16C650A and it will power-up to be

functionally equivalent to the 16C450. Programming of control registers enables the

added features of the SC16C650B. Some of these added features are the 32-byte

receive and transmit FIFOs, automatic hardware or software ﬂow control and infrared

encoding/decoding. The selectable auto-ﬂow control feature signiﬁcantly reduces

software overload and increases system efﬁciency while in FIFO mode by

automatically controlling serial data ﬂow using RTS output and CTS input signals.

The SC16C650B also provides DMA mode data transfers through FIFO trigger levels

and the RXRDY and TXRDY signals. On-board status registers provide the user with

error indications, operational status, and modem interface control. System interrupts

may be tailored to meet user requirements. An internal loop-back capability allows

on-board diagnostics.

The SC16C650B operates at 5 V, 3.3 V and 2.5 V, and the industrial temperature

range, and is available in plastic DIP40, PLCC44, LQFP48, and HVQFN32 packages.

2. Features

■ Single channel

■ 5 V, 3.3 V and 2.5 V operation

■ 5 V tolerant inputs

■ Industrial temperature range (−40 °C to +85 °C)

■ After reset, all registers are identical to the typical 16C450 register set

■ Capable of running with all existing generic 16C450 software

■ Pin compatibility with the industry-standard ST16C450/550, TL16C450/550,

PC16C450/550. Software compatible with ST16C650.

■ Up to 3 Mbit/s transmit/receive operation at 5 V, 2 Mbit/s at 3.3 V, and 1 Mbit/s at

2.5 V

■ 32 byte transmit FIFO

■ 32 byte receive FIFO with error ﬂags

■ Programmable auto-RTS and auto-CTS

◆ In auto-CTS mode, CTS controls transmitter

◆ In auto-RTS mode, RxFIFO contents and threshold control RTS

■ Automatic software/hardware ﬂow control

■ Programmable Xon/Xoff characters

SC16C650B

UART with 32-byte FIFOs and IrDA encoder/decoder

Philips Semiconductors

■ Software selectable Baud Rate Generator

■ Supports IrDA version 1.0 (up to 115.2 kbit/s)

■ Four selectable Receive and Transmit FIFO interrupt trigger levels

■ Standard modem interface or infrared IrDA encoder/decoder interface

■ Sleep mode

■ Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun

Break)

■ Independent receiver clock input

■ Transmit, Receive, Line Status, and Data Set interrupts independently controlled

■ Fully programmable character formatting:

◆ 5, 6, 7, or 8-bit characters

◆ Even, Odd, or No-Parity formats

◆ 1, 1¹⁄₂, or 2-stop bit

◆ Baud generation (DC to 3 Mbit/s)

■ False start-bit detection

■ Complete status reporting capabilities

■ 3-State output TTL drive capabilities for bi-directional data bus and control bus

■ Line Break generation and detection

■ Internal diagnostic capabilities:

◆ Loop-back controls for communications link fault isolation

■ Prioritized interrupt system controls

■ Modem control functions (CTS, RTS, DSR, DTR, RI, DCD).

3. Ordering information

Table 1:

Ordering information

Industrial: V_CC= 2.5 V, 3.3 V or 5 V ± 10%; T_amb= −40 °C to +85 °C.

Type number

Package

Name

Description

Version

SC16C650BIA44

SC16C650BIB48

SC16C650BIBS

PLCC44

LQFP48

plastic leaded chip carrier; 44 leads

plastic low proﬁle quad ﬂat package; 48 leads; body 7 × 7 × 1.4 mm

SOT187-2

SOT313-2

SOT617-1

HVQFN32 plastic thermal enhanced very thin quad ﬂat package; no leads;

32 terminals; body 5 × 5 × 0.85 mm

SC16C650BIN40

DIP40

plastic dual in-line package; 40 leads (600 mil)

SOT129-1

9397 750 14451

Product data

Rev. 03 — 10 December 2004

2 of 51

SC16C650B

UART with 32-byte FIFOs and IrDA encoder/decoder

Philips Semiconductors

4. Block diagram

SC16C650B

TRANSMIT

FIFO

TRANSMIT

SHIFT

TX

REGISTERS

REGISTER

D0–D7

IOR, IOR

IOW, IOW

RESET

DATA BUS

AND

CONTROL LOGIC

FLOW

CONTROL

LOGIC

IR

ENCODER

RECEIVE

FIFO

RECEIVE

SHIFT

RX

REGISTERS

REGISTER

FLOW

CONTROL

LOGIC

IR

DECODER

REGISTER

SELECT

LOGIC

A0–A2

CS0, CS1, CS2

AS

DDIS

DTR

RTS

OUT1, OUT2

MODEM

CONTROL

LOGIC

INT

TXRDY

RXRDY

CTS

RI

DCD

CLOCK AND

BAUD RATE

GENERATOR

INTERRUPT

CONTROL

LOGIC

DSR

002aaa602

XTAL1 XTAL2

RCLK BAUDOUT

Fig 1. Block diagram.

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SC16C650B

UART with 32-byte FIFOs and IrDA encoder/decoder

Philips Semiconductors

5. Pinning information

5.1 Pinning

D5

D6

D7

7

8

9

39 RESET

38 OUT1

37 DTR

RCLK 10

RX 11

36 RTS

35 OUT2

SC16C650BIA44

n.c. 12

TX 13

34 n.c.

33 INT

32 RXRDY

31 A0

CS0 14

CS1 15

CS2 16

30 A1

BAUDOUT 17

29 A2

002aaa603

Fig 2. PLCC44 pin conﬁguration.

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SC16C650B

UART with 32-byte FIFOs and IrDA encoder/decoder

Philips Semiconductors

n.c.

D5

1

2

3

4

5

6

7

8

9

36 n.c.

35 RESET

34 OUT1

33 DTR

32 RTS

D6

D7

RCLK

n.c.

RX

31 OUT2

SC16C650BIB48

30 INT

TX

29 RXRDY

28 A0

CS0

CS1 10

CS2 11

27 A1

26 A2

BAUDOUT 12

25 n.c.

002aaa604

Fig 3. LQFP48 pin conﬁguration.

terminal 1

index area

D5

D6

1

2

3

4

5

6

7

8

24 RESET

23 OUT

22 DTR

21 RTS

20 INT

D7

RCLK

RX

SC16C650BIBS

(top view)

TX

19 RXRDY

18 A0

CS

BAUDOUT

17 A1

002aaa947

Fig 4. HVQFN32 pin conﬁguration (top view).

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Product data

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5 of 51

SC16C650B

UART with 32-byte FIFOs and IrDA encoder/decoder

Philips Semiconductors

D0

D1

1

2

3

4

5

6

7

8

9

40 V

CC

39 RI

D2

38 DCD

37 DSR

36 CTS

35 RESET

34 OUT1

33 DTR

32 RTS

31 OUT2

30 INT

D3

D4

D5

D6

D7

RCLK

RX 10

TX 11

CS0 12

29 RXRDY

28 A0

CS1 13

CS2 14

27 A1

BAUDOUT 15

XTAL1 16

XTAL2 17

IOW 18

26 A2

25 AS

24 TXRDY

23 DDIS

22 IOR

21 IOR

IOW 19

GND 20

002aaa605

Fig 5. DIP40 pin conﬁguration.

5.2 Pin description

Table 2:

Symbol

Pin description

Type Description

PLCC44 LQFP48 HVQFN32 DIP40

A0-A2

AS

31, 30,

29

28, 27, 18, 17, 16 28,

I

Register select. A0-A2 are used during read and write

operations to select the UART register to read from or write

to. Refer to Table 3 for register addresses and refer to AS

description.

26

27, 26

28

24

-

25

15

Address strobe. When AS is active (LOW), A0, A1, and A2

and CS0, CS1, and CS2 drive the internal select logic

directly; when AS is HIGH, the register select and chip select

signals are held at the logic levels they were in when the

LOW-to-HIGH transition of AS occurred.

BAUDOUT 17

12

8

O

Baud out. BAUDOUT is a 16× clock signal for the

transmitter section of the UART. The clock rate is established

by the reference oscillator frequency divided by a divisor

speciﬁed in the baud generator divisor latches. BAUDOUT

may also be used for the receiver section by tying this output

to RCLK.

9397 750 14451

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Rev. 03 — 10 December 2004

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SC16C650B

UART with 32-byte FIFOs and IrDA encoder/decoder

Philips Semiconductors

Table 2:

Symbol

Pin description…continued

Type Description

PLCC44 LQFP48 HVQFN32 DIP40

CS0, CS1, 14, 15,

9, 10,

11

-

12,

13, 14

I

Chip select. When CS0 and CS1 are HIGH and CS2 is

LOW, these three inputs select the UART. When any of these

inputs are inactive, the UART remains inactive (refer to AS

description).

CS2

16

CS

-

7

-

I

CTS

40

38

25

36

Clear to send. CTS is a modem status signal. Its condition

can be checked by reading bit 4 (CTS) of the modem status

register. Bit 0 (∆CTS) of the modem status register indicates

that CTS has changed states since the last read from the

modem status register. If the modem status interrupt is

enabled when CTS changes levels and the auto-CTS mode

is not enabled, an interrupt is generated. CTS is also used in

the auto-CTS mode to control the transmitter.

D7-D0

DCD

9-2

42

4-2,

47-43

3-1, 32-28 8-1

I/O

I

Data bus. Eight data lines with 3-State outputs provide a

bi-directional path for data, control and status information

between the UART and the CPU.

40

-

38

Data carrier detect. DCD is a modem status signal. Its

condition can be checked by reading bit 7 (DCD) of the

modem status register. Bit 3 (∆DCD) of the modem status

register indicates that DCD has changed states since the

last read from the modem status register. If the modem

status interrupt is enabled when DCD changes levels, an

interrupt is generated.

DDIS

DSR

26

41

22

39

-

23

37

O

I

Driver disable. DDIS is active (LOW) when the CPU is not

reading data. When active, DDIS can disable an external

transceiver.

26

Data set ready. DSR is a modem status signal. Its condition

can be checked by reading bit 5 (DSR) of the modem status

register. Bit 1 (∆DSR) of the modem status register indicates

DSR has changed levels since the last read from the modem

status register. If the modem status interrupt is enabled

when DSR changes levels, an interrupt is generated.

DTR

INT

37

33

30

22

20

33

30

O

Data terminal ready. When active (LOW), DTR informs a

modem or data set that the UART is ready to establish

communication. DTR is placed in the active level by setting

the DTR bit of the modem control register. DTR is placed in

the inactive level either as a result of a Master Reset, during

loop mode operation, or clearing the DTR bit.

Interrupt. When active (HIGH), INT informs the CPU that

the UART has an interrupt to be serviced. Four conditions

that cause an interrupt to be issued are: a receiver error,

received data that is available or timed out (FIFO mode

only), an empty transmitter holding register or an enabled

modem status interrupt. INT is reset (deactivated) either

when the interrupt is serviced or as a result of a Master

Reset.

9397 750 14451

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Rev. 03 — 10 December 2004

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SC16C650B

UART with 32-byte FIFOs and IrDA encoder/decoder

Philips Semiconductors

Table 2:

Symbol

Pin description…continued

Type Description

PLCC44 LQFP48 HVQFN32 DIP40

OUT1,

OUT2

38, 35

34, 31

-

34, 31

O

Outputs 1 and 2. These are user-designated output

terminals that are set to the active (low) level by setting

respective modem control register (MCR) bits (OUT1 and

OUT2). OUT1 and OUT2 are set to inactive the (HIGH) level

as a result of Master Reset, during loop mode operations, or

by clearing bit 2 (OUT1) or bit 3 (OUT2) of the MCR.

OUT

-

23

-

RCLK

10

5

4

9

I

Receiver clock. RCLK is the 16× baud rate clock for the

receiver section of the UART.

IOR

25

24

20

19

-

22

21

I

Read inputs. When either IOR or IOR is active (LOW or

HIGH, respectively) while the UART is selected, the CPU is

allowed to read status information or data from a selected

UART register. Only one of these inputs is required for the

transfer of data during a read operation; the other input

should be tied to its inactive level (i.e., IOR tied LOW or IOR

tied HIGH).

14

RESET

RI

39

43

35

41

24

-

35

39

I

Master Reset. When active (HIGH), MR clears most UART

registers and sets the levels of various output signals.

Ring indicator. RI is a modem status signal. Its condition

can be checked by reading bit 6 (RI) of the modem status

register. Bit 2 (∆RI) of the modem status register indicates

that RI has transitioned from a LOW to a HIGH level since

the last read from the modem status register. If the modem

status interrupt is enabled when this transition occurs, an

interrupt is generated.

RTS

36

32

29

21

19

32

29

O

Request to send. When active, RTS informs the modem or

data set that the UART is ready to receive data. RTS is set to

the active level by setting the RTS modem control register bit

and is set to the inactive (HIGH) level either as a result of a

Master Reset or during loop mode operations or by clearing

bit 1 (RTS) of the MCR. In the auto-RTS mode, RTS is set to

the inactive level by the receiver threshold control logic.

RXRDY

Receiver ready. Receiver direct memory access (DMA)

signaling is available with RXRDY. When operating in the

FIFO mode, one of two types of DMA signaling can be

selected using the FIFO control register bit 3 (FCR[3]).

When operating in the 16C450 mode, only DMA mode 0 is

allowed. Mode 0 supports single-transfer DMA in which a

transfer is made between CPU bus cycles. Mode 1 supports

multi-transfer DMA in which multiple transfers are made

continuously until the receiver FIFO has been emptied. In

DMA mode 0 (FCR0 = 0 or FCR0 = 1, FCR3 = 0), when

there is at least one character in the receiver FIFO or

receiver holding register, RXRDY is active (LOW). When

RXRDY has been active but there are no characters in the

FIFO or holding register, RXRDY goes inactive (HIGH). In

DMA mode 1 (FCR0 = 1, FCR3 = 1), when the trigger level

or the time-out has been reached, RXRDY goes active

(LOW); when it has been active but there are no more

characters in the FIFO or holding register, it goes inactive

(HIGH).

9397 750 14451

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SC16C650B

UART with 32-byte FIFOs and IrDA encoder/decoder

Philips Semiconductors

Table 2:

Symbol

Pin description…continued

Type Description

PLCC44 LQFP48 HVQFN32 DIP40

RX

TX

11

7

5

10

I

Serial data input. RX is serial data input from a connected

communications device.

13

8

6

11

O

Serial data output. TX is composite serial data output to a

connected communication device. TX is set to the marking

(HIGH) level as a result of Master Reset.

TXRDY

27

23

15

24

O

Transmitter ready. Transmitter DMA signaling is available

with TXRDY. When operating in the FIFO mode, one of two

types of DMA signaling can be selected using FCR[3]. When

operating in the 16C450 mode, only DMA mode 0 is allowed.

Mode 0 supports single-transfer DMA in which a transfer is

made between CPU bus cycles. Mode 1 supports

multi-transfer DMA in which multiple transfers are made

continuously until the transmit FIFO has been ﬁlled.

V_CC

44

22

21

20

42

18

17

16

27

13

-

40

20

19

18

Power 2.5 V, 3 V or 5 V supply voltage.

Power Ground voltage.

GND

IOW

I

Write inputs. When either IOW or IOW is active (LOW or

HIGH, respectively) and while the UART is selected, the

CPU is allowed to write control words or data into a selected

UART register. Only one of these inputs is required to

transfer data during a write operation; the other input should

be tied to its inactive level (i.e., IOW tied LOW or IOW tied

HIGH).

11

XTAL1

XTAL2^[1]

18

19

14

15

9

16

17

I

Crystal connection or External clock input.

10

O

Crystal connection or the inversion of XTAL1 if XTAL1 is

driven.

n.c.

1, 12,

23, 34

1, 6, 13, 12

21, 25,

36, 37,

48

-

not connected

[1] In sleep mode, XTAL2 is left ﬂoating.

9397 750 14451

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SC16C650B

UART with 32-byte FIFOs and IrDA encoder/decoder

Philips Semiconductors

6. Functional description

The SC16C650B provides serial asynchronous receive data synchronization,

parallel-to-serial and serial-to-parallel data conversions for both the transmitter and

receiver sections. These functions are necessary for converting the serial data

stream into parallel data that is required with digital data systems. Synchronization for

the serial data stream is accomplished by adding start and stop bits to the transmit

data to form a data character (character orientated protocol). Data integrity is insured

by attaching a parity bit to the data character. The parity bit is checked by the receiver

for any transmission bit errors. The SC16C650B is fabricated with an advanced

CMOS process to achieve low drain power and high speed requirements.

The SC16C650B is an upward solution that provides 32 bytes of transmit and receive

FIFO memory, instead of none in the 16C450, or 16 in the 16C550. The SC16C650B

is designed to work with high speed modems and shared network environments that

require fast data processing time. Increased performance is realized in the

SC16C650B by the larger transmit and receive FIFOs. This allows the external

processor to handle more networking tasks within a given time. In addition, the four

selectable levels of FIFO trigger interrupt and automatic hardware/software ﬂow

control is uniquely provided for maximum data throughput performance, especially

when operating in a multi-channel environment. The combination of the above greatly

reduces the bandwidth requirement of the external controlling CPU, increases

performance, and reduces power consumption.

The SC16C650B is capable of operation up to 3 Mbit/s with a 48 MHz external clock

input (at 5 V).

The rich feature set of the SC16C650B is available through internal registers.

Automatic hardware/software ﬂow control, selectable transmit and receive FIFO

trigger level, selectable TX and RX baud rates, modem interface controls, and a sleep

mode are some of these features.

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SC16C650B

UART with 32-byte FIFOs and IrDA encoder/decoder

Philips Semiconductors

6.1 Internal registers

The SC16C650B provides 17 internal registers for monitoring and control. These

registers are shown in Table 3. Twelve registers are similar to those already available

in the standard 16C550. These registers function as data holding registers

(THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control register

(FCR), line status and control registers (LCR/LSR), modem status and control

registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM),

and a user accessible scratchpad register (SPR). Beyond the general 16C550

features and capabilities, the SC16C650B offers an enhanced feature register set

(EFR, Xon/Xoff1-2) that provides on-board hardware/software ﬂow control. Register

functions are more fully described in the following paragraphs.

Table 3:

A2

Internal registers decoding

A0 READ mode

A1

WRITE mode

General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR)^[1]

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Receive Holding Register

Interrupt Enable Register

Interrupt Status Register

Line Control Register

Modem Control Register

Line Status Register

Transmit Holding Register

Interrupt Enable Register

FIFO Control Register

Line Control Register

Modem Control Register

n/a

Modem Status Register

n/a

Scratchpad Register

Baud rate register set (DLL/DLM)^[2]

0

LSB of Divisor Latch

MSB of Divisor Latch

0

1

MSB of Divisor Latch

Enhanced register set (EFR, Xon/off 1-2)^[3]

0

1

0

1

0

1

0

1

Enhanced Feature Register

Xon1 word

Enhanced Feature Register

Xon1 word

Xon2 word

Xoff1 word

Xoff2 word

[1] These registers are accessible only when LCR[7] is a logic 0.

[2] These registers are accessible only when LCR[7] is a logic 1.

[3] Enhanced Feature Register, Xon1, 2 and Xoff1, 2 are accessible only when the LCR is set to “BF”

(HEX).

6.2 FIFO operation

The 32-byte transmit and receive data FIFOs are enabled by the FIFO Control

Register bit-0 (FCR[0]). With 16C550 devices, the user can set the receive trigger

level, but not the transmit trigger level. The SC16C650B provides independent trigger

levels for both receiver and transmitter. To remain compatible with SC16C550, the

transmit interrupt trigger level is set to 16 following a reset. It should be noted that the

user can set the transmit trigger levels by writing to the FCR register, but activation

will not take place until EFR[4] is set to a logic 1. The receiver FIFO section includes

9397 750 14451

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SC16C650B

UART with 32-byte FIFOs and IrDA encoder/decoder

Philips Semiconductors

a time-out function to ensure data is delivered to the external CPU. An interrupt is

generated whenever the Receive Holding Register (RHR) has not been read

following the loading of a character or the receive trigger level has not been reached.

Table 4:

Flow control mechanism

Selected trigger level

(characters)

INT pin activation

Negate RTS or

send Xoff

Assert RTS or

send Xon

8

0

16

24

28

16

24

28

16

24

28

7

15

23

6.3 Hardware ﬂow control

When automatic hardware ﬂow control is enabled, the SC16C650B monitors the CTS

pin for a remote buffer overﬂow indication and controls the RTS pin for local buffer

overﬂows. Automatic hardware ﬂow control is selected by setting EFR[6] (RTS) and

EFR[7] (CTS) to a logic 1. If CTS transitions from a logic 0 to a logic 1 indicating a

ﬂow control request, ISR[5] will be set to a logic 1 (if enabled via IER[6,7]), and the

SC16C650B will suspend TX transmissions as soon as the stop bit of the character in

process is shifted out. Transmission is resumed after the CTS input returns to a

logic 0, indicating more data may be sent.

With the Auto-RTS function enabled, an interrupt is generated when the receive FIFO

reaches the programmed trigger level. The RTS pin will not be forced to a logic 1

(RTS off), until the receive FIFO reaches the next trigger level. However, the RTS pin

will return to a logic 0 after the data buffer (FIFO) is unloaded to the next trigger level

below the programmed trigger level. However, under the above described conditions,

the SC16C650B will continue to accept data until the receive FIFO is full.

6.4 Software ﬂow control

When software ﬂow control is enabled, the SC16C650B compares one or two

sequential receive data characters with the programmed Xon or Xoff character

value(s). If received character(s) match the programmed Xoff values, the

SC16C650B will halt transmission (TX) as soon as the current character(s) has

completed transmission. When a match occurs, the receive ready (if enabled via Xoff

IER[5]) ﬂags will be set and the interrupt output pin (if receive interrupt is enabled) will

be activated. Following a suspension due to a match of the Xoff characters’ values,

the SC16C650B will monitor the receive data stream for a match to the Xon1,2

character value(s). If a match is found, the SC16C650B will resume operation and

clear the ﬂags (ISR[4]).

Reset initially sets the contents of the Xon/Xoff 8-bit ﬂow control registers to a logic 0.

Following reset, the user can write any Xon/Xoff value desired for software ﬂow

control. Different conditions can be set to detect Xon/Xoff characters and

suspend/resume transmissions. When double 8-bit Xon/Xoff characters are selected,

the SC16C650B compares two consecutive receive characters with two software ﬂow

control 8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions

accordingly. Under the above described ﬂow control mechanisms, ﬂow control

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SC16C650B

UART with 32-byte FIFOs and IrDA encoder/decoder

Philips Semiconductors

characters are not placed (stacked) in the user accessible RX data buffer or FIFO.

When using a software ﬂow control the Xon/Xoff characters cannot be used for data

transfer.

In the event that the receive buffer is overﬁlling and ﬂow control needs to be executed,

the SC16C650B automatically sends an Xoff message (when enabled) via the serial

TX output to the remote modem. The SC16C650B sends the Xoff1,2 characters as

soon as received data passes the programmed trigger level. To clear this condition,

the SC16C650B will transmit the programmed Xon1,2 characters as soon as receive

data drops below the next low or programmed trigger level.

6.5 Special feature software ﬂow control

A special feature is provided to detect an 8-bit character when EFR[5] is set. When

8-bit character is detected, it will be placed on the user-accessible data stack along

with normal incoming RX data. This condition is selected in conjunction with

EFR[0:3]. Note that software ﬂow control should be turned off when using this special

mode by setting EFR[0:3] to a logic 0.

The SC16C650B compares each incoming receive character with Xoff2 data. If a

match exists, the received data will be transferred to the FIFO, and ISR[4] will be set

to indicate detection of a special character. Although the Internal Register Table

(Table 8) shows each X-Register with eight bits of character information, the actual

number of bits is dependent on the programmed word length. Line Control Register

bits LCR[0:1] deﬁne the number of character bits, i.e., either 5 bits, 6 bits, 7 bits or

8 bits. The word length selected by LCR[0:1] also determine the number of bits that

will be used for the special character comparison. Bit 0 in the X-registers corresponds

with the LSB bit for the receive character.

6.6 Hardware/software and time-out interrupts

Three special interrupts have been added to monitor the hardware and software ﬂow

control. The interrupts are enabled by IER[5:7]. Care must be taken when handling

these interrupts. Following a reset, the transmitter interrupt is enabled, the

SC16C650B will issue an interrupt to indicate that the Transmit Holding Register is

empty. This interrupt must be serviced prior to continuing operations. The ISR

register provides the current singular highest priority interrupt only. It could be noted

that CTS and RTS interrupts have lowest interrupt priority. A condition can exist

where a higher priority interrupt may mask the lower priority CTS/RTS interrupt(s).

Only after servicing the higher pending interrupt will the lower priority CTS/TRS

interrupt(s) be reﬂected in the status register. Servicing the interrupt without

investigating further interrupt conditions can result in data errors.

When two interrupt conditions have the same priority, it is important to service these

interrupts correctly. Receive Data Ready and Receive Time Out have the same

interrupt priority (when enabled by IER[0]). The receiver issues an interrupt after the

number of characters have reached the programmed trigger level. In this case, the

SC16C650B FIFO may hold more characters than the programmed trigger level.

Following the removal of a data byte, the user should re-check LSR[0] for additional

characters. A Receive Time Out will not occur if the receive FIFO is empty. The

time-out counter is reset at the center of each stop bit received or each time the

receive holding register (RHR) is read. The actual time-out value is 4 character time.

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6.7 Programmable baud rate generator

The SC16C650B supports high speed modem technologies that have increased

input data rates by employing data compression schemes. For example, a 33.6 kbit/s

modem that employs data compression may require a 115.2 kbit/s input data rate.

A 128.0 kbit/s ISDN modem that supports data compression may need an input

data rate of 460.8 kbit/s.

A single baud rate generator is provided for the transmitter and receiver, allowing

independent TX/RX channel control. The programmable Baud Rate Generator is

capable of accepting an input clock up to 48 MHz, as required for supporting a

3 Mbit/s data rate. The SC16C650B can be conﬁgured for internal or external clock

operation. For internal clock oscillator operation, an industry standard microprocessor

crystal (parallel resonant/22-33 pF load) is connected externally between the XTAL1

and XTAL2 pins (see Figure 6). Alternatively, an external clock can be connected to

the XTAL1 pin to clock the internal baud rate generator for standard or custom rates

(see Table 5).

1.5 kΩ

X1

1.8432 MHz

C1

22 pF

C2

33 pF

C1

22 pF

C2

47 pF

002aaa586

Fig 6. Crystal oscillator connection.

The generator divides the input 16× clock by any divisor from 1 to 2¹⁶− 1. The

SC16C650B divides the basic crystal or external clock by 16. The frequency of the

BAUDOUT output pin is exactly 16× (16 times) of the selected baud rate

(BAUDOUT = 16 Baud Rate). Customized baud rates can be achieved by selecting

the proper divisor values for the MSB and LSB sections of baud rate generator.

Setting MCR[7] to a logic 1 provides an additional divide-by-4, whereas setting

MCR[7] to a logic 0 only divides by 1 (see Table 5 and Figure 7).

Programming the Baud Rate Generator registers DLM (MSB) and DLL (LSB)

provides a user capability for selecting the desired ﬁnal baud rate. The example in

Table 5 shows selectable baud rates when using a 1.8432 MHz crystal and setting

MCR[7] to a logic 0.

For custom baud rates, the divisor value can be calculated using the following

equation:

XTAL1 clock frequency

serial data rate × 16

Divisor (in decimal) =

(1)

----------------------------------------------------------

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Table 5:

Baud rates using 1.8432 MHz or 3.072 MHz crystal

Using 3.072 MHz crystal

Using 1.8432 MHz crystal

Desired

baud rate

Divisor for

16× clock

Baud rate

error

Desired

baud rate

Divisor for

16× clock

Baud rate

error

50

2304

1536

1047

857

768

384

192

96

50

3840

2560

1745

1428

1280

640

320

160

107

96

75

110

0.026

0.058

110

0.026

0.034

134.5

150

134.5

150

300

600

1200

1800

2000

2400

3600

4800

7200

9600

19200

38400

56000

1200

1800

2000

2400

3600

4800

7200

9600

19200

38400

64

0.312

58

0.69

48

80

32

53

0.628

1.23

24

40

16

27

12

20

6

10

3

5

2

2.86

MCR[7] = 0

DIVIDE-BY-1

LOGIC

XTAL1

XTAL2

CLOCK

OSCILLATOR

LOGIC

BAUD RATE

GENERATOR

LOGIC

BAUDOUT

002aaa208

DIVIDE-BY-4

LOGIC

MCR[7] = 1

Fig 7. Baud rate generator circuitry.

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UART with 32-byte FIFOs and IrDA encoder/decoder

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6.8 DMA operation

The SC16C650B FIFO trigger level provides additional ﬂexibility to the user for block

mode operation. The user can optionally operate the transmit and receive FIFOs in

the DMA mode (FCR[3]). The DMA mode affects the state of the RXRDY and TXRDY

output pins. Tables 6 and 7 show this.

Table 6:

Effect of DMA mode on state of RXRDY pin

Non-DMA mode

DMA mode

1 = FIFO empty

0-to-1 transition when FIFO empties

0 = at least 1 byte in FIFO

1-to-0 transition when FIFO reaches trigger level,

or time-out occurs

Table 7:

Effect of DMA mode on state of TXRDY pin

Non-DMA mode

1 = at least 1 byte in FIFO

0 = FIFO empty

DMA mode

0-to-1 transition when FIFO becomes full

1-to-0 transition when FIFO has 1 empty space

6.9 Sleep mode

The SC16C650B is designed to operate with low power consumption. A special sleep

mode is included to further reduce power consumption when the chip is not being

used. With EFR[4] and IER[4] enabled (set to a logic 1), the SC16C650B enters the

sleep mode, but resumes normal operation when a start bit is detected, a change of

state on any of the modem input pins RI, CTS, DSR, DCD, RX pin, or a transmit data

is provided by the user. If the sleep mode is enabled and the SC16C650B is

awakened by one of the conditions described above, it will return to the sleep mode

automatically after the last character is transmitted or read by the user. In any case,

the sleep mode will not be entered while an interrupt(s) is pending. The SC16C650B

will stay in the sleep mode of operation until it is disabled by setting IER[4] to a

logic 0.

6.10 Loop-back mode

The internal loop-back capability allows on-board diagnostics. In the loop-back mode,

the normal modem interface pins are disconnected and reconﬁgured for loop-back

internally. MCR[0:3] register bits are used for controlling loop-back diagnostic testing.

In the loop-back mode, OUT1 and OUT2 in the MCR register (bits 2:3) control the

modem RI and DCD inputs, respectively. MCR signals DTR and RTS (bits 0:1) are

used to control the modem DSR and CTS inputs, respectively. The transmitter output

(TX) and the receiver input (RX) are disconnected from their associated interface

pins, and instead are connected together internally (see Figure 8). The CTS, DSR,

DCD, and RI are disconnected from their normal modem control input pins, and

instead are connected internally to DTR, RTS, OUT1 and OUT2. Loop-back test data

is entered into the transmit holding register via the user data bus interface, D0-D7.

The transmit UART serializes the data and passes the serial data to the receive

UART via the internal loop-back connection. The receive UART converts the serial

data back into parallel data that is then made available at the user data interface

D0-D7. The user optionally compares the received data to the initial transmitted data

for verifying error-free operation of the UART TX/RX circuits.

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In this mode, the receiver and transmitter interrupts are fully operational. The Modem

Control Interrupts are also operational. However, the interrupts can only be read

using lower four bits of the Modem Status Register (MSR[0:3]) instead of the four

Modem Status Register bits 4:7. The interrupts are still controlled by the IER.

SC16C650B

TRANSMIT

FIFO

TRANSMIT

SHIFT

TX

REGISTERS

REGISTER

D0–D7

IOR, IOR

IOW, IOW

RESET

DATA BUS

AND

CONTROL LOGIC

FLOW

CONTROL

LOGIC

IR

ENCODER

RECEIVE

SHIFT

REGISTER

RECEIVE

FIFO

REGISTERS

RX

A0–A2

CS0, CS1

FLOW

CONTROL

LOGIC

IR

DECODER

REGISTER

SELECT

LOGIC

CS2

AS

RTS

DDIS

CTS

DTR

MODEM

CONTROL

LOGIC

DSR

OUT1

RI

INT

TXRDY

RXRDY

CLOCK AND

BAUD RATE

GENERATOR

INTERRUPT

CONTROL

LOGIC

OUT2

DCD

002aaa606

XTAL1

RCLK

XTAL2

BAUDOUT

Fig 8. Internal loop-back mode diagram.

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UART with 32-byte FIFOs and IrDA encoder/decoder

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7. Register descriptions

Table 8 details the assigned bit functions for the ﬁfteen SC16C650B internal registers.

The assigned bit functions are more fully deﬁned in Section 7.1 through Section 7.11.

Table 8:

SC16C650B internal registers

Shaded bits are only accessible when EFR[4] is set.

A2 A1 A0 Register Default^[1]Bit 7

General Register Set^[2]

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

1

RHR

THR

IER

XX

00

bit 7

CTS

bit 6

RTS

bit 5

Xoff

bit 4

bit 3

bit 2

bit 1

bit 0

bit 4

Sleep

modem receive

status line status holding holding

interrupt interrupt register register

transmit receive

interrupt interrupt interrupt mode

0

1

0

1

0

1

FCR

ISR

00

01

00

60

RCVR

trigger

(MSB)

RCVR

trigger

(LSB)

TX

trigger

(MSB)

TXtrigger DMA

XMIT

FIFO

reset

RCVR

FIFO

reset

FIFO

enable

(LSB)

mode

select

FIFOs

INT

priority

bit 1

INT

priority

bit 0

INT

status

enabled enabled priority

bit 4

priority

bit 3

priority

bit 2

LCR

MCR

LSR

divisor

latch

enable

set break set parity even

parity

stop bits

OUT1

word

length

bit 1

word

length

bit 0

parity

enable

Clock

select

IR enable INT type loop back OUT2,

RTS

DTR

select

INT

enable

FIFO

data

error

trans.

empty

trans.

holding

empty

break

framing parity

overrun receive

error

interrupt error

error

data

ready

1

0

1

MSR

SPR

X0

FF

DCD

bit 7

RI

DSR

bit 5

CTS

bit 4

∆DCD

∆RI

∆DSR

∆CTS

bit 6

bit 3

bit 2

bit 1

bit 0

Special Register Set^[3]

0

DLL

XX

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 9

bit 0

bit 8

0

1

DLM

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

Enhanced Register Set^[4]

0

1

0

EFR

00

Auto

CTS

Auto RTS Special Enable

Cont-3

Cont-2

Tx, Rx

Control

Cont-1

Tx, Rx

Control Control

Cont-0

Tx, Rx

char.

IER[4:7], Tx, Rx

ISR[4,5], Control

FCR[4,5],

select

MCR[5:7]

1

0

1

0

1

0

1

Xon-1

Xon-2

Xoff-1

Xoff-2

00

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 9

bit 1

bit 9

bit 0

bit 8

bit 0

bit 8

bit 15

bit 7

bit 14

bit 6

bit 13

bit 5

bit 12

bit 4

bit 11

bit 3

bit 10

bit 2

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

[1] The value shown represents the register’s initialized HEX value; X = n/a.

[2] These registers are accessible only when LCR[7] = 0.

[3] The Special Register set is accessible only when LCR[7] is set to a logic 1.

[4] Enhanced Feature Register, Xon-1,2 and Xoff-1,2 are accessible only when LCR is set to ‘BF_Hex’.

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UART with 32-byte FIFOs and IrDA encoder/decoder

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7.1 Transmit (THR) and Receive (RHR) Holding Registers

The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and

Transmit Shift Register (TSR). The status of the THR is provided in the Line Status

Register (LSR). Writing to the THR transfers the contents of the data bus (D7-D0) to

the THR, providing that the THR or TSR is empty. The THR empty ﬂag in the LSR

register will be set to a logic 1 when the transmitter is empty or when data is

transferred to the TSR. Note that a write operation can be performed when the THR

empty ﬂag is set (logic 0 = FIFO full; logic 1 = at least one FIFO location available).

The serial receive section also contains an 8-bit Receive Holding Register (RHR).

Receive data is removed from the SC16C650B and receive FIFO by reading the RHR

register. The receive section provides a mechanism to prevent false starts. On the

falling edge of a start or false start bit, an internal receiver counter starts counting

clocks at the 16× clock rate. After 7-¹⁄₂clocks, the start bit time should be shifted to

the center of the start bit. At this time the start bit is sampled, and if it is still a logic 0

it is validated. Evaluating the start bit in this manner prevents the receiver from

assembling a false character. Receiver status codes will be posted in the LSR.

7.2 Interrupt Enable Register (IER)

The Interrupt Enable Register (IER) masks the interrupts from receiver ready,

transmitter empty, line status and modem status registers. These interrupts would

normally be seen on the INT output pin.

Table 9:

Interrupt Enable Register bits description

Description

Bit

Symbol

IER[7]

7

CTS interrupt.

Logic 0 = Disable the CTS interrupt (normal default condition).

Logic 1 = Enable the CTS interrupt. The SC16C650B issues an interrupt

when the CTS pin transitions from a logic 0 to a logic 1.

6

5

IER[6]

IER[5]

RTS interrupt.

Logic 0 = Disable the RTS interrupt (normal default condition).

Logic 1 = Enable the RTS interrupt. The SC16C650B issues an interrupt

when the RTS pin transitions from a logic 0 to a logic 1.

Xoff interrupt.

Logic 0 = Disable the software ﬂow control, receive Xoff interrupt

(normal default condition).

Logic 1 = Enable the software ﬂow control, receive Xoff interrupt. See

Section 6.4 “Software ﬂow control” for details.

4

3

IER[4]

IER[3]

Sleep mode.

Logic 0 = Disable sleep mode (normal default condition).

Logic 1 = Enable sleep mode. See Section 6.9 “Sleep mode” for details.

Modem Status Interrupt.

Logic 0 = Disable the modem status register interrupt (normal default

condition).

Logic 1 = Enable the modem status register interrupt.

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UART with 32-byte FIFOs and IrDA encoder/decoder

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Table 9:

Interrupt Enable Register bits description…continued

Bit

Symbol

Description

2

IER[2]

Receive Line Status interrupt. This interrupt will be issued whenever a fully

assembled receive character is transferred from RSR to the RHR/FIFO,

i.e., data ready, LSR[0].

Logic 0 = Disable the receiver line status interrupt (normal default

condition).

Logic 1 = Enable the receiver line status interrupt.

1

0

IER[1]

IER[0]

Transmit Holding Register interrupt. This interrupt will be issued whenever

the THR is empty, and is associated with LSR[1].

Logic 0 = Disable the transmitter empty interrupt (normal default

condition).

Logic 1 = Enable the transmitter empty interrupt.

Receive Holding Register interrupt. This interrupt will be issued when the

FIFO has reached the programmed trigger level, or is cleared when the

FIFO drops below the trigger level in the FIFO mode of operation.

Logic 0 = Disable the receiver ready interrupt (normal default condition).

Logic 1 = Enable the receiver ready interrupt.

7.2.1 IER versus Receive FIFO interrupt mode operation

When the receive FIFO (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1)

are enabled, the receive interrupts and register status will reﬂect the following:

• The receive data available interrupts are issued to the external CPU when the

FIFO has reached the programmed trigger level. It will be cleared when the FIFO

drops below the programmed trigger level.

• FIFO status will also be reﬂected in the user accessible ISR register when the

FIFO trigger level is reached. Both the ISR register status bit and the interrupt will

be cleared when the FIFO drops below the trigger level.

• The data ready bit (LSR[0]) is set as soon as a character is transferred from the

shift register to the receive FIFO. It is reset when the FIFO is empty.

7.2.2 IER versus Receive/Transmit FIFO polled mode operation

When FCR[0] = logic 1, resetting IER[0:3] enables the SC16C650B in the FIFO

polled mode of operation. Since the receiver and transmitter have separate bits in the

LSR, either or both can be used in the polled mode by selecting respective transmit or

receive control bit(s).

• LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.

• LSR[1:4] will provide the type of errors encountered, if any.

• LSR[5] will indicate when the transmit FIFO is empty.

• LSR[6] will indicate when both the transmit FIFO and transmit shift register are

empty.

• LSR[7] will indicate any FIFO data errors.

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7.3 FIFO Control Register (FCR)

This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO

trigger levels, and select the DMA mode.

7.3.1 DMA mode

Mode 0 (FCR bit 3 = 0): Set and enable the interrupt for each single transmit or

receive operation, and is similar to the 16C450 mode. Transmit Ready (TXRDY) will

go to a logic 0 whenever an empty transmit space is available in the Transmit Holding

Register (THR). Receive Ready (RXRDY) will go to a logic 0 whenever the Receive

Holding Register (RHR) is loaded with a character.

Mode 1 (FCR bit 3 = 1): Set and enable the interrupt in a block mode operation. The

transmit interrupt is set when the transmit FIFO is below the programmed trigger

level. The receive interrupt is set when the receive FIFO ﬁlls to the programmed

trigger level. However, the FIFO continues to ﬁll regardless of the programmed level

until the FIFO is full. RXRDY remains a logic 0 as long as the FIFO ﬁll level is above

the programmed trigger level.

7.3.2 FIFO mode

Table 10: FIFO Control Register bits description

Bit

Symbol

Description

7-6

FCR[7]

(MSB),

FCR[6]

(LSB)

RCVR trigger. These bits are used to set the trigger level for the receive

FIFO interrupt.

An interrupt is generated when the number of characters in the FIFO

equals the programmed trigger level. However, the FIFO will continue to

be loaded until it is full. Refer to Table 11.

5-4

FCR[5]

(MSB),

FCR[4]

(LSB)

Logic 0 or cleared is the default condition; TX trigger level = 16.

These bits are used to set the trigger level for the transmit FIFO

interrupt. The SC16C650B will issue a transmit empty interrupt when the

number of characters in FIFO drops below the selected trigger level.

Refer to Table 12.

3

FCR[3]

DMA mode select.

Logic 0 = Set DMA mode ‘0’ (normal default condition).

Logic 1 = Set DMA mode ‘1’

Transmit operation in mode ‘0’: When the SC16C650B is in the

16C450 mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode

(FIFOs enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there are

no characters in the transmit FIFO or transmit holding register, the

TXRDY pin will be a logic 0. Once active, the TXRDY pin will go to a

logic 1 after the ﬁrst character is loaded into the transmit holding

register.

Receive operation in mode ‘0’: When the SC16C650B is in 16C450

mode, or in the FIFO mode (FCR[0] = logic 1; FCR[3] = logic 0) and

there is at least one character in the receive FIFO, the RXRDY pin will

be a logic 0. Once active, the RXRDY pin will go to a logic 1 when there

are no more characters in the receiver.

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UART with 32-byte FIFOs and IrDA encoder/decoder

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Table 10: FIFO Control Register bits description…continued

Bit

Symbol

Description

Transmit operation in mode ‘1’: When the SC16C650B is in FIFO

mode (FCR[0] = logic 1; FCR[3] = logic 1), the TXRDY pin will be a

logic 1 when the transmit FIFO is completely full. It will be a logic 0 when

FIFO has 1 empty space.

Receive operation in mode ‘1’: When the SC16C650B is in FIFO

mode (FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been

reached, or a Receive Time-Out has occurred, the RXRDY pin will go to

a logic 0. Once activated, it will go to a logic 1 after there are no more

characters in the FIFO.

2

1

0

FCR[2]

FCR[1]

FCR[0]

XMIT FIFO reset.

Logic 0 = No FIFO transmit reset (normal default condition).

Logic 1 = Clears the contents of the transmit FIFO and resets the

FIFO counter logic (the transmit shift register is not cleared or

altered). This bit will return to a logic 0 after clearing the FIFO.

RCVR FIFO reset.

Logic 0 = No FIFO receive reset (normal default condition).

Logic 1 = Clears the contents of the receive FIFO and resets the FIFO

counter logic (the receive shift register is not cleared or altered). This

bit will return to a logic 0 after clearing the FIFO.

FIFO enable.

Logic 0 = Disable the transmit and receive FIFO (normal default

condition).

Logic 1 = Enable the transmit and receive FIFO. This bit must be a

‘1’ when other FCR bits are written to, or they will not be

programmed.

Table 11: RCVR trigger levels

FCR[7]

FCR[6]

RX FIFO trigger level (bytes)

0

1

0

1

0

1

8

16

24

28

Table 12: TX FIFO trigger levels

FCR[5]

FCR[4]

TX FIFO trigger level (bytes)

0

1

0

1

0

1

16

8

24

30

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7.4 Interrupt Status Register (ISR)

The SC16C650B provides six levels of prioritized interrupts to minimize external

software interaction. The Interrupt Status Register (ISR) provides the user with six

interrupt status bits. Performing a read cycle on the ISR will provide the user with the

highest pending interrupt level to be serviced. No other interrupts are acknowledged

until the pending interrupt is serviced. Whenever the interrupt status register is read,

the interrupt status is cleared. However, it should be noted that only the current

pending interrupt is cleared by the read. A lower level interrupt may be seen after

re-reading the interrupt status bits. Table 13 “Interrupt source” shows the data values

(bits 0:5) for the six prioritized interrupt levels and the interrupt sources associated

with each of these interrupt levels.

Table 13: Interrupt source

Priority ISR[5] ISR[4] ISR[3] ISR[2] ISR[1] ISR[0] Source of the interrupt

level

1

2

3

4

5

6

0

1

0

1

0

1

0

1

0

1

0

1

0

LSR (Receiver Line Status

Register)

RXRDY (Received Data

Ready)

RXRDY (Receive Data

time-out)

TXRDY (Transmitter

Holding Register Empty)

MSR (Modem Status

Register)

RXRDY (Received Xoff

signal) / Special character

CTS, RTS change of state

Table 14: Interrupt Status Register bits description

Bit

Symbol

Description

7:6

ISR[7:6]

FIFOs enabled. These bits are set to a logic 0 when the FIFO is

not being used. They are set to a logic 1 when the FIFOs are

enabled.

Logic 0 or cleared = default condition.

5:4

ISR[5:4]

INT priority bits 4:3. These bits are enabled when EFR[4] is set to

a logic 1. ISR[4] indicates that matching Xoff character(s) have

been detected. ISR[5] indicates that CTS, RTS have been

generated. Note that once set to a logic 1, the ISR[4] bit will stay a

logic 1 until Xon character(s) are received.

Logic 0 or cleared = default condition.

3:1

0

ISR[3:1]

ISR[0]

INT priority bits 2:0. These bits indicate the source for a pending

interrupt at interrupt priority levels 1, 2, and 3 (see Table 13).

Logic 0 or cleared = default condition.

INT status.

Logic 0 = An interrupt is pending and the ISR contents may be

used as a pointer to the appropriate interrupt service routine.

Logic 1 = No interrupt pending (normal default condition).

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UART with 32-byte FIFOs and IrDA encoder/decoder

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7.5 Line Control Register (LCR)

The Line Control Register is used to specify the asynchronous data communication

format. The word length, the number of stop bits, and the parity are selected by

writing the appropriate bits in this register.

Table 15: Line Control Register bits description

Bit

Symbol

Description

7

LCR[7]

Divisor latch enable. The internal baud rate counter latch and Enhance

Feature mode enable.

Logic 0 = Divisor latch disabled (normal default condition).

Logic 1 = Divisor latch and enhanced feature register enabled.

6

5

LCR[6]

LCR[5]

Set break. When enabled, the Break control bit causes a break condition

to be transmitted (the TX output is forced to a logic 0 state). This

condition exists until disabled by setting LCR[6] to a logic 0.

Logic 0 = no TX break condition (normal default condition).

Logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the

remote receiver to a line break condition.

Set parity. If the parity bit is enabled, LCR[5] selects the forced parity

format. Programs the parity conditions (see Table 16).

Logic 0 = parity is not forced (normal default condition).

LCR[5] = logic 1 and LCR[4] = logic 0: parity bit is forced to a logical 1

for the transmit and receive data.

LCR[5] = logic 1 and LCR[4] = logic 1: parity bit is forced to a logical 0

for the transmit and receive data.

4

LCR[4]

Even parity. If the parity bit is enabled with LCR[3] set to a logic 1,

LCR[4] selects the even or odd parity format.

Logic 0 = ODD Parity is generated by forcing an odd number of

logic 1s in the transmitted data. The receiver must be programmed to

check the same format (normal default condition).

Logic 1 = EVEN Parity is generated by forcing an even number of

logic 1s in the transmitted data. The receiver must be programmed to

check the same format.

3

LCR[3]

Parity enable. Parity or no parity can be selected via this bit.

Logic 0 = no parity (normal default condition).

Logic 1 = a parity bit is generated during the transmission, receiver

checks the data and parity for transmission errors.

2

LCR[2]

Stop bits. The length of stop bit is speciﬁed by this bit in conjunction with

the programmed word length (see Table 17).

Logic 0 or cleared = default condition.

1:0

LCR[1:0]

Word length bits 1, 0. These two bits specify the word length to be

transmitted or received (see Table 18).

Logic 0 or cleared = default condition.

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SC16C650B

UART with 32-byte FIFOs and IrDA encoder/decoder

Philips Semiconductors

Table 16: LCR[5] parity selection

LCR[5]

LCR[4]

LCR[3]

Parity selection

no parity

X

0

1

X

0

1

0

1

0

1

ODD parity

EVEN parity

force parity ‘1’

forced parity ‘0’

Table 17: LCR[2] stop bit length

LCR[2]

Word length

5, 6, 7, 8

5

Stop bit length (bit times)

0

1

1-¹⁄₂

6, 7, 8

2

Table 18: LCR[1:0] word length

LCR[1]

LCR[0]

Word length

0

1

0

1

0

1

5

6

7

8

7.6 Modem Control Register (MCR)

This register controls the interface with the modem or a peripheral device.

Table 19: Modem Control Register bits description

Bit

Symbol

Description

7

MCR[7]

Clock select.

Logic 0 = Divide-by-1. The input clock (crystal or external) is

divided by 16 and then presented to the Programmable Baud Rate

Generator (BGR) without further modiﬁcation, i.e., divide-by-1

(normal default condition).

Logic 1 = Divide-by-4. The divide-by-1 clock described in MCR[7]

equals a logic 0, is further divided by four (see also Section 6.7

“Programmable baud rate generator”).

6

MCR[6]

IR enable.

Logic 0 = Enable the standard modem receive and transmit

input/output interface (normal default condition).

Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs.

While in this mode, the TX/RX output/inputs are routed to the

infrared encoder/decoder. The data input and output levels will

conform to the IrDA infrared interface requirement. As such, while

in this mode, the infrared TX output will be a logic 0 during idle data

conditions.

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UART with 32-byte FIFOs and IrDA encoder/decoder

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Table 19: Modem Control Register bits description…continued

Bit

Symbol

Description

5

MCR[5]

INT typ select.

Logic 0 = Enable active or 3-State interrupt output mode (normal

default condition).

Logic= 1 = Enable open source interrupt output mode. Provides

shared interrupts in the STD mode by producing a wire-OR output

driver capability for interrupts. This output appears at the IRQA/INT

pin. When using this option, an external pull-down resistor of

200 to 500 Ω must be tied from the IRQA/INT pin to ground to

provide and acceptable logic 0 level

4

MCR[4]

Loop-back. Enable the local loop-back mode (diagnostics). In this

mode the transmitter output (TX) and the receiver input (RX), CTS,

DSR, DCD, and RI are disconnected from the SC16C650B I/O pins.

Internally the modem data and control pins are connected into a

loop-back data conﬁguration (see Figure 8). In this mode, the receiver

and transmitter interrupts remain fully operational. The Modem

Control Interrupts are also operational, but the interrupts’ sources are

switched to the lower four bits of the Modem Control. Interrupts

continue to be controlled by the IER register.

Logic 0 = Disable loop-back mode (normal default condition).

Logic 1 = Enable local loop-back mode (diagnostics).

3

MCR[3]

OUT2, INTx enable. Used to control the modem DCD signal in the

loop-back mode.

Logic 0 = Forces INT output to the 3-State mode. In the loop-back

mode, sets OUT2 (DCD) internally to a logic 1.

Logic 1 = Forces the INT output to the active mode. In the

loop-back mode, sets OUT2 (DCD) internally to a logic 0.

2

1

MCR[2]

MCR[1]

OUT1. This bit is used in the Loop-back mode only. In the loop-back

mode, this bit is used to write the state of the modem RI interface

signal via OUT1.

RTS

Logic 0 = Force RTS output to a logic 1 (normal default condition).

Logic 1 = Force RTS output to a logic 0.

DTR

0

MCR[0]

Logic 0 = Force DTR output to a logic 1 (normal default condition).

Logic 1 = Force DTR output to a logic 0.

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UART with 32-byte FIFOs and IrDA encoder/decoder

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7.7 Line Status Register (LSR)

This register provides the status of data transfers between the SC16C650B and

the CPU.

Table 20: Line Status Register bits description

Bit

Symbol

Description

7

LSR[7]

FIFO data error.

Logic 0 = No error (normal default condition).

Logic 1 = At least one parity error, framing error or break indication is in

the current FIFO data. This bit is cleared when LSR register is read.

6

5

LSR[6]

LSR[5]

THR and TSR empty. This bit is the Transmit Empty indicator. This bit is

set to a logic 1 whenever the transmit holding register and the transmit

shift register are both empty. It is reset to logic 0 whenever either the THR

or TSR contains a data character. In the FIFO mode, this bit is set to ‘1’

whenever the transmit FIFO and transmit shift register are both empty.

THR empty. This bit is the Transmit Holding Register Empty indicator.

This bit indicates that the UART is ready to accept a new character for

transmission. In addition, this bit causes the UART to issue an interrupt to

CPU when the THR interrupt enable is set. The THR bit is set to a logic 1

when a character is transferred from the transmit holding register into the

transmitter shift register. The bit is reset to a logic 0 concurrently with the

loading of the transmitter holding register by the CPU. In the FIFO mode,

this bit is set when the transmit FIFO is empty; it is cleared when at least

1 byte is written to the transmit FIFO.

4

3

2

1

LSR[4]

LSR[3]

LSR[2]

LSR[1]

Break interrupt.

Logic 0 = No break condition (normal default condition).

Logic 1 = The receiver received a break signal (RX was a logic 0 for

one character frame time). In the FIFO mode, only one break character

is loaded into the FIFO.

Framing error.

Logic 0 = No framing error (normal default condition).

Logic 1 = Framing error. The receive character did not have a valid stop

bit(s). In the FIFO mode, this error is associated with the character at

the top of the FIFO.

Parity error.

Logic 0 = No parity error (normal default condition).

Logic 1 = Parity error. The receive character does not have correct

parity information and is suspect. In the FIFO mode, this error is

associated with the character at the top of the FIFO.

Overrun error.

Logic 0 = No overrun error (normal default condition).

Logic 1 = Overrun error. A data overrun error occurred in the receive

shift register. This happens when additional data arrives while the FIFO

is full. In this case, the previous data in the shift register is overwritten.

Note that under this condition, the data byte in the receive shift register

is not transferred into the FIFO, therefore the data in the FIFO is not

corrupted by the error.

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SC16C650B

UART with 32-byte FIFOs and IrDA encoder/decoder

Philips Semiconductors

Table 20: Line Status Register bits description…continued

Bit

Symbol

Description

0

LSR[0]

Receive data ready.

Logic 0 = No data in receive holding register or FIFO (normal default

condition).

Logic 1 = Data has been received and is saved in the receive holding

register or FIFO.

7.8 Modem Status Register (MSR)

This register provides the current state of the control interface signals from the

modem, or other peripheral device to which the SC16C650B is connected. Four bits

of this register are used to indicate the changed information. These bits are set to a

logic 1 whenever a control input from the modem changes state. These bits are set to

a logic 0 whenever the CPU reads this register.

Table 21: Modem Status Register bits description

Bit

Symbol

Description

7

MSR[7]

Data Carrier Detect. DCD (Active-HIGH, logical 1). Normally this bit is

the complement of the DCD input. In the loop-back mode this bit is

equivalent to the OUT2 bit in the MCR register.

6

5

4

MSR[6]

MSR[5]

MSR[4]

Ring Indicator. RI (Active-HIGH, logical 1). Normally this bit is the

complement of the RI input. In the loop-back mode this bit is equivalent

to the OUT1 bit in the MCR register.

Data Set Ready. DSR (Active-HIGH, logical 1). Normally this bit is the

complement of the DSR input. In loop-back mode this bit is equivalent to

the DTR bit in the MCR register.

Clear To Send. CTS. CTS functions as hardware ﬂow control signal input

if it is enabled via EFR[7]. Flow control (when enabled) allows starting

and stopping the transmissions based on the external modem CTS

signal. A logic 1 at the CTS pin will stop SC16C650B transmissions as

soon as current character has ﬁnished transmission. Normally MSR[4] is

the complement of the CTS input. However, in the loop-back mode, this

bit is equivalent to the RTS bit in the MCR register.

3

2

MSR[3]

MSR[2]

∆DCD ^[1]

Logic 0 = No DCD change (normal default condition).

Logic 1 = The DCD input to the SC16C650B has changed state since

the last time it was read. A modem Status Interrupt will be generated.

∆RI ^[1]

Logic 0 = No RI change (normal default condition).

Logic 1 = The RI input to the SC16C650B has changed from a logic 0

to a logic 1. A modem Status Interrupt will be generated.

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SC16C650B

UART with 32-byte FIFOs and IrDA encoder/decoder

Philips Semiconductors

Table 21: Modem Status Register bits description…continued

Bit

Symbol

Description

∆DSR ^[1]

Logic 0 = No DSR change (normal default condition).

1

MSR[1]

Logic 1 = The DSR input to the SC16C650B has changed state since

the last time it was read. A modem Status Interrupt will be generated.

0

MSR[0]

∆CTS ^[1]

Logic 0 = No CTS change (normal default condition).

Logic 1 = The CTS input to the SC16C650B has changed state since

the last time it was read. A modem Status Interrupt will be generated.

[1] Whenever any MSR bit 0:3 is set to logic 1, a Modem Status Interrupt will be generated.

7.9 Scratchpad Register (SPR)

The SC16C650B provides a temporary data register to store 8 bits of user

information.

7.10 Enhanced Feature Register (EFR)

Enhanced features are enabled or disabled using this register.

Bits 0 through 4 provide single or dual character software ﬂow control selection.

When the Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double

8-bit words are concatenated into two sequential numbers.

Table 22: Enhanced Feature Register bits description

Bit

Symbol Description

7

EFR[7]

Automatic CTS ﬂow control.

Logic 0 = Automatic CTS ﬂow control is disabled (normal default

condition).

Logic 1 = Enable Automatic CTS ﬂow control. Transmission will stop

when CTS goes to a logical 1. Transmission will resume when the CTS

pin returns to a logical 0.

6

EFR[6]

Automatic RTS ﬂow control. Automatic RTS may be used for hardware ﬂow

control by enabling EFR[6]. When Auto-RTS is selected, an interrupt will

be generated when the receive FIFO is ﬁlled to the programmed trigger

level and RTS will go to a logic 1 at the next trigger level. RTS will return to

a logic 0 when data is unloaded below the next lower trigger level

(programmed trigger level 1). The state of this register bit changes with the

status of the hardware ﬂow control. RTS functions normally when

hardware ﬂow control is disabled.

0 = Automatic RTS ﬂow control is disabled (normal default condition).

1 = Enable Automatic RTS ﬂow control.

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SC16C650B

UART with 32-byte FIFOs and IrDA encoder/decoder

Philips Semiconductors

Table 22: Enhanced Feature Register bits description…continued

Bit

Symbol Description

EFR[5] Special Character Detect.

5

Logic 0 = Special character detect disabled (normal default condition).

Logic 1 = Special character detect enabled. The SC16C650B compares

each incoming receive character with Xoff2 data. If a match exists, the

received data will be transferred to FIFO and ISR[4] will be set to

indicate detection of special character. Bit-0 in the X-registers

corresponds with the LSB bit for the receive character. When this feature

is enabled, the normal software ﬂow control must be disabled (EFR[3:0]

must be set to a logic 0).

4

EFR[4]

Enhanced function control bit. The content of IER[7:4], ISR[5:4], FCR[5:4],

and MCR[7:5] can be modiﬁed and latched. After modifying any bits in the

enhanced registers, EFR[4] can be set to a logic 0 to latch the new values.

This feature prevents existing software from altering or overwriting the

SC16C650B enhanced functions.

Logic 0 = Disable (normal default condition).

Logic 1 = Enable.

3:0

EFR[3:0] Cont-3:0 Tx, Rx control. Logic 0 or cleared is the default condition.

Combinations of software ﬂow control can be selected by programming

these bits. See Table 23.

Table 23: Software ﬂow control functions^[1]

Cont-3 Cont-2 Cont-1 Cont-0 TX, RX software ﬂow controls

0

1

0

1

X

1

0

1

X

0

X

0

1

0

1

X

0

1

No transmit ﬂow control

Transmit Xon1/Xoff1

Transmit Xon2/Xoff2

Transmit Xon1 and Xon2/Xoff1 and Xoff2

No receive ﬂow control

Receiver compares Xon1/Xoff1

Receiver compares Xon2/Xoff2

Transmit Xon1/Xoff1

Receiver compares Xon1 and Xon2, Xoff1 and Xoff2

Transmit Xon2/Xoff2

0

1

Receiver compares Xon1 and Xon2/Xoff1 and Xoff2

Transmit Xon1 and Xon2/Xoff1 and Xoff2

Receiver compares Xon1 and Xon2/Xoff1 and Xoff2

[1] When using a software ﬂow control the Xon/Xoff characters cannot be used for data transfer.

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SC16C650B

UART with 32-byte FIFOs and IrDA encoder/decoder

Philips Semiconductors

7.11 SC16C650B external reset conditions

Table 24: Reset state for registers

Register

IER

Reset state

IER[7:0] = 0

ISR

ISR[7:1] = 0; ISR[0] = 1

LCR[7:0] = 0

LCR

MCR

LSR

MCR[7:0] = 0

LSR[7] = 0; LSR[6:5] = 1; LSR[4:0] = 0

MSR[7:4] = input signals; MSR[3:0] = 0

FCR[7:0] = 0

MSR

FCR

EFR

EFR[7:0] = 0

Table 25: Reset state for outputs

Output

TX

Reset state

HIGH

RTS

HIGH

DTR

HIGH

RXRDY

TXRDY

INT

HIGH (STD mode)

LOW (STD mode)

8. Limiting values

Table 26: Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_CC

Parameter

Conditions

Min

Max

Unit

V

supply voltage

-

7

V_n

voltage at any pin

operating temperature

storage temperature

GND − 0.3 V_CC+ 0.3

V

T_amb

−40

−65

-

+85

°C

mW

T_stg

+150

500

P_tot(pack)

total power dissipation per

package

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UART with 32-byte FIFOs and IrDA encoder/decoder

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9. Static characteristics

Table 27: DC electrical characteristics

T_amb= −40 °C to +85 °C; V_CC= 2.5 V, 3.3 V or 5.0 V ±10%, unless otherwise speciﬁed.

Symbol Parameter

Conditions

2.5 V

Max

3.3 V

Max

5.0 V

Max

Unit

Min

−0.3

1.8

−0.3

1.6

-

Min

−0.3

2.4

−0.3

2.0

-

Min

−0.5

3.0

−0.5

2.2

-

V_IL(CK)

V_IH(CK)

V_IL

LOW-level clock input voltage

0.45

V_CC

0.65

-

0.6

V_CC

0.8

-

0.6

V

HIGH-level clock input voltage

LOW-level input voltage

HIGH-level input voltage

V_CC

0.8

V_IH

V_CC

0.4

V_OL

LOW-level output voltage

on all outputs^[1]

I_OL= 5 mA

(databus)

-

I

_OL= 4 mA

(other outputs)

_OL= 2 mA

(databus)

_OL= 1.6 mA

-

0.4

-

V

I

-

0.4

-

I

-

0.4

-

(other outputs)

V_OH

HIGH-level output voltage

I_OH= −5 mA

(databus)

-

2.4

I

_OH= −1 mA

(other outputs)

_OH= −800 µA

(databus)

_OH= −400 µA

-

2.0

-

I

1.85

-

I

(other outputs)

I_LIL

LOW-level input leakage current

clock leakage

-

±10

±30

3.5

5

-

±10

±30

4.5

5

-

±10

±30

4.5

5

µA

mA

pF

I_CL

-

I_CC

average power supply current

f = 5 MHz

-

C_i

input capacitance

-

R_pu(int)

internal pull-up resistance^[2]

500

-

500

-

500

-

kΩ

[1] Except for x₂, V_OL= 1 V typically.

[2] Refer to Table 2 “Pin description” on page 6 for a listing of pins having internal pull-up resistors.

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SC16C650B

UART with 32-byte FIFOs and IrDA encoder/decoder

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10. Dynamic characteristics

Table 28: AC electrical characteristics

T_amb= −40 °C to +85 °C; V_CC= 2.5 V, 3.3 V or 5 V ±10%, unless otherwise speciﬁed.

Symbol

Parameter

Conditions

2.5 V

3.3 V

5.0 V

Unit

Min Max

t_1w, t_2w

t_3w

clock pulse duration

oscillator/clock frequency

address strobe width

address set-up time

address hold time

15

-

13

-

10

-

ns

MHz

ns

[1]

16

32

-

48

-

t_4w

45

5

-

35

5

25

1

t_5s

-

t_5h

5

-

5

-

5

-

t_6s

chip select set-up time to AS

address hold time

10

0

-

5

-

0

-

t_6h

-

0

-

0

-

[2]

t_6s'

address set-up time

chip select hold time

IOR delay from chip select

IOR strobe width

10

0

-

10

0

-

5

-

t_6h

-

0

-

t_7d

10

77

0

-

10

26

0

-

10

23

0

-

t_7w

25 pF load

-

t_7h

chip select hold time from IOR

address hold time

-

[2]

t_7h'

5

-

5

-

5

-

t_8d

IOR delay from address

read cycle delay

10

20

-

10

20

-

10

20

-

t_9d

25 pF load

-

t_11d

t_12d

t_12h

t_13d

t_13w

t_13h

t_14d

t_15d

t_16s

t_16h

t_17d

t_18d

IOR to DDIS delay

100

35

26

15

-

30

23

15

-

delay from IOR to data

data disable time

-

77

-

15

-

IOW delay from chip select

IOW strobe width

10

20

0

-

10

20

0

10

15

0

-

chip select hold time from IOW

IOW delay from address

write cycle delay

-

10

25

20

15

-

10

25

20

5

-

10

20

15

5

-

data set-up time

-

data hold time

-

delay from IOW to output

25 pF load

100

-

33

24

-

29

23

delay to set interrupt from Modem

input

-

t_19d

t_20d

t_21d

t_22d

t_23d

t_24d

t_25d

t_26d

t_27d

delay to reset interrupt from IOR

delay from stop to set interrupt

delay from IOR to reset interrupt

delay from start to set interrupt

delay from IOW to transmit start

delay from IOW to reset interrupt

delay from stop to set RXRDY

delay from IOR to reset RXRDY

delay from IOW to set TXRDY

25 pF load

-

8

-

100

1

-

8

-

24

1

-

8

-

23

1

ns

R_clk

ns

100

24

29

45

24

45

1

28

40

24

40

1

ns

R_clk

ns

100

1

R_clk

ns

100

45

40

ns

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SC16C650B

UART with 32-byte FIFOs and IrDA encoder/decoder

Philips Semiconductors

Table 28: AC electrical characteristics…continued

T_amb= −40 °C to +85 °C; V_CC= 2.5 V, 3.3 V or 5 V ±10%, unless otherwise speciﬁed.

Symbol

Parameter

Conditions

2.5 V

3.3 V

5.0 V

Unit

Min Max

t_28d

t_RESET

N

delay from start to reset TXRDY

Reset pulse width

-

8

-

8

-

8

R_clk

ns

100

1

-

40

1

-

40

1

-

baud rate divisor

2¹⁶− 1

2¹⁶− 1 R_clk

[1] Applies to external clock, crystal oscillator max 24 MHz.

[2] Applicable only when AS is tied LOW.

10.1 Timing diagrams

t

4w

AS

t

5s

t

5h

VALID

ADDRESS

A0–A2

t

6s

t

6h

CS2

CS1–CS0

VALID

t

7d

t

7h

t

7w

t

8d

t

9d

IOR, IOR

ACTIVE

t

11d

t

11d

DDIS

ACTIVE

t

12h

12d

D0–D7

DATA

002aaa331

Fig 9. General read timing when using AS signal.

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SC16C650B

UART with 32-byte FIFOs and IrDA encoder/decoder

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t

4w

AS

t

5s

t

5h

VALID

ADDRESS

A0–A2

t

6s

t

6h

CS2

CS1–CS0

VALID

t

13h

13d

t

13w

t

15d

14d

IOW, IOW

ACTIVE

t

16h

16s

D0–D7

DATA

002aaa332

Fig 10. General write timing when using AS signal.

VALID

ADDRESS

VALID

ADDRESS

A0–A2

t

′

7h

t

′

6s

t

′

7h

t

′

6s

t

7w

ACTIVE

CS

t

7w

t

9d

IOR

ACTIVE

t

12h

t

12h

12d

D0–D7

DATA

002aaa333

Fig 11. General read timing when AS is tied to GND.

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SC16C650B

UART with 32-byte FIFOs and IrDA encoder/decoder

Philips Semiconductors

VALID

ADDRESS

VALID

ADDRESS

A0–A2

t

′

7h

t

′

6s

t

′

7h

t

′

6s

ACTIVE

CS

t

13w

15d

IOW

ACTIVE

t

16h

t

16h

16s

D0–D7

DATA

002aaa334

Fig 12. General write timing when AS is tied to GND.

IOW

ACTIVE

t

17d

RTS

DTR

CHANGE OF STATE

DCD

CTS

DSR

CHANGE OF STATE

t

18d

INT

ACTIVE

t

19d

IOR

ACTIVE

t

18d

RI

CHANGE OF STATE

002aaa351

Fig 13. Modem input/output timing.

9397 750 14451

Product data

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t

1w

2w

EXTERNAL

CLOCK

002aaa112

t

3w

Fig 14. External clock timing.

start

bit

parity stop start

bit

data bits (0 to 7)

D3 D4

RX

D0

D1

D2

D5

D6

D7

5 data bits

6 data bits

7 data bits

t

20d

active

INT

t

21d

active

IOR

16 baud rate clock

002aaa113

Fig 15. Receive timing.

9397 750 14451

Product data

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UART with 32-byte FIFOs and IrDA encoder/decoder

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START

BIT

PARITY STOP START

BIT

DATA BITS (5–8)

RX

D0

D1

D2

D3

D4

D5

D6

D7

t

25d

ACTIVE

DATA

READY

RXRDY

t

26d

ACTIVE

IOR

002aaa578

Fig 16. Receive ready timing in non-FIFO mode.

START

BIT

PARITY STOP

BIT BIT

DATA BITS (5–8)

RX

D0

D1

D2

D3

D4

D5

D6

D7

FIRST BYTE THAT

REACHES THE

TRIGGER LEVEL

t

25d

ACTIVE

DATA

READY

RXRDY

t

26d

ACTIVE

IOR

002aaa579

Fig 17. Receive ready timing in FIFO mode.

9397 750 14451

Product data

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UART with 32-byte FIFOs and IrDA encoder/decoder

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start

bit

parity stop start

bit

data bits (0 to 7)

TX

D0

D1

D2

D3

D4

D5

D6

D7

5 data bits

6 data bits

7 data bits

active

INT

transmitter ready

t

22d

t

24d

t

23d

active

IOW

active

16 baud rate clock

002aaa116

Fig 18. Transmit timing.

START

BIT

PARITY STOP START

BIT BIT

BIT

DATA BITS (5-8)

TX

D0

D1

D2

D3

D4

D5

D6

D7

ACTIVE

IOW

D0-D7

BYTE #1

t

28d

t

27d

ACTIVE

TRANSMITTER READY

TXRDY

TRANSMITTER

NOT READY

002aaa580

Fig 19. Transmit ready timing in non-FIFO mode.

9397 750 14451

Product data

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UART with 32-byte FIFOs and IrDA encoder/decoder

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START

BIT

PARITY STOP

BIT

DATA BITS (5-8)

TX

D0

D1

D2

D3

D4

D5

D6

D7

5 DATA BITS

6 DATA BITS

7 DATA BITS

ACTIVE

IOW

D0–D7

TXRDY

t

28d

BYTE #16

t

27d

FIFO FULL

002aaa581

Fig 20. Transmit ready timing in FIFO mode (DMA mode ‘1’).

9397 750 14451

Product data

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UART frame

data bits

start

stop

1

0

1

0

1

0

1

0

TX data

IrDA TX data

1

/

bit time

2

bit

time

3

/

bit time

16

002aaa212

Fig 21. Infrared transmit timing.

IrDA RX data

bit

time

0 to 1 16× clock delay

0

1

0

1

0

1

0

1

RX data

start

data bits

stop

UART frame

002aaa213

Fig 22. Infrared receive timing.

9397 750 14451

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11. Package outline

PLCC44: plastic leaded chip carrier; 44 leads

SOT187-2

e

D

E

y

X

A

39

29

b

p

Z

E

28

40

b

1

w

M

44

1

H

E

pin 1 index

A

1

A

4

e

(A )

3

6

18

β

L

p

k

detail X

7

17

v

M

A

e

Z

D

B

H

v

M

B

D

0

5

10 mm

scale

DIMENSIONS (mm dimensions are derived from the original inch dimensions)

(1)

A

Z

E

4

1

(1)

D

UNIT

mm

A

b

D

E

e

H

k

L

p

v

w

y

β

b

3

1

D

E

D

E

p

max.

min.

max. max.

4.57

4.19

0.81 16.66 16.66

0.66 16.51 16.51

16.00 16.00 17.65 17.65 1.22 1.44

14.99 14.99 17.40 17.40 1.07 1.02

0.53

0.33

0.51 0.25 3.05

0.02 0.01 0.12

1.27

0.05

0.18 0.18

0.1

2.16 2.16

o

45

0.180

0.165

0.032 0.656 0.656

0.026 0.650 0.650

0.63 0.63 0.695 0.695 0.048 0.057

0.59 0.59 0.685 0.685 0.042 0.040

0.021

0.013

inches

0.007 0.007 0.004 0.085 0.085

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

01-11-14

SOT187-2

112E10

MS-018

EDR-7319

Fig 23. PLCC44 (SOT187-2).

9397 750 14451

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LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm

SOT313-2

c

y

X

36

25

A

E

37

24

Z

E

e

H

E

A

2

A

(A )

3

A

1

w M

p

θ

pin 1 index

b

L

p

L

13

48

detail X

1

12

Z

v M

D

A

e

w M

b

p

D

B

H

v

M

B

D

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

v

w

y

Z

E

θ

1

2

3

p

E

p

D

max.

7^o

0^o

0.20 1.45

0.05 1.35

0.27 0.18 7.1

0.17 0.12 6.9

7.1

6.9

9.15 9.15

8.85 8.85

0.75

0.45

0.95 0.95

0.55 0.55

1.6

mm

0.25

0.5

1

0.2 0.12 0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-01-19

03-02-25

SOT313-2

136E05

MS-026

Fig 24. LQFP48 (SOT313-2).

9397 750 14451

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HVQFN32: plastic thermal enhanced very thin quad flat package; no leads;

32 terminals; body 5 x 5 x 0.85 mm

SOT617-1

B

A

D

terminal 1

index area

A

1

E

c

detail X

C

e

1

y

e

1/2 e

v

M

b

C

A B

C

1

w

9

16

L

17

8

e

E

h

2

1/2 e

1

24

terminal 1

index area

32

25

X

D

h

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

A

(1)

UNIT

A

b

c

E

e

2

y

D

E

L

v

w

y

1

h

1

h

max.

0.05 0.30

0.00 0.18

5.1

4.9

3.25

2.95

5.1

4.9

3.25

2.95

0.5

0.3

mm

0.05 0.1

1

0.2

0.5

3.5

0.1

0.05

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

01-08-08

02-10-18

SOT617-1

- - -

MO-220

- - -

Fig 25. HVQFN32 (SOT617-1).

9397 750 14451

Product data

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DIP40: plastic dual in-line package; 40 leads (600 mil)

SOT129-1

D

M

E

A

2

A

L

A

1

c

e

w M

Z

b

1

(e )

1

b

M

H

40

21

pin 1 index

E

1

20

0

5

10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

(1)

A

(1)

Z

1

2

w

UNIT

mm

b

c

D

E

e

L

M

1

E

H

max.

min.

max.

1.70

1.14

0.53

0.38

0.36

0.23

52.5

51.5

14.1

13.7

3.60

3.05

15.80

15.24

17.42

15.90

4.7

0.51

4

2.54

0.1

15.24

0.6

0.254

0.01

2.25

0.067

0.045

0.021

0.015

0.014

0.009

2.067

2.028

0.56

0.54

0.14

0.12

0.62

0.60

0.69

0.63

inches

0.19

0.02

0.16

0.089

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-13

SOT129-1

051G08

MO-015

SC-511-40

Fig 26. DIP40 (SOT129-1).

9397 750 14451

Product data

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12. Soldering

12.1 Introduction

This text gives a very brief insight to a complex technology. A more in-depth account

of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit

Packages (document order number 9398 652 90011).

There is no soldering method that is ideal for all IC packages. Wave soldering is often

preferred when through-hole and surface mount components are mixed on one

printed-circuit board. Wave soldering can still be used for certain surface mount ICs,

but it is not suitable for ﬁne pitch SMDs. In these situations reﬂow soldering is

recommended. Driven by legislation and environmental forces the worldwide use of

lead-free solder pastes is increasing.

12.2 Through-hole mount packages

12.2.1 Soldering by dipping or by solder wave

Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 °C or

265 °C, depending on solder material applied, SnPb or Pb-free respectively.

The total contact time of successive solder waves must not exceed 5 seconds.

The device may be mounted up to the seating plane, but the temperature of the

plastic body must not exceed the speciﬁed maximum storage temperature (T_stg(max)).

If the printed-circuit board has been pre-heated, forced cooling may be necessary

immediately after soldering to keep the temperature within the permissible limit.

12.2.2 Manual soldering

Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the

seating plane or not more than 2 mm above it. If the temperature of the soldering iron

bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit

temperature is between 300 and 400 °C, contact may be up to 5 seconds.

12.3 Surface mount packages

12.3.1 Reﬂow soldering

Reﬂow soldering requires solder paste (a suspension of ﬁne solder particles, ﬂux and

binding agent) to be applied to the printed-circuit board by screen printing, stencilling

or pressure-syringe dispensing before package placement.

Several methods exist for reﬂowing; for example, convection or convection/infrared

heating in a conveyor type oven. Throughput times (preheating, soldering and

cooling) vary between 100 and 200 seconds depending on heating method.

Typical reﬂow peak temperatures range from 215 to 270 °C depending on solder

paste material. The top-surface temperature of the packages should preferably be

kept:

• below 225 °C (SnPb process) or below 245 °C (Pb-free process)

– for all the BGA and SSOP-T packages

9397 750 14451

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– for packages with a thickness ≥ 2.5 mm

– for packages with a thickness < 2.5 mm and a volume ≥ 350 mm³so called

thick/large packages.

• below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with

a thickness < 2.5 mm and a volume < 350 mm³so called small/thin packages.

Moisture sensitivity precautions, as indicated on packing, must be respected at all

times.

12.3.2 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices

(SMDs) or printed-circuit boards with a high component density, as solder bridging

and non-wetting can present major problems.

To overcome these problems the double-wave soldering method was speciﬁcally

developed.

If wave soldering is used the following conditions must be observed for optimal

results:

• Use a double-wave soldering method comprising a turbulent wave with high

upward pressure followed by a smooth laminar wave.

• For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be

parallel to the transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the

transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

• For packages with leads on four sides, the footprint must be placed at a 45° angle

to the transport direction of the printed-circuit board. The footprint must

incorporate solder thieves downstream and at the side corners.

During placement and before soldering, the package must be ﬁxed with a droplet of

adhesive. The adhesive can be applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 °C or

265 °C, depending on solder material applied, SnPb or Pb-free respectively.

A mildly-activated ﬂux will eliminate the need for removal of corrosive residues in

most applications.

12.3.3 Manual soldering

Fix the component by ﬁrst soldering two diagonally-opposite end leads. Use a low

voltage (24 V or less) soldering iron applied to the ﬂat part of the lead. Contact time

must be limited to 10 seconds at up to 300 °C.

When using a dedicated tool, all other leads can be soldered in one operation within

2 to 5 seconds between 270 and 320 °C.

9397 750 14451

Product data

Rev. 03 — 10 December 2004

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Philips Semiconductors

12.4 Package related soldering information

Table 29: Suitability of IC packages for wave, reﬂow and dipping soldering methods

Mounting

Package^[1]

Soldering method

Wave

Reﬂow^[2]Dipping

Through-hole

mount

DBS, DIP, HDIP, RDBS,

SDIP, SIL

suitable^[3]

−

suitable

Through-hole-

surface mount

PMFP^[4]

not suitable

not

suitable

−

Surface mount

BGA, LBGA, LFBGA,

SQFP, SSOP-T^[5],

TFBGA, VFBGA

suitable

DHVQFN, HBCC, HBGA, not suitable^[6]

HLQFP, HSQFP, HSOP,

suitable

−

HTQFP, HTSSOP,

HVQFN, HVSON, SMS

PLCC^[7], SO, SOJ

suitable

−

LQFP, QFP, TQFP

not recommended^[7][8]suitable

not recommended^[9]

suitable

SSOP, TSSOP, VSO,

VSSOP

[1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note

(AN01026); order a copy from your Philips Semiconductors sales ofﬁce.

[2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the

maximum temperature (with respect to time) and body size of the package, there is a risk that internal

or external package cracks may occur due to vaporization of the moisture in them (the so called

popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated

Circuit Packages; Section: Packing Methods.

[3] For SDIP packages, the longitudinal axis must be parallel to the transport direction of the

printed-circuit board.

[4] Hot bar soldering or manual soldering is suitable for PMFP packages.

[5] These transparent plastic packages are extremely sensitive to reﬂow soldering conditions and must

on no account be processed through more than one soldering cycle or subjected to infrared reﬂow

soldering with peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reﬂow

oven. The package body peak temperature must be kept as low as possible.

[6] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom

side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with

the heatsink on the top side, the solder might be deposited on the heatsink surface.

[7] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave

direction. The package footprint must incorporate solder thieves downstream and at the side corners.

[8] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it

is deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

[9] Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than

0.65 mm; it is deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

9397 750 14451

Product data

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Philips Semiconductors

13. Revision history

Table 30: Revision history

Rev Date

CPCN

-

Description

03 20041210

Product data (9397 750 14451)

Modiﬁcations:

• There is no modiﬁcation to the data sheet. However, reader is advised to refer to

AN10333 (Rev. 02) “SC16CXXXB baud rate deviation tolerance” (9397 750 14411)

that was released together with this revision.

02 20040603

01 20040330

-

Product data (9397 750 13317)

Product data (9397 750 11994)

9397 750 14451

Product data

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49 of 51

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14. Data sheet status

Level Data sheet status^[1]

Product status^[2][3]

Deﬁnition

I

Objective data

Development

This data sheet contains data from the objective speciﬁcation for product development. Philips

Semiconductors reserves the right to change the speciﬁcation in any manner without notice.

II

Preliminary data

Qualiﬁcation

This data sheet contains data from the preliminary speciﬁcation. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in

order to improve the design and supply the best possible product.

III

Product data

Production

This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

[1]

[2]

Please consult the most recently issued data sheet before initiating or completing a design.

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3]

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

15. Deﬁnitions

16. Disclaimers

Short-form speciﬁcation — The data in a short-form speciﬁcation is

extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors

customers using or selling these products for use in such applications do so

at their own risk and agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

Limiting values deﬁnition — Limiting values given are in accordance with

the Absolute Maximum Rating System (IEC 60134). Stress above one or

more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any

other conditions above those given in the Characteristics sections of the

speciﬁcation is not implied. Exposure to limiting values for extended periods

may affect device reliability.

Right to make changes — Philips Semiconductors reserves the right to

make changes in the products - including circuits, standard cells, and/or

software - described or contained herein in order to improve design and/or

performance. When the product is in full production (status ‘Production’),

relevant changes will be communicated via a Customer Product/Process

Change Notiﬁcation (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no

licence or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are

free from patent, copyright, or mask work right infringement, unless otherwise

speciﬁed.

Application information — Applications that are described herein for any

of these products are for illustrative purposes only. Philips Semiconductors

make no representation or warranty that such applications will be suitable for

the speciﬁed use without further testing or modiﬁcation.

Contact information

For additional information, please visit http://www.semiconductors.philips.com.

For sales ofﬁce addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.

Fax: +31 40 27 24825

50 of 51

9397 750 14451

Product data

Rev. 03 — 10 December 2004

SC16C650B

UART with 32-byte FIFOs and IrDA encoder/decoder

Philips Semiconductors

Contents

1

2

3

4

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

8

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 31

Static characteristics . . . . . . . . . . . . . . . . . . . 32

Dynamic characteristics. . . . . . . . . . . . . . . . . 33

Timing diagrams. . . . . . . . . . . . . . . . . . . . . . . 34

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 42

9

10

10.1

11

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

12

12.1

12.2

12.2.1

12.2.2

12.3

12.3.1

12.3.2

12.3.3

12.4

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Through-hole mount packages . . . . . . . . . . . 46

Soldering by dipping or by solder wave . . . . . 46

Manual soldering . . . . . . . . . . . . . . . . . . . . . . 46

Surface mount packages . . . . . . . . . . . . . . . . 46

Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 46

Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 47

Manual soldering . . . . . . . . . . . . . . . . . . . . . . 47

Package related soldering information. . . . . . 48

6

Functional description . . . . . . . . . . . . . . . . . . 10

Internal registers. . . . . . . . . . . . . . . . . . . . . . . 11

FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . 11

Hardware ﬂow control. . . . . . . . . . . . . . . . . . . 12

Software ﬂow control . . . . . . . . . . . . . . . . . . . 12

Special feature software ﬂow control . . . . . . . 13

Hardware/software and time-out interrupts. . . 13

Programmable baud rate generator . . . . . . . . 14

DMA operation . . . . . . . . . . . . . . . . . . . . . . . . 16

Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Loop-back mode. . . . . . . . . . . . . . . . . . . . . . . 16

6.1

6.2

6.3

6.4

6.5

6.6

6.7

6.8

6.9

6.10

13

14

15

16

Revision history . . . . . . . . . . . . . . . . . . . . . . . 49

Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 50

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

7

7.1

Register descriptions . . . . . . . . . . . . . . . . . . . 18

Transmit (THR) and Receive (RHR)

Holding Registers . . . . . . . . . . . . . . . . . . . . . 19

Interrupt Enable Register (IER) . . . . . . . . . . . 19

IER versus Receive FIFO interrupt

7.2

7.2.1

mode operation . . . . . . . . . . . . . . . . . . . . . . . 20

IER versus Receive/Transmit FIFO polled

7.2.2

mode operation . . . . . . . . . . . . . . . . . . . . . . . 20

FIFO Control Register (FCR) . . . . . . . . . . . . . 21

DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Interrupt Status Register (ISR) . . . . . . . . . . . . 23

Line Control Register (LCR) . . . . . . . . . . . . . . 24

Modem Control Register (MCR) . . . . . . . . . . . 25

Line Status Register (LSR). . . . . . . . . . . . . . . 27

Modem Status Register (MSR). . . . . . . . . . . . 28

Scratchpad Register (SPR) . . . . . . . . . . . . . . 29

Enhanced Feature Register (EFR) . . . . . . . . . 29

SC16C650B external reset conditions . . . . . . 31

7.3

7.3.1

7.3.2

7.4

7.5

7.6

7.7

7.8

7.9

7.10

7.11

Printed in the U.S.A.

All rights are reserved. Reproduction in whole or in part is prohibited without the prior

written consent of the copyright owner.

The information presented in this document does not form part of any quotation or

contract, is believed to be accurate and reliable and may be changed without notice. No

liability will be accepted by the publisher for any consequence of its use. Publication

thereof does not convey nor imply any license under patent- or other industrial or

intellectual property rights.

Date of release: 10 December 2004

Document order number: 9397 750 14451


型号：	SC16C650BIB48
厂家：	NXP
描述：	5 V, 3.3 V and 2.5 V UART with 32-byte FIFOs and infrared (IrDA) encoder/decoder 5 V ， 3.3 V和2.5 V UART，具有32字节FIFO和红外线（ IrDA）编码器/解码器解码器微控制器和处理器串行IO控制器通信控制器外围集成电路先进先出芯片编码器数据传输时钟
文件：	总51页 (文件大小：720K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SC16C650BIB48 [NXP]

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