SC16C654IB64,157_技术文档

SC16C654/654D

Quad UART with 64-byte FIFO and infrared (IrDA)

encoder/decoder

Rev. 04 — 19 June 2003

Product data

1. Description

The SC16C654/654D is a 4-channel Universal Asynchronous Receiver and

Transmitter (QUART) used for serial data communications. Its principal function is to

convert parallel data into serial data and vice versa. The UART can handle serial data

rates up to 5 Mbits/s. It comes with an Intel or Motorola interface.

The SC16C654/654D is pin compatible with the ST16C654 and TL16C754 and it will

power-up to be functionally equivalent to the 16C454. Programming of control

registers enables the added features of the SC16C654/654D. Some of these added

features are the 64-byte receive and transmit FIFOs, automatic hardware or software

ﬂow control and Infrared encoding/decoding. The selectable auto-ﬂow control feature

signiﬁcantly reduces software overload and increases system efﬁciency while in FIFO

mode by automatically controlling serial data ﬂow using RTS output and CTS input

signals. The SC16C654/654D also provides DMA mode data transfers through FIFO

trigger levels and the TXRDY and RXRDY signals. On-board status registers provide

the user with error indications, operational status, and modem interface control.

System interrupts may be tailored to meet user requirements. An internal loop-back

capability allows on-board diagnostics.

The SC16C654/654D operates at 5 V, 3.3 V and 2.5 V, and the industrial temperature

range, and is available in plastic PLCC68 and LQFP64 packages.

2. Features

■ 5 V, 3.3 V and 2.5 V operation

■ Industrial temperature range

■ Pin compatibility with the industry-standard ST16C454/554, ST68C454/554,

TL16C554

■ Up to 5 Mbits/s data rate at 5 V and 3.3 V and 3 Mbits/s at 2.5 V

■ 64-byte transmit FIFO

■ 64-byte receive FIFO with error ﬂags

■ Automatic software/hardware ﬂow control

■ Programmable Xon/Xoff characters

■ Software selectable Baud Rate Generator

■ Four selectable Receive and Transmit FIFO interrupt trigger levels

■ Standard modem interface or infrared IrDA encoder/decoder interface

■ Sleep mode

■ Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun

Break)

■ Transmit, Receive, Line Status, and Data Set interrupts independently controlled

SC16C654/654D

Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder

Philips Semiconductors

■ Fully programmable character formatting:

◆ 5-, 6-, 7-, or 8-bit characters

◆ Even-, Odd-, or No-Parity formats

◆ 1-, 1¹⁄₂-, or 2-stop bit

◆ Baud generation (DC to 1.5 Mbit/s)

■ False start-bit detection

■ Complete status reporting capabilities

■ 3-State output TTL drive capabilities for bi-directional data bus and control bus

■ Line Break generation and detection

■ Internal diagnostic capabilities:

◆ Loop-back controls for communications link fault isolation

■ Prioritized interrupt system controls

■ Modem control functions (CTS, RTS, DSR, DTR, RI, DCD).

3. Ordering information

Table 1:

Ordering information

Type number

Package

Name

Description

Version

SC16C654IA68

SC16C654IB64

SC16C654DIB64

PLCC68

LQFP64

plastic leaded chip carrier; 68 leads

SOT188-2

SOT314-2

plastic low proﬁle quad ﬂat package; 64 leads; body 10 × 10 × 1.4 mm

9397 750 11617

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SC16C654/654D

Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder

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4. Block diagram

SC16C654/654D

TRANSMIT

FIFO

TRANSMIT

SHIFT

TXA-TXD

REGISTERS

REGISTER

D0–D7

IOR

IOW

DATA BUS

AND

CONTROL LOGIC

RESET

FLOW

CONTROL

LOGIC

IR

ENCODER

RECEIVE

FIFO

RECEIVE

SHIFT

RXA-RXD

REGISTERS

REGISTER

FLOW

CONTROL

LOGIC

IR

DECODER

REGISTER

SELECT

LOGIC

A0–A2

CSA-CSD

16/68

DTRA-DTRD

RTSA-RTSD

MODEM

CONTROL

LOGIC

INTA-INTD

TXRDY

RXRDY

CTSA-CTSD

RIA-RID

CDA-CDD

CLOCK AND

BAUD RATE

GENERATOR

INTERRUPT

CONTROL

LOGIC

DSRA-DSRD

INTSEL

002aaa206

XTAL1 XTAL2

CLKSEL

Fig 1. SC16C654/654D block diagram (16 mode).

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SC16C654/654D

Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder

Philips Semiconductors

SC16C654/654D

TRANSMIT

FIFO

TRANSMIT

SHIFT

TXA-TXD

REGISTERS

REGISTER

D0–D7

R/W

RESET

DATA BUS

AND

CONTROL LOGIC

FLOW

CONTROL

LOGIC

IR

ENCODER

RECEIVE

FIFO

RECEIVE

SHIFT

RXA-RXD

REGISTERS

REGISTER

FLOW

CONTROL

LOGIC

IR

DECODER

REGISTER

SELECT

LOGIC

A0–A4

CS

16/68

DTRA-DTRD

RTSA-RTSD

MODEM

CONTROL

LOGIC

CTSA-CTSD

RIA-RID

IRQ

TXRDY

RXRDY

CLOCK AND

BAUD RATE

GENERATOR

INTERRUPT

CONTROL

LOGIC

CDA-CDD

DSRA-DSRD

002aaa207

XTAL1 XTAL2 CLKSEL

Fig 2. SC16C654/654D block diagram (68 mode).

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SC16C654/654D

Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder

Philips Semiconductors

5. Pinning information

5.1 Pinning

5.1.1 PLCC68

DSRA 10

CTSA 11

DTRA 12

60 DSRD

59 CTSD

58 DTRD

57 GND

56 RTSD

55 INTD

54 CSD

53 TXD

V

13

CC

RTSA 14

INTA 15

CSA 16

TXA 17

IOW 18

TXB 19

52 IOR

SC16C654IA68

16 MODE

51 TXC

50 CSC

49 INTC

48 RTSC

CSB 20

INTB 21

RTSB 22

GND 23

DTRB 24

CTSB 25

DSRB 26

47

V

CC

46 DTRC

45 CTSC

44 DSRC

002aaa203

Fig 3. PLCC68 pin conﬁguration (16 mode).

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SC16C654/654D

Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder

Philips Semiconductors

DSRA 10

CTSA 11

DTRA 12

60 DSRD

59 CTSD

58 DTRD

57 GND

56 RTSD

55 NC

V

13

CC

RTSA 14

IRQ 15

CS 16

54 NC

TXA 17

R/W 18

TXB 19

A3 20

53 TXD

52 NC

51 TXC

50 A4

SC16C654IA68

68 MODE

NC 21

49 NC

48 RTSC

RTSB 22

GND 23

DTRB 24

CTSB 25

DSRB 26

47

V

CC

46 DTRC

45 CTSC

44 DSRC

002aaa205

Fig 4. PLCC68 pin conﬁguration (68 mode).

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SC16C654/654D

Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder

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5.1.2 LQFP64

DSRA

1

48 DSRD

47 CTSD

46 DTRD

45 GND

44 RTSD

43 INTD

42 CSD

CTSA

DTRA

2

3

4

5

6

7

8

9

V

CC

RTSA

INTA

CSA

TXA

41 TXD

SC16C654IB64

SC16C654DIB64

IOW

40 IOR

TXB 10

CSB 11

39 TXC

38 CSC

37 INTC

36 RTSC

INTB 12

RTSB 13

GND 14

DTRB 15

CTSB 16

35

V

CC

34 DTRC

33 CTSC

002aaa204

Fig 5. LQFP64 pin conﬁguration.

5.2 Pin description

Table 2:

Symbol

16/68

Pin description

Type Description

PLCC68 LQFP64

31

-

I

16/68 Interface type select (input with internal pull-up). This input provides

the 16 (Intel) or 68 (Motorola) bus interface type select. The functions of IOR,

IOW, INTA-INTD, and CSA-CSD are re-assigned with the logical state of this

pin. When this pin is a logic 1, the 16 mode interface (16C654) is selected.

When this pin is a logic 0, the 68 mode interface (68C654) is selected. When

this pin is a logic 0, IOW is re-assigned to R/W, RESET is re-assigned to

RESET, IOR is not used, and INTA-INTD are connected in a wire-OR

conﬁguration. The wire-OR outputs are connected internally to the open drain

IRQ signal output. This pin is not available on 64-pin packages which operate in

the 16 mode only.

A0

A1

A2

34

33

32

24

23

22

I

Address 0 select bit. Internal registers address selection in 16 and 68 modes.

Address 1 select bit. Internal registers address selection in 16 and 68 modes.

Address 2 select bit. Internal registers address selection in 16 and 68 modes.

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SC16C654/654D

Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder

Philips Semiconductors

Table 2:

Symbol

A3, A4

Pin description…continued

Type Description

PLCC68 LQFP64

20, 50

-

I

Address 3-4 select bits. When the 68 mode is selected, these pins are used

to address or select individual UARTs (providing CS is a logic 0). In the

16 mode, these pins are re-assigned as chip selects, see CSB and CSC. These

pins are not available on 64-pin packages which operate in the 16 mode only.

CDA, CDB,

CDC, CDD

9, 27,

43, 61

64, 18,

31, 49

I

Carrier Detect (Active-LOW). These inputs are associated with individual

UART channels A through D. A logic 0 on this pin indicates that a carrier has

been detected by the modem for that channel.

CLKSEL

30

-

Clock Select. The 1× or 4× pre-scalable clock is selected by this pin. The 1×

clock is selected when CLKSEL is a logic 1 (connected to V_CC) or the 4× is

selected when CLKSEL is a logic 0 (connected to GND). MCR[7] can override

the state of this pin following reset or initialization (see MCR[7]). This pin is not

available on 64-pin packages which provide MCR[7] selection only.

CS

16

-

I

Chip Select (Active-LOW). In the 68 mode, this pin functions as a multiple

channel chip enable. In this case, all four UARTs (A-D) are enabled when the

CS pin is a logic 0. An individual UART channel is selected by the data contents

of address bits A3-A4. when the 16 mode is selected (68-pin devices), this pin

functions as CSA (see deﬁnition under CSA, CSB). This pin is not available on

64-pin packages which operate in the 16 mode only.

CSA, CSB,

CSC, CSD

16, 20, 7, 11,

50, 54 38, 42

Chip Select A, B, C, D (Active-LOW). This function is associated with the

16 mode only, and for individual channels ‘A’ through ‘D’. When in 16 mode,

these pins enable data transfers between the user CPU and the

SC16C654/654D for the channel(s) addressed. Individual UART sections (A, B,

C, D) are addressed by providing a logic 0 on the respective CSA-CSD pin.

When the 68 mode is selected, the functions of these pins are re-assigned.

68 mode functions are described under their respective name/pin headings.

CTSA, CTSB, 11, 25, 2, 16,

I

Clear to Send (Active-LOW). These inputs are associated with individual

UART channels A through D. A logic 0 on the CTS pin indicates the modem or

data set is ready to accept transmit data from the SC16C654/654D. Status can

be tested by reading MSR[4]. This pin only affects the transmit or receive

operations when Auto CTS function is enabled via the Enhanced Feature

Register EFR[7] for hardware ﬂow control operation.

CTSC, CTSD 45, 59

33, 47

D0-D2,

D3-D7

66-68,

1-5

53-55,

56-60

I/O

I

Data bus (bi-directional). These pins are the 8-bit, 3-State data bus for

transferring information to or from the controlling CPU. D0 is the least

signiﬁcant bit and the ﬁrst data bit in a transmit or receive serial data stream.

DSRA,

DSRB,

DSRC, DSRD

10, 26, 1, 17,

44, 60 32, 48

Data Set Ready (Active-LOW). These inputs are associated with individual

UART channels, A through D. A logic 0 on this pin indicates the modem or data

set is powered-on and is ready for data exchange with the UART. This pin has

no effect on the UART’s transmit or receive operation.

DTRA,

DTRB,

DTRC, DTRD

12, 24, 3, 15,

O

Data Terminal Ready (Active-LOW). These outputs are associated with

individual UART channels, A through D. A logic 0 on this pin indicates that the

SC16C654/654D is powered-on and ready. This pin can be controlled via the

modem control register. Writing a logic 1 to MCR[0] will set the DTR output to

logic 0, enabling the modem. This pin will be a logic 1 after writing a logic 0 to

MCR[0], or after a reset. This pin has no effect on the UART’s transmit or

receive operation.

46, 58

34, 46

GND

6, 23,

40, 57

14, 28,

45, 61

I

Signal and power ground.

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SC16C654/654D

Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder

Philips Semiconductors

Table 2:

Symbol

Pin description…continued

Type Description

PLCC68 LQFP64

INTA, INTB,

INTC, INTD

15, 21, 6, 12,

O

Interrupt A, B, C, D (Active-HIGH). This function is associated with the

16 mode only. These pins provide individual channel interrupts INTA-INTD.

INTA-INTD are enabled when MCR[3] is set to a logic 1, interrupts are enabled

in the interrupt enable register (IER), and when an interrupt condition exists.

Interrupt conditions include: receiver errors, available receiver buffer data,

transmit buffer empty, or when a modem status ﬂag is detected. When the

68 mode is selected, the functions of these pins are re-assigned. 68 mode

functions are described under their respective name/pin headings.

49, 55

37, 43

INTSEL

65

-

I

Interrupt Select (Active-HIGH, with internal pull-down). This function is

associated with the 16 mode only. When the 16 mode is selected, this pin can

be used in conjunction with MCR[3] to enable or disable the 3-State interrupts,

INTA-INTD, or override MCR[3] and force continuous interrupts. Interrupt

outputs are enabled continuously by making this pin a logic 1. Making this pin a

logic 0 allows MCR[3] to control the 3-State interrupt output. In this mode,

MCR[3] is set to a logic 1 to enable the 3-State outputs. This pin is disabled in

the 68 mode. Due to pin limitations on the 64-pin packages, this pin is not

available. To cover this limitation, the SC16C654DIB64 version operates in the

continuous interrupt enable mode by bonding this pin to V_CCinternally. The

SC16C654IB64 operates with MCR[3] control by bonding this pin to GND.

IOR

52

18

40

9

I

Input/Output Read strobe (Active-LOW). This function is associated with the

16 mode only. A logic 0 transition on this pin will load the contents of an internal

register deﬁned by address bits A0-A2 onto the SC16C654/654D data bus

(D0-D7) for access by external CPU. This pin is disabled in the 68 mode.

IOW

Input/Output Write strobe (Active-LOW). This function is associated with the

16 mode only. A logic 0 transition on this pin will transfer the contents of the

data bus (D0-D7) from the external CPU to an internal register that is deﬁned

by address bits A0-A2. When the 16 mode is selected (PLCC68), this pin

functions as R/W (see deﬁnition under R/W).

IRQ

15

-

O

Interrupt Request or Interrupt ‘A’. This function is associated with the

68 mode only. In the 68 mode, interrupts from UART channels A-D are

wire-ORed internally to function as a single IRQ interrupt. This pin transitions to

a logic 0 (if enabled by the interrupt enable register) whenever a UART

channel(s) requires service. Individual channel interrupt status can be

determined by addressing each channel through its associated internal

register, using CS and A3-A4. In the 68 mode, and external pull-up resistor

must be connected between this pin and V_CC. The function of this pin changes

to INTA when operating in the 16 mode (see deﬁnition under INTA).

NC

21, 49,

52, 54,

55, 65

-

I

Not connected.

RESET,

RESET

37

27

Reset. In the 16 mode, a logic 1 on this pin will reset the internal registers and

all the outputs. The UART transmitter output and the receiver input will be

disabled during reset time. (See Section 7.11 “SC16C654/654D external reset

conditions” for initialization details.) When 16/68 is a logic 0 (68 mode), this pin

functions similarly, bus as an inverted reset interface signal, RESET.

RIA, RIB,

RIC, RID

8, 28,

42, 62

63, 19,

30, 50

I

Ring Indicator (Active-LOW). These inputs are associated with individual

UART channels, A through D. A logic 0 on this pin indicates the modem has

received a ringing signal from the telephone line. A logic 1 transition on this

input pin will generate an interrupt.

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SC16C654/654D

Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder

Philips Semiconductors

Table 2:

Symbol

Pin description…continued

Type Description

PLCC68 LQFP64

RTSA, RTSB, 14, 22, 5, 13,

RTSC, RTSD 48, 56 36, 44

O

Request to Send (Active-LOW). These outputs are associated with individual

UART channels, A through D. A logic 0 on the RTS pin indicates the transmitter

has data ready and waiting to send. Writing a logic 1 in the modem control

register MCR[1] will set this pin to a logic 0, indicating data is available. After a

reset this pin will be set to a logic 1. This pin only affects the transmit and

receive operations when Auto RTS function is enabled via the Enhanced

Feature Register (EFR[6]) for hardware ﬂow control operation.

R/W

18

-

I

Read/Write strobe. This function is associated with the 68 mode only. This pin

provides the combined functions for Read or Write strobes.

Logic 1 = Read from UART register selected by CS and A0-A4.

Logic 0 = Write to UART register selected by CS and A0-A4.

RXA, RXB,

RXC, RXD

7, 29,

41, 63

62, 20,

29, 51

Receive data input RXA-RXD. These inputs are associated with individual

serial channel data to the SC16C654/654D. The RX signal will be a logic 1

during reset, idle (no data), or when the transmitter is disabled. During the local

loop-back mode, the RX input pin is disabled and TX data is connected to the

UART RX input internally.

RXRDY

38

-

O

Receive Ready (Active-LOW). This function is associated with 68-pin package

only. RXRDY contains the wire-ORed status of all four receive channel FIFOs,

RXRDYA-RXRDYD. A logic 0 indicates receive data ready status, i.e., the RHR

is full, or the FIFO has one or more RX characters available for unloading. This

pin goes to a logic 1 when the FIFO/RHR is empty, or when there are no more

characters available in either the FIFO or RHR. Individual channel RX status is

read by examining individual internal registers via CS and A0-A4 pin functions.

TXA, TXB,

TXC, TXD

17, 19, 8, 10,

O

Transmit data A, B, C, D. These outputs are associated with individual serial

transmit channel data from the SC16C654/654D. The TX signal will be a logic 1

during reset, idle (no data), or when the transmitter is disabled. During the local

loop-back mode, the TX output pin is disabled and TX data is internally

connected to the UART RX input.

51, 53

39, 41

TXRDY

39

-

Transmit Ready (Active-LOW). This function is associated with the 68-pin

package only. TXRDY contains the wire-ORed status of all four transmit

channel FIFOs, TXRDYA-TXRDYD. A logic 0 indicates a buffer ready status,

i.e., at least one location is empty and available in one of the TX channels

(A-D). This pin goes to a logic 1 when all four channels have no more empty

locations in the TX FIFO or THR. Individual channel TX status can be read by

examining individual internal registers via CS and A0-A4 pin functions.

V_CC

13, 47, 4, 21,

I

Power supply inputs.

64

35, 52

XTAL1

35

25

Crystal or external clock input. Functions as a crystal input or as an external

clock input. A crystal can be connected between this pin and XTAL2 to form an

internal oscillator circuit (see Figure 6). Alternatively, an external clock can be

connected to this pin to provide custom data rates. (See Section 6.11

“Programmable baud rate generator”.)

XTAL2

36

26

O

Output of the crystal oscillator or buffered clock. (See also XTAL1.) Crystal

oscillator output or buffered clock output.

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SC16C654/654D

Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder

Philips Semiconductors

6. Functional description

The SC16C654/654D provides serial asynchronous receive data synchronization,

parallel-to-serial and serial-to-parallel data conversions for both the transmitter and

receiver sections. These functions are necessary for converting the serial data

stream into parallel data that is required with digital data systems. Synchronization for

the serial data stream is accomplished by adding start and stop bits to the transmit

data to form a data character. Data integrity is insured by attaching a parity bit to the

data character. The parity bit is checked by the receiver for any transmission bit

errors. The electronic circuitry to provide all these functions is fairly complex,

especially when manufactured on a single integrated silicon chip. The

SC16C654/654D represents such an integration with greatly enhanced features. The

SC16C654/654D is fabricated with an advanced CMOS process to achieve low drain

power and high speed requirements.

The SC16C654/654D is an upward solution that provides 64 bytes of transmit and

receive FIFO memory, instead of 16 bytes provided in the 16C554, or none in the

16C454. The SC16C654/654D is designed to work with high speed modems and

shared network environments that require fast data processing time. Increased

performance is realized in the SC16C654/654D by the larger transmit and receive

FIFOs. This allows the external processor to handle more networking tasks within a

given time. For example, the SC16C554 with a 16-byte FIFO unloads 16 bytes of

receive data in 1.53 ms. (This example uses a character length of 11 bits, including

start/stop bits at 115.2 kbit/s.) This means the external CPU will have to service the

receive FIFO at 1.53 ms intervals. However, with the 64-byte FIFO in the

SC16C654/654D, the data buffer will not require unloading/loading for 6.1 ms. This

increases the service interval, giving the external CPU additional time for other

applications and reducing the overall UART interrupt servicing time. In addition, the

four selectable levels of FIFO trigger interrupt and automatic hardware/software ﬂow

control is uniquely provided for maximum data throughput performance, especially

when operating in a multi-channel environment. The combination of the above greatly

reduces the bandwidth requirement of the external controlling CPU, increases

performance, and reduces power consumption.

The SC16C654/654D combines the package interface modes of the 16C454/554 and

68C454/554 series on a single integrated chip. The 16 mode interface is designed to

operate with the Intel-type of microprocessor bus, while the 68 mode is intended to

operate with Motorola and other popular microprocessors. Following a reset, the

SC16C654/654D is downward compatible with the 16C454/554 or the 68C454/554,

dependent on the state of the interface mode selection pin, 16/68.

The SC16C654/654D is capable of operation to 1.5 Mbits/s with a 24 MHz crystal and

up to 5 Mbits/s with an external clock input (at 3.3 V and 5 V; at 2.5 V the max speed

is 3 Mbits/s). With a crystal of 14.7464 MHz, and through a software option, the user

can select data rates up to 460.8 kbits/s or 921.6 kbits/s, 8 times faster than the

16C554.

The rich feature set of the SC16C654/654D is available through internal registers.

Automatic hardware/software ﬂow control, selectable transmit and receive FIFO

trigger levels, selectable TX and RX baud rates, infrared encoder/decoder interface,

modem interface controls, and a sleep mode are all standard features. MCR[5]

provides a facility for turning off (Xon) software ﬂow control with any incoming (RX)

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SC16C654/654D

Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder

Philips Semiconductors

character. In the 16 mode, INTSEL and MCR[3] can be conﬁgured to provide a

software controlled or continuous interrupt capability. Due to pin limitations of the

64-pin package, this feature is offered by two different LQFP64 packages. The

SC16C654D operates in the continuous interrupt enable mode by bonding INTSEL to

V_CCinternally. The SC16C654 operates in conjunction with MCR[3] by bonding

INTSEL to GND internally.

The PLCC68 SC16C654 package offers a clock select pin to allow system/board

designers to preset the default baud rate table. The CLKSEL pin selects the 1× or 4×

pre-scalable baud rate generator table during initialization, but can be overridden

following initialization by MCR[7].

6.1 Interface options

Two user interface modes are selectable for the PLCC68 package. These interface

modes are designated as the ‘16 mode’ and the ‘68 mode’. This nomenclature

corresponds to the early 16C454/554 and 68C454/554 package interfaces

respectively.

6.2 The 16 mode interface

The 16 mode conﬁgures the package interface pins for connection as a standard

16 series (Intel) device and operates similar to the standard CPU interface available

on the 16C454/554. In the 16 mode (pin 16/68 = logic 1), each UART is selected with

individual chip select (CSx) pins, as shown in Table 3.

Table 3:

Serial port channel selection, 16 mode interface

CSA

CSB

CSC

CSD

UART channel

1

0

1

0

1

0

1

0

none

A

B

C

D

6.3 The 68 mode interface

The 68 mode conﬁgures the package interface pins for connection with Motorola, and

other popular microprocessor bus types. The interface operates similar to the

68C454/554. In this mode, the SC16C654/654D decodes two additional addresses,

A3-A4, to select one of the four UART ports. The A3-A4 address decode function is

used only when in the 68 mode (16/68 = logic 0), and is shown in Table 4.

Table 4:

Serial port channel selection, 68 mode interface

CS

1

A4

n/a

0

A3

n/a

0

UART channel

none

A

0

1

B

0

1

0

C

0

1

D

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6.4 Internal registers

The SC16C654/654D provides 15 internal registers for monitoring and control. These

registers are shown in Table 5. Twelve registers are similar to those already available

in the standard 16C554. These registers function as data holding registers

(THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control register

(FCR), line status and control registers (LCR/LSR), modem status and control

registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM),

and a user accessible scratchpad register (SPR). Beyond the general 16C554

features and capabilities, the SC16C654/654D offers an enhanced feature register

set (EFR, Xon/Xoff1-2) that provides on-board hardware/software ﬂow control.

Register functions are more fully described in the following paragraphs.

Table 5:

A2

Internal registers decoding

A0 READ mode

A1

WRITE mode

General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR)^[1]

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Receive Holding Register

Interrupt Status Register

Transmit Holding Register

Interrupt Enable Register

FIFO Control Register

Line Control Register

Modem Control Register

n/a

Line Status Register

Modem Status Register

Scratchpad Register

n/a

Scratchpad Register

Baud rate register set (DLL/DLM)^[2]

0

LSB of Divisor Latch

MSB of Divisor Latch

0

1

MSB of Divisor Latch

Enhanced register set (EFR, Xon/off 1-2)^[3]

0

1

0

1

0

1

0

1

Enhanced Feature Register

Xon1 word

Enhanced Feature Register

Xon1 word

Xon2 word

Xoff1 word

Xoff2 word

[1] These registers are accessible only when LCR[7] is a logic 0.

[2] These registers are accessible only when LCR[7] is a logic 1.

[3] Enhanced Feature Register, Xon1, 2 and Xoff1, 2 are accessible only when the LCR is set to

“BF” (HEX).

6.5 FIFO operation

The 64-byte transmit and receive data FIFOs are enabled by the FIFO Control

Register (FCR) bit 0. With SC16C554 devices, the user can set the receive trigger

level, but not the transmit trigger level. The SC16C654/654D provides independent

trigger levels for both receiver and transmitter. To remain compatible with SC16C554,

the transmit interrupt trigger level is set to 8 following a reset. It should be noted that

the user can set the transmit trigger levels by writing to the FCR register, but

activation will not take place until EFR[4] is set to a logic 1. The receiver FIFO section

includes a time-out function to ensure data is delivered to the external CPU. An

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Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder

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interrupt is generated whenever the Receive Holding Register (RHR) has not been

read following the loading of a character or the receive trigger level has not been

reached. (For a description of this timing, see Section 6.6 “Hardware ﬂow control”.)

Table 6:

RX trigger levels

Selected trigger level

(characters)

INT pin activation

Negate RTS or

send Xoff

Assert RTS or

send Xon

(characters)

8

16

56

60

0

16

56

60

16

56

60

7

15

55

6.6 Hardware ﬂow control

When automatic hardware ﬂow control is enabled, the SC16C654/654D monitors the

CTS pin for a remote buffer overﬂow indication and controls the RTS pin for local

buffer overﬂows. Automatic hardware ﬂow control is selected by setting EFR[6] (RTS)

and EFR[7] (CTS) to a logic 1. If CTS transitions from a logic 0 to a logic 1 indicating

a ﬂow control request, ISR[5] will be set to a logic 1 (if enabled via IER[6,7]), and the

SC16C654/654D will suspend TX transmissions as soon as the stop bit of the

character in process is shifted out. Transmission is resumed after the CTS input

returns to a logic 0, indicating more data may be sent.

With the Auto RTS function enabled, an interrupt is generated when the receive FIFO

reaches the programmed trigger level. The RTS pin will not be forced to a logic 1

(RTS off), until the receive FIFO reaches the next trigger level. However, the RTS pin

will return to a logic 0 after the data buffer (FIFO) is unloaded to the next trigger level

below the programmed trigger. However, under the above described conditions, the

SC16C654/654D will continue to accept data until the receive FIFO is full.

6.7 Software ﬂow control

When software ﬂow control is enabled, the SC16C654/654D compares one or two

sequential receive data characters with the programmed Xon/Xoff or Xoff1,2

character value(s). If received character(s) match the programmed values, the

SC16C654/654D will halt transmission (TX) as soon as the current character(s) has

completed transmission. When a match occurs, the receive ready (if enabled via Xoff

IER[5]) ﬂags will be set and the interrupt output pin (if receive interrupt is enabled) will

be activated. Following a suspension due to a match of the Xoff characters’ values,

the SC16C654/654D will monitor the receive data stream for a match to the Xon1,2

character value(s). If a match is found, the SC16C654/654D will resume operation

and clear the ﬂags (ISR[4]). The SC16C654/654D offers a special Xon mode via

MCR[5]. The initialized default setting of MCR[5] is a logic 0. In this state, Xoff and

Xon will operate as deﬁned above. Setting MCR[5] to a logic 1 sets a special

operational mode for the Xon function. In this case, Xoff operates normally, however,

transmission (Xon) will resume with the next character received, i.e., a match is

declared simply by the receipt of an incoming (RX) character.

Reset initially sets the contents of the Xon/Xoff 8-bit ﬂow control registers to a logic 0.

Following reset, the user can write any Xon/Xoff value desired for software ﬂow

control. Different conditions can be set to detect Xon/Xoff characters and

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suspend/resume transmissions. When double 8-bit Xon/Xoff characters are selected,

the SC16C654/654D compares two consecutive receive characters with two software

ﬂow control 8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions

accordingly. Under the above described ﬂow control mechanisms, ﬂow control

characters are not placed (stacked) in the user accessible RX data buffer or FIFO.

In the event that the receive buffer is overﬁlling and ﬂow control needs to be executed,

the SC16C654/654D automatically sends an Xoff message (when enabled) via the

serial TX output to the remote modem. The SC16C654/654D sends the Xoff1,2

characters as soon as received data passes the programmed trigger level. To clear

this condition, the SC16C654/654D will transmit the programmed Xon1,2 characters

as soon as receive data drops below the programmed trigger level.

6.8 Special feature software ﬂow control

A special feature is provided to detect an 8-bit character when EFR[5] is set. When

8-bit character is detected, it will be placed on the user-accessible data stack along

with normal incoming RX data. This condition is selected in conjunction with

EFR[0-3]. Note that software ﬂow control should be turned off when using this special

mode by setting EFR[0-3] to a logic 0.

The SC16C654/654D compares each incoming receive character with Xoff2 data. If a

match exists, the received data will be transferred to the FIFO, and ISR[4] will be set

to indicate detection of a special character. Although the Internal Register Table

(Table 8) shows each X-Register with eight bits of character information, the actual

number of bits is dependent on the programmed word length. Line Control Register

bits LCR[0-1] deﬁne the number of character bits, i.e., either 5 bits, 6 bits, 7 bits or

8 bits. The word length selected by LCR[0-1] also determine the number of bits that

will be used for the special character comparison. Bit 0 in the X-registers corresponds

with the LSB bit for the receive character.

6.9 Xon any feature

A special feature is provided to return the Xoff ﬂow control to the inactive state

following its activation. In this mode, any RX character received will return the Xoff

ﬂow control to the inactive state so that transmissions may be resumed with a remote

buffer. This feature is more fully deﬁned in Section 6.7 “Software ﬂow control”.

6.10 Hardware/software and time-out interrupts

Three special interrupts have been added to monitor the hardware and software ﬂow

control. The interrupts are enabled by IER[5-7]. Care must be taken when handling

these interrupts. Following a reset, the transmitter interrupt is enabled, the

SC16C654/654D will issue an interrupt to indicate that the Transmit Holding Register

is empty. This interrupt must be serviced prior to continuing operations. The LSR

register provides the current singular highest priority interrupt only. It could be noted

that CTS and RTS interrupts have lowest interrupt priority. A condition can exist

where a higher priority interrupt may mask the lower priority CTS/RTS interrupt(s).

Only after servicing the higher pending interrupt will the lower priority CTS/TRS

interrupt(s) be reﬂected in the status register. Servicing the interrupt without

investigating further interrupt conditions can result in data errors.

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When two interrupt conditions have the same priority, it is important to service these

interrupts correctly. Receive Data Ready and Receive Time Out have the same

interrupt priority (when enabled by IER[0]). The receiver issues an interrupt after the

number of characters have reached the programmed trigger level. In this case, the

SC16C654/654D FIFO may hold more characters than the programmed trigger level.

Following the removal of a data byte, the user should re-check LSR[0] for additional

characters. A Receive Time Out will not occur if the receive FIFO is empty. The

time-out counter is reset at the center of each stop bit received or each time the

receive holding register (RHR) is read. The actual time-out value is 4 character time.

In the 16 mode for the PLCC68 package, the system/board designer can optionally

provide software controlled 3-State interrupt operation. This is accomplished by

INTSEL and MCR[3]. When INTSEL interface pin is left open or made a logic 0,

MCR[3] controls the 3-State interrupt outputs, INTA-INTD. When INTSEL is a logic 1,

MCR[3] has no effect on the INTA-INTD outputs, and the package operates with

interrupt outputs enabled continuously.

6.11 Programmable baud rate generator

The SC16C654/654D supports high speed modem technologies that have increased

input data rates by employing data compression schemes. For example, a 33.6 kbit/s

modem that employs data compression may require a 115.2 kbit/s input data rate.

A 128.0 kbit/s ISDN modem that supports data compression may need an input

data rate of 460.8 kbit/s.

A single baud rate generator is provided for the transmitter and receiver, allowing

independent TX/RX channel control. The programmable Baud Rate Generator is

capable of accepting an input clock up to 80 MHz (for 3.3 V and 5 V operation), as

required for supporting a 5 Mbits/s data rate. The SC16C654/654D can be conﬁgured

for internal or external clock operation. For internal clock oscillator operation, an

industry standard microprocessor crystal (parallel resonant/22-33 pF load) is

connected externally between the XTAL1 and XTAL2 pins (see Figure 6).

Alternatively, an external clock can be connected to the XTAL1 pin to clock the

internal baud rate generator for standard or custom rates (see Table 7).

1.5 kΩ

X1

1.8432 MHz

C1

47 pF

C2

100 pF

C1

22 pF

C2

47 pF

002aaa169

Fig 6. Crystal oscillator connection.

The generator divides the input 16× clock by any divisor from 1 to 2¹⁶− 1. The

SC16C654/654D divides the basic external clock by 16. Further division of this 16×

clock provides two table rates to support low and high data rate applications using the

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same system design. After a hardware reset and during initialization, the

SC16C654/654D sets the default baud rate table according to the state of the

CLKSEL pin. A logic 1 on CLKSEL will set the 1× clock default, whereas logic 0 will

set the 4× clock default table. Following the default clock rate selection during

initialization, the rate tables can be changed by the internal register MCR[7]. Setting

MCR[7] to a logic 1 when CLKSEL is a logic 1 provides an additional divide-by-4,

whereas setting MCR[7] to a logic 0 only divides by 1. (See Table 7 and Figure 7.)

Customized Baud Rates can be achieved by selecting the proper divisor values for

the MSB and LSB sections of baud rate generator.

Programming the Baud Rate Generator Registers DLM (MSB) and DLL (LSB)

provides a user capability for selecting the desired ﬁnal baud rate. The example in

Table 7 shows the two selectable baud rate tables available when using a

7.3728 MHz crystal.

Table 7:

Baud rate generator programming table using a 7.3728 MHz clock

Output baud rate

User

DLM

DLL

16× clock divisor

program value program value

(HEX)

MCR[7] = 1 MCR[7] = 0 Decimal

HEX

900

180

C0

60

50

200

2304

384

192

96

48

24

12

6

09

01

00

80

C0

60

30

18

0C

06

03

02

01

300

1200

600

2400

1200

2400

4800

9600

19.2 k

38.4 k

57.6 k

115.2 k

4800

9600

30

19.2 k

38.4 k

76.8 k

153.6 k

230.4 k

460.8 k

18

0C

06

3

03

2

02

1

01

MCR[7] = 0

DIVIDE-BY-1

LOGIC

XTAL1

XTAL2

CLOCK

OSCILLATOR

LOGIC

BAUD RATE

GENERATOR

LOGIC

BAUDOUT

DIVIDE-BY-4

LOGIC

MCR[7] = 1

002aaa208

Fig 7. Baud rate generator circuitry.

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6.12 DMA operation

The SC16C654/654D FIFO trigger level provides additional ﬂexibility to the user for

block mode operation. LSR[5,6] provide an indication when the transmitter is empty

or has an empty location(s). The user can optionally operate the transmit and receive

FIFOs in the DMA mode (FCR[3]). When the transmit and receive FIFOs are enabled

and the DMA mode is de-activated (DMA Mode 0), the SC16C654/654D activates the

interrupt output pin for each data transmit or receive operation. When DMA mode is

activated (DMA Mode 1), the user takes the advantage of block mode operation by

loading or unloading the FIFO in a block sequence determined by the preset trigger

level. In this mode, the SC16C654/654D sets the interrupt output pin when characters

in the transmit FIFOs are below the transmit trigger level, or the characters in the

receive FIFOs are above the receive trigger level.

6.13 Sleep mode

The SC16C654/654D is designed to operate with low power consumption. A special

sleep mode is included to further reduce power consumption when the chip is not

being used. With EFR[4] and IER[4] enabled (set to a logic 1), the SC16C654/654D

enters the sleep mode, but resumes normal operation when a start bit is detected, a

change of state on any of the modem input pins RX, RI, CTS, DSR, CD, or a transmit

data is provided by the user. If the sleep mode is enabled and the SC16C654/654D is

awakened by one of the conditions described above, it will return to the sleep mode

automatically after the last character is transmitted or read by the user. In any case,

the seep mode will not be entered while an interrupt(s) is pending. The

SC16C654/654D will stay in the sleep mode of operation until it is disabled by setting

IER[4] to a logic 0.

6.14 Loop-back mode

The internal loop-back capability allows on-board diagnostics. In the loop-back mode,

the normal modem interface pins are disconnected and reconﬁgured for loop-back

internally. MCR[0-3] register bits are used for controlling loop-back diagnostic testing.

In the loop-back mode, OP1 and OP2 in the MCR register (bits 2-3) control the

modem RI and CD inputs, respectively. MCR signals DTR and RTS (bits 0-1) are

used to control the modem CTS and DSR inputs, respectively. The transmitter output

(TX) and the receiver input (RX) are disconnected from their associated interface

pins, and instead are connected together internally (see Figure 8). The CTS, DSR,

CD, and RI are disconnected from their normal modem control input pins, and instead

are connected internally to DTR, RTS, OP1 and OP2. Loop-back test data is entered

into the transmit holding register via the user data bus interface, D0-D7. The transmit

UART serializes the data and passes the serial data to the receive UART via the

internal loop-back connection. The receive UART converts the serial data back into

parallel data that is then made available at the user data interface D0-D7. The user

optionally compares the received data to the initial transmitted data for verifying

error-free operation of the UART TX/RX circuits.

In this mode, the receiver and transmitter interrupts are fully operational. The Modem

Control Interrupts are also operational. However, the interrupts can only be read

using lower four bits of the Modem Status Register (MSR[0-3]) instead of the four

Modem Status Register bits 4-7. The interrupts are still controlled by the IER.

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Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder

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SC16C654/654D

TRANSMIT

FIFO

TRANSMIT

SHIFT

TXA-TXD

REGISTERS

REGISTER

D0–D7

IOR

IOW

DATA BUS

AND

CONTROL LOGIC

RESET

FLOW

CONTROL

LOGIC

IR

ENCODER

RECEIVE

SHIFT

REGISTER

RECEIVE

FIFO

REGISTERS

RXA-RXD

FLOW

CONTROL

LOGIC

A0–A2

CSA-CSD

IR

DECODER

REGISTER

SELECT

LOGIC

RTSA-RTSD

DSRA-DSRD

DTRA-DTRD

MODEM

CONTROL

LOGIC

CTSA-CTSD

OP1A-OP1D

RIA-RID

INTA-INTD

TXRDY

RXRDY

CLOCK AND

BAUD RATE

GENERATOR

INTERRUPT

CONTROL

LOGIC

OP2A-OP2D

CDA-CDD

002aaa209

XTAL1

XTAL2

Fig 8. Internal loop-back mode diagram.

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7. Register descriptions

Table 8 details the assigned bit functions for the SC16C654/654D internal registers.

The assigned bit functions are more fully deﬁned in Section 7.1 through Section 7.11.

Table 8:

SC16C654/654D internal registers

Shaded bits are only accessible when EFR[4] is set.

A2 A1 A0 Register Default^[1]Bit 7

General Register Set^[2]

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

1

RHR

THR

IER

XX

00

bit 7

CTS

bit 6

RTS

bit 5

Xoff

bit 4

bit 3

bit 2

bit 1

bit 0

bit 4

Sleep

modem receive

transmit receive

interrupt interrupt interrupt mode

status

line status holding holding

interrupt interrupt

register register

0

1

0

1

0

1

FCR

ISR

00

01

00

60

RCVR

trigger

(MSB)

RCVR

trigger

(LSB)

TX

trigger

(MSB)

TXtrigger DMA

XMIT

FIFO reset FIFO

reset

RCVR

FIFO

enable

(LSB)

mode

select

FIFOs

INT

priority

bit 1

INT

priority

bit 0

INT

status

enabled enabled priority

bit 4

priority

bit 3

priority

bit 2

LCR

MCR

LSR

divisor

latch

enable

set

break

set parity even

parity

enable

stop bits

OP1

word

length

bit 1

word

length

bit 0

Clock

select

IR

enable

Xon Any loop back OP2,

RTS

DTR

INTx

enable

FIFO

data

error

trans.

empty

trans.

holding

empty

break

framing parity

overrun receive

error

interrupt error

error

data

ready

1

0

1

MSR

SPR

X0

FF

CD

RI

DSR

bit 5

CTS

bit 4

∆CD

∆RI

∆DSR

∆CTS

bit 7

bit 6

bit 3

bit 2

bit 1

bit 0

Special Register Set^[3]

0

DLL

XX

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 9

bit 0

bit 8

0

1

DLM

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

Enhanced Register Set^[4]

0

1

0

EFR

00

Auto

CTS

Auto

RTS

Special Enable

Cont-3

Cont-2 Tx, Cont-1

Rx Control Tx, Rx

Control

Cont-0

Tx, Rx

Control

char.

IER[4-7], Tx, Rx

ISR[4,5], Control

FCR[4,5],

select

MCR[5-7]

1

0

1

0

1

0

1

Xon-1

Xon-2

Xoff-1

Xoff-2

00

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 9

bit 1

bit 9

bit 0

bit 8

bit 0

bit 8

bit 15

bit 7

bit 14

bit 6

bit 13

bit 5

bit 12

bit 4

bit 11

bit 3

bit 10

bit 2

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

[1] The value shown represents the register’s initialized HEX value; X = n/a.

[2] These registers are accessible only when LCR[7] = 0.

[3] The Special Register set is accessible only when LCR[7] is set to a logic 1.

[4] Enhanced Feature Register, Xon-1,2 and Xoff-1,2 are accessible only when LCR is set to ‘BF_Hex’.

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7.1 Transmit (THR) and Receive (RHR) Holding Registers

The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and

Transmit Shift Register (TSR). The status of the THR is provided in the Line Status

Register (LSR). Writing to the THR transfers the contents of the data bus (D7-D0) to

the THR, providing that the THR or TSR is empty. The THR empty ﬂag in the LSR

register will be set to a logic 1 when the transmitter is empty or when data is

transferred to the TSR. Note that a write operation can be performed when the THR

empty ﬂag is set (logic 0 = FIFO full; logic 1 = at least one FIFO location available).

The serial receive section also contains an 8-bit Receive Holding Register (RHR).

Receive data is removed from the SC16C654/654D and receive FIFO by reading the

RHR register. The receive section provides a mechanism to prevent false starts. On

the falling edge of a start or false start bit, an internal receiver counter starts counting

clocks at the 16× clock rate. After 7-¹⁄₂clocks, the start bit time should be shifted to

the center of the start bit. At this time the start bit is sampled, and if it is still a logic 0

it is validated. Evaluating the start bit in this manner prevents the receiver from

assembling a false character. Receiver status codes will be posted in the LSR.

7.2 Interrupt Enable Register (IER)

The Interrupt Enable Register (IER) masks the interrupts from receiver ready,

transmitter empty, line status and modem status registers. These interrupts would

normally be seen on the INTA-INTD output pins in the 16 mode, or on wire-OR IRQ

output pin in the 68 mode.

Table 9:

Interrupt Enable Register bits description

Description

Bit

Symbol

IER[7]

7

CTS interrupt.

Logic 0 = Disable the CTS interrupt (normal default condition).

Logic 1 = Enable the CTS interrupt. The SC16C654/654D issues an

interrupt when the CTS pin transitions from a logic 0 to a logic 1.

6

5

IER[6]

IER[5]

RTS interrupt.

Logic 0 = Disable the RTS interrupt (normal default condition).

Logic 1 = Enable the RTS interrupt. The SC16C654/654D issues an

interrupt when the RTS pin transitions from a logic 0 to a logic 1.

Xoff interrupt.

Logic 0 = Disable the software ﬂow control, receive Xoff interrupt

(normal default condition).

Logic 1 = Enable the software ﬂow control, receive Xoff interrupt. See

Section 6.7 “Software ﬂow control” for details.

4

3

IER[4]

IER[3]

Sleep mode.

Logic 0 = Disable sleep mode (normal default condition).

Logic 1 = Enable sleep mode. See Section 6.13 “Sleep mode” for details.

Modem Status Interrupt.

Logic 0 = Disable the modem status register interrupt (normal default

condition).

Logic 1 = Enable the modem status register interrupt.

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Table 9:

Interrupt Enable Register bits description…continued

Bit

Symbol

Description

2

IER[2]

Receive Line Status interrupt. This interrupt will be issued whenever a fully

assembled receive character is transferred from RSR to the RHR/FIFO,

i.e., data ready, LSR[0].

Logic 0 = Disable the receiver line status interrupt (normal default

condition).

Logic 1 = Enable the receiver line status interrupt.

1

0

IER[1]

IER[0]

Transmit Holding Register interrupt. This interrupt will be issued whenever

the THR is empty, and is associated with LSR[1].

Logic 0 = Disable the transmitter empty interrupt (normal default

condition).

Logic 1 = Enable the transmitter empty interrupt.

Receive Holding Register interrupt. This interrupt will be issued when the

FIFO has reached the programmed trigger level, or is cleared when the

FIFO drops below the trigger level in the FIFO mode of operation.

Logic 0 = Disable the receiver ready interrupt (normal default condition).

Logic 1 = Enable the receiver ready interrupt.

7.2.1 IER versus Receive FIFO interrupt mode operation

When the receive FIFO (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1)

are enabled, the receive interrupts and register status will reﬂect the following:

• The receive data available interrupts are issued to the external CPU when the

FIFO has reached the programmed trigger level. It will be cleared when the FIFO

drops below the programmed trigger level.

• FIFO status will also be reﬂected in the user accessible ISR register when the

FIFO trigger level is reached. Both the ISR register status bit and the interrupt will

be cleared when the FIFO drops below the trigger level.

• The data ready bit (LSR[0]) is set as soon as a character is transferred from the

shift register to the receive FIFO. It is reset when the FIFO is empty.

7.2.2 IER versus Receive/Transmit FIFO polled mode operation

When FCR[0] = logic 1, resetting IER[0-3] enables the SC16C654/654D in the FIFO

polled mode of operation. Since the receiver and transmitter have separate bits in the

LSR, either or both can be used in the polled mode by selecting respective transmit or

receive control bit(s).

• LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.

• LSR[1-4] will provide the type of errors encountered, if any.

• LSR[5] will indicate when the transmit FIFO is empty.

• LSR[6] will indicate when both the transmit FIFO and transmit shift register are

empty.

• LSR[7] will indicate any FIFO data errors.

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7.3 FIFO Control Register (FCR)

This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive

FIFO trigger levels, and select the DMA mode.

7.3.1 DMA mode

Mode 0 (FCR bit 3 = 0): Set and enable the interrupt for each single transmit or

receive operation, and is similar to the 16C454 mode. Transmit Ready (TXRDY) will

go to a logic 0 whenever an empty transmit space is available in the Transmit Holding

Register (THR). Receive Ready (RXRDY) will go to a logic 0 whenever the Receive

Holding Register (RHR) is loaded with a character.

Mode 1 (FCR bit 3 = 1): Set and enable the interrupt in a block mode operation. The

transmit interrupt is set when the transmit FIFO is below the programmed trigger

level. TXRDY remains a logic 0 as long as one empty FIFO location is available. The

receive interrupt is set when the receive FIFO ﬁlls to the programmed trigger level.

However, the FIFO continues to ﬁll regardless of the programmed level until the FIFO

is full. RXRDY remains a logic 0 as long as the FIFO ﬁll level is above the

programmed trigger level.

7.3.2 FIFO mode

Table 10: FIFO Control Register bits description

Bit

Symbol

Description

7-6

FCR[7]

(MSB),

FCR[6]

(LSB)

RCVR trigger. These bits are used to set the trigger level for the receive

FIFO interrupt.

An interrupt is generated when the number of characters in the FIFO

equals the programmed trigger level. However, the FIFO will continue to

be loaded until it is full. Refer to Table 11.

5-4

FCR[5]

(MSB),

FCR[4]

(LSB)

TX trigger.

These bits are used to set the trigger level for the transmit FIFO

interrupt. The SC16C654/654D will issue a transmit empty interrupt

when the number of characters in FIFO drops below the selected trigger

level. Refer to Table 12.

3

FCR[3]

DMA mode select.

Logic 0 = Set DMA mode ‘0’ (normal default condition).

Logic 1 = Set DMA mode ‘1’

Transmit operation in mode ‘0’: When the SC16C654/654D is in the

16C450 mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode

(FIFOs enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there are

no characters in the transmit FIFO or transmit holding register, the

TXRDY pin will be a logic 0. Once active, the TXRDY pin will go to a

logic 1 after the ﬁrst character is loaded into the transmit holding

register.

Receive operation in mode ‘0’: When the SC16C654/654D is in

mode ‘0’ (FCR[0] = logic 0), or in the FIFO mode (FCR[0] = logic 1;

FCR[3] = logic 0) and there is at least one character in the receive FIFO,

the RXRDY pin will be a logic 0. Once active, the RXRDY pin will go to a

logic 1 when there are no more characters in the receiver.

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Table 10: FIFO Control Register bits description…continued

Bit

Symbol

Description

Transmit operation in mode ‘1’: When the SC16C654/654D is in FIFO

mode (FCR[0] = logic 1; FCR[3] = logic 1), the TXRDY pin will be a

logic 1 when the transmit FIFO is completely full. It will be a logic 0 when

the trigger level has been reached.

Receive operation in mode ‘1’: When the SC16C654/654D is in FIFO

mode (FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been

reached, or a Receive Time-Out has occurred, the RXRDY pin will go to

a logic 0. Once activated, it will go to a logic 1 after there are no more

characters in the FIFO.

2

1

0

FCR[2]

FCR[1]

FCR[0]

XMIT FIFO reset.

Logic 0 = No FIFO transmit reset (normal default condition).

Logic 1 = Clears the contents of the transmit FIFO and resets the

FIFO counter logic (the transmit shift register is not cleared or

altered). This bit will return to a logic 0 after clearing the FIFO.

RCVR FIFO reset.

Logic 0 = No FIFO receive reset (normal default condition).

Logic 1 = Clears the contents of the receive FIFO and resets the FIFO

counter logic (the receive shift register is not cleared or altered). This

bit will return to a logic 0 after clearing the FIFO.

FIFO enable.

Logic 0 = Disable the transmit and receive FIFO (normal default

condition).

Logic 1 = Enable the transmit and receive FIFO. This bit must be a

‘1’ when other FCR bits are written to, or they will not be

programmed.

Table 11: RCVR trigger levels

FCR[7]

FCR[6]

RX FIFO trigger level

0

1

0

1

0

1

08

16

56

60

Table 12: TX trigger levels

FCR[5]

FCR[4]

TX FIFO trigger level (# of characters)

0

1

0

1

0

1

08

16

32

56

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7.4 Interrupt Status Register (ISR)

The SC16C654/654D provides six levels of prioritized interrupts to minimize external

software interaction. The Interrupt Status Register (ISR) provides the user with six

interrupt status bits. Performing a read cycle on the ISR will provide the user with the

highest pending interrupt level to be serviced. No other interrupts are acknowledged

until the pending interrupt is serviced. Whenever the interrupt status register is read,

the interrupt status is cleared. However, it should be noted that only the current

pending interrupt is cleared by the read. A lower level interrupt may be seen after

re-reading the interrupt status bits. Table 13 “Interrupt source” shows the data values

(bits 0-5) for the six prioritized interrupt levels and the interrupt sources associated

with each of these interrupt levels.

Table 13: Interrupt source

Priority ISR[5] ISR[4] ISR[3] ISR[2] ISR[1] ISR[0] Source of the interrupt

level

1

2

3

4

5

6

0

1

0

1

0

1

0

1

0

1

0

1

0

LSR (Receiver Line Status

Register)

RXRDY (Received Data

Ready)

RXRDY (Receive Data

time-out)

TXRDY (Transmitter

Holding Register Empty)

MSR (Modem Status

Register)

RXRDY (Received Xoff

signal) / Special character

CTS, RTS change of state

Table 14: Interrupt Status Register bits description

Bit

Symbol

Description

7-6

ISR[7-6]

FIFOs enabled. These bits are set to a logic 0 when the FIFO is

not being used. They are set to a logic 1 when the FIFOs are

enabled.

Logic 0 or cleared = default condition.

5-4

ISR[5-4]

INT priority bits 4-3. These bits are enabled when EFR[4] is set to

a logic 1. ISR[4] indicates that matching Xoff character(s) have

been detected. ISR[5] indicates that CTS, RTS have been

generated. Note that once set to a logic 1, the ISR[4] bit will stay a

logic 1 until Xon character(s) are received.

Logic 0 or cleared = default condition.

3-1

0

ISR[3-1]

ISR[0]

INT priority bits 2-0. These bits indicate the source for a pending

interrupt at interrupt priority levels 1, 2, and 3 (see Table 13).

Logic 0 or cleared = default condition.

INT status.

Logic 0 = An interrupt is pending and the ISR contents may be

used as a pointer to the appropriate interrupt service routine.

Logic 1 = No interrupt pending (normal default condition).

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7.5 Line Control Register (LCR)

The Line Control Register is used to specify the asynchronous data communication

format. The word length, the number of stop bits, and the parity are selected by

writing the appropriate bits in this register.

Table 15: Line Control Register bits description

Bit

Symbol

Description

7

LCR[7]

Divisor latch enable. The internal baud rate counter latch and

Enhance Feature mode enable.

Logic 0 = Divisor latch disabled (normal default condition).

Logic 1 = Divisor latch and enhanced feature register enabled.

6

5

LCR[6]

LCR[5]

Set break. When enabled, the Break control bit causes a break

condition to be transmitted (the TX output is forced to a logic 0

state). This condition exists until disabled by setting LCR[6] to a

logic 0.

Logic 0 = no TX break condition (normal default condition).

Logic 1 = forces the transmitter output (TX) to a logic 0 for

alerting the remote receiver to a line break condition.

Set parity. If the parity bit is enabled, LCR[5] selects the forced

parity format. Programs the parity conditions (see Table 16).

Logic 0 = parity is not forced (normal default condition).

LCR[5] = logic 1 and LCR[4] = logic 0: parity bit is forced to a

logical 1 for the transmit and receive data.

LCR[5] = logic 1 and LCR[4] = logic 1: parity bit is forced to a

logical 0 for the transmit and receive data.

4

LCR[4]

Even parity. If the parity bit is enabled with LCR[3] set to a logic 1,

LCR[4] selects the even or odd parity format.

Logic 0 = ODD Parity is generated by forcing an odd number of

logic 1s in the transmitted data. The receiver must be

programmed to check the same format (normal default

condition).

Logic 1 = EVEN Parity is generated by forcing an even number

of logic 1s in the transmitted data. The receiver must be

programmed to check the same format.

3

LCR[3]

Parity enable. Parity or no parity can be selected via this bit.

Logic 0 = no parity (normal default condition).

Logic 1 = a parity bit is generated during the transmission,

receiver checks the data and parity for transmission errors.

2

LCR[2]

Stop bits. The length of stop bit is speciﬁed by this bit in

conjunction with the programmed word length (see Table 17).

Logic 0 or cleared = default condition.

1-0

LCR[1-0]

Word length bits 1, 0. These two bits specify the word length to be

transmitted or received (see Table 18).

Logic 0 or cleared = default condition.

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Table 16: LCR[5] parity selection

LCR[5]

LCR[4]

LCR[3]

Parity selection

no parity

X

0

1

X

0

1

0

1

0

1

ODD parity

EVEN parity

force parity ‘1’

forced parity ‘0’

Table 17: LCR[2] stop bit length

LCR[2]

Word length

5, 6, 7, 8

5

Stop bit length (bit times)

0

1

1-¹⁄₂

6, 7, 8

2

Table 18: LCR[1-0] word length

LCR[1]

LCR[0]

Word length

0

1

0

1

0

1

5

6

7

8

7.6 Modem Control Register (MCR)

This register controls the interface with the modem or a peripheral device.

Table 19: Modem Control Register bits description

Bit

Symbol

Description

7

MCR[7]

Clock select.

Logic 0 = Divide-by-1. The input clock (crystal or external) is

divided by 16 and then presented to the Programmable Baud Rate

Generator (BGR) without further modiﬁcation, i.e., divide-by-1.

(normal default condition).

Logic 1 = Divide-by-4. The divide-by-1 clock described in MCR[7] =

a logic 0, if further divided by four. Also see Section 6.11

“Programmable baud rate generator”.

6

MCR[6]

IR enable.

Logic 0 = Enable the standard modem receive and transmit

input/output interface (normal default condition).

Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs.

While in this mode, the TX/RX output/inputs are routed to the

infrared encoder/decoder. The data input and output levels will

conform to the IrDA infrared interface requirement. As such, while

in this mode, the infrared TX output will be a logic 0 during idle data

conditions.

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Table 19: Modem Control Register bits description…continued

Bit

Symbol

Description

5

MCR[5]

Xon Any.

Logic 0 = Disable Xon Any function (for 16C550 compatibility)

(normal default condition).

Logic 1 = Enable Xon Any function. In this mode, any RX character

received will enable Xon

4

MCR[4]

Loop-back. Enable the local loop-back mode (diagnostics). In this

mode the transmitter output (TX) and the receiver input (RX), CTS,

DSR, CD, and RI are disconnected from the SC16C654/654D I/O

pins. Internally the modem data and control pins are connected into a

loop-back data conﬁguration (see Figure 8). In this mode, the receiver

and transmitter interrupts remain fully operational. The Modem

Control Interrupts are also operational, but the interrupts’ sources are

switched to the lower four bits of the Modem Control. Interrupts

continue to be controlled by the IER register.

Logic 0 = Disable loop-back mode (normal default condition).

Logic 1 = Enable local loop-back mode (diagnostics).

3

MCR[3]

OP2, INTx enable. Used to control the modem CD signal in the

loop-back mode.

Logic 0 = Forces INTA-INTD outputs to the 3-State mode during

the 16 mode (normal default condition). In the loop-back mode,

sets OP2 (CD) internally to a logic 1.

Logic 1 = Forces the INTA-INTD outputs to the active mode during

the 16 mode. In the loop-back mode, sets OP2 (CD) internally to a

logic 0.

2

1

MCR[2]

MCR[1]

OP1. This bit is used in the Loop-back mode only. In the loop-back

mode, this bit is used to write the state of the modem RI interface

signal via OP1.

RTS

Logic 0 = Force RTS output to a logic 1 (normal default condition).

Logic 1 = Force RTS output to a logic 0.

Automatic RTS may be used for hardware ﬂow control by enabling

EFR[6]. See Table 22.

0

MCR[0]

DTR

Logic 0 = Force DTR output to a logic 1 (normal default condition).

Logic 1 = Force DTR output to a logic 0.

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7.7 Line Status Register (LSR)

This register provides the status of data transfers between the SC16C654/654D and

the CPU.

Table 20: Line Status Register bits description

Bit

Symbol

Description

7

LSR[7]

FIFO data error.

Logic 0 = No error (normal default condition).

Logic 1 = At least one parity error, framing error or break indication is in

the current FIFO data. This bit is cleared when LSR register is read.

6

5

LSR[6]

LSR[5]

THR and TSR empty. This bit is the Transmit Empty indicator. This bit is

set to a logic 1 whenever the transmit holding register and the transmit

shift register are both empty. It is reset to logic 0 whenever either the THR

or TSR contains a data character. In the FIFO mode, this bit is set to ‘1’

whenever the transmit FIFO and transmit shift register are both empty.

THR empty. This bit is the Transmit Holding Register Empty indicator.

This bit indicates that the UART is ready to accept a new character for

transmission. In addition, this bit causes the UART to issue an interrupt to

CPU when the THR interrupt enable is set. The THR bit is set to a logic 1

when a character is transferred from the transmit holding register into the

transmitter shift register. The bit is reset to a logic 0 concurrently with the

loading of the transmitter holding register by the CPU. In the FIFO mode,

this bit is set when the transmit FIFO is empty; it is cleared when at least

1 byte is written to the transmit FIFO.

4

3

2

1

LSR[4]

LSR[3]

LSR[2]

LSR[1]

Break interrupt.

Logic 0 = No break condition (normal default condition).

Logic 1 = The receiver received a break signal (RX was a logic 0 for

one character frame time). In the FIFO mode, only one break character

is loaded into the FIFO.

Framing error.

Logic 0 = No framing error (normal default condition).

Logic 1 = Framing error. The receive character did not have a valid stop

bit(s). In the FIFO mode, this error is associated with the character at

the top of the FIFO.

Parity error.

Logic 0 = No parity error (normal default condition).

Logic 1 = Parity error. The receive character does not have correct

parity information and is suspect. In the FIFO mode, this error is

associated with the character at the top of the FIFO.

Overrun error.

Logic 0 = No overrun error (normal default condition).

Logic 1 = Overrun error. A data overrun error occurred in the receive

shift register. This happens when additional data arrives while the FIFO

is full. In this case, the previous data in the shift register is overwritten.

Note that under this condition, the data byte in the receive shift register

is not transferred into the FIFO, therefore the data in the FIFO is not

corrupted by the error.

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Table 20: Line Status Register bits description…continued

Bit

Symbol

Description

0

LSR[0]

Receive data ready.

Logic 0 = No data in receive holding register or FIFO (normal default

condition).

Logic 1 = Data has been received and is saved in the receive holding

register or FIFO.

7.8 Modem Status Register (MSR)

This register provides the current state of the control interface signals from the

modem, or other peripheral device to which the SC16C654/654D is connected.

Four bits of this register are used to indicate the changed information. These bits are

set to a logic 1 whenever a control input from the modem changes state. These bits

are set to a logic 0 whenever the CPU reads this register.

Table 21: Modem Status Register bits description

Bit

Symbol

Description

7

MSR[7]

CD (Active-HIGH, logical 1). Normally this bit is the complement of the

CD input. In the loop-back mode this bit is equivalent to the OP2 bit in the

MCR register.

6

5

4

MSR[6]

MSR[5]

MSR[4]

RI (Active-HIGH, logical 1). Normally this bit is the complement of the RI

input. In the loop-back mode this bit is equivalent to the OP1 bit in the

MCR register.

DSR (Active-HIGH, logical 1). Normally this bit is the complement of the

DSR input. In loop-back mode this bit is equivalent to the DTR bit in the

MCR register.

CTS. CTS functions as hardware ﬂow control signal input if it is enabled

via EFR[7]. The transmit holding register ﬂow control is enabled/disabled

by MSR[4]. Flow control (when enabled) allows starting and stopping the

transmissions based on the external modem CTS signal. A logic 1 at the

CTS pin will stop SC16C654/654D transmissions as soon as current

character has ﬁnished transmission. Normally MSR[4] is the complement

of the CTS input. However, in the loop-back mode, this bit is equivalent to

the RTS bit in the MCR register.

3

2

MSR[3]

MSR[2]

∆CD ^[1]

Logic 0 = No CD change (normal default condition).

Logic 1 = The CD input to the SC16C654/654D has changed state

since the last time it was read. A modem Status Interrupt will be

generated.

∆RI ^[1]

Logic 0 = No RI change (normal default condition).

Logic 1 = The RI input to the SC16C654/654D has changed from a

logic 0 to a logic 1. A modem Status Interrupt will be generated.

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Table 21: Modem Status Register bits description…continued

Bit

Symbol

Description

1

MSR[1]

∆DSR ^[1]

Logic 0 = No DSR change (normal default condition).

Logic 1 = The DSR input to the SC16C654/654D has changed state

since the last time it was read. A Modem Status Interrupt will be

generated.

0

MSR[0]

∆CTS ^[1]

Logic 0 = No CTS change (normal default condition).

Logic 1 = The CTS input to the SC16C654/654D has changed state

since the last time it was read. A Modem Status Interrupt will be

generated.

[1] Whenever any MSR bit 0-3 is set to logic 1, a Modem Status Interrupt will be generated.

7.9 Scratchpad Register (SPR)

The SC16C654/654D provides a temporary data register to store 8 bits of user

information.

7.10 Enhanced Feature Register (EFR)

Enhanced features are enabled or disabled using this register.

Bits 0 through 4 provide single or dual character software ﬂow control selection.

When the Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double

8-bit words are concatenated into two sequential numbers.

Table 22: Enhanced Feature Register bits description

Bit

Symbol

Description

7

EFR[7]

Auto CTS. Automatic CTS Flow Control.

Logic 0 = Automatic CTS ﬂow control is disabled (normal default

condition).

Logic 1 = Enable Automatic CTS ﬂow control. Transmission will stop

when CTS goes to a logical 1. Transmission will resume when the CTS

pin returns to a logical 0.

6

EFR[6]

Auto RTS. Automatic RTS may be used for hardware ﬂow control by

enabling EFR[6]. When Auto RTS is selected, an interrupt will be

generated when the receive FIFO is ﬁlled to the programmed trigger

level and RTS will go to a logic 1 at the next trigger level. RTS will return

to a logic 0 when data is unloaded below the next lower trigger level

(Programmed trigger level -1). The state of this register bit changes with

the status of the hardware ﬂow control. RTS functions normally when

hardware ﬂow control is disabled.

Logic 0 = Automatic RTS ﬂow control is disabled (normal default

condition).

Logic 1 = Enable Automatic RTS ﬂow control.

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Table 22: Enhanced Feature Register bits description…continued

Bit

Symbol

Description

5

EFR[5]

Special Character Detect.

Logic 0 = Special character detect disabled (normal default condition).

Logic 1 = Special character detect enabled. The SC16C654/654D

compares each incoming receive character with Xoff2 data. If a match

exists, the received data will be transferred to FIFO and ISR[4] will be

set to indicate detection of special character. Bit-0 in the X-registers

corresponds with the LSB bit for the receive character. When this

feature is enabled, the normal software ﬂow control must be disabled

(EFR[3-0] must be set to a logic 0).

4

EFR[4]

Enhanced function control bit. The content of IER[7-4], ISR[5-4],

FCR[5-4], and MCR[7-5] can be modiﬁed and latched. After modifying

any bits in the enhanced registers, EFR[4] can be set to a logic 0 to latch

the new values. This feature prevents existing software from altering or

overwriting the SC16C654/654D enhanced functions.

Logic 0 = Disable (normal default condition).

Logic 1 = Enable.

3-0

EFR[3-0] Cont-3-0 Tx, Rx control. Logic 0 or cleared is the default condition.

Combinations of software ﬂow control can be selected by programming

these bits. See Table 23.

Table 23: Software ﬂow control functions^[1]

Cont-3 Cont-2 Cont-1 Cont-0 TX, RX software ﬂow controls

0

1

0

1

X

1

0

1

X

0

X

0

1

0

1

X

0

1

No transmit ﬂow control

Transmit Xon1/Xoff1

Transmit Xon2/Xoff2

Transmit Xon1 and Xon2/Xoff1 and Xoff2

No receive ﬂow control

Receiver compares Xon1/Xoff1

Receiver compares Xon2/Xoff2

Transmit Xon1/Xoff1

Receiver compares Xon1 and Xon2, Xoff1 and Xoff2

Transmit Xon2/Xoff2

0

1

Receiver compares Xon1 and Xon2/Xoff1 and Xoff2

Transmit Xon1 and Xon2/Xoff1 and Xoff2

Receiver compares Xon1 and Xon2/Xoff1 and Xoff2

[1] When using software ﬂow control the Xon/Xoff characters cannot be used for data transfer.

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7.11 SC16C654/654D external reset conditions

Table 24: Reset state for registers

Register

IER

Reset state

IER[7-0] = 0

ISR

ISR[7-1] = 0; ISR[0] = 1

LCR[7-0] = 0

LCR

MCR

LSR

MCR[7-0] = 0

LSR[7] = 0; LSR[6-5] = 1; LSR[4-0] = 0

MSR[7-4] = input signals; MSR[3-0] = 0

FCR[7-0] = 0

MSR

FCR

EFR

EFR[7-0] = 0

Table 25: Reset state for outputs

Output

Reset state

HIGH

TXA, TXB, TXC, TXD

RTSA, RTSB, RTSC, RTSD

DTRA, DTRB, DTRC, DTRD

RXRDY

HIGH

TXRDY

LOW

8. Limiting values

Table 26: Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_CC

Parameter

Conditions

Min

Max

Unit

V

supply voltage

-

7

V_n

voltage at any pin

operating temperature

storage temperature

GND − 0.3 V_CC+ 0.3

V

T_amb

−40

−65

-

+85

°C

mW

T_stg

+150

500

P_tot(pack)

total power dissipation per

package

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10. Dynamic characteristics

Table 28: AC electrical characteristics

T_amb= −40 °C to +85 °C; V_CC= 2.5 V, 3.3 V or 5.0 V ±10%, unless otherwise speciﬁed.

Symbol Parameter

Conditions

2.5 V

Max

3.3 V

Max

5.0 V

Unit

Min

10

-

Min

6

Min Max

t_1w, t_2w

t_3w

clock pulse duration

-

6

-

ns

MHz

ns

[1]

oscillator/clock frequency

address set-up time

address hold time

48

-

80

-

80

-

t_6s

0

-

0

t_6h

0

-

0

-

0

-

t_7d

IOR delay from chip select

IOR strobe width

10

77

0

-

10

26

0

-

10

23

0

-

t_7w

25 pF load

-

t_7h

chip select hold time from IOR

read cycle delay

-

t_9d

25 pF load

20

-

20

-

20

-

t_12d

t_12h

t_13d

t_13w

t_13h

t_15d

t_16s

t_16h

t_17d

t_18d

delay from IOR to data

data disable time

77

26

15

-

23

15

-

15

-

IOW delay from chip select

IOW strobe width

10

20

0

-

10

20

0

10

15

0

[2]

[3]

-

chip select hold time from IOW

write cycle delay

-

25

20

15

-

25

20

5

-

20

15

5

-

data set-up time

-

data hold time

-

delay from IOW to output

25 pF load

100

-

33

24

-

29

23

delay to set interrupt from Modem 25 pF load

input

-

t_19d

t_20d

t_21d

t_22d

t_23d

t_24d

t_25d

t_26d

t_27d

t_28d

t_30s

t_30w

t_30h

t_30d

t_31d

t_31h

t_32s

t_32h

delay to reset interrupt from IOR

delay from stop to set interrupt

delay from IOR to reset interrupt

delay from start to set interrupt

delay from IOW to transmit start

delay from IOW to reset interrupt

delay from stop to set RXRDY

delay from IOR to reset RXRDY

delay from IOW to set TXRDY

delay from start to reset TXRDY

address set-up time

25 pF load

-

100

1

-

24

1

-

23

1

ns

-

R_clk

ns

25 pF load

-

100

24

100

1

-

29

45

24

45

1

-

28

40

24

40

1

-

ns

8

-

8

-

8

-

R_clk

ns

-

R_clk

ns

-

100

8

-

45

8

-

40

8

-

ns

-

R_clk

ns

10

90

15

20

-

10

26

15

20

-

10

23

15

20

-

[1]

chip select strobe width

25 pF load

-

ns

address hold time

-

ns

read cycle delay

25 pF load

-

ns

delay from CS to data

90

15

-

26

15

-

23

15

-

ns

data disable time

-

ns

write strobe set-up time

10

ns

write strobe hold time

-

ns

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Table 28: AC electrical characteristics…continued

T_amb= −40 °C to +85 °C; V_CC= 2.5 V, 3.3 V or 5.0 V ±10%, unless otherwise speciﬁed.

Symbol Parameter

Conditions

2.5 V

Max

3.3 V

Max

5.0 V

Unit

Min

25

20

15

200

1

Min

25

15

5

Min Max

[3]

t_32d

t_33s

t_33h

t_RESET

N

write cycle delay

-

20

15

5

-

ns

data set-up time

data hold time

-

Reset pulse width

baud rate divisor

-

40

1

-

40

1

2¹⁶− 1

2¹⁶− 1 R_clk

[1] Applies to external clock, crystal oscillator max 24 MHz.

1

[2] IOWstrobe_max

=

--------------------------------------

2(Baudrate_max

)

= 333 ns (for Baudrate_max= 1.5 Mbits/s)

= 1 µs (for Baudrate_max= 460.8 kbits/s)

= 4 µs (for Baudrate_max= 115.2 kbits/s)

[3] When in both DMA mode 0 and FIFO enable mode, the write cycle delay should be larger than one x₁, clock cycle.

10.1 Timing diagrams

A0–A4

t

30h

t

30w

30s

t

30d

CS

t

31h

32s

R/W

t

31d

D0–D7

002aaa210

Fig 9. General read timing in 68 mode.

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A0–A4

t

30h

30s

30w

CS

t

32d

32s

32h

R/W

t

33h

t

33s

D0–D7

002aaa211

Fig 10. General write timing in 68 mode.

t

6h

VALID

ADDRESS

A0–A2

t

6s

t

13h

ACTIVE

CS

t

13d

t

15d

t

13w

IOW

ACTIVE

t

16h

t

16s

D0–D7

DATA

002aaa171

Fig 11. General write timing in 16 mode.

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t

6h

VALID

ADDRESS

A0–A2

t

6s

t

7h

ACTIVE

CS

t

7d

t

9d

t

7w

IOR

ACTIVE

t

12h

t

12d

D0–D7

DATA

002aaa172

Fig 12. General read timing in 16 mode.

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IOW

ACTIVE

t

17d

RTS

DTR

CHANGE OF STATE

CD

CTS

DSR

CHANGE OF STATE

t

18d

INT

ACTIVE

t

19d

IOR

ACTIVE

t

18d

RI

CHANGE OF STATE

002aaa352

Fig 13. Modem input/output timing.

t

1w

2w

EXTERNAL

CLOCK

002aaa112

t

3w

Fig 14. External clock timing.

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START

BIT

PARITY STOP START

BIT

DATA BITS (5-8)

RX

D0

D1

D2

D3

D4

D5

D6

D7

5 DATA BITS

6 DATA BITS

7 DATA BITS

t

20d

ACTIVE

INT

t

21d

ACTIVE

IOR

16 BAUD RATE CLOCK

002aaa113

Fig 15. Receive timing.

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START

BIT

PARITY STOP START

BIT

DATA BITS (5–8)

RX

D0

D1

D2

D3

D4

D5

D6

D7

t

25d

ACTIVE

DATA

READY

RXRDY

t

26d

ACTIVE

IOR

002aaa114

Fig 16. Receive ready timing in non-FIFO mode.

START

BIT

PARITY STOP

BIT BIT

DATA BITS (5–8)

RX

D0

D1

D2

D3

D4

D5

D6

D7

FIRST BYTE THAT

REACHES THE

TRIGGER LEVEL

t

25d

ACTIVE

DATA

READY

RXRDY

t

26d

ACTIVE

IOR

002aaa115

Fig 17. Receive ready timing in FIFO mode.

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START

BIT

PARITY STOP START

BIT

DATA BITS (5–8)

TX

D0

D1

D2

D3

D4

D5

D6

D7

5 DATA BITS

6 DATA BITS

7 DATA BITS

ACTIVE TX READY

INT

t

22d

t

24d

t

23d

ACTIVE

IOW

16 BAUD RATE CLOCK

002aaa116

Fig 18. Transmit timing.

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Fig 19. Transmit ready timing in non-FIFO mode.

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START

BIT

PARITY STOP

BIT

DATA BITS (5-8)

TX

D0

D1

D2

D3

D4

D5

D6

D7

5 DATA BITS

6 DATA BITS

7 DATA BITS

ACTIVE

IOW

D0–D7

TXRDY

t

28d

BYTE #16

t

27d

FIFO FULL

002aaa346

Fig 20. Transmit ready timing in FIFO mode (DMA mode ‘1’).

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UART FRAME

DATA BITS

0

1

0

1

0

1

0

1

TX DATA

IRTXA–IRTXD

TX

BIT

TIME

1/2 BIT TIME

3/16 BIT TIME

002aaa212

Fig 21. Infrared transmit timing.

IRRXA–IRRXD

RX

BIT

TIME

0-1 16X CLOCK DELAY

0

1

0

1

0

1

0

1

RX DATA

DATA BITS

UART FRAME

002aaa213

Fig 22. Infrared receive timing.

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11. Package outline

PLCC68: plastic leaded chip carrier; 68 leads

SOT188-2

e

E

D

y

X

A

60

44

Z

E

43

61

b

p

b

1

w

M

68

1

H

E

pin 1 index

A

e

A

1

A

4

(A )

3

L

p

9

k

27

β

detail X

10

26

v

M

A

e

Z

D

B

H

v

M

B

D

0

5

10 mm

scale

DIMENSIONS (mm dimensions are derived from the original inch dimensions)

(1)

A

Z

E

4

1

(1)

D

UNIT

mm

A

b

D

E

e

H

k

L

p

v

w

y

β

b

3

1

D

E

D

E

p

max.

min.

max. max.

4.57

4.19

0.81 24.33 24.33

0.66 24.13 24.13

23.62 23.62 25.27 25.27 1.22 1.44

22.61 22.61 25.02 25.02 1.07 1.02

0.53

0.33

0.51 0.25

3.3

1.27

0.05

0.18 0.18

0.1

2.16 2.16

o

45

0.180

0.165

0.032 0.958 0.958

0.026 0.950 0.950

0.93 0.93 0.995 0.995 0.048 0.057

0.89 0.89 0.985 0.985 0.042 0.040

0.021

0.013

inches

0.02 0.01 0.13

0.007 0.007 0.004 0.085 0.085

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

01-11-14

SOT188-2

112E10

MS-018

EDR-7319

Fig 23. PLCC68 package outline (SOT188-2).

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LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm

SOT314-2

y

X

A

48

33

Z

49

32

E

e

H

A

E

2

E

A

(A )

3

A

1

w M

p

θ

b

L

p

pin 1 index

L

64

17

detail X

1

16

Z

v

M

A

D

e

w M

b

p

D

B

H

v

M

B

D

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

L

v

w

y

Z

E

θ

1

2

3

p

D

E

p

D

max.

7^o

0^o

0.20 1.45

0.05 1.35

0.27 0.18 10.1 10.1

0.17 0.12 9.9 9.9

12.15 12.15

11.85 11.85

0.75

0.45

1.45 1.45

1.05 1.05

1.6

mm

0.25

0.5

1

0.2 0.12 0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-01-19

03-02-25

SOT314-2

136E10

MS-026

Fig 24. LQFP64 package outline (SOT314-2).

9397 750 11617

Product data

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12. Soldering

12.1 Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology. A more in-depth account

of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit

Packages (document order number 9398 652 90011).

There is no soldering method that is ideal for all IC packages. Wave soldering can still

be used for certain surface mount ICs, but it is not suitable for ﬁne pitch SMDs. In

these situations reﬂow soldering is recommended. In these situations reﬂow

soldering is recommended.

12.2 Reﬂow soldering

Reﬂow soldering requires solder paste (a suspension of ﬁne solder particles, ﬂux and

binding agent) to be applied to the printed-circuit board by screen printing, stencilling

or pressure-syringe dispensing before package placement. Driven by legislation and

environmental forces the worldwide use of lead-free solder pastes is increasing.

Several methods exist for reﬂowing; for example, convection or convection/infrared

heating in a conveyor type oven. Throughput times (preheating, soldering and

cooling) vary between 100 and 200 seconds depending on heating method.

Typical reﬂow peak temperatures range from 215 to 270 °C depending on solder

paste material. The top-surface temperature of the packages should preferably be

kept:

• below 220 °C (SnPb process) or below 245 °C (Pb-free process)

– for all BGA and SSOP-T packages

– for packages with a thickness ≥ 2.5 mm

– for packages with a thickness < 2.5 mm and a volume ≥ 350 mm³so called

thick/large packages.

• below 235 °C (SnPb process) or below 260 °C (Pb-free process) for packages with

a thickness < 2.5 mm and a volume < 350 mm³so called small/thin packages.

Moisture sensitivity precautions, as indicated on packing, must be respected at all

times.

12.3 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices

(SMDs) or printed-circuit boards with a high component density, as solder bridging

and non-wetting can present major problems.

To overcome these problems the double-wave soldering method was speciﬁcally

developed.

If wave soldering is used the following conditions must be observed for optimal

results:

• Use a double-wave soldering method comprising a turbulent wave with high

upward pressure followed by a smooth laminar wave.

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• For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be

parallel to the transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the

transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

• For packages with leads on four sides, the footprint must be placed at a 45° angle

to the transport direction of the printed-circuit board. The footprint must

incorporate solder thieves downstream and at the side corners.

During placement and before soldering, the package must be ﬁxed with a droplet of

adhesive. The adhesive can be applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 °C or

265 °C, depending on solder material applied, SnPb or Pb-free respectively.

A mildly-activated ﬂux will eliminate the need for removal of corrosive residues in

most applications.

12.4 Manual soldering

Fix the component by ﬁrst soldering two diagonally-opposite end leads. Use a low

voltage (24 V or less) soldering iron applied to the ﬂat part of the lead. Contact time

must be limited to 10 seconds at up to 300 °C.

When using a dedicated tool, all other leads can be soldered in one operation within

2 to 5 seconds between 270 and 320 °C.

12.5 Package related soldering information

Table 29: Suitability of surface mount IC packages for wave and reﬂow soldering

methods

Package^[1]

Soldering method

Wave

Reﬂow^[2]

BGA, LBGA, LFBGA, SQFP, SSOP-T^[3],

TFBGA, VFBGA

not suitable

suitable

DHVQFN, HBCC, HBGA, HLQFP, HSQFP,

HSOP, HTQFP, HTSSOP, HVQFN, HVSON,

SMS

not suitable^[4]

suitable

PLCC^[5], SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended^[5][6]

not recommended^[7]

SSOP, TSSOP, VSO, VSSOP

[1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note

(AN01026); order a copy from your Philips Semiconductors sales ofﬁce.

[2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the

maximum temperature (with respect to time) and body size of the package, there is a risk that internal

or external package cracks may occur due to vaporization of the moisture in them (the so called

popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated

Circuit Packages; Section: Packing Methods.

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[3] These transparent plastic packages are extremely sensitive to reﬂow soldering conditions and must

on no account be processed through more than one soldering cycle or subjected to infrared reﬂow

soldering with peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reﬂow

oven. The package body peak temperature must be kept as low as possible.

[4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom

side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with

the heatsink on the top side, the solder might be deposited on the heatsink surface.

[5] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave

direction. The package footprint must incorporate solder thieves downstream and at the side corners.

[6] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it

is deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

[7] Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than

0.65 mm; it is deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

13. Revision history

Table 30: Revision history

Rev Date

CPCN

-

Description

04 20030619

Product data (9397 750 11617); ECN 853-2377 30029 of 16 June 2003.

Modiﬁcations:

• Figure 6 “Crystal oscillator connection.” on page 16: changed capacitors’ values and added

connection with resistor.

• Table 27 “DC electrical characteristics” on page 34: I_CCsleep: change all values to 1 mA nom.

• Table 28 “AC electrical characteristics”: add Table note 2, its reference to parameter ‘IOW

strobe width’, and re-number subsequent note.

03 20030415

02 20030313

01 20020910

-

Product data (9397 750 11373); ECN 853-2377 29798 of 11 April 2003.

Product data (9397 750 10985); ECN 853-2377 29458 of 03 February 2003.

Product data (9397 750 09393); ECN 853-2377 28891 of 10 September 2002.

9397 750 11617

Product data

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14. Data sheet status

Level Data sheet status^[1]

Product status^[2][3]

Deﬁnition

I

Objective data

Development

This data sheet contains data from the objective speciﬁcation for product development. Philips

Semiconductors reserves the right to change the speciﬁcation in any manner without notice.

II

Preliminary data

Qualiﬁcation

This data sheet contains data from the preliminary speciﬁcation. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in

order to improve the design and supply the best possible product.

III

Product data

Production

This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

[1]

[2]

Please consult the most recently issued data sheet before initiating or completing a design.

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3]

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

15. Deﬁnitions

16. Disclaimers

Short-form speciﬁcation — The data in a short-form speciﬁcation is

extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors

customers using or selling these products for use in such applications do so

at their own risk and agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

Limiting values deﬁnition — Limiting values given are in accordance with

the Absolute Maximum Rating System (IEC 60134). Stress above one or

more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any

other conditions above those given in the Characteristics sections of the

speciﬁcation is not implied. Exposure to limiting values for extended periods

may affect device reliability.

Right to make changes — Philips Semiconductors reserves the right to

make changes in the products - including circuits, standard cells, and/or

software - described or contained herein in order to improve design and/or

performance. When the product is in full production (status ‘Production’),

relevant changes will be communicated via a Customer Product/Process

Change Notiﬁcation (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no

licence or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are

free from patent, copyright, or mask work right infringement, unless otherwise

speciﬁed.

Application information — Applications that are described herein for any

of these products are for illustrative purposes only. Philips Semiconductors

make no representation or warranty that such applications will be suitable for

the speciﬁed use without further testing or modiﬁcation.

Contact information

For additional information, please visit http://www.semiconductors.philips.com.

For sales ofﬁce addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.

Fax: +31 40 27 24825

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9397 750 11617

Product data

Rev. 04 — 19 June 2003

SC16C654/654D

Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder

Philips Semiconductors

Contents

1

2

3

4

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

8

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 33

Static characteristics . . . . . . . . . . . . . . . . . . . 34

Dynamic characteristics. . . . . . . . . . . . . . . . . 35

Timing diagrams. . . . . . . . . . . . . . . . . . . . . . . 36

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 46

9

10

10.1

11

12

12.1

5

5.1

5.1.1

5.1.2

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

PLCC68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

LQFP64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Introduction to soldering surface mount

packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 48

Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 48

Manual soldering . . . . . . . . . . . . . . . . . . . . . . 49

Package related soldering information. . . . . . 49

12.2

12.3

12.4

12.5

6

Functional description . . . . . . . . . . . . . . . . . . 11

Interface options . . . . . . . . . . . . . . . . . . . . . . . 12

The 16 mode interface . . . . . . . . . . . . . . . . . . 12

The 68 mode interface . . . . . . . . . . . . . . . . . . 12

Internal registers. . . . . . . . . . . . . . . . . . . . . . . 13

FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . 13

Hardware ﬂow control. . . . . . . . . . . . . . . . . . . 14

Software ﬂow control . . . . . . . . . . . . . . . . . . . 14

Special feature software ﬂow control . . . . . . . 15

Xon any feature . . . . . . . . . . . . . . . . . . . . . . . 15

Hardware/software and time-out interrupts. . . 15

Programmable baud rate generator . . . . . . . . 16

DMA operation . . . . . . . . . . . . . . . . . . . . . . . . 18

Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Loop-back mode. . . . . . . . . . . . . . . . . . . . . . . 18

6.1

6.2

6.3

6.4

6.5

6.6

6.7

6.8

6.9

6.10

6.11

6.12

6.13

6.14

13

14

15

16

Revision history . . . . . . . . . . . . . . . . . . . . . . . 50

Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 51

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

7

7.1

Register descriptions . . . . . . . . . . . . . . . . . . . 20

Transmit (THR) and Receive (RHR)

Holding Registers . . . . . . . . . . . . . . . . . . . . . 21

Interrupt Enable Register (IER) . . . . . . . . . . . 21

IER versus Receive FIFO interrupt

7.2

7.2.1

mode operation . . . . . . . . . . . . . . . . . . . . . . . 22

IER versus Receive/Transmit FIFO polled

7.2.2

mode operation . . . . . . . . . . . . . . . . . . . . . . . 22

FIFO Control Register (FCR) . . . . . . . . . . . . . 23

DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Interrupt Status Register (ISR) . . . . . . . . . . . . 25

Line Control Register (LCR) . . . . . . . . . . . . . . 26

Modem Control Register (MCR) . . . . . . . . . . . 27

Line Status Register (LSR). . . . . . . . . . . . . . . 29

Modem Status Register (MSR). . . . . . . . . . . . 30

Scratchpad Register (SPR) . . . . . . . . . . . . . . 31

Enhanced Feature Register (EFR) . . . . . . . . . 31

SC16C654/654D external reset conditions. . . 33

7.3

7.3.1

7.3.2

7.4

7.5

7.6

7.7

7.8

7.9

7.10

7.11

Printed in the U.S.A

All rights are reserved. Reproduction in whole or in part is prohibited without the prior

written consent of the copyright owner.

The information presented in this document does not form part of any quotation or

contract, is believed to be accurate and reliable and may be changed without notice. No

liability will be accepted by the publisher for any consequence of its use. Publication

thereof does not convey nor imply any license under patent- or other industrial or

intellectual property rights.

Date of release: 19 June 2003

Document order number: 9397 750 11617


型号：	SC16C654IB64,157
厂家：	NXP
描述：	SC16C654IB64 通信时钟数据传输外围集成电路
文件：	总52页 (文件大小：238K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SC16C654IB64,157 [NXP]

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