SC18IS601_技术文档

SC18IS600/601

SPI to I²C-bus interface

Rev. 03 — 13 December 2006

Product data sheet

1. General description

The SC18IS600/601 is designed to serve as an interface between the standard SPI of a

host (microcontroller, microprocessor, chip set, etc.) and the serial I²C-bus. This allows

the host to communicate directly with other I²C-bus devices. The SC18IS600/601 can

operate as an I²C-bus master-transmitter or master-receiver. The SC18IS600/601

controls all the I²C-bus speciﬁc sequences, protocol, arbitration and timing.

The key distinction between the SC18IS600 and the SC18IS601 lies in the clock source:

internal (SC18IS600) versus external (SC18IS601).

2. Features

I SPI slave interface

I SPI Mode 3

I Master I²C-bus controller

I General Purpose Input/Output (GPIO) pins: 4 (SC18IS600); 3 (SC18IS601)

I Two quasi-bidirectional I/O pins

I 5 V tolerant I/O pins

I High-speed SPI:

N Up to 3 Mbit/s (SC18IS601)

N Up to 1.2 Mbit/s (SC18IS600)

I High-speed I²C-bus: 400 kbit/s

I 96-byte transmit buffer

I 96-byte receive buffer

I 2.4 V to 3.6 V operation

I Power-down mode with WAKEUP pin

I Oscillator: internal (SC18IS600); external (SC18IS601)

I Active LOW interrupt output

I Available in very small TSSOP16 package

3. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

SC18IS600IPW

SC18IS601IPW

TSSOP16 plastic thin shrink small outline package; 16 leads;

body width 4.4 mm

SOT403-1

SC18IS600/601

NXP Semiconductors

SPI to I²C-bus interface

4. Block diagram

SC18IS600

CONTROL

LOGIC

RESET

MISO

MOSI

SCLK

CS

SDA

2

I C-BUS

BUFFER

SPI

CONTROLLER

SCL

GPIO0

GPIO1

GPIO2

GPIO3

IO5

INT

INTERRUPT

CONTROL

LOGIC

GENERAL

PURPOSE

I/Os

IO4/WAKEUP

OSCILLATOR

ON-CHIP

RC

OSCILLATOR

002aab712

Fig 1. Block diagram of SC18IS600

SC18IS600_601_3

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SC18IS600/601

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SPI to I²C-bus interface

SC18IS601

CONTROL

LOGIC

RESET

MISO

MOSI

SCLK

CS

SDA

2

I C-BUS

BUFFER

SPI

CONTROLLER

SCL

GPIO0

GPIO1

GPIO2

INT

INTERRUPT

CONTROL

LOGIC

GENERAL

PURPOSE

I/Os

IO5

IO4/WAKEUP

external clock input

(CLKIN)

OSCILLATOR

002aab784

Fig 2. Block diagram of SC18IS601

SC18IS600_601_3

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SPI to I²C-bus interface

5. Pinning information

5.1 Pinning

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

GPIO0

CS

IO5

GPIO0

CS

IO5

WAKEUP/IO4

INT

WAKEUP/IO4

INT

RESET

V

GPIO3

V

CLKIN

SS

SC18IS600IPW

SC18IS601IPW

MISO

MOSI

SDA

V

DD

MISO

MOSI

SDA

V

DD

SCLK

GPIO2

GPIO1

GPIO2

GPIO1

SCL

002aab713

002aab714

Fig 3. SC18IS600 pin conﬁguration for TSSOP16

Fig 4. SC18IS601 pin conﬁguration for TSSOP16

5.2 Pin description

Table 2.

Symbol

Pin description

Type Description

SC18IS600 SC18IS601

GPIO0

CS

1

2

3

1

2

3

I/O

programmable I/O pin

I

Chip select. When CS is LOW, the SC18IS600/601 is selected.

RESET

Master Reset. When active (LOW), RESET sets internal registers to

the default values, and resets the I²C-bus and SPI hardware. See

Table 3.

V_SS

4

I

ground supply voltage

SPI slave data output

SPI slave data input

I²C-bus serial data input/output

I²C-bus serial clock output

programmable I/O pin

SPI clock input

MISO

MOSI

SDA

5

O

I

6

7

I/O

O

I/O

I

SCL

8

GPIO1

GPIO2

SCLK

V_DD

9

10

11

12

13

-

10

11

12

-

I

2.4 V to 3.6 V supply voltage

programmable I/O pin

external clock input

GPIO3

CLKIN

INT

I/O

I

13

14

O

Interrupt. When active (LOW), INT informs the CPU that the

SC18IS600/601 has an interrupt to be serviced.

INT is reset (deactivated) either when the I2CStat register is read or as

a result of a master reset (RESET). This pin is an open-drain pin.

WAKEUP/IO4

IO5

15

16

15

16

I/O

Wake up the SC18IS600/601 from the Power-down mode. Pulled LOW

by the host to wake-up from low power state. This pin can also be used

as a quasi-bidirectional I/O when not in a power-down state.

quasi-bidirectional I/O pin

SC18IS600_601_3

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SC18IS600/601

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SPI to I²C-bus interface

6. Functional description

The SC18IS600/601 acts as a bridge between a SPI interface and an I²C-bus. It allows a

SPI master device to communicate with I²C-bus slave devices. The SPI interface supports

Mode 3 of the SPI speciﬁcation and can operate up to 3 Mbit/s (SC18IS601).

6.1 Internal registers

The SC18IS600/601 provides internal registers for monitoring and control. These

registers are shown in Table 3. Register functions are more fully described in the following

paragraphs.

Table 3.

Internal registers summary

Register Register Bit 7

address

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

R/W Default

value

0x00

0x01

0x02

0x03

0x04

0x05

IOConﬁg IO3.1^[1]IO3.0^[1]IO2.1

IO2.0

IO1.1

IO1.0

IO0.1

GPIO1

CR1

IO0.0

GPIO0

CR0

TE

R/W 0x00

R/W 0x3F

R/W 0x19

R/W 0xFE

IOState

0

GPIO5 GPIO4 GPIO3^[2]GPIO2

I2CClock CR7

CR6

TO5

1

CR5

TO4

1

CR4

TO3

1

CR3

TO2

CR2

TO1

I2CTO

I2CStat

I2CAdr

TO6

1

TO0

I2CSTAT3 I2CSTAT2 I2CSTAT1 I2CSTAT0 R

0xF0

ADR7

ADR6

ADR5 ADR4 ADR3

ADR2 ADR1 R/W 0x00

X

[1] For SC18IS601, these bits are ‘Don’t care’.

[2] For SC18IS601 GPIO3 is not used.

6.2 Register descriptions

6.2.1 Programmable IO port conﬁguration register (IOConﬁg)

Pins GPIO0 to GPIO3 may be conﬁgured by software to one of four types. These are:

quasi-bidirectional, push-pull, open-drain, and input-only. Two conﬁguration bits per pin,

located in the IOConﬁg register, select the IO type for each pin. Each pin has

Schmitt-triggered input that also has a glitch suppression circuit. IO4 and IO5 are

quasi-bidirectional pins and are not user-conﬁgurable. For SC18IS601, GPIO3 is

non-existent.

Table 4 shows the conﬁgurations for the programmable I/O pins. IOx.1 and IOx.0

correspond to GPIOx.

Table 4.

Pin conﬁgurations

IOx.1

IOx.0

Pin conﬁguration

0

1

0

1

0

1

quasi-bidirectional output conﬁguration

input-only conﬁguration

push-pull output conﬁguration

open-drain output conﬁguration

SC18IS600_601_3

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SPI to I²C-bus interface

6.2.1.1 Quasi-bidirectional output conﬁguration

Quasi-bidirectional outputs can be used both as an input and output without the need to

reconﬁgure the pin. This is possible because when the pin outputs a logic HIGH, it is

weakly driven, allowing an external device to pull the pin LOW. When the pin is driven

LOW, it is driven strongly and able to sink a large current. There are three pull-up

transistors in the quasi-bidirectional output that serve different purposes.

One of these pull-ups, called the ‘very weak’ pull-up, is turned on whenever the pin latch

for the pin contains a logic 1. This very weak pull-up sources a very small current that will

pull the pin HIGH if it is left ﬂoating.

A second pull-up, called the ‘weak’ pull-up, is turned on when the pin latch for the pin

contains a logic 1 and the pin itself is also at a logic 1 level. This pull-up provides the

primary source current for a quasi-bidirectional pin that is outputting a 1. If this pin is

pulled LOW by an external device, the weak pull-up turns off, and only the very weak

pull-up remains on. In order to pull the pin LOW under these conditions, the external

device has to sink enough current to overpower the weak pull-up and pull the pin below its

input threshold voltage.

The third pull-up is referred to as the ‘strong’ pull-up. This pull-up is used to speed up

LOW-to-HIGH transitions on a quasi-bidirectional pin when the pin latch changes from a

logic 0 to a logic 1. When this occurs, the strong pull-up turns on for two system clock

cycles quickly pulling the pin HIGH.

The quasi-bidirectional pin conﬁguration is shown in Figure 5.

Although the SC18IS600/601 is a 3 V device, most of the pins are 5 V tolerant. If 5 V is

applied to a pin conﬁgured in quasi-bidirectional mode, there will be a current ﬂowing from

the pin to V_DDcausing extra power consumption. Therefore, applying 5 V to pins

conﬁgured in quasi-bidirectional mode is discouraged.

A quasi-bidirectional pin has a Schmitt-triggered input that also has a glitch suppression

circuit.

V

DD

2 SYSTEM

CLOCK

CYCLES

P

very

weak

strong

weak

GPIOn,

IOn pin

pin latch data

V

SS

input data

glitch rejection

002aab882

Fig 5. Quasi-bidirectional output conﬁguration

SC18IS600_601_3

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SPI to I²C-bus interface

6.2.1.2 Open-drain output conﬁguration

The open-drain output conﬁguration turns off all pull-ups and only drives the pull-down

transistor of the pin when the pin latch contains a logic 0. To be used as a logic output, a

pin conﬁgured in this manner must have an external pull-up, typically a resistor tied to

V_DD. The pull-down for this mode is the same as for the quasi-bidirectional mode.

The open-drain pin conﬁguration is shown in Figure 6.

An open-drain pin has a Schmitt-triggered input that also has a glitch suppression circuit.

GPIO pin

pin latch data

V

SS

input data

glitch rejection

002aab883

Fig 6. Open-drain output conﬁguration

6.2.1.3 Input-only conﬁguration

The input-only pin conﬁguration is shown in Figure 7. It is a Schmitt-triggered input that

also has a glitch suppression circuit.

input data

GPIO pin

002aab884

glitch rejection

Fig 7. Input-only conﬁguration

6.2.1.4 Push-pull output conﬁguration

The push-pull output conﬁguration has the same pull-down structure as both the

open-drain and the quasi-bidirectional output modes, but provides a continuous strong

pull-up when the pin latch contains a logic 1. The push-pull mode may be used when

more source current is needed from a pin output.

The push-pull pin conﬁguration is shown in Figure 8.

A push-pull pin has a Schmitt-triggered input that also has a glitch suppression circuit.

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SPI to I²C-bus interface

V

DD

P

N

strong

GPIO pin

pin latch data

V

SS

input data

glitch rejection

002aab885

Fig 8. Push-pull output conﬁguration

6.2.2 I/O pins state register (IOState)

When read, this register returns the actual state of all programmable and

quasi-bidirectional I/O pins. When written, each register bit will be transferred to the

corresponding I/O pin programmed as output.

Table 5.

IOState - I/O pins state register (address 0x01) bit description

Bit

7:6

5

Symbol

Description

-

reserved

IO5

Set the logic level on the output pins.

Write to this register:

4

IO4

logic 0 = set output pin to zero

logic 1 = set output pin to one

A read from this register returns states of all pins.

3

GPIO3 (SC18IS600 only)

2

GPIO2

GPIO1

GPIO0

1

0

6.2.3 I²C-bus address register (I2CAdr)

The contents of the register represents the device’s own I²C-bus address. The most

signiﬁcant bit corresponds to the ﬁrst bit received from the I²C-bus after a START

condition. The least signiﬁcant bit is not used, but should be programmed with a ‘0’.

I2CAdr is not needed for device operation, but should be conﬁgured so that its address

does not conﬂict with an I²C-bus device address used by the bus master.

6.2.4 I²C-bus clock rates register (I2CClk)

This register determines the I²C-bus clock frequency. Various clock rates are shown in

Table 6 for the SC18IS600. The frequency can be determined using the following formula:

7.3728 × 10⁶

4 × I2CClk

I²C-bus clock frequency =

(Hz)

------------------------------

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SPI to I²C-bus interface

The I²C-bus clock frequency for the SC18IS601 can be determined using the following

formula:

CLKIN

4 × I2CClk

I²C-bus clock frequency =

(Hz)

----------------------------

Table 6.

I²C-bus clock frequency example at 7.3728 MHz

I2CClk (decimal)

I²C-bus clock frequency

5 (minimum)

369 kHz

7

263 kHz

9

204 kHz

19

97 kHz

255 (maximum)

7.2 kHz

6.2.5 I²C-bus time-out register (I2CTO)

The time-out register is used to determine the maximum time that the I²C-bus master is

allowed to complete a transfer before setting an I²C-bus time-out interrupt.

Table 7.

I2CTO - I²C-bus time-out register (address 0x04) bit description

Bit

7:1

0

Symbol

TO[7:1]

TE

Description

Time-out value

Enable/disable time-out function

logic 0 = disable

logic 1 = enable

The least signiﬁcant bit of I2CTO (TE bit) is used as a time-out enable/disable. A logic 1

will enable the time-out function.

On the SC18IS600 the time-out oscillator operates at 57.6 kHz. For the SC18IS601 the

time-out oscillator frequency can be determined using the following formula:

CLKIN

128

Time-out oscillator frequency =

(Hz)

------------------

This oscillator is fed into a 16-bit down counter. The down counter’s lower nine bits are

loaded with ‘1’, while the upper seven bits are loaded with the contents of I2CTO.

57.6 kHz

OSCILLATOR

16-BIT DOWN COUNTER

[I2CTO][111111111]

time-out

002aab715

Fig 9. Time-out value

The time-out value is an approximate value.

In the case of arbitration loss, the SC18IS600/601 will transmit a START condition when

the bus becomes free unless the time-out condition is reached. If the time-out condition is

reached, an interrupt will be generated on the INT pin. The ‘I²C-bus time-out’ status can

be read in I2CStat.

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SPI to I²C-bus interface

6.2.6 I²C-bus status register (I2CStat)

This register reports the results of I²C-bus transmit and receive transaction between

SC18IS600/601 and an I²C-bus slave device.

Table 8.

I²C-bus status

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 I²C-bus status description

Register

value

0xF0

1

0

1

Transmission successful. The SC18IS600/601

has successfully completed and I²C-bus read or

write transaction. An interrupt is generated on

INT. This is also the default status after reset. No

interrupt is generated after reset.

I²C-bus device address not acknowledged. No

I²C-bus slave device has acknowledged the slave

address that has been sent out in an I²C-bus read

or write transaction. An interrupt is generated on

INT.

0xF1

1

0xF2

0xF3

0xF8

1

0

1

0

1

0

1

0

I²C-bus device address not acknowledged. An

I²C-bus slave has not acknowledged the byte that

has just been transmitted by the SC18IS600/601.

An interrupt is generated on INT.

I²C-bus busy. The SC18IS600/601 is busy

performing an I²C-bus transaction, no new

transaction should be initiated by the host. No

interrupt is generated.

I²C-bus time-out (see Section 6.2.5 “I²C-bus

time-out register (I2CTO)”). The SC18IS600/601

has started an I²C-bus transaction that has taken

longer than the time programmed in I2CTO

register. This could happen after a period of

unsuccessful arbitration or when an I²C-bus slave

is (continuously) pulling the SCL clock LOW. An

interrupt is generated on INT.)

0xF9

1

0

1

I²C-bus invalid data count. The number of bytes

speciﬁed in a read or write command to the

SC18IS600/601. An interrupt is generated on INT.

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SPI to I²C-bus interface

6.3 External clock input (SC18IS601)

In this device, the processor clock is derived from an external source driving the CLKIN

pin. The clock rate may be from 0 Hz up to 18 MHz.

6.4 I²C-bus serial interface

I²C-bus uses two wires (SDA and SCL) to transfer information between devices connected

to the bus, and it has the following features:

• Bidirectional data transfer between masters and slaves

• Multi-master bus (no central master)

• Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus

• Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer

• The I²C-bus may be used for test and diagnostic purposes.

A typical I²C-bus conﬁguration is shown in Figure 10. The SC18IS600/601 device

provides a byte-oriented I²C-bus interface that supports data transfers up to 400 kHz.

(Refer to Philips Semiconductors The I²C-bus speciﬁcation, document order number

9398 393 40011.)

V

DD

R

PU

R

PU

SDA

SCL

2

I C-bus

2

I C-BUS

DEVICE

I C-BUS

SC18IS600/601

DEVICE

002aab716

Fig 10. I²C-bus conﬁguration

6.5 Serial Peripheral Interface (SPI)

The host communicates with the SC18IS600/601 via the SPI interface. The

SC18IS600/601 operates in Slave mode up to 3 Mbit/s.

The SPI interface has four pins: SCLK, MOSI, MISO, and CS.

• SCLK, MOSI and MISO are typically tied together between two or more SPI devices.

Data ﬂows from the master to the SC18IS600/601 on the MOSI (Master Out Slave In)

pin and ﬂows from SC18IS600/601 to the master on the MISO (Master In Slave Out)

pin. The SCLK signal is an input to the SC18IS600/601.

• CS is the slave select pin. In a typical conﬁguration, an SPI master selects one SPI

device as the current slave. An SPI slave device uses its CS pin to determine whether

it is selected. The CS pin may be tied LOW if it is the only device on the bus.

Typical connections are shown in Figure 11.

SC18IS600_601_3

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SPI to I²C-bus interface

master

slave

SC18IS600/601

MISO

MOSI

SPICLK

PORT

SCLK

CS

slave

OTHER SPI

DEVICE

SCLK

CS

PORT

002aab717

Fig 11. SPI single master multiple slaves conﬁguration

6.6 SPI message format

6.6.1 Write N bytes to I²C-bus slave device

SPI host sends

0x00

NUMBER

SLAVE ADDRESS

+ W

DATA

BYTE 1

DATA

BYTE N

COMMAND OF BYTES

CS

SCLK

MOSI

command 0x00

number of bytes D[7:0] slave address A[7:1]

0

data byte 1

data byte N

002aab718

Fig 12. Write N bytes to I²C-bus slave device

The SPI host issues the write command by sending a 0x00 command followed by the total

number of bytes (maximum 96 bytes excluding the address) to send and an I²C-bus slave

device address followed by I²C-bus data bytes, beginning with the ﬁrst byte (data byte 1)

and ending with the last byte (data byte N). Once the SPI host issues this command, the

SC18IS600/601 will access the I²C-bus slave device and start sending the I²C-bus data

bytes.

When the I²C-bus write transaction has successfully ﬁnished, and interrupt is generated

on the INT pin, and the ‘transaction completed’ status can be read in I2CStat.

Note that the third byte sent by the host is the device I²C-bus slave address. The

SC18IS600/601 will ignore the least signiﬁcant bit so a write will always be performed

even if the least signiﬁcant bit is a ‘1’.

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SPI to I²C-bus interface

6.6.2 Read N bytes from I²C-bus slave device

SPI host sends

0x01

NUMBER

SLAVE ADDRESS

+ R

COMMAND OF BYTES

CS

SCLK

MOSI

command 0x01

number of bytes D[7:0] slave address A[7:1]

1

002aab719

Fig 13. Read N bytes from I²C-bus slave device

Once the host issues this command, the SC18IS600/601 will start an I²C-bus read

transaction on the I²C-bus to the speciﬁed slave address. Once the data is received, the

SC18IS600/601 will place this data in the receiver buffer, and will generate an interrupt on

the INT pin. The ‘transaction completed’ status can be read in the I2CStat. Note that the

data is not returned until a read buffer command is performed (see Section 6.6.4 “Read

buffer”).

Note that the third byte sent by the host is the device slave address. The SC18IS600/601

will ignore the least signiﬁcant bit so a read will always be performed even if the least

signiﬁcant bit is a ‘0’. The maximum number of bytes to be read is 96.

6.6.3 I²C-bus read after write

SPI host sends

NUMBER OF NUMBER OF

SLAVE

ADDRESS

+ W

DATA

WRITE

BYTE 0

DATA

WRITE

BYTE N

SLAVE

ADDRESS

+ R

0x02

COMMAND

WRITE

BYTES

READ

BYTES

002aab720

Fig 14. I²C-bus read after write

Once the host issues this command, the SC18IS600/601 will start a write transaction on

the I²C-bus to the speciﬁed slave address. Once the data is written, the SC18IS600/601

will read data from the speciﬁed slave, place the data in the Receiver Buffer and generate

an interrupt on the INT pin. The ‘transaction completed’ status can be read in I2CStat.

Note that the data is not returned until a ‘read buffer’ command is performed.

6.6.4 Read buffer

SPI host sends

0x06

COMMAND

DATA

BYTE 1

DATA

BYTE N

002aab868

Fig 15. Read buffer

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SPI to I²C-bus interface

When the host issues a Read Buffer command, the SC18IS600/601 will return the data in

the read buffer on the MISO pin. Note that the Read Buffer will be overwritten if an

additional ‘Read N bytes’ or a ‘Read after write’ command is executed before the Read

Buffer command.

6.6.5 I²C-bus write after write

SPI host sends

0x03

COMMAND

NUMBER OF NUMBER OF

BYTES 1 BYTES 2

SLAVE 1

ADDRESS + W

DATA

BYTE 1

DATA

BYTE N

SLAVE 2

ADDRESS + W

DATA

BYTE 1

DATA

BYTE N

002aab721

Fig 16. Write after write

When the host issues this command, the SC18IS600/601 will ﬁrst write N data bytes to

the I²C-bus slave 1 device followed by a write of M data bytes to the I²C-bus slave 2

device.

6.6.6 SPI conﬁguration

SPI host sends

0x18

SPI

COMMAND CONFIGURATION

CS

SCLK

MOSI

character 0x18

SPI configuration data

002aab722

Fig 17. SPI conﬁguration

Table 9. SPI conﬁguration

SPI conﬁguration

Data order

0x42

0x81

LSB ﬁrst

MSB ﬁrst (default)

The SPI conﬁguration command can be used to change the order in which the bits of SPI

data byte are sent on the SPI bus. In the LSB ﬁrst conﬁguration (SPI conﬁguration data is

0x42), bit 0 is the ﬁrst bit sent of any SPI byte. In MSB ﬁrst (SPI conﬁguration data is

0x81), bit 7 is the ﬁrst bit sent. Table 9 shows the two possible conﬁgurations that can be

programmed.

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SPI to I²C-bus interface

6.6.7 Write to SC18IS600/601 internal registers

SPI host sends

0x20

COMMAND

REGISTER

X

DATA

BYTE

CS

SCLK

MOSI

character 0x20

register X

data byte

002aab723

Fig 18. Write to SC18IS600/601 internal registers

A Write Register function is initiated by sending a 0x20 command followed by an internal

register address to be written (see Section 6.1). The register data byte follows the register

address. Only one register can be accessed in a single transaction. There is no

auto-incrementing of the register address.

6.6.8 Read from SC18IS600/601 internal register

SPI host sends

0x21

COMMAND

REGISTER

X

REGISTER

DATA

CS

SCLK

MOSI

MISO

character 0x21

register X

dummy byte

data byte

002aab724

Fig 19. Read from SC18IS600/601 internal register

A Read Register function is initiated by sending a 0x21 command followed by an internal

register address to be read (see Section 6.1) and a dummy byte. The data byte of the

read register is returned by the SC18IS600 on the MISO pin. Only one register can be

accessed in a single transaction. There is no auto-incrementing of the register address.

Note that write and read from internal registers are processed immediately as soon as the

SC18IS600/601 determines the intended register.

SC18IS600_601_3

Product data sheet

Rev. 03 — 13 December 2006

15 of 28

SC18IS600/601

NXP Semiconductors

SPI to I²C-bus interface

6.6.9 Power-down mode

SPI host sends

0x30

COMMAND

0x5A

0xA5

CS

SCLK

MOSI

character 0x30

character 0x5A

character 0xA5

002aab725

Fig 20. Power-down mode

The SC18IS600/601 can be placed in a low-power mode where the internal oscillator is

stopped and it will no longer respond to SPI messages. Enter the Power-down mode by

sending the power-down command (0x30) followed by the two deﬁned bytes, which are

0x5A followed by 0xA5. If the exact message is not received, the device will not enter the

power-down state.

Before entering the power-down state, WAKEUP/IO4 should be placed in a HIGH state.

To exit the power-down state, the WAKEUP/IO4 should be brought LOW. After leaving the

power-down state, the WAKEUP/IO4 can once again be used as a general-purpose IO

pin.

7. Limiting values

Table 10. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).^[1][2]

Symbol

T_amb(bias)

T_stg

Parameter

Conditions

Min

Max

+125

+150

+5.5

8

Unit

°C

bias ambient temperature

operating

−55

storage temperature

−65

°C

V_n

voltage on any other pin

referenced to V_SS

−0.5

V

I_OH(I/O)

I_OL(I/O)

I_{I/O(tot)(max)}

P_tot/pack

HIGH-state output current per input/output pin

LOW-state output current per input/output pin

maximum total I/O current

-

mA

W

20

120

1.5

[3]

total power dissipation per package

[1] This product includes circuitry speciﬁcally designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.

[2] Parameters are valid over the operating temperature range unless otherwise speciﬁed. All voltages are with respect to V_SSunless

otherwise noted.

[3] Based on package heat transfer, not device power consumption.

SC18IS600_601_3

Product data sheet

Rev. 03 — 13 December 2006

16 of 28

SC18IS600/601

NXP Semiconductors

SPI to I²C-bus interface

8. Static characteristics

Table 11. Static characteristics

V_DD= 2.4 V to 3.6 V; T_amb= −40 °C to +85 °C (industrial); unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ^[1]

Max

13

16

4.8

6

Unit

mA

µA

V

I_DD(oper)

operating supply current

V_DD= 3.6 V; f = 12 MHz

V_DD= 3.6 V; f = 18 MHz

V_DD= 3.6 V; f = 12 MHz

V_DD= 3.6 V; f = 18 MHz

V_DD= 3.6 V; industrial

V_DD= 3.6 V; extended

Schmitt trigger input

-

7

11

3.6

4

I_DD(idle)

Idle mode supply current

I_DD(tpd)

total Power-down mode supply

current

< 0.1

-

5

50

-

V_th(HL)

V_th(LH)

V_hys

HIGH-LOW threshold voltage

LOW-HIGH threshold voltage

hysteresis voltage

0.22V_DD0.4V_DD

-

0.6V_DD

0.2V_DD

0.6

0.7V_DD

-

V

-

V

V_OL

LOW-level output voltage

all pins; I_OL= 20 mA

all pins; I_OL= 10 mA

all pins; I_OL= 3.2 mA

-

1.0

0.5

0.3

-

V

-

0.3

V

-

0.2

V

V_OH

HIGH-level output voltage

all pins; I_OH= −8 mA;

V_DD− 1

-

V

push-pull mode

all pins; I_OH= −3.2 mA;

push-pull mode

V

_DD− 0.7 V_DD− 0.4 -

_DD− 0.3 V_DD− 0.2 -

V

all pins; I_OH= −20 µA;

V

quasi-bidirectional mode

[2]

[3]

C_ig

I_IL

input capacitance at gate

LOW-level input current

input leakage current

-

15

pF

µA

logical 0; V_I= 0.4 V

-

−80

[4]

I_LI

all ports; V_I= V_ILor V_IH

-

±10

[5][6]

I_THL

HIGH-LOW transition current

all ports; logical 1-to-0;

V_I= 2.0 V at V_DD= 3.6 V

−30

−450

R_{RESET_N(int)}internal pull-up resistance on pin

RESET

10

-

30

kΩ

[1] Typical ratings are not guaranteed. The values listed are at room temperature, 3 V.

[2] Pin capacitance is characterized but not tested.

[3] Measured with pins in quasi-bidirectional mode.

[4] Measured with pins in high-impedance mode.

[5] Pins in quasi-bidirectional mode with weak pull-up (applies to all pins with pull-ups).

[6] Pins source a transition current when used in quasi-bidirectional mode and externally driven from logic 1 to logic 0. This current is

highest when V_Iis approximately 2 V.

SC18IS600_601_3

Product data sheet

Rev. 03 — 13 December 2006

17 of 28

SC18IS600/601

NXP Semiconductors

SPI to I²C-bus interface

9. Dynamic characteristics

Table 12. Dynamic characteristics

V_DD= 2.4 V to 3.6 V; T_amb= −40 °C to +85 °C (industrial); unless otherwise speciﬁed.^[1]

Symbol Parameter

Conditions

Variable clock

f_osc= 12 MHz Unit

Min Max

7.189 7.557 MHz

Min

Max

f_osc(RC)

internal RC oscillator

nominal f = 7.3728 MHz; trimmed to

7.189

7.557

frequency (SC18IS600) ±1 % at T_amb= 25 °C

External clock input (SC18IS601); see Figure 22

f_osc

oscillator frequency

clock cycle time

clock HIGH time

clock LOW time

clock rise time

V_DD= 2.4 V to 3.6 V

0

83

22

-

12

-

MHz

ns

T_CLCL

t_CHCX

t_CLCX

t_CLCH

t_CHCL

-

T

_CLCL− t_CLCX

22

-

ns

T

_CLCL− t_CHCX

-

ns

8

ns

clock fall time

-

ns

Glitch ﬁlter

[2]

t_gr

glitch rejection time

RESET pin

-

50

15

-

50

15

-

ns

any pin except RESET

t_sa

signal acceptance time RESET pin

125

50

125

50

any pin except RESET

-

SPI slave interface

fosc

f_SPI

SPI operating frequency 2.0 MHz

0

⁄

6

0

500

4

2.0

MHz

ns

6

T_SPICYCSPI cycle time

t_SPILEADSPI enable lead time

2.0 MHz

⁄

-

fosc

4

-

µs

t_SPILAG

SPI enable lag time

-

4

µs

3

t_SPICLKHSPICLK HIGH time

t_SPICLKLSPICLK LOW time

⁄

-

190

100

0

ns

fosc

3

⁄

ns

fosc

t_SPIDSU

t_SPIDH

t_SPIA

SPI data setup time

SPI data hold time

SPI access time

SPI disable time

100

0

-

ns

-

ns

120

240

167

-

120 ns

240 ns

167 ns

t_SPIDIS

t_SPIDV

2.0 MHz

3.0 MHz

0

-

SPI enable to output

data valid time

0

-

0

-

t_SPIOH

t_SPIR

SPI output data hold

time

0

-

ns

SPI rise time

SPI outputs (SPICLK, MOSI, MISO)

-

100

-

100 ns

2000 ns

SPI inputs (SPICLK, MOSI, MISO,

SS)

2000

t_SPIF

SPI fall time

SPI outputs (SPICLK, MOSI, MISO)

-

100

-

100 ns

2000 ns

SPI inputs (SPICLK, MOSI, MISO,

SS)

2000

[1] Parameters are valid over operating temperature range unless otherwise speciﬁed. Parts are tested to 2 MHz, but are guaranteed to

operate down to 0 Hz.

[2] SCL and SDA do not have glitch suppression circuits.

SC18IS600_601_3

Product data sheet

Rev. 03 — 13 December 2006

18 of 28

SC18IS600/601

NXP Semiconductors

SPI to I²C-bus interface

Table 13. Dynamic characteristics

V_DD= 3.0 V to 3.6 V; T_amb= −40 °C to +85 °C (industrial); unless otherwise speciﬁed.^[1]

Symbol Parameter

Conditions

Variable clock

f_osc= 18 MHz

Unit

Min

Max

Min

Max

7.557 MHz

f_osc(RC)

internal RC oscillator

frequency (SC18IS600)

nominalf = 7.3728 MHz;

trimmed to ±1 % at

7.189

7.557

7.189

T_amb= 25 °C

External clock input (SC18IS601); see Figure 22

f_osc

oscillator frequency

clock cycle time

clock HIGH time

clock LOW time

clock rise time

0

55

22

-

18

-

MHz

ns

T_CLCL

t_CHCX

-

T

_CLCL− t_CLCX

22

-

ns

t_CLCX

T

_CLCL− t_CHCX

-

ns

t_CLCH

5

ns

t_CHCL

clock fall time

-

ns

Glitch ﬁlter

[2]

t_gr

glitch rejection time

RESET pin

-

50

15

-

50

15

-

ns

any pin except RESET

RESET pin

t_sa

signal acceptance time

125

50

125

50

any pin except RESET

-

SPI slave interface

fosc

f_SPI

SPI operating frequency

3.0 MHz

0

⁄

0

333

4

3

MHz

ns

µs

ns

6

T_SPICYC

t_SPILEAD

t_SPILAG

t_SPICLKH

t_SPICLKL

t_SPIDSU

t_SPIDH

t_SPIA

SPI cycle time

⁄

-

fosc

SPI enable lead time

SPI enable lag time

SPICLK HIGH time

SPICLK LOW time

SPI data setup time

SPI data hold time

SPI access time

4

-

4

-

3

⁄

-

167

100

0

-

fosc

3

⁄

fosc

100

0

-

80

160

80

160

t_SPIDIS

t_SPIDV

SPI disable time

3.0 MHz

0

-

SPI enable to output data

valid time

0

-

t_SPIOH

t_SPIR

SPI output data hold time

SPI rise time

0

-

0

-

ns

SPI outputs (SPICLK,

MOSI, MISO)

100

SPI inputs (SPICLK,

MOSI, MISO, SS)

-

2000

100

-

2000 ns

100 ns

2000 ns

t_SPIF

SPI fall time

SPI outputs (SPICLK,

MOSI, MISO)

SPI inputs (SPICLK,

MOSI, MISO, SS)

2000

[1] Parameters are valid over operating temperature range unless otherwise speciﬁed. Parts are tested to 2 MHz, but are guaranteed to

operate down to 0 Hz.

[2] SCL and SDA do not have glitch suppression circuits.

SC18IS600_601_3

Product data sheet

Rev. 03 — 13 December 2006

19 of 28

SC18IS600/601

NXP Semiconductors

SPI to I²C-bus interface

SS

t

SPIF

T

CLCL

t

SPILEAD

t

SPIR

t

SPILAG

t

SPIF

SPIR

t

SPICLKL

SPICLKH

SPICLK

(input)

t

SPIOH

t

SPIDV

t

SPIDIS

t

SPIA

MISO

(output)

slave LSB/MSB out

slave MSB/LSB out

not defined

t

SPIDH

SPIDSU

SPIDH

SPIDSU

MOSI

(input)

MSB/LSB in

LSB/MSB in

002aab797

Fig 21. SPI slave timing (Mode 3)

V

DD

− 0.5 V

0.2V

+ 0.9 V

DD

0.2V

− 0.1 V

DD

0.45 V

t

CHCX

t

CLCH

CHCL

CLCX

T

CLCL

002aab886

Fig 22. External clock timing

SC18IS600_601_3

Product data sheet

Rev. 03 — 13 December 2006

20 of 28

SC18IS600/601

NXP Semiconductors

SPI to I²C-bus interface

Table 14. Additional SPI AC characteristics

Symbol Parameter

Conditions

Min

Typ

Max Unit

t_SPICLKWSPICLK HIGH time

between two SPI bytes

8

-

µs

t_CSW

t_SPILAG1

t_d

CS HIGH time

between two SPI transactions

refer to Figure 24

refer to Figure 25

refer to Figure 26

SPI enable lag time 1 in a SPI to I²C-bus transaction

delay time

from last SCLK pulse to SDA LOW in a SPI to I²C-bus

transaction

t

SPICLKW

SCLK

t

SPILAG1

t

SPILEAD

CS

t

CSW

t

d

SDA

002aab927

Fig 23. SPI to I²C-bus timing diagram

002aab929

002aab930

8

5

t

SPILAG1

t

CSW

(µs)

4

6

4

2

0

3

2

1

0

1.843

3.687

7.373

12.00

18.00

1.843

3.687

7.373

12.00

18.00

CLKIN frequency (MHz)

Fig 24. t_CSWas a function of CLKIN frequency

Fig 25. t_SPILAG1as a function of CLKIN frequency

002aab931

160

t

d

(µs)

120

80

40

0

1.843

3.687

7.373

12.00

18.00

CLKIN frequency (MHz)

Fig 26. t_das a function of CLKIN frequency

SC18IS600_601_3

Product data sheet

Rev. 03 — 13 December 2006

21 of 28

SC18IS600/601

NXP Semiconductors

SPI to I²C-bus interface

10. Package outline

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm

SOT403-1

D

E

A

X

c

y

H

v

M

A

E

Z

9

16

Q

(A )

3

A

2

A

1

pin 1 index

θ

L

p

L

1

8

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

UNIT

A

b

c

D

E

e

H

L

Q

v

w

y

Z

θ

1

2

3

p

E

p

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

5.1

4.9

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.40

0.06

mm

1.1

0.65

0.25

1

0.2

0.13

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-18

SOT403-1

MO-153

Fig 27. Package outline SOT403-1 (TSSOP16)

SC18IS600_601_3

Product data sheet

Rev. 03 — 13 December 2006

22 of 28

SC18IS600/601

NXP Semiconductors

SPI to I²C-bus interface

11. Soldering

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reﬂow

soldering description”.

11.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

11.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

• Board speciﬁcations, including the board ﬁnish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus PbSn soldering

11.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath speciﬁcations, including temperature and impurities

SC18IS600_601_3

Product data sheet

Rev. 03 — 13 December 2006

23 of 28

SC18IS600/601

NXP Semiconductors

SPI to I²C-bus interface

11.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 28) than a PbSn process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 15 and 16

Table 15. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

235

≥ 350

220

< 2.5

≥ 2.5

220

Table 16. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 28.

SC18IS600_601_3

Product data sheet

Rev. 03 — 13 December 2006

24 of 28

SC18IS600/601

NXP Semiconductors

SPI to I²C-bus interface

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 28. Temperature proﬁles for large and small components

For further information on temperature proﬁles, refer to Application Note AN10365

“Surface mount reﬂow soldering description”.

12. Abbreviations

Table 17. Abbreviations

Acronym

ASCII

GPIO

UART

LSB

Description

American Standard Code for Information Interchange

General Purpose Input/Output

Universal Asynchronous Receiver/Transmitter

Least Signiﬁcant Bit

MSB

Most Signiﬁcant Bit

I²C-bus

Inter IC bus

SPI

Serial Peripheral Interface

SC18IS600_601_3

Product data sheet

Rev. 03 — 13 December 2006

25 of 28

SC18IS600/601

NXP Semiconductors

SPI to I²C-bus interface

13. Revision history

Table 18. Revision history

Document ID

Release date

20061213

Data sheet status

Change notice

Supersedes

SC18IS600_601_3

Modiﬁcations:

Product data sheet

-

SC18IS600_601_2

• The format of this data sheet has been redesigned to comply with the new identity guidelines

of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• Figure 1 “Block diagram of SC18IS600” and Figure 2 “Block diagram of SC18IS601” modiﬁed:

removed (input) directional arrow for signal SCL

• Table 2 “Pin description”, signal SCL: changed Type from “I/O” to “O”; changed Description

from “I²C-bus serial clock input/output” to “I²C-bus serial clock output”

• Table 8 “I²C-bus status”: added column “Register value”

• Section 6.6.8 “Read from SC18IS600/601 internal register”:

–

Figure 19 “Read from SC18IS600/601 internal register” modiﬁed: changed “register data”

to “dummy byte” on signal MOSI

–

1^stparagraph, 1^stsentence: appended “and a dummy byte” to end of sentence

• Table 14 “Additional SPI AC characteristics”: t_SPICLKWminimum value changed from “3 µs” to

“8 µs”

SC18IS600_601_2

SC18IS600_601_1

20060811

20060224

Product data sheet

-

SC18IS600_601_1

-

SC18IS600_601_3

Product data sheet

Rev. 03 — 13 December 2006

26 of 28

SC18IS600/601

NXP Semiconductors

SPI to I²C-bus interface

14. Legal information

14.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

result in personal injury, death or severe property or environmental damage.

14.2 Deﬁnitions

NXP Semiconductors accepts no liability for inclusion and/or use of NXP

Semiconductors products in such equipment or applications and therefore

such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

14.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

14.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of a NXP Semiconductors product can reasonably be expected to

I²C-bus — logo is a trademark of NXP B.V.

15. Contact information

For additional information, please visit: http://www.nxp.com

For sales ofﬁce addresses, send an email to: salesaddresses@nxp.com

SC18IS600_601_3

Product data sheet

Rev. 03 — 13 December 2006

27 of 28

SC18IS600/601

NXP Semiconductors

SPI to I²C-bus interface

16. Contents

1

2

3

4

General description . . . . . . . . . . . . . . . . . . . . . . 1

14

Legal information . . . . . . . . . . . . . . . . . . . . . . 27

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 27

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 27

14.1

14.2

14.3

14.4

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 1

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

15

16

Contact information . . . . . . . . . . . . . . . . . . . . 27

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6

Functional description . . . . . . . . . . . . . . . . . . . 5

Internal registers. . . . . . . . . . . . . . . . . . . . . . . . 5

Register descriptions . . . . . . . . . . . . . . . . . . . . 5

Programmable IO port conﬁguration register

6.1

6.2

6.2.1

(IOConﬁg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Quasi-bidirectional output conﬁguration . . . . . . 6

Open-drain output conﬁguration . . . . . . . . . . . . 7

Input-only conﬁguration . . . . . . . . . . . . . . . . . . 7

Push-pull output conﬁguration . . . . . . . . . . . . . 7

I/O pins state register (IOState) . . . . . . . . . . . . 8

I²C-bus address register (I2CAdr) . . . . . . . . . . 8

I²C-bus clock rates register (I2CClk) . . . . . . . . 8

I²C-bus time-out register (I2CTO). . . . . . . . . . . 9

I²C-bus status register (I2CStat). . . . . . . . . . . 10

External clock input (SC18IS601). . . . . . . . . . 11

I²C-bus serial interface . . . . . . . . . . . . . . . . . . 11

Serial Peripheral Interface (SPI) . . . . . . . . . . . 11

SPI message format . . . . . . . . . . . . . . . . . . . . 12

Write N bytes to I²C-bus slave device. . . . . . . 12

Read N bytes from I²C-bus slave device . . . . 13

I²C-bus read after write. . . . . . . . . . . . . . . . . . 13

Read buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

I²C-bus write after write . . . . . . . . . . . . . . . . . 14

SPI conﬁguration . . . . . . . . . . . . . . . . . . . . . . 14

Write to SC18IS600/601 internal registers . . . 15

Read from SC18IS600/601 internal register. . 15

Power-down mode . . . . . . . . . . . . . . . . . . . . . 16

6.2.1.1

6.2.1.2

6.2.1.3

6.2.1.4

6.2.2

6.2.3

6.2.4

6.2.5

6.2.6

6.3

6.4

6.5

6.6

6.6.1

6.6.2

6.6.3

6.6.4

6.6.5

6.6.6

6.6.7

6.6.8

6.6.9

7

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 16

Static characteristics. . . . . . . . . . . . . . . . . . . . 17

Dynamic characteristics . . . . . . . . . . . . . . . . . 18

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 22

8

9

10

11

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Introduction to soldering . . . . . . . . . . . . . . . . . 23

Wave and reﬂow soldering . . . . . . . . . . . . . . . 23

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 23

Reﬂow soldering . . . . . . . . . . . . . . . . . . . . . . . 24

11.1

11.2

11.3

11.4

12

13

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 25

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 26

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 13 December 2006

Document identifier: SC18IS600_601_3


型号：	SC18IS601
厂家：	NXP
描述：	SPI to IC-bus interface SPI与IC总线接口
文件：	总28页 (文件大小：154K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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