SC68C562C1A-T [NXP]
IC 2 CHANNEL(S), 10M bps, MULTI PROTOCOL CONTROLLER, PQCC52, PLASTIC, SOT238-3, LCC-52, Serial IO/Communication Controller;
| 型号： | SC68C562C1A-T |
| 厂家： | 
NXP |
| 描述： | IC 2 CHANNEL(S), 10M bps, MULTI PROTOCOL CONTROLLER, PQCC52, PLASTIC, SOT238-3, LCC-52, Serial IO/Communication Controller |
| 文件： | 总24页 (文件大小：133K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
SC68C562
CMOS dual universal serial
communications controller (CDUSCC)
Product data
2004 Mar 29
Supersedes data of 1998 Sep 04
Philips
Semiconductors
Philips Semiconductors
Product data
CMOS Dual universal serial communications controller
(CDUSCC)
SC68C562
DESCRIPTION
• Programmable bit rate for each receiver and transmitter selectable
The Philips Semiconductors SC68C562 Dual Universal Serial
Communications Controller (CDUSCC) is a single-chip CMOS-LSI
communications device that provides two independent,
from:
– 19 fixed rates: 50 to 64 kbaud
– One user-defined rate derived from programmable
counter/timer
multi-protocol, full-duplex receiver/transmitter channels in a single
package. It supports bit-oriented and character-oriented (byte count
and byte control) synchronous data link controls as well as
asynchronous protocols. The SC68C562 interfaces to the 68000
MPUs via asynchronous bus control signals and is capable of
program-polled, interrupt driven, block-move or DMA data transfers.
– External 1X or 16X clock
– Digital phase-locked loop
• Parity and FCS (frame check sequence LRC or CRC) generation
and checking
The SC68C562 is hardware (pin) and software (Register)
compatible with SCN68562 (NMOS version). It will automatically
configure to NMOS DUSCC register map on power-up or reset.
• Programmable data encoding/decoding: NRZ, NRZI, FM0, FM1,
Manchester
• Programmable channel mode: full- and half-duplex, auto-echo, or
The operating mode and data format of each channel can be
programmed independently. Each channel consists of a receiver, a
transmitter, a 16-bit multifunction counter/timer, a digital
phase-locked loop (DPLL), a parity/CRC generator and checker, and
associated control circuits. The two channels share a common bit
rate generator (BRG), operating directly from a crystal or an external
clock, which provides 16 common bit rates simultaneously. The
operating rate for the receiver and transmitter of each channel can
be independently selected from the BRG, the DPLL, the
local loopback
• Programmable data transfer mode: polled, interrupt, DMA, wait
• DMA interface
– Compatible with the Philips Semiconductors SCB68430 Direct
Memory Access Interface (DMAI) and other DMA controllers
– Single- or dual-address dual transfers
– Half- or full-duplex operation
– Automatic frame termination on counter/timer terminal count or
counter/timer, or from an external 1X or 16X clock.
DMA DONE
This makes the CDUSCC well suited for dual speed channel
applications. Data rates up to 10 Mb/s are supported.
• Transmit path clear status
• Interrupt capabilities
Each transmitter and each receiver is serviced by a 16-byte FIFO.
The receiver FIFO also stores 9 status bits for each character
received; the transmit FIFO is able to store transmitter commands
with each byte. This permits reading and writing of up to 16 bytes at
a time, thus minimizing the potential for transmitter underrun,
receiver overrun and reducing interrupt or DMA overhead.
– Daisy chain option
– Vector output (fixed or modified by status)
– Programmable internal priorities
– Interrupt at any FIFO fill level
– Maskable interrupt conditions
In addition, a flow control capability is provided to disable a remote
transmitter when the FIFO of the local receiving device is full. Two
modem control inputs (DCD and CTS) and three modem control
outputs (RTS and two general purpose) are provided. Because the
modem control inputs are general purpose in nature, they can be
optionally programmed for other functions. This document contains
the electrical specifications for the SC68C562. Refer to the CMOS
Dual Universal Serial Communications Controller (CDUSCC) User
Manual for a complete operational description of this product.
• FIFO’d status bits
• Watchdog timer
• Multi-function programmable 16-bit counter/timer
– Bit rate generator
– Event counter
– Count received or transmitted characters
– Delay generator
– Automatic bit length measurement
FEATURES
• Modem controls
– RTS, CTS, DCD, and up to four general I/O pins per channel
– CTS and DCD programmable auto-enables for Tx and Rx
– Programmable interrupt on change of CTS or DCD
• Full hardware and software upward compatibility with previous
NMOS device
General Features
• On-chip oscillator for crystal
• TTL compatible
• Single +5 V power supply
• Dual full-duplex synchronous/ asynchronous receiver and
transmitter
• Low power CMOS process
• Multiprotocol operation
Asynchronous Mode Features
–
BOP: HDLC/ADCCP, SDLC, SDLC loop, X.25 or X.75 link level,
etc.
• Character length: 5 to 8 bits
– COP: BISYNC, DDCMP
• Odd or even parity, no parity, or force parity
• Up to two stop bits programmable in 1/16-bit increments
• 1X or 16X Rx and Tx clock factors
– ASYNC: 5–8 bits plus optional parity
• Sixteen character receiver and transmitter FIFOs
• 0 to 10 MHz data rate
2
2004 Mar 29
Philips Semiconductors
Product data
CMOS Dual universal serial communications controller
(CDUSCC)
SC68C562
• Parity, overrun, and framing error detection
• False start bit detection
• Start bit search 1/2-bit time after framing error detection
• Break generation with handshake for counting break characters
• Detection of start and end of received break
• Character compare with optional interrupt on match
• Auto hunt after receipt of EOM sequence (with closing PAD check
after EOT or NAK)
• Control character sequence detection for both transparent and
normal text
Bit-Oriented Protocol Features
• Character length: 5 to 8 bits
• Detection and transmission of residual character: 0–7 bits
• Automatic switch to programmed character length for I field
• Zero insertion and deletion
• Optional opening PAD transmission
• Detection and generation of FLAG, ABORT, and IDLE bit patterns
• Transmits up to 10 Mb/s at 1X and receive up to 1 Mb/s at 16X
data rates
Character-Oriented Protocol Features
• Character length: 5 to 8 bits
• Odd or even parity, no parity, or force parity
• LRC or CRC generation and checking
• Optional opening PAD transmission
• One or two SYN characters
• Detection and generation of shared (single) FLAG between
frames
• Detection of overlapping (shared zero) FLAGs
• ABORT, ABORT-FLAGs, or FCS FLAGs line fill on underrun
• Idle in MARK or FLAGs
• External sync capability
• SYN detection and optional stripping
• SYN or MARK line fill on underrun
• Idle in MARK or SYNs
• Secondary address recognition including group and global
address
• Single- or dual-octet secondary address
• Extended address and control fields
• Short frame rejection for receiver
• Detection and notification of received end of message
• CRC generation and checking
• Parity, FCS, overrun, and underrun error detection
BISYNC Features
• EBCDIC or ASCII header, text and control messages
• SYN, DLE stripping
• EOM (end of message) detection and transmission
• Auto transparent mode switching
• SDLC loop mode capability
ORDERING INFORMATION
V
CC
= +5V ± 10 %; T
= 0 °C to +70 °C. Serial data rate = 10 Mb/s
amb
Package
Type number
Name
Description
Version
SC68C562C1A
PLCC52
plastic leaded chip carrier; 52 leads; pedestal
SOT238-3
1
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
0 to +70
UNIT
°C
°C
V
2
T
amb
Operating ambient temperature
Storage temperature
Voltage from V to GND
T
stg
–65 to +150
–0.5 to +7.0
3
V
V
CC
CC
3
Voltage from any pin to ground
–0.5 to V +0.5
V
S
CC
3
2004 Mar 29
Philips Semiconductors
Product data
CMOS Dual universal serial communications controller
(CDUSCC)
SC68C562
BLOCK DIAGRAM
CHANNEL MODE
AND TIMING A/B
D0-D7
BUS
BUFFER
DPLL CLK
MUX A/B
DPLL A/B
BRG
INTERFACE/
OPERATION
CONTROL
ADDRESS
DECODE
A7 CONTROL
LOGIC
COUNTER/
TIMER A/B
DTACKN
RWN
R/W
DECODE
C/T CLK
MUX A/B
MPU
INTERFACE
A1-A6
CSN
CTCRA/B
CTPRHA/B
CTPRLA/B
CTHA/B
DMA
CONTROL
RESETN
CCRA/B
PCRA/B
RSRA/B
RTxDRQAN/GPO1AN
RTxDRQBN/GPO1BN
TxDRQAN/GPO2AN
TxDRQBN/GPO2BN
RTxDAKAN/GPI1AN
RTxDAKBN/GPI1BN
TxDAKAN/GPI2AN
TxDAKBN/GPI2BN
DTCN
CTLA/B
TRSRA/B
ICTSRA/B
TRANSMIT A/B
GSR
TRANS CLK
MUX
DMA INTERFACE
CMR1A/B
CMR2A/B
OMRA/B
TPRA/B
TTRA/B
TRCR A/B
FTLR A/B
DONEN
TX SHIFT
REG
TxD A/B
TRMR A/B
CID
TRANSMIT
16 DEEP
FIFO
TRxCA/B
RTxCA/B
RTSBN/SYNOUTBN
RTSAN/SYNOUTAN
CTSA/BN
SPECIAL
FUNCTION
PINS
TELRA/B
CONTROL
CRC
GEN
DCDBN/SYNIBN
DCDAN/SYNIAN
SPEC CHAR
GEN LOGIC
RECEIVER A/B
RCVR CLK
MUX
INTERRRUPT
CONTROL
ICRA/B
RPRA/B
RTRA/B
S1RA/B
S2RA/B
IRQN
IERA/B
IVR
IACKN
RxD A/B
IVRM
IER1
RCVR
SHIFT REG
IER2
IER3
RECEIVER
16 DEEP
FIFO
RFLRA/B
DUSCC
LOGIC
CRC
ACCUM
BISYNC
COMPARE
LOGIC
X1/CLK
OSCILLATOR
X2/IDCN
SD00253
4
2004 Mar 29
Philips Semiconductors
Product data
CMOS Dual universal serial communications controller
(CDUSCC)
SC68C562
PIN CONFIGURATION
INDEX
CORNER
7
1
47
8
46
34
PLCC
20
21
33
TOP VIEW
Pin Function
Pin Function
1
2
3
4
5
IACKN
A3
A2
27 CSN
28 R/WN
29 DONEN
30 D3
31 D2
A1
RTxDAKBN/GPI1BN
IRQN
6
32 D1
7
NC
33 D0
8
RESETN
34 NC
9
RTSBN/SYNOUTBN
35 CTSAN/LCAN
36 TxDRQAN/GPO2AN/RTSAN
37 RTxDRQAN/GPO1AN
38 TxDAKAN/GPI2AN
39 TxDA
10 TRxCB
11 RTxCB
12 DCDBN/SYNIBN
13 NC
14 RxDB
40 RxDA
15 TxDB
41 NC
16 TxDAKBN/GPI2BN
17 RTxDRQBN/GPO1BN
18 TxDRQBN/GPO2BN/RTSBN
19 CTSBN/LCBN
20 D7
42 DCDAN/SYNIAN
43 RTxCA
44 TRxCA
45 RTSAN/SYNOUTAN
46 X2/IDCN
47 X1/CLK
21 D6
22 D5
23 D4
48 RTxDAKAN/GPI1AN
49 A6
24 DTACKN
25 DTCN
50 A5
51 A4
26 GND
52 V
DD
SD00739
PIN DESCRIPTION
MNEMONIC
A1–A6
PIN
TYPE
NAME AND FUNCTION
4-2,
51-49
I
Address Lines: Active-HIGH. Address inputs which specify which of the internal registers is
accessed for read/write operation.
D0–D7
33-30,
23-20
I/O
Bidirectional Data Bus: Active-HIGH, 3-State. Bit 0 is the LSB and bit 7 is the MSB. All data,
command and status transfers between the CPU and the CDUSCC take place over this bus. The
data bus is enabled when CSN and R/WN or during interrupt acknowledge cycles and single
address DMA acknowledge cycles.
R/WN
CSN
28
27
I
I
Read/Write: A HIGH input indicates a read cycle and a LOW indicates a write cycle when CEN is
active.
Chip Select: Active-LOW input. When active, data transfers between the CPU and the CDUSCC
are enabled on D0–D7 as controlled by R/WN and A1–A6 inputs. When CSN is HIGH, the data lines
are placed in the 3-State condition (except during interrupt acknowledge cycles and single address
DMA transfers).
IRQN
6
1
O
I
Interrupt Request: Active-LOW, open-drain. This output is asserted upon occurrence of any
enabled interrupting condition. The CPU can read the general status register to determine the
interrupting condition(s), or can respond with an interrupt acknowledge cycle to cause the CDUSCC
to output an interrupt vector on the data bus.
IACKN
X1/CLK
Interrupt Acknowledge: Active-LOW. When IACKN is asserted, the CDUSCC responds by either
forcing the bus into high-impedance, placing a vector number, call instruction or zero on the data
bus. The vector number can be modified or unmodified by the status. If no interrupt is pending,
IACKN is ignored and the data bus placed in high-impedance.
47
I
Crystal or External Clock: When using the crystal oscillator, the crystal is connected between pins
X1 and X2. If a crystal is not used, an external clock is supplied at this input. This clock is used to
drive the internal bit rate generator, as an optional input to the counter/timer or DPLL, and to provide
other required clocking signals. When a crystal is used, a capacitor must be connected from this pin
to ground.
5
2004 Mar 29
Philips Semiconductors
Product data
CMOS Dual universal serial communications controller
(CDUSCC)
SC68C562
MNEMONIC
X2/IDCN
PIN
TYPE
NAME AND FUNCTION
46
O
Crystal or Interrupt Daisy Chain: When a crystal is used as the timing source, the crystal is
connected between pins X1 and X2. This pin can be programmed to provide an interrupt daisy chain
active-LOW output which propagates the IACKN signal to lower priority devices, if no active interrupt
is pending. This pin should be left floating when an external clock is used on X1 and X2 is not used
as an interrupt daisy chain output. When a crystal is used, a capacitor must be connected from this
pin to ground.
RESETN
8
I
Master Reset: Active-LOW. A LOW on this pin resets the transmitters and receivers and resets the
registers shown in Table 1 of the CDUSCC Users’ Guide. Reset is asynchronous, i.e., no clock is
required.
RxDA, RxDB
TxDA, TxDB
40, 14
39, 15
I
Channel A (B) Receiver Serial Data Input: The least significant bit is received first. If external
receiver clock is specified for the channel, the input is sampled on the rising edge of the clock.
O
Channel A (B) Transmitter Serial Data Output: The least significant bit is transmitted first. This
output is in the marking (HIGH) condition when the transmitter is disabled or when the channel is
operating in local loopback mode. If external transmitter clock is specified for the channel, the data is
shifted on the falling edge of the clock.
RTxCA, RTxCB
TRxCA, TRxCB
43, 11
44, 10
I/O
I/O
Channel A (B) Receiver/Transmitter Clock: As an input, it can be programmed to supply the
receiver, transmitter, counter/timer, or DPLL clock. As an output, it can supply the counter/timer
output, the transmitter shift clock (1X), or the receiver sampling clock (1X).
Channel A (B) Transmitter/Receiver Clock: As an input, it can supply the receiver, transmitter,
counter/timer, or DPLL clock. As an output, it can supply the counter/timer output, the DPLL output,
the transmitter shift clock (1X), the receiver sampling clock (1X), the transmitter BRG clock (16X),
The receiver BRG clock (16X), or the internal system clock (X1 ÷ 2).
CTSA/BN,
LCA/BN
35, 19
42, 12
I/O
Channel A (B) Clear-to-Send Input or Loop Control Output: Active-LOW. The signal can be pro-
grammed to act as an enable for the transmitter when not in loop mode. The CDUSCC detects logic
level transitions on this input and can be programmed to generate an interrupt when a transition
occurs. When operating in the BOP loop mode, this pin becomes a loop control output which is as-
serted and negated by CDUSCC commands. This output provides the means of controlling external
loop interface hardware to go on-line and off-line without disturbing operation of the loop.
DCDA/BN,
SYNIA/BN
I
Channel A (B) Data Carrier Detected or External Sync Input: The function of this pin is
programmable. As a DCD active-LOW input, it acts as an enable for the receiver or can be used as
a general purpose input. For the DCD function, the CDUSCC detects logic level transitions on this
pin and can be programmed to generate an interrupt when a transition occurs. As an active-LOW
external sync input, it is used in COP mode to obtain character synchronization for the receiver
without receipt of a SYN character. This mode can be used in disc or tape controller applications or
for the optional byte timing lead in X.21.
RTxDRQA/BN,
GPO1A/BN
37, 17
O
Channel A (B) Receiver/Transmitter DMA Service Request or General Purpose Output:
Active-LOW. For half-duplex DMA operation, this output indicates to the DMA controller that one or
more characters are available in the receiver FIFO (when the receiver is enabled) or that the
transmit FIFO is not full (when the transmitter is enabled). For full-duplex DMA operation, this output
indicates to the DMA controller that data is available in the receiver FIFO. In non-DMA mode, this
pin is a general purpose output that can be asserted and negated under program control.
TxDRQA/BN,
GPO2A/BN,
RTSA/BN
36, 18
48, 5
O
I
Channel A (B) Transmitter DMA Service Request, General Purpose Output, or
Request-to-Send: Active-LOW. For full-duplex DMA operation, this output indicates to the DMA
controller that the transmit FIFO is not full and can accept more data. When not in full-duplex DMA
mode, this pin can be programmed as a general purpose or a Request-to-Send output, which can be
asserted and negated under program control.
RTxDAKA/BN,
GPI1A/BN
Channel A (B) Receiver/Transmitter DMA Acknowledge or General Purpose Input:
Active-LOW. For half-duplex single address operation, this input indicates to the CDUSCC that the
DMA controller has acquired the bus and that the requested bus cycle (read receiver FIFO when the
receiver is enabled or load transmitter FIFO when the transmitter is enabled) is beginning. For
full-duplex single address DMA operation, this input indicates to the CDUSCC that the DMA
controller has acquired the bus and that the requested read receiver FIFO bus cycle is beginning.
Because the state of this input can be read under program control, it can be used as a general
purpose input when not in single address DMA mode.
TxDAKA/BN,
GPI2A/BN
38, 16
I
Channel A (B) Transmitter DMA Acknowledge or General Purpose Input: Active-LOW. When
the channel is programmed for full-duplex single address DMA operation, this input is asserted to
indicate to the CDUSCC that the DMA controller has acquired the bus and that the requested load
transmitter FIFO bus cycle is beginning. Because the state of this input can be read under program
control, it can be used as a general purpose input when not in full-duplex single address DMA mode.
6
2004 Mar 29
Philips Semiconductors
Product data
CMOS Dual universal serial communications controller
(CDUSCC)
SC68C562
MNEMONIC
DONEN
PIN
TYPE
NAME AND FUNCTION
29
I/O
Done: Active-LOW, open-drain. DONEN can be used and is active in both DMA and non-DMA
modes. As an input, DONEN indicates the last DMA transfer cycle to the TxFIFO. As an output,
DONEN indicates either the last DMA transfer from the RxFIFO or that the transmitted character
count has reached terminal count.
RTSA/BN,
SYNOUTA/BN
45, 9
24
O
O
Channel A (B) Sync Detect or Request-to-Send: Active-LOW. If programmed as a sync output, it
is asserted one bit time after the specified sync character (COP or BISYNC modes) or a FLAG
(BOP modes) is detected by the receiver. As a Request-to-Send modem control signal, it functions
as described previously for the TxDRQN/RTSN pin.
DTACKN
Data Transfer Acknowledge: Active-LOW, 3-state. DTACKN is asserted on a write cycle to indicate
that the data on the bus has been latched, and on a read cycle or interrupt acknowledge cycle to
indicate valid data is on the bus. In a write bus cycle, input data is latched by the assertion (falling
edge) of DTACKN or by the negation (rising edge) of CSN, whichever occurs first. The signal is
negated when completion of the cycle is indicated by negation of CSN or IACKN input, and returns
to the inactive state (3-state) a short period after it is negated. In single address DMA mode, input
data is latched by the assertion (falling edge) of DTCN or by the negation (rising edge) of the DMA
acknowledge input, whichever occurs first. DTACK is negated when completion of the cycle is
indicated by the assertion of DTCN or negation of DMA acknowledge inputs (whichever occurs first),
and returns to the inactive state (3-state) a short period after it is negated. When inactive, DTACKN
requires an external pull-up resistor.
DTC
25
I
Device Transfer Complete: Active-LOW. DTCN is asserted by the DMA controller to indicate that
the requested data transfer is complete.
V
34, 52
I
I
+5V Power Input
CC
GND
26, 13,
41, 7
Signal and Power Ground Input
7
2004 Mar 29
Philips Semiconductors
Product data
CMOS Dual universal serial communications controller
(CDUSCC)
SC68C562
4, 5
ELECTRICAL CHARACTERISTICS
T
amb
= 0 °C to +70 °C, V = 5.0 V " 10 %
CC
LIMITS
Typ
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
Max
Min
V
V
V
V
Input LOW voltage:
All except X1/CLK
IL
–
–
–
–
0.8
0.8
V
V
X1/CLK
Input HIGH voltage:
IH
All except X1/CLK
X1/CLK
2.0
0.8 × V
–
–
–
V
CC
V
V
CC
14
Output LOW voltage:
OL
OH
All except IRQN
I
I
= 5.3 mA
= 8.8 mA
–
–
–
–
0.5
0.5
V
V
OL
7
IRQN
OL
14
Output HIGH voltage:
(Except open drain outputs)
I
= –400 µA
V
CC
– 0.5
–
–
V
OH
10
I
I
I
X1/CLK input LOW current
V
= 0, X2 = GND
–150
–
–
–
–
–
0.0
150
–15
+15
–0.5
µA
µA
ILX1
IN
10
X1/CLK input HIGH current
V
IN
= V , X2 = GND
–
–
IHX1
SCX2
CC
X2 short circuit current (X2 mode)
X1 open; V = 0 V
mA
mA
µA
IN
V
IN
= V
–
CC
I
IL
Input LOW current on RESETN, DTCN,
TxDAKA/BN, RTxDAKA/BN
V
IN
= 0 V
–15
I
I
I
I
Input leakage current
V
IN
= 0 V to V
CC
–1
–
–
–
–
+1
+1
–
µA
µA
µA
L
Output off current HIGH, 3-State data bus
Output off current LOW, 3-State data bus
V = V
IN CC
OZH
OZL
ODL
V
IN
= 0 V
–1
Open drain output LOW current in off state:
DONEN, DTACKN (3-state)
IRQN
V
V
= 0 V
= 0 V
–15
–1
–
–
–0.5
–
µA
µA
IN
IN
6
I
I
Open drain output HIGH current in off state:
DONEN, IRQN, DTACKN (3-state)
V
= V
CC
–1
–
+1
µA
ODH
IN
16
Power supply current
0 °C to 70 °C
–
25
80
mA
CC
(See Figure 17 for graphs)
9
C
C
C
Input capacitance
V
= GND = 0 V
= GND = 0 V
= GND = 0 V
–
–
–
–
–
–
10
15
20
pF
pF
pF
IN
CC
CC
CC
9
Output capacitance
V
V
OUT
9
Input/output capacitance
I/O
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not
implied.
2. Clock may be stopped (DC) for testing purposes or when the CDUSCC is in non-operational modes. Operation down to 0 rate clocks is
implied by a full static CMOS design, but is not verified in testing or characterization.
3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
4. Parameters are valid over specified temperature and voltage range.
5. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.2 V and 3.0 V with a
transition time of 20 ns maximum. For X1/CLK, this swing is between 0.2 V and 4.4 V. All time measurements are referenced at input
voltages of 0.2 V and 3.0 V and output voltages of 0.8 V and 2.0 V, as appropriate.
6. See Figure 18 for test conditions for outputs.
7. Tests for open drain outputs are intended to guarantee switching of the output transistor. To include noise margin this response is measured
from the switching signal midpoint to 0.2 V above the required output level.
8. Execution of the valid command (after it is latched) requires a minimum of three rising edges of X1 (see Figure 19).
9. These values were no explicitly tested; they are guaranteed by design and characterization data.
10.X1/CLK and X2 are not tested with a crystal installed.
11. X1/CLK frequency must be at least as fast as the faster of the receiver or transmitter data rate.
12.The X1 clock drives DTACKN, Baud Rate Generator, command register and the update of the FIFO fill level encoders. The Command
Register requires three X1 clocks between two commands; FIFO fill level encoding requires 2.5 to 3.5 X1 cycles.
13.The 68562 bus interface may be operated in two modes; a 68000 compatible mode with automatic DTACK generation and a short chip
select mode. DTACKN should not be used externally in the short chip select mode. The DTACKN signal is generated by the assertion of
the chip select, and data is latched by assertion of DTACKN or by de-assertion of the chip select, whichever comes first. In single address
DMA, the DTACK signal will be de-asserted by the assertion of the DTCN or from the de-assertion of the TxDAKN, whichever occurs first.
14.Also includes X2/IDCN pin in IDC mode.
15.In case of 3-state output, output levels V + 0.2 V are considered float or high-impedance.
OL
16.V = 0 V to V , Rx/Tx at 10 MHz and X1 at 10 MHz
O
CC
8
2004 Mar 29
Philips Semiconductors
Product data
CMOS Dual universal serial communications controller
(CDUSCC)
SC68C562
RESETN
t
RELREH
SD00205
Figure 1. Reset Timing
LIMITS
SYMBOL
PARAMETER
UNIT
Max
Min
t
RESETN LOW to RESETN HIGH
200
–
ns
RELREH
t
ADVCSL
A1–A6
t
t
RWHCSL
CSHRWL
R/WN
t
CSLADI
t
CSHCSL
t
CSLCSH
CSN
t
t
CSLDDV
CSHDDF
INVALID
t
D0–D7
INVALID
DATA VALID
t
CSHDDI
t
DDVDAL
CSLDDA
12
DTACKN
t
t
CSHDAH
t
t
CSLDAL
DALCSH
CSHDAZ
SD00254
Figure 2. Read Cycle Bus Timing
Times represent an X1 clock frequency of 14.745 MHz
LIMITS
SYMBOL
PARAMETER
UNIT
Min
5
Max
–
t
t
t
t
t
t
t
t
A0-A6 valid to CSN LOW
RWN HIGH to CSN LOW
CSN HIGH to RWN LOW
ns
ns
ns
ns
ns
ns
ns
ns
ADVCSL
RWHCSL
CSHRWL
CSHCSL
CSLDDV
CSHDDF
DDVDAL
DALCSH
5
–
10
30
–
–
8
CSN HIGH to CSN LOW
–
CSN LOW to read data valid
CSN HIGH to data bus float
Read data valid to DTACKN LOW
130
40
–
–
9
20
0
9
DTACKN LOW to CSN HIGH
–
1.5
fCL
1
fCL
13
9
40 )
130 )
t
CSN LOW to DTACKN LOW
ns
CSLDAL
t
t
t
t
t
t
CSN HIGH to DTACKN HIGH
–
–
60
90
–
ns
ns
ns
ns
ns
ns
CSHDAH
CSHDAZ
CSLADI
CSN HIGH to DTACKN HIGH impedance
CSN LOW to address invalid
CSN LOW to CSN HIGH
50
130
10
5
–
CSLCSH
CSLDDA
CSHDDI
9
CSN LOW to data bus driver active
–
CSN HIGH to data invalid
–
9
2004 Mar 29
Philips Semiconductors
Product data
CMOS Dual universal serial communications controller
(CDUSCC)
SC68C562
t
ADVCSL
A1–A6
t
CSHRWH
t
CSLADI
R/WN
t
CSLCSH
t
t
RWLCSL
CSHCSL
t
DALCSH
CSN
t
CSHWDI
D0–D7
12
t
t
DALWDI
CSLWDV
DTACKN
t
CSHDAH
t
CSLDAL
t
CSHDAZ
SD00255
Figure 3. Write Cycle Bus Timing
LIMITS
SYMBOL
PARAMETER
UNIT
Min
5
Max
–
t
t
t
t
t
t
t
A0-A6 valid to CSN LOW
CSN LOW to A0-A6 invalid
RWN LOW to CSN LOW
CSN HIGH to RWN HIGH
ns
ns
ns
ns
ns
ns
ns
ADVCSL
50
0
–
CSLADI
–
RWLCSL
CSHRWH
CSHCSL
DALCSH
DALWDI
0
–
8
CSN HIGH to CSN LOW
30
0
–
9
DTACKN LOW to CSN HIGH
–
9
DTACKN LOW to write data invalid
0
–
1.5
fCL
1
fCL
13
9
40 )
130 )
t
CSN LOW to DTACKN LOW
ns
CSLDAL
t
t
t
t
t
CSN HIGH to DTACKN HIGH
–
–
60
ns
ns
ns
ns
ns
CSHDAH
CSHDAZ
CSLCSH
CSLWDV
CSHWDI
CSN HIGH to DTACKN high-impedance
CSN LOW to CSN HIGH
90
–
130
35
5
CSN LOW to write data valid
CSN HIGH to write data invalid
–
–
10
2004 Mar 29
Philips Semiconductors
Product data
CMOS Dual universal serial communications controller
(CDUSCC)
SC68C562
IRQN
t
IALIAH
t
IACKN
IAHDDF
t
t
IALDDV
IAHDDI
INVALID
DATA VALID
INVALID
D0-D7
t
IAHDAH
t
t
DDVDAL
IALDDA
12
DTACHN
t
IALDAL
t
IAHDAZ
t
DALIAH
SD00256
Figure 4. Interrupt Cycle Timing
LIMITS
12
SYMBOL
PARAMETER
UNIT
Min
Max
–
t
t
t
t
t
t
t
IACKN LOW to IACKN HIGH
130
10
–
ns
ns
ns
ns
ns
ns
ns
IALIAH
9
IACKN LOW to data bus drivers active
IACKN LOW to read data valid
–
IALDDA
IALDDV
IAHDDF
DDVDAL
IAHDAH
IAHDAZ
130
60
–
IACKN HIGH to data bus floating
–
9
Read data valid to DTACKN LOW
20
–
IACKN HIGH to DTACKN HIGH
70
100
IACKN HIGH to DTACKN high-impedance
–
1.5
fCL
1
fCL
9
40 )
130 )
t
IACKN LOW to DTACKN LOW
ns
IALDAL
t
t
IACKN HIGH to data bus invalid
5
0
–
ns
ns
IAHDDI
9
DTACKN LOW to IACKN HIGH
–
DALIAH
IACKN
IDCN
t
IALDCL
SD00257
Figure 5. Interrupt Daisy Chain Timing
PARAMETER
LIMITS
SYMBOL
UNIT
Min
Max
t
IACKN LOW to IDCN (daisy chain) LOW
–
60
ns
IALDCL
11
2004 Mar 29
Philips Semiconductors
Product data
CMOS Dual universal serial communications controller
(CDUSCC)
SC68C562
RWN
CSN
GPI1_N
AND/OR
GPI2_N
t
CSLGII
t
GIVCSL
SD00258
Figure 6. Input Port Timing
LIMITS
SYMBOL
PARAMETER
UNIT
Min
20
Max
t
t
GPI input valid to CSN LOW
CSN LOW to GPI input invalid
–
–
ns
ns
GIVCSL
40
CSLGII
RWN
CSN
t
CSHGOV
t
DALGOV
GPO1_N
AND/OR
GPO2_N
OLD DATA
NEW DATA
12
DTACKN
t
CSLDAL
SD00259
Figure 7. Output Port Timing
LIMITS
SYMBOL
PARAMETER
UNIT
ns
Min
Max
9
t
t
DTACKN LOW to GPO output data valid
–
40
DALGOV
1.5
fCL
1
fCL
13
9
40 )
130 )
CSN LOW to DTACKN LOW
ns
CSLDAL
t
CSN HIGH to GPO output data valid
–
100
ns
CSHGOV
12
2004 Mar 29
Philips Semiconductors
Product data
CMOS Dual universal serial communications controller
(CDUSCC)
SC68C562
CSN
t
CSHIRH
DTACKN
t
DALIRH
IRQN
SD00260
Figure 8. Interrupt Timing, Write Cycle
LIMITS
SYMBOL
PARAMETER
UNIT
Min
Max
9
t
t
DTACKN LOW to IRQN HIGH, write cycle
DALIRH
9
Write TxFIFO (TxRDY interrupt)
–
–
–
–
–
40
40
40
40
40
ns
ns
ns
ns
ns
9
Write RSR (Rx condition interrupt)
9
Write TRSR (Rx/Tx interrupt)
9
Write ICTSR (port change and CT interrupt)
9
Write TRMSR (Tx Path, Patt recognition)
CSN HIGH to IRQN HIGH, write cycle
Write TxFIFO (TxRDY interrupt)
CSHIRH
–
–
–
–
–
90
90
90
90
90
ns
ns
ns
ns
ns
Write RSR (Rx condition interrupt)
Write TRSR (Rx/Tx interrupt)
Write ICTSR (port change and CT interrupt)
9
Write TRMSR (Tx Path, Patt recognition)
CSN
t
CSHIRH
IRQN
V
+.5V
OL
SD00261
Figure 9. Interrupt Timing, Read Cycle
PARAMETER
LIMITS
SYMBOL
UNIT
Min
Max
t
CSN HIGH to IRQN HIGH, read cycle
Read RxFIFO (RxRDY interrupt)
CSHIRH
–
90
ns
13
2004 Mar 29
Philips Semiconductors
Product data
CMOS Dual universal serial communications controller
(CDUSCC)
SC68C562
t
CLHCLL
*PULL-UP RESISTOR IS NOT REQUIRED
WHEN USING CMOS LEVELS
t
t
t
+5V
CCHCCL
RCHRCL
TCHTCL
TTL
470Ω
X1
*
X1/CLK
CTCLK
RxC
CLK
t
t
t
t
CLLCLH
CCLCCH
RCLRCH
TCLTCH
TxC
OPEN X2
a. Driving X1 from an External Source
CRYSTAL SERIES RESISTANCE SHOULD
BE LESS THAN 180Ω
X1
CP1
C1
TO DTACKN
BLOCK
360k
TO
1.5M
Y1
÷2
C2
ALL OTHER BLOCKS
CDUSCC
X2
CP2
SD00262
Figure 10. Receive, Dual Address DMA
LIMITS
UNIT
SYMBOL
PARAMETER
Min
25
25
45
45
50
50
50
50
0
Typ
Max
–
t
t
t
t
t
t
t
t
f
f
f
f
f
X1/CLK HIGH to LOW time
X1/CLK LOW to HIGH time
–
ns
ns
CLHCLL
CLLCLH
CCHCCL
CCLCCH
RCHRCL
RCLRCH
TCHTCL
TCLTCH
CL
–
–
CT and DPLL CLK HIGH to LOW time
CT and DPLL CLK LOW to HIGH time
RxC HIGH to LOW time
–
–
ns
–
–
ns
–
–
ns
RxC LOW to HIGH time
–
–
ns
TxC HIGH to LOW time
–
–
ns
TxC LOW to HIGH time
–
–
ns
11, 2
X1/CLK frequency
14.7456
16.0
10
10
10
5
MHz
MHz
MHz
MHz
MHz
CT CLK frequency
0
–
–
–
–
CC
RxC frequency (16X or 1X)
TxC frequency (16X or 1X)
0
RC
0
TC
Tx/Rx frequency for FM/Manchester encoding
–
RTC
14
2004 Mar 29
Philips Semiconductors
Product data
CMOS Dual universal serial communications controller
(CDUSCC)
SC68C562
1 BIT TIME
(1 OR 16 CLOCKS)
TxC
(INPUT)
TxC
(INPUT)
t
CILTXV
t
CILTXV
t
CILTXV
TxD
TxD
t
COLTXV
t
COLTXV
TxC
(1X OUTPUT)
t
COLTXV
TxC
(1X OUTPUT)
a. Transmit Timing NRZ
b. Transmit Timing FM0/1, Manchester Encoding
SD00263
Figure 11.
LIMITS
UNIT
SYMBOL
PARAMETER
Min
Max
TxC input LOW
t
(1X) to TxD output
(16X) to TxD output
–
–
120
120
ns
ns
CILTXV
TxC output LOW to TxD output
9
t
*
(NRZ, NRZI)
–
–
20
30
ns
ns
COLTXV
9
(FM, Manchester)
NOTE: Characterized with no loads on TxD and TxC outputs.* Tester load approximately 50 pF.
t
RCHSOL
RXC
(INPUT)
SYNOUTN
SYNIN
t
RCHRXI
t
SILRCH
t
RXVRCH
t
t
RXVRCH
RCHSIH
RxD
RXC (1X)
INPUT
t
t
t
RCHRXI
RCHRXI
RXVRCH
RxD
a. Receive Timing NRZ
b. Receive Timing FM0/1, Manchester Encoding
SD00264
Figure 12.
LIMITS
SYMBOL
PARAMETER
UNIT
Min
Max
RxD data valid to RxC HIGH:
For NRZ data
t
t
20
30
–
–
ns
ns
RXVRCH
For NRZI, Manchester, FM0, FM1 data
RxC HIGH to RxD data invalid:
For NRZ data
20
30
–
–
ns
ns
RCHRXI
For NRZI, Manchester, FM0, FM1 data
t
t
t
SYNIN LOW to RxC HIGH
RxC HIGH to SYNIN HIGH
RxC HIGH to SYNOUT LOW
50
20
–
–
–
ns
ns
ns
SILRCH
RCHSIH
RCHSOL
100
15
2004 Mar 29
Philips Semiconductors
Product data
CMOS Dual universal serial communications controller
(CDUSCC)
SC68C562
t
CSLDAL
CSN
t
ROLDAL
12
DTACKN
t
CSLROL
t
CSHROH
DONEN (OUTPUT)
(EOM)
t
RRHDAL
t
CSLRRH
RTxDRQ_N
SD00265
Figure 13. Receive, Dual Address DMA
PARAMETER
LIMITS
SYMBOL
UNIT
Min
–
Max
100
100
60
t
t
t
t
t
CSN LOW to Rx DONEN output LOW
CSN LOW to Rx DMA REQN HIGH
CSN HIGH to Rx DONEN output HIGH
Rx DONEN output LOW to DTACKN LOW
ns
ns
ns
ns
ns
CSLROL
CSLRRH
CSHROH
ROLDAL
RRHDAL
–
–
9
40
40
–
9
Rx DMA REQN HIGH to DTACKN LOW
–
1.5
fCL
1
fCL
40 )
130 )
13
9
t
CSN LOW to DTACKN LOW
ns
CSLDAL
t
TOLDAL
t
DALTOH
DONEN
(OUTPUT)
t
CSHTOH
t
CSLTOL
CSN
t
CSLDAL
12
t
DTACKN
CSHDIH
t
CSLDIL
t
DALDIH
DONEN
(INPUT)
t
CSLTRH
TxDRQ_N OR
RTxDRQ_N
t
TRHDAL
SD00266
Figure 14. Transmit, Dual Address DMA
PARAMETER
LIMITS
SYMBOL
UNIT
Min
–
Max
100
100
–
t
t
t
t
t
t
CSN LOW to Tx DONEN output LOW
CSN LOW to Tx DMA REQN HIGH
DTACKN LOW to Tx DONEN input HIGH
ns
ns
ns
ns
ns
ns
CSLTOL
CSLTRH
DALDIH
DALTOH
TOLDAL
TRHDAL
–
9
0
9
DTACKN LOW to Tx DONEN output HIGH
–
20
–
9
Tx DONEN output LOW to DTACKN LOW
40
40
9
Tx DMA REQN HIGH to DTACKN LOW
–
1.5
fCL
1
fCL
40 )
130 )
13
9
t
CSN LOW to DTACKN LOW
ns
CSLDAL
t
t
t
CSN LOW to Tx DONEN input LOW
CSN HIGH to Tx DONEN output HIGH
CSN HIGH to Tx DONEN input HIGH
40
–
–
ns
ns
ns
CSLDIL
CSHTOH
CSHDIH
60
–
25
16
2004 Mar 29
Philips Semiconductors
Product data
CMOS Dual universal serial communications controller
(CDUSCC)
SC68C562
SD00267
Figure 15. DMA Rx Read Timing—Single Address DMA
17
2004 Mar 29
Philips Semiconductors
Product data
CMOS Dual universal serial communications controller
(CDUSCC)
SC68C562
DMA Rx Read Timing — Single Address DMA
LIMITS
SYMBOL
PARAMETER
UNIT
Min
–
Max
t
t
t
t
Receive DMA ACKN LOW to read data valid
130
–
ns
ns
ns
ns
RALDDV
DTLDTH
DALDTL
DTLDDF
DTCN LOW to DTCN HIGH
DTACKN LOW to DTCN LOW
DTCN LOW to data bus float
40
0
9
–
–
60
1.5
fCL
1
fCL
9
40 )
130 )
t
Rx DMA ACK LOW to DTACKN LOW
ns
RALDAL
9
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Read data valid to DTACKN LOW
20
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DDVDAL
DTLDAH
DTLDAZ
RRHDAL
ROLDAL
RALRRH
RAHRAL
RALROL
DTLROH
RALRAH
RAHDDF
RALDDA
RAHDDI
DTLDDI
DTCN LOW to DTACKN HIGH
–
–
80
110
–
DTCN LOW to DTACKN high-impedance
9
Rx DMA REQN HIGH to DTACKN LOW
40
40
–
9
Rx DONEN output LOW to DTACKN LOW
–
Rx DMA ACKN LOW to receive DMA REQN HIGH
Receive DMA ACKN HIGH to LOW time
Rx DMA ACK LOW to Rx DONEN output LOW
DTCN LOW to Rx DONEN output HIGH
Rx DMA ACKN LOW to Rx DMA ACKN HIGH
Rx DMA ACKN HIGH to data bus float
100
–
30
–
100
70
–
–
130
–
60
–
9
Rx DMA ACKN LOW to data bus drivers active
10
5
Rx DMA ACKN HIGH to data bus invalid
DTCN LOW to data bus invalid
–
5
–
Rx DMA ACKN LOW to DTCN LOW
130
–
–
RALDTL
RAHDAH
RAHDAZ
RAHROH
Rx DMA ACKN HIGH to DTACKN HIGH
Rx DMA ACKN HIGH to DTACKN high-impedance
Rx DMA ACKN HIGH to DONEN output HIGH
70
100
60
–
–
18
2004 Mar 29
Philips Semiconductors
Product data
CMOS Dual universal serial communications controller
(CDUSCC)
SC68C562
DMA Tx Write Timing — Single Address DMA
LIMITS
SYMBOL
PARAMETER
UNIT
Min
40
0
Max
t
t
DTCN LOW to DTCN HIGH
DTACKN LOW to DTCN LOW
ns
ns
DTLDTH
9
DALDTL
1.5
fCL
1
fCL
9
40 )
130 )
t
Tx DMA ACK LOW to DTACKN LOW
ns
TALDAL
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
DTCN LOW to DTACKN HIGH
80
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DTLDAH
DTLDAZ
TRHDAL
TOLDAL
DTLTOH
WDVDTL
DTLWDI
TALTRH
TAHTAL
TALTOL
DILDTL
DTCN LOW to DTACKN high-impedance
110
70
9
Tx DMA REQN HIGH to DTACKN LOW
40
40
9
Tx DONEN output LOW to DTACKN LOW
DTCN LOW to Tx DONEN output HIGH
Write data valid to DTCN LOW
40
20
DTCN LOW to write data invalid
Tx DMA ACKN LOW to transmit DMA REQN HIGH
Transmit DMA ACKN HIGH to LOW time
Tx DMA ACKN LOW to Tx DONEN output LOW
Transmit DONEN input LOW to DTCN LOW
DTCN LOW to transmit DONEN input HIGH
Tx ACKN LOW to Tx ACKN HIGH
100
90
30
30
30
DTLDIH
TALTAH
TAHWDI
WDVTAH
TAHDAH
TAHDAZ
TAHTOH
DILTAH
100
10
Tx ACKN HIGH to write data invalid
Write data valid to Tx DAKN HIGH
40
Tx DAKN HIGH to DTACKN HIGH
70
100
60
Tx DAKN HIGH to DTACKN HIGH impedance
Tx DAKN HIGH to DONEN output HIGH
DONEN input LOW to Tx DAKN HIGH
Tx DAKN HIGH to DONEN input HIGH
Tx DAKN LOW to DTCN LOW
30
25
TAHDIH
TALDTL
100
19
2004 Mar 29
Philips Semiconductors
Product data
CMOS Dual universal serial communications controller
(CDUSCC)
SC68C562
SD00269
Figure 16. DMA Tx Write Timing—SIngle Address DMA
20
2004 Mar 29
Philips Semiconductors
Product data
CMOS Dual universal serial communications controller
(CDUSCC)
SC68C562
50
40
30
20
10
0
50
40
30
20
10
0
0 °C
25 °C
I
I
CC
CC
70 °C
4
4.5
5
5.5
6
4
6
8
10
V
Tx/Rx Clk and X1 Frequency
CC
Test Condition: Tx/Rx and X1 Frequency @ 10 MHz
Test Condition: V = 5 V at 25 °C
CC
SD00250
Figure 17.
2.7 kΩ
820 Ω
1 kΩ
TRxC
RTxC
IRQN
V
CC
50 pF
50 pF
DTACKN
+5.0 V
150 pF
DONEN
V
CC
50 pF
710 Ω
ALL OTHER
+5.0 V
OUTPUTS
150 pF
6.0 kΩ
NOTE:
All C includes 50 pF stray capacitance, i.e., C = 150 pF = (100 pF discrete + 50 pF stray).
L
L
SD00270
Figure 18. Test Conditions for Outputs
X1/CLK
WRN
COMMAND
VALID
SD00219
Figure 19. Command Timing
21
2004 Mar 29
Philips Semiconductors
Product data
CMOS Dual universal serial communications controller
(CDUSCC)
SC68C562
RxC
1
2
3
4
5
6
7
8
RxD
LCN
a. Loop Control Output Assertion
RxC
RxD
1
2
3
4
5
6
7
8
9
LCN
b. Loop Control Output Negation
SD00220
Figure 20. Relationship Between Received Data and the Loop Control Output
22
2004 Mar 29
Philips Semiconductors
Product data
CMOS Dual universal serial communications controller
(CDUSCC)
SC68C562
REVISION HISTORY
Rev
Date
Description
_3
20040329
Product data (9397 750 13068). Supersedes data of 1998 Sep 04 (9397 750 04356)
Modifications:
• Remove reference to Type numbers SC68C562C1N and SC68C562A8A (product discontinued), and to
“Industrial” temperature range throughout data sheet.
_2
_1
19980904
19940427
Product specification (9397 750 04356). ECN 853-1682 19973 of 04 September 1998.
Supersedes data of 1994 Apr 27.
23
2004 Mar 29
Philips Semiconductors
Product data
CMOS Dual universal serial communications controller
(CDUSCC)
SC68C562
Data sheet status
Product
status
Definitions
[1]
Level
Data sheet status
[2] [3]
I
Objective data
Development
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Product data
Qualification
Production
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limitingvaluesdefinition— Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given
in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no
representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be
expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described
or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated
viaaCustomerProduct/ProcessChangeNotification(CPCN).PhilipsSemiconductorsassumesnoresponsibilityorliabilityfortheuseofanyoftheseproducts,conveys
nolicenseortitleunderanypatent, copyright, ormaskworkrighttotheseproducts, andmakesnorepresentationsorwarrantiesthattheseproductsarefreefrompatent,
copyright, or mask work right infringement, unless otherwise specified.
Koninklijke Philips Electronics N.V. 2004
Contact information
All rights reserved. Printed in U.S.A.
For additional information please visit
http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
Date of release: 03-04
9397 750 13068
For sales offices addresses send e-mail to:
sales.addresses@www.semiconductors.philips.com.
Document order number:
Philips
Semiconductors
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