SCIMX6X4AVK10AB_技术文档

Document Number: IMX6SXIEC

Rev. 4, 11/2018

NXP Semiconductors

Data Sheet: Technical Data

MCIMX6XxCxxxxxB

MCIMX6XxCxxxxxC

i.MX 6SoloX Applications

Processors for Industrial

Products

Package Information

Plastic Package

BGA 19 x 19 mm, 0.8 mm pitch

BGA 17 x 17 mm, 0.8 mm pitch

BGA 14 x 14 mm, 0.65 mm pitch

Ordering Information

See Table 1 on page 3

1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.1 Special Signal Considerations. . . . . . . . . . . . . . . . 18

3.2 Recommended Connections for Unused Analog

Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 20

4.1 Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . . 20

4.2 Power Supplies Requirements and Restrictions . . 32

4.3 Integrated LDO Voltage Regulator Parameters . . 33

4.4 PLL Electrical Characteristics . . . . . . . . . . . . . . . . 35

4.5 On-Chip Oscillators . . . . . . . . . . . . . . . . . . . . . . . . 36

4.6 I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 37

4.7 I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 42

4.8 Output Buffer Impedance Parameters. . . . . . . . . . 45

4.9 System Modules Timing . . . . . . . . . . . . . . . . . . . . 48

4.10 Multi-mode DDR Controller (MMDC). . . . . . . . . . . 60

4.11 General-Purpose Media Interface (GPMI) Timing. 61

4.12 External Peripheral Interface Parameters . . . . . . . 69

4.13 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Boot Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . 116

5.1 Boot Mode Configuration Pins. . . . . . . . . . . . . . . 116

5.2 Boot Device Interface Allocation . . . . . . . . . . . . . 118

Package Information and Contact Assignments. . . . . . 126

6.1 i.MX 6SoloX Signal Availability by Package . . . . 126

6.2 Signals with Different States During Reset and After

Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

1 Introduction

The i.MX 6SoloX processors represent NXP

Semiconductor's latest achievement in integrated

multimedia-focused products offering high-performance

processing with a high degree of functional integration to

meet the demands of high-end, advanced industrial and

medical applications requiring graphically rich and

highly responsive user interfaces.

2

3

4

The i.MX 6SoloX processor features NXP’s advanced

®

implementation of the single Arm Cortex -A9 core,

which operates at speeds of up to 800 MHz, in addition

to the Arm Cortex-M4 core, which operates at speeds of

up to 227 MHz. This type of heterogeneous multicore

architecture provides greater levels of system

integration, smart low-power system awareness, and fast

real-time responsiveness. The i.MX 6SoloX includes a

GPU processor capable of supporting 2D and 3D

operations, a wide range of display and connectivity

options, and integrated power management. Each

processor provides a 32-bit

5

6

6.3 19x19 mm Package Information . . . . . . . . . . . . . 129

6.4 17x17 mm Package Information . . . . . . . . . . . . . 148

6.5 14x14 mm Package Information . . . . . . . . . . . . . 183

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

DDR3/DDR3L/LPDDR2-800 memory interface and a

number of other interfaces for connecting peripherals,

such as WLAN, Bluetooth™, GPS, displays, and camera

sensors.

7

NXP Reserves the right to change the production detail specifications as may be

required to permit improvements in the design of its products

Introduction

The i.MX 6SoloX processors are specifically useful for applications such as:

•

Entry-level infotainment

Telematics

Portable medical and health care

Smart appliances

Home energy management systems

Industrial control and automation

The features of the i.MX 6SoloX processors include:

•

Dual-core architecture with one Arm Cortex-A9 processor plus one Arm Cortex-M4 processor—

Dual-core architecture enables the device to run an open operating system like Linux on the

Cortex-A9 core and an RTOS like MQX™ or FreeRTOS™ on the Cortex-M4 core. The Cortex-M4

core is standard on all i.MX 6SoloX processors.

•

Multilevel memory system—The multilevel memory system of each processor is based on the L1

instruction and data caches, L2 cache, and internal and external memory. The processors support

many types of external memory devices, including DDR3, low voltage DDR3, LPDDR2, NOR

Flash, NAND Flash (MLC and SLC), OneNAND, Quad SPI, and managed NAND, including

eMMC up to rev 4.4/4.41/4.5.

•

Smart speed technology—Power management implemented throughout the IC that enables

multimedia features and peripherals to consume minimum power in both active and various low

power modes.

•

Dynamic voltage and frequency scaling—The processors improve the power efficiency of devices

by scaling the voltage and frequency to optimize performance.

Multimedia powerhouse—The multimedia performance of each processor is enhanced by a

multilevel cache system, NEON™ MPE (Media Processor Engine) co-processor, a programmable

smart DMA (SDMA) controller, and an asynchronous sample rate converter.

•

2x Gigabit Ethernet with AVB—2x 10/100/1000 Mbps Gigabit Ethernet controllers with support

for Audio Video Bridging (AVB) for reliable, high-quality, low-latency multimedia streaming.

Human-machine interface—Each processor provides a single integrated graphics processing unit

that supports an OpenGL ES 2.0 and OpenVG 1.1 3D and 2D graphics accelerator. In addition,

each processor provides up to two separate display interfaces (parallel display and LVDS display)

and a CMOS sensor interface (parallel).

•

Interface flexibility—Each processor supports connections to a variety of interfaces: High-speed

USB on-the-go with PHY, high-speed USB host with PHY, High-Speed Inter-Chip USB, multiple

expansion card ports (high-speed MMC/SDIO host and other), 2 Gigabit Ethernet controllers with

support for Ethernet AVB, PCIe-II, two 12-bit ADC modules with 4 dedicated single-ended inputs,

2

two CAN ports, ESAI audio interface, and a variety of other popular interfaces (such as UART, I C,

2

and I S serial audio).

Advanced security—The processors deliver hardware-enabled security features that enable secure

e-commerce, digital rights management (DRM), information encryption, secure boot, and secure

software downloads. The security features are discussed in detail in the i.MX 6SoloX Security

Reference Manual (IMX6XSRM).

i.MX 6SoloX Applications Processors for Industrial Products, Rev. 4, 11/2018

2

NXP Semiconductors

Introduction

•

Integrated power management—The processors integrate linear regulators and internally generate

voltage levels for different domains. This significantly simplifies system power management

structure.

For a comprehensive list of the i.MX 6SoloX features, see Section 1.2, “Features”.

1.1

Ordering Information

Table 1 provides examples of orderable sample part numbers covered by this data sheet.

Table 1. Ordering Information

Cortex- Cortex-

Junction

Temperature

Range

Mask

Set

Qualification

Tier

Part Number

Options

A9

M4

Package

Speed¹Speed

MCIMX6X1CVO08AB Features not 2N19K

supported: or

800

MHz

227

MHz

Industrial

-40 to

+105°C

17x17NP (NP=No PCIe)

Package code “VO”

17mm x 17mm

- 2D&3D GPU 3N19K

- PCIe

- LVDS

- MLB

0.8pitch Map BGA

MCIMX6X1CVO08AC Features not 4N19K

800

MHz

227

MHz

-40 to

+105°C

17x17NP (NP=No PCIe)

Package code “VO”

17mm x 17mm

supported:

- 2D&3D GPU

- PCIe

0.8pitch Map BGA

- LVDS

- MLB

MCIMX6X3CVO08AB Features not 2N19K

800

MHz

227

MHz

Industrial

-40 to

+105°C

17x17NP (NP=No PCIe)

Package code “VO”

17mm x 17mm

supported:

- PCIe

or

3N19K

- LVDS

- MLB

0.8pitch Map BGA

MCIMX6X3CVO08AC Features not 4N19K

800

MHz

227

MHz

-40 to

+105°C

17x17NP (NP=No PCIe)

Package code “VO”

17mm x 17mm

supported:

- PCIe

- LVDS

- MLB

0.8pitch Map BGA

MCIMX6X1CVK08AB Features not 2N19K

800

MHz

227

MHz

-40 to

+105°C

14x14NP (NP = No PCIe)

Package code “VK”

14mm x 14mm

supported:

or

- 2D&3D GPU 3N19K

- PCIe

- LVDS

- MLB

0.65pitch Map BGA

MCIMX6X1CVK08AC Features not 4N19K

800

MHz

227

MHz

Industrial

-40 to

+105°C

14x14NP (NP = No PCIe)

Package code “VK”

14mm x 14mm

supported:

- 2D&3D GPU

- PCIe

0.65pitch Map BGA

- LVDS

- MLB

i.MX 6SoloX Applications Processors for Industrial Products, Rev. 4, 11/2018

NXP Semiconductors

3

Introduction

Table 1. Ordering Information (continued)

Cortex- Cortex-

Junction

Temperature

Range

Mask

Set

Qualification

Tier

Part Number

Options

A9

M4

Package

Speed¹Speed

MCIMX6X3CVK08AB Features not 2N19K

800

MHz

227

MHz

Industrial

-40 to

+105°C

14x14NP (NP = No PCIe)

Package code “VK”

14mm x 14mm

supported:

- PCIe

or

3N19K

- LVDS

- MLB

0.65pitch Map BGA

MCIMX6X3CVK08AC Features not 4N19K

800

MHz

227

MHz

-40 to

+105°C

14x14NP (NP = No PCIe)

Package code “VK”

14mm x 14mm

supported:

- PCIe

- LVDS

- MLB

0.65pitch Map BGA

MCIMX6X2CVN08AB Features not 2N19K

800

MHz

227

MHz

-40 to

+105°C

17x17WP (WP=With PCIe)

Package code “VN”

17mm x 17mm

supported:

or

- 2D&3D GPU 3N19K

- LVDS

- MLB

0.8pitch Map BGA

MCIMX6X2CVN08AC Features not 4N19K

800

MHz

227

MHz

-40 to

+105°C

17x17WP (WP=With PCIe)

Package code “VN”

17mm x 17mm

supported:

- 2D&3D GPU

- LVDS

0.8pitch Map BGA

- MLB

MCIMX6X3CVN08AB Features not 2N19K

800

MHz

227

MHz

Industrial

-40 to

+105°C

17x17WP (WP=With PCIe)

Package code “VN”

17mm x 17mm

supported:

- LVDS

- MLB

or

3N19K

0.8pitch Map BGA

MCIMX6X3CVN08AC Features not 4N19K

800

MHz

227

MHz

-40 to

+105°C

17x17WP (WP=With PCIe)

Package code “VN”

17mm x 17mm

supported:

- LVDS

- MLB

0.8pitch Map BGA

MCIMX6X4CVM08AB Features not 2N19K

800

MHz

227

MHz

-40 to

+105°C

19x19

Package code “VM”

19mm x 19mm

supported:

- MLB

or

3N19K

0.8pitch Map BGA

MCIMX6X4CVM08AC Features not 4N19K

800

227

-40 to

19x19

supported:

- MLB

MHz

+105°C

Package code “VM”

19mm x 19mm

0.8pitch Map BGA

1

If a 24 MHz input clock is used (required for USB), the maximum Cortex-A9 speed for 1 GHz speed grade is limited to 996 MHz

and the maximum Cortex-A9 speed for 800 MHz speed grade is limited to 792 MHz.

Figure 1 describes the part number nomenclature so that the users can identify the characteristics of the

specific part number they have (for example, cores, frequency, temperature grade, fuse options, and silicon

revision). The primary characteristic which describes which data sheet applies to a specific part is the

temperature grade (junction) field.

•

The i.MX 6SoloX Automotive and Infotainment Applications Processors data sheet

(IMX6SXAEC) covers parts listed with an “A (Automotive temp)”

i.MX 6SoloX Applications Processors for Industrial Products, Rev. 4, 11/2018

4

NXP Semiconductors

Introduction

•

The i.MX 6SoloX Applications Processors for Consumer Products data sheet (IMX6SXCEC)

covers parts listed with a “D (Commercial temp)” or “E (Extended Commercial temp)”

The i.MX 6SoloX Applications Processors for Industrial Products data sheet (IMX6SXIEC) covers

parts listed with “C (Industrial temp)”

Ensure to have the proper data sheet for specific part by verifying the temperature grade (junction) field

and matching it to the proper data sheet. If there will be any questions, visit see the web page

nxp.com/imx6series or contact a NXP representative for details.

MC

IMX6 X @ + VV $$ % A

Silicon Revision¹

A

Qualification Level

MC

Rev 1.2 Production (Maskset 2N19K)

Rev 1.3 Production (Maskset 3N19K)

B

Prototype Samples

Mass Production

Special

PC

MC

SC

Rev 1.4 Production (Maskset 4N19K)

C

Fusing

%

i.MX 6 Family

X

Security Enabled

A

i.MX 6SoloX

X

ARM Cortex-A9 Frequency

$$

08

10

Part Differentiator

@

4

800 MHz

1 GHz

Package

VM

GPU

PCIe

LVDS

ADC

MLB

Y

-

Y

-

Y

-

2x 4ch

1x 2ch

2x 4ch

1x 2ch

2x 4ch

Y

-

Automotive

Ext. Commercial/ Industrial

Automotive

ROHS

Package Type

VN

VO

VK

-

14x14NP: MAPBGA 14x14 0.65mm

NP = No PCIe

VK

-

3

17x17NP: MAPBGA 17x17 0.8mm

NP = No PCIe

-

VO

Y

-

Y

-

17x17WP: MAPBGA 17x17 0.8mm

WP = With PCIe

VN

VO

VK

VN

VM

2

-

Ext. Commercial/ Industrial

Automotive

MAPBGA 19x19 0.8mm

-

Y

-

Ext. Commercial/ Industrial

Automotive

1

Junction Temperature (Tj)

+

-

Y

-

Extended Commercial: -20 to + 105C

Industrial: -40 to +105C

E

C

A

-

Ext. Commercial/ Industrial

1. See the nxp.com\imx6series Web page for latest information on the available silicon revision.

Auto: -40 to + 125C

Figure 1. Part Number Nomenclature—i.MX 6SoloX

1.2

Features

The i.MX 6SoloX processors are based on the Arm Cortex-A9 MPCore™ platform, which has the

following features:

•

Supports single Arm Cortex-A9 MPCore processor (with TrustZone)

The core configuration is symmetric, where each core includes:

— 32 KByte L1 Instruction Cache

— 32 KByte L1 Data Cache

— Private Timer and Watchdog

i.MX 6SoloX Applications Processors for Industrial Products, Rev. 4, 11/2018

NXP Semiconductors

5

Introduction

— Cortex-A9 NEON MPE (Media Processing Engine) coprocessor

The Arm Cortex-A9 MPCore complex includes:

•

General Interrupt Controller (GIC) with 128 interrupt support

Global Timer

Snoop Control Unit (SCU)

256 KB unified I/D L2 cache:

Two Master AXI bus interfaces output of L2 cache

Frequency of the core (including NEON coprocessor and L1 cache), as per Table 9, “Operating

Ranges,” on page 25.

•

NEON MPE coprocessor

— SIMD Media Processing Architecture

— NEON register file with 32x64-bit general-purpose registers

— NEON Integer execute pipeline (ALU, Shift, MAC)

— NEON dual, single-precision floating point execute pipeline (FADD, FMUL)

— NEON load/store and permute pipeline

— 32 double-precision VFPv3 floating point registers

The Arm Cortex-M4 platform:

•

Cortex-M4 CPU core

MPU (Memory Protection Unit)

FPU (Floating Point Unit)

16 KByte Instruction Cache

16 KByte Data Cache

64 KByte TCM (Tightly-Coupled Memory)

The SoC-level memory system consists of the following additional components:

— Boot ROM, including HAB (96 KB)

— Internal multimedia / shared, fast access RAM (OCRAM, 128 KB)

— Internal RAM for state retention or general use (OCRAM_S, 16KB)

— Secure/non-secure RAM (32 KB)

•

External memory interfaces: The i.MX 6SoloX processors support latest, high volume, cost

effective handheld DRAM, NOR, and NAND Flash memory standards.

— 16/32-bit LPDDR2-800, 16/32-bit DDR3-800 and DDR3L-800

— 16-bit NAND-Flash, including support for Raw MLC/SLC, 2 KB, 4 KB, and 8 KB page size,

BA-NAND, PBA-NAND, LBA-NAND, OneNAND and others. BCH ECC up to 62 bits. 16-bit

boot is supported from OneNAND. 8-bit boot is supported from other NAND types.

— 16/32-bit NOR Flash. All EIMv2 pins are muxed on other interfaces.

i.MX 6SoloX Applications Processors for Industrial Products, Rev. 4, 11/2018

6

NXP Semiconductors

Introduction

Each i.MX 6SoloX processor enables the following interfaces to external devices (some of them are

muxed and not available simultaneously):

•

Displays—Total three interfaces available.

— Two parallel 24-bit display ports, each up to 1080P at 60 Hz

— LVDS serial port—One port up to 85 MP/sec (for example, WXGA at 60 Hz)

Camera sensors:

•

— Two parallel camera ports (up to 24 bit and up to 133 MHz peak)

Expansion cards:

— Four MMC/SD/SDIO card ports all supporting:

– 1-bit or 4-bit transfer mode specifications for SD and SDIO cards up to UHS-I SDR-104

mode (104 MB/s max)

– 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards up to 200 MHz in HS200

mode (200 MB/s max)

•

USB^:

— Two high speed (HS) USB 2.0 OTG (Up to 480 Mbps), with integrated HS USB Phy

— One HS-IC USB (High-Speed Inter-Chip USB) host

Expansion PCI Express port (PCIe) v2.0 one lane

•

— PCI Express (Gen 2.0) dual mode complex, supporting Root complex operations and Endpoint

operations. Uses x1 PHY configuration.

Miscellaneous IPs and interfaces:

— Three SSIs and two SAIs supporting up to five I2S or AC97 ports

— Enhanced Serial Audio Interface (ESAI)

— Sony Philips Digital Interconnect Format (SPDIF), Rx and Tx

— Audio MUX (AUDMUX)

— Medium Quality Sound (MQS) module provides an opportunity for BOM cost reduction if

high-quality sound is not required

— Six UARTs, up to 5.0 Mbps each:

– Providing RS232 interface

– Supporting 9-bit RS485 multidrop mode

– One of the six UARTs (UART1) supports 8-wire while others support 4-wire. This is due to

the SoC IOMUX limitation, since all UART IPs are identical.

— Five eCSPI (Enhanced CSPI)

2

— Four I C

— Two Gigabit Ethernet Controllers (designed to be compatible with IEEE AVB standards and

®

IEEE Std 1588 ), 10/100/1000 Mbps

— Eight Pulse Width Modulators (PWM)

— System JTAG Controller (SJC)

— GPIO with interrupt capabilities

i.MX 6SoloX Applications Processors for Industrial Products, Rev. 4, 11/2018

NXP Semiconductors

7

Introduction

— 8x8 Key Pad Port (KPP)

— Two Quad SPIs

— Two Flexible Controller Area Network (FlexCAN), 1 Mbps each

— Three Watchdog timers (WDOG)

— Up to two 4-channel, 12-bit Analog to Digital Converters (ADC), VM, VO, VK packages

— One 2-channel, 12-bit Analog to Digital Converter (ADC), VN package

The i.MX 6SoloX processors integrate advanced power management unit and controllers:

•

Provide PMU, including LDO supplies, for on-chip resources

Use Temperature Sensor for monitoring the die temperature

Support DVFS techniques for low power modes

Use software state retention and power gating for Arm Cortex-A9 CPU core, the Arm Cortex-M4

CPU core, and the Arm NEON MPE coprocessor.

•

Support various levels of system power modes

Use flexible clock gating control scheme

The i.MX 6SoloX processors use dedicated hardware accelerators to meet the targeted multimedia

performance. The use of hardware accelerators is a key factor in obtaining high performance at low power

consumption, while having the CPU core relatively free for performing other tasks.

The i.MX 6SoloX processors incorporate the following hardware accelerators:

•

GPU—2D (BitBlt) and 3D (OpenGL ES) Graphics Processing Unit

PXP—PiXel Processing Pipeline for imagine resize, rotation, overlay and CSC. Off loading key

pixel processing operations are required to support the LCD display applications.

•

ASRC—Asynchronous Sample Rate Converter

Security functions are enabled and accelerated by the following hardware:

•

Arm TrustZone including the TZ architecture (separation of interrupts, memory mapping, etc.)

SJC—SystemJTAGController. ProtectingJTAGfromdebugportattacks by regulating orblocking

the access to the system debug features.

•

CAAM—Cryptographic Acceleration and Assurance Module, containing cryptographic and hash

engines, 32 KB secure RAM, and True and Pseudo Random Number Generator (NIST certified).

•

SNVS—Secure Non-Volatile Storage, including Secure Real Time Clock

CSU—Central Security Unit. Enhancement for the IC Identification Module (IIM). Will be

configured during boot and by eFUSEs and will determine the security level operation mode as

well as the TZ policy.

•

A-HAB—Advanced High Assurance Boot—HABv4 with the new embedded enhancements:

SHA-256, 2048-bit RSA key, version control mechanism, warm boot, CSU, and TZ initialization.

NOTE

The actual feature set depends on the part numbers as described in Table 1.

Functions, such as display and camera interfaces, connectivity interfaces,

video hardware acceleration, and 2D and 3D hardware graphics acceleration

may not be enabled for specific part numbers.

i.MX 6SoloX Applications Processors for Industrial Products, Rev. 4, 11/2018

8

NXP Semiconductors

Architectural Overview

2 Architectural Overview

The following subsections provide an architectural overview of the i.MX 6SoloX processor system.

2.1

Block Diagram

Figure 2 shows the functional modules in the i.MX 6SoloX processor system.

LP-DDR2

/ DDR3

Battery Ctrl

Device

JTAG

(IEEE1149.6)

Crystal &

Clock Source

Sensors

External Memory

ARM Cortex A9

MPCore Platform

Debug

Clock& Reset

MMC/SD

eMMC/eSD

NAND FLASH

MMDC

DAP

PLL (7)

Cortex-A9 Core

EIM

TPIU

CTIs

SJC

CCM

GPC

SRC

I$ 32KB

NEON

D$ 32KB

PTM

GPMI & BCH

QSPI (2)

NOR FLASH

(Parallel)

MMC/SD

SDXC

SCU & Timer

XTAL OSC

32K OSC

L2 Cache 256KB

Internal Memory

Timer/Control

OCRAM144KB

WDOG(3)

ARM CortexM4

NOR FLASH

(Quad SPI)

Touch Panel

Control

AP Peripherals

ROM 96KB

GPT

Platform

uSDHC(4)

EPIT (2)

Cortex-M4 Core

AUDMUX

UART(5)

Security

CAAM

(32KB RAM)

Temp Monitor

I$ 16KB

MPU

TCM 64KB

D$ 16KB

FPU

Temper

Detection

eCSPI (1)

I2C (4)

Keypad

CSU

Smart DMA

SDMA

Fuse Box

PWM (8)

OCOTP

SNVS

(SRTC)

Multi-CoreUnit

RDC MU

SPBA

10/100/1000M

Ethernetx2

LCD Panel

IOMUXC

KPP

DisplayInterface

SEMAPHORE

Shared Peripherals

LCDIF

eCSPI (4)

GPIO

Graphics

LVDS (LDB)

SPDIF Tx/Rx

MLB/MOST

Network

Ethernet(2)

CAN(2)

CMOS Sensor

3D&2D Graphics

Processing Unit

(GPU)

SSI (3)

ESAI

Camera Interface

(

)

UART 1

ASRC

USB OTG(2)

USB Host(HSIC)

MLB

CSI (2)

Image Processing

CAN x2

Power Management

Pixel Processing Pipeline

(PXP)

LDOs

PCIe

USB OTG

(dev/host)

WLAN

Modem IC

Digital Audio

PCIe Bus

Figure 2. i.MX 6SoloX System Block Diagram

NOTE

The numbers in brackets indicate number of module instances. For example,

PWM (8) indicates eight separate PWM peripherals.

i.MX 6SoloX Applications Processors for Industrial Products, Rev. 4, 11/2018

NXP Semiconductors

9

Modules List

3 Modules List

The i.MX 6SoloX processors contain a variety of digital and analog modules. Table 2 describes these

modules in alphabetical order.

Table 2. i.MX 6SoloX Modules List

Block Mnemonic

Block Name

Subsystem

Brief Description

ADC1

ADC2

Analog to Digital

Converter

—

The ADC is a 12-bit general purpose analog to digital

converter.

ARM

ARM Platform

Arm

The ARM Core Platform includes 1x Cortex-A9 and 1x

Cortex-M4 cores. It also includes associated sub-blocks,

such as the Level 2 Cache Controller, SCU (Snoop Control

Unit), GIC (General Interrupt Controller), private timers,

watchdog, and CoreSight debug modules.

ASRC

Asynchronous Sample

Rate Converter

Multimedia

Peripherals

The Asynchronous Sample Rate Converter (ASRC)

converts the sampling rate of a signal associated to an

input clock into a signal associated to a different output

clock. The ASRC supports concurrent sample rate

conversion of up to 10 channels of about -120dB THD+N.

The sample rate conversion of each channel is associated

to a pair of incoming and outgoing sampling rates. The

ASRC supports up to three sampling rate pairs.

AUDMUX

Digital Audio Mux

Multimedia

Peripherals

The AUDMUX is a programmable interconnect for voice,

audio, and synchronous data routing between host serial

interfaces (for example, SSI1, SSI2, and SSI3) and

peripheral serial interfaces (audio and voice codecs). The

AUDMUX has seven ports with identical functionality and

programming models. A desired connectivity is achieved

by configuring two or more AUDMUX ports.

BCH

Binary-BCH ECC

Processor

System Control

Peripherals

The BCH module provides up to 62-bit ECC for NAND

Flash controller (GPMI).

CAAM

Cryptographic

accelerator and

assurance module

Security

CAAM is a cryptographic accelerator and assurance

module. CAAM implements several encryption and

hashing functions, a run-time integrity checker, and a

Pseudo Random Number Generator (PRNG). The pseudo

random number generator is certified by Cryptographic

Algorithm Validation Program (CAVP) of National Institute

of Standards and Technology (NIST). Its DRBG validation

number is 94 and its SHS validation number is 1455.

CAAM also implements a Secure Memory mechanism. In

i.MX 6SoloX processors, the security memory provided is

32 KB.

CCM

GPC

SRC

Clock Control Module,

Clocks, Resets,

These modules are responsible for clock and reset

GeneralPowerController, and Power Control distribution in the system, and also for the system power

System Reset Controller

management.

CSI

Parallel CSI

Multimedia

Peripherals

The CSI IP provides parallel CSI standard camera

interface port. The CSI parallel data ports are up to 24 bits.

It is designed to support 24-bit RGB888/YUV444,

CCIR656 video interface, 8-bit YCbCr, YUV or RGB, and

8-bit/10-bit/26-bit Bayer data input.

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Modules List

Table 2. i.MX 6SoloX Modules List (continued)

Block Name Subsystem Brief Description

Central Security Unit Security

Block Mnemonic

CSU

The Central Security Unit (CSU) is responsible for setting

comprehensive security policy within the i.MX 6SoloX

platform.

CTI

Cross Trigger Interfaces Debug/Trace

Cross Trigger Interfaces allows cross-triggering based on

inputs from masters attached to CTIs. The CTI module is

internal to the Cortex-A9 Core Platform.

DAP

Debug Access Port

System Control

Peripherals

The DAP provides real-time access for the debugger

without halting the core to:

System memory and peripheral registers

All debug configuration registers

The DAP also provides debugger access to JTAG scan

chains. The DAP module is internal to the Cortex-A9 Core

Platform.

DBGMON

Debug Monitor

Debug

DBGMON is a real-time debug monitor to record last AXI

transaction before system reset.

eCSPI1

eCSPI2

eCSPI3

eCSPI4

eCSPI5

Configurable SPI

Connectivity

Peripherals

Full-duplex enhanced Synchronous Serial Interface. It is

configurable to support Master/Slave modes, four chip

selects to support multiple peripherals.

EIM

NOR-Flash /PSRAM

interface

Connectivity

Peripherals

The EIM NOR-FLASH / PSRAM provides:

Support 16-bit (in muxed IO mode only) PSRAM memories

(sync and async operating modes), at slow frequency

Support 16-bit (in muxed IO mode only) NOR-Flash

memories, at slow frequency

Multiple chip selects

ENET1

ENET2

Ethernet Controller

Connectivity

Peripherals

The Ethernet Media Access Controller (MAC) is designed

to support 10/100/1000 Mbps Ethernet/IEEE 802.3

networks. An external transceiver interface and transceiver

function are required to complete the interface to the

media. The module has dedicated hardware to support the

IEEE 1588 standard. See the ENET chapter of the i.MX

6SoloX Applications Processor Reference Manual

(IMX6SXRM) for details.

EPIT1

EPIT2

Enhanced Periodic

Interrupt Timer

Timer Peripherals Each EPIT is a 32-bit “set and forget” timer that starts

counting after the EPIT is enabled by software. It is capable

of providing precise interrupts at regular intervals with

minimal processor intervention. It has a 12-bit prescaler for

division of input clock frequency to get the required time

setting for the interrupts to occur, and counter value can be

programmed on the fly.

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Modules List

Table 2. i.MX 6SoloX Modules List (continued)

Block Name Subsystem Brief Description

Connectivity

Block Mnemonic

ESAI

Enhanced Serial Audio

Interface

The Enhanced Serial Audio Interface (ESAI) provides a

full-duplex serial port for serial communication with a

variety of serial devices, including industry-standard

codecs, SPDIF transceivers, and other processors.

The ESAI consists of independent transmitter and receiver

sections, each section with its own clock generator. All

serial transfers are synchronized to a clock. Additional

synchronization signals are used to delineate the word

frames. The normal mode of operation is used to transfer

data at a periodic rate, one word per period. The network

mode is also intended for periodic transfers; however, it

supports up to 32 words (time slots) per period. This mode

can be used to build time division multiplexed (TDM)

networks. In contrast, the on-demand mode is intended for

non-periodic transfers of data and to transfer data serially

at high speed when the data becomes available.

The ESAI has 12 pins for data and clocking connection to

external devices.

Peripherals

FLEXCAN1

FLEXCAN2

Flexible Controller Area

Network

Connectivity

Peripherals

The CAN protocol was primarily, but not only, designed to

be used as a vehicle serial data bus, meeting the specific

requirements of this field: real-time processing, reliable

operation in the Electromagnetic interference (EMI)

environment of a vehicle, cost-effectiveness and required

bandwidth. The FlexCAN module is a full implementation

of the CAN protocol specification, Version 2.0 B, which

supports both standard and extended message frames.

Fuse Box

GC400T

GIC

Electrical Fuse Array

Graphics Engine

Security

Electrical Fuse Array. Enables setup of boot modes,

security levels, security keys, and many other system

parameters.The fuses are accessible through

OCOTP_CTRL interface.

Multimedia

Peripherals

The GC400T is a graphics engine with separate 2D and 3D

pipelines to provide both 2D and 3D acceleration. It

supports DirectFB and GAL APIs. It supports OpenGL

ES1.1/2.0 and OpenVG 1.1 APIs.

Global Interrupt

Controller

Arm/Control

The Global Interrupt Controller (GIC) collects interrupt

requests from all i.MX 6SoloX sources and routes them to

the Arm MPCore(s). Each interrupt can be configured as a

normal or a secure interrupt. Software Force Registers and

software Priority Masking are also supported. This IP is

part of the Arm Core complex.

GIS

General Interrupt Service Camera, Display, GIS can be used to automate the flow of data from the

module

& Graphics

camera to the display.

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

General Purpose I/O

Modules

System Control

Peripherals

Used for general purpose input/output to external ICs.

Each GPIO module supports 32 bits of I/O.

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Modules List

Table 2. i.MX 6SoloX Modules List (continued)

Block Name Subsystem Brief Description

Block Mnemonic

GPMI

General Purpose

Memory Interface

Connectivity

Peripherals

The GPMI module supports up to 8x NAND devices and

60-bit ECC encryption/decryption for NAND Flash

Controller (GPMI2). GPMI supports separate DMA

channels for each NAND device.

GPT

General Purpose Timer

Timer Peripherals Each GPT is a 32-bit “free-running” or “set and forget”

mode timer with programmable prescaler and compare

and capture register. A timer counter value can be

captured using an external event and can be configured to

trigger a capture event on either the leading or trailing

edges of an input pulse. When the timer is configured to

operate in “set and forget” mode, it is capable of providing

precise interrupts at regular intervals with minimal

processor intervention. The counter has output compare

logic to provide the status and interrupt at comparison.

This timer can be configured to run either with an external

clock or an internal clock.

I2C-1

I2C-2

I2C-3

I2C-4

I2C Interface

Connectivity

Peripherals

I2C provide serial interface for external devices. Data rates

of up to 400 kbps are supported.

IOMUXC

IOMUX Control

Key Pad Port

System Control

Peripherals

This module enables flexible IO multiplexing. Each IO pad

has default and several alternate functions. The alternate

functions are software configurable.

KPP

Connectivity

Peripherals

KPP Supports 8x8 external key pad matrix. KPP features

are:

• Open drain design

• Glitch suppression circuit design

• Multiple keys detection

• Standby key press detection

LCDIF

LCD Interface

Multimedia

Peripherals

The LCDIF provides display data for external LCD panels

from simple text-only displays to WVGA, 16/18/24 bpp

color TFT panels. The LCDIF supports all of these different

interfaces by providing fully programmable functionality

and sharing register space, FIFOs, and ALU resources at

the same time. The LCDIF supports RGB (DOTCLK)

modes as well as system mode including both VSYNC and

WSYNC modes.

LVDS (LDB)

LVDS Display Bridge

MediaLB

Connectivity

Peripherals

LVDS Display Bridge is used to connect an external LVDS

display interface. LDB supports the following signals:

• One clock pair

• Four data pairs

MLB

Connectivity/

Multimedia

Peripherals

The MLB interface module provides a link to a MOST®

data network, using the standardized MediaLB protocol

(MOST25, MOST 50).

MMDC

Multi-Mode DDR

Controller

Connectivity

Peripherals

DDR Controller supports 16/32-bit LPDDR2-800,

DDR3-800 and DDR3L-800.

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Modules List

Table 2. i.MX 6SoloX Modules List (continued)

Block Mnemonic

Block Name

Subsystem

Brief Description

The MU module supports interprocessor communication

MU

Messaging Unit

OTP Controller

Interprocessor

Communication & between the Cortex-A9 and Cortex-M4 cores.

Synchronization

OCOTP_CTRL

Security

The On-Chip OTP controller (OCOTP_CTRL) provides an

interface for reading, programming, and/or overriding

identification and control information stored in on-chip fuse

elements. The module supports electrically-programmable

(eFUSE) polyfuses. The OCOTP_CTRL also provides a

set of volatile software-accessible signals that can be used

for software control of hardware elements, not requiring

non-volatility. The OCOTP_CTRL provides the primary

user-visible mechanism for interfacing with on-chip fuse

elements. Among the uses for the fuses are unique chip

identifiers, mask revision numbers, cryptographic keys,

JTAG secure mode, boot characteristics, and various

control signals, requiring permanent non-volatility.

OCRAM

On-Chip Memory

Controller

Data Path

The On-Chip Memory controller (OCRAM) module is

designed as an interface between system’s AXI bus and

internal (on-chip) SRAM memory module.

OCRAM 128 KB Internal RAM

Internal Memory

Internal RAM, which is accessed through OCRAM memory

controller.

OCRAM_S 16KB Secure/nonsecure RAM Secured Internal

Memory

Secure/nonsecure internal RAM, interfaced through the

CAAM. OCRAM_S can be used by software for state

retention of the CPU and other hardware blocks.

OSC32KHz

PCIe

OSC32KHz

Clocking

Generates 32.768 KHz clock from external crystal.

PCI Express 2.0

Connectivity

Peripherals

The PCIe IP provides PCI Express Gen 2.0 functionality.

PMU

Power-Management

functions

Data Path

Integrated power management unit. Used to provide power

to various SoC domains.

PWM-1

PWM-2

PWM-3

PWM-4

PWM-5

PWM-6

PWM-7

PWM-8

Pulse Width Modulation Connectivity

Peripherals

The pulse-width modulator (PWM) has a 16-bit counter

and is optimized to generate sound from stored sample

audio images and it can also generate tones. It uses 16-bit

resolution and a 4x16 data FIFO to generate sound.

PXP

PiXel Processing Pipeline Display

Peripherals

A high-performance pixel processor capable of 1

pixel/clock performance for combined operations, such as

color-space conversion, alpha blending, gamma-mapping,

and rotation. The PXP is enhanced with features

specifically for gray scale applications.

QSPI

Quad Serial Peripheral

Interface

Connectivity

Peripherals

The Quad Serial Peripheral Interface (QuadSPI) block acts

as an interface to one or two external serial flash devices,

each with up to four bidirectional data lines.

ROM 96KB

Boot ROM

Internal Memory

Supports secure and regular boot modes

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Modules List

Table 2. i.MX 6SoloX Modules List (continued)

Block Name Subsystem Brief Description

Block Mnemonic

RDC

Resource Domain

Controller

Multicore

Isolation/Sharing

RDC module supports domain-based access control to

shared resources.

SEMA4

Semaphore

Multicore/Isolation Supports hardware-enforced semaphores.

/Sharing

SEMA42

Semaphore

Multicore/Isolation SEMA42 is similar to SEMA4 with the following key

/Sharing

differences:

SEMA42 increases the number of access domains from 2

to 15

SEMA42 does not have interrupt to indicate semaphore

release

RDC programming model supports the option to require

hardware semaphore for peripherals shared between

domains. Signaling between the SEMA42 and RDC binds

peripherals to semaphore gates within SEMA42.

SAI1

SAI2

—

The SAI module provides a synchronous audio interface

(SAI) that supports full duplex serial interfaces with frame

synchronization, such as I2S, AC97, TDM, and codec/DSP

interfaces.

SDMA

Smart Direct Memory

Access

System Control

Peripherals

The SDMA is multi-channel flexible DMA engine. It helps in

maximizing system performance by off-loading the various

cores in dynamic data routing. It has the following features:

Powered by a 16-bit Instruction-Set micro-RISC engine

Multi-channel DMA supporting up to 32 time-division

multiplexed DMA channels

48 events with total flexibility to trigger any combination of

channels

Memory accesses including linear, FIFO, and 2D

addressing

Shared peripherals between ARM and SDMA

Very fast Context-Switching with 2-level priority based

preemptive multi-tasking

DMA units with auto-flush and prefetch capability

Flexible address management for DMA transfers

(increment, decrement, and no address changes on

source and destination address)

DMA ports can handle unit-directional and bi-directional

flows (copy mode)

Up to 8-word buffer for configurable burst transfers for

EMIv2.5

Support of byte-swapping and CRC calculations

Library of Scripts and API is available

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Modules List

Table 2. i.MX 6SoloX Modules List (continued)

Block Mnemonic

Block Name

Subsystem

Brief Description

SJC

System JTAG Controller System Control

Peripherals

The SJC provides JTAG interface, which complies with

JTAG TAP standards, to internal logic. The i.MX 6SoloX

processors use JTAG port for production, testing, and

system debugging. In addition, the SJC provides BSR

(Boundary Scan Register) standard support, which

complies with IEEE1149.1 and IEEE1149.6 standards.

The JTAG port must be accessible during platform initial

laboratory bring-up, for manufacturing tests and

troubleshooting, as well as for software debugging by

authorized entities. The i.MX 6SoloX SJC incorporates

three security modes for protecting against unauthorized

accesses. Modes are selected through eFUSE

configuration.

SNVS

SPDIF

Secure Non-Volatile

Storage

Security

Secure Non-Volatile Storage, including Secure Real Time

Clock, Security State Machine, Master Key Control, and

Violation/Tamper Detection and reporting.

Sony Philips Digital

Interconnect Format

Multimedia

Peripherals

A standard audio file transfer format, developed jointly by

the Sony and Phillips corporations. Has Transmitter and

Receiver functionality.

SSI1

SSI2

SSI3

I2S/SSI/AC97 Interface

Connectivity

Peripherals

The SSI is a full-duplex synchronous interface, which is

used on the AP to provide connectivity with off-chip audio

peripherals. The SSI supports a wide variety of protocols

(SSI normal, SSI network, I2S, and AC-97), bit depths (up

to 24 bits per word), and clock / frame sync options.

The SSI has two pairs of 8x24 FIFOs and hardware

support for an external DMA controller in order to minimize

its impact on system performance. The second pair of

FIFOs provides hardware interleaving of a second audio

stream that reduces CPU overhead in use cases where

two time slots are being used simultaneously.

TEMPMON

Temperature Monitor

System Control

Peripherals

The Temperature sensor IP is used for detecting die

temperature. The temperature read out does not reflect

case or ambient temperature. It reflects the temperature in

proximity of the sensor location on the die. Temperature

distribution may not be uniformly distributed, therefore the

read out value may not be the reflection of the temperature

value of the entire die.

TZASC

Trust-Zone Address

Space Controller

Security

The TZASC (TZC-380 by Arm) provides security address

region control functions required for intended application. It

is used on the path to the DRAM controller.

UART1

UART2

UART3

UART4

UART5

UART6

UART Interface

Connectivity

Peripherals

Each of the UARTv2 modules support the following serial

data transmit/receive protocols and configurations:

• 7- or 8-bit data words, 1 or 2 stop bits, programmable

parity (even, odd or none)

• Programmable baud rates up to 5 Mbps.

• 32-byte FIFO on Tx and 32 half-word FIFO on Rx

supporting auto-baud

• Option to operate as 8-pins full UART, DCE, or DTE

• UART1/6 support 8-pin, UART2/3/4/5 support 4-pin

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Modules List

Table 2. i.MX 6SoloX Modules List (continued)

Block Name Subsystem Brief Description

i.MX 6SoloX specific SoC characteristics:

Block Mnemonic

uSDHC1

uSDHC2

uSDHC3

uSDHC4

SD/MMC and SDXC

Enhanced Multi-Media

Card/SecureDigital Host

Controller

Connectivity

Peripherals

All four MMC/SD/SDIO controller IPs are identical and are

based on the uSDHC IP. They are:

• Fully compliant with MMC command/response sets and

Physical Layer as defined in the Multimedia Card

System Specification, v4.5/4.2/4.3/4.4/4.41/ including

high-capacity (size > 2 GB) cards HC MMC.

• Fully compliant with SD command/response sets and

Physical Layer as defined in the SD Memory Card

Specifications, v3.0 including high-capacity SDHC

cards up to 32 GB.

• Fully compliant with SDIO command/response sets and

interrupt/read-wait mode as defined in the SDIO Card

Specification, Part E1, v3.0.

• Conforms to the SD Host Controller Standard

Specification version 3.0.

All four ports support:

• 1-bit or 4-bit transfer mode specifications for SD and

SDIO cards up to UHS-I SDR104 mode (104 MB/s max)

• 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC

cards up to 52 MHz in both SDR and DDR modes (104

MB/s max)

• All ports can work with 1.8 V and 3.3 V cards. Each port

is placed on a separate power domain.

USB

Universal Serial Bus 2.0 Connectivity

Peripherals

USBOH3 contains:

• Two high-speed OTG 2.0 modules with integrated HS

USB PHYs

• One high-speed Host module connected to HSIC USB

port

WDOG1

WDOG3

Watch Dog

Timer Peripherals The Watch Dog Timer supports two comparison points

during each counting period. Each of the comparison

points is configurable to evoke an interrupt to the Arm core,

and a second point evokes an external event on the WDOG

line.

WDOG2

(TZ)

Watch Dog (TrustZone)

Timer Peripherals The TrustZone Watchdog (TZ WDOG) timer module

protects against TrustZone starvation by providing a

method of escaping normal mode and forcing a switch to

the TZ mode. TZ starvation is a situation where the normal

OS prevents switching to the TZ mode. Such situation is

undesirable as it can compromise the system’s security.

Once the TZ WDOG module is activated, it must be

serviced by TZ software on a periodic basis. If servicing

does not take place, the timer times out. Upon a time-out,

the TZ WDOG asserts a TZ mapped interrupt that forces

switching to the TZ mode. If it is still not served, the TZ

WDOG asserts a security violation signal to the CSU. The

TZ WDOG module cannot be programmed or deactivated

by a normal mode software.

XTALOSC

Crystal Oscillator

Interface

Clocks, Resets,

and Power Control provide system clocks.

The XTALOSC module connects to an external crystal to

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Modules List

3.1

Special Signal Considerations

Table 3 lists special signal considerations for the i.MX 6SoloX processors. The signal names are listed in

alphabetical order.

The package contact assignments can be found in Section 6, “Package Information and Contact

Assignments.” Signal descriptions are provided in the i.MX 6SoloX Applications Processor Reference

Manual (IMX6SXRM).

Table 3. Special Signal Considerations

Signal Name

Remarks

CCM_CLK1_P/

CCM_CLK1_N

CCM_CLK2

Two general purpose differential high speed clock Input/outputs are provided.

Any or both of them could be used:

• To feed external reference clock to the PLLs and further to the modules inside SoC, for example

as alternate reference clock for PCIe, Video/Audio interfaces, etc.

• To output internal SoC clock to be used outside the SoC as either reference clock or as a

functional clock for peripherals

See the i.MX 6SoloX Applications Processor Reference Manual (IMX6SXRM) for details on the

respective clock trees.

The clock inputs/outputs are LVDS differential pairs compatible with TIA/EIA-644 standard, the

frequency range supported is 0...600 MHz.

Alternatively one may use single ended signal to drive CLKx_P input. In this case corresponding

CLKx_N input should be tied to the constant voltage level equal 1/2 of the input signal swing.

Termination should be provided in case of high frequency signals.

See LVDS pad electrical specification for further details.

After initialization, the CLKx inputs/outputs could be disabled (if not used). If unused any or both of

the CLKx_N/P pairs may be left unconnected.

RTC_XTALI/RTC_XTALO If the user needs to configure RTC_XTALI and RTC_XTALO as an RTC oscillator, a 32.768 kHz

crystal (≤100 kΩ ESR, 10 pF load), should be connected between RTC_XTALI and RTC_XTALO.

Keep in mind the capacitors implemented on either side of the crystal are about twice the crystal

load capacitor. To hit the exact oscillation frequency, the board capacitors need to be reduced to

account for board and chip parasitics. The integrated oscillation amplifier is self biasing, but

relatively weak. Care must be taken to limit parasitic leakage from RTC_XTALI and RTC_XTALO

to either power or ground (>100 MΩ). This will debias the amplifier and cause a reduction of startup

margin. Typically RTC_XTALI and RTC_XTALO should bias to approximately 0.5 V.

If it is desired to feed an external low frequency clock into RTC_XTALI the RTC_XTALO pin should

be left unconnected or driven with a complimentary signal. The logic level of this forcing clock

should not exceed VDD_SNVS_CAP level and the frequency should be <100 kHz under typical

conditions.

When a high accuracy real time clock is not required, the system can use an internal low frequency

ring oscillator. It is recommended to connect RTC_XTALI to GND and leave RTC_XTALO

unconnected.

XTALI/XTALO

A 24.0 MHz crystal should be connected between XTALI and XTALO. NXP BSP (board support

package) software requires 24 MHz on XTALI/XTALO. For details on crystal selection, see the

“i.MX 6SoloX Design Checklist” chapter of the Hardware Development Guide for i.MX 6SoloX

Applications Processors (IMX6SXHDG), as well as the engineering bulletin i.MX 6 Series Crystal

Drive (24 MHz) (EB830).

The crystal can be eliminated if an external 24 MHz oscillator is available in the system. In this

case, XTALI must be directly driven by the external oscillator and XTALO is left unconnected.

If this clock is used as a reference for USB and PCIe, then there are strict frequency tolerance and

jitter requirements. See OSC24M chapter and relevant interface specifications chapters for details.

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Modules List

Table 3. Special Signal Considerations (continued)

Remarks

Signal Name

DRAM_VREF

When using DDR_VREF with DDR I/O, the nominal reference voltage must be half of the

NVCC_DRAM supply. The user must tie DDR_VREF to a precision external resistor divider. Use a

1 kΩ 0.5% resistor to GND and a 1 kΩ 0.5% resistor to NVCC_DRAM. Shunt the resistor from

DRAM_VREF to ground with a closely mounted 0.1 μF capacitor.

To reduce supply current, a pair of 1.5 kΩ 0.1% resistors can be used. Using resistors with

recommended tolerances ensures the 2% DDR_VREF tolerance (per the DDR3 specification) is

maintained when four DDR3 ICs plus the i.MX 6SoloX are drawing current on the resistor divider.

ZQPAD

DRAM calibration resistor 240 Ω 1% used as reference during DRAM output buffer driver

calibration should be connected between this pad and GND.

NVCC_LVDS

On the 19 x 19 package, this ball can be shorted to VDD_HIGH_CAP on the circuit board. On the

17 x 17 and 14 x 14 packages, NVCC_LVDS is internally connected to VDD_HIGH_CAP.

GPANAIO

Analog output for NXP use only. This output must always be left unconnected.

JTAG_nnnn

The JTAG interface is summarized in Table 4. Use of external resistors is unnecessary. However,

if external resistors are used, the user must ensure that the on-chip pull-up/down configuration is

followed. For example, do not use an external pull down on an input that has on-chip pull-up.

JTAG_TDO is configured with a keeper circuit such that the floating condition is eliminated if an

external pull resistor is not present. An external pull resistor on JTAG_TDO is detrimental and

should be avoided.

JTAG_MOD is referenced as SJC_MOD in the i.MX 6SoloX Applications Processor Reference

Manual (IMX6SXRM). Both names refer to the same signal. JTAG_MOD must be externally

connected to GND for normal operation. Termination to GND through an external pull-down resistor

(such as 1 kΩ) is allowed. JTAG_MOD set to high configures the JTAG interface to mode compliant

with IEEE1149.1 standard. JTAG_MOD set to low configures the JTAG interface for common

software debug adding all the system TAPs to the chain.

NC

These signals are No Connect (NC) and should be left unconnected by the user.

This cold reset negative logic input resets all modules and logic in the IC.

POR_B

ONOFF

ONOFF can be configured in debounce, off to on time, and max timeout configurations. The

debounce and off to on time configurations supports 0, 50, 100 and 500 msecs. Debounce is used

to generate the power off interrupt. While in the ON state, if ONOFF button is pressed longer than

the debounce time, the power off interrupt is generated. Off to on time supports the time it takes to

request power on after a configured button press time has been reached. While in the OFF state,

if ONOFF button is pressed longer than the off to on time, the state will transition from OFF to ON.

Max timeout configuration supports 5, 10, 15 secs and disable. Max timeout configuration supports

the time it takes to request power down after ONOFF button has been pressed for the defined time.

TEST_MODE

PCIE_REXT

TEST_MODE is for NXP factory use. The user must tie this pin directly to GND.

The impedance calibration process requires connection of reference resistor 200 Ω 1% precision

resistor on PCIE_REXT pad to ground.

Table 4. JTAG Controller Interface Summary

JTAG

I/O Type

On-chip Termination

JTAG_TCK

JTAG_TMS

JTAG_TDI

Input

47 kΩ pull-up

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Electrical Characteristics

JTAG

Table 4. JTAG Controller Interface Summary (continued)

I/O Type

On-chip Termination

JTAG_TDO

JTAG_TRSTB

JTAG_MOD

3-state output

Input

Keeper

47 kΩ pull-up

100 kΩ pull-up

Input

3.2

Recommended Connections for Unused Analog Interfaces

The recommended connections for unused analog interfaces can be found in the section, “Unused analog

interfaces,” of the Hardware Development Guide for i.MX 6SoloX Applications Processors

(IMX6SXHDG).

4 Electrical Characteristics

This section provides the device and module-level electrical characteristics for the i.MX 6SoloX

processors.

4.1

Chip-Level Conditions

This section provides the device-level electrical characteristics for the IC. See Table 5 for a quick reference

to the individual tables and sections.

Table 5. i.MX 6SoloX Chip-Level Conditions

For these characteristics, …

Absolute Maximum Ratings

Topic appears …

on page 21

on page 23

on page 25

on page 28

on page 29

on page 30

on page 31

on page 32

Thermal Resistance

Operating Ranges

External Clock Sources

Maximum Supply Currents

Low Power Mode Supply Currents

USB PHY Current Consumption

PCIe 2.0 Power Consumption

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Electrical Characteristics

4.1.1

Absolute Maximum Ratings

CAUTION

Stresses beyond those listed under Table 6 may cause permanent damage to

the device. These are stress ratings only. Functional operation of the device

at these or any other conditions beyond those indicated under

“recommended operating conditions” is not implied. Exposure to

absolute-maximum-rated conditions for extended periods may affect device

reliability.

Table 6 shows the absolute maximum operating ratings.

Table 6. Absolute Maximum Ratings

Symbol¹

Parameter Description

Min

Max

Unit

Core Supplies Input Voltage (LDO Enabled)

VDDSOC_IN

VDDARM_IN

-0.3

1.6

V

Core Supplies Input Voltage (LDO Bypass)

VDDSOC_IN

VDDARM_IN

-0.3

1.4

3.7

V

VDD_HIGH_IN Supply voltage (LDO

Enabled)

VDD_HIGH_IN

VDD_HIGH_IN Supply voltage (LDO

Bypass)

VDD_HIGH_IN

2.85

1.4

Core Supplies Output Voltage (LDO

Enabled)

VDD_ARM_CAP

VDD_SOC_CAP

VDD_HIGH_CAP LDO Output Supply

voltage

VDD_HIGH_CAP

2.6

Supply Input Voltage to Secure Non-Volatile

Storage and Real Time Clock

VDD_SNVS_IN

3.6

USB VBUS Supply

USB_OTG_VBUS

—

5.6

V

Input voltage on USB signals (non-VBUS)

USB_OTG_DP,

USB_OTG_DN,

USB_H1_DP,

-0.3

3.63

USB_H1_DN,

USB_OTG_CHD_B

Supply for the USB HSIC interface

IO Supply for DDR Interface

Supply for DDR pre-drivers

NVCC_USB_H

NVCC_DRAM

—

2.85

1.975²

2.85

V

-0.4

-0.3

-0.5

NVCC_DRAM_2P5

NVCC_RGMII

IO Supply for RGMII Interface

3.7

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Electrical Characteristics

Table 6. Absolute Maximum Ratings (continued)

Parameter Description

Symbol¹

Min

Max

Unit

IO Supply for GPIO Type Pins

NVCC_CSI

NVCC_ENET

NVCC_HIGH

NVCC_KEY

NVCC_GPIO

NVCC_LCD

NVCC_LOW

NVCC_NAND

NVCC_QSPI

NVCC_SD

-0.5

3.7

V

NVCC_JTAG

IO Supply for LVDS

NVCC_LVDS

Supplies denoted as GPIO supplies

PCIE_VP

-0.3

—

2.85

2.9

V

IO Supply for MLB

VP Supplies for PCIe

VPH Supplies for PCIe

Supply for PCIe PHY

Supply for ADC 3P3V

3.3V Supply for analog circuitry

1.4

PCIE_VPH

2.85

PCIE_VPTX

1.4

VDDA_ADC_3P3

VDD_AFE_3P3

V_in/V_out

3.7

—

3.7

Input/Output Voltage Range (non-DDR

pins)

-0.5

OVDD+0.3³

Input/Output Voltage Range (DDR pins)

V_in/V_out

-0.5

—

OVDD³+0.4²

2000

V

ESD damage Immunity: Human Body

Model (HBM)

V_esd_HBM

ESD damage Immunity: Charge Device

Model (CDM)

V_esd_CDM

—

500

150

V

Storage Temperature Range

TSTORAGE

-40

°C

1

2

3

Not all of the supplies shown exist on all packages. See the package ball maps for details on which supplies are used on each

package.

The absolute maximum voltage includes an allowance for 400 mV of overshoot on the IO pins. Per JEDEC standards, the

allowed signal overshoot must be de-rated if NVCC_DRAM exceeds 1.575V.

OVDD is the I/O supply voltage.

4.1.2

Thermal Resistance

NOTE

Per JEDEC JESD51-2, the intent of thermal resistance measurements is

solely for a thermal performance comparison of one package to another in a

standardized environment. This methodology is not meant to and will not

predict the performance of a package in an application-specific

environment.

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Electrical Characteristics

4.1.2.1

19x19 mm (VM) Package Thermal Resistance

Table 7 displays the 19x19 mm (VM) package thermal resistance data.

Table 7. 19x19 mm (VM) Package Thermal Resistance Data

Rating

Test Conditions

Symbol

Value

Unit

Notes

Junction to Ambient Natural Single-layer board (1s)

Convection

R_θJA

40.6

^oC/W

1,2

Junction to Ambient Natural Four-layer board (2s2p)

Convection

R_θJA

R_θJMA

28.0

32.1

23.0

^oC/W

1,2,3

1,3

Junction to Ambient (@ 200 Single layer board (1s)

ft/min)

1,3

Junction to Ambient (@ 200 Four layer board (2s2p)

ft/min)

Junction to Board

—

R_θJB

R_θJC

Ψ_JT

17.9

7.8

2

^oC/W

4

5

6

7

Junction to Case

Junction to Package Top

Natural Convection

Junction to Package Bottom Natural Convection

Ψ_JB

7.5

1

Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

2

3

4

Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.

Per JEDEC JESD51-6 with the board horizontal.

Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on

the top surface of the board near the package.

5

6

7

Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method

1012.1).

Thermal characterization parameter indicating the temperature difference between package top and the junction temperature

per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.

Thermal characterization parameter indicating the temperature difference between package bottom center and the junction

temperature per JEDEC JESD51-12. When Greek letters are not available, the thermal characterization parameter is written

as Psi-JB.

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Electrical Characteristics

4.1.2.2

17x17 mm NP (VO) and 17x17 mm WP (VN) Package Thermal Resistance

Table 8 displays the 17x17 mm NP (VO) and 17x17 mm WP (VN) package thermal resistance data.

Table 8. 17x17 mm NP (VO) and 17x17 mm WP (VN) Thermal Resistance Data

Rating

Test Conditions

Symbol

Value

Unit

Notes

Junction to Ambient Natural Single-layer board (1s)

Convection

R_θJA

44.4

^oC/W

1,2

Junction to Ambient Natural Four-layer board (2s2p)

Convection

R_θJA

R_θJMA

27.4

35.2

22.5

^oC/W

1,2,3

1,3

Junction to Ambient (@ 200 Single layer board (1s)

ft/min)

1,3

Junction to Ambient (@ 200 Four layer board (2s2p)

ft/min)

Junction to Board

—

R_θJB

R_θJC

Ψ_JT

13.2

8.4

2

^oC/W

4

5

6

7

Junction to Case

Junction to Package Top

Natural Convection

Junction to Package Bottom Natural Convection

Ψ_JB

8.6

1

Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

2

3

4

Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.

Per JEDEC JESD51-6 with the board horizontal.

Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on

the top surface of the board near the package.

5

6

7

Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method

1012.1).

Thermal characterization parameter indicating the temperature difference between package top and the junction temperature

per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.

Thermal characterization parameter indicating the temperature difference between package bottom center and the junction

temperature per JEDEC JESD51-12. When Greek letters are not available, the thermal characterization parameter is written

as Psi-JB.

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Electrical Characteristics

4.1.3

Operating Ranges

Table 9 provides the operating ranges of the i.MX 6SoloX processors. For details on the chip's power

structure, see the “Power Management Unit (PMU)” chapter of the i.MX 6SoloX Applications Processor

Reference Manual (IMX6SXRM).

NOTE

Applying the maximum power supply voltage results in maximum power

consumption and heat generation. NXP recommends a voltage set point =

(Vmin + the supply tolerance). This results in an optimized power/speed

ratio.

Table 9. Operating Ranges

Parameter

Description

Operating

Conditions

Symbol

Min

Typ

Max¹Unit

Notes

Power Supply Operating Ranges

Run Mode:

LDO enabled

VDD_ARM_IN

A9 core at

792 MHz

1.275

1.175

1.075

1.15

—

1.5

1.3

1.5

V

VDDARM_IN must be 125mV higher

than the LDO Output Set Point

(VDD_ARM_CAP) for correct supply

voltage regulation.

A9 core at

396 MHz

A9 core at

198 MHz

VDD_ARM_CAP

A9 core at

792 MHz

Output voltage must be set to the

following rule:

VDD_ARM_CAP – VDD_SOC_CAP <

+50 mV

A9 core at

396 MHz

1.05

A9 core at

198 MHz

0.95

VDD_SOC_IN

VDD_SOC_CAP

VDD_ARM_IN

—

1.275

VDDSOC_IN must be 125 mV higher

than the LDO Output Set Point

(VDD_SOC_CAP) for correct supply

voltage regulation.

1.15

—

1.3

V

Output voltage must be set to the

following rule:

VDD_ARM_CAP – VDD_SOC_CAP <

+50 mV

Run Mode:

LDO

bypassed

A9 core at

792 MHz

1.15

1.05

0.95

1.15

—

1.3

V

A9 core at

396 MHz

A9 core at

198 MHz

VDD_SOC_IN

—

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Electrical Characteristics

Parameter

Table 9. Operating Ranges (continued)

Operating

Symbol

Min

Typ

Max¹Unit

Notes

Description

Conditions

Standby/DSM

Mode

VDD_ARM_IN

VDD_SOC_IN

VDD_HIGH_IN

—

0.9

1.05

2.8

—

1.3

3.6

V

See Table 13 and Table 14.

VDD_HIGH

internal

regulator

Must match the range of voltages that

the rechargeable backup battery

supports.

Backup

batterysupply

range

VDD_SNVS_IN

—

2.4

4.4

—

3.6

5.5

V

Could be combined with VDD_HIGH_IN

if the system does not require real time

and other data on off state.

USB supply

voltages

USB_OTG1_VBUS/

USB_OTG2_VBUS

—

DDR I/O

supply

NVCC_DRAM

LPDDR2

DDR3L

DDR3

1.14

1.283

1.425

1.15

1.2

1.35

1.5

1.3

1.45

1.575

1.3

V

—

HSIC I/O

supply

NVCC_USB_H

1.2 V

operation

1.2

IOMUXC_SW_PAD_CTL_PAD_USB_H

_DATA[DDR_SEL] = ‘10’

IOMUXC_SW_PAD_CTL_PAD_USB_H

_STROBE[DDR_SEL] = ‘10’

NVCC_USB_H should be grounded

through a 10k resistor if the HSIC pins

are not used.

1.5 V

operation

1.425

1.62

2.25

1.5

1.8

2.5

1.575

1.98

2.75

V

IOMUXC_SW_PAD_CTL_PAD_USB_H

_DATA[DDR_SEL] = ‘11’

IOMUXC_SW_PAD_CTL_PAD_USB_H

_STROBE[DDR_SEL] = ‘11’

1.8 V

operation

NVCC_USB_H should be grounded

through a 10k resistor if the HSIC pins

are not used.

2.5 V

operation

RGMII I/O

supply

NVCC_RGMII1

NVCC_RGMII2

1.5 V mode

1.8 V mode

2.5 V mode

3.3 V mode

1.43

1.7

1.5

1.8

2.5

1.58

1.9

V

—

2.25

3.0

2.625

3.15/3.3 3.6

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Electrical Characteristics

Notes

Table 9. Operating Ranges (continued)

Operating

Parameter

Description

Symbol

Min

Typ

Max¹Unit

Conditions

GPIO

supplies

NVCC_CSI

NVCC_ENET

NVCC_GPIO

NVCC_HIGH

NVCC_KEY

NVCC_LCD1

NVCC_LOW

NVCC_NAND

NVCC_QSPI

NVCC_SD1

NVCC_SD2

NVCC_SD4

NVCC_JTAG

—

1.65

1.8

2.8

3.15

3.6

V

All digital I/O supplies (NVCC_xxxx)

must be powered (unless otherwise

specified in this data sheet) under

normal conditions whether the

associated I/O pins are in use or not and

the associated IO pins need to have a

pull-up or pull-down resistor applied to

limit any floating gate current.

NVCC_LVDS

—

2.25

2.5

2.75

V

NVCC_DRAM_2P5

PCIe supplies

PCIE_VP

PCIE_VPH

PCIE_VPTX

—

1.023

2.325

1.023

3

1.1

2.5

1.21

2.75

1.21

3.6

V

—

1.1

A/D converter VDDA_ADC_3P3

supply

3.15

VDDA_ADC_3P3mustbepoweredeven

if the ADC is not used. VDDA_ADC_3P3

should not be powered when the other

SoC supplies (except VDD_SNVS_IN)

are off.

Temperature Operating Ranges

Industrial –40 105

Junction

temperature

T_J

—

°C See the application note, i.MX 6SoloX

Product Lifetime Usage Estimates

(AN5062) for information on product

lifetime (power-on years) for this

processor.

1

Applying the maximum voltage results in maximum power consumption and heat generation. NXP recommends a voltage set

point = (V_min+ the supply tolerance). This results in an optimized power/speed ratio.

Table 10 shows on-chip LDO regulators that can supply on-chip loads.

1

Table 10. On-Chip LDOs and their On-Chip Loads

Voltage Source

Load

Comment

VDD_HIGH_CAP

NVCC_LVDS

NVCC_DRAM_2P5

PCIE_VPH

Board-level connection to VDD_HIGH_CAP

1

On-chip LDOs are designed to supply i.MX6 loads and must not be used to supply external loads.

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Electrical Characteristics

4.1.4

External Clock Sources

Each i.MX 6SoloX processor has two external input system clocks: a low frequency (RTC_XTALI) and a

high frequency (XTALI).

The RTC_XTALI is used for low-frequency functions. It supplies the clock for wake-up circuit,

power-down real time clock operation, and slow system and watch-dog counters. The clock input can be

connected to either external oscillator or a crystal using an internal oscillator amplifier. Additionally, there

is an internal ring oscillator, which can be used instead of the RTC_XTALI if accuracy is not important.

The system clock input XTALI is used to generate the main system clock. It supplies the PLLs and other

peripherals. The system clock input can be connected to either external oscillator or a crystal using an

internal oscillator amplifier.

CAUTION

The internal RTC oscillator does not provide an accurate frequency and is

affected by process, voltage, and temperature variations. NXP strongly

recommends using an external crystal as the RTC_XTALI reference. If the

internal oscillator is used, careful consideration must be given to the timing

implications on all of the SoC modules dependent on this clock.

Table 11 shows the interface frequency requirements.

Table 11. External Input Clock Frequency

Parameter Description

Symbol

Min

Typ

Max

Unit

RTC_XTALI Oscillator^1,2

XTALI Oscillator^2,4

f_ckil

f_xtal

—

32.768³/32.0

24

—

kHz

MHz

1

External oscillator or a crystal with internal oscillator amplifier.

2

The required frequency stability of this clock source is application dependent. For recommendations, see the Hardware

Development Guide for i.MX 6SoloX Applications Processors (IMX6XHDG).

3

4

Recommended nominal frequency 32.768 kHz.

External oscillator or a fundamental frequency crystal with internal oscillator amplifier.

The typical values shown in Table 11 are required for use with NXP BSPs to ensure precise time

keeping and USB operation. For RTC_XTALI operation, two clock sources are available.

•

On-chip 40 kHz ring oscillator—this clock source has the following characteristics:

— Approximately 25 µA more Idd than crystal oscillator

— Approximately 50ꢀ tolerance

— No external component required

— Starts up quicker than 32 kHz crystal oscillator

External crystal oscillator with on-chip support circuit:

•

— At power up, ring oscillator is utilized. After crystal oscillator is stable, the clock circuit

switches over to the crystal oscillator automatically.

— Higher accuracy than ring oscillator

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Electrical Characteristics

— If no external crystal is present, then the ring oscillator is utilized

The decision of choosing a clock source should be taken based on real-time clock use and precision

timeout.

4.1.5

Maximum Supply Currents

The data shown in Table 12 represent a use case designed specifically to show the maximum current

consumption possible. All cores are running at the defined maximum frequency and are limited to L1

cache accesses only to ensure no pipeline stalls. Although a valid condition, it would have a very limited

practical use case, if at all, and be limited to an extremely low duty cycle unless the intention was to

specifically show the worst case power consumption.

Table 12. Maximum Supply Currents

Power Line

Conditions

Max Current

Unit

VDD_ARM_IN

996 MHz Arm clock based on

Power Virus operation

1100

mA

VDD_SOC_IN

VDD_HIGH_IN

VDD_SNVS_IN

996 MHz Arm clock

1260

125¹

400²

50³

mA

μA

—

USB_OTG1_VBUS/USB_OTG2_VBUS (LDO_USB)

mA

VDDA_ADC_3P3

1.5

Primary Interface (IO) Supplies

NVCC_DRAM

NVCC_DRAM_2P5

NVCC_ENET

NVCC_LCD1

NVCC_GPIO

NVCC_CSI

—

(See Note⁴)

—

Use Maximum IO equation ⁵

N=10

N=29

N=14

N=12

N=16

N=6

NVCC_QSPI

NVCC_JTAG

NVCC_RGMII1

NVCC_RGMII2

NVCC_SD1

N=12

N=6

NVCC_SD2

N=6

NVCC_SD4

N=11

N=16

N=10

NVCC_NAND

NVCC_KEY

NVCC_LOW

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Electrical Characteristics

Table 12. Maximum Supply Currents (continued)

Conditions

Power Line

Max Current

Unit

NVCC_HIGH

N=10

N=2

Use Maximum IO equation ⁵

—

NVCC_USB_H

1

The actual maximum current drawn from VDD_HIGH_IN will be as shown plus any additional current drawn from the

VDD_HIGH_CAP outputs, depending upon actual application configuration (for example, NVCC_LVDS).

2

Under normal operating conditions, the maximum current on VDD_SNVS_IN is shown Table 12. The maximum

VDD_SNVS_IN current may be higher depending on specific operating configurations, such as BOOT_MODE[1:0] not equal

to 00, or use of the Tamper feature. During initial power on, VDD_SNVS_IN can draw up to 1 mA if the supply is capable of

sourcing that current. If less than 1 mA is available, the VDD_SNVS_CAP charge time will increase.

3

4

This is the maximum current per active USB physical interface.

The DRAM power consumption is dependent on several factors such as external signal termination. DRAM power calculators

are typically available from memory vendors which take into account factors such as signal termination.

See the i.MX 6SoloX Power Consumption Measurement Application Note (AN5050) for examples of DRAM power

consumption during specific use case scenarios.

5

General equation for estimated, maximum power consumption of an IO power supply:

Imax = N x C x V x (0.5 x F)

Where:

N—Number of IO pins supplied by the power line

C—Equivalent external capacitive load

V—IO voltage

(0.5 xF)—Data change rate. Up to 0.5 of the clock rate (F)

In this equation, Imax is in Amps, C in Farads, V in Volts, and F in Hertz.

4.1.6

Low Power Mode Supply Currents

Table 13 and Table 14 show the current core consumption (not including I/O) of i.MX 6SoloX processors

in selected low power modes.

Table 13. Low Power Mode Current and Power Consumption (LDO Bypass Mode)

Mode

Test Conditions

Supply

Typical¹Units

System Idle

See the Power Modes table in the Clock and Power Management VDDARM_IN (1.15 V)

7.469

8.436

3.376

29.430

0.001

2.337

0.404

4.022

mA

chapter of the i.MX 6SoloX Applications Processor Reference

Manual (IMX6SXRM) for the definition of this mode.

VDDSOC_IN (1.15 V)

VDDHIGH_IN (3.3 V)

Total

mW

mA

Low Power Idle See the Power Modes table in the Clock and Power Management VDDARM_IN (1.15 V)

chapter of the i.MX 6SoloX Applications Processor Reference

Manual (IMX6SXRM) for the definition of this mode.

VDDSOC_IN (1.15 V)

SOC LDO must be bypassed.

Bandgap is disabled.

VDDHIGH_IN (3.3 V)

Total

mW

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Electrical Characteristics

Table 13. Low Power Mode Current and Power Consumption (LDO Bypass Mode) (continued)

Mode

Test Conditions

Supply

Typical¹Units

Suspend/

Deep Sleep

mode

See the Power Modes table in the Clock and Power Management VDD_ARM_IN (0.9 V)

0.001

mA

chapter of the i.MX 6SoloX Applications Processor Reference

VDD_SOC_IN (1.05 V) 1.005

Manual (IMX6SXRM) for the definition of this mode.

(DSM)

VDDHIGH_IN (3.3 V)

Total

0.034

2.067

41

mW

μA

SNVS

SNVS power domain powered.

All other power domains are off.

VDD_SNVS_IN (2.8 V)

Total

0.115

mW

1

Typical process material in fab.

Table 14. Low Power Mode Current and Power Consumption (LDO Enabled Mode)

Mode

Test Conditions

Supply

Typical¹Units

Low Power Idle See the Power Modes table in the Clock and Power Management

chapter of the i.MX 6SoloX Applications Processor Reference

Manual (IMX6SXRM) for the definition of this mode.

SOC LDO is enabled.

VDDARM_IN (1.3V)

VDDSOC_IN (1.3V)

0.008

2.343

mA

VDDHIGH_IN (3.3V) 3.376

Bandgap is enabled.

Total

14.196 mW

Suspend/

Deep Sleep

mode

See the Power Modes table in the Clock and Power Management

chapter of the i.MX 6SoloX Applications Processor Reference

Manual (IMX6SXRM) for the definition of this mode.

VDDARM_IN (1.3V)

VDDSOC_IN (1.3V)

0.033

1.3

mA

(DSM

VDDHIGH_IN (3.3V) 0.034

Total 2.231

mW

1

Typical process material in fab.

4.1.7

USB PHY Current Consumption

Power Down Mode

4.1.7.1

In power down mode, everything is powered down, including the USB_VBUS valid detectors in typical

condition. Table 15 shows the USB interface current consumption in power down mode.

Table 15. USB PHY Current Consumption in Power Down Mode

VDD_USB_CAP (3.0 V)

VDD_HIGH_CAP (2.5 V)

NVCC_PLL (1.1 V)

Current

5.1 μA

1.7 μA

<0.5 μA

NOTE

The currents on the VDD_HIGH_CAP and VDD_USB_CAP were

identified to be the voltage divider circuits in the USB-specific level shifters.

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4.1.8

PCIe 2.0 Power Consumption

Table 16 provides PCIe PHY currents under certain transmit operating modes.

Table 16. PCIe PHY Current Drain

Mode

Test Conditions

Supply

Max Current

Unit

P0: Normal Operation

5G Operations

2.5G Operations

5G Operations

2.5G Operations

—

PCIE_VPH (2.5 V)

21

20

18

12

mA

P0s: Low Recovery Time

Latency, Power Saving State

mA

P1: Longer Recovery Time

Latency, Lower Power State

mA

Power Down

—

PCIE_VPH (2.5 V)

0.36

4.2

Power Supplies Requirements and Restrictions

The system design must comply with power-up sequence, power-down sequence, and steady state

guidelines as described in this section to guarantee the reliable operation of the device. Any deviation

from these sequences may result in the following situations:

•

Excessive current during power-up phase

Prevention of the device from booting

Irreversible damage to the processor (worst-case scenario)

4.2.1

Power-Up Sequence

The restrictions that follow must be observed:

•

VDD_SNVS_IN supply must be turned on before any other power supply or be connected

(shorted) with VDD_HIGH_IN supply.

If a coin cell is used to power VDD_SNVS_IN, then ensure that it is connected before any other

supply is switched on.

When the SRC_POR_B signal is used to control the processor POR, then SRC_POR_B must be

immediately asserted at power-up and remain asserted until the VDD_ARM_CAP and

VDD_SOC_CAP supplies are stable. VDD_ARM_IN and VDD_SOC_IN may be applied in either

order with no restrictions.

NOTE

Ensure there is no back voltage (leakage) from any supply on the board

towards the 3.3 V supply (for example, from the external components that

use both the 1.8 V and 3.3 V supplies).

NOTE

USB_OTG1_VBUS and USB_OTG2_VBUS are not part of the power

supply sequence and may be powered at any time.

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4.2.2

Power-Down Sequence

There are no special restrictions for the i.MX 6SoloX IC.

4.2.3

Power Supplies Usage

All I/O pins must not be externally driven while the I/O power supply for the pin (NVCC_xxx) is OFF.

This can cause internal latch-up and malfunctions due to reverse current flows. For information about I/O

power supply of each pin, see “Power Rail” columns in pin list tables of Section 6, “Package Information

and Contact Assignments.”

4.3

Integrated LDO Voltage Regulator Parameters

Various internal supplies can be powered ON from internal LDO voltage regulators. All the supply pins

named *_CAP must be connected to external capacitors. The onboard LDOs are intended for internal use

only and must not be used to power any external circuitry. See the i.MX 6SoloX Applications Processor

Reference Manual (IMX6SXRM) for details on the power tree scheme.

NOTE

The *_CAP signals must not be powered externally. These signals are

intended for internal LDO operation only.

4.3.1

Digital Regulators (LDO_ARM, LDO_SOC, LDO_PCIE)

There are three digital LDO regulators (“Digital”, because of the logic loads that they drive, not because

of their construction). The advantages of the regulators are to reduce the input supply variation because of

their input supply ripple rejection and their on-die trimming. This translates into more stable voltage for

the on-chip logic.

These regulators have two basic modes:

•

Power Gate. The regulation FET is switched fully off limiting the current draw from the supply.

The analog part of the regulator is powered down here limiting the power consumption.

•

Analog regulation mode. The regulation FET is controlled such that the output voltage of the

regulator equals the programmed target voltage. The target voltage is fully programmable in 25 mV

steps.

For additional information, see the i.MX 6SoloX Applications Processor Reference Manual

(IMX6SXRM).

4.3.2

Regulators for Analog Modules

LDO_1P1

4.3.2.1

The LDO_1P1 regulator implements a programmable linear-regulator function from VDD_HIGH_IN (see

Table 9 for minimum and maximum input requirements). Typical Programming Operating Range is 1.0 V

to 1.2 V with the nominal default setting as 1.1 V. The LDO_1P1 supplies the USB Phy, LVDS Phy, and

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PLLs. A programmable brown-out detector is included in the regulator that can be used by the system to

determine when the load capability of the regulator is being exceeded to take the necessary steps.

Active-pull-down can also be enabled for systems requiring this feature.

For information on external capacitor requirements for this regulator, see the Hardware Development

Guide for i.MX 6SoloX Applications Processors (IMX6XHDG).

For additional information, see the i.MX 6SoloX Applications Processor Reference Manual

(IMX6SXRM).

4.3.2.2

LDO_2P5

The LDO_2P5 module implements a programmable linear-regulator function from VDD_HIGH_IN (see

Table 9 for minimum and maximum input requirements). Typical Programming Operating Range is

2.25 V to 2.75 V with the nominal default setting as 2.5 V. LDO_2P5 supplies the DDR IOs, USB Phy,

LVDS Phy, E-fuse module, and PLLs. A programmable brown-out detector is included in the regulator that

can be used by the system to determine when the load capability of the regulator is being exceeded, to take

the necessary steps. Active-pull-down can also be enabled for systems requiring this feature. An alternate

self-biased low-precision weak-regulator is included that can be enabled for applications needing to keep

the output voltage alive during low-power modes where the main regulator driver and its associated global

bandgap reference module are disabled. The output of the weak-regulator is not programmable and is a

function of the input supply as well as the load current. Typically, with a 3 V input supply the

weak-regulator output is 2.525 V and its output impedance is approximately 40 Ω.

For information on external capacitor requirements for this regulator, see the Hardware Development

Guide for i.MX 6SoloX Applications Processors (IMX6XHDG).

For additional information, see the i.MX 6SoloX Applications Processor Reference Manual

(IMX6SXRM).

4.3.2.3

LDO_USB

The LDO_USB module implements a programmable linear-regulator function from the

USB_OTG1_VBUS and USB_OTG2_VBUS voltages (4.4 V–5.5 V) to produce a nominal 3.0 V output

voltage. A programmable brown-out detector is included in the regulator that can be used by the system to

determine when the load capability of the regulator is being exceeded, to take the necessary steps. This

regulator has a built in power-mux that allows the user to select to run the regulator from either

USB_VBUS supply, when both are present. If only one of the USB_VBUS voltages is present, then, the

regulator automatically selects this supply. Current limit is also included to help the system meet in-rush

current targets.

For information on external capacitor requirements for this regulator, see the Hardware Development

Guide for i.MX 6SoloX Applications Processors (IMX6XHDG).

For additional information, see the i.MX 6SoloX Applications Processor Reference Manual

(IMX6SXRM).

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4.4

PLL Electrical Characteristics

4.4.1

Audio/Video PLL Electrical Parameters

Table 17. Audio/Video PLL Electrical Parameters

Parameter

Value

Clock output range

Reference clock

Lock time

650 MHz ~1.3 GHz

24 MHz

<11250 reference cycles

4.4.2

4.4.3

4.4.4

528 MHz PLL

Table 18. 528 MHz PLL Electrical Parameters

Parameter

Value

Clock output range

Reference clock

Lock time

528 MHz PLL output

24 MHz

<11250 reference cycles

Ethernet PLL

Table 19. Ethernet PLL Electrical Parameters

Parameter

Value

Clock output range

Reference clock

Lock time

500 MHz

24 MHz

<11250 reference cycles

480 MHz PLL

Table 20. 480 MHz PLL Electrical Parameters

Parameter

Value

Clock output range

Reference clock

Lock time

480 MHz PLL output

24 MHz

<383 reference cycles

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4.4.5

Arm PLL

Table 21. Arm PLL Electrical Parameters

Parameter

Value

Clock output range

Reference clock

Lock time

650 MHz ~ 1.3 GHz

24 MHz

<2250 reference cycles

4.5

On-Chip Oscillators

OSC24M

4.5.1

This block implements an amplifier that when combined with a suitable quartz crystal and external load

capacitors implements an oscillator. The oscillator is powered from NVCC_PLL.

The system crystal oscillator consists of a Pierce-type structure running off the digital supply. A straight

forward biased-inverter implementation is used.

4.5.2

OSC32K

This block implements an amplifier that when combined with a suitable quartz crystal and external load

capacitors implements a low power oscillator. It also implements a power mux such that it can be powered

from either a ~3 V backup battery (VDD_SNVS_IN) or VDD_HIGH_IN such as the oscillator consumes

power from VDD_HIGH_IN when that supply is available and transitions to the back up battery when

VDD_HIGH_IN is lost.

Additionally, if the clock monitor determines that the OSC32K is not present, then the source of the 32 kHz

clock will automatically switch to the internal ring oscillator.

CAUTION

The internal RTC oscillator does not provide an accurate frequency and is

affected by process, voltage, and temperature variations. NXP strongly

recommends using an external crystal as the RTC_XTALI reference. If the

internal oscillator is used, careful consideration must be given to the timing

implications on all of the SoC modules dependent on this clock.

The OSC32K runs from VDD_SNVS_CAP supply, which comes from the VDD_HIGH_IN/

VDD_SNVS_IN.

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Table 22. OSC32K Main Characteristics

Characteristics

Min

Typ

Max

Comments

Fosc

—

32.768 KHz

—

This frequency is nominal and determined mainly by the crystal selected.

32.0 K would work as well.

Current consumption

—

4 μA

—

The 4 μA is the consumption of the oscillator alone (OSC32K). Total supply

consumption will depend on what the digital portion of the RTC consumes.

The ring oscillator consumes 1 μA when ring oscillator is inactive, 20 μA

when the ring oscillator is running. Another 1.5 μA is drawn from

VDD_SNVS_IN in the power_detect block. So, the total current is 6.5 μA

on VDD_SNVS_IN when the ring oscillator is not running.

Bias resistor

—

14 MΩ

This the integrated bias resistor that sets the amplifier into a high gain

state. Any leakage through the ESD network, external board leakage, or

even a scope probe that is significant relative to this value will debias the

amp. The debiasing will result in low gain, and will impact the circuit's ability

to start up and maintain oscillations.

Crystal Properties

Cload

ESR

—

10 pF

—

Usually crystals can be purchased tuned for different Cloads. This Cload

value is typically 1/2 of the capacitances realized on the PCB on either side

of the quartz. A higher Cload will decrease oscillation margin, but

increases current oscillating through the crystal.

50 kΩ

100 kΩ Equivalent series resistance of the crystal. Choosing a crystal with a higher

value will decrease the oscillating margin.

4.6

I/O DC Parameters

This section includes the DC parameters of the following I/O types:

•

General Purpose I/O (GPIO)

Double Data Rate I/O (DDR) for LPDDR2 and DDR3 modes

LVDS I/O

NOTE

The term ‘OVDD’ in this section refers to the associated supply rail of an

input or output.

ovdd

pmos (Rpu)

Voh min

1

Vol max

or

0

pdat

pad

Predriver

nmos (Rpd)

ovss

Figure 3. Circuit for Parameters Voh and Vol for I/O Cells

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4.6.1

XTALI and RTC_XTALI (Clock Inputs) DC Parameters

Table 23 shows the DC parameters for the clock inputs.

Table 23. XTALI and RTC_XTALI DC Parameters

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

XTALI high-level DC input voltage

XTALI low-level DC input voltage

RTC_XTALI high-level DC input voltage

RTC_XTALI low-level DC input voltage

Input Capacitance

Vih

—

0.8 x NVCC_PLL

—

5

NVCC_PLL

0.2V

1.1¹

V

Vil

—

0

0.8

0

Vih

—

V

Vil

C_IN

0.2

V

Simulated data

—

pF

uA

Startup current

I_{XTALI_STARTUP}

Power-on startup for

0.15msec with a driven

24 MHz clock at 1.1V.

This current draw is

present even if an

—

600

external clock source

directly drives XTALI

DC input current

I_{XTALI_DC}

—

2.5

uA

1

This voltage specification must not be exceeded and, as such, is an absolute maximum specification.

NOTE

The Vil and Vih specifications only apply when an external clock source is

used. If a crystal is used, Vil and Vih do not apply.

4.6.2

Single Voltage General Purpose I/O (GPIO) DC Parameters

Table 24 shows DC parameters for GPIO pads. The parameters in Table 24 are guaranteed per the

operating ranges in Table 9, unless otherwise noted.

Table 24. Single Voltage GPIO DC Parameters

Parameter

Symbol

Test Conditions

Min

Max

Units

High-level output voltage¹

V_OH

Ioh= -0.1mA (DSE=001,010)

Ioh= -1mA

OVDD-0.15

–

V

(DSE=011,100,101,110,111)

Low-level output voltage¹

VOL

Iol= 0.1mA (DSE=001,010)

Iol= 1mA

–

0.15

V

(DSE=011,100,101,110,111)

High-Level input voltage^1,2

Low-Level input voltage^1,2

VIH

VIL

—

0.7*OVDD

0

OVDD

V

0.3*OVDD

V

Input Hysteresis (OVDD= 1.8V) VHYS_Low VDD

Input Hysteresis (OVDD=3.3V) VHYS_High VDD

OVDD=1.8 V

OVDD=3.3 V

—

250

—

mV

250

Schmitt trigger VT+ ^2,3

VTH+

0.5*OVDD

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Table 24. Single Voltage GPIO DC Parameters (continued)

Parameter

Symbol

Test Conditions

Min

Max

Units

Schmitt trigger VT- ^2,3

Pull-up resistor (22_kΩ PU)

Pull-up resistor (47_kΩ PU)

Pull-up resistor (100_kΩ PU)

Pull-down resistor (100_kΩ PD)

Input current (no PU/PD)

VTH-

—

Vin=0V

—

-1

0.5*OVDD

mV

uA

kΩ

RPU_22K

RPU_47K

RPU_100K

RPD_100K

IIN

212

1

Vin=OVDD

Vin=0V

100

1

Vin=OVDD

Vin=0V

48

1

Vin=OVDD

48

1

Vin=0V

VI = 0, VI = OVDD

VI =0.3*OVDD, VI = 0.7* OVDD

1

Keeper Circuit Resistance

R_Keeper

105

175

1

Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.6 V,

and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/ undershoot must

be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other

methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device.

2

3

To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC

level through to the target DC level, Vil or Vih. Monotonic input transition time is from 0.1 ns to 1 s.

Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.

4.6.3

Dual Voltage GPIO I/O DC Parameters

Table 25 shows DC parameters for GPIO pads. The parameters in Table 25 are guaranteed per the

operating ranges in Table 9, unless otherwise noted.

Table 25. Dual Voltage GPIO I/O DC Parameters

Parameter

Symbol

Test Conditions

Min

Max

Unit

High-level output voltage¹

Voh

Ioh = -0.1 mA (DSE²= 001, 010) OVDD – 0.15

Ioh = -1 mA

—

V

(DSE = 011, 100, 101, 110, 111)

Low-level output voltage¹

Vol

Iol = 0.1 mA (DSE = 001, 010)

Iol = 1mA

—

0.15

V

(DSE = 011, 100, 101, 110, 111)

High-Level DC input voltage ^1,3

Low-Level DC input voltage^1,3

Input Hysteresis

Vih

Vil

—

0.7 × OVDD

OVDD

0.3 × OVDD

—

V

0

Vhys

OVDD = 1.8 V

OVDD = 3.3 V

0.25

Schmitt trigger VT+ ^3,4

Schmitt trigger VT– ^3,4

VT+

VT–

—

0.5 × OVDD

—

V

—

0.5 × OVDD

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Parameter

Table 25. Dual Voltage GPIO I/O DC Parameters (continued)

Symbol

Test Conditions

Min

Max

Unit

Input current (no pull-up/down)

Iin

Vin = OVDD or 0

-1.25

—

1.25

μA

Input current (22 kΩ pull-up)

Vin = 0 V

Vin = OVDD

212

1

μA

kΩ

Input current (47 kΩ pull-up)

Input current (100 kΩ pull-up)

Input current (100 kΩ pull-down)

Iin

Vin = 0 V

Vin = OVDD

—

100

1

Vin = 0 V

Vin= OVDD

48

1

Iin

Vin = 0 V

Vin = OVDD

—

1

48

Keeper circuit resistance

Rkeep

Vin = 0.3 x OVDD

Vin = 0.7 x OVDD

105

205

1

Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.6 V,

and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/ undershoot must be

controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods.

Non-compliance to this specification may affect device reliability or cause permanent damage to the device.

2

3

DSE is the Drive Strength Field setting in the associated IOMUX control register.

To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC

level through to the target DC level, Vil or Vih. Monotonic input transition time is from 0.1 ns to 1 s.

4

Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.

4.6.4

DDR I/O DC Parameters

The DDR I/O pads support LPDDR2 and DDR3/DDR3L operational modes.

4.6.4.1 LPDDR2 Mode I/O DC Parameters

For details on supported DDR memory configurations, see Section 4.10, “Multi-mode DDR Controller

(MMDC).

1

Table 26. LPDDR2 I/O DC Electrical Parameters

Parameters

Symbol

Test Conditions

Min

Max

Unit

High-level output voltage

Low-level output voltage

VOH

VOL

Ioh= -0.1mA

0.9*OVDD

—

0.1*OVDD

0.51*OVDD

OVDD

Vref-0.13

Note²

V

Iol= 0.1mA

Input Reference Voltage

Vref

—

0.49*OVDD

Vref+0.13

OVSS

0.26

V

DC High-Level input voltage

DC Low-Level input voltage

Differential Input Logic High

Differential Input Logic Low

Pull-up/Pull-down Impedance Mismatch

240 Ω unit calibration resolution

Vih_DC

Vil_DC

Vih_diff

Vil_diff

Mmpupd

Rres

V

—

%

Ω

Note³

-15

-0.26

15

—

10

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1

Table 26. LPDDR2 I/O DC Electrical Parameters (continued)

Parameters

Symbol

Test Conditions

Min

Max

Unit

Keeper Circuit Resistance

Rkeep

Iin

—

110

-2.5

175

2.5

kΩ

μA

Input current (no pull-up/down)

VI = 0, VI = OVDD

1

2

Note that the JEDEC LPDDR2 specification (JESD209_2B) supersedes any specification in this document.

The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well as

the limitations for overshoot and undershoot.

3

The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well as

the limitations for overshoot and undershoot.

4.6.4.2

DDR3/DDR3L Mode I/O DC Parameters

For details on supported DDR memory configurations, see Section 4.10, “Multi-mode DDR Controller

(MMDC). The parameters in Table 27 are guaranteed per the operating ranges in Table 9, unless otherwise

noted.

Table 27. DDR3/DDR3L I/O DC Electrical Characteristics

Parameters

Symbol

Test Conditions

Min

Max

Unit

High-level output voltage

VOH

Ioh= -0.1mA

0.8*OVDD¹

—

V

Voh (for DSE=001)

Low-level output voltage

High-level output voltage

Low-level output voltage

VOL

VOH

VOL

Iol= 0.1mA

Vol (for DSE=001)

0.2*OVDD

0.8*OVDD

0.2*OVDD

V

—

V

Ioh= -1mA

Voh (for all except DSE=001)

Iol= 1mA

V

—

Vol (for all except DSE=001)

Input Reference Voltage

DC High-Level input voltage

DC Low-Level input voltage

Differential Input Logic High

Differential Input Logic Low

Termination Voltage

Vref

Vih_DC

Vil_DC

Vih_diff

Vil_diff

Vtt

—

0.49*ovdd

Vref²+0.1

OVSS

0.2

0.51*ovdd

OVDD

Vref-0.1

See Note³

-0.2

V

—

V

—

V

—

See Note

0.49*OVDD

-10

V

Vtt tracking OVDD/2

0.51*OVDD

10

V

Pull-up/Pull-down Impedance Mismatch Mmpupd

—

%

Ω

240 Ω unit calibration resolution

Keeper Circuit Resistance

Rres

Rkeep

Iin

—

10

105

165

kΩ

μA

Input current (no pull-up/down)

VI = 0,VI = OVDD

-2.9

2.9

1

2

3

OVDD – I/O power supply (1.425 V–1.575 V for DDR3 and 1.283 V–1.45 V for DDR3L)

Vref – DDR3/DDR3L external reference voltage

The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well as

the limitations for overshoot and undershoot.

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4.6.5

LVDS I/O DC Parameters

The LVDS interface complies with TIA/EIA 644-A standard. See TIA/EIA STANDARD 644-A,

“Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits” for details.

Table 28 shows the Low Voltage Differential Signaling (LVDS) I/O DC parameters.

Table 28. LVDS I/O DC Characteristics

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Output Differential Voltage

Output High Voltage

Output Low Voltage

Offset Voltage

VOD

VOH

VOL

VOS

Rload-100 Ω Diff

IOH = 0 mA

IOL = 0 mA

—

250

1.25

0.9

350

1.375

1.025

1.2

450

1.6

mV

V

1.25

1.375

V

1.125

V

4.7

I/O AC Parameters

This section includes the AC parameters of the following I/O types:

•

General Purpose I/O (GPIO)

Double Data Rate I/O (DDR) for LPDDR2 and DDR3/DDR3L modes

LVDS I/O

The GPIO and DDR I/O load circuit and output transition time waveforms are shown in Figure 4 and

Figure 5.

From Output

Under Test

Test Point

CL

CL includes package, probe and fixture capacitance

Figure 4. Load Circuit for Output

OVDD

0 V

80%

20%

80%

20%

tr

Output (at pad)

tf

Figure 5. Output Transition Time Waveform

4.7.1

General Purpose I/O AC Parameters

The I/O AC parameters for GPIO in slow and fast modes are presented in the Table 29 and Table 30,

respectively. Note that the fast or slow I/O behavior is determined by the appropriate control bits in the

IOMUXC control registers.

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Table 29. General Purpose I/O AC Parameters 1.8 V Mode

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Output Pad Transition Times, rise/fall

(Max Drive, DSE=111)

tr, tf

15 pF Cload, slow slew rate

15 pF Cload, fast slew rate

2.72/2.79

1.51/1.54

—

Output Pad Transition Times, rise/fall

(High Drive, DSE=101)

tr, tf

trm

15 pF Cload, slow slew rate

15 pF Cload, fast slew rate

3.20/3.36

1.96/2.07

—

ns

Output Pad Transition Times, rise/fall

(Medium Drive, DSE=100)

15 pF Cload, slow slew rate

15 pF Cload, fast slew rate

3.64/3.88

2.27/2.53

Output Pad Transition Times, rise/fall

(Low Drive. DSE=011)

15 pF Cload, slow slew rate

15 pF Cload, fast slew rate

4.32/4.50

3.16/3.17

—

Input Transition Times¹

—

25

1

Hysteresis mode is recommended for inputs with transition times greater than 25 ns.

Table 30. General Purpose I/O AC Parameters 3.3 V Mode

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Output Pad Transition Times, rise/fall

(Max Drive, DSE=101)

tr, tf

15 pF Cload, slow slew rate

15 pF Cload, fast slew rate

1.70/1.79

1.06/1.15

—

Output Pad Transition Times, rise/fall

(High Drive, DSE=011)

tr, tf

trm

15 pF Cload, slow slew rate

15 pF Cload, fast slew rate

2.35/2.43

1.74/1.77

—

ns

Output Pad Transition Times, rise/fall

(Medium Drive, DSE=010)

15 pF Cload, slow slew rate

15 pF Cload, fast slew rate

3.13/3.29

2.46/2.60

Output Pad Transition Times, rise/fall

(Low Drive, DSE=001)

15 pF Cload, slow slew rate

15 pF Cload, fast slew rate

5.14/5.57

4.77/5.15

—

Input Transition Times¹

—

25

1

Hysteresis mode is recommended for inputs with transition times greater than 25 ns.

4.7.2

DDR I/O AC Parameters

For details on supported DDR memory configurations, see Section 4.10, “Multi-mode DDR Controller

(MMDC).

Table 31 shows the AC parameters for DDR I/O operating in LPDDR2 mode.

1

Table 31. DDR I/O LPDDR2 Mode AC Parameters

Parameter

AC input logic high

Symbol

Test Condition

Min

Max

Unit

Vih(ac)

Vil(ac)

—

Vref + 0.22

OVDD

Vref - 0.22

—

V

AC input logic low

—

0

0.44

—

AC differential input high voltage²

AC differential input low voltage

Input AC differential cross point voltage³

Over/undershoot peak

Vidh(ac)

Vidl(ac)

Vix(ac)

Vpeak

—

Relative to Vref

—

0.44

-0.12

—

0.12

0.35

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Table 31. DDR I/O LPDDR2 Mode AC Parameters (continued)

1

Parameter

Symbol

Test Condition

Min

Max

Unit

Over/undershoot area (above OVDD

or below OVSS)

Varea

400 MHz

—

0.3

V-ns

Single output slew rate, measured between

Vol(ac) and Voh(ac)

50 Ω to Vref.

5 pF load.

Drive impedance = 40 Ω 30%

1.5

1

3.5

2.5

0.1

tsr

V/ns

ns

50 Ω to Vref.

5pF load.

Drive impedance = 60 Ω 30%

Skew between pad rise/fall asymmetry + skew

caused by SSN

t_SKD

clk = 400 MHz

—

1

Note that the JEDEC LPDDR2 specification (JESD209_2B) supersedes any specification in this document.

2

3

Vid(ac) specifies the input differential voltage | Vtr - Vcp | required for switching, where Vtr is the “true” input signal and Vcp is

the “complementary” input signal. The Minimum value is equal to Vih(ac) - Vil(ac).

The typical value of Vix(ac) is expected to be about 0.5 x OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac)

indicates the voltage at which differential input signal must cross.

Table 32 shows the AC parameters for DDR I/O operating in DDR3/DDR3L mode.

1

Table 32. DDR I/O DDR3/DDR3L Mode AC Parameters

Parameter

AC input logic high

Symbol

Test Condition

Min

Typ

Max

Unit

Vih(ac)

Vil(ac)

Vid(ac)

Vix(ac)

Vpeak

Varea

—

Vref + 0.175

—

OVDD

Vref - 0.175

—

V

AC input logic low

—

0

0.35

AC differential input voltage²

Input AC differential cross point voltage^3,4

Over/undershoot peak

—

Relative to Vref

—

V

Vref - 0.15

—

Vref + 0.15

0.4

V

Over/undershoot area (above OVDD

or below OVSS)

400 MHz

—

0.5

V-ns

Single output slew rate, measured between

Vol(ac) and Voh(ac)

tsr

Driver impedance = 34 Ω

2.5

—

5

V/ns

ns

Skew between pad rise/fall asymmetry + skew

caused by SSN

t_SKD

clk = 400 MHz

0.1

—

1

2

Note that the JEDEC JESD79_3C specification supersedes any specification in this document.

Vid(ac) specifies the input differential voltage | Vtr-Vcp | required for switching, where Vtr is the “true” input signal and Vcp is

the “complementary” input signal. The Minimum value is equal to Vih(ac) - Vil(ac).

3

4

The typical value of Vix(ac) is expected to be about 0.5 x OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac)

indicates the voltage at which differential input signal must cross.

Extended range for Vix is only allowed for the clock and when the single-ended clock input signals CK and CK# are:

Monotonic with a single-ended swing VSEL/VSEH of at least VDD/2 250 mV, and

The differential slew rate of CK - CK# is larger than 3 V/ns

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4.7.3

LVDS I/O AC Parameters

The differential output transition time waveform is shown in Figure 6.

padp

V

OH

0V

0V (Differential)

padn

V

OL

80%

0V

VDIFF

VDIFF = {padp} - {padn}

20%

t

THL

TLH

Figure 6. Differential LVDS Driver Transition Time Waveform

Table 33 shows the AC parameters for LVDS I/O.

Table 33. I/O AC Parameters of LVDS Pad

Parameter

Differential pulse skew¹

Symbol Test Condition

Min

Typ

Max

Unit

t_SKD

—

0.25

0.5

Rload = 100 Ω,

Cload = 2 pF

Transition Low to High Time²

Transition High to Low Time²

Operating Frequency

t_TLH

ns

t_THL

—

0.5

f

—

600

—

800

150

MHz

mV

Offset voltage imbalance

Vos

1

t_SKD= | t_PHLD- t_PLHD|, is the magnitude difference in differential propagation delay time between the positive going edge and

the negative going edge of the same channel.

2

Measurement levels are 20-80% from output voltage.

4.8

Output Buffer Impedance Parameters

This section defines the I/O impedance parameters of the i.MX 6SoloX processors for the following I/O

types:

•

Dual Voltage General Purpose I/O (DVGPIO)

Single Voltage General Purpose I/O (GPIO)

Double Data Rate I/O (DDR) for LPDDR2, and DDR3/DDR3L modes

LVDS I/O

NOTE

GPIO and DDR I/O output driver impedance is measured with “long”

transmission line of impedance Ztl attached to I/O pad and incident wave

launched into transmission line. Rpu/Rpd and Ztl form a voltage divider that

defines specific voltage of incident wave relative to OVDD. Output driver

impedance is calculated from this voltage divider (see Figure 7).

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Electrical Characteristics

OVDD

PMOS (Rpu)

Ztl Ω, L = 20 inches

ipp_do

pad

predriver

Cload = 1p

NMOS (Rpd)

OVSS

U,(V)

VDD

Vin (do)

t,(ns)

0

U,(V)

Vout (pad)

OVDD

Vref2

Vref1

Vref

t,(ns)

0

Vovdd – Vref1

Vref1

Rpu =

× Ztl

Vref2

Rpd =

Vovdd – Vref2

Figure 7. Impedance Matching Load for Measurement

4.8.1

Dual Voltage GPIO Output Buffer Impedance

Table 34 shows the GPIO output buffer impedance (OVDD 1.8 V).

Table 34. DVGPIO Output Buffer Average Impedance (OVDD 1.8 V)

Typical

Parameter

Symbol

Drive Strength (DSE)

Unit

ADD_DS=1

ADD_DS=0

000

001

010

011

100

101

110

111

Hi-Z

262

134

88

62

51

Hi-Z

235

117

78

52

43

Output Driver

Impedance

Rdrv

Ω

43

37

36

31

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Table 35 shows the GPIO output buffer impedance (OVDD 3.3 V).

Table 35. DVGPIO Output Buffer Average Impedance (OVDD 3.3 V)

Parameter

Symbol

Drive Strength (DSE)

Typical

Unit

000

001

010

011

100

101

110

111

Hi-Z

247

126

84

57

47

Output Driver

Impedance

Rdrv

Ω

40

34

4.8.2

Single Voltage GPIO Output Buffer Impedance

Table 36 shows the GPIO output buffer impedance (OVDD 1.8 V).

Table 36. GPIO Output Buffer Average Impedance (OVDD 1.8 V)

Parameter

Symbol

Drive Strength (DSE)

Typ Value

Unit

001

010

011

100

101

110

111

260

130

88

65

52

Output Driver

Impedance

Rdrv

Ω

43

37

Table 37 shows the GPIO output buffer impedance (OVDD 3.3 V).

Table 37. GPIO Output Buffer Average Impedance (OVDD 3.3 V)

Parameter

Symbol

Drive Strength (DSE)

Typ Value

Unit

001

010

011

100

101

110

111

157

78

53

39

32

26

23

Output Driver

Impedance

Rdrv

Ω

4.8.3

DDR I/O Output Buffer Impedance

For details on supported DDR memory configurations, see Section 4.10, “Multi-mode DDR Controller

(MMDC).

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Table 38 shows DDR I/O output buffer impedance of i.MX 6SoloX processors.

Table 38. DDR I/O Output Buffer Impedance

Typical

Test Conditions DSE

Parameter

Symbol

Unit

NVCC_DRAM=1.5 V

(DDR3)

NVCC_DRAM=1.2 V

(LPDDR2)

(Drive Strength)

DDR_SEL=11

DDR_SEL=10

000

001

010

011

100

101

110

111

Hi-Z

240

120

80

60

48

Hi-Z

240

120

80

60

48

Output Driver

Impedance

Rdrv

Ω

40

34

40

34

Note:

1. Output driver impedance is controlled across PVTs using ZQ calibration procedure.

2. Calibration is done against 240 Ω external reference resistor.

3. Output driver impedance deviation (calibration accuracy) is 5% (max/min impedance) across PVTs.

4.8.4

USB HSIC I/O Output Buffer Impedance

Table 39 shows the USB HSIC I/O (USB_H_DATA and USB_H_STROBE) output buffer impedance.

Table 39. USB HSIC I/O Output Buffer Impedance

Typical

Drive

Parameter Symbol Strength

(DSE)

Unit

NVCC_USB_H=1.2V NVCC_USB_H=1.5V NVCC_USB_H=1.8V NVCC_USB_H=2.5V

DDR_SEL=10

DDR_SEL=11

000

001

010

Hi-Z

240

120

80

60

48

Hi-Z

240

120

80

60

48

Hi-Z

247

113

73

55

43

Hi-Z

287

121

76

57

45

Output

011

Driver

Impedance

Rdrv

Ω

100

101

110

111

40

34

40

34

36

30

37

31

4.8.5

LVDS I/O Output Buffer Impedance

The LVDS interface complies with TIA/EIA 644-A standard. See, TIA/EIA STANDARD 644-A,

“Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits” for details.

4.9

System Modules Timing

This section contains the timing and electrical parameters for the modules in each i.MX 6SoloX processor.

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4.9.1

Reset Timing Parameters

Figure 8 shows the reset timing and Table 40 lists the timing parameters.

POR_B

(Input)

CC1

Figure 8. Reset Timing Diagram

Table 40. Reset Timing Parameters

ID

Parameter

Min Max

Unit

CC1

Duration of POR_B to be qualified as valid.

1

—

RTC_XTALI cycle

4.9.2

WDOG Reset Timing Parameters

Figure 9 shows the WDOG reset timing and Table 41 lists the timing parameters.

WDOGn_B

(Output)

CC3

Figure 9. WDOGn_B Timing Diagram

Table 41. WDOGn_B Timing Parameters

ID

Parameter

Duration of WDOGn_B Assertion

Min

Max

Unit

CC3

1

—

RTC_XTALI cycle

NOTE

RTC_XTALI is approximately 32 kHz. RTC_XTALI cycle is one period or

approximately 30 μs.

NOTE

WDOG1_B output signals (for each one of the Watchdog modules) do not

have dedicated pins, but are muxed out through the IOMUX. See the IOMUX

manual for detailed information.

4.9.3

External Interface Module (EIM)

The following subsections provide information on the EIM. Maximum operating frequency for EIM data

transfer is 104 MHz. Two system clocks are used with the EIM:

•

ACLK_EIM_SLOW_CLK_ROOT is used to clock the EIM module.

The maximum frequency for CLK_EIM_SLOW_CLK_ROOT is 132 MHz.

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•

ACLK_EXSC is also used when the EIM is in synchronous mode.

The maximum frequency for ACLK_EXSC is 132 MHz.

Timing parameters in this section that are given as a function of register settings.

4.9.3.1 EIM Interface Pads Allocation

EIM supports 32-bit, 16-bit and 8-bit devices operating in address/data separate or multiplexed modes.

Table 42 provides EIM interface pads allocation in different modes.

1

Table 42. EIM Internal Module Multiplexing

Multiplexed

Non Multiplexed Address/Data Mode

Address/Data mode

Setup

8 Bit

16 Bit

32 Bit

16 Bit

32 Bit

MUM = 0, MUM = 0, MUM = 0, MUM = 0, MUM = 0, MUM = 0, MUM = 0, MUM = 1, MUM = 1,

DSZ = 100 DSZ = 101 DSZ = 110 DSZ = 111 DSZ = 001 DSZ = 010 DSZ = 011 DSZ = 001 DSZ = 011

EIM_ADDR

[15:00]

EIM_AD

[15:00]

EIM_AD

[15:00]

EIM_AD

[15:00]

EIM_AD

[15:00]

EIM_AD

[15:00]

EIM_AD

[15:00]

EIM_AD

[15:00]

EIM_AD

[15:00]

EIM_AD

[15:00]

EIM_ADDR EIM_ADDR EIM_ADDR EIM_ADDR EIM_ADDR EIM_ADDR EIM_ADDR EIM_ADDR EIM_ADDR EIM_DATA

[25:16]

EIM_DATA EIM_AD

[07:00] [07:00]

[25:16]

[09:00]

EIM_DATA EIM_DATA

[07:00],

EIM_EB0_B

—

EIM_DATA

[07:00]

—

EIM_AD

[07:00]

—

EIM_DATA

[15:08],

EIM_EB1_B

EIM_DATA

[15:08]

—

EIM_DATA

[15:08]

—

EIM_DATA EIM_AD

EIM_AD

[15:08]

EIM_DATA

[23:16],

EIM_EB2_B

—

EIM_DATA

[23:16]

—

EIM_DATA EIM_DATA

[23:16] [23:16]

—

EIM_DATA

[07:00]

EIM_DATA

[31:24],

—

EIM_DATA

[31:24]

EIM_DATA EIM_DATA

[31:24] [31:24]

—

EIM_DATA

[15:08]

EIM_EB3_B

1

For more information on configuration ports mentioned in this table, see the i.MX 6SoloX Applications Processor Reference

Manual (IMX6SXRM).

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4.9.3.2

General EIM Timing-Synchronous Mode

Figure 10, Figure 11, and Table 43 specify the timings related to the EIM module. All EIM output control

signals may be asserted and deasserted by an internal clock synchronized to the EIM_BCLK rising edge

according to corresponding assertion/negation control fields.

,

WE2

...

WE3

EIM_BCLK

WE1

WE4

WE6

WE5

WE7

WE9

EIM_ADDRxx

EIM_CSx_B

WE8

WE10

WE12

EIM_WE_B

EIM_OE_B

EIM_EBx_B

WE11

WE13

WE15

WE17

WE14

WE16

EIM_LBA_B

Output Data

Figure 10. EIM Outputs Timing Diagram

EIM_BCLK

WE18

Input Data

WE19

WE20

EIM_WAIT_B

WE21

Figure 11. EIM Inputs Timing Diagram

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4.9.3.3

Examples of EIM Synchronous Accesses

1

Table 43. EIM Bus Timing Parameters

BCD = 0 BCD = 1

BCD = 2

Max

BCD = 3

Max

ID

Parameter

Min

Max

Min

Max

Min

WE1 EIM_BCLK Cycle

time²

t

—

2 x t

—

3 x t

—

4 x t

—

WE2 EIM_BCLK Low

Level Width

0.4 x t

—

0.8 x t

—

1.2 x t

1.6 x t

WE3 EIM_BCLK High

Level Width

WE4 Clock rise to

address valid³

-0.5 x t - -0.5 x t + 1.75 -t - 1.25 -t + 1.75 -1.5 x t -

-1.5 x t

+1.75

-2 x t - -2 x t + 1.75

1.25

WE5 Clock rise to

address invalid

0.5 x t - 1.25 0.5 x t + 1.75 t - 1.25

t + 1.75 1.5 x t - 1.5 x t +1.75 2 x t - 1.25 2 x t + 1.75

1.25

WE6 Clock rise to

EIM_CSx_B valid

-0.5 x t - -0.5 x t + 1.75 -t - 1.25 - t + 1.75 -1.5 x t -

-1.5 x t

+1.75

-2 x t - -2 x t + 1.75

1.25

WE7 Clock rise to

EIM_CSx_B invalid

0.5 x t - 1.25 0.5 x t + 1.75 t - 1.25

t + 1.75 1.5 x t - 1.5 x t +1.75 2 x t - 1.25 2 x t + 1.75

1.25

WE8 Clock rise to

EIM_WE_B Valid

-0.5 x t - -0.5 x t + 1.75 -t - 1.25 - t + 1.75 -1.5 x t -

-1.5 x t

+1.75

-2 x t - -2 x t + 1.75

1.25

WE9 Clock rise to

EIM_WE_B Invalid

0.5 x t - 1.25 0.5 x t + 1.75 t - 1.25

t + 1.75 1.5 x t - 1.5 x t +1.75 2 x t - 1.25 2 x t + 1.75

1.25

WE10 Clock rise to

EIM_OE_B Valid

-0.5 x t - -0.5 x t + 1.75 -t - 1.25 - t + 1.75 -1.5 x t -

-1.5 x t

+1.75

-2 x t - -2 x t + 1.75

1.25

WE11 Clock rise to

EIM_OE_B Invalid

0.5 x t - 1.25 0.5 x t + 1.75 t - 1.25

t + 1.75 1.5 x t - 1.5 x t +1.75 2 x t - 1.25 2 x t + 1.75

1.25

WE12 Clock rise to

EIM_EBx_B Valid

-0.5 x t - -0.5 x t + 1.75 -t - 1.25 - t + 1.75 -1.5 x t -

-1.5 x t

+1.75

-2 x t - -2 x t + 1.75

1.25

WE13 Clock rise to

EIM_EBx_B Invalid

0.5 x t - 1.25 0.5 x t + 1.75 t - 1.25

t + 1.75 1.5 x t - 1.5 x t +1.75 2 x t - 1.25 2 x t + 1.75

1.25

WE14 Clock rise to

EIM_LBA_B Valid

-0.5 x t - -0.5 x t + 1.75 -t - 1.25 - t + 1.75 -1.5 x t -

-1.5 x t

+1.75

-2 x t - -2 x t + 1.75

1.25

WE15 Clock rise to

EIM_LBA_B Invalid

0.5 x t - 1.25 0.5 x t + 1.75 t - 1.25

t + 1.75 1.5 x t - 1.5 x t +1.75 2 x t - 1.25 2 x t + 1.75

1.25

WE16 Clock rise to Output -0.5 x t - -0.5 x t + 1.75 -t - 1.25 - t + 1.75 -1.5 x t -

Data Valid 1.25 1.25

-1.5 x t

+1.75

-2 x t - -2 x t + 1.75

1.25

WE17 Clock rise to Output 0.5 x t - 1.25 0.5 x t + 1.75 t - 1.25

Data Invalid

t + 1.75 1.5 x t - 1.5 x t +1.75 2 x t - 1.25 2 x t + 1.75

1.25

WE18 Input Data setup

time to Clock rise

2

—

4

2

4

2

—

WE19 Input Data hold time

from Clock rise

WE20 EIM_WAIT_B setup

time to Clock rise

WE21 EIM_WAIT_B hold

time from Clock rise

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1

t is the maximum EIM logic (ACLK_EXSC) cycle time. The maximum allowed axi_clk frequency depends on the fixed/non-fixed

latency configuration, whereas the maximum allowed EIM_BCLK frequency is:

—Fixed latency for both read and write is 104 MHz.

—Variable latency for read only is 104 MHz.

—Variable latency for write only is 52 MHz.

In variable latency configuration for write, if BCD = 0 & WBCDD = 1 or BCD = 1, axi_clk must be 104 MHz.Write BCD = 1 and

104 MHz ACLK_EXSC, will result in a EIM_BCLK of 52 MHz. When the clock branch to EIM is decreased to 104 MHz, other

buses are impacted which are clocked from this source. See the CCM chapter of the ii.MX 6SoloX Applications Processor

Reference Manual (IMX6SXRM) for a detailed clock tree description.

2

EIM_BCLK parameters are being measured from the 50% point, that is, high is defined as 50% of signal value and low is

defined as 50% as signal value.

3

For signal measurements, “High” is defined as 80% of signal value and “Low” is defined as 20% of signal value.

Figure 12 to Figure 15 provide few examples of basic EIM accesses to external memory devices with the

timing parameters mentioned previously for specific control parameters settings.

EIM_BCLK

WE4

WE6

WE5

WE7

EIM_ADDRxx

Address v1

Last Valid Address

EIM_CSx_B

EIM_WE_B

EIM_LBA_B

WE14

WE10

WE12

WE15

WE18

WE11

WE13

EIM_OE_B

EIM_EBx_B

EIM_DATAxx

D(v1)

WE19

Figure 12. Synchronous Memory Read Access, WSC=1

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EIM_BCLK

WE5

WE4

EIM_ADDRxx

Last Valid Address

Address V1

WE7

WE6

WE8

EIM_CSx_B

EIM_WE_B

EIM_LBA_B

EIM_OE_B

WE9

WE14

WE15

WE13

WE12

WE16

EIM_EBx_B

WE17

EIM_DATAxx

D(V1)

Figure 13. Synchronous Memory, Write Access, WSC=1, WBEA=0 and WADVN=0

EIM_BCLK

WE16

WE17

WE5

WE4

EIM_ADDRxx/

EIM_ADxx

Write Data

Last Valid Address

Address V1

WE6

WE7

WE9

EIM_CSx_B

EIM_WE_B

WE8

WE14

WE15

EIM_LBA_B

EIM_OE_B

WE10

WE11

EIM_EBx_B

Figure 14. Muxed Address/Data (A/D) Mode, Synchronous Write Access,

WSC=6, ADVA=0, ADVN=1, and ADH=1

NOTE

In 32-bit muxed address/data (A/D) mode the 16 MSBs are driven on the

data bus.

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EIM_BCLK

WE4

Valid Address

WE6

WE5

Address V1

WE19

Data

EIM_ADDRxx/

EIM_ADxx

Last

WE18

EIM_CSx_B

EIM_WE_B

WE7

WE15

WE10

WE14

WE12

EIM_LBA_B

EIM_OE_B

WE11

WE13

EIM_EBx_B

Figure 15. 16-Bit Muxed A/D Mode, Synchronous Read Access, WSC=7, RADVN=1, ADH=1, OEA=0

4.9.3.4

General EIM Timing-Asynchronous Mode

Figure 16 through Figure 21, and Table 44 help you determine timing parameters relative to the chip

select (CS) state for asynchronous and DTACK EIM accesses with corresponding EIM bit fields and the

timing parameters mentioned above.

Asynchronous read and write access length in cycles may vary from what is shown in Figure 16 through

Figure 19 as RWSC, OEN and CSN is configured differently. See the ii.MX 6SoloX Applications

Processor Reference Manual (IMX6SXRM) for the EIM programming model.

end of

access

start of

access

INT_CLK

MAXCSO

EIM_CSx_B

EIM_ADDRxx/

EIM_ADxx

WE31

WE32

Next Address

Last Valid Address

Address V1

EIM_WE_B

EIM_LBA_B

WE39

WE40

WE36

WE38

WE35

WE37

EIM_OE_B

EIM_EBx_B

WE44

MAXCO

EIM_DATAxx[7:0]

D(V1)

WE43

MAXDI

Figure 16. Asynchronous Memory Read Access (RWSC = 5)

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Electrical Characteristics

end of

access

start of

access

INT_CLK

MAXCSO

EIM_CSx_B

MAXDI

WE31

EIM_ADDRxx/

EIM_ADxx

D(V1)

Addr. V1

WE32A

WE44

EIM_WE_B

EIM_LBA_B

WE40A

WE39

WE35A

WE37

WE36

WE38

EIM_OE_B

EIM_EBx_B

MAXCO

Figure 17. Asynchronous A/D Muxed Read Access (RWSC = 5)

EIM_CSx_B

WE31

Last Valid Address

WE33

WE32

WE34

WE40

EIM_ADDRxx

Next Address

Address V1

EIM_WE_B

EIM_LBA_B

EIM_OE_B

WE39

WE45

WE41

WE46

EIM_EBx_B

WE42

EIM_DATAxx

D(V1)

Figure 18. Asynchronous Memory Write Access

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EIM_CSx_B

WE41A

WE31

EIM_ADDRxx/

EIM_DATAxx

D(V1)

Addr. V1

WE32A

WE42

WE33

WE39

WE34

EIM_WE_B

WE40A

EIM_LBA_B

EIM_OE_B

WE45

WE46

EIM_EBx_B

Figure 19. Asynchronous A/D Muxed Write Access

EIM_CSx_B

WE31

WE32

EIM_ADDRxx

Next Address

Last Valid Address

Address V1

EIM_WE_B

EIM_LBA_B

EIM_OE_B

WE39

WE35

WE37

WE40

WE36

WE38

EIM_EBx_B

WE44

D(V1)

EIM_DATAxx[7:0]

EIM_DTACK_B

WE43

WE48

WE47

Figure 20. DTACK Mode Read Access (DAP=0)

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Electrical Characteristics

EIM_CSx_B

WE31

WE32

WE34

WE40

EIM_ADDRxx

EIM_WE_B

Next Address

Last Valid Address

Address V1

WE33

WE39

EIM_LBA_B

EIM_OE_B

EIM_EBx_B

WE45

WE41

WE46

WE42

EIM_DATAxx

D(V1)

WE48

EIM_DTACK_B

WE47

Figure 21. DTACK Mode Write Access (DAP=0)

1 2

,

Table 44. EIM Asynchronous Timing Parameters Relative to Chip Select

DeterminationbySynchronous

Ref No.

Parameter

Min

Max

Unit

measured parameters

WE31 EIM_CSx_B valid to Address

Valid

WE4-WE6-CSA×t

-3.5-CSA×t

3.5-CSA×t

3.5-CSN×t

ns

WE32 Address Invalid to EIM_CSx_B

Invalid

WE7-WE5-CSN× t

-3.5-CSN×t

ns

WE32A EIM_CSx_B valid to Address

(muxed Invalid

A/D)

t+WE4-WE7+

(ADVN+ADVA+1-CSA)×t

t - 3.5+(ADVN+A t + 3.5+(ADVN+ADVA+ ns

DVA+1-CSA)×t 1-CSA)×t

WE33 EIM_CSx_B Valid to EIM_WE_B WE8-WE6+(WEA-WCSA)×t -3.5+(WEA-WCS 3.5+(WEA-WCSA)×t

ns

Valid

A)×t

WE34 EIM_WE_B Invalid to

EIM_CSx_B Invalid

WE7-WE9+(WEN-WCSN)×t -3.5+(WEN-WCS 3.5+(WEN-WCSN)×t

N)×t

WE35 EIM_CSx_B Valid to EIM_OE_B WE10- WE6+(OEA-RCSA)×t -3.5+(OEA-RCS 3.5+(OEA-RCSA)×t

Valid A)×t

WE35A EIM_CSx_B Valid to EIM_OE_B WE10-WE6+(OEA+RADVN+R -3.5+(OEA+RAD 3.5+(OEA+RADVN+RA ns

(muxed Valid

A/D)

ADVA+ADH+1-RCSA)×t

VN+RADVA+ADH DVA+ADH+1-RCSA)×t

+1-RCSA)×t

WE36 EIM_OE_B Invalid to

EIM_CSx_B Invalid

WE7-WE11+(OEN-RCSN)×t -3.5+(OEN-RCS 3.5+(OEN-RCSN)×t

N)×t

ns

WE37 EIM_CSx_BValidtoEIM_EBx_B WE12-WE6+(RBEA-RCSA)× t -3.5+(RBEA- RC 3.5+(RBEA - RCSA)×t ns

Valid (Read access)

SA)×t

WE38 EIM_EBx_B Invalid to

EIM_CSx_B Invalid (Read

access)

WE7-WE13+(RBEN-RCSN)×t

-3.5+

(RBEN-RCSN)×t

3.5+(RBEN-RCSN)×t ns

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1 2

,

Table 44. EIM Asynchronous Timing Parameters Relative to Chip Select (continued)

DeterminationbySynchronous

Ref No.

Parameter

Min

Max

Unit

measured parameters

WE39 EIM_CSx_B Valid to

EIM_LBA_B Valid

WE14-WE6+(ADVA-CSA)×t

-3.5+

(ADVA-CSA)×t

3.5+(ADVA-CSA)×t

ns

WE40 EIM_LBA_B Invalid to

EIM_CSx_B Invalid (ADVL is

asserted)

WE7-WE15-CSN×t

-3.5-CSN×t

3.5-CSN×t

ns

WE40A EIM_CSx_B Valid to

(muxed EIM_LBA_B Invalid

A/D)

WE14-WE6+(ADVN+ADVA+1- -3.5+(ADVN+AD

3.5+(ADVN+ADVA

CSA)×t

VA+1-CSA)×t

+1-CSA)×t

WE41 EIM_CSx_B Valid to Output Data

Valid

WE16-WE6-WCSA×t

-3.5-WCSA×t

3.5-WCSA×t

WE41A EIM_CSx_B Valid to Output Data WE16-WE6+(WADVN+WADVA -3.5+(WADVN+ 3.5+(WADVN+WADVA ns

(muxed Valid

A/D)

+ADH+1-WCSA)×t

WADVA

+ADH+1-WCSA)

×t

+ADH+1-WCSA)×t

WE42 Output Data Invalid to

EIM_CSx_B Invalid

WE17-WE7-CSN×t

-3.5-CSN×t

3.5-CSN×t

ns

MAXCO Output maximum delay from

internal driving

10

—

10

EIM_ADDRxx/controlflip-flopsto

chip outputs.

MAXCSO Output maximum delay from

internal chip selects driving

10

5

—

10

5

ns

flip-flops to EIM_CSx_B out.

MAXDI EIM_DATAxx MAXIMUM delay

from chip input data to its internal

flip-flop

WE43 Input Data Valid to EIM_CSx_B

Invalid

MAXCO-MAXCSO+MAXDI MAXCO-MAXCS

O+MAXDI

—

ns

WE44 EIM_CSx_B Invalid to Input Data

Invalid

0

WE45 EIM_CSx_BValidtoEIM_EBx_B WE12-WE6+(WBEA-WCSA)×t -3.5+(WBEA-WC 3.5+(WBEA-WCSA)×t ns

Valid (Write access)

SA)×t

WE46 EIM_EBx_B Invalid to

EIM_CSx_B Invalid (Write

access)

WE7-WE13+(WBEN-WCSN)×t -3.5+(WBEN-WC 3.5+(WBEN-WCSN)×t ns

SN)×t

MAXDTI Maximum delay from

EIM_DTACK_B input to its

internal flip-flop + 2 cycles for

synchronization

10

—

10

ns

WE47 EIM_DTACK_B Active to

EIM_CSx_B Invalid

MAXCO-MAXCSO+MAXDTI MAXCO-MAXCS

O+MAXDTI

—

ns

WE48 EIM_CSx_B Invalid to

EIM_DTACK_B invalid

0

1

For more information on configuration parameters mentioned in this table, see the i.MX 6SoloX Applications Processor

Reference Manual (IMX6SXRM).

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2

In this table:

t means clock period from axi_clk frequency.

CSA means register setting for WCSA when in write operations or RCSA when in read operations.

CSN means register setting for WCSN when in write operations or RCSN when in read operations.

ADVN means register setting for WADVN when in write operations or RADVN when in read operations.

ADVA means register setting for WADVA when in write operations or RADVA when in read operations.

4.10 Multi-mode DDR Controller (MMDC)

The Multi-mode DDR Controller is a dedicated interface to DDR3/DDR3L/LPDDR2 SDRAM.

4.10.1 MMDC Compatibility with JEDEC-Compliant SDRAMs

The i.MX 6SoloX MMDC supports the following memory types:

•

LPDDR2 SDRAM compliant to JESD209-2B LPDDR2 JEDEC standard release June, 2009

DDR3 SDRAM compliant to JESD79-3D DDR3 JEDEC standard release April, 2008

MMDC operation with the standards stated above is contingent upon the board DDR design adherence to

the DDR design and layout requirements stated in the Hardware Development Guide for i.MX 6SoloX

Application Processors (IMX6SXHDG).

4.10.2 MMDC Supported DDR3/LPDDR2 Configurations

The table below shows the supported DDR3/LPDDR2 configurations:

Table 45. i.MX 6SoloX Supported DDR3/LPDDR2 Configurations

Parameter

Min

Max

Unit

LPDDR2

JEDEC LPDDR2 Device Speed Grade¹

JEDEC LPDDR2 Device Bus Width

JEDEC LPDDR2 Device Count²

LPDDR2-800

—

x32

2

—

Bits

x16

1

Devices

DDR3/DDR3L

JEDEC DDR3/DDR3L Device Speed Grade³

DDR3-800

—

x32

2

—

Bits

JEDEC DDR3/DDR3L Device Bus Width

JEDEC DDR3/DDR3L Device Count⁴

x16

1

Devices

1

2

3

4

Higher speed grade memories are supported as long as they are backward compatible with the speed grade shown.

Supported configurations are one 32-bit DDR memory or two 16-bit DDR memories.

Higher speed grade memories are supported as long as they are backward compatible with the speed grade shown.

Supported configurations are one 32-bit DDR memory or two 16-bit DDR memories.

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4.11 General-Purpose Media Interface (GPMI) Timing

The i.MX 6SoloX GPMI controller is a flexible interface NAND Flash controller with 8-bit data width, up

to 200 MB/s I/O speed and individual chip select.

It supports Asynchronous timing mode, Source Synchronous timing mode and Samsung Toggle timing

mode separately described in the following subsections.

4.11.1 Asynchronous Mode AC Timing (ONFI 1.0 Compatible)

Asynchronous mode AC timings are provided as multiplications of the clock cycle and fixed delay. The

maximum I/O speed of GPMI in asynchronous mode is about 50 MB/s. Figure 22 through Figure 25

depicts the relative timing between GPMI signals at the module level for different operations under

asynchronous mode. Table 46 describes the timing parameters (NF1–NF17) that are shown in the figures.

NF2

NF1

.!.$?#,%

NF3

NF4

.!.$?#%ꢀ?"

.!.$?7%?"

NF5

.!.$?!,%

NF6

NF8

Command

NF7

NF9

.!.$?$!4!XX

Figure 22. Command Latch Cycle Timing Diagram

NF1

.!.$?#,%

NF3

.!.$?#%ꢀ?"

.!.$?7%?"

NF10

NF5

NF11

NF7

.!.$?!,%

NF6

NF8

Address

NF9

NAND_DATAxx

Figure 23. Address Latch Cycle Timing Diagram

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Electrical Characteristics

NF1

.!.$?#,%

.!.$?#%ꢀ?"

.!.$?7%?"

NF3

NF10

NF5

NF11

NF7

NF6

.!.$?!,%

NF8

Data to NF

NF9

.!.$?$!4!XX

Figure 24. Write Data Latch Cycle Timing Diagram

.!.$?#,%

.!.$?#%ꢀ?"

NF14

NF15

NF13

.!.$?2%?"

.!.$?2%!$9?"

NF12

NF16

NF17

Data from NF

.!.$?$!4!XX

Figure 25. Read Data Latch Cycle Timing Diagram (Non-EDO Mode)

.!.$?#,%

.!.$?#%ꢀ?"

NF14

NF13

NF15

.!.$?2%?"

.!.$?2%!$9?"

NF12

NF17

NF16

NAND_DATAxx

Data from NF

Figure 26. Read Data Latch Cycle Timing Diagram (EDO Mode)

1

Table 46. Asynchronous Mode Timing Parameters

Timing

T = GPMI Clock Cycle

ID

Parameter

Symbol

Unit

Min

(AS + DS) × T - 0.12 [see ^2,3

Max

NF1

NF2

NF3

NF4

NF5

NF6

NF7

NAND_CLE setup time

NAND_CLE hold time

NAND_CE0_B setup time

NAND_CE0_B hold time

NAND_WE_B pulse width

NAND_ALE setup time

NAND_ALE hold time

tCLS

tCLH

tCS

]

ns

DH × T - 0.72 [see ²]

(AS + DS + 1) × T [see ^3,2

(DH+1) × T - 1 [see ²]

DS × T [see ²]

]

tCH

tWP

tALS

tALH

(AS + DS) × T - 0.49 [see ^3,2

(DH × T - 0.42 [see ²]

]

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1

Table 46. Asynchronous Mode Timing Parameters (continued)

Timing

T = GPMI Clock Cycle

ID

Parameter

Symbol

Unit

Min

Max

NF8

NF9

Data setup time

Data hold time

tDS

tDH

DS × T - 0.26 [see ²]

DH × T - 1.37 [see ²]

(DS + DH) × T [see ²]

DH × T [see ²]

ns

NF10 Write cycle time

tWC

tWH

tRR⁴

tRP

NF11 NAND_WE_B hold time

NF12 Ready to NAND_RE_B low

NF13 NAND_RE_B pulse width

NF14 READ cycle time

(AS + 2) × T [see ^3,2

]

—

ns

DS × T [see ²]

(DS + DH) × T [see ²]

DH × T [see ²]

tRC

NF15 NAND_RE_B high hold time

NF16 Data setup on read

NF17 Data hold on read

tREH

tDSR

tDHR

—

(DS × T -0.67)/18.38 [see ^5,6

]

0.82/11.83 [see ^5,6

]

—

1

GPMI’s Async Mode output timing can be controlled by the module’s internal registers

HW_GPMI_TIMING0_ADDRESS_SETUP, HW_GPMI_TIMING0_DATA_SETUP, and HW_GPMI_TIMING0_DATA_HOLD.

This AC timing depends on these registers settings. In the table, AS/DS/DH represents each of these settings.

2

3

4

5

6

AS minimum value can be 0, while DS/DH minimum value is 1.

T = GPMI clock period -0.075ns (half of maximum p-p jitter).

NF12 is guaranteed by the design.

Non-EDO mode.

EDO mode, GPMI clock ≈ 100 MHz

(AS=DS=DH=1, GPMI_CTL1 [RDN_DELAY] = 8, GPMI_CTL1 [HALF_PERIOD] = 0).

In EDO mode (Figure 25), NF16/NF17 are different from the definition in non-EDO mode (Figure 24).

They are called tREA/tRHOH (RE# access time/RE# HIGH to output hold). The typical value for them

are 16 ns (max for tREA)/15 ns (min for tRHOH) at 50 MB/s EDO mode. In EDO mode, GPMI will

sample NAND_DATAxx at rising edge of delayed NAND_RE_B provided by an internal DPLL. The delay

value can be controlled by GPMI_CTRL1.RDN_DELAY (see the GPMI chapter of the i.MX 6SoloX

Applications Processor Reference Manual (IMX6SXRM)). The typical value of this control register is 0x8

at 50 MT/s EDO mode. But if the board delay is big enough and cannot be ignored, the delay value should

be made larger to compensate the board delay.

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4.11.2 Source Synchronous Mode AC Timing (ONFI 2.x Compatible)

Figure 27 to Figure 29 show the write and read timing of Source Synchronous Mode.

NF19

NF18

.!.$?#%?"

NF23

NAND_CLE

NF26

NF25

NF24

NAND_ALE

NF25 NF26

NAND_WE/RE_B

NF22

NAND_CLK

NAND_DQS

Output enable

NF20

NF21

CMD

ADD

NAND_DATA[7:0]

Output enable

Figure 27. Source Synchronous Mode Command and Address Timing Diagram

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NF19

NF18

.!.$?#%ꢀ?"

.!.$?#,%

NF23

NF24

NF25

NF26

.!.$?!,%

NAND_WE/RE_B

NF22

.!.$?#,+

.!.$?$13

NF27

.!.$?$13

Output enable

NF29

.!.$?$1;ꢁꢂꢀ=

NF28

.!.$?$1;ꢁꢂꢀ=

Output enable

Figure 28. Source Synchronous Mode Data Write Timing Diagram

NF18

NF19

.!.$?#%?"

.!.$?#,%

NF24

NF23

NF26

NF25

NAND_ALE

NF25

.!.$?7%ꢃ2%

NF25

NF22

NF26

.!.$?#,+

.!.$?$13

/UTPUT ENABLE

.!.$?$!4!;ꢁꢂꢀ=

/UTPUT ENABLE

Figure 29. Source Synchronous Mode Data Read Timing Diagram

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Electrical Characteristics

.!.$?$13

NF30

.!.$?$!4!;ꢁꢂꢀ=

D0

D1

D2

D3

NF30

NF31

Figure 30. NAND_DQS/NAND_DQ Read Valid Window

1

Table 47. Source Synchronous Mode Timing Parameters

Timing

T = GPMI Clock Cycle

ID

Parameter

Symbol

Unit

Min

Max

2

NF18 NAND_CE0_B access time

NF19 NAND_CE0_B hold time

tCE

tCH

CE_DELAY × T - 0.79 [see ]

0.5 × tCK - 0.63 [see ²]

0.5 × tCK - 0.05

ns

—

NF20 Command/address NAND_DATAxx setup time

NF21 Command/address NAND_DATAxx hold time

NF22 clock period

tCAS

tCAH

tCK

0.5 × tCK - 1.23

—

NF23 preamble delay

tPRE

tPOST

tCALS

tCALH

tDQSS

—

PRE_DELAY × T - 0.29 [see ²]

POST_DELAY × T - 0.78 [see ²]

0.5 × tCK - 0.86

NF24 postamble delay

NF25 NAND_CLE and NAND_ALE setup time

NF26 NAND_CLE and NAND_ALE hold time

NF27 NAND_CLK to first NAND_DQS latching transition

NF28 Data write setup

0.5 × tCK - 0.37

T - 0.41 [see ²]

0.25 × tCK - 0.35

NF29 Data write hold

—

0.25 × tCK - 0.85

NF30 NAND_DQS/NAND_DQ read setup skew

—

2.06

1.95

NF31 NAND_DQS/NAND_DQ read hold skew

—

1

2

GPMI’s source synchronous mode output timing can be controlled by the module’s internal registers

GPMI_TIMING2_CE_DELAY,GPMI_TIMING_PREAMBLE_DELAY,GPMI_TIMING2_POST_DELAY.ThisACtimingdepends

on these registers settings. In the table, CE_DELAY/PRE_DELAY/POST_DELAY represents each of these settings.

T = tCK(GPMI clock period) -0.075ns (half of maximum p-p jitter).

For DDR Source sync mode, Figure 30 shows the timing diagram of NAND_DQS/NAND_DATAxx read

valid window. The typical value of tDQSQ is 0.85ns (max) and 1ns (max) for tQHS at 200MB/s. GPMI

will sample NAND_DATA[7:0] at both rising and falling edge of an delayed NAND_DQS signal, which

can be provided by an internal DPLL. The delay value can be controlled by GPMI register

GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET (see the GPMI chapter of the i.MX 6SoloX

Applications Processor Reference Manual (IMX6SXRM)). Generally, the typical delay value of this

register is equal to 0x7 which means 1/4 clock cycle delay expected. But if the board delay is big enough

and cannot be ignored, the delay value should be made larger to compensate the board delay.

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4.11.3 Samsung Toggle Mode AC Timing

4.11.3.1 Command and Address Timing

NOTE

Samsung Toggle Mode command and address timing is the same as ONFI

1.0 compatible Async mode AC timing. See Section 4.11.1, “Asynchronous

Mode AC Timing (ONFI 1.0 Compatible),” for details.

4.11.3.2 Read and Write Timing

DEV?CLK

ꢀ

.!.$?#%X?"

.!.$?#,%

.!.$?!,%

ꢀ

ꢄ

.!.$?7%?"

.!.$?2%?"

.!.$?$13

.&ꢇꢉ

.&ꢇꢈ

ꢀꢅꢆ T#+

.!.$?$!4!;ꢁꢂꢀ=

Figure 31. Samsung Toggle Mode Data Write Timing

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Electrical Characteristics

DEV?CLK

.!.$?#%X?"

.& ꢄꢊ

.!.$?#,%

.!.$?!,%

ꢄ T #+

ꢄ

.&ꢇꢉ

.!.$?7%?"

.!.$?2%?"

ꢄ T #+

.& ꢇꢈ

ꢄ T #+

.!.$?$13

.!.$?$!4!;ꢁꢂꢀ=

Figure 32. Samsung Toggle Mode Data Read Timing

1

Table 48. Samsung Toggle Mode Timing Parameters

Timing

T = GPMI Clock Cycle

Min

ID

Parameter

Symbol

Unit

Max

NF1 NAND_CLE setup time

NF2 NAND_CLE hold time

NF3 NAND_CE0_B setup time

NF4 NAND_CE0_B hold time

NF5 NAND_WE_B pulse width

NF6 NAND_ALE setup time

NF7 NAND_ALE hold time

tCLS

tCLH

tCS

(AS + DS) × T - 0.12 [see ^2,3

DH × T - 0.72 [see ²]

(AS + DS) × T - 0.58 [see ^3,2

DH × T - 1 [see ²]

]

—

ns

]

tCH

tWP

tALS

tALH

DS × T [see ²]

(AS + DS) × T - 0.49 [see ^3,2

DH × T - 0.42 [see ²]

DS × T - 0.26 [see ²]

DH × T - 1.37 [see ²]

]

NF8 Command/address NAND_DATAxx setup time tCAS

NF9 Command/address NAND_DATAxx hold time

NF18 NAND_CEx_B access time

NF22 clock period

tCAH

tCE

CE_DELAY × T [see ^4,2

]

—

tCK

—

NF23 preamble delay

tPRE

PRE_DELAY × T [see ^5,2

]

NF24 postamble delay

tPOST POST_DELAY × T +0.43 [see ²]

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Table 48. Samsung Toggle Mode Timing Parameters (continued)

Timing

T = GPMI Clock Cycle

ID

Parameter

Symbol

Unit

Min

Max

NF28 Data write setup

NF29 Data write hold

tDS⁶

tDH⁶

tDQSQ⁷

tQHS⁷

0.25 × tCK - 0.32

—

ns

—

0.25 × tCK - 0.79

NF30 NAND_DQS/NAND_DQ read setup skew

NF31 NAND_DQS/NAND_DQ read hold skew

—

3.18

3.27

1

The GPMI toggle mode output timing can be controlled by the module’s internal registers

HW_GPMI_TIMING0_ADDRESS_SETUP, HW_GPMI_TIMING0_DATA_SETUP, and HW_GPMI_TIMING0_DATA_HOLD.

This AC timing depends on these registers settings. In the table, AS/DS/DH represents each of these settings.

2

3

4

AS minimum value can be 0, while DS/DH minimum value is 1.

T = tCK (GPMI clock period) -0.075ns (half of maximum p-p jitter).

CE_DELAY represents HW_GPMI_TIMING2[CE_DELAY]. NF18 is guaranteed by the design. Read/Write operation is started

with enough time of ALE/CLE assertion to low level.

5

6

7

PRE_DELAY+1) ≥ (AS+DS)

Shown in Figure 31.

Shown in Figure 32.

For DDR Toggle mode, Figure 30 shows the timing diagram of NAND_DQS/NAND_DATAxx read valid

window. The typical value of tDQSQ is 1.4 ns (max) and 1.4 ns (max) for tQHS at 133 MB/s. GPMI will

sample NAND_DATA[7:0] at both rising and falling edge of an delayed NAND_DQS signal, which is

provided by an internal DPLL. The delay value of this register can be controlled by GPMI register

GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET (see the GPMI chapter of the i.MX 6SoloX

Applications Processor Reference Manual (IMX6SXRM)). Generally, the typical delay value is equal to

0x7 which means 1/4 clock cycle delay expected. But if the board delay is big enough and cannot be

ignored, the delay value should be made larger to compensate the board delay.

4.12 External Peripheral Interface Parameters

The following subsections provide information on external peripheral interfaces.

4.12.1 AUDMUX Timing Parameters

The AUDMUX provides a programmable interconnect logic for voice, audio, and data routing between

internal serial interfaces (SSIs) and external serial interfaces (audio and voice codecs). The AC timing of

AUDMUX external pins is governed by the SSI module. For more information, see the respective SSI

electrical specifications found within this document.

4.12.2 CMOS Sensor Interface (CSI) Timing Parameters

The CSI enables the chip to connect directly to external CMOS image sensors, which are classified as

dumb or smart as follows:

•

Dumb sensors only support traditional sensor timing (vertical sync (VSYNC) and horizontal sync

(HSYNC)) and output-only Bayer and statistics data.

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•

Smart sensors support CCIR656 video decoder formats and perform additional processing of the

image (for example, image compression, image pre-filtering, and various data output formats).

The following subsections describe the CSI timing in gated and ungated clock modes.

4.12.2.1 Gated Clock Mode Timing

Figure 33 and Figure 34 shows the gated clock mode timings for CSI, and Table 49 describes the timing

parameters (P1–P7) shown in the figures. A frame starts with a rising/falling edge on CSI_VSYNC

(VSYNC), then CSI_HSYNC (HSYNC) is asserted and holds for the entire line. The pixel clock,

CSI_PIXCLK (PIXCLK), is valid as long as HSYNC is asserted.

CSI_VSYNC

P1

CSI_HSYNC

P7

P2

P5 P6

CSI_PIXCLK

P3 P4

CSI_DATA[15:00]

Figure 33. CSI Gated Clock Mode—Sensor Data at Falling Edge, Latch Data at Rising Edge

CSI_VSYNC

P1

CSI_HSYNC

P7

P2

P6 P5

CSI_PIXCLK

P3 P4

CSI_DATA[15:00]

Figure 34. CSI Gated Clock Mode—Sensor Data at Rising Edge, Latch Data at Falling Edge

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Table 49. CSI Gated Clock Mode Timing Parameters

ID

Parameter

Symbol

Min

Max

Units

P1

P2

P3

P4

P5

P6

P7

CSI_VSYNC to CSI_HSYNC time

CSI_HSYNC setup time

CSI DATA setup time

tV2H

tHsu

tDsu

tDh

33.5

1

—

ns

1

—

ns

CSI DATA hold time

1

—

ns

CSI pixel clock high time

CSI pixel clock low time

CSI pixel clock frequency

tCLKh

tCLKl

fCLK

3.75

—

ns

—

ns

133

MHz

4.12.2.2 Ungated Clock Mode Timing

Figure 35 shows the ungated clock mode timings of CSI, and Table 50 describes the timing parameters

(P1–P6) that are shown in the figure. In ungated mode the CSI_VSYNC and CSI_PIXCLK signals are

used, and the CSI_HSYNC signal is ignored.

CSI_VSYNC

P1

P6

P4 P5

CSI_PIXCLK

P2 P3

CSI_DATA[15:00]

Figure 35. CSI Ungated Clock Mode—Sensor Data at Falling Edge, Latch Data at Rising Edge

Table 50. CSI Ungated Clock Mode Timing Parameters

ID

Parameter

Symbol

Min

Max

Units

P1

P2

P3

P4

P5

P6

CSI_VSYNC to pixel clock time

CSI DATA setup time

tVSYNC

tDsu

33.5

1

—

ns

CSI DATA hold time

tDh

1

—

ns

CSI pixel clock high time

CSI pixel clock low time

CSI pixel clock frequency

tCLKh

tCLKl

fCLK

3.75

—

ns

—

ns

133

MHz

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4.12.3 ECSPI Timing Parameters

This section describes the timing parameters of the ECSPI blocks. The ECSPI have separate timing

parameters for master and slave modes.

4.12.3.1 ECSPI Master Mode Timing

Figure 36 depicts the timing of ECSPI in master mode. Table 51 lists the ECSPI master mode timing

characteristics.

ECSPIx_RDY_B

ECSPIx_SS_B

CS10

CS5

CS2

CS6

CS3

CS1

CS4

ECSPIx_SCLK

ECSPIx_MOSI

ECSPIx_MISO

CS2

CS3

CS7

CS9

CS8

Figure 36. ECSPI Master Mode Timing Diagram

NOTE

ECSPIx_MOSI is always driven (not tri-stated) between actual data

transmissions. This limits the ECSPI to be connected between a single

master and a single slave.

Table 51. ECSPI Master Mode Timing Parameters

ID

Parameter

Symbol

Min

Max Unit

CS1 ECSPIx_SCLK Cycle Time–Read

ECSPIx_SCLK Cycle Time–Write

t_clk

43

15

—

ns

CS2 ECSPIx_SCLK High or Low Time–Read

ECSPIx_SCLK High or Low Time–Write

t_SW

21.5

7

—

ns

CS3 ECSPIx_SCLK Rise or Fall¹

t_RISE/FALL

t_CSLH

—

1

ns

CS4 ECSPIx_SS_B pulse width

Half ECSPIx_SCLK period

CS5 ECSPIx_SS_B Lead Time (CS setup time)

CS6 ECSPIx_SS_B Lag Time (CS hold time)

CS7 ECSPIx_MOSI Propagation Delay (C_LOAD= 20 pF)

CS8 ECSPIx_MISO Setup Time

t_SCS

Half ECSPIx_SCLK period - 4

t_HCS

Half ECSPIx_SCLK period - 2

t_PDmosi

t_Smiso

-1

14

—

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Max Unit

Table 51. ECSPI Master Mode Timing Parameters (continued)

ID

Parameter

Symbol

Min

CS9 ECSPIx_MISO Hold Time

t_Hmiso

t_SDRY

0

5

—

ns

CS10 RDY to ECSPIx_SS_B Time²

1

2

See specific I/O AC parameters Section 4.7, “I/O AC Parameters.”

SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals.

4.12.3.2 ECSPI Slave Mode Timing

Figure 37 depicts the timing of ECSPI in slave mode. Table 52 lists the ECSPI slave mode timing

characteristics.

ECSPIx_SS_B

CS5

CS6

CS2

CS1

CS4

ECSPIx_SCLK

ECSPIx_MISO

CS2

CS9

CS8

CS7

ECSPIx_MOSI

Figure 37. ECSPI Slave Mode Timing Diagram

NOTE

ECSPIx_MISO is always driven (not tri-stated) between actual data

transmissions. This limits the ECSPI to be connected between a single

master and a single slave.

Table 52. ECSPI Slave Mode Timing Parameters

ID

Parameter

Symbol

Min

Max Unit

CS1 ECSPIx_SCLK Cycle Time–Read

ECSPI_SCLK Cycle Time–Write

t_clk

15

43

—

ns

CS2 ECSPIx_SCLK High or Low Time–Read

ECSPIx_SCLK High or Low Time–Write

t_SW

7

21.5

—

ns

CS4 ECSPIx_SS_B pulse width

t_CSLH

t_SCS

Half ECSPIx_SCLK period

—

19

ns

CS5 ECSPIx_SS_B Lead Time (CS setup time)

CS6 ECSPIx_SS_B Lag Time (CS hold time)

CS7 ECSPIx_MOSI Setup Time

5

4

t_HCS

t_Smosi

t_Hmosi

t_PDmiso

CS8 ECSPIx_MOSI Hold Time

CS9 ECSPIx_MISO Propagation Delay (C_LOAD= 20 pF)

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4.12.4 Enhanced Serial Audio Interface (ESAI) Timing Parameters

The ESAI consists of independent transmitter and receiver sections, each section with its own clock

generator. Table 53 shows the interface timing values. The number field in the table refers to timing

signals found in Figure 38 and Figure 39.

Table 53. Enhanced Serial Audio Interface (ESAI) Timing

No.

Characteristics^1,2

Symbol Expression²Min

Max Condition³Unit

62 Clock cycle⁴

t_SSICC

4 × T

30.0

—

i ck

ns

c

63 Clock high period:

ns

• For internal clock

• For external clock

—

2 × T − 9.0

6

15

—

c

2 × T

c

64 Clock low period:

• For internal clock

• For external clock

ns

—

2 × T − 9.0

6

15

—

c

2 × T

c

65 ESAI_RX_CLK rising edge to ESAI_RX_FS out (bl) high

—

17.0

7.0

x ck

i ck a

ns

66 ESAI_RX_CLK rising edge to ESAI_RX_FS out (bl) low

—

17.0

7.0

x ck

i ck a

67 ESAI_RX_CLK rising edge to ESAI_RX_FS out (wr)

high⁵

—

19.0

9.0

x ck

i ck a

68 ESAI_RX_CLK rising edge to ESAI_RX_FS out (wr) low⁵

69 ESAI_RX_CLK rising edge to ESAI_RX_FS out (wl) high

70 ESAI_RX_CLK rising edge to ESAI_RX_FS out (wl) low

—

19.0

9.0

x ck

i ck a

—

16.0

6.0

x ck

i ck a

—

17.0

7.0

x ck

i ck a

71 Data in setup time before ESAI_RX_CLK (SCK in

synchronous mode) falling edge

—

12.0

19.0

—

x ck

i ck

72 Data in hold time after ESAI_RX_CLK falling edge

—

3.5

9.0

—

x ck

i ck

73 ESAI_RX_FS input (bl, wr) high before ESAI_RX_CLK

falling edge⁵

—

2.0

12.0

—

x ck

i ck a

74 ESAI_RX_FS input (wl) high before ESAI_RX_CLK

falling edge

—

2.0

12.0

—

x ck

i ck a

75 ESAI_RX_FS input hold time after ESAI_RX_CLK falling

edge

—

2.5

8.5

—

x ck

i ck a

78 ESAI_TX_CLK rising edge to ESAI_TX_FS out (bl) high

—

18.0

8.0

x ck

i ck

79 ESAI_TX_CLK rising edge to ESAI_TX_FS out (bl) low

—

20.0

10.0

x ck

i ck

80 ESAI_TX_CLK rising edge to ESAI_TX_FS out (wr)

high⁵

—

20.0

10.0

x ck

i ck

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Table 53. Enhanced Serial Audio Interface (ESAI) Timing (continued)

Characteristics^1,2Symbol Expression²Min Max Condition³Unit

No.

81 ESAI_TX_CLK rising edge to ESAI_TX_FS out (wr) low⁵

82 ESAI_TX_CLK rising edge to ESAI_TX_FS out (wl) high

83 ESAI_TX_CLK rising edge to ESAI_TX_FS out (wl) low

—

22.0

12.0

x ck

i ck

ns

—

19.0

9.0

x ck

i ck

—

20.0

10.0

x ck

i ck

84 ESAI_TX_CLK rising edge to data out enable from high

impedance

—

22.0

17.0

x ck

i ck

86 ESAI_TX_CLK rising edge to data out valid

—

18.0

13.0

x ck

i ck

87 ESAI_TX_CLK rising edge to data out high impedance ⁶⁷

—

21.0

16.0

x ck

i ck

89 ESAI_TX_FS input (bl, wr) setup time before

ESAI_TX_CLK falling edge⁵

—

2.0

18.0

—

x ck

i ck

90 ESAI_TX_FS input (wl) setup time before ESAI_TX_CLK

falling edge

—

2.0

18.0

—

x ck

i ck

91 ESAI_TX_FS input hold time after ESAI_TX_CLK falling

edge

—

4.0

5.0

—

x ck

i ck

95 ESAI_RX_HF_CLK/ESAI_TX_HF_CLK clock cycle

—

2 x T_C

—

15

—

ns

96 ESAI_TX_HF_CLK input rising edge to ESAI_TX_CLK

output

18.0

97 ESAI_RX_HF_CLK input rising edge to ESAI_RX_CLK

output

—

18.0

—

ns

1

i ck = internal clock

x ck = external clock

i ck a = internal clock, asynchronous mode

(asynchronous implies that ESAI_TX_CLK and ESAI_RX_CLK are two different clocks)

i ck s = internal clock, synchronous mode

(synchronous implies that ESAI_TX_CLK and ESAI_RX_CLK are the same clock)

2

3

bl = bit length

wl = word length

wr = word length relative

ESAI_TX_CLK(SCKT pin) = transmit clock

ESAI_RX_CLK(SCKR pin) = receive clock

ESAI_TX_FS(FST pin) = transmit frame sync

ESAI_RX_FS(FSR pin) = receive frame sync

ESAI_TX_HF_CLK(HCKT pin) = transmit high frequency clock

ESAI_RX_HF_CLK(HCKR pin) = receive high frequency clock

4

5

For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register.

The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync

signal waveform, but it spreads from one serial clock before the first bit clock (like the bit length frame sync signal), until the

second-to-last bit clock of the first word in the frame.

6

Periodically sampled and not 100% tested.

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62

63

64

ESAI_TX_CLK

(Input/Output)

78

79

ESAI_TX_FS

(Bit)

82

83

Out

ESAI_TX_FS

(Word)

86

84

86

Out

87

First Bit

Last Bit

Data Out

89

91

ESAI_TX_FS

(Bit) In

91

90

ESAI_TX_FS

(Word) In

Figure 38. ESAI Transmitter Timing

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62

63

64

ESAI_RX_CLK

(Input/Output)

65

66

ESAI_RX_FS

(Bit)

Out

69

70

ESAI_RX_FS

(Word)

Out

72

71

Data In

Last Bit

First Bit

75

73

ESAI_RX_FS

(Bit)

In

74

75

ESAI_RX_FS

(Word)

In

Figure 39. ESAI Receiver Timing

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4.12.5 Ultra High Speed SD/SDIO/MMC Host Interface (uSDHC)

AC Timing

This section describes the electrical information of the uSDHC, which includes SD/eMMC4.3 (Single

Data Rate) timing, eMMC4.4/4.41 (Dual Date Rate) timing and SDR104/50(SD3.0) timing.

4.12.5.1 SD/eMMC4.3 (Single Data Rate) AC Timing

Figure 40 depicts the timing of SD/eMMC4.3, and Table 54 lists the SD/eMMC4.3 timing characteristics.

SD4

SD2

SD1

SD5

SDx_CLK

SD3

SD6

Output from uSDHC to card

SDx_DATA[7:0]

SD7

SD8

Input from card to uSDHC

SDx_DATA[7:0]

Figure 40. SD/eMMC4.3 Timing

Table 54. SD/eMMC4.3 Interface Timing Specification

ID

Parameter

Symbols

Min

Max

Unit

Card Input Clock

1

SD1 Clock Frequency (Low Speed)

f_PP

0

400

25/50

20/52

400

—

kHz

MHz

kHz

ns

2

Clock Frequency (SD/SDIO Full Speed/High Speed)

Clock Frequency (MMC Full Speed/High Speed)

Clock Frequency (Identification Mode)

f_PP

3

f_PP

0

f_OD

t_WL

100

7

SD2 Clock Low Time

SD3 Clock High Time

SD4 Clock Rise Time

SD5 Clock Fall Time

t_WH

t_TLH

t_THL

7

—

ns

—

3

ns

3

ns

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx (Reference to CLK)

SD6 uSDHC Output Delay t_OD-6.6

3.6

ns

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Table 54. SD/eMMC4.3 Interface Timing Specification (continued)

Parameter Symbols Min

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx (Reference to CLK)

ID

Max

Unit

SD7 uSDHC Input Setup Time

SD8 uSDHC Input Hold Time⁴

t_ISU

t_IH

2.5

1.5

—

ns

1

2

In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.

In normal (full) speed mode for SD/SDIO card, clock frequency can be any value between 0–25 MHz. In high-speed mode,

clock frequency can be any value between 0–50 MHz.

3

4

In normal (full) speed mode for MMC card, clock frequency can be any value between 0–20 MHz. In high-speed mode, clock

frequency can be any value between 0–52 MHz.

To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.

4.12.5.2 eMMC4.4/4.41 (Dual Data Rate) AC Timing

Figure 41 depicts the timing of eMMC4.4/4.41. Table 55 lists the eMMC4.4/4.41 timing characteristics.

Be aware that only DATA is sampled on both edges of the clock (not applicable to CMD).

SD1

SDx_CLK

SD2

Output from eSDHCv3 to card

SDx_DATA[7:0]

......

SD3

SD4

Input from card to eSDHCv3

SDx_DATA[7:0]

Figure 41. eMMC4.4/4.41 Timing

Table 55. eMMC4.4/4.41 Interface Timing Specification

ID

Parameter

Symbols

Card Input Clock

Min

Max

Unit

SD1 Clock Frequency (eMMC4.4/4.41 DDR)

SD1 Clock Frequency (SD3.0 DDR)

f_PP

0

52

50

MHz

uSDHC Output / Card Inputs SD_CMD, SDx_DATAx (Reference to CLK)

SD2 uSDHC Output Delay t_OD2.8 6.8

uSDHC Input / Card Outputs SD_CMD, SDx_DATAx (Reference to CLK)

ns

SD3 uSDHC Input Setup Time

SD4 uSDHC Input Hold Time

t_ISU

t_IH

1.7

1.5

—

ns

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4.12.5.3 SDR50/SDR104 AC Timing

Figure 42 depicts the timing of SDR50/SDR104, and Table 56 lists the SDR50/SDR104 timing

characteristics.

SD1

SD2

SD3

SCK

SD5

SD4

Output from uSDHC to card

SD7

SD6

SD8

Figure 42. SDR50/SDR104 Timing

Table 56. SDR50/SDR104 Interface Timing Specification

ID

Parameter

Symbols

Min

Max

Unit

Card Input Clock

SD1 Clock Frequency Period

SD2 Clock Low Time

t_CLK

t_CL

4.8

—

ns

0.46 × t_CLK

0.54 × tCLK

SD3 Clock High Time

t_CH

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK)

SD4 uSDHC Output Delay t_OD–3

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK)

SD5 uSDHC Output Delay t_OD–1.6 0.74

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK)

1

ns

SD6 uSDHC Input Setup Time

SD7 uSDHC Input Hold Time

t_ISU

t_IH

2.5

1.5

—

ns

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK)¹

SD8 Card Output Data Window

t_ODW

0.5 × tCLK

—

ns

1

Data window in SDR100 mode is variable.

4.12.5.4 HS200 Mode Timing

Figure 43 depicts the timing of HS200 mode, and Table 57 lists the HS200 timing characteristics.

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SD1

SD2

SD3

SCK

SD4/SD5

8-bit output from uSDHC to eMMC

8-bit input from eMMC to uSDHC

SD8

Figure 43. HS200 Mode Timing

Table 57. HS200 Interface Timing Specification

ID

Parameter

Symbols

Min

Max

Unit

Card Input Clock

SD1 Clock Frequency Period

SD2 Clock Low Time

t_CLK

t_CL

5.0

—

ns

0.46 x t_CLK

0.54 x t_CLK

ns

SD3 Clock High Time

t_CH

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)

uSDHC Output Delay t_OD–1.6 0.74

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)¹

Card Output Data Window t_ODW0.5 x t_CLK

ns

SD5

—

SD8

¹HS200 is for 8 bits while SDR104 is for 4 bits.

4.12.5.5 Bus Operation Condition for 3.3 V and 1.8 V Signaling

Signaling level of SD/eMMC4.3 and eMMC4.4/4.41 modes is 3.3 V. Signaling level of SDR104/SDR50

mode is 1.8 V. The DC parameters for the NVCC_SD1, NVCC_SD2, and NVCC_SD4 supplies are

identical to those shown in Table 24, “Single Voltage GPIO DC Parameters”. The DC parameters for the

NVCC_LOW/NVCC_HIGH are identical to those shown in Table 25, “Dual Voltage GPIO I/O DC

Parameters”.

4.12.6 Ethernet Controller (ENET) AC Electrical Specifications

The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive

at timing specs/constraints for the physical interface.

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4.12.6.1 ENET MII Mode Timing

This subsection describes MII receive, transmit, asynchronous inputs, and serial management signal

timings.

4.12.6.1.1 MII Receive Signal Timing (ENET_RX_DATA3,2,1,0, ENET_RX_EN,

ENET_RX_ER, and ENET_RX_CLK)

The receiver functions correctly up to an ENET_RX_CLK maximum frequency of 25 MHz + 1ꢀ. There

is no minimum frequency requirement.

Figure 44 shows MII receive signal timings. Table 58 describes the timing parameters (M1–M4) shown in

the figure.

M3

ENET_RX_CLK (input)

M4

ENET_RX_DATA3,2,1,0

(inputs)

ENET_RX_EN

ENET_RX_ER

M1

M2

Figure 44. MII Receive Signal Timing Diagram

Table 58. MII Receive Signal Timing

ID

Characteristic¹

Min

Max

Unit

M1

M2

ENET_RX_DATA3,2,1,0, ENET_RX_EN, ENET_RX_ER to

ENET_RX_CLK setup

5

—

ns

ENET_RX_CLK to ENET_RX_DATA3,2,1,0, ENET_RX_EN,

ENET_RX_ER hold

5

—

ns

M3

M4

ENET_RX_CLK pulse width high

ENET_RX_CLK pulse width low

35%

65%

ENET_RX_CLK period

¹ENET_RX_EN, ENET_RX_CLK, and ENET0_RXD0 have the same timing in 10 Mbps 7-wire interface mode.

4.12.6.1.2 MII Transmit Signal Timing (ENET_TX_DATA3,2,1,0, ENET_TX_EN,

ENET_TX_ER, and ENET_TX_CLK)

The transmitter functions correctly up to an ENET_TX_CLK maximum frequency of 25 MHz + 1ꢀ.

There is no minimum frequency requirement.

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Figure 45 shows MII transmit signal timings. Table 59 describes the timing parameters (M5–M8) shown

in the figure.

M7

ENET_TX_CLK (input)

M5

M8

ENET_TX_DATA3,2,1,0

(outputs)

ENET_TX_EN

ENET_TX_ER

M6

Figure 45. MII Transmit Signal Timing Diagram

Table 59. MII Transmit Signal Timing

ID

Characteristic¹

Min

Max

Unit

M5

ENET_TX_CLK to ENET_TX_DATA3,2,1,0, ENET_TX_EN,

ENET_TX_ER invalid

5

—

ns

M6

ENET_TX_CLK to ENET_TX_DATA3,2,1,0, ENET_TX_EN,

ENET_TX_ER valid

—

20

ns

M7

M8

ENET_TX_CLK pulse width high

ENET_TX_CLK pulse width low

35%

65%

ENET_TX_CLK period

¹ENET_TX_EN, ENET_TX_CLK, and ENET0_TXD0 have the same timing in 10-Mbps 7-wire interface mode.

4.12.6.1.3 MII Asynchronous Inputs Signal Timing (ENET_CRS and ENET_COL)

Figure 46 shows MII asynchronous input timings. Table 60 describes the timing parameter (M9) shown in

the figure.

ENET_CRS, ENET_COL

M9

Figure 46. MII Async Inputs Timing Diagram

Table 60. MII Asynchronous Inputs Signal Timing

ID

Characteristic

Min

Max

Unit

M9¹

ENET_CRS to ENET_COL minimum pulse width

1.5

—

ENET_TX_CLK period

¹ENET_COL has the same timing in 10-Mbit 7-wire interface mode.

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4.12.6.1.4 MII Serial Management Channel Timing (ENET_MDIO and ENET_MDC)

The MDC frequency is designed to be equal to or less than 2.5 MHz to be compatible with the IEEE 802.3

MII specification. However the ENET can function correctly with a maximum MDC frequency of

15 MHz.

Figure 47 shows MII asynchronous input timings. Table 61 describes the timing parameters (M10–M15)

shown in the figure.

M14

M15

ENET_MDC (output)

M10

ENET_MDIO (output)

M11

ENET_MDIO (input)

M12

M13

Figure 47. MII Serial Management Channel Timing Diagram

Table 61. MII Serial Management Channel Timing

ID

Characteristic

Min

Max

Unit

M10

ENET_MDC falling edge to ENET_MDIO output invalid (minimum

propagation delay)

0

—

ns

M11

ENET_MDC falling edge to ENET_MDIO output valid

(maximum propagation delay)

—

5

ns

M12

M13

M14

M15

ENET_MDIO (input) to ENET_MDC rising edge setup

ENET_MDIO (input) to ENET_MDC rising edge hold

ENET_MDC pulse width high

18

0

—

ns

40%

60%

ENET_MDC period

ENET_MDC pulse width low

4.12.6.2 RMII Mode Timing

In RMII mode, ENET_CLK is used as the REF_CLK, which is a 50 MHz 50 ppm continuous reference

clock. ENET_RX_EN is used as the ENET_RX_EN in RMII. Other signals under RMII mode include

ENET_TX_EN, ENET_TX_DATA[1:0], ENET_RX_DATA[1:0] and ENET_RX_ER.

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Figure 48 shows RMII mode timings. Table 62 describes the timing parameters (M16–M21) shown in the

figure.

M16

M17

ENET_CLK (input)

M18

ENET_TX_DATA (output)

ENET_TX_EN

M19

ENET_RX_EN (input)

ENET_RX_DATA[1:0]

ENET_RX_ER

M20

M21

Figure 48. RMII Mode Signal Timing Diagram

Table 62. RMII Signal Timing

ID

Characteristic

Min

Max

Unit

M16 ENET_CLK pulse width high

M17 ENET_CLK pulse width low

35%

4

65%

—

ENET_CLK period

M18 ENET_CLK to ENET0_TXD[1:0], ENET_TX_DATA invalid

M19 ENET_CLK to ENET0_TXD[1:0], ENET_TX_DATA valid

ns

—

13

M20 ENET_RX_DATAD[1:0], ENET_RX_EN(ENET_RX_EN), ENET_RX_ER to

ENET_CLK setup

2

—

M21 ENET_CLK to ENET_RX_DATAD[1:0], ENET_RX_EN, ENET_RX_ER hold

2

—

ns

4.12.6.3 Signal Switching Specifications

The following timing specifications meet the requirements for RGMII interfaces for a range of transceiver

devices.

1

Table 63. RGMII Signal Switching Specifications

Symbol

Description

Min

Max

Unit

2

T_cyc

Clock cycle duration

Data to clock output skew at transmitter

7.2

8.8

ns

ps

3

T_skewT

-500

500

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1

Table 63. RGMII Signal Switching Specifications (continued)

Symbol

Description

Data to clock input skew at receiver

Min

Max

Unit

4

T_skewR

Duty_G⁵

Duty_T⁶

Tr/Tf

1

2.6

55

ns

%

ns

Duty cycle for Gigabit

Duty cycle for 10/100T

Rise/fall time (20–80%)

45

40

—

60

0.75

1

For all signals, the maximum load is as follows:

CL = 5 pF at 1.8 V

CL = 10 pF at 2.5 V

See Figure 4 for the test circuit.

2

3

For 10 Mbps and 100 Mbps, T_cycwill scale to 400 ns 40 ns and 40 ns 4 ns respectively.

For all versions of RGMII prior to 2.0; This implies that PC board design will require clocks to be routed such that an additional

trace delay of greater than 1.5 ns and less than 2.0 ns will be added to the associated clock signal. For 10/100, the Max value

is unspecified.

4

5

6

For all versions of RGMII prior to 2.0; This implies that PC board design will require clocks to be routed such that an additional

trace delay of greater than 1.5 ns and less than 2.0 ns will be added to the associated clock signal. For 10/100, the Max value

is unspecified.

Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domain as long

as minimum duty cycle is not violated and stretching occurs for no more than three Tcyc of the lowest speed transitioned

between.

Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domain as long

as minimum duty cycle is not violated and stretching occurs for no more than three Tcyc of the lowest speed transitioned

between.

2'-))?48# ꢋAT TRANSMITTERꢌ

4SKEW4

2'-))?48$N ꢋN ꢍ ꢀ TO ꢈ ꢌ

2'-))?48?#4,

48%.

48%22

4SKEW2

2'-))?48# ꢋAT RECEIVERꢌ

Figure 49. RGMII Transmit Signal Timing Diagram Original

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Electrical Characteristics

2'-))?28# ꢋAT TRANSMITTERꢌ

2'-))?28$N ꢋN ꢍ ꢀ TO ꢈ ꢌ

2'-))?28?#4,

4SKEW4

28$6

28%22

4SKEW2

2'-))?28# ꢋAT RECEIVERꢌ

Figure 50. RGMII Receive Signal Timing Diagram Original

)NTERNAL DELAY

2'-))?28# ꢋSOURCE OF DATAꢌ

4SETUP 4

4 HOLD 4

2'-))?28$N ꢋN ꢍ ꢀ TO ꢈ ꢌ

28$6

28%22

2'-))?28?#4,

4 SETUP 2

4 HOLD 2

2'-))?28# ꢋAT RECEIVERꢌ

Figure 51. RGMII Receive Signal Timing Diagram with Internal Delay

4.12.7 Flexible Controller Area Network (FLEXCAN) AC Electrical

Specifications

The Flexible Controller Area Network (FlexCAN) module is a communication controller implementing

the CAN protocol according to the CAN 2.0B protocol specification. The processor has two CAN modules

available for systems design. Tx and Rx ports for both modules are multiplexed with other I/O pins. See

the IOMUXC chapter of the i.MX 6SoloX Applications Processor Reference Manual (IMX6SXRM) to see

which pins expose Tx and Rx pins; these ports are named CAN_TX and CAN_RX, respectively.

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4.12.8 I²C Module Timing Parameters

2

This section describes the timing parameters of the I C module. Figure 52 depicts the timing of I C

2

module, and Table 64 lists the I C module timing characteristics.

IC11

IC9

IC10

I2Cx_SDA

I2Cx_SCL

IC7

IC4

IC2

IC3

IC8

IC10

IC6

IC11

STOP

START

IC5

IC1

2

Figure 52. I C Bus Timing

2

Table 64. I C Module Timing Parameters

Standard Mode

Fast Mode

ID

Parameter

Unit

Min

Max

Min

Max

IC1

IC2

I2Cx_SCL cycle time

10

4.0

0¹

—

2.5

0.6

0¹

—

µs

Hold time (repeated) START condition

Set-up time for STOP condition

IC3

—

IC4

Data hold time

3.45²

—

0.9²µs

IC5

HIGH Period of I2Cx_SCL Clock

LOW Period of the I2Cx_SCL Clock

Set-up time for a repeated START condition

Data set-up time

4.0

4.7

250

4.7

—

0.6

1.3

0.6

100³

1.3

—

µs

ns

µs

IC6

—

IC7

—

IC8

—

IC9

Bus free time between a STOP and START condition

Rise time of both I2Cx_SDA and I2Cx_SCL signals

Fall time of both I2Cx_SDA and I2Cx_SCL signals

Capacitive load for each bus line (C_b)

—

4

IC10

IC11

IC12

1000

300

400

20 + 0.1C_b300 ns

4

—

20 + 0.1C_b300 ns

—

400 pF

1

A device must internally provide a hold time of at least 300 ns for I2Cx_SDA signal to bridge the undefined region of the falling

edge of I2Cx_SCL.

2

3

The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC5) of the I2Cx_SCL signal.

A Fast-mode I²C-bus device can be used in a Standard-mode I²C-bus system, but the requirement of Set-up time (ID No IC7)

of 250 ns must be met. This automatically is the case if the device does not stretch the LOW period of the I2Cx_SCL signal.

If such a device does stretch the LOW period of the I2Cx_SCL signal, it must output the next data bit to the I2Cx_SDA line

max_rise_time (IC9) + data_setup_time (IC7) = 1000 + 250 = 1250 ns (according to the Standard-mode I²C-bus specification)

before the I2Cx_SCL line is released.

4

C_b= total capacitance of one bus line in pF.

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4.12.9 LCD Controller (LCDIF) Timing Parameters

Figure 53 shows the LCDIF timing and Table 65 lists the timing parameters.

Figure 53. LCD Timing

Table 65. LCD Timing Parameters

ID

Parameter

Symbol

tCLK(LCD)

Min Max Unit

L1

L2

L3

L4

L5

L6

L7

LCD pixel clock frequency

-

150 MHz

LCD pixel clock high (falling edge capture)

tCLKH(LCD)

3

-

ns

LCD pixel clock low (rising edge capture)

tCLKL(LCD)

3

LCD pixel clock high to data valid (falling edge capture)

LCD pixel clock low to data valid (rising edge capture)

LCD pixel clock high to control signals valid (falling edge capture)

LCD pixel clock low to control signals valid (rising edge capture)

td(CLKH-DV)

td(CLKL-DV)

-1

1

td(CLKH-CTRLV)

td(CLKL-CTRLV)

4.12.9.1 LCDIF Display Interface Signal Mapping

Table 66. LCDIF Display Interface Signal Mapping

8-bit DOTCLK

LCD IF

16-bit DOTCLK

LCD IF

18-bit DOTCLK

LCD IF

24-bit DOTCLK

8-bit DVI

LCD IF

Pin Name

LCD_RS

LCD IF

—

CCIR_CLK

LCD_CS

—

LCD_WR_RWn

LCD_RD_E

—

LCD_VSYNC* (two

options)

LCD_VSYNC

LCD_HSYNC

—

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Pin Name

Table 66. LCDIF Display Interface Signal Mapping (continued)

8-bit DOTCLK

LCD IF

16-bit DOTCLK

LCD IF

18-bit DOTCLK

LCD IF

24-bit DOTCLK

LCD IF

8-bit DVI

LCD IF

LCD_DOTCLK

LCD_ENABLE

LCD_D23

LCD_DOTCLK

—

LCD_ENABLE

R[7]

—

LCD_D22

R[6]

LCD_D21

—

R[5]

LCD_D20

—

R[4]

LCD_D19

—

R[3]

LCD_D18

—

R[2]

LCD_D17

—

R[5]

R[4]

R[3]

R[2]

R[1]

LCD_D16

—

R[0]

LCD_D15 / VSYNC*

LCD_D14 / HSYNC**

R[4]

R[3]

R[2]

G[7]

G[6]

LCD_D13 /

G[5]

LCD_DOTCLK**

LCD_D12 / ENABLE**

LCD_D11

LCD_D10

LCD_D9

—

R[1]

R[0]

G[5]

G[4]

G[3]

—

G[5]

G[4]

G[2]

—

G[4]

G[3]

G[1]

—

LCD_D8

—

G[3]

G[2]

G[0]

—

LCD_D7

R[2]

R[1]

R[0]

G[2]

G[1]

G[0]

B[1]

G[2]

G[1]

B[7]

Y/C[7]

Y/C[6]

Y/C[5]

Y/C[4]

Y/C[3]

Y/C[2]

Y/C[1]

Y/C[0]

—

LCD_D6

G[1]

G[0]

B[6]

LCD_D5

G[0]

B[5]

LCD_D4

B[4]

LCD_D3

B[3]

LCD_D2

B[2]

LCD_D1

B[1]

LCD_D0

B[0]

LCD_RESET

LCD_BUSY /

LCD_VSYNC

LCD_BUSY (OR

optional

LCD_BUSY (OR

optional

LCD_BUSY (OR

optional

LCD_BUSY (OR

optional

—

LCD_VSYNC)

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4.12.10 LVDS Display Bridge (LDB) Module Parameters

The LVDS interface complies with TIA/EIA 644-A standard. For more details, see TIA/EIA STANDARD

644-A, “Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits”.

Table 67. LVDS Display Bridge (LDB) Electrical Specification

Parameter

Symbol

Test Condition

Min Max Units

DifferentialVoltageOutputVoltage V_OD100 Ω Differential load

250 450

Voh 100 Ω differential load (0 V Diff—Output High Voltage static) 1.25 1.6

Vol 100 Ω differential load (0 V Diff—Output Low Voltage static) 0.9 1.25

mV

V

Output Voltage High

Output Voltage Low

Offset Static Voltage

V

V_OSTwo 49.9 Ω resistors in series between N-P terminal, with

output in either Zero or One state, the voltage measured

between the 2 resistors.

1.15 1.375

V

VOS Differential

V_OSDIFFDifference in V_OSbetween a One and a Zero state

ISA ISB With the output common shorted to GND

-50

-24

50

24

mV

mA

mV

Output short circuited to GND

VT Full Load Test

VTLoad 100 Ω Differential load with a 3.74 kΩ load between GND and 247 454

IO Supply Voltage

4.12.11 PCIe PHY Parameters

The PCIe interface complies with PCIe specification Gen2 x1 lane and supports the PCI Express 1.1/2.0

standard.

4.12.11.1 PCIE_REXT Reference Resistor Connection

The impedance calibration process requires connection of reference resistor 200 Ω. 1ꢀ precision resistor

on PCIE_REXT pads to ground. It is used for termination impedance calibration.

4.12.12 Pulse Width Modulator (PWM) Timing Parameters

This section describes the electrical information of the PWM. The PWM can be programmed to select one

of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before

being input to the counter. The output is available at the pulse-width modulator output (PWMx_OUT)

external pin.

Figure 54 depicts the timing of the PWM, and Table 68 lists the PWM timing parameters.

0ꢄ

0ꢇ

07-N?/54

Figure 54. PWM Timing

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Table 68. PWM Output Timing Parameters

ID

Parameter

Min

Max

Unit

—

P1

P2

PWM Module Clock Frequency

PWM output pulse width high

PWM output pulse width low

0

ipg_clk

—

MHz

ns

15

—

ns

4.12.13 QUAD SPI (QSPI) Timing Parameters

Measurement conditions are with 35 pF load on SCK and SIO pins and input slew rate of 1 V/ns.

4.12.13.1 SDR Mode

1

2

3

4

5

6

7

QSPI1x_SCLK

Tis Tih

QSPI1x_DATA[0:3]

Figure 55. QuadSPI Input/Read Timing (SDR mode with internal sampling)

Table 69. QuadSPI Input/Read Timing (SDR mode with internal sampling)

Value

Symbol

Parameter

Unit

Min

Max

T_is

T_ih

Setup time for incoming data

8.67

0

—

ns

Hold time requirement for incoming data

Tis

Tih

Q S P I1 x _ D A TA [0 :3 ]

Q S P I1 x _ D Q S

Figure 56. QuadSPI Input/Read Timing (SDR mode with loopback DQS sampling)

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Table 70. QuadSPI Input/Read Timing (SDR mode with loopback DQS sampling)

Value

Symbol

Parameter

Unit

Min

Max

T_is

T_ih

Setup time for incoming data

Hold time requirement for incoming data

1

—

ns

NOTE

•

For internal sampling, the timing values assumes using sample point 0,

that is QuadSPIx_SMPR[SDRSMP] = 0.

For loopback DQS sampling, the data strobe is output to the DQS pad

together with the serial clock. The data strobe is looped back from DQS

pad and used to sample input data.

Figure 57. QuadSPI Output/Write Timing (SDR mode)

Table 71. QuadSPI Output/Write Timing (SDR mode)

Value

Symbol

Parameter

Unit

Min

Max

T_ov

T_oh

T_ck

Output Data Valid

—

0

3.2

—

ns

Output Data Hold

SCK clock period

12.5

3

ns

T_css

T_csh

Chip select output setup time

Chip select output hold time

SCK cycle(s)

3

NOTE

Tcss and Tcsh are configured by the QuadSPIx_FLSHCR register, the

default values of 3 are shown on the timing. Please refer to Reference

Manual for further details.

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4.12.13.2 DDR Mode

Figure 58. QuadSPI Input/Read Timing (DDR mode with internal sampling)

Table 72. QuadSPI Input/Read Timing (DDR mode with internal sampling)

Value

Symbol

Parameter

Unit

Min

Max

T_is

T_ih

Setup time for incoming data

8.67

0

—

ns

Hold time requirement for incoming data

Figure 59. QuadSPI Input/Read Timing (DDR mode with loopback DQS sampling)

Table 73. QuadSPI Input/Read Timing (DDR mode with loopback DQS sampling)

Value

Symbol

Parameter

Unit

Min

Max

T_is

T_ih

Setup time for incoming data

1

—

ns

Hold time requirement for incoming data

NOTE

•

For internal sampling, the timing values assumes sample point 0, that is

QuadSPIx_SMPR[DDRSMP] = 0.

For loopback DQS sampling, the data strobe is output to the DQS pad

together with the serial clock. The data strobe is looped back from the

DQS pad and used to sample input data.

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Figure 60. QuadSPI Output/Write Timing (DDR mode)

Table 74. QuadSPI Output/Write Timing (DDR mode)

Value

Symbol

Parameter

Unit

Min

Max

T_ov

T_oh

T_ck

Output Data Valid

—

1

2

ns

Output Data Hold

—

SCK clock period

22

3

ns

T_css

T_csh

Chip select output setup time

Chip select output hold time

SCK cycle(s)

3

NOTE

Tcss and Tcsh are configured by the QuadSPIx_FLSHCR register, the

default register values of 3 are shown on the timing. Please refer to

Reference Manual for further details.

4.12.14 SAI/I2S Switching Specifications

This sections provides the AC timings for the SAI in master (clocks driven) and slave (clocks input) modes.

All timings are given for non-inverted serial clock polarity (SAI_TCR[TSCKP] = 0, SAI_RCR[RSCKP]

= 0) and non-inverted frame sync (SAI_TCR[TFSI] = 0, SAI_RCR[RFSI] = 0). If the polarity of the clock

and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal

(SAI_BCLK) and/or the frame sync (SAI_FS) shown in the figures below.

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Figure 61. SAI Timing—Master Modes

Table 75. Master Mode SAI Timing

Num

Characteristic

Min

Max

Unit

S1

S2

S3

S4

S5

S6

S7

S8

S9

S10

SAI_MCLK cycle time

SAI_MCLK pulse width high/low

20

40%

2 x S1

40%

—

60%

—

ns

MCLK period

SAI_BCLK cycle time

ns

SAI_BCLK pulse width high/low

SAI_BCLK to SAI_FS output valid

SAI_BCLK to SAI_FS output invalid

SAI_BCLK to SAI_TXD valid

60%

15

BCLK period

ns

0

—

15

SAI_BCLK to SAI_TXD invalid

0

—

SAI_RXD/SAI_FS input setup before SAI_BCLK

SAI_RXD/SAI_FS input hold after SAI_BCLK

15

—

0

—

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Figure 62. SAI Timing—Slave Modes

Table 76. Slave Mode SAI Timing

Num

Characteristic

SAI_BCLK cycle time (input)

Min

Max

Unit

S11

S12

S13

S14

S15

S16

S17

S18

S19

20

40%

10

2

—

60%

—

ns

SAI_BCLK pulse width high/low (input)

SAI_FS input setup before SAI_BCLK

SAI_FA input hold after SAI_BCLK

BCLK period

ns

—

SAI_BCLK to SAI_TXD/SAI_FS output valid

SAI_BCLK to SAI_TXD/SAI_FS output invalid

SAI_RXD setup before SAI_BCLK

—

0

20

—

10

2

—

SAI_RXD hold after SAI_BCLK

—

I2S_TX_FX input assertion to I2S_TXD output valid¹

—

25

1

Applies to first bit in each frame and only if the TCR4[FSE] bit is clear

4.12.15 SCAN JTAG Controller (SJC) Timing Parameters

Figure 63 depicts the SJC test clock input timing. Figure 64 depicts the SJC boundary scan timing.

Figure 65 depicts the SJC test access port. Signal parameters are listed in Table 77.

SJ1

SJ2

JTAG_TCK

(Input)

VM

VIH

VIL

SJ3

Figure 63. Test Clock Input Timing Diagram

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JTAG_TCK

(Input)

VIH

SJ5

VIL

SJ4

Input Data Valid

Data

Inputs

SJ6

Data

Outputs

Output Data Valid

SJ7

SJ6

Data

Outputs

Data

Outputs

Output Data Valid

Figure 64. Boundary Scan (JTAG) Timing Diagram

JTAG_TCK

(Input)

VIH

VIL

SJ8

Input Data Valid

SJ9

JTAG_TDI

JTAG_TMS

(Input)

SJ10

SJ11

SJ10

JTAG_TDO

(Output)

Output Data Valid

JTAG_TDO

(Output)

JTAG_TDO

(Output)

Output Data Valid

Figure 65. Test Access Port Timing Diagram

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JTAG_TCK

(Input)

SJ13

JTAG_TRST_B

(Input)

SJ12

Figure 66. JTAG_TRST_B Timing Diagram

Table 77. JTAG Timing

All Frequencies

ID

Parameter^1,2

Unit

Min

Max

1

SJ0

SJ1

JTAG_TCK frequency of operation 1/(3•T_DC

)

0.001

45

22.5

—

22

—

3

MHz

ns

JTAG_TCK cycle time in crystal mode

2

SJ2

JTAG_TCK clock pulse width measured at V_M

JTAG_TCK rise and fall times

SJ3

SJ4

Boundary scan input data set-up time

Boundary scan input data hold time

JTAG_TCK low to output data valid

JTAG_TCK low to output high impedance

JTAG_TMS, JTAG_TDI data set-up time

JTAG_TMS, JTAG_TDI data hold time

JTAG_TCK low to JTAG_TDO data valid

5

—

40

—

44

—

SJ5

24

—

SJ6

SJ7

—

SJ8

5

SJ9

25

—

SJ10

SJ11

SJ12

SJ13

JTAG_TCK low to JTAG_TDO high impedance

JTAG_TRST_B assert time

—

100

40

JTAG_TRST_B set-up time to JTAG_TCK low

1

2

T

= target frequency of SJC

DC

V_M= mid-point voltage

4.12.16 SPDIF Timing Parameters

The Sony/Philips Digital Interconnect Format (SPDIF) data is sent using the bi-phase marking code. When

encoding, the SPDIF data signal is modulated by a clock that is twice the bit rate of the data signal.

Table 78 and Figure 67 and Figure 68 show SPDIF timing parameters for the Sony/Philips Digital

Interconnect Format (SPDIF), including the timing of the modulating Rx clock (SPDIF_SR_CLK) for

SPDIF in Rx mode and the timing of the modulating Tx clock (SPDIF_ST_CLK) for SPDIF in Tx mode.

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Table 78. SPDIF Timing Parameters

Symbol

Timing Parameter Range

Characteristics

Unit

Min

Max

SPDIF_IN Skew: asynchronous inputs, no specs apply

SPDIF_OUT output (Load = 50pf)

—

0.7

ns

—

1.5

24.2

31.3

• Skew

• Transition rising

• Transition falling

ns

SPDIF_OUT1 output (Load = 30pf)

—

1.5

13.6

18.0

• Skew

• Transition rising

• Transition falling

Modulating Rx clock (SPDIF_SR_CLK) period

SPDIF_SR_CLK high period

srckp

srckph

srckpl

stclkp

stclkph

stclkpl

40.0

16.0

40.0

16.0

—

ns

SPDIF_SR_CLK low period

Modulating Tx clock (SPDIF_ST_CLK) period

SPDIF_ST_CLK high period

SPDIF_ST_CLK low period

srckp

srckpl

srckph

V_M

SPDIF_SR_CLK

V_M

(Output)

Figure 67. SPDIF_SR_CLK Timing Diagram

stclkp

stclkpl

V_M

stclkph

V_M

SPDIF_ST_CLK

(Input)

Figure 68. SPDIF_ST_CLK Timing Diagram

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4.12.17 SSI Timing Parameters

This section describes the timing parameters of the SSI module. The connectivity of the serial

synchronous interfaces are summarized in Table 79.

Table 79. AUDMUX Port Allocation

Port

Signal Nomenclature

Type and Access

AUDMUX port 1

AUDMUX port 2

AUDMUX port 3

AUDMUX port 4

AUDMUX port 5

AUDMUX port 6

AUDMUX port 7

SSI 1

SSI 2

AUD3

AUD4

AUD5

AUD6

SSI 3

Internal

External— LCD or SD4 through IOMUXC

External— ENET or NAND through IOMUXC

External— KPP or SD1 through IOMUXC

External— SD2 or CSI through IOMUXC

Internal

NOTE

The terms WL and BL used in the timing diagrams and tables refer to Word

Length (WL) and Bit Length (BL).

4.12.17.1 SSI Transmitter Timing with Internal Clock

Figure 69 depicts the SSI transmitter internal clock timing and Table 80 lists the timing parameters for

the SSI transmitter internal clock.

.

SS1

SS5

SS4

SS3

SS2

AUDx_TXC

(Output)

SS8

SS6

AUDx_TXFS (bl)

(Output)

SS10

SS12

AUDx_TXFS (wl)

(Output)

SS14

SS17

SS15

SS16

SS18

AUDx_TXD

(Output)

SS43

SS42

SS19

AUDx_RXD

(Input)

Note: AUDx_RXD input in synchronous mode only

Figure 69. SSI Transmitter Internal Clock Timing Diagram

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Table 80. SSI Transmitter Timing with Internal Clock

ID

Parameter

Internal Clock Operation

Min

Max

Unit

SS1

SS2

AUDx_TXC/AUDxRXC clock period

81.4

36.0

—

ns

AUDx_TXC/AUDxRXC clock high period

AUDx_TXC/AUDxRXC clock low period

—

SS4

—

SS6

AUDx_TXC high to AUDx_TXFS (bl) high

AUDx_TXC high to AUDx_TXFS (bl) low

AUDx_TXC high to AUDx_TXFS (wl) high

AUDx_TXC high to AUDx_TXFS (wl) low

AUDx_TXC/AUDxRXC Internal AUDx_TXFS rise time

AUDx_TXC/AUDxRXC Internal AUDx_TXFS fall time

AUDx_TXC high to AUDx_TXD valid from high impedance

AUDx_TXC high to AUDx_TXD high/low

15.0

6.0

SS8

—

SS10

SS12

SS14

SS15

SS16

SS17

SS18

—

6.0

—

15.0

—

AUDx_TXC high to AUDx_TXD high impedance

—

Synchronous Internal Clock Operation

SS42

SS43

AUDx_RXD setup before AUDx_TXC falling

AUDx_RXD hold after AUDx_TXC falling

10.0

0.0

—

ns

NOTE

•

All the timings for the SSI are given for a non-inverted serial clock

polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync

(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have

been inverted, all the timing remains valid by inverting the clock signal

AUDx_TXC/AUDx_RXC and/or the frame sync

AUDx_TXFS/AUDx_RXFS shown in the tables and in the figures.

•

All timings are on Audiomux Pads when SSI is being used for data

transfer.

•

The terms, WL and BL, refer to Word Length (WL) and Bit Length(BL).

For internal Frame Sync operation using external clock, the frame sync

timing is same as that of transmit data (for example, during AC97 mode

of operation).

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4.12.17.2 SSI Receiver Timing with Internal Clock

Figure 70 depicts the SSI receiver internal clock timing and Table 81 lists the timing parameters for the

receiver timing with the internal clock.

SS1

SS3

SS5

SS4

SS2

AUDx_TXC

(Output)

SS9

SS7

AUDx_TXFS (bl)

(Output)

SS11

SS13

AUDx_TXFS (wl)

(Output)

SS20

SS21

AUDx_RXD

(Input)

SS51

SS50

SS47

SS49

SS48

AUDx_RXC

(Output)

Figure 70. SSI Receiver Internal Clock Timing Diagram

Table 81. SSI Receiver Timing with Internal Clock

ID

Parameter

Min

Max

Unit

Internal Clock Operation

SS1

SS2

AUDx_TXC/AUDx_RXC clock period

81.4

36.0

—

ns

AUDx_TXC/AUDx_RXC clock high period

AUDx_TXC/AUDx_RXC clock rise time

AUDx_TXC/AUDx_RXC clock low period

AUDx_TXC/AUDx_RXC clock fall time

AUDx_RXC high to AUDx_TXFS (bl) high

AUDx_RXC high to AUDx_TXFS (bl) low

AUDx_RXC high to AUDx_TXFS (wl) high

AUDx_RXC high to AUDx_TXFS (wl) low

AUDx_RXD setup time before AUDx_RXC low

AUDx_RXD hold time after AUDx_RXC low

SS3

6.0

—

SS4

36.0

—

SS5

6.0

15.0

—

SS7

—

SS9

—

SS11

SS13

SS20

SS21

—

10.0

0.0

—

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Table 81. SSI Receiver Timing with Internal Clock (continued)

ID

Parameter

Min

Max

Unit

Oversampling Clock Operation

SS47

SS48

SS49

SS50

SS51

Oversampling clock period

Oversampling clock high period

15.04

6.0

—

ns

Oversampling clock rise time

Oversampling clock low period

Oversampling clock fall time

3.0

—

6.0

—

3.0

NOTE

•

All the timings for the SSI are given for a non-inverted serial clock

polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync

(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have

been inverted, all the timing remains valid by inverting the clock signal

AUDx_TXC/AUDx_RXC and/or the frame sync

AUDx_TXFS/AUDx_RXFS shown in the tables and in the figures.

•

All timings are on Audiomux Pads when SSI is being used for data

transfer.

•

The terms, WL and BL, refer to Word Length (WL) and Bit Length(BL).

For internal Frame Sync operation using external clock, the frame sync

timing is same as that of transmit data (for example, during AC97 mode

of operation).

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4.12.17.3 SSI Transmitter Timing with External Clock

Figure 71 depicts the SSI transmitter external clock timing and Table 82 lists the timing parameters for

the transmitter timing with the external clock.

SS22

SS23

SS25

SS26

SS24

AUDx_TXC

(Input)

SS27

SS29

AUDx_TXFS (bl)

(Input)

SS33

SS31

AUDx_TXFS (wl)

(Input)

SS39

SS37

SS38

AUDx_TXD

(Output)

SS45

SS44

AUDx_RXD

(Input)

SS46

Note: AUDx_RXD Input in Synchronous mode only

Figure 71. SSI Transmitter External Clock Timing Diagram

Table 82. SSI Transmitter Timing with External Clock

ID

Parameter

External Clock Operation

Min

Max

Unit

SS22

SS23

SS24

SS25

SS26

SS27

SS29

SS31

SS33

SS37

SS38

SS39

AUDx_TXC/AUDx_RXC clock period

81.4

36.0

—

ns

AUDx_TXC/AUDx_RXC clock high period

AUDx_TXC/AUDx_RXC clock rise time

AUDx_TXC/AUDx_RXC clock low period

AUDx_TXC/AUDx_RXC clock fall time

6.0

—

36.0

—

6.0

15.0

—

AUDx_TXC high to AUDx_TXFS (bl) high

AUDx_TXC high to AUDx_TXFS (bl) low

AUDx_TXC high to AUDx_TXFS (wl) high

AUDx_TXC high to AUDx_TXFS (wl) low

AUDx_TXC high to AUDx_TXD valid from high impedance

AUDx_TXC high to AUDx_TXD high/low

AUDx_TXC high to AUDx_TXD high impedance

-10.0

10.0

-10.0

10.0

—

15.0

—

15.0

—

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Table 82. SSI Transmitter Timing with External Clock (continued)

ID

Parameter

Min

Max

Unit

Synchronous External Clock Operation

SS44

SS45

SS46

AUDx_RXD setup before AUDx_TXC falling

10.0

2.0

—

ns

AUDx_RXD hold after AUDx_TXC falling

AUDx_RXD rise/fall time

6.0

NOTE

•

All the timings for the SSI are given for a non-inverted serial clock

polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync

(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have

been inverted, all the timing remains valid by inverting the clock signal

AUDx_TXC/AUDx_RXC and/or the frame sync

AUDx_TXFS/AUDx_RXFS shown in the tables and in the figures.

•

All timings are on Audiomux Pads when SSI is being used for data

transfer.

•

The terms WL and BL refer to Word Length (WL) and Bit Length (BL).

For internal Frame Sync operation using external clock, the frame sync

timing is same as that of transmit data (for example, during AC97 mode

of operation).

4.12.17.4 SSI Receiver Timing with External Clock

Figure 72 depicts the SSI receiver external clock timing and Table 83 lists the timing parameters for the

receiver timing with the external clock.

SS22

SS26

SS25

SS24

SS23

AUDx_TXC

(Input)

SS30

SS28

AUDx_TXFS (bl)

(Input)

SS32

SS35

SS34

AUDx_TXFS (wl)

(Input)

SS41

SS36

SS40

AUDx_RXD

(Input)

Figure 72. SSI Receiver External Clock Timing Diagram

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Table 83. SSI Receiver Timing with External Clock

ID

Parameter

Min

Max

Unit

External Clock Operation

SS22

SS23

SS24

SS25

SS26

SS28

SS30

SS32

SS34

SS35

SS36

SS40

SS41

AUDx_TXC/AUDx_RXC clock period

81.4

36

—

ns

AUDx_TXC/AUDx_RXC clock high period

AUDx_TXC/AUDx_RXC clock rise time

6.0

—

AUDx_TXC/AUDx_RXC clock low period

AUDx_TXC/AUDx_RXC clock fall time

36

—

6.0

15.0

—

AUDx_RXC high to AUDx_TXFS (bl) high

AUDx_RXC high to AUDx_TXFS (bl) low

AUDx_RXC high to AUDx_TXFS (wl) high

AUDx_RXC high to AUDx_TXFS (wl) low

AUDx_TXC/AUDx_RXC External AUDx_TXFS rise time

AUDx_TXC/AUDx_RXC External AUDx_TXFS fall time

AUDx_RXD setup time before AUDx_RXC low

AUDx_RXD hold time after AUDx_RXC low

-10

10

-10

10

—

15.0

—

6.0

—

10

2

—

NOTE

•

All the timings for the SSI are given for a non-inverted serial clock

polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync

(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have

been inverted, all the timing remains valid by inverting the clock signal

AUDx_TXC/AUDx_RXC and/or the frame sync

AUDx_TXFS/AUDx_RXFS shown in the tables and in the figures.

•

All timings are on Audiomux Pads when SSI is being used for data

transfer.

•

The terms WL and BL refer to Word Length (WL) and Bit Length(BL).

For internal Frame Sync operation using external clock, the frame sync

timing is same as that of transmit data (for example, during AC97 mode

of operation).

4.12.18 UART I/O Configuration and Timing Parameters

4.12.18.1 UART RS-232 Serial Mode Timing

The following sections describe the electrical information of the UART module in the RS-232 mode.

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4.12.18.1.1 UART Transmitter

Figure 73 depicts the transmit timing of UART in the RS-232 serial mode, with 8 data bit/1 stop bit

format. Table 84 lists the UART RS-232 serial mode transmit timing characteristics.

Possible

UA1

Parity

Bit

Start

Bit

UARTx_TX_DATA

(output)

STOP

BIT

Bit 7

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Par Bit

UA1

Figure 73. UART RS-232 Serial Mode Transmit Timing Diagram

Table 84. RS-232 Serial Mode Transmit Timing Parameters

ID

Parameter

Symbol

Min

Max

1/F_{baud_rate}+ T_{ref_clk}

Unit

2

UA1 Transmit Bit Time

t_Tbit

1/F_{baud_rate}¹- T_{ref_clk}

—

1

2

F_{baud_rate}: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.

T_{ref_clk}: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).

4.12.18.1.2 UART Receiver

Figure 74 depicts the RS-232 serial mode receive timing with 8 data bit/1 stop bit format. Table 85 lists

serial mode receive timing characteristics.

Possible

Parity

UA2

Bit

Start

Bit

UARTx_RX_DATA

(output)

STOP

BIT

Bit 7

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Par Bit

UA2

Figure 74. UART RS-232 Serial Mode Receive Timing Diagram

Table 85. RS-232 Serial Mode Receive Timing Parameters

ID

Parameter

Symbol

Min

Max

Unit

UA2

Receive Bit Time¹

t_Rbit

1/F_{baud_rate}²- 1/(16

1/F_{baud_rate}

+

—

x F_{baud_rate}

)

1/(16 x F_{baud_rate})

1

2

The UART receiver can tolerate 1/(16 x F_{baud_rate}) tolerance in each bit. But accumulation tolerance in one frame must not

exceed 3/(16 x F_{baud_rate}).

F_{baud_rate}: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.

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4.12.18.1.3 UART IrDA Mode Timing

The following subsections give the UART transmit and receive timings in IrDA mode.

UART IrDA Mode Transmitter

Figure 75 depicts the UART IrDA mode transmit timing, with 8 data bit/1 stop bit format. Table 86 lists

the transmit timing characteristics.

UA4

UA3

UARTx_TX_DAT

A

Start

Bit

STOP

BIT

Bit 0

Bit 1

Possible

Parity

Bit

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Figure 75. UART IrDA Mode Transmit Timing Diagram

Table 86. IrDA Mode Transmit Timing Parameters

ID

Parameter

Symbol

Min

Max

1/F_{baud_rate}+ T_{ref_clk}

Unit

1

UA3

Transmit Bit Time in IrDA mode

Transmit IR Pulse Duration

t_TIRbit

1/F_{baud_rate}

-

—

2

T_{ref_clk}

UA4

t_TIRpulse(3/16) x (1/F_{baud_rate}

- T_{ref_clk}

)

(3/16) x (1/F_{baud_rate}

)

—

+ T_{ref_clk}

1

F_{baud_rate}: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.

T_{ref_clk}: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).

2

UART IrDA Mode Receiver

Figure 76 depicts the UART IrDA mode receive timing, with 8 data bit/1 stop bit format. Table 87 lists

the receive timing characteristics.

UA6

UA5

UARTx_RX_

DATA

(input)

Start

Bit

STOP

BIT

Bit 0

Bit 1

Possible

Parity

Bit

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Figure 76. UART IrDA Mode Receive Timing Diagram

Table 87. IrDA Mode Receive Timing Parameters

ID

Parameter

Symbol

Min

Max

Unit

UA5

Receive Bit Time¹in IrDA mode

t_RIRbit

1/F_{baud_rate}²- 1/(16 1/F_{baud_rate}+ 1/(16 x

—

x F_{baud_rate}

)

F_{baud_rate}

)

UA6

Receive IR Pulse Duration

t_RIRpulse

1.41 μs

(5/16) x (1/F_{baud_rate}

)

—

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1

The UART receiver can tolerate 1/(16 x F_{baud_rate}) tolerance in each bit. But accumulation tolerance in one frame must not

exceed 3/(16 x F_{baud_rate}).

2

F_{baud_rate}: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.

4.12.19 USB HSIC Timings

This section describes the electrical information of the USB HSIC port.

NOTE

In Figure 77, HSIC is a DDR interface and the timing parameters shown

refer to both rising and falling edges.

4.12.19.1 Transmit Timing

Tstrobe

USB_H_STROBE

Todelay

USB_H_DATA

Figure 77. USB HSIC Transmit Waveform

Table 88. USB HSIC Transmit Parameters

Name

Parameter

Min

Max

Unit

Comment

Tstrobe strobe period

4.166

550

4.167

1350

2

ns

ps

—

Todelay data output delay time

Measured at 50% point

Averaged from 30% – 70% points

Tslew

strobe/data rising/falling time

0.7

V/ns

4.12.19.2 Receive Timing

Tstrobe

USB_H_STROBE

USB_H_DATA

Thold

Tsetup

Figure 78. USB HSIC Receive Waveform

1

Table 89. USB HSIC Receive Parameters

Name

Parameter

Min

Max

Unit

Comment

Tstrobe strobe period

Thold data hold time

4.166

300

4.167

—

ns

ps

—

Measured at 50% point

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Comment

1

Table 89. USB HSIC Receive Parameters (continued)

Name

Parameter

Min

Max

Unit

Tsetup

Tslew

data setup time

strobe/data rising/falling time

365

0.7

—

2

ps

Measured at 50% point

Averaged from 30% – 70% points

V/ns

1

The timings in the table are guaranteed when:

—AC I/O voltage is between 0.9x to 1x of the I/O supply

—DDR_SEL configuration bits of the I/O are set to (10)b

4.12.20 USB PHY Parameters

This section describes the USB-OTG PHY and the USB Host port PHY parameters.

The USB PHY meets the electrical compliance requirements defined in revision 2.0 of the USB

On-The-Go and Embedded Host Supplement to the USB 2.0 Specification with the amendments below

(On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification is not applicable to

Host port).

•

USB ENGINEERING CHANGE NOTICE

— Title: 5V Short Circuit Withstand Requirement Change

— Applies to: Universal Serial Bus Specification, Revision 2.0

Errata for USB Revision 2.0 April 27, 2000 as of 12/7/2000

USB ENGINEERING CHANGE NOTICE

•

— Title: Pull-up/Pull-down resistors

— Applies to: Universal Serial Bus Specification, Revision 2.0

USB ENGINEERING CHANGE NOTICE

•

— Title: Suspend Current Limit Changes

— Applies to: Universal Serial Bus Specification, Revision 2.0

USB ENGINEERING CHANGE NOTICE

— Title: USB 2.0 Phase Locked SOFs

— Applies to: Universal Serial Bus Specification, Revision 2.0

On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification

— Revision 2.0 plus errata and ECN June 4, 2010

Battery Charging Specification (available from USB-IF)

— Revision 1.2, December 7, 2010

•

— Portable device only

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4.13 A/D Converter

4.13.1 12-bit ADC Electrical Characteristics

4.13.1.1 12-bit ADC Operating Conditions

Table 90. 12-bit ADC Operating Conditions

Characteristic

Conditions

Absolute

Symbol

Min

Typ¹

Max

Unit

Comment

Supply voltage

VDDA_ADC_ 3.0

3P3

-

3.6

V

—

Delta to VDD

VDDA_ADC_ -100

3P3

0

100

mV

—

(VDD-VDDA_ADC_3P3

2

)

Ground voltage

Delta to VSS

(VSS-VSSAD)

ΔVSSAD

-100

Ref Voltage High

Ref Voltage Low

Input Voltage

—

V_REFH

V_REFL

V_ADIN

C_ADIN

R_ADIN

1.13 VDDA_ADC_3P3 VDDA_ADC_3P3

V

—

V_SSAD

V_REFL

—

V_SSAD

—

V_SSAD

V_REFH

V

Input Capacitance 8/10/12 bit modes

Input Resistance ADLPC=0, ADHSC=1

ADLPC=0, ADHSC=0

1.5

5

2

7

pF

—

kohms

—

12.5

25

15

30

1

ADLPC=1, ADHSC=0

—

Analog Source

Resistance

12 bit mode f_ADCK

40MHz ADLSMP=0,

=

R_AS

—

kohms T_samp=150ns

ADSTS=10, ADHSC=1

R_ASdepends on Sample Time Setting (ADLSMP, ADSTS) and ADC Power Mode (ADHSC, ADLPC). See charts for Minimum

Sample Time versus R_AS

ADC Conversion ADLPC=0, ADHSC=1

Clock Frequency 12 bit mode

f_ADCK

4

—

40

30

20

MHz

—

ADLPC=0, ADHSC=0

12 bit mode

ADLPC=1, ADHSC=0

12 bit mode

1

Typical values assume VDDA_ADC_3P3= 3.0 V, Temp = 25°C, f_ADCK=20 MHz unless otherwise stated. Typical values are for

reference only and are not tested in production.

2

DC potential difference

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Electrical Characteristics

Figure 79. 12-bit ADC Input Impedance Equivalency Diagram

4.13.1.2 12-bit ADC Characteristics

Table 91. 12-bit ADC Characteristics (V

= VDDA_ADC_3P3, V

= V

)

SSAD

REFH

REFL

Characteristic

Conditions¹

Symbol Min

Typ²

250

Max

Unit

Comment

[L:] Supply Current

ADLPC=1, ADHSC=0 I_DDAD

ADLPC=0, ADHSC=0

—

µA

ADLSMP=0

ADSTS=10

ADCO=1

350

400

0.01

ADLPC=0, ADHSC=1

[L:] Supply Current

Stop, Reset,

Module Off

I_DDAD

—

0.8

µA

—

ADC Asynchronous

Clock Source

ADHSC=0

ADHSC=1

f_ADACK

—

10

20

2

—

MHz

t_ADACK= 1/f_ADACK

Sample Cycles

ADLSMP=0, ADSTS=00 Csamp

ADLSMP=0, ADSTS=01

ADLSMP=0, ADSTS=10

ADLSMP=0, ADSTS=11

ADLSMP=1, ADSTS=00

ADLSMP=1, ADSTS=01

ADLSMP=1, ADSTS=10

ADLSMP=1, ADSTS=11

cycles

—

4

6

8

12

16

20

24

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Electrical Characteristics

Table 91. 12-bit ADC Characteristics (V

= VDDA_ADC_3P3, V

= V

) (continued)

SSAD

REFH

REFL

Characteristic

Conditions¹

Symbol Min

Typ²

Max

Unit

Comment

Conversion Cycles ADLSMP=0 ADSTS=00 Cconv

ADLSMP=0 ADSTS=01

—

28

30

—

cycles

—

ADLSMP=0 ADSTS=10

32

ADLSMP=0 ADSTS=11

34

ADLSMP=1 ADSTS=00

38

ADLSMP=1 ADSTS=01

42

ADLSMP=1 ADSTS=10

46

ADLSMP=1, ADSTS=11

50

Conversion Time

ADLSMP=0 ADSTS=00 Tconv

ADLSMP=0 ADSTS=01

ADLSMP=0 ADSTS=10

ADLSMP=0 ADSTS=11

ADLSMP=1 ADSTS=00

ADLSMP=1 ADSTS=01

ADLSMP=1 ADSTS=10

ADLSMP=1, ADSTS=11

—

0.7

0.75

0.8

0.85

0.95

1.05

1.15

1.25

—

µs

Fadc=40 MHz

[P:][C:] Total

Unadjusted Error

12 bit mode

10 bit mode

8 bit mode

TUE

DNL

INL

-2

-0.5

-0.25

—

+5

+2

+1.5

2.5

1

LSB

1 LSB =

(V_REFH- V_REFL)/2N

With Max Averaging

—

[P:][C:] Differential 12 bit mode

Non-Linearity

0.6

0.5

0.25

2

LSB

Waiting for histogram

method confirmation

10bit mode

—

8 bit mode

—

0.5

5

[P:][C:] Integral

Non-Linearity

12 bit mode

10bit mode

8 bit mode

12 bit mode

10bit mode

8 bit mode

12 bit mode

10bit mode

8 bit mode

—

Waiting for histogram

method confirmation

—

1

2

—

0.5

1

Zero-Scale Error

Full-Scale Error

E_ZS

—

2

VADIN = V_REFLWith

Max Averaging

—

0.5

0.2

2

1

—

0.5

+1/-6

1/-2

0.75

E_FS

—

VADIN = V_REFHWith

Max Averaging

—

0.5

0.25

—

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Electrical Characteristics

= V ) (continued)

SSAD

Table 91. 12-bit ADC Characteristics (V

= VDDA_ADC_3P3, V

REFH

REFL

Characteristic

Conditions¹

12 bit mode

Symbol Min

ENOB 10.1

Typ²

Max

Unit

Comment

[L:] Effective

10.7

—

Bits

Fin = 100Hz

Number of Bits

[L:] Signal to Noise See ENOB

plus Distortion

SINAD SINAD = 6.02 x ENOB + 1.76

dB

—

1

All accuracy numbers assume the ADC is calibrated with V_REFH=VDDA_ADC_3P3

2

Typical values assume VDDA_{_}ADC_3P3 = 3.0 V, Temp = 25°C, F_adck=20 MHz unless otherwise stated. Typical values are for

reference only and are not tested in production.

NOTE

The ADC electrical spec is met with the calibration enabled configuration.

Figure 80. Minimum Sample Time versus Ras (Cas = 2pF)

Figure 81. Minimum Sample Time versus Ras (Cas = 5pF)

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Boot Mode Configuration

Figure 82. Minimum Sample Time versus Ras (Cas = 10pF)

5 Boot Mode Configuration

This section provides information on boot mode configuration pins allocation and boot devices interfaces

allocation.

5.1

Boot Mode Configuration Pins

Table 92 provides boot options, functionality, fuse values, and associated pins. Several input pins are also

sampled at reset and can be used to override fuse values, depending on the value of BT_FUSE_SEL fuse.

The boot option pins are in effect when BT_FUSE_SEL fuse is ‘0’ (cleared, which is the case for an

unblown fuse). For detailed boot mode options configured by the boot mode pins, see the i.MX 6SoloX

Fuse Map chapter and the System Boot chapter in i.MX 6SoloX Applications Processor Reference

Manual (IMX6SXRM).

Table 92. Fuses and Associated Pins Used for Boot

State during

reset (POR_B

asserted)

State after reset

(POR_B

deasserted)

Direction at

reset

eFuse name

Details

BOOT_MODE0

BOOT_MODE1

Input

N/A

Hi-Z

Boot mode selection

Bootmode selection

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Table 92. Fuses and Associated Pins Used for Boot (continued)

State during

reset (POR_B

asserted)

State after reset

(POR_B

deasserted)

Direction at

reset

eFuse name

Details

LCD1_DATA00

LCD1_DATA01

LCD1_DATA02

LCD1_DATA03

LCD1_DATA04

LCD1_DATA05

LCD1_DATA06

LCD1_DATA07

LCD1_DATA08

LCD1_DATA09

LCD1_DATA10

LCD1_DATA11

LCD1_DATA12

LCD1_DATA13

LCD1_DATA14

LCD1_DATA15

LCD1_DATA16

LCD1_DATA17

LCD1_DATA18

LCD1_DATA19

LCD1_DATA20

LCD1_DATA21

LCD1_DATA22

LCD1_DATA23

Input

BT_CFG1[0]

BT_CFG1[1]

BT_CFG1[2]

BT_CFG1[3]

BT_CFG1[4]

BT_CFG1[5]

BT_CFG1[6]

BT_CFG1[7]

BT_CFG2[0]

BT_CFG2[1]

BT_CFG2[2]

BT_CFG2[3]

BT_CFG2[4]

BT_CFG2[5]

BT_CFG2[6]

BT_CFG2[7]

BT_CFG4[0]

BT_CFG4[1]

BT_CFG4[2]

BT_CFG4[3]

BT_CFG4[4]

BT_CFG4[5]

BT_CFG4[6]

BT_CFG4[7]

100K Pull Down

Keeper

Boot Options, Pin value

overrides fuse settings for

BT_FUSE_SEL=’0’. Signal

Configuration as Fuse

Override Input at Power Up.

These are special I/O lines that

control the boot up

configuration during product

development. In production,

the boot configuration can be

controlled by fuses.

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Boot Mode Configuration

5.2

Boot Device Interface Allocation

The tables below list the interfaces that can be used by the boot process in accordance with the specific

boot mode configuration. The tables also describe the interface’s specific modes and IOMUXC

allocation, which are configured during boot when appropriate.

Table 93. QSPI Boot through QSPI1

Mux

Mode

Quad + Port A + Port A + Port + Port B + Port B

Ball Name

Signal Name

Common

Mode

DQS

CS1

B

DQS

CS1

QSPI1A_SCLK

QSPI1A_SS0_B

QSPI1A_DATA0

QSPI1A_DATA1

QSPI1A_DATA2

QSPI1A_DATA3

QSPI1B_DATA3

QSPI1B_DATA2

QSPI1B_DATA1

QSPI1B_DATA0

QSPI1B_SS0_B

QSPI1B_SCLK

QSPI1A_SS1_B

QSPI1A_DQS

qspi1.A_SCLK

qspi1.A_SS0_B

qspi1.A_DATA[0]

qspi1.A_DATA[1]

qspi1.A_DATA[2]

qspi1.A_DATA[3]

qspi1.B_DATA[3]

qspi1.B_DATA[2]

qspi1.B_DATA[1]

qspi1.B_DATA[0]

qspi1.B_SS0_B

qspi1.B_SCLK

Alt0

Yes

—

Yes

—

Yes

—

Yes

—

Yes

—

Yes

—

Yes

—

qspi1.A_SS1_B

qspi1.A_DQS

—

QSPI1B_SS1_B

QSPI1B_DQS

qspi1.B_SS1_B

qspi1.B_DQS

—

Table 94. QPSI Boot through QPSI2

Mux

Mode

Quad

Mode

+ Port A + Port A + Port + Port B + Port B

Ball Name

Signal Name

Common

DQS

CS1

B

DQS

CS1

NAND_CLE

NAND_ALE

NAND_WP_B

qspi2.A_SCLK

qspi2.A_SS0_B

qspi2.A_DATA[0]

Alt2

Yes

—

Yes

—

NAND_READY_B qspi2.A_DATA[1]

—

NAND_CE0_B

NAND_CE1_B

NAND_RE_B

NAND_WE_B

qspi2.A_DATA[2]

qspi2.A_DATA[3]

qspi2.B_DATA[3]

qspi2.B_DATA[2]

—

Yes

—

NAND_DATA00 qspi2.B_DATA[1]

—

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Table 94. QPSI Boot through QPSI2 (continued)

Mux

Mode

Quad

Mode

+ Port A + Port A + Port + Port B + Port B

Ball Name

Signal Name

Common

DQS

CS1

B

DQS

CS1

NAND_DATA01 qspi2.B_DATA[0]

Alt2

—

Yes

—

NAND_DATA03

NAND_DATA02

NAND_DATA06

NAND_DATA07

NAND_DATA04

NAND_DATA05

qspi2.B_SS0_B

qspi2.B_SCLK

qspi2.A_SS1_B

qspi2.A_DQS

qspi2.B_SS1_B

qspi2.B_DQS

—

Yes

—

Yes

—

Yes

—

Yes

Table 95. SPI Boot through ECSPI1

Mux

Mode

BOOT_CFG BOOT_CFG BOOT_CFG BOOT_CFG

Ball Name

Signal Name

Common

4[5:4]=00b

4[5:4]=01b

4[5:4]=10b

4[5:4]=11b

KEY_COL1

KEY_ROW0

ecspi1.MISO

ecspi1.MOSI

Alt 3

Alt 7

Yes

—

KEY_COL0 (SCLK)

KEY_ROW1

ecspi1.SCLK

ecspi1.SS0

ecspi1.SS1

ecspi1.SS2

ecspi1.SS3

—

Yes

—

KEY_ROW3

KEY_COL3

—

Yes

—

Yes

—

KEY_ROW2

—

Yes

Table 96. SPI Boot through ECSPI2

BOOT_CFG BOOT_CFG BOOT_CFG BOOT_CFG

Ball Name

Signal Name Mux Mode Common

4[5:4]=00b 4[5:4]=01b

4[5:4]=10b 4[5:4]=11b

SD4_CLK

SD4_CMD

ecspi2.MISO

ecspi2.MOSI

Alt 2

Alt 6

Yes

—

SD4_DATA1 ecspi2.SCLK

—

SD4_DATA0

SD3_DATA0

SD3_DATA1

SD4_DATA2

ecspi2.SS0

ecspi2.SS1

ecspi2.SS2

ecspi2.SS3

Yes

—

Yes

—

Yes

—

Yes

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Boot Mode Configuration

Table 97. SPI Boot through ECSPI3

BOOT_CFG BOOT_CFG BOOT_CFG BOOT_CFG

Ball Name

Signal Name Mux Mode Common

4[5:4]=00b

4[5:4]=01b 4[5:4]=10b 4[5:4]=11b

SD4_DATA6

SD4_DATA5

SD4_DATA4

SD4_DATA7

SD4_CMD

ecspi3.MISO

ecspi3.MOSI

ecspi3.SCLK

ecspi3.SS0

ecspi3.SS1

ecspi3.SS2

ecspi3.SS3

Alt 3

Alt 6

Yes

—

Yes

—

Yes

—

SD4_CLK

—

Yes

—

SD4_DATA0

—

Yes

Table 98. SPI Boot through ECSPI4

BOOT_CFG4 BOOT_CFG4 BOOT_CFG4 BOOT_CFG4

Ball Name

Signal Name

Mux Mode Common

[5:4]=00b

[5:4]=01b

[5:4]=10b

[5:4]=11b

SD2_DATA3

SD2_CMD

ecspi4.MISO

ecspi4.MOSI

ecspi4.SCLK

ecspi4.SS0

ecspi4.SS1

ecspi4.SS2

ecspi4.SS3

Alt 3

Alt 6

Yes

—

SD2_CLK

—

SD2_DATA2

SD1_DATA3

SD2_DATA1

SD2_DATA0

Yes

—

Yes

—

Yes

—

Yes

Table 99. SPI Boot through ECSPI5

BOOT_CFG4 BOOT_CFG4 BOOT_CFG4[ BOOT_CFG4

Ball Name

Signal Name Mux Mode Common

[5:4]=00b

[5:4]=01b

5:4]=10b

[5:4]=11b

QSPI1A_SS1_B

QSPI1A_DQS

ecspi5.MISO

ecspi5.MOSI

ecspi5.SCLK

ecspi5.SS0

ecspi5.SS1

ecspi5.SS2

ecspi5.SS3

Alt 3

Alt 2

Yes

—

QSPI1B_SS1_B

QSPI1B_DQS

—

Yes

—

QSPI1A_DATA2

QSPI1A_DATA3

QSPI1B_DATA3

—

Yes

—

Yes

—

Yes

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BOOT_CFG1[3:2]=10b

Table 100. NAND Boot through GPMI

Ball Name

Signal Name

Mux Mode Common BOOT_CFG1[3:2]=01b

NAND_CLE

NAND_ALE

NAND_WP_B

rawnand.CLE

rawnand.ALE

rawnand.WP_B

Alt 0

Alt 1

Yes

—

Yes

—

Yes

NAND_READY_B rawnand.READY_B

NAND_CE0_B

NAND_CE1_B

NAND_RE_B

rawnand.CE0_B

rawnand.CE1_B

rawnand.RE_B

Yes

—

NAND_WE_B

NAND_DATA00

NAND_DATA01

NAND_DATA02

NAND_DATA03

NAND_DATA04

NAND_DATA05

NAND_DATA06

NAND_DATA07

SD4_RESET_B

SD4_DATA5

rawnand.WE_B

rawnand.DATA00

rawnand.DATA01

rawnand.DATA02

rawnand.DATA03

rawnand.DATA04

rawnand.DATA05

rawnand.DATA06

rawnand.DATA07

rawnand.DQS

rawnand.CE2_B

rawnand.CE3_B

SD4_DATA6

—

Table 101. SD/MMC Boot through USDHC1

BOOT_CFG1[1]=1

SDMMC

Mux

Mode

(SD Power Cycle

MFG

Ball Name

Signal Name

Common

4-bit

8-bit

or SD boot with

Mode

SDR50/SDR104)

GPIO1_IO02

SD1_CLK

usdhc1.CD_B

usdhc1.CLK

Alt 1

Alt 0

Alt 1

—

Yes

—

Yes

—

SD1_CMD

usdhc1.CMD

—

SD1_DATA0

SD1_DATA1

SD1_DATA2

SD1_DATA3

NAND_DATA00

NAND_DATA01

usdhc1.DATA0

usdhc1.DATA1

usdhc1.DATA2

usdhc1.DATA3

usdhc1.DATA4

usdhc1.DATA5

—

Yes

—

Yes

—

Yes

—

Yes

—

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Table 101. SD/MMC Boot through USDHC1 (continued)

Mux

BOOT_CFG1[1]=1

(SD Power Cycle

or SD boot with

SDR50/SDR104)

SDMMC

MFG

Mode

Ball Name

Signal Name

Common

4-bit

8-bit

Mode

NAND_DATA02

NAND_DATA03

NAND_WP_B

usdhc1.DATA6

usdhc1.DATA7

GPIO4_15

Alt 1

Alt 5

Alt 1

—

Yes

—

Yes

NAND_READY_B usdhc1.VSELECT

—

Table 102. SD/MMC Boot through USDHC2

BOOT_CFG1[1]=1

(SD Power Cycle

or SD boot with

SDR50/SDR104)

Ball Name

Signal Name

Mux Mode Common

4-bit

8-bit

SD2_CLK

SD2_CMD

usdhc2.CLK

usdhc2.CMD

Alt 0

Alt 1

Alt 5

Alt 1

Yes

—

SD2_DATA0

SD2_DATA1

SD2_DATA2

SD2_DATA3

NAND_DATA04

NAND_DATA05

NAND_DATA06

NAND_DATA07

NAND_RE_B

NAND_CE0_B

usdhc2.DATA0

usdhc2.DATA1

usdhc2.DATA2

usdhc2.DATA3

usdhc2.DATA4

usdhc2.DATA5

usdhc2.DATA6

usdhc2.DATA7

GPIO4_IO12

—

Yes

—

Yes

—

Yes

—

Yes

—

Yes

usdhc2.VSELECT

—

Table 103. SD/MMC Boot through USDHC3

BOOT_CFG1[1]=1

(SD Power Cycle

or SD boot with

SDR50/SDR104)

Ball Name

Signal Name

Mux Mode Common

4-bit

8-bit

SD3_CLK

SD3_CMD

usdhc3.CLK

usdhc3.CMD

Alt 0

Yes

—

SD3_DATA0

SD3_DATA1

SD3_DATA2

usdhc3.DATA0

usdhc3.DATA1

usdhc3.DATA2

—

Yes

—

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Table 103. SD/MMC Boot through USDHC3 (continued)

BOOT_CFG1[1]=1

(SD Power Cycle

or SD boot with

SDR50/SDR104)

Ball Name

Signal Name

Mux Mode Common

4-bit

8-bit

SD3_DATA3

SD3_DATA4

SD3_DATA5

SD3_DATA6

SD3_DATA7

KEY_COL1

usdhc3.DATA3

usdhc3.DATA4

usdhc3.DATA5

usdhc3.DATA6

usdhc3.DATA7

GPIO2_IO11

Alt 0

Alt 5

Yes

—

Yes

—

Yes

Table 104. SD/MMC Boot through USDHC4

BOOT_CFG1[1]=1

(SDPowerCycleor

SD boot with

Ball Name

Signal Name

Mux Mode Common

4-bit

8-bit

SDR50/SDR104)

SD4_CLK

SD4_CMD

usdhc4.CLK

usdhc4.CMD

Alt 0

Alt 5

Alt 1

Yes

—

SD4_DATA0

SD4_DATA1

SD4_DATA2

SD4_DATA3

SD4_DATA4

SD4_DATA5

SD4_DATA6

SD4_DATA7

SD4_RESET_B

KEY_ROW1

usdhc4.DATA0

usdhc4.DATA1

usdhc4.DATA2

usdhc4.DATA3

usdhc4.DATA4

usdhc4.DATA5

usdhc4.DATA6

usdhc4.DATA7

GPIO6_IO22

—

Yes

—

Yes

—

Yes

—

Yes

—

Yes

usdhc4.VSELECT

—

Table 105. NOR/OneNAND Boot through EIM

ADH16

Non-Mux

ADL16

Non-Mux

Ball Name

Signal Name

Mux Mode Common

AD16 Mux

NAND_DATA00

NAND_DATA01

NAND_DATA02

NAND_DATA03

NAND_DATA04

weim.AD[0]

weim.AD[1]

weim.AD[2]

weim.AD[3]

weim.AD[4]

Alt 6

Yes

—

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Ball Name

Table 105. NOR/OneNAND Boot through EIM (continued)

ADH16

ADL16

Non-Mux

Signal Name

Mux Mode Common

AD16 Mux

Non-Mux

NAND_DATA05

NAND_DATA06

NAND_DATA07

LCD1_DATA08

LCD1_DATA09

LCD1_DATA10

LCD1_DATA11

LCD1_DATA12

LCD1_DATA13

LCD1_DATA14

LCD1_DATA15

LCD1_DATA16

LCD1_DATA17

LCD1_DATA18

LCD1_DATA19

LCD1_DATA20

LCD1_DATA21

LCD1_DATA22

LCD1_DATA23

LCD1_DATA03

LCD1_DATA04

LCD1_DATA05

NAND_ALE

weim.AD[5]

weim.AD[6]

Alt 6

Alt 1

Alt 6

Yes

—

weim.AD[7]

—

weim.AD[8]

—

weim.AD[9]

—

weim.AD[10]

—

weim.AD[11]

—

weim.AD[12]

—

weim.AD[13]

—

weim.AD[14]

—

weim.AD[15]

—

weim.ADDR[16]

weim.ADDR[17]

weim.ADDR[18]

weim.ADDR[19]

weim.ADDR[20]

weim.ADDR[21]

weim.ADDR[22]

weim.ADDR[23]

weim.ADDR[24]

weim.ADDR[25]

weim.ADDR[26]

weim.CS0_B

weim.DATA[0]

weim.DATA[1]

weim.DATA[2]

weim.DATA[3]

weim.DATA[4]

weim.DATA[5]

weim.DATA[6]

weim.DATA[7]

weim.DATA[8]

Yes

—

Yes

—

Yes

—

Yes

—

QSPI1A_SCLK

QSPI1A_SS0_B

QSPI1A_SS1_B

QSPI1A_DATA3

QSPI1A_DATA2

QSPI1A_DATA1

QSPI1A_DATA0

QSPI1A_DQS

QSPI1B_SCLK

—

Yes

—

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Table 105. NOR/OneNAND Boot through EIM (continued)

ADH16

ADL16

Ball Name

Signal Name

Mux Mode Common

AD16 Mux

Non-Mux

QSPI1B_SS0_B

QSPI1B_SS1_B

QSPI1B_DATA3

QSPI1B_DATA2

QSPI1B_DATA1

QSPI1B_DATA0

QSPI1B_DQS

CSI_DATA07

CSI_DATA06

CSI_DATA05

CSI_DATA04

CSI_DATA03

CSI_DATA02

CSI_DATA01

CSI_DATA00

CSI_VSYNC

weim.DATA[9]

weim.DATA[10]

weim.DATA[11]

weim.DATA[12]

weim.DATA[13]

weim.DATA[14]

weim.DATA[15]

weim.DATA[16]

weim.DATA[17]

weim.DATA[18]

weim.DATA[19]

weim.DATA[20]

weim.DATA[21]

weim.DATA[22]

weim.DATA[23]

weim.DATA[24]

weim.DATA[25]

weim.DATA[26]

weim.DATA[27]

weim.DATA[28]

weim.DATA[29]

weim.DATA[30]

weim.DATA[31]

weim.EB_B[0]

weim.EB_B[1]

weim.EB_B[2]

weim.EB_B[3]

weim.LBA_B

Alt 6

Alt 1

Alt 6

—

Yes

—

Yes

—

Yes

—

Yes

—

CSI_HSYNC

—

CSI_MCLK

—

CSI_PIXCLK

KEY_COL3

—

KEY_ROW2

—

KEY_COL2

—

KEY_ROW1

—

NAND_WP_B

NAND_READY_B

LCD1_DATA06

LCD1_DATA07

NAND_CE0_B

NAND_CE1_B

NAND_RE_B

Yes

—

Yes

—

weim.OE

—

weim.RW

—

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Package Information and Contact Assignments

6 Package Information and Contact Assignments

This section includes the contact assignment information and mechanical package drawing.

6.1

i.MX 6SoloX Signal Availability by Package

The i.MX 6SoloX is available in multiple packages. Not all signals are available in all packages. Table 106

summarizes the signal differences and their implications. Signals available on all packages are not shown in this

table. This table only shows signals impacted that are not available through another IOMUX option.

Table 106. i.MX 6SoloX Signal Availability by Package

Package

Affected

Module

SoC Capability

Implication

19x19 mm

[VM]

17x17 mm NP 17x17 mm WP

(no PCIe) [VO] (with PCIe) [VN]

14x14 mm

[VK]

ADC

ADC1_IN0

ADC1_IN1

ADC1_IN2

ADC1_IN3

ADC2_IN0

ADC2_IN1

ADC2_IN2

ADC2_IN3

ADC_VREFL

ADC1_IN0

ADC1_IN1

ADC1_IN2

ADC1_IN3

ADC2_IN0

ADC2_IN1

ADC2_IN2

ADC2_IN3

ADC_VREFL

ADC1_IN0

ADC1_IN1

ADC1_IN2

ADC1_IN3

ADC2_IN0

ADC2_IN1

ADC2_IN2

ADC2_IN3

—

ADC1_IN1

—

Tied internally

to VSS

ADC_VREFL 17x17NP low reference voltage is not

controllable.

ADC_VREFH

ECSPI4_RDY

ADC_VREFH Tied internally to ADC_VREFH 17x17NP high reference voltage is not

VDDA_ADC_3P3

controllable.

ECSPI4

EIM

—

Master mode flow control cannot be

used without ECSPI4_RDY

EIM_DATA[27:16]

—

Reduced EIM throughput on the

smaller packages

ENET1

1588_EVENT1_IN

1588_EVENT1_OUT

1588_EVENT1_IN

1588_EVENT1_OUT

—

ENET2

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Table 106. i.MX 6SoloX Signal Availability by Package (continued)

Package

Affected

Module

SoC Capability

Implication

19x19 mm

[VM]

17x17 mm NP 17x17 mm WP

(no PCIe) [VO] (with PCIe) [VN]

14x14 mm

[VK]

GPIO

GPIO1_IO[21]

GPIO1_IO[20]

GPIO1_IO[19]

GPIO1_IO[18]

GPIO1_IO[17]

GPIO1_IO[16]

GPIO1_IO[15]

GPIO1_IO[14]

GPIO1_IO[25]

GPIO1_IO[22]

GPIO1_IO[23]

GPIO1_IO[24]

GPIO6_IO[2]

—

GPIO6_IO[3]

GPIO6_IO[1]

GPIO6_IO[0]

GPIO6_IO[4]

GPIO6_IO[5]

GPT

GPT_CAPTURE1

GPT_CAPTURE2

GPT_COMPARE1

GPT_CLK

GPT_COMPARE2

GPT_COMPARE3

GPT_CAPTURE1

LVDS_CLK_N

LVDS_CLK_P

LVDS_DATA0_N

LVDS_DATA0_P

LVDS_DATA1_N

LVDS_DATA1_P

LVDS_DATA2_N

LVDS_DATA2_P

LVDS_DATA3_N

LVDS_DATA3_P

LVDS_CLK_N

LVDS I/F

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Package Information and Contact Assignments

Table 106. i.MX 6SoloX Signal Availability by Package (continued)

Package

Affected

Module

SoC Capability

Implication

19x19 mm

[VM]

17x17 mm NP 17x17 mm WP

(no PCIe) [VO] (with PCIe) [VN]

14x14 mm

[VK]

MMDC

PCIe

DRAM_ADDR15

—

Address space is limited to 2GB on the

smaller packages vs.4 GB on the

19x19 package.

PCIE_REXT

PCIE_RX_N

PCIE_RX_P

PCIE_TX_N

PCIE_TX_P

PCIE_VP

—

PCIE_REXT

PCIE_RX_N

PCIE_RX_P

PCIE_TX_N

PCIE_TX_P

PCIE_VP

—

PCIE_VP_CAP

PCIE_VPH

—

PCIE_VPH

PCIE_VPTX

—

PCIE_VPTX

UART6_DCD_B

UART6_DTR_B

UART6_DSR_B

UART6_RI_B

SD1_DATA0

UART6

—

uSDHC1

—

Entire interface not available on the

smaller packages

SD1_DATA1

SD1_CMD

—

SD1_CLK

SD1_DATA2

SD1_DATA3

6.2

Signals with Different States During Reset and After Reset

For most of the signals, the state during reset is the same as the state after reset as listed in the “Out of Reset

Condition” column of the Functional Contact Assignment tables for the various packages (Table 109,

Table 113, Table 116, and Table 119). However, there are a few signals for which the state during reset is

different from the state after reset. These signals along with their state during reset are given in Table 107.

Table 107. Signals with Different States During Reset and After Reset

State During Reset (POR_B Asserted)

Ball Name

Input/Output

Value

GPIO1_IO06

GPIO1_IO09

Output

Drive state unknown. This signal should not be used for system functions that will

require it to be an input or stable output during reset.

Output

Drive state unknown. This signal should not be used for system functions that will

require it to be an input or stable output during reset.

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Package Information and Contact Assignments

Table 107. Signals with Different States During Reset and After Reset (continued)

State During Reset (POR_B Asserted)

Value

Ball Name

Input/Output

RGMII2_TD3

Output

Drive state unknown. This signal should not be used for system functions that will

require it to be an input or stable output during reset.

LCD1_DATA00

LCD1_DATA01

LCD1_DATA02

LCD1_DATA03

LCD1_DATA04

LCD1_DATA05

LCD1_DATA06

LCD1_DATA07

LCD1_DATA08

LCD1_DATA09

LCD1_DATA10

LCD1_DATA11

LCD1_DATA12

LCD1_DATA13

LCD1_DATA14

LCD1_DATA15

LCD1_DATA16

LCD1_DATA17

LCD1_DATA18

LCD1_DATA19

LCD1_DATA20

LCD1_DATA21

LCD1_DATA22

LCD1_DATA23

Input

BT_CFG[0] with 100K Pull Down

BT_CFG[1] with 100K Pull Down

BT_CFG[2] with 100K Pull Down

BT_CFG[3] with 100K Pull Down

BT_CFG[4] with 100K Pull Down

BT_CFG[5] with 100K Pull Down

BT_CFG[6] with 100K Pull Down

BT_CFG[7] with 100K Pull Down

BT_CFG[8] with 100K Pull Down

BT_CFG[9] with 100K Pull Down

BT_CFG[10] with 100K Pull Down

BT_CFG[11] with 100K Pull Down

BT_CFG[12] with 100K Pull Down

BT_CFG[13] with 100K Pull Down

BT_CFG[14] with 100K Pull Down

BT_CFG[15] with 100K Pull Down

BT_CFG[24] with 100K Pull Down

BT_CFG[25] with 100K Pull Down

BT_CFG[26] with 100K Pull Down

BT_CFG[27] with 100K Pull Down

BT_CFG[28] with 100K Pull Down

BT_CFG[29] with 100K Pull Down

BT_CFG[30] with 100K Pull Down

BT_CFG[31] with 100K Pull Down

6.3

19x19 mm Package Information

6.3.1

19x19 mm, 0.8 mm Pitch, 23x23 Ball Matrix

Figure 83 shows the top, bottom, and side views of the 19×19 mm BGA package.

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Package Information and Contact Assignments

Figure 83. 19x19 mm BGA Package—Top, Bottom, and Side Views

i.MX 6SoloX Applications Processors for Industrial Products, Rev. 4, 11/2018

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NXP Semiconductors

Package Information and Contact Assignments

Figure 84. 19x19 mm BGA Package Notes

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Package Information and Contact Assignments

6.3.2

19x19 mm Supplies Contact Assignments and Functional Contact

Assignments

Table 108 shows supplies contact assignments for the 19x19 mm package.

Table 108. 19x19 mm Supplies Contact Assignments

19x19

Ball(s) Position(s)

Supply Rail Name

Remark

ADC_VREFH

ADC_VREFL

DRAM_VREF

AA16

U16

M3

ADC high reference voltage

ADC low reference voltage

DDR voltage reference input. Connect to a voltage source

that is 50% of NVCC_DRAM.

DRAM_ZQPAD

GPANAIO

C4

DDR output buffer driver calibration reference voltage input.

Connect DRAM_ZQPAD to an external 240 ohm 1% resistor

to Vss.

V18

Analog output for NXP use only. This output must always be

left unconnected.

NGND_KEL0

NVCC_CSI

R16

P18

Connect to Vss

Supply input for the CSI interface

Supply input for the DDR I/O interface

NVCC_DRAM

F5, G5, H5, J5, K5, L5, M5, N5, P5,

R5, T5, U5, V5

NVCC_DRAM_2P5

NVCC_ENET

NVCC_GPIO

M6

F6

Supply input for the DDR interface

Supply input for the ENET interfaces

Supply input for the GPIO interface

G15

U12

NVCC_HIGH

3.3 V Supply input for the dual-voltage I/Os on the SD3

interface

NVCC_JTAG

NVCC_KEY

NVCC_LCD1

NVCC_LOW

U11

G16

G17

V11

Supply input for the JTAG interface

Supply input for the Key Pad Port (KPP) interface

Supply input for the LCD interface

1.8 V Supply input for the dual-voltage IOs on the SD3

interface

NVCC_LVDS

NVCC_NAND

NVCC_PLL

T18

U8

Supply input for the LVDS interface

Supply input for the Raw NAND flash memories interface

Supply input for the PLLs

Y23

G14

F8

NVCC_QSPI

NVCC_RGMII1

NVCC_RGMII2

NVCC_SD1

Supply input for the QSPI interface

Supply input for the RGMII1 interface

Supply input for the RGMII2 interface

Supply input for the SD1 interface

G9

G12

G11

U10

AA6

M21

NVCC_SD2

Supply input for the SD2 interface

NVCC_SD4

Supply input for the SD4 interface

NVCC_USB_H

PCIE_REXT

Supply input for the USB HSIC interface

PCIe impedance calibration resistor. Connect PCIE_REXT to

an external 200 ohm 1% resistor to Vss.

PCIE_VP

L18

R18

Supply input for the PCIe PHY

PCIE_VPH

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Package Information and Contact Assignments

Table 108. 19x19 mm Supplies Contact Assignments (continued)

19x19

Ball(s) Position(s)

Supply Rail Name

Remark

PCIE_VPTX

RSVD

M18

E5

Supply input for the PCIe PHY

Reserved. Do not connect.

USB_OTG1_VBUS

USB_OTG2_VBUS

Reserved

W20

Y18

K21

L21

N18

VBUS input for USB_OTG1

VBUS input for USB_OTG2

Reserved. Leave unconnected.

Reserved

Reserved. Connect to ground through a 10 kΩ resistor.

Reserved

VDD_ARM_CAP

C18, J12, J13, J14, J15, J16, K16,

L16, M16

Supply voltage output from internal LDO_ARM. Requires

external capacitor(s).

VDD_ARM_IN

K12, K13, K14, K15, J21, L15, M15

U17, U18

Supply voltage input for internal LDO_ARM.

VDD_HIGH_CAP

Supply voltage output from internal LDO_2P5. Requires

external capacitor(s).

VDD_HIGH_IN

U14, U15

Y22

Supply voltage input to internal LDO_2P5, LDO_1P1 and

LDO_SNVS.

VDD_SNVS_CAP

Supply voltage output from internal LDO_SNVS. Requires

external capacitor(s).

VDD_SNVS_IN

VDD_SOC_CAP

V15

Supply voltage input to the SNVS voltage domain

J7, J8, J9, J10, J11, K7, L7, M7, N7,

N16, P7, P16, R7, R8, R9, R10, R11,

R12, R13, R14, R15, Y10, AA10

Supply voltage output from internal LDO_SOC. Requires

external capacitor(s).

VDD_SOC_IN

C9, K8, K9, K10, K11, L8, M8, N8,

N15, P8, P9, P10, P11, P12, P13,

P14, P15

Supply voltage input to internal LDO_SOC and LDO_PCIE

VDD_USB_CAP

VDDA_ADC_3P3

VSS

AA17

Supply voltage output from internal LDO_USB. Requires

external capacitor(s).

U13

Supply voltage input to the ADC. This supply must be

provided even if the ADC is not used.

A1, A6, A23, B3, B6, C2, C3, C5, D7,

D9, D11, D13, D15, D17, D19, F2, F3,

F20, G6, G7, G8, H6, H7, H8, H9,

H10, H11, H12, H13, H14, H15, H16,

H17, J2, J3, J6, J17, J20, K6, K17, L2,

L3, L6, L9, L10, L11, L12, L13, L14,

L17, M9, M10, M11, M12, M13, M14,

M17, M20, M22, M23, N2, N3, N6, N9,

N10, N11, N12, N13, N14, N17, P6,

P17, R2, R3, R6, R17, R20, R21, R22,

R23, T6, T7, T8, T9, T10, T11, T12,

T13, T14, T15, T16, T17, U6, U7, U20,

U21, V2, V3, V8, V9, W19, W21, W22,

W23, Y7, Y11, Y13, Y15, Y17, Y20,

AA2, AA3, AA5, AA18, AA20, AB3,

AB6, AB19, AB21, AB23, AC1, AC6,

AC19, AC21, AC23

Ground

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Package Information and Contact Assignments

Table 109 shows an alpha-sorted list of functional contact assignments for the 19x19 mm package.

Table 109. 19x19 mm Functional Contact Assignments

Out of Reset Condition

19x19

Ball

Power

Group

Ball

Type

Ball Name

Default

Mode

Default

Input/

Value

Function

Output

ADC1_IN0

AC15 VDDA_ADC_3P3

AB15 VDDA_ADC_3P3

AC16 VDDA_ADC_3P3

AB16 VDDA_ADC_3P3

AC17 VDDA_ADC_3P3

AB17 VDDA_ADC_3P3

AC18 VDDA_ADC_3P3

AB18 VDDA_ADC_3P3

—

ADC1_IN0

ADC1_IN1

ADC1_IN2

ADC1_IN3

ADC2_IN0

ADC2_IN1

ADC2_IN2

ADC2_IN3

BOOT_MODE0

Input

—

ADC1_IN1

ADC1_IN2

ADC1_IN3

ADC2_IN0

ADC2_IN1

ADC2_IN2

ADC2_IN3

BOOT_MODE0

—

W14

VDD_SNVS_IN

GPIO

100 kΩ

pull-down

BOOT_MODE1

W15

VDD_SNVS_IN

GPIO

—

BOOT_MODE1

Input

100 kΩ

pull-down

CCM_CLK1_N

CCM_CLK1_P

CCM_CLK2

AA22 VDD_HIGH_CAP

AA23 VDD_HIGH_CAP

—

CCM_CLK1_N

CCM_CLK1_P

CCM_CLK2

—

W18

V16

P21

P20

P19

N21

N19

N20

M19

L19

L20

R19

T19

U19

N4

VDD_HIGH_CAP

VDD_SNVS_IN

NVCC_CSI

NVCC_DRAM

—

CCM_PMIC_STBY_REQ

CSI_DATA00

CSI_DATA01

CSI_DATA02

CSI_DATA03

CSI_DATA04

CSI_DATA05

CSI_DATA06

CSI_DATA07

CSI_HSYNC

GPIO

DDR

—

CCM_PMIC_STBY_REQ Output

0

ALT5

—

GPIO1_IO14

GPIO1_IO15

GPIO1_IO16

GPIO1_IO17

GPIO1_IO18

GPIO1_IO19

GPIO1_IO20

GPIO1_IO21

GPIO1_IO22

GPIO1_IO23

GPIO1_IO24

GPIO1_IO25

DRAM_ADDR00

Input

Output

Keeper

CSI_MCLK

CSI_PIXCLK

CSI_VSYNC

DRAM_ADDR00

100 kΩ

pull-up

DRAM_ADDR01

Y4

NVCC_DRAM

DDR

—

DRAM_ADDR01

Output

100 kΩ

pull-up

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Package Information and Contact Assignments

Table 109. 19x19 mm Functional Contact Assignments (continued)

Out of Reset Condition

19x19

Ball

Power

Group

Ball

Type

Ball Name

Default

Mode

Default

Function

Input/

Output

Value

DRAM_ADDR02

DRAM_ADDR03

DRAM_ADDR04

DRAM_ADDR05

DRAM_ADDR06

DRAM_ADDR07

DRAM_ADDR08

DRAM_ADDR09

DRAM_ADDR10

DRAM_ADDR11

DRAM_ADDR12

DRAM_ADDR13

DRAM_ADDR14

DRAM_ADDR15

DRAM_CAS_B

DRAM_CS0_B

DRAM_CS1_B

DRAM_DATA00

DRAM_DATA01

DRAM_DATA02

G4

H3

R4

G3

Y3

F4

T3

P3

U4

T4

W3

P4

W4

E4

K4

J4

NVCC_DRAM

DDR

—

DRAM_ADDR02

DRAM_ADDR03

DRAM_ADDR04

DRAM_ADDR05

DRAM_ADDR06

DRAM_ADDR07

DRAM_ADDR08

DRAM_ADDR09

DRAM_ADDR10

DRAM_ADDR11

DRAM_ADDR12

DRAM_ADDR13

DRAM_ADDR14

DRAM_ADDR15

DRAM_CAS_B

DRAM_CS0_B

DRAM_CS1_B

DRAM_DATA00

DRAM_DATA01

DRAM_DATA02

Output

100 kΩ

pull-up

Output

Input

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

D3

U2

W2

V1

100 kΩ

pull-up

100 kΩ

pull-up

Input

100 kΩ

pull-up

Input

100 kΩ

pull-up

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Package Information and Contact Assignments

Table 109. 19x19 mm Functional Contact Assignments (continued)

Out of Reset Condition

19x19

Ball

Power

Group

Ball

Type

Ball Name

Default

Mode

Default

Function

Input/

Output

Value

DRAM_DATA03

DRAM_DATA04

DRAM_DATA05

DRAM_DATA06

DRAM_DATA07

DRAM_DATA08

DRAM_DATA09

DRAM_DATA10

DRAM_DATA11

DRAM_DATA12

DRAM_DATA13

DRAM_DATA14

DRAM_DATA15

DRAM_DATA16

DRAM_DATA17

DRAM_DATA18

DRAM_DATA19

DRAM_DATA20

DRAM_DATA21

DRAM_DATA22

W1

P1

NVCC_DRAM

DDR

—

DRAM_DATA03

DRAM_DATA04

DRAM_DATA05

DRAM_DATA06

DRAM_DATA07

DRAM_DATA08

DRAM_DATA09

DRAM_DATA10

DRAM_DATA11

DRAM_DATA12

DRAM_DATA13

DRAM_DATA14

DRAM_DATA15

DRAM_DATA16

DRAM_DATA17

DRAM_DATA18

DRAM_DATA19

DRAM_DATA20

DRAM_DATA21

DRAM_DATA22

Input

100 kΩ

pull-up

100 kΩ

pull-up

N1

100 kΩ

pull-up

R1

100 kΩ

pull-up

P2

100 kΩ

pull-up

J1

100 kΩ

pull-up

L1

100 kΩ

pull-up

K2

100 kΩ

pull-up

G2

K1

100 kΩ

pull-up

100 kΩ

pull-up

F1

100 kΩ

pull-up

E2

100 kΩ

pull-up

E1

100 kΩ

pull-up

AB1

AB5

AC5

AB4

Y2

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

AC3

AA1

100 kΩ

pull-up

100 kΩ

pull-up

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Package Information and Contact Assignments

Table 109. 19x19 mm Functional Contact Assignments (continued)

Out of Reset Condition

19x19

Ball

Power

Group

Ball

Type

Ball Name

Default

Mode

Default

Function

Input/

Output

Value

DRAM_DATA23

DRAM_DATA24

DRAM_DATA25

DRAM_DATA26

DRAM_DATA27

DRAM_DATA28

DRAM_DATA29

DRAM_DATA30

DRAM_DATA31

DRAM_DQM0

DRAM_DQM1

DRAM_DQM2

DRAM_DQM3

DRAM_ODT0

Y1

B4

D1

B2

D2

B1

A4

B5

A5

T2

NVCC_DRAM

DDR

—

DRAM_DATA23

DRAM_DATA24

DRAM_DATA25

DRAM_DATA26

DRAM_DATA27

DRAM_DATA28

DRAM_DATA29

DRAM_DATA30

DRAM_DATA31

DRAM_DQM0

DRAM_DQM1

DRAM_DQM2

DRAM_DQM3

DRAM_ODT0

Input

100 kΩ

pull-up

Input

100 kΩ

pull-up

100 kΩ

pull-up

Input

100 kΩ

pull-up

Input

100 kΩ

pull-up

Input

100 kΩ

pull-up

Input

100 kΩ

pull-up

Input

100 kΩ

pull-up

Input

100 kΩ

pull-up

Output

100 kΩ

pull-up

G1

AC4

C1

AA4

L4

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-down

DRAM_RAS_B

DRAM_RESET

DRAM_SDBA0

DRAM_SDBA1

DRAM_SDBA2

DRAM_SDCKE0

DRAM_RAS_B

DRAM_RESET

DRAM_SDBA0

DRAM_SDBA1

DRAM_SDBA2

DRAM_SDCKE0

100 kΩ

pull-up

D4

H4

U3

M4

V4

100 kΩ

pull-down

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-down

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Package Information and Contact Assignments

Table 109. 19x19 mm Functional Contact Assignments (continued)

Out of Reset Condition

19x19

Ball

Power

Group

Ball

Type

Ball Name

Default

Mode

Default

Function

Input/

Output

Value

DRAM_SDCKE1

E3

NVCC_DRAM

DDR

—

DRAM_SDCKE1

Output

100 kΩ

pull-down

DRAM_SDCLK0_N

DRAM_SDCLK0_P

DRAM_SDQS0_N

DRAM_SDQS0_P

DRAM_SDQS1_N

DRAM_SDQS1_P

DRAM_SDQS2_N

DRAM_SDQS2_P

DRAM_SDQS3_N

DRAM_SDQS3_P

DRAM_SDWE_B

M1

M2

U1

NVCC_DRAM

DDRCLK

DDR

—

DRAM_SDCLK0_N

DRAM_SDCLK0_P

DRAM_SDQS0_N

DRAM_SDQS0_P

DRAM_SDQS1_N

DRAM_SDQS1_P

DRAM_SDQS2_N

DRAM_SDQS2_P

DRAM_SDQS3_N

DRAM_SDQS3_P

DRAM_SDWE_B

—

Output

—

Low

—

T1

Input

—

H2

—

H1

Input

—

AC2

AB2

A2

—

Input

—

A3

Input

Output

—

K3

100 kΩ

pull-up

ENET1_COL

ENET1_CRS

ENET1_MDC

ENET1_MDIO

ENET1_RX_CLK

ENET1_TX_CLK

ENET2_COL

ENET2_CRS

ENET2_RX_CLK

ENET2_TX_CLK

GPIO1_IO00

GPIO1_IO01

GPIO1_IO02

GPIO1_IO03

GPIO1_IO04

GPIO1_IO05

GPIO1_IO06

GPIO1_IO07

GPIO1_IO08

GPIO1_IO09

E6

C7

NVCC_ENET

NVCC_GPIO

GPIO

ALT5

GPIO2_IO00

GPIO2_IO01

GPIO2_IO02

GPIO2_IO03

GPIO2_IO04

GPIO2_IO05

GPIO2_IO06

GPIO2_IO07

GPIO2_IO08

GPIO2_IO09

GPIO1_IO00

GPIO1_IO01

GPIO1_IO02

GPIO1_IO03

GPIO1_IO04

GPIO1_IO05

GPIO1_IO06

GPIO1_IO07

GPIO1_IO08

GPIO1_IO09

Input

Keeper

F9

E7

B7

A7

F7

D6

D5

C6

A20

B20

C20

D20

A19

B19

C19

A18

B18

D18

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Table 109. 19x19 mm Functional Contact Assignments (continued)

Out of Reset Condition

19x19

Ball

Power

Group

Ball

Type

Ball Name

Default

Mode

Default

Function

Input/

Output

Value

GPIO1_IO10

E19

E18

A17

B17

U9

NVCC_GPIO

NVCC_JTAG

GPIO

ALT5

—

GPIO1_IO10

GPIO1_IO11

GPIO1_IO12

GPIO1_IO13

JTAG_MOD

Input

Keeper

GPIO1_IO11

GPIO1_IO12

GPIO1_IO13

JTAG_MOD

100 kΩ

pull-up

JTAG_TCK

JTAG_TDI

V10

V12

NVCC_JTAG

GPIO

—

JTAG_TCK

JTAG_TDI

Input

47 kΩ

pull-up

47 kΩ

pull-up

JTAG_TDO

JTAG_TMS

W9

NVCC_JTAG

GPIO

—

JTAG_TDO

JTAG_TMS

Output

Input

Keeper

W12

47 kΩ

pull-up

JTAG_TRST_B

V13

NVCC_JTAG

GPIO

—

JTAG_TRST_B

Input

47 kΩ

pull-up

KEY_COL0

C23

C22

B23

B22

A22

A21

B21

C21

D21

D22

H21

J23

J22

K20

K19

K18

J19

J18

H23

H22

NVCC_KEY

NVCC_LCD1

GPIO

ALT5

GPIO2_IO10

GPIO2_IO11

GPIO2_IO12

GPIO2_IO13

GPIO2_IO14

GPIO2_IO15

GPIO2_IO16

GPIO2_IO17

GPIO2_IO18

GPIO2_IO19

GPIO3_IO00

GPIO3_IO01

GPIO3_IO02

GPIO3_IO03

GPIO3_IO04

GPIO3_IO05

GPIO3_IO06

GPIO3_IO07

GPIO3_IO08

GPIO3_IO09

Input

Keeper

KEY_COL1

KEY_COL2

KEY_COL3

KEY_COL4

KEY_ROW0

KEY_ROW1

KEY_ROW2

KEY_ROW3

KEY_ROW4

LCD1_CLK

LCD1_DATA00

LCD1_DATA01

LCD1_DATA02

LCD1_DATA03

LCD1_DATA04

LCD1_DATA05

LCD1_DATA06

LCD1_DATA07

LCD1_DATA08

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Table 109. 19x19 mm Functional Contact Assignments (continued)

Out of Reset Condition

19x19

Ball

Power

Group

Ball

Type

Ball Name

Default

Mode

Default

Function

Input/

Output

Value

LCD1_DATA09

H20

H19

H18

G23

G22

G21

G19

G18

F23

F22

F21

G20

F19

F18

E20

E21

D23

E22

E23

T20

T21

V22

V23

V20

V21

U22

U23

T22

T23

AB7

AB8

AC9

AB9

NVCC_LCD1

NVCC_LVDS

NVCC_NAND

GPIO

LVDS

GPIO

ALT5

—

GPIO3_IO10

GPIO3_IO11

GPIO3_IO12

GPIO3_IO13

GPIO3_IO14

GPIO3_IO15

GPIO3_IO16

GPIO3_IO17

GPIO3_IO18

GPIO3_IO19

GPIO3_IO20

GPIO3_IO21

GPIO3_IO22

GPIO3_IO23

GPIO3_IO24

GPIO3_IO25

GPIO3_IO26

GPIO3_IO27

GPIO3_IO28

LVDS_CLK_N

LVDS_CLK_P

LVDS_DATA0_N

LVDS_DATA0_P

LVDS_DATA1_N

LVDS_DATA1_P

LVDS_DATA2_N

LVDS_DATA2_P

LVDS_DATA3_N

LVDS_DATA3_P

GPIO4_IO00

GPIO4_IO01

GPIO4_IO02

GPIO4_IO03

Input

—

Keeper

—

LCD1_DATA10

LCD1_DATA11

LCD1_DATA12

LCD1_DATA13

LCD1_DATA14

LCD1_DATA15

LCD1_DATA16

LCD1_DATA17

LCD1_DATA18

LCD1_DATA19

LCD1_DATA20

LCD1_DATA21

LCD1_DATA22

LCD1_DATA23

LCD1_ENABLE

LCD1_HSYNC

LCD1_RESET

LCD1_VSYNC

LVDS_CLK_N

LVDS_CLK_P

LVDS_DATA0_N

LVDS_DATA0_P

LVDS_DATA1_N

LVDS_DATA1_P

LVDS_DATA2_N

LVDS_DATA2_P

LVDS_DATA3_N

LVDS_DATA3_P

NAND_ALE

ALT0

—

Input

—

ALT0

—

Input

—

ALT0

—

Input

—

ALT0

—

Input

—

ALT0

ALT5

Input

—

Keeper

NAND_CE0_B

NAND_CE1_B

NAND_CLE

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Table 109. 19x19 mm Functional Contact Assignments (continued)

Out of Reset Condition

19x19

Ball

Power

Group

Ball

Type

Ball Name

Default

Mode

Default

Function

Input/

Output

Value

NAND_DATA00

NAND_DATA01

NAND_DATA02

NAND_DATA03

NAND_DATA04

NAND_DATA05

NAND_DATA06

NAND_DATA07

NAND_RE_B

V7

AA8

W8

NVCC_NAND

VDD_SNVS_IN

GPIO

ALT5

—

GPIO4_IO04

GPIO4_IO05

GPIO4_IO06

GPIO4_IO07

GPIO4_IO08

GPIO4_IO09

GPIO4_IO10

GPIO4_IO11

GPIO4_IO12

GPIO4_IO13

GPIO4_IO14

GPIO4_IO15

ONOFF

Input

Keeper

V6

W7

W5

Y8

W6

AA9

AC7

AA7

AC8

W17

NAND_READY_B

NAND_WE_B

NAND_WP_B

ONOFF

100 kΩ

pull-up

PCIE_RX_N

PCIE_RX_P

PCIE_TX_N

PCIE_TX_P

POR_B

N22

N23

P22

P23

V17

PCIE_VPH

—

PCIE_RX_N

PCIE_RX_P

PCIE_TX_N

PCIE_TX_P

POR_B

—

PCIE_VPH

—

PCIE_VPH

—

VDD_SNVS_IN

GPIO

Input

100 kΩ

pull-up

QSPI1A_DATA0

QSPI1A_DATA1

QSPI1A_DATA2

QSPI1A_DATA3

QSPI1A_DQS

C16

E16

D16

C17

E13

E17

F16

F17

C14

E14

D14

C15

C13

E15

NVCC_QSPI

GPIO

ALT5

GPIO4_IO16

GPIO4_IO17

GPIO4_IO18

GPIO4_IO19

GPIO4_IO20

GPIO4_IO21

GPIO4_IO22

GPIO4_IO23

GPIO4_IO24

GPIO4_IO25

GPIO4_IO26

GPIO4_IO27

GPIO4_IO28

GPIO4_IO29

Input

Keeper

QSPI1A_SCLK

QSPI1A_SS0_B

QSPI1A_SS1_B

QSPI1B_DATA0

QSPI1B_DATA1

QSPI1B_DATA2

QSPI1B_DATA3

QSPI1B_DQS

QSPI1B_SCLK

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Table 109. 19x19 mm Functional Contact Assignments (continued)

Out of Reset Condition

19x19

Ball

Power

Group

Ball

Type

Ball Name

Default

Mode

Default

Function

Input/

Output

Value

QSPI1B_SS0_B

QSPI1B_SS1_B

RGMII1_RD0

RGMII1_RD1

RGMII1_RD2

RGMII1_RD3

RGMII1_RX_CTL

RGMII1_RXC

RGMII1_TD0

RGMII1_TD1

RGMII1_TD2

RGMII1_TD3

RGMII1_TX_CTL

RGMII1_TXC

RGMII2_RD0

RGMII2_RD1

RGMII2_RD2

RGMII2_RD3

RGMII2_RX_CTL

RGMII2_RXC

RGMII2_TD0

RGMII2_TD1

RGMII2_TD2

RGMII2_TD3

RGMII2_TX_CTL

RGMII2_TXC

RTC_XTALI

F14

F15

D8

NVCC_QSPI

GPIO

—

ALT5

—

GPIO4_IO30

GPIO4_IO31

GPIO5_IO00

GPIO5_IO01

GPIO5_IO02

GPIO5_IO03

GPIO5_IO04

GPIO5_IO05

GPIO5_IO06

GPIO5_IO07

GPIO5_IO08

GPIO5_IO09

GPIO5_IO10

GPIO5_IO11

GPIO5_IO12

GPIO5_IO13

GPIO5_IO14

GPIO5_IO15

GPIO5_IO16

GPIO5_IO17

GPIO5_IO18

GPIO5_IO19

GPIO5_IO20

GPIO5_IO21

GPIO5_IO22

GPIO5_IO23

RTC_XTALI

RTC_XTALO

GPIO6_IO00

GPIO6_IO01

GPIO6_IO02

GPIO6_IO03

GPIO6_IO04

Input

—

Keeper

—

NVCC_RGMII1

NVCC_RGMII2

E9

C8

E8

E10

D10

C12

D12

E12

C11

C10

E11

A9

B9

A8

B8

B10

A10

A12

B12

A13

B13

B11

A11

AB20 VDD_SNVS_CAP

AC20 VDD_SNVS_CAP

RTC_XTALO

SD1_CLK

—

A15

B15

B16

A16

B14

NVCC_SD1

GPIO

ALT5

Input

Keeper

SD1_CMD

SD1_DATA0

SD1_DATA1

SD1_DATA2

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Table 109. 19x19 mm Functional Contact Assignments (continued)

Out of Reset Condition

19x19

Ball

Power

Group

Ball

Type

Ball Name

Default

Mode

Default

Function

Input/

Output

Value

SD1_DATA3

A14

F12

F11

G13

F13

F10

G10

Y12

NVCC_SD1

NVCC_SD2

GPIO

ALT5

GPIO6_IO05

GPIO6_IO06

GPIO6_IO07

GPIO6_IO08

GPIO6_IO09

GPIO6_IO10

GPIO6_IO11

GPIO7_IO00

Input

Keeper

SD2_CLK

SD2_CMD

SD2_DATA0

SD2_DATA1

SD2_DATA2

SD2_DATA3

SD3_CLK

NVCC_LOW

NVCC_HIGH

100 kΩ

pull-down

SD3_CMD

W13

AA11

W10

NVCC_LOW

NVCC_HIGH

GPIO

ALT5

GPIO7_IO01

GPIO7_IO02

GPIO7_IO03

GPIO7_IO04

GPIO7_IO05

GPIO7_IO06

GPIO7_IO07

GPIO7_IO08

GPIO7_IO09

Input

100 kΩ

pull-down

SD3_DATA0

SD3_DATA1

SD3_DATA2

SD3_DATA3

SD3_DATA4

SD3_DATA5

SD3_DATA6

SD3_DATA7

NVCC_LOW

NVCC_HIGH

100 kΩ

pull-down

NVCC_LOW

NVCC_HIGH

100 kΩ

pull-down

AA15

Y14

NVCC_LOW

NVCC_HIGH

100 kΩ

pull-down

NVCC_LOW

NVCC_HIGH

100 kΩ

pull-down

AA14

AA13

AA12

W11

NVCC_LOW

NVCC_HIGH

100 kΩ

pull-down

NVCC_LOW

NVCC_HIGH

100 kΩ

pull-down

NVCC_LOW

NVCC_HIGH

100 kΩ

pull-down

NVCC_LOW

NVCC_HIGH

100 kΩ

pull-down

SD4_CLK

AB12

AB13

AC10

AB10

AC14

AB14

AC13

AC12

AC11

NVCC_SD4

GPIO

ALT5

GPIO6_IO12

GPIO6_IO13

GPIO6_IO14

GPIO6_IO15

GPIO6_IO16

GPIO6_IO17

GPIO6_IO18

GPIO6_IO19

GPIO6_IO20

Input

Keeper

SD4_CMD

SD4_DATA0

SD4_DATA1

SD4_DATA2

SD4_DATA3

SD4_DATA4

SD4_DATA5

SD4_DATA6

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Table 109. 19x19 mm Functional Contact Assignments (continued)

Out of Reset Condition

19x19

Ball

Power

Group

Ball

Type

Ball Name

Default

Mode

Default

Function

Input/

Output

Value

SD4_DATA7

AB11

Y9

NVCC_SD4

GPIO

ALT5

—

GPIO6_IO21

GPIO6_IO22

Input

Keeper

SD4_RESET_B

SNVS_PMIC_ON_REQ¹

W16

VDD_SNVS_IN

SNVS_PMIC_ON_REQ

Output

100 kΩ

pull-up

SNVS_TAMPER

TEST_MODE

V14

Y16

Y5

VDD_SNVS_IN

NVCC_USB_H

GPIO

—

SNVS_TAMPER

TEST_MODE

GPIO7_IO10

GPIO7_IO11

Input

100 kΩ

pull-down

—

100 kΩ

pull-down

USB_H_DATA

USB_H_STROBE

GPIO

ALT5

100 kΩ

pull-down

Y6

100 kΩ

pull-down

USB_OTG1_CHD_B

USB_OTG1_DN

USB_OTG1_DP

USB_OTG2_DN

USB_OTG2_DP

Reserved

V19

Y21

VDD_USB_CAP

—

USB_OTG1_CHD_B

—

USB_OTG1_DN

AA21

Y19

USB_OTG1_DP

USB_OTG2_DN

AA19

L23

USB_OTG2_DP

—

Reserved

L22

—

Reserved

K23

—

Reserved

K22

—

XTALI

AB22

AC22

NVCC_PLL

XTALI

XTALO

1

On silicon revisions prior to 1.2, the SNVS_PMIC_ON_REQ may briefly go low and then return high during POR. SNVS_PMIC_ON_REQ should be

high during POR. An external 100k pull-up is required.

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6.3.3

19x19 mm, 0.8 mm Pitch, 23x23 Ball Map

Table 110 shows the 19x19 mm, 0.8 mm pitch ball map for the i.MX 6SoloX.

Table 110. 19x19 mm, 0.8 mm Pitch, 23x23 Ball Map

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Table 110. 19x19 mm, 0.8 mm Pitch, 23x23 Ball Map (continued)

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Table 110. 19x19 mm, 0.8 mm Pitch, 23x23 Ball Map (continued)

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Table 110. 19x19 mm, 0.8 mm Pitch, 23x23 Ball Map (continued)

6.4

17x17 mm Package Information

6.4.1

17x17 mm Package Comparison

The i.MX 6SoloX comes in two versions in a 17x17 mm package:

•

The 17x17 NP (No PCIe) package does not support PCIe but supports an increased number of ADC

input channels.

•

The 17x17 WP (With PCIe) package supports PCIe with a reduced number of ADC input channels.

Note that the package pinouts have differences beyond the PCIe and ADC signals.

A summary of the difference between the two packages is shown in Table 111 below. All other signals have

the same ball number on both 17x17 package versions.

Table 111. Pinout Differences Between 17x17 NP and 17x17 WP Packages

17x17 NP Package

(No PCIe)

17x17 WP Package

(With PCIe)

Ball Name

M18

N19

N20

V15

U14

V16

R14

Y15

W15

Y16

L18

M18

LCD1_DATA01

LCD1_DATA03

LCD1_DATA04

SD3_DATA2

SD3_DATA4

ADC_VREFH¹

ADC_VREFL¹

ADC1_IN2

N17

U14

T14

Not in this package

ADC1_IN3

ADC2_IN0

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Table 111. Pinout Differences Between 17x17 NP and 17x17 WP Packages (continued)

17x17 NP Package

(No PCIe)

17x17 WP Package

(With PCIe)

Ball Name

W16

Not in this package

ADC2_IN1

ADC2_IN2

T16

Not in this package

U16

Not in this package

ADC2_IN3

N15

U20

U19

BOOT_MODE0

BOOT_MODE1

CCM_CLK1_N

CCM_CLK1_P

CCM_CLK2

P14

P19

P16

P20

R16

T14

R15

N16

P15

CCM_PMIC_STBY_REQ

GPANAIO

T15

U16

U18

W20

N15

NVCC_PLL

R15

ONOFF

Not in this package

N18

PCIE_REXT

Not in this package

P19

PCIE_RX_N

Not in this package

P20

PCIE_RX_P

Not in this package

R19

PCIE_TX_N

Not in this package

R20

PCIE_TX_P

Not in this package

P18

PCIE_VP

L18

Not in this package

R18

PCIE_VP_CAP²

PCIE_VPH

Not in this package

P17

PCIE_VPTX

R16

V19

V20

P16

P15

W20

W19

Y19

T17

W17

Y17

P14

POR_B

W19

Y19

RTC_XTALI

RTC_XTALO

SNVS_PMIC_ON_REQ

SNVS_TAMPER

USB_OTG1_CHD_B

USB_OTG1_DN

USB_OTG1_DP

USB_OTG1_VBUS

USB_OTG2_DN

USB_OTG2_DP

N16

R14

T17

W17

Y17

T16

W15

Y15

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Table 111. Pinout Differences Between 17x17 NP and 17x17 WP Packages (continued)

17x17 NP Package

(No PCIe)

17x17 WP Package

(With PCIe)

Ball Name

U17

T15

USB_OTG2_VBUS

VDD_HIGH_CAP

VDD_HIGH_IN

VDD_SNVS_CAP

VDD_SNVS_IN

VDD_USB_CAP

VSS

N17

V17

N18

V18

P17

U17

P18

U18

T18

V16

R18

T18

V17

V15

R19

N19

R20

N20

VSS

U19

T19

VSS

U20

T20

VSS

V18

Not in this package

T19

Not in this package

VSS

W16

Y16

V19

V20

VSS

XTALI

T20

XTALO

1

2

In the 17x17 WP package, ADC_VREFL is connected internally to VSS. ADC_VREFH is

connected internally to VDDA_ADC_3P3.

In the 17x17 NP package, PCIE_VP_CAP must be connected to an external 4.7uF filter capacitor.

6.4.2

17x17 mm, 0.8 mm Pitch, 20x20 Ball Matrix

Figure 85 shows the top, bottom, and side views of the 17×17 mm BGA package.

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Figure 85. 17x17 mm BGA Package—Top, Bottom, and Side Views

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Package Information and Contact Assignments

Figure 86. 17x17 mm BGA Package Notes

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6.4.3

17x17 mm NP (No PCIe) Supplies Contact Assignments and

Functional Contact Assignments

Table 112 shows supplies contact assignments for the 17x17 mm NP (No PCIe) package.

Table 112. 17x17 mm NP (no PCIe) Supplies Contact Assignments

17x17 NP [No PCIe]

Ball(s) Position(s)

Supply Rail Name

Remark

ADC high reference voltage

ADC_VREFH

ADC_VREFL

DRAM_VREF

V16

R14

J3

ADC low reference voltage

DDR voltage reference input. Connect to a voltage source that

is 50% of NVCC_DRAM.

DRAM_ZQPAD

GPANAIO

C5

DDR output buffer driver calibration reference voltage input.

Connect DRAM_ZQPAD to an external 240 ohm 1% resistor to

Vss.

T15

Analog output for NXP use only. This output must always be left

unconnected.

NGND_KEL0

NVCC_DRAM

NVCC_DRAM_2P5

NVCC_ENET

NVCC_GPIO

NVCC_HIGH

P13

Connect to Vss

G6, H6, J6, K6, L6, M6, N6, P6

Supply input for the DDR I/O interface

Supply input for the DDR interface

Supply input for the ENET interfaces

Supply input for the GPIO interface

K7

F6

F15

R12

3.3 V Supply input for the dual-voltage I/Os on the SD3

interface

NVCC_JTAG

NVCC_KEY

NVCC_LCD1

NVCC_LOW

R11

G15

H15

V13

Supply input for the JTAG interface

Supply input for the Key Pad Port (KPP) interface

Supply input for the LCD interface

1.8 V Supply input for the dual-voltage I/Os on the SD3

interface

NVCC_NAND

NVCC_PLL

R6

U18

F14

F8

Supply input for the Raw NAND flash memories interface

Supply input for the PLLs

NVCC_QSPI

Supply input for the QSPI interface

Supply input for the RGMII1 interface

Supply input for the RGMII2 interface

Supply input for the SD2 interface

Supply input for the SD4 interface

Supply input for the USB HSIC interface

PCIe LDO output

NVCC_RGMII1

NVCC_RGMII2

NVCC_SD2

F9

F13

V10

V5

NVCC_SD4

NVCC_USB_H

PCIE_VP_CAP

USB_OTG1_VBUS

L18

T17

VBUS input for USB_OTG1

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Package Information and Contact Assignments

Table 112. 17x17 mm NP (no PCIe) Supplies Contact Assignments (continued)

17x17 NP [No PCIe]

Ball(s) Position(s)

Supply Rail Name

Remark

VBUS input for USB_OTG2

USB_OTG2_VBUS

VDD_ARM_CAP

U17

C16, D16, H10, H11, H12, H13, Supply voltage output from internal LDO_ARM. Requires

J13, K13, L13

H18, J10, J11, J12, K12, L12

N17, N18

external capacitor(s).

VDD_ARM_IN

Supply voltage input for internal LDO_ARM.

VDD_HIGH_CAP

Supply voltage output from internal LDO_2P5. Requires

external capacitor(s).

VDD_HIGH_IN

P17, P18

T18

Supply voltage input to internal LDO_2P5, LDO_1P1 and

LDO_SNVS.

VDD_SNVS_CAP

Supply voltage output from internal LDO_SNVS. Requires

external capacitor(s).

VDD_SNVS_IN

VDD_SOC_CAP

R18

Supply voltage input to the SNVS voltage domain

H8, H9, J8, K8, L8, M8, M13, N8, Supply voltage output from internal LDO_SOC. Requires

N9, N10, N11, N12, V8

external capacitor(s).

VDD_SOC_IN

VDD_USB_CAP

VDDA_ADC_3P3

VSS

C7, C8, J9, K9, L9,

M9, M10, M11, M12

Supply voltage input to internal LDO_SOC and LDO_PCIE

V17

Supply voltage output from internal LDO_USB. Requires

external capacitor(s).

R13

Supply voltage input to the ADC. This supply must be provided

even if the ADC is not used.

A1, A20, C3, C4, C18, D6, D9, D12, Ground

D15, E3, F3, F5, F17, G7, G8, G9,

G10, G11, G12, G13, G14, H3, H7,

H14, J7, J14, J17, K3, K10, K11,

K14, L3, L7, L10, L11, L14, M7,

M14, M17, N3, N7, N13, P7, P8,

P9, P10, P11, P12, R3, R5, R17,

R19, R20, T3, U6, U9, U12, U15,

U19, U20, V3, V4, V18, W18, Y1,

Y18, Y20

Table 113 shows an alpha-sorted list of functional contact assignments for the 17x17 mm NP (No PCIe)

package.

Table 113. 17x17 mm NP (No PCIe) Functional Contact Assignments

Out of Reset Condition

17x17

Power

Group

Ball

Type

Ball Name

NP

Ball

Default

Mode

Default

Function

Input/

Output

Value

ADC1_IN0

Y14

W14

Y15

VDDA_ADC_3P3

—

ADC1_IN0

ADC1_IN1

ADC1_IN2

Input

—

ADC1_IN1

ADC1_IN2

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NXP Semiconductors

Package Information and Contact Assignments

Table 113. 17x17 mm NP (No PCIe) Functional Contact Assignments (continued)

Out of Reset Condition

17x17

NP

Ball

Power

Group

Ball

Type

Ball Name

Default

Mode

Default

Input/

Value

Function

Output

ADC1_IN3

W15

Y16

W16

T16

U16

N15

VDDA_ADC_3P3

VDD_SNVS_IN

—

ADC1_IN3

ADC2_IN0

Input

—

ADC2_IN0

ADC2_IN1

ADC2_IN2

ADC2_IN3

BOOT_MODE0

—

ADC2_IN1

—

ADC2_IN2

—

ADC2_IN3

GPIO

BOOT_MODE0

100 kΩ

pull-down

BOOT_MODE1

P14

VDD_SNVS_IN

GPIO

—

BOOT_MODE1

Input

100 kΩ

pull-down

CCM_CLK1_N

CCM_CLK1_P

CCM_CLK2

P19

P20

T14

VDD_HIGH_CAP

VDD_SNVS_IN

NVCC_DRAM

—

CCM_CLK1_N

CCM_CLK1_P

CCM_CLK2

—

0

—

CCM_PMIC_STBY_REQ N16

GPIO

DDR

CCM_PMIC_STBY_REQ Output

DRAM_ADDR00

DRAM_ADDR01

DRAM_ADDR02

DRAM_ADDR03

DRAM_ADDR04

DRAM_ADDR05

DRAM_ADDR06

DRAM_ADDR07

DRAM_ADDR08

DRAM_ADDR09

DRAM_ADDR10

L4

U4

K5

G5

M3

G4

T4

F4

M5

L5

DRAM_ADDR00

DRAM_ADDR01

DRAM_ADDR02

DRAM_ADDR03

DRAM_ADDR04

DRAM_ADDR05

DRAM_ADDR06

DRAM_ADDR07

DRAM_ADDR08

DRAM_ADDR09

DRAM_ADDR10

Output

100 kΩ

pull-up

NVCC_DRAM

DDR

—

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

N5

100 kΩ

pull-up

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Package Information and Contact Assignments

Table 113. 17x17 mm NP (No PCIe) Functional Contact Assignments (continued)

Out of Reset Condition

17x17

NP

Ball

Power

Group

Ball

Type

Ball Name

Default

Mode

Default

Input/

Value

Function

Output

DRAM_ADDR11

DRAM_ADDR12

DRAM_ADDR13

DRAM_ADDR14

DRAM_CAS_B

DRAM_CS0_B

DRAM_CS1_B

DRAM_DATA00

DRAM_DATA01

DRAM_DATA02

DRAM_DATA03

DRAM_DATA04

DRAM_DATA05

DRAM_DATA06

DRAM_DATA07

DRAM_DATA08

DRAM_DATA09

DRAM_DATA10

DRAM_DATA11

N4

P4

M4

R4

J4

NVCC_DRAM

DDR

—

DRAM_ADDR11

DRAM_ADDR12

DRAM_ADDR13

DRAM_ADDR14

DRAM_CAS_B

DRAM_CS0_B

DRAM_CS1_B

DRAM_DATA00

DRAM_DATA01

DRAM_DATA02

DRAM_DATA03

DRAM_DATA04

DRAM_DATA05

DRAM_DATA06

DRAM_DATA07

DRAM_DATA08

DRAM_DATA09

DRAM_DATA10

DRAM_DATA11

Output

100 kΩ

pull-up

Output

Input

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

H4

D3

R1

T2

T1

R2

M1

M2

L2

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

Input

100 kΩ

pull-up

Input

100 kΩ

pull-up

Input

100 kΩ

pull-up

Input

100 kΩ

pull-up

Input

100 kΩ

pull-up

Input

100 kΩ

pull-up

N1

H1

F2

K2

J2

Input

100 kΩ

pull-up

Input

100 kΩ

pull-up

Input

100 kΩ

pull-up

Input

100 kΩ

pull-up

Input

100 kΩ

pull-up

i.MX 6SoloX Applications Processors for Industrial Products, Rev. 4, 11/2018

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NXP Semiconductors

Package Information and Contact Assignments

Table 113. 17x17 mm NP (No PCIe) Functional Contact Assignments (continued)

Out of Reset Condition

17x17

NP

Ball

Power

Group

Ball

Type

Ball Name

Default

Mode

Default

Input/

Value

Function

Output

DRAM_DATA12

DRAM_DATA13

DRAM_DATA14

DRAM_DATA15

DRAM_DATA16

DRAM_DATA17

DRAM_DATA18

DRAM_DATA19

DRAM_DATA20

DRAM_DATA21

DRAM_DATA22

DRAM_DATA23

DRAM_DATA24

DRAM_DATA25

DRAM_DATA26

DRAM_DATA27

DRAM_DATA28

DRAM_DATA29

DRAM_DATA30

J1

F1

E2

E1

V1

W4

Y4

U2

W3

Y2

U1

V2

A2

D1

C1

D2

C2

B3

B4

NVCC_DRAM

DDR

—

DRAM_DATA12

DRAM_DATA13

DRAM_DATA14

DRAM_DATA15

DRAM_DATA16

DRAM_DATA17

DRAM_DATA18

DRAM_DATA19

DRAM_DATA20

DRAM_DATA21

DRAM_DATA22

DRAM_DATA23

DRAM_DATA24

DRAM_DATA25

DRAM_DATA26

DRAM_DATA27

DRAM_DATA28

DRAM_DATA29

DRAM_DATA30

Input

100 kΩ

pull-up

Input

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

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157

Package Information and Contact Assignments

Table 113. 17x17 mm NP (No PCIe) Functional Contact Assignments (continued)

Out of Reset Condition

17x17

NP

Ball

Power

Group

Ball

Type

Ball Name

Default

Mode

Default

Input/

Value

Function

Output

DRAM_DATA31

DRAM_DQM0

DRAM_DQM1

DRAM_DQM2

DRAM_DQM3

DRAM_ODT0

DRAM_RAS_B

DRAM_RESET

DRAM_SDBA0

DRAM_SDBA1

DRAM_SDBA2

DRAM_SDCKE0

DRAM_SDCKE1

A4

N2

G2

Y3

A3

U3

H5

D4

G3

P3

K4

P5

E4

NVCC_DRAM

DDR

—

DRAM_DATA31

DRAM_DQM0

DRAM_DQM1

DRAM_DQM2

DRAM_DQM3

DRAM_ODT0

DRAM_RAS_B

DRAM_RESET

DRAM_SDBA0

DRAM_SDBA1

DRAM_SDBA2

DRAM_SDCKE0

DRAM_SDCKE1

Input

100 kΩ

pull-up

Output

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-down

100 kΩ

pull-up

100 kΩ

pull-down

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-down

100 kΩ

pull-down

DRAM_SDCLK0_N

DRAM_SDCLK0_P

DRAM_SDQS0_N

DRAM_SDQS0_P

DRAM_SDQS1_N

DRAM_SDQS1_P

DRAM_SDQS2_N

DRAM_SDQS2_P

DRAM_SDQS3_N

DRAM_SDQS3_P

L1

K1

P2

P1

H2

G1

W1

W2

B2

B1

NVCC_DRAM

DDRCLK

—

DRAM_SDCLK0_N

DRAM_SDCLK0_P

DRAM_SDQS0_N

DRAM_SDQS0_P

DRAM_SDQS1_N

DRAM_SDQS1_P

DRAM_SDQS2_N

DRAM_SDQS2_P

DRAM_SDQS3_N

DRAM_SDQS3_P

—

Output

—

Low

—

Input

—

Input

—

Input

—

Input

—

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NXP Semiconductors

Package Information and Contact Assignments

Table 113. 17x17 mm NP (No PCIe) Functional Contact Assignments (continued)

Out of Reset Condition

17x17

NP

Ball

Power

Group

Ball

Type

Ball Name

Default

Mode

Default

Input/

Value

Function

Output

DRAM_SDWE_B

J5

NVCC_DRAM

DDR

—

DRAM_SDWE_B

Output

100 kΩ

pull-up

ENET1_COL

ENET1_CRS

ENET1_MDC

ENET1_MDIO

ENET1_RX_CLK

ENET1_TX_CLK

ENET2_COL

ENET2_CRS

ENET2_RX_CLK

ENET2_TX_CLK

GPIO1_IO00

GPIO1_IO01

GPIO1_IO02

GPIO1_IO03

GPIO1_IO04

GPIO1_IO05

GPIO1_IO06

GPIO1_IO07

GPIO1_IO08

GPIO1_IO09

GPIO1_IO10

GPIO1_IO11

GPIO1_IO12

GPIO1_IO13

JTAG_MOD

B5

C6

NVCC_ENET

NVCC_GPIO

NVCC_JTAG

GPIO

ALT5

—

GPIO2_IO00

GPIO2_IO01

GPIO2_IO02

GPIO2_IO03

GPIO2_IO04

GPIO2_IO05

GPIO2_IO06

GPIO2_IO07

GPIO2_IO08

GPIO2_IO09

GPIO1_IO00

GPIO1_IO01

GPIO1_IO02

GPIO1_IO03

GPIO1_IO04

GPIO1_IO05

GPIO1_IO06

GPIO1_IO07

GPIO1_IO08

GPIO1_IO09

GPIO1_IO10

GPIO1_IO11

GPIO1_IO12

GPIO1_IO13

JTAG_MOD

Input

Keeper

B6

A6

A5

F7

E7

E6

E5

D5

C19

D19

C20

D20

A18

B18

D18

A17

B17

A19

B19

B20

B16

A16

R7

100 kΩ

pull-up

JTAG_TCK

JTAG_TDI

R9

NVCC_JTAG

GPIO

—

JTAG_TCK

JTAG_TDI

Input

47 kΩ

pull-up

R10

47 kΩ

pull-up

i.MX 6SoloX Applications Processors for Industrial Products, Rev. 4, 11/2018

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Package Information and Contact Assignments

Table 113. 17x17 mm NP (No PCIe) Functional Contact Assignments (continued)

Out of Reset Condition

17x17

NP

Ball

Power

Group

Ball

Type

Ball Name

Default

Mode

Default

Input/

Value

Function

Output

JTAG_TDO

R8

NVCC_JTAG

GPIO

—

JTAG_TDO

JTAG_TMS

Output

Input

Keeper

JTAG_TMS

T10

47 kΩ

pull-up

JTAG_TRST_B

T9

NVCC_JTAG

GPIO

—

JTAG_TRST_B

Input

47 kΩ

pull-up

KEY_COL0

G20

F20

G18

E20

E19

F16

E18

F18

F19

G19

L17

M20

M18

M19

N19

N20

M16

M15

L20

K18

L16

L19

L15

K16

K15

K17

H16

NVCC_KEY

NVCC_LCD1

GPIO

ALT5

GPIO2_IO10

GPIO2_IO11

GPIO2_IO12

GPIO2_IO13

GPIO2_IO14

GPIO2_IO15

GPIO2_IO16

GPIO2_IO17

GPIO2_IO18

GPIO2_IO19

GPIO3_IO00

GPIO3_IO01

GPIO3_IO02

GPIO3_IO03

GPIO3_IO04

GPIO3_IO05

GPIO3_IO06

GPIO3_IO07

GPIO3_IO08

GPIO3_IO09

GPIO3_IO10

GPIO3_IO11

GPIO3_IO12

GPIO3_IO13

GPIO3_IO14

GPIO3_IO15

GPIO3_IO16

Input

Keeper

KEY_COL1

KEY_COL2

KEY_COL3

KEY_COL4

KEY_ROW0

KEY_ROW1

KEY_ROW2

KEY_ROW3

KEY_ROW4

LCD1_CLK

LCD1_DATA00

LCD1_DATA01

LCD1_DATA02

LCD1_DATA03

LCD1_DATA04

LCD1_DATA05

LCD1_DATA06

LCD1_DATA07

LCD1_DATA08

LCD1_DATA09

LCD1_DATA10

LCD1_DATA11

LCD1_DATA12

LCD1_DATA13

LCD1_DATA14

LCD1_DATA15

i.MX 6SoloX Applications Processors for Industrial Products, Rev. 4, 11/2018

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NXP Semiconductors

Package Information and Contact Assignments

Table 113. 17x17 mm NP (No PCIe) Functional Contact Assignments (continued)

Out of Reset Condition

17x17

NP

Ball

Power

Group

Ball

Type

Ball Name

Default

Mode

Default

Input/

Value

Function

Output

LCD1_DATA16

LCD1_DATA17

LCD1_DATA18

LCD1_DATA19

LCD1_DATA20

LCD1_DATA21

LCD1_DATA22

LCD1_DATA23

LCD1_ENABLE

LCD1_HSYNC

LCD1_RESET

LCD1_VSYNC

NAND_ALE

H20

K19

K20

J20

H17

G17

H19

G16

J19

J16

J18

J15

W6

U7

NVCC_LCD1

NVCC_NAND

VDD_SNVS_IN

GPIO

ALT5

—

GPIO3_IO17

GPIO3_IO18

GPIO3_IO19

GPIO3_IO20

GPIO3_IO21

GPIO3_IO22

GPIO3_IO23

GPIO3_IO24

GPIO3_IO25

GPIO3_IO26

GPIO3_IO27

GPIO3_IO28

GPIO4_IO00

GPIO4_IO01

GPIO4_IO02

GPIO4_IO03

GPIO4_IO04

GPIO4_IO05

GPIO4_IO06

GPIO4_IO07

GPIO4_IO08

GPIO4_IO09

GPIO4_IO10

GPIO4_IO11

GPIO4_IO12

GPIO4_IO13

GPIO4_IO14

GPIO4_IO15

ONOFF

Input

Keeper

NAND_CE0_B

NAND_CE1_B

NAND_CLE

V9

T8

NAND_DATA00

NAND_DATA01

NAND_DATA02

NAND_DATA03

NAND_DATA04

NAND_DATA05

NAND_DATA06

NAND_DATA07

NAND_RE_B

V6

W8

Y7

U5

W7

T5

Y8

T6

U8

NAND_READY_B

NAND_WE_B

NAND_WP_B

ONOFF

Y6

T7

V7

R15

100 kΩ

pull-up

POR_B

R16

VDD_SNVS_IN

GPIO

—

POR_B

Input

100 kΩ

pull-up

i.MX 6SoloX Applications Processors for Industrial Products, Rev. 4, 11/2018

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161

Package Information and Contact Assignments

Table 113. 17x17 mm NP (No PCIe) Functional Contact Assignments (continued)

Out of Reset Condition

17x17

NP

Ball

Power

Group

Ball

Type

Ball Name

Default

Mode

Default

Input/

Value

Function

Output

QSPI1A_DATA0

QSPI1A_DATA1

QSPI1A_DATA2

QSPI1A_DATA3

QSPI1A_DQS

QSPI1A_SCLK

QSPI1A_SS0_B

QSPI1A_SS1_B

QSPI1B_DATA0

QSPI1B_DATA1

QSPI1B_DATA2

QSPI1B_DATA3

QSPI1B_DQS

QSPI1B_SCLK

QSPI1B_SS0_B

QSPI1B_SS1_B

RGMII1_RD0

E15

C15

D14

E16

A13

D17

C17

E17

B14

A14

D13

C13

B13

B15

C14

A15

D8

NVCC_QSPI

NVCC_RGMII1

NVCC_RGMII2

GPIO

ALT5

GPIO4_IO16

GPIO4_IO17

GPIO4_IO18

GPIO4_IO19

GPIO4_IO20

GPIO4_IO21

GPIO4_IO22

GPIO4_IO23

GPIO4_IO24

GPIO4_IO25

GPIO4_IO26

GPIO4_IO27

GPIO4_IO28

GPIO4_IO29

GPIO4_IO30

GPIO4_IO31

GPIO5_IO00

GPIO5_IO01

GPIO5_IO02

GPIO5_IO03

GPIO5_IO04

GPIO5_IO05

GPIO5_IO06

GPIO5_IO07

GPIO5_IO08

GPIO5_IO09

GPIO5_IO10

GPIO5_IO11

GPIO5_IO12

GPIO5_IO13

GPIO5_IO14

Input

Keeper

RGMII1_RD1

C9

RGMII1_RD2

D7

RGMII1_RD3

E8

RGMII1_RX_CTL

RGMII1_RXC

RGMII1_TD0

C10

E9

D11

C12

E11

D10

E10

C11

A8

RGMII1_TD1

RGMII1_TD2

RGMII1_TD3

RGMII1_TX_CTL

RGMII1_TXC

RGMII2_RD0

RGMII2_RD1

B8

RGMII2_RD2

A7

i.MX 6SoloX Applications Processors for Industrial Products, Rev. 4, 11/2018

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NXP Semiconductors

Package Information and Contact Assignments

Table 113. 17x17 mm NP (No PCIe) Functional Contact Assignments (continued)

Out of Reset Condition

17x17

NP

Ball

Power

Group

Ball

Type

Ball Name

Default

Mode

Default

Input/

Value

Function

Output

RGMII2_RD3

B7

NVCC_RGMII2

VDD_SNVS_CAP

NVCC_SD2

GPIO

—

ALT5

—

GPIO5_IO15

GPIO5_IO16

GPIO5_IO17

GPIO5_IO18

GPIO5_IO19

GPIO5_IO20

GPIO5_IO21

GPIO5_IO22

GPIO5_IO23

RTC_XTALI

RTC_XTALO

GPIO6_IO06

GPIO6_IO07

GPIO6_IO08

GPIO6_IO09

GPIO6_IO10

GPIO6_IO11

GPIO7_IO00

Input

—

Keeper

—

RGMII2_RX_CTL

RGMII2_RXC

RGMII2_TD0

RGMII2_TD1

RGMII2_TD2

RGMII2_TD3

RGMII2_TX_CTL

RGMII2_TXC

RTC_XTALI

RTC_XTALO

SD2_CLK

B9

A9

A11

B11

A12

B12

B10

A10

V19

V20

E12

F12

E13

E14

F10

F11

V11

—

GPIO

ALT5

Input

Keeper

SD2_CMD

NVCC_SD2

SD2_DATA0

SD2_DATA1

SD2_DATA2

SD2_DATA3

SD3_CLK

NVCC_SD2

NVCC_LOW

NVCC_HIGH

100 kΩ

pull-down

SD3_CMD

T13

U10

T11

V15

V14

U14

U13

NVCC_LOW

NVCC_HIGH

GPIO

ALT5

GPIO7_IO01

GPIO7_IO02

GPIO7_IO03

GPIO7_IO04

GPIO7_IO05

GPIO7_IO06

GPIO7_IO07

Input

100 kΩ

pull-down

SD3_DATA0

SD3_DATA1

SD3_DATA2

SD3_DATA3

SD3_DATA4

SD3_DATA5

NVCC_LOW

NVCC_HIGH

100 kΩ

pull-down

NVCC_LOW

NVCC_HIGH

100 kΩ

pull-down

NVCC_LOW

NVCC_HIGH

100 kΩ

pull-down

NVCC_LOW

NVCC_HIGH

100 kΩ

pull-down

NVCC_LOW

NVCC_HIGH

100 kΩ

pull-down

NVCC_LOW

NVCC_HIGH

100 kΩ

pull-down

i.MX 6SoloX Applications Processors for Industrial Products, Rev. 4, 11/2018

NXP Semiconductors

163

Package Information and Contact Assignments

Table 113. 17x17 mm NP (No PCIe) Functional Contact Assignments (continued)

Out of Reset Condition

17x17

NP

Ball

Power

Group

Ball

Type

Ball Name

Default

Mode

Default

Input/

Value

Function

Output

SD3_DATA6

V12

U11

NVCC_LOW

NVCC_HIGH

GPIO

ALT5

GPIO7_IO08

Input

100 kΩ

pull-down

SD3_DATA7

NVCC_LOW

NVCC_HIGH

ALT5

GPIO7_IO09

Input

100 kΩ

pull-down

SD4_CLK

W11

W12

Y9

NVCC_SD4

VDD_SNVS_IN

GPIO

ALT5

—

GPIO6_IO12

GPIO6_IO13

GPIO6_IO14

GPIO6_IO15

GPIO6_IO16

GPIO6_IO17

GPIO6_IO18

GPIO6_IO19

GPIO6_IO20

GPIO6_IO21

GPIO6_IO22

Input

Keeper

SD4_CMD

SD4_DATA0

SD4_DATA1

SD4_DATA2

SD4_DATA3

SD4_DATA4

SD4_DATA5

SD4_DATA6

SD4_DATA7

SD4_RESET_B

SNVS_PMIC_ON_REQ

W9

Y13

W13

Y12

Y11

Y10

W10

T12

P16

SNVS_PMIC_ON_REQ Output

100 kΩ

pull-up

SNVS_TAMPER

TEST_MODE

P15

N14

Y5

VDD_SNVS_IN

NVCC_USB_H

GPIO

—

SNVS_TAMPER

TEST_MODE

GPIO7_IO10

GPIO7_IO11

Input

100 kΩ

pull-down

100 kΩ

pull-down

USB_H_DATA

USB_H_STROBE

GPIO

ALT5

100 kΩ

pull-down

W5

100 kΩ

pull-down

USB_OTG1_CHD_B

USB_OTG1_DN

USB_OTG1_DP

USB_OTG2_DN

USB_OTG2_DP

XTALI

W20

W19

Y19

W17

Y17

T19

T20

VDD_USB_CAP

NVCC_PLL

—

USB_OTG1_CHD_B

USB_OTG1_DN

USB_OTG1_DP

USB_OTG2_DN

USB_OTG2_DP

XTALI

—

XTALO

NVCC_PLL

XTALO

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Package Information and Contact Assignments

6.4.4

17x17 mm NP (No PCIe), 0.8 mm Pitch, 20x20 Ball Map

Table 114. 17x17 mm (No PCIe), 0.8 mm Pitch, 20x20 Ball Map

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Table 114. 17x17 mm (No PCIe), 0.8 mm Pitch, 20x20 Ball Map (continued)

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Package Information and Contact Assignments

Table 114. 17x17 mm (No PCIe), 0.8 mm Pitch, 20x20 Ball Map (continued)

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Package Information and Contact Assignments

6.4.5

17x17 mm WP (with PCIe) Supplies Contact Assignments and

Functional Contact Assignments

Table 115 shows supplies contact assignments for the 17x17 mm WP (with PCIe) package.

Table 115. 17x17 mm WP (with PCIe) Supplies Contact Assignments

17x17 WP [with PCIe]

Ball(s) Position(s)

Supply Rail Name

DRAM_VREF

Remark

J3

DDR voltage reference input. Connect to a voltage source that

is 50% of NVCC_DRAM.

DRAM_ZQPAD

GPANAIO

C5

DDR output buffer driver calibration reference voltage input.

Connect DRAM_ZQPAD to an external 240 ohm 1% resistor

to Vss.

U16

Analog output for NXP use only. This output must always be

left unconnected.

NGND_KEL0

NVCC_DRAM

NVCC_DRAM_2P5

NVCC_ENET

NVCC_GPIO

NVCC_HIGH

P13

Connect to Vss

G6, H6, J6, K6, L6, M6, N6, P6

Supply input for the DDR I/O interface

Supply input for the DDR interface

Supply input for the ENET interfaces

Supply input for the GPIO interface

K7

F6

F15

R12

3.3 V Supply input for the dual-voltage I/Os on the SD3

interface

NVCC_JTAG

NVCC_KEY

NVCC_LCD1

NVCC_LOW

R11

G15

H15

V13

Supply input for the JTAG interface

Supply input for the Key Pad Port (KPP) interface

Supply input for the LCD interface

1.8 V Supply input for the dual-voltage I/Os on the SD3

interface

NVCC_NAND

NVCC_PLL

R6

W20

F14

F8

Supply input for the Raw NAND flash memories interface

Supply input for the PLLs

NVCC_QSPI

NVCC_RGMII1

NVCC_RGMII2

NVCC_SD2

Supply input for the QSPI interface

Supply input for the RGMII1 interface

Supply input for the RGMII2 interface

Supply input for the SD2 interface

F9

F13

V10

V5

NVCC_SD4

Supply input for the SD4 interface

NVCC_USB_H

PCIE_REXT

Supply input for the USB HSIC interface

N18

PCIe impedance calibration resistor. Connect PCIE_REXT to

an external 200 ohm 1% resistor to Vss.

PCIE_VP

P18

R18

P17

Supply input for the PCIe PHY

PCIE_VPH

PCIE_VPTX

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Package Information and Contact Assignments

Table 115. 17x17 mm WP (with PCIe) Supplies Contact Assignments (continued)

17x17 WP [with PCIe]

Ball(s) Position(s)

Supply Rail Name

Remark

USB_OTG1_VBUS

USB_OTG2_VBUS

VDD_ARM_CAP

T16

T15

VBUS input for USB_OTG1

VBUS input for USB_OTG2

C16, D16, H10, H11, H12, H13, Supply voltage output from internal LDO_ARM. Requires

J13, K13, L13

H18, J10, J11, J12, K12, L12

V17, V18

external capacitor(s).

VDD_ARM_IN

Supply voltage input for internal LDO_ARM.

VDD_HIGH_CAP

Supply voltage output from internal LDO_2P5. Requires

external capacitor(s).

VDD_HIGH_IN

U17, U18

V16

Supply voltage input to internal LDO_2P5, LDO_1P1 and

LDO_SNVS.

VDD_SNVS_CAP

Supply voltage output from internal LDO_SNVS. Requires

external capacitor(s).

VDD_SNVS_IN

VDD_SOC_CAP

T18

Supply voltage input to the SNVS voltage domain

H8, H9, J8, K8, L8, M8, M13, N8, Supply voltage output from internal LDO_SOC. Requires

N9, N10, N11, N12, V8

external capacitor(s).

VDD_SOC_IN

VDD_USB_CAP

VDDA_ADC_3P3

VSS

C7, C8, J9, K9, L9,

M9, M10, M11, M12

Supply voltage input to internal LDO_SOC and LDO_PCIE

V15

Supply voltage output from internal LDO_USB. Requires

external capacitor(s).

R13

Supply voltage input to the ADC. This supply must be provided

even if the ADC is not used.

A1, A20, C3, C4, C18, D6, D9, D12, Ground

D15, E3, F3, F5, F17, G7, G8, G9,

G10, G11, G12, G13, G14, H3, H7,

H14, J7, J14, J17, K3, K10, K11,

K14, L3, L7, L10, L11, L14, M7,

M14, M17, N3, N7, N13, N19, N20,

P7, P8, P9, P10, P11, P12, R3, R5,

R17, T3, T19, T20, U6, U9, U12,

U15, V3, V4, W16, W18, Y1, Y16,

Y18, Y20

Table 116 shows an alpha-sorted list of functional contact assignments for the 17x17 mm WP (with

PCIe) package.

Table 116. 17x17 WP (with PCIe) Functional Contact Assignments

Out of Reset Condition

17x17

Power

Group

Ball

Type

Ball Name

WP

Ball

Default

Mode

Default

Function

Input/

Output

Value

ADC1_IN0

Y14

VDDA_ADC_3P3

—

ADC1_IN0

ADC1_IN1

Input

—

ADC1_IN1

W14

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Package Information and Contact Assignments

Table 116. 17x17 WP (with PCIe) Functional Contact Assignments (continued)

Out of Reset Condition

17x17

WP

Ball

Power

Group

Ball

Type

Ball Name

Default

Mode

Default

Input/

Value

Function

Output

BOOT_MODE0

BOOT_MODE1

U20

U19

VDD_SNVS_IN

GPIO

—

BOOT_MODE0

Input

100 kΩ

pull-down

—

BOOT_MODE1

Input

100 kΩ

pull-down

CCM_CLK1_N

CCM_CLK1_P

CCM_CLK2

P16

R16

R15

VDD_HIGH_CAP

VDD_SNVS_IN

NVCC_DRAM

—

CCM_CLK1_N

CCM_CLK1_P

CCM_CLK2

—

0

—

CCM_PMIC_STBY_REQ P15

GPIO

DDR

CCM_PMIC_STBY_REQ Output

DRAM_ADDR00

DRAM_ADDR01

DRAM_ADDR02

DRAM_ADDR03

DRAM_ADDR04

DRAM_ADDR05

DRAM_ADDR06

DRAM_ADDR07

DRAM_ADDR08

DRAM_ADDR09

DRAM_ADDR10

DRAM_ADDR11

DRAM_ADDR12

DRAM_ADDR13

L4

U4

K5

G5

M3

G4

T4

F4

M5

L5

DRAM_ADDR00

DRAM_ADDR01

DRAM_ADDR02

DRAM_ADDR03

DRAM_ADDR04

DRAM_ADDR05

DRAM_ADDR06

DRAM_ADDR07

DRAM_ADDR08

DRAM_ADDR09

DRAM_ADDR10

DRAM_ADDR11

DRAM_ADDR12

DRAM_ADDR13

Output

100 kΩ

pull-up

NVCC_DRAM

DDR

—

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

N5

N4

P4

M4

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

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Package Information and Contact Assignments

Table 116. 17x17 WP (with PCIe) Functional Contact Assignments (continued)

Out of Reset Condition

17x17

WP

Ball

Power

Group

Ball

Type

Ball Name

Default

Mode

Default

Input/

Value

Function

Output

DRAM_ADDR14

DRAM_CAS_B

DRAM_CS0_B

DRAM_CS1_B

DRAM_DATA00

DRAM_DATA01

DRAM_DATA02

DRAM_DATA03

DRAM_DATA04

DRAM_DATA05

DRAM_DATA06

DRAM_DATA07

DRAM_DATA08

DRAM_DATA09

DRAM_DATA10

DRAM_DATA11

DRAM_DATA12

DRAM_DATA13

DRAM_DATA14

R4

J4

NVCC_DRAM

DDR

—

DRAM_ADDR14

DRAM_CAS_B

DRAM_CS0_B

DRAM_CS1_B

DRAM_DATA00

DRAM_DATA01

DRAM_DATA02

DRAM_DATA03

DRAM_DATA04

DRAM_DATA05

DRAM_DATA06

DRAM_DATA07

DRAM_DATA08

DRAM_DATA09

DRAM_DATA10

DRAM_DATA11

DRAM_DATA12

DRAM_DATA13

DRAM_DATA14

Output

100 kΩ

pull-up

Output

Input

100 kΩ

pull-up

H4

D3

R1

T2

T1

R2

M1

M2

L2

N1

H1

F2

K2

J2

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

J1

100 kΩ

pull-up

F1

E2

100 kΩ

pull-up

100 kΩ

pull-up

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Package Information and Contact Assignments

Table 116. 17x17 WP (with PCIe) Functional Contact Assignments (continued)

Out of Reset Condition

17x17

WP

Ball

Power

Group

Ball

Type

Ball Name

Default

Mode

Default

Input/

Value

Function

Output

DRAM_DATA15

DRAM_DATA16

DRAM_DATA17

DRAM_DATA18

DRAM_DATA19

DRAM_DATA20

DRAM_DATA21

DRAM_DATA22

DRAM_DATA23

DRAM_DATA24

DRAM_DATA25

DRAM_DATA26

DRAM_DATA27

DRAM_DATA28

DRAM_DATA29

DRAM_DATA30

DRAM_DATA31

DRAM_DQM0

E1

V1

W4

Y4

U2

W3

Y2

U1

V2

A2

D1

C1

D2

C2

B3

B4

A4

N2

G2

NVCC_DRAM

DDR

—

DRAM_DATA15

DRAM_DATA16

DRAM_DATA17

DRAM_DATA18

DRAM_DATA19

DRAM_DATA20

DRAM_DATA21

DRAM_DATA22

DRAM_DATA23

DRAM_DATA24

DRAM_DATA25

DRAM_DATA26

DRAM_DATA27

DRAM_DATA28

DRAM_DATA29

DRAM_DATA30

DRAM_DATA31

DRAM_DQM0

Input

100 kΩ

pull-up

Input

Output

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

DRAM_DQM1

100 kΩ

pull-up

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Package Information and Contact Assignments

Table 116. 17x17 WP (with PCIe) Functional Contact Assignments (continued)

Out of Reset Condition

17x17

WP

Ball

Power

Group

Ball

Type

Ball Name

Default

Mode

Default

Input/

Value

Function

Output

DRAM_DQM2

Y3

A3

U3

H5

D4

G3

P3

K4

P5

E4

NVCC_DRAM

DDR

—

DRAM_DQM2

DRAM_DQM3

DRAM_ODT0

Output

100 kΩ

pull-up

DRAM_DQM3

DRAM_ODT0

Output

100 kΩ

pull-up

100 kΩ

pull-down

DRAM_RAS_B

DRAM_RESET

DRAM_SDBA0

DRAM_SDBA1

DRAM_SDBA2

DRAM_SDCKE0

DRAM_SDCKE1

DRAM_RAS_B

DRAM_RESET

DRAM_SDBA0

DRAM_SDBA1

DRAM_SDBA2

DRAM_SDCKE0

DRAM_SDCKE1

100 kΩ

pull-up

100 kΩ

pull-down

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-up

100 kΩ

pull-down

100 kΩ

pull-down

DRAM_SDCLK0_N

DRAM_SDCLK0_P

DRAM_SDQS0_N

DRAM_SDQS0_P

DRAM_SDQS1_N

DRAM_SDQS1_P

DRAM_SDQS2_N

DRAM_SDQS2_P

DRAM_SDQS3_N

DRAM_SDQS3_P

DRAM_SDWE_B

L1

K1

P2

P1

H2

G1

W1

W2

B2

B1

J5

NVCC_DRAM

DDRCLK

DDR

—

DRAM_SDCLK0_N

DRAM_SDCLK0_P

DRAM_SDQS0_N

DRAM_SDQS0_P

DRAM_SDQS1_N

DRAM_SDQS1_P

DRAM_SDQS2_N

DRAM_SDQS2_P

DRAM_SDQS3_N

DRAM_SDQS3_P

DRAM_SDWE_B

—

Output

—

Low

—

Input

—

Input

—

Input

—

Input

Output

—

100 kΩ

pull-up

ENET1_COL

ENET1_CRS

ENET1_MDC

B5

C6

B6

NVCC_ENET

GPIO

ALT5

GPIO2_IO00

GPIO2_IO01

GPIO2_IO02

Input

Keeper

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Package Information and Contact Assignments

Table 116. 17x17 WP (with PCIe) Functional Contact Assignments (continued)

Out of Reset Condition

17x17

WP

Ball

Power

Group

Ball

Type

Ball Name

Default

Mode

Default

Input/

Value

Function

Output

ENET1_MDIO

A6

A5

NVCC_ENET

NVCC_GPIO

NVCC_JTAG

GPIO

ALT5

—

GPIO2_IO03

GPIO2_IO04

GPIO2_IO05

GPIO2_IO06

GPIO2_IO07

GPIO2_IO08

GPIO2_IO09

GPIO1_IO00

GPIO1_IO01

GPIO1_IO02

GPIO1_IO03

GPIO1_IO04

GPIO1_IO05

GPIO1_IO06

GPIO1_IO07

GPIO1_IO08

GPIO1_IO09

GPIO1_IO10

GPIO1_IO11

GPIO1_IO12

GPIO1_IO13

JTAG_MOD

Input

Keeper

ENET1_RX_CLK

ENET1_TX_CLK

ENET2_COL

ENET2_CRS

ENET2_RX_CLK

ENET2_TX_CLK

GPIO1_IO00

GPIO1_IO01

GPIO1_IO02

GPIO1_IO03

GPIO1_IO04

GPIO1_IO05

GPIO1_IO06

GPIO1_IO07

GPIO1_IO08

GPIO1_IO09

GPIO1_IO10

GPIO1_IO11

GPIO1_IO12

GPIO1_IO13

JTAG_MOD

F7

E7

E6

E5

D5

C19

D19

C20

D20

A18

B18

D18

A17

B17

A19

B19

B20

B16

A16

R7

100 kΩ

pull-up

JTAG_TCK

JTAG_TDI

R9

NVCC_JTAG

GPIO

—

JTAG_TCK

JTAG_TDI

Input

47 kΩ

pull-up

R10

47 kΩ

pull-up

JTAG_TDO

JTAG_TMS

R8

NVCC_JTAG

GPIO

—

JTAG_TDO

JTAG_TMS

Output

Input

Keeper

T10

47 kΩ

pull-up

JTAG_TRST_B

KEY_COL0

T9

NVCC_JTAG

NVCC_KEY

GPIO

—

JTAG_TRST_B

GPIO2_IO10

Input

47 kΩ

pull-up

G20

ALT5

Keeper

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Table 116. 17x17 WP (with PCIe) Functional Contact Assignments (continued)

Out of Reset Condition

17x17

WP

Ball

Power

Group

Ball

Type

Ball Name

Default

Mode

Default

Input/

Value

Function

Output

KEY_COL1

F20

G18

E20

E19

F16

E18

F18

F19

G19

L17

M20

L18

M19

M18

N17

M16

M15

L20

K18

L16

L19

L15

K16

K15

K17

H16

H20

K19

K20

J20

NVCC_KEY

NVCC_LCD1

GPIO

ALT5

GPIO2_IO11

GPIO2_IO12

GPIO2_IO13

GPIO2_IO14

GPIO2_IO15

GPIO2_IO16

GPIO2_IO17

GPIO2_IO18

GPIO2_IO19

GPIO3_IO00

GPIO3_IO01

GPIO3_IO02

GPIO3_IO03

GPIO3_IO04

GPIO3_IO05

GPIO3_IO06

GPIO3_IO07

GPIO3_IO08

GPIO3_IO09

GPIO3_IO10

GPIO3_IO11

GPIO3_IO12

GPIO3_IO13

GPIO3_IO14

GPIO3_IO15

GPIO3_IO16

GPIO3_IO17

GPIO3_IO18

GPIO3_IO19

GPIO3_IO20

GPIO3_IO21

Input

Keeper

KEY_COL2

KEY_COL3

KEY_COL4

KEY_ROW0

KEY_ROW1

KEY_ROW2

KEY_ROW3

KEY_ROW4

LCD1_CLK

LCD1_DATA00

LCD1_DATA01

LCD1_DATA02

LCD1_DATA03

LCD1_DATA04

LCD1_DATA05

LCD1_DATA06

LCD1_DATA07

LCD1_DATA08

LCD1_DATA09

LCD1_DATA10

LCD1_DATA11

LCD1_DATA12

LCD1_DATA13

LCD1_DATA14

LCD1_DATA15

LCD1_DATA16

LCD1_DATA17

LCD1_DATA18

LCD1_DATA19

LCD1_DATA20

H17

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Table 116. 17x17 WP (with PCIe) Functional Contact Assignments (continued)

Out of Reset Condition

17x17

WP

Ball

Power

Group

Ball

Type

Ball Name

Default

Mode

Default

Input/

Value

Function

Output

LCD1_DATA21

G17

H19

G16

J19

J16

J18

J15

W6

U7

NVCC_LCD1

NVCC_NAND

VDD_SNVS_IN

GPIO

ALT5

—

GPIO3_IO22

GPIO3_IO23

GPIO3_IO24

GPIO3_IO25

GPIO3_IO26

GPIO3_IO27

GPIO3_IO28

GPIO4_IO00

GPIO4_IO01

GPIO4_IO02

GPIO4_IO03

GPIO4_IO04

GPIO4_IO05

GPIO4_IO06

GPIO4_IO07

GPIO4_IO08

GPIO4_IO09

GPIO4_IO10

GPIO4_IO11

GPIO4_IO12

GPIO4_IO13

GPIO4_IO14

GPIO4_IO15

ONOFF

Input

Keeper

LCD1_DATA22

LCD1_DATA23

LCD1_ENABLE

LCD1_HSYNC

LCD1_RESET

LCD1_VSYNC

NAND_ALE

NAND_CE0_B

NAND_CE1_B

NAND_CLE

V9

T8

NAND_DATA00

NAND_DATA01

NAND_DATA02

NAND_DATA03

NAND_DATA04

NAND_DATA05

NAND_DATA06

NAND_DATA07

NAND_RE_B

NAND_READY_B

NAND_WE_B

NAND_WP_B

ONOFF

V6

W8

Y7

U5

W7

T5

Y8

T6

U8

Y6

T7

V7

N15

100 kΩ

pull-up

PCIE_RX_N

PCIE_RX_P

PCIE_TX_N

PCIE_TX_P

POR_B

P19

P20

R19

R20

P14

PCIE_VPH

—

PCIE_RX_N

PCIE_RX_P

PCIE_TX_N

PCIE_TX_P

POR_B

—

PCIE_VPH

—

PCIE_VPH

—

VDD_SNVS_IN

GPIO

Input

100 kΩ

pull-up

QSPI1A_DATA0

E15

NVCC_QSPI

GPIO

ALT5

GPIO4_IO16

Input

Keeper

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Package Information and Contact Assignments

Table 116. 17x17 WP (with PCIe) Functional Contact Assignments (continued)

Out of Reset Condition

17x17

WP

Ball

Power

Group

Ball

Type

Ball Name

Default

Mode

Default

Input/

Value

Function

Output

QSPI1A_DATA1

QSPI1A_DATA2

QSPI1A_DATA3

QSPI1A_DQS

QSPI1A_SCLK

QSPI1A_SS0_B

QSPI1A_SS1_B

QSPI1B_DATA0

QSPI1B_DATA1

QSPI1B_DATA2

QSPI1B_DATA3

QSPI1B_DQS

QSPI1B_SCLK

QSPI1B_SS0_B

QSPI1B_SS1_B

RGMII1_RD0

C15

D14

E16

A13

D17

C17

E17

B14

A14

D13

C13

B13

B15

C14

A15

D8

NVCC_QSPI

NVCC_RGMII1

NVCC_RGMII2

GPIO

ALT5

GPIO4_IO17

GPIO4_IO18

GPIO4_IO19

GPIO4_IO20

GPIO4_IO21

GPIO4_IO22

GPIO4_IO23

GPIO4_IO24

GPIO4_IO25

GPIO4_IO26

GPIO4_IO27

GPIO4_IO28

GPIO4_IO29

GPIO4_IO30

GPIO4_IO31

GPIO5_IO00

GPIO5_IO01

GPIO5_IO02

GPIO5_IO03

GPIO5_IO04

GPIO5_IO05

GPIO5_IO06

GPIO5_IO07

GPIO5_IO08

GPIO5_IO09

GPIO5_IO10

GPIO5_IO11

GPIO5_IO12

GPIO5_IO13

GPIO5_IO14

GPIO5_IO15

Input

Keeper

RGMII1_RD1

C9

RGMII1_RD2

D7

RGMII1_RD3

E8

RGMII1_RX_CTL

RGMII1_RXC

RGMII1_TD0

C10

E9

D11

C12

E11

D10

E10

C11

A8

RGMII1_TD1

RGMII1_TD2

RGMII1_TD3

RGMII1_TX_CTL

RGMII1_TXC

RGMII2_RD0

RGMII2_RD1

B8

RGMII2_RD2

A7

RGMII2_RD3

B7

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Table 116. 17x17 WP (with PCIe) Functional Contact Assignments (continued)

Out of Reset Condition

17x17

WP

Ball

Power

Group

Ball

Type

Ball Name

Default

Mode

Default

Input/

Value

Function

Output

RGMII2_RX_CTL

RGMII2_RXC

RGMII2_TD0

RGMII2_TD1

RGMII2_TD2

RGMII2_TD3

RGMII2_TX_CTL

RGMII2_TXC

RTC_XTALI

RTC_XTALO

SD2_CLK

B9

A9

NVCC_RGMII2

VDD_SNVS_CAP

NVCC_SD2

GPIO

—

ALT5

—

GPIO5_IO16

GPIO5_IO17

GPIO5_IO18

GPIO5_IO19

GPIO5_IO20

GPIO5_IO21

GPIO5_IO22

GPIO5_IO23

RTC_XTALI

RTC_XTALO

GPIO6_IO06

GPIO6_IO07

GPIO6_IO08

GPIO6_IO09

GPIO6_IO10

GPIO6_IO11

GPIO7_IO00

Input

—

Keeper

—

A11

B11

A12

B12

B10

A10

W19

Y19

E12

F12

E13

E14

F10

F11

V11

—

GPIO

ALT5

Input

Keeper

SD2_CMD

NVCC_SD2

SD2_DATA0

SD2_DATA1

SD2_DATA2

SD2_DATA3

SD3_CLK

NVCC_SD2

NVCC_LOW

NVCC_HIGH

100 kΩ

pull-down

SD3_CMD

T13

U10

T11

U14

V14

T14

U13

V12

NVCC_LOW

NVCC_HIGH

GPIO

ALT5

GPIO7_IO01

GPIO7_IO02

GPIO7_IO03

GPIO7_IO04

GPIO7_IO05

GPIO7_IO06

GPIO7_IO07

GPIO7_IO08

Input

100 kΩ

pull-down

SD3_DATA0

SD3_DATA1

SD3_DATA2

SD3_DATA3

SD3_DATA4

SD3_DATA5

SD3_DATA6

NVCC_LOW

NVCC_HIGH

100 kΩ

pull-down

NVCC_LOW

NVCC_HIGH

100 kΩ

pull-down

NVCC_LOW

NVCC_HIGH

100 kΩ

pull-down

NVCC_LOW

NVCC_HIGH

100 kΩ

pull-down

NVCC_LOW

NVCC_HIGH

100 kΩ

pull-down

NVCC_LOW

NVCC_HIGH

100 kΩ

pull-down

NVCC_LOW

NVCC_HIGH

100 kΩ

pull-down

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Package Information and Contact Assignments

Table 116. 17x17 WP (with PCIe) Functional Contact Assignments (continued)

Out of Reset Condition

17x17

WP

Ball

Power

Group

Ball

Type

Ball Name

Default

Mode

Default

Input/

Value

Function

Output

SD3_DATA7

U11

NVCC_LOW

NVCC_HIGH

GPIO

ALT5

GPIO7_IO09

Input

100 kΩ

pull-down

SD4_CLK

W11

W12

Y9

NVCC_SD4

VDD_SNVS_IN

GPIO

ALT5

—

GPIO6_IO12

GPIO6_IO13

GPIO6_IO14

GPIO6_IO15

GPIO6_IO16

GPIO6_IO17

GPIO6_IO18

GPIO6_IO19

GPIO6_IO20

GPIO6_IO21

GPIO6_IO22

Input

Keeper

SD4_CMD

SD4_DATA0

SD4_DATA1

SD4_DATA2

SD4_DATA3

SD4_DATA4

SD4_DATA5

SD4_DATA6

SD4_DATA7

SD4_RESET_B

SNVS_PMIC_ON_REQ

W9

Y13

W13

Y12

Y11

Y10

W10

T12

N16

SNVS_PMIC_ON_REQ Output

100 kΩ

pull-up

SNVS_TAMPER

TEST_MODE

R14

N14

Y5

VDD_SNVS_IN

NVCC_USB_H

GPIO

—

SNVS_TAMPER

TEST_MODE

GPIO7_IO10

GPIO7_IO11

Input

100 kΩ

pull-down

100 kΩ

pull-down

USB_H_DATA

USB_H_STROBE

GPIO

ALT5

100 kΩ

pull-down

W5

100 kΩ

pull-down

USB_OTG1_CHD_B

USB_OTG1_DN

USB_OTG1_DP

USB_OTG2_DN

USB_OTG2_DP

XTALI

T17

W17

Y17

W15

Y15

V19

V20

VDD_USB_CAP

NVCC_PLL

—

USB_OTG1_CHD_B

USB_OTG1_DN

USB_OTG1_DP

USB_OTG2_DN

USB_OTG2_DP

XTALI

—

XTALO

NVCC_PLL

XTALO

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Package Information and Contact Assignments

6.4.6

17x17 mm WP (with PCIe), 0.8 mm Pitch, 20x20 Ball Map

Table 117. 17x17 mm WP (with PCIe), 0.8 mm Pitch, 20x20 Ball Map

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Package Information and Contact Assignments

Table 117. 17x17 mm WP (with PCIe), 0.8 mm Pitch, 20x20 Ball Map (continued)

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Package Information and Contact Assignments

Table 117. 17x17 mm WP (with PCIe), 0.8 mm Pitch, 20x20 Ball Map (continued)

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Package Information and Contact Assignments

6.5

14x14 mm Package Information

6.5.1

14x14 mm, 0.65 mm Pitch, 20x20 Ball Matrix

Figure 87 shows the top, bottom, and side views of the 14×14 mm BGA package.

Figure 87. 14x14 mm BGA Package—Top, Bottom, and Side Views

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Package Information and Contact Assignments

Figure 88. 14x14 mm BGA Package Notes

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Package Information and Contact Assignments

6.5.2

14x14 mm Supplies Contact Assignments and Functional Contact

Assignments

Table 118 shows supplies contact assignments for the 14x14 mm package and Table 119 shows the

functional contact assignments.

Table 118. 14x14 mm Supplies Contact Assignments

14x14 mm

Ball Position(s)

Supply Rail Name

Comments

ADC_VREFH

ADC_VREFL

DRAM_VREF

Y15

V14

K4

ADC high reference voltage

ADC low reference voltage

DDR voltage reference input. Connect to a voltage source that is 50% of

NVCC_DRAM.

DRAM_ZQPAD

H2

DDR output buffer driver calibration reference voltage input. Connect

DRAM_ZQPAD to an external 240 ohm 1% resistor to Vss.

GPANAIO

P16

Analog output for NXP use only. This output must always be left unconnected.

NVCC_DRAM

G6, H6, J6, K6, L6, Supply input for the DDR I/O interface

M6, N6, P6

NVCC_DRAM_2P5

NVCC_ENET

NVCC_GPIO

NVCC_HIGH

NVCC_JTAG

NVCC_KEY

K7

F6

Supply input for the DDR interface

Supply input for the ENET interfaces

Supply input for the GPIO interface

F15

R12

T9

3.3 V Supply input for the dual-voltage I/Os on the SD3 interface

Supply input for the JTAG interface

G15

H15

V13

R6

Supply input for the Key Pad Port (KPP) interface

Supply input for the LCD interface

NVCC_CSI_LCD1

NVCC_LOW

1.8 V Supply input for the dual-voltage I/Os on the SD3 interface

Supply input for the Raw NAND flash memories interface

Supply input for the PLLs

NVCC_NAND

NVCC_PLL

U18

F14

F8

NVCC_QSPI

Supply input for the QSPI interface

NVCC_RGMII1

NVCC_RGMII2

NVCC_SD1_SD2

NVCC_SD4

Supply input for the RGMII1 interface

Supply input for the RGMII2 interface

Supply input for the SD2 interface

E11

F13

T12

V5

Supply input for the SD4 interface

NVCC_USB_H

NGND_KEL0

PCIE_VP_CAP

Supply input for the USB HSIC interface

Ground

T16

L18

PCIe LDO output. Although this package does not support PCIe, this output

requires a 4.7uF capacitor to ground unless the PCIE LDO is disabled.

USB_OTG1_VBUS

USB_OTG2_VBUS

W20

U17

VBUS input for USB_OTG1

VBUS input for USB_OTG2

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Package Information and Contact Assignments

Table 118. 14x14 mm Supplies Contact Assignments (continued)

14x14 mm

Ball Position(s)

Supply Rail Name

Comments

VDD_ARM_CAP

C16, D16, H10, Supply voltage output from internal LDO_ARM. Requires external capacitor(s).

H11, H12, H13,

J13, K13, L13

VDD_ARM_IN

H18, J10, J11,

J12, K12, L12

Supply voltage input for internal LDO_ARM.

VDD_HIGH_CAP

VDD_HIGH_IN

VDD_SNVS_CAP

VDD_SNVS_IN

VDD_SOC_CAP

N17, N18

P17, P18

T18

Supply voltage output from internal LDO_2P5. Requires external capacitor(s).

Supply voltage input to internal LDO_2P5, LDO_1P1 and LDO_SNVS.

Supply voltage output from internal LDO_SNVS. Requires external capacitor(s).

Supply voltage input to the SNVS voltage domain

R18

H8, H9, J8, K8, L8, Supply voltage output from internal LDO_SOC. Requires external capacitor(s).

M8, M13, N8, N9,

N10, N11, N12, V9

VDD_SOC_IN

D7, D8, J9, K9, L9, Supply voltage input to internal LDO_SOC and LDO_PCIE

M9, M10, M11,

M12

VDD_USB_CAP

VDDA_ADC_3P3

V17

R13

Supply voltage output from internal LDO_USB. Requires external capacitor(s).

Supply voltage input to the ADC. This supply must be provided even if the ADC is

not used.

VSS

A1, A20, C3, C4, Ground

C18, D6, D9, D12,

D15, E3, F3, F5,

F17, G7, G8, G9,

G10, G11, G12,

G13, G14, H3, H7,

H14, J7, J14, J17,

K3, K10, K11,

K14, L3, L7, L10,

L11, L14, M7,

M14, M17, N3, N7,

N13, P7, P8, P9,

P10, P11, P12,

R3, R5, R17, R19,

R20, T3, U6, U9,

U12, U15, U19,

U20, V3, V4, V18,

W18, Y1, Y18,

Y20

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Package Information and Contact Assignments

Table 119. 14 x 14 Functional Contact Assignments

Out of Reset Condition

14x14

Ball

Power

Group

Ball

Type

Ball Name

Default

Mode

Default

Function

Input/

Output

Value

ADC1_IN0

ADC1_IN1

ADC1_IN2

ADC1_IN3

ADC2_IN0

ADC2_IN1

ADC2_IN2

ADC2_IN3

BOOT_MODE0

N14

T15

W14

P13

W15

R14

N15

R15

Y16

VDDA_ADC_3P3

VDD_SNVS_IN

—

ADC1_IN0

ADC1_IN1

ADC1_IN2

ADC1_IN3

ADC2_IN0

ADC2_IN1

ADC2_IN2

ADC2_IN3

BOOT_MODE0

Input

—

GPIO

100 kΩ

pull-down

BOOT_MODE1

W16

VDD_SNVS_IN

GPIO

—

BOOT_MODE1

Input

100 kΩ

pull-down

CCM_CLK1_N

CCM_CLK1_P

P20

P19

V16

N16

VDD_HIGH_CAP

VDD_SNVS_IN

—

CCM_CLK1_N

CCM_CLK1_P

CCM_CLK2

—

0

CCM_CLK2

—

CCM_PMIC_STBY_REQ

GPIO

CCM_PMIC_STB Output

Y_REQ

DRAM_ADDR00

DRAM_ADDR01

DRAM_ADDR02

DRAM_ADDR03

DRAM_ADDR04

DRAM_ADDR05

DRAM_ADDR06

DRAM_ADDR07

DRAM_ADDR08

DRAM_ADDR09

DRAM_ADDR10

DRAM_ADDR11

DRAM_ADDR12

DRAM_ADDR13

DRAM_ADDR14

N5

P5

M4

K5

H5

F4

N4

G5

J4

NVCC_DRAM

DDR

—

DRAM_ADDR00 Output 100 kΩ pull-up

DRAM_ADDR01 Output 100 kΩ pull-up

DRAM_ADDR02 Output 100 kΩ pull-up

DRAM_ADDR03 Output 100 kΩ pull-up

DRAM_ADDR04 Output 100 kΩ pull-up

DRAM_ADDR05 Output 100 kΩ pull-up

DRAM_ADDR06 Output 100 kΩ pull-up

DRAM_ADDR07 Output 100 kΩ pull-up

DRAM_ADDR08 Output 100 kΩ pull-up

DRAM_ADDR09 Output 100 kΩ pull-up

DRAM_ADDR10 Output 100 kΩ pull-up

DRAM_ADDR11 Output 100 kΩ pull-up

DRAM_ADDR12 Output 100 kΩ pull-up

DRAM_ADDR13 Output 100 kΩ pull-up

DRAM_ADDR14 Output 100 kΩ pull-up

L2

H4

M3

M5

J3

R1

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Package Information and Contact Assignments

Table 119. 14 x 14 Functional Contact Assignments (continued)

Out of Reset Condition

14x14

Ball

Power

Group

Ball

Type

Ball Name

Default

Mode

Default

Function

Input/

Output

Value

DRAM_CAS_B

DRAM_CS0_B

DRAM_CS1_B

DRAM_DATA00

DRAM_DATA01

DRAM_DATA02

DRAM_DATA03

DRAM_DATA04

DRAM_DATA05

DRAM_DATA06

DRAM_DATA07

DRAM_DATA08

DRAM_DATA09

DRAM_DATA10

DRAM_DATA11

DRAM_DATA12

DRAM_DATA13

DRAM_DATA14

DRAM_DATA15

DRAM_DATA16

DRAM_DATA17

DRAM_DATA18

DRAM_DATA19

DRAM_DATA20

DRAM_DATA21

DRAM_DATA22

DRAM_DATA23

DRAM_DATA24

DRAM_DATA25

DRAM_DATA26

DRAM_DATA27

N2

L4

NVCC_DRAM

DDR

—

DRAM_CAS_B

DRAM_CS0_B

DRAM_CS1_B

DRAM_DATA00

DRAM_DATA01

DRAM_DATA02

DRAM_DATA03

DRAM_DATA04

DRAM_DATA05

DRAM_DATA06

DRAM_DATA07

DRAM_DATA08

DRAM_DATA09

DRAM_DATA10

DRAM_DATA11

DRAM_DATA12

DRAM_DATA13

DRAM_DATA14

DRAM_DATA15

DRAM_DATA16

DRAM_DATA17

DRAM_DATA18

DRAM_DATA19

DRAM_DATA20

DRAM_DATA21

DRAM_DATA22

DRAM_DATA23

DRAM_DATA24

DRAM_DATA25

DRAM_DATA26

DRAM_DATA27

Output 100 kΩ pull-up

K2

T2

U2

U1

R2

U3

R4

P3

P4

F1

F2

G3

E2

E4

D1

E1

D2

Y4

W4

Y3

U4

W3

Y2

T4

W2

D3

B3

A3

C2

Input

100 kΩ pull-up

100 kΩpull-up

100 kΩ pull-up

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Package Information and Contact Assignments

Table 119. 14 x 14 Functional Contact Assignments (continued)

Out of Reset Condition

14x14

Ball

Power

Group

Ball

Type

Ball Name

Default

Mode

Default

Function

Input/

Output

Value

DRAM_DATA28

DRAM_DATA29

DRAM_DATA30

DRAM_DATA31

DRAM_DQM0

DRAM_DQM1

DRAM_DQM2

DRAM_DQM3

DRAM_ODT0

A2

C5

B4

A4

N1

G2

W1

C1

T1

NVCC_DRAM

DDR

—

DRAM_DATA28

DRAM_DATA29

DRAM_DATA30

DRAM_DATA31

DRAM_DQM0

DRAM_DQM1

DRAM_DQM2

DRAM_DQM3

DRAM_ODT0

Input

100 kΩ pull-up

Output 100 kΩ pull-up

Output

100 kΩ

pull-down

DRAM_RAS_B

DRAM_RESET

J1

NVCC_DRAM

DDR

—

DRAM_RAS_B

DRAM_RESET

Output 100 kΩ pull-up

D4

Output

100 kΩ

pull-down

DRAM_SDBA0

DRAM_SDBA1

DRAM_SDBA2

DRAM_SDCKE0

G4

M2

J2

NVCC_DRAM

DDR

—

DRAM_SDBA0

DRAM_SDBA1

DRAM_SDBA2

Output 100 kΩ pull-up

L5

DRAM_SDCKE0 Output

100 kΩ

pull-down

DRAM_SDCKE1

DRAM_SDCLK0_N

DRAM_SDCLK0_P

DRAM_SDQS0_N

J5

L1

K1

NVCC_DRAM

DDR

—

DRAM_SDCKE1 Output

100 kΩ

pull-down

DDRCLK

DRAM_SDCLK0_

N

—

DRAM_SDCLK0_ Output

P

Low

—

DRAM_SDQS0_N

P2

P1

H1

NVCC_DRAM

DDRCLK

DRAM_SDQS0_P

DRAM_SDQS1_N

—

DRAM_SDQS0_P Input

—

DRAM_SDQS1_

N

—

DRAM_SDQS1_P

DRAM_SDQS2_N

G1

V2

NVCC_DRAM

DDRCLK

—

DRAM_SDQS1_P Input

—

DRAM_SDQS2_

N

—

DRAM_SDQS2_P

DRAM_SDQS3_N

V1

B1

NVCC_DRAM

DDRCLK

—

DRAM_SDQS2_P Input

—

DRAM_SDQS3_

N

—

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Package Information and Contact Assignments

Table 119. 14 x 14 Functional Contact Assignments (continued)

Out of Reset Condition

14x14

Ball

Power

Group

Ball

Type

Ball Name

Default

Mode

Default

Function

Input/

Output

Value

DRAM_SDQS3_P

DRAM_SDWE_B

ENET1_COL

ENET1_CRS

ENET1_MDC

ENET1_MDIO

ENET1_RX_CLK

ENET1_TX_CLK

ENET2_COL

ENET2_CRS

ENET2_RX_CLK

ENET2_TX_CLK

GPIO1_IO00

GPIO1_IO01

GPIO1_IO02

GPIO1_IO03

GPIO1_IO04

GPIO1_IO05

GPIO1_IO06

GPIO1_IO07

GPIO1_IO08

GPIO1_IO09

GPIO1_IO10

GPIO1_IO11

GPIO1_IO12

GPIO1_IO13

JTAG_MOD

B2

M1

NVCC_DRAM

NVCC_ENET

NVCC_GPIO

NVCC_JTAG

DDRCLK

DDR

—

DRAM_SDQS3_P Input

—

DRAM_SDWE_B Output 100 kΩ pull-up

B5

GPIO

ALT5

—

GPIO2_IO00

GPIO2_IO01

GPIO2_IO02

GPIO2_IO03

GPIO2_IO04

GPIO2_IO05

GPIO2_IO06

GPIO2_IO07

GPIO2_IO08

GPIO2_IO09

GPIO1_IO00

GPIO1_IO01

GPIO1_IO02

GPIO1_IO03

GPIO1_IO04

GPIO1_IO05

GPIO1_IO06

GPIO1_IO07

GPIO1_IO08

GPIO1_IO09

GPIO1_IO10

GPIO1_IO11

GPIO1_IO12

GPIO1_IO13

JTAG_MOD

JTAG_TCK

Input

Output

Input

Keeper

C6

B6

Keeper

A6

Keeper

A5

Keeper

F7

Keeper

E7

Keeper

E6

Keeper

E5

Keeper

D5

Keeper

B20

D19

C19

D20

E16

B18

D18

A17

E17

A19

B19

C20

D17

A16

R8

Keeper

100 kΩ pull-up

47 kΩ pull-up

Keeper

JTAG_TCK

R9

—

JTAG_TDI

R10

Y9

—

JTAG_TDI

JTAG_TDO

—

JTAG_TDO

JTAG_TMS

W9

—

47 kΩ pull-up

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Package Information and Contact Assignments

Table 119. 14 x 14 Functional Contact Assignments (continued)

Out of Reset Condition

14x14

Ball

Power

Group

Ball

Type

Ball Name

Default

Mode

Default

Function

Input/

Output

Value

JTAG_TRST_B

KEY_COL0

V8

NVCC_JTAG

NVCC_KEY

NVCC_LCD1

GPIO

—

JTAG_TRST_B

GPIO2_IO10

GPIO2_IO11

GPIO2_IO12

GPIO2_IO13

GPIO2_IO14

GPIO2_IO15

GPIO2_IO16

GPIO2_IO17

GPIO2_IO18

GPIO2_IO19

GPIO3_IO00

GPIO3_IO01

GPIO3_IO02

GPIO3_IO03

GPIO3_IO04

GPIO3_IO05

GPIO3_IO06

GPIO3_IO07

GPIO3_IO08

GPIO3_IO09

GPIO3_IO10

GPIO3_IO11

GPIO3_IO12

GPIO3_IO13

GPIO3_IO14

GPIO3_IO15

GPIO3_IO16

GPIO3_IO17

GPIO3_IO18

GPIO3_IO19

Input

47 kΩ pull-up

Keeper

F18

F19

G17

E20

E19

F16

E18

F20

G20

H19

L19

M19

L17

M18

N20

N19

M15

M16

J19

ALT5

KEY_COL1

KEY_COL2

KEY_COL3

KEY_COL4

KEY_ROW0

KEY_ROW1

KEY_ROW2

KEY_ROW3

KEY_ROW4

LCD1_CLK

LCD1_DATA00

LCD1_DATA01

LCD1_DATA02

LCD1_DATA03

LCD1_DATA04

LCD1_DATA05

LCD1_DATA06

LCD1_DATA07

LCD1_DATA08

LCD1_DATA09

LCD1_DATA10

LCD1_DATA11

LCD1_DATA12

LCD1_DATA13

LCD1_DATA14

LCD1_DATA15

LCD1_DATA16

LCD1_DATA17

LCD1_DATA18

K18

L15

K19

L16

K15

K16

K17

H16

H20

M20

L20

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Table 119. 14 x 14 Functional Contact Assignments (continued)

Out of Reset Condition

14x14

Ball

Power

Group

Ball

Type

Ball Name

Default

Mode

Default

Function

Input/

Output

Value

LCD1_DATA19

LCD1_DATA20

LCD1_DATA21

LCD1_DATA22

LCD1_DATA23

LCD1_ENABLE

LCD1_HSYNC

LCD1_RESET

LCD1_VSYNC

NAND_ALE

J20

H17

G18

G19

G16

K20

J15

J18

J16

W6

U7

NVCC_LCD1

NVCC_NAND

VDD_SNVS_IN

NVCC_QSPI

GPIO

ALT5

—

GPIO3_IO20

GPIO3_IO21

GPIO3_IO22

GPIO3_IO23

GPIO3_IO24

GPIO3_IO25

GPIO3_IO26

GPIO3_IO27

GPIO3_IO28

GPIO4_IO00

GPIO4_IO01

GPIO4_IO02

GPIO4_IO03

GPIO4_IO04

GPIO4_IO05

GPIO4_IO06

GPIO4_IO07

GPIO4_IO08

GPIO4_IO09

GPIO4_IO10

GPIO4_IO11

GPIO4_IO12

GPIO4_IO13

GPIO4_IO14

GPIO4_IO15

ONOFF

Input

Keeper

100 kΩ pull-up

Keeper

NAND_CE0_B

NAND_CE1_B

NAND_CLE

T8

R7

NAND_DATA00

NAND_DATA01

NAND_DATA02

NAND_DATA03

NAND_DATA04

NAND_DATA05

NAND_DATA06

NAND_DATA07

NAND_RE_B

V6

W8

Y7

U5

W7

T5

Y8

T6

U8

NAND_READY_B

NAND_WE_B

NAND_WP_B

ONOFF

Y6

T7

V7

U16

R16

E15

C15

D14

A18

POR_B

—

POR_B

QSPI1A_DATA0

QSPI1A_DATA1

QSPI1A_DATA2

QSPI1A_DATA3

ALT5

GPIO4_IO16

GPIO4_IO17

GPIO4_IO18

GPIO4_IO19

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Table 119. 14 x 14 Functional Contact Assignments (continued)

Out of Reset Condition

14x14

Ball

Power

Group

Ball

Type

Ball Name

Default

Mode

Default

Function

Input/

Output

Value

QSPI1A_DQS

QSPI1A_SCLK

QSPI1A_SS0_B

QSPI1A_SS1_B

QSPI1B_DATA0

QSPI1B_DATA1

QSPI1B_DATA2

QSPI1B_DATA3

QSPI1B_DQS

QSPI1B_SCLK

QSPI1B_SS0_B

QSPI1B_SS1_B

RGMII1_RD0

A13

B16

C17

B17

A15

A14

C13

D13

B13

B14

C14

B15

E8

NVCC_QSPI

GPIO

ALT5

GPIO4_IO20

GPIO4_IO21

GPIO4_IO22

GPIO4_IO23

GPIO4_IO24

GPIO4_IO25

GPIO4_IO26

GPIO4_IO27

GPIO4_IO28

GPIO4_IO29

GPIO4_IO30

GPIO4_IO31

GPIO5_IO00

GPIO5_IO01

GPIO5_IO02

GPIO5_IO03

GPIO5_IO04

GPIO5_IO05

GPIO5_IO06

GPIO5_IO07

GPIO5_IO08

GPIO5_IO09

GPIO5_IO10

GPIO5_IO11

GPIO5_IO12

GPIO5_IO13

GPIO5_IO14

GPIO5_IO15

GPIO5_IO16

GPIO5_IO17

GPIO5_IO18

Input

Keeper

NVCC_QSPI

NVCC_RGMII1

NVCC_RGMII2

RGMII1_RD1

A7

RGMII1_RD2

C7

RGMII1_RD3

C8

RGMII1_RX_CTL

RGMII1_RXC

RGMII1_TD0

B7

C10

E10

A8

RGMII1_TD1

RGMII1_TD2

F9

RGMII1_TD3

E9

RGMII1_TX_CTL

RGMII1_TXC

D10

B8

RGMII2_RD0

C11

A9

RGMII2_RD1

RGMII2_RD2

A11

D11

B9

RGMII2_RD3

RGMII2_RX_CTL

RGMII2_RXC

RGMII2_TD0

A12

A10

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Table 119. 14 x 14 Functional Contact Assignments (continued)

Out of Reset Condition

14x14

Ball

Power

Group

Ball

Type

Ball Name

Default

Mode

Default

Function

Input/

Output

Value

RGMII2_TD1

RGMII2_TD2

RGMII2_TD3

RGMII2_TX_CTL

RGMII2_TXC

RTC_XTALI

RTC_XTALO

SD2_CLK

C12

B10

B12

C9

NVCC_RGMII2

GPIO

—

ALT5

—

GPIO5_IO19

GPIO5_IO20

GPIO5_IO21

GPIO5_IO22

GPIO5_IO23

RTC_XTALI

RTC_XTALO

GPIO6_IO06

GPIO6_IO07

GPIO6_IO08

GPIO6_IO09

GPIO6_IO10

GPIO6_IO11

GPIO7_IO00

Input

—

Keeper

—

NVCC_RGMII2

VDD_SNVS_CAP

NVCC_SD1_SD2

B11

Y17

W17

E12

F12

E13

E14

F10

F11

V11

—

GPIO

ALT5

Input

Keeper

SD2_CMD

SD2_DATA0

SD2_DATA1

SD2_DATA2

SD2_DATA3

SD3_CLK

NVCC_LOW

NVCC_HIGH

100 kΩ

pull-down

SD3_CMD

SD3_DATA0

SD3_DATA1

SD3_DATA2

SD3_DATA3

SD3_DATA4

SD3_DATA5

SD3_DATA6

SD3_DATA7

T13

R11

T11

Y14

T14

U14

U13

V12

U11

NVCC_LOW

NVCC_HIGH

GPIO

ALT5

GPIO7_IO01

GPIO7_IO02

GPIO7_IO03

GPIO7_IO04

GPIO7_IO05

GPIO7_IO06

GPIO7_IO07

GPIO7_IO08

GPIO7_IO09

Input

100 kΩ

pull-down

NVCC_LOW

NVCC_HIGH

100 kΩ

pull-down

NVCC_LOW

NVCC_HIGH

100 kΩ

pull-down

NVCC_LOW

NVCC_HIGH

100 kΩ

pull-down

NVCC_LOW

NVCC_HIGH

100 kΩ

pull-down

NVCC_LOW

NVCC_HIGH

100 kΩ

pull-down

NVCC_LOW

NVCC_HIGH

100 kΩ

pull-down

NVCC_LOW

NVCC_HIGH

100 kΩ

pull-down

NVCC_LOW

NVCC_HIGH

100 kΩ

pull-down

SD4_CLK

SD4_CMD

T10

NVCC_SD4

GPIO

ALT5

GPIO6_IO12

GPIO6_IO13

Input

Keeper

W12

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Package Information and Contact Assignments

Table 119. 14 x 14 Functional Contact Assignments (continued)

Out of Reset Condition

14x14

Ball

Power

Group

Ball

Type

Ball Name

Default

Mode

Default

Function

Input/

Output

Value

SD4_DATA0

SD4_DATA1

Y10

Y11

Y13

W13

Y12

W10

U10

W11

V10

P15

NVCC_SD4

VDD_SNVS_IN

GPIO

ALT5

—

GPIO6_IO14

GPIO6_IO15

GPIO6_IO16

GPIO6_IO17

GPIO6_IO18

GPIO6_IO19

GPIO6_IO20

GPIO6_IO21

GPIO6_IO22

Input

Keeper

SD4_DATA2

SD4_DATA3

SD4_DATA4

SD4_DATA5

SD4_DATA6

SD4_DATA7

SD4_RESET_B

SNVS_PMIC_ON_REQ

SNVS_PMIC_ON Output 100 kΩ pull-up

_REQ

SNVS_TAMPER

TEST_MODE

P14

V15

Y5

VDD_SNVS_IN

NVCC_USB_H

VDD_USB_CAP

GPIO

—

SNVS_TAMPER

TEST_MODE

GPIO7_IO10

GPIO7_IO11

Input

—

100 kΩ

pull-down

100 kΩ

pull-down

USB_H_DATA

GPIO

—

ALT5

—

100 kΩ

pull-down

USB_H_STROBE

USB_OTG1_CHD_B

W5

T17

100 kΩ

pull-down

USB_OTG1_CHD

_B

—

USB_OTG1_DN

USB_OTG1_DP

USB_OTG2_DN

USB_OTG2_DP

XTALI

V19

V20

Y19

W19

T19

T20

VDD_USB_CAP

NVCC_PLL

—

USB_OTG1_DN

USB_OTG1_DP

USB_OTG2_DN

USB_OTG2_DP

XTALI

—

XTALO

NVCC_PLL

XTALO

6.5.3

14 x 14 mm, 0.65 mm pitch, 20 x 20 Ball Map

Table 120 shows the 14 x14 mm, 0.65 mm pitch, 20 x 20 ball map for the i.MX 6SoloX.

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Table 120. 14 x 14 mm Ball Map

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Package Information and Contact Assignments

Table 120. 14 x 14 mm Ball Map (continued)

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Package Information and Contact Assignments

Table 120. 14 x 14 mm Ball Map (continued)

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Revision History

7 Revision History

Table 121 provides a revision history for this data sheet.

Table 121. i.MX 6SoloX Data Sheet Document Revision History

Substantive Change(s)

Rev.

Number

Date

4

10/2018 Changes for this revision include:

• Table 1, “Part Number Nomenclature—i.MX 6SoloX,” on page 5,

– Part Differentiator section: Removed VADC column.”

• Section 4.12.6.1.1, “MII Receive Signal Timing (ENET_RX_DATA3,2,1,0, ENET_RX_EN,

ENET_RX_ER, and ENET_RX_CLK)” on page 82, and Section 4.12.6.1.2, “MII Transmit Signal

Timing (ENET_TX_DATA3,2,1,0, ENET_TX_EN, ENET_TX_ER, and ENET_TX_CLK)” on page 82

– Removed sentence: Additionally, the processor clock frequency must exceed twice the

ENET_RX_CLK frequency.”

• Table 6, “Absolute Maximum Ratings,” on page 21,

– Row VDD_SNVS_IN: Corrected maximum value from 3.4V to 3.6V.

• Table 23, “XTALI and RTC_XTALI DC Parameters,” on page 38,

– Row: XTALI input leakage current at startup, I_{XTALI_STARTUP}: Changed from “... driven 32KHz

RTC clock @ 1.1V” to “...driven 24 MHz clock at 1.1V.”

• Table 55, “eMMC4.4/4.41 Interface Timing Specification,” on page 79,

– Row: SD2, uSDHC Output Delay: Changed t_ODfrom 2.5ns minimum to 2.8ns and 7.1ns

maximum to 6.8ns.

• Table 66, “LCDIF Display Interface Signal Mapping,” on page 89,

– Rows LCD_D23 and LCD_D22: Corrected Column 24-bit DOTCLK LCD IF from G[7] to R[7] and

G[6] to R[6].

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Revision History

Table 121. i.MX 6SoloX Data Sheet Document Revision History (continued)

Date Substantive Change(s)

Rev.

Number

3

09/2017 • Minor formatting updates and editorial corrections throughout.

• Removed references of ‘NTSC/PAL analog video input interface’ from features and throughout.

• Removed support of Video ADC (VADC) and TVDECODE throughout.

• Replaced ipp_dse with DSE throughout.

• Section 1, “Introduction: Replaced LVDDR3 with DDR3L in text description.

• Table 1: Added orderable part numbers in the Ordering Information table.

• Figure 1:

– Changed the Part Differentiator table’s ADC column to include channel count.

– Included Rev 1.4 in Silicon Revision section

• Figure 2: Removed VADC and TV Decoder blocks from the block diagram.

• Section 1.2, “Features”:

– Modified “Displays” information from “Total two interfaces available” to “Total three interfaces

available”. Also added “Two parallel 24-bit display ports, each up to 1080P at 60 Hz” to

the list. Removed “One Parallel 24-bit display port, up to dual WXGA at 60 Hz“.

– Clarified the Miscellaneous interfaces from “Two 4-channel …(ADC)” to “Up to two 4-channel

…(ADC)”.

• Table 6:

– IO Supply for DDR Interface row, added the footnote “The absolute maximum voltage includes an

allowance for 400 mV of overshoot on the IO pins. Per JEDEC standards, the allowed

signal overshoot must be de-rated if NVCC_DRAM exceeds 1.575V.“

– IO Supply for RGMII Interface row, maximum value from 2.725 V to 3.7 V.

– Input/Output Voltage Range row, split the row into DDR and non-DDR and added the corresponding

details.

– 1.2V supply for video A/D converter row, removed

– 3.3V supply for video A/D converter row, parameter name changed to 3.3V supply for analog

circuitry.

• Table 9:

– GPIO supplies row, added NVCC_NAND to the Symbol column.

– Video A/D converter supply row, removed

• Table 12:Following rows removed: VDD_AFE_1P2, VDDA_AFE_3P3

• Table 56: SDR50/SDR104 Interface Timing Specification table, changed duplicate SD2 to SD3. Minor

format changes to minimum and maximum columns for SD2 and SD3 rows.

• Updated introductory text of the following sections: Section 4.6.4.1, “LPDDR2 Mode I/O DC

Parameters, Section 4.6.4.2, “DDR3/DDR3L Mode I/O DC Parameters, Section 4.7.2, “DDR I/O AC

Parameters, Section 4.8.3, “DDR I/O Output Buffer Impedance.

• Corrected Figure 19, "Asynchronous A/D Muxed Write Access," on page 57

• Table 55: Minimum value of ‘uSDHC Input Setup Time’ corrected to 1.7ns.

• Added Section 4.12.5.4, “HS200 Mode Timing.

• Added Section 4.12.9.1, “LCDIF Display Interface Signal Mapping.

• Removed phrase “Case x” from figure titles of all package diagrams. Also updated the diagrams with

NXP branding.

• Table 108:

– Made the following ball positions Reserved: K21, L21, N18.

• Table 109:

– Made the following balls Reserved: L23, L22, K23, and K22.

• Table 110:

– Made the following balls Reserved: K21, K22, K23, L21, L22, L23, N18.

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Table 121. i.MX 6SoloX Data Sheet Document Revision History (continued)

Date Substantive Change(s)

Rev.

Number

2

06/2016 • Changed throughout:

- VDD_AFE_3P3 to VDDA_AFE_3P3

- VDDAD to VDDA_ADC_3P3

• Table 1, changed all instances of “2N19K” to “2N19K or 3N19K”.

• Figure 1, added new row under Silicon Rev, “Rev 1.3 Production...”

• Table 2, i.MX 6SoloX Modules List:

- BCH, deleted “encryption/decryption” in Brief Description column

- eCSPI1-eCSPI5: deleted “with data rate...” in Brief Description column

- uSDHC1-uSDHC4: added “Conforms to the SD...”

- uSDHC1-uSDHC4: deleted 7th and 8th paragraphs

- uSDHC1-uSDHC4: added “Each port is placed...”

• Table 3, Special Signal Considerations

- Signal Name, GPANAIO: updated text to “Analog output for NXP...”

- Signal Name, POR_B: deleted second sentence

• Section 3.2, “Recommended Connections for Unused Analog Interfaces”, removed text and original

table, Recommended Connections for Unused Analog Interfaces, and referred reader to the Hardware

Development Guide.

• Section 4.1.1, “Absolute Maximum Ratings

- added new CAUTION

- updated Table 6, Absolute Maximum Ratings

• Section 4.1.2, “Thermal Resistance, added NOTE

• Table 7, 19x19 mm (VM)..., corrected Junction to Package Top value 0.2 to 2

• Table 8, 17x17 mm NP (VO)..., corrected Junction to Package Top value 0.2 to 2

• Table 9, 14x14 mm (VK)..., updated Junction to Package Top value 0.2 to 2

• Table 9, Operating ranges, USB supply voltages: changed 5.25 to 5.5

• Table 12, Maximum Supply Currents

- added text: Use Maximum IO equation

- added footnotes

• Section 4.2.1, “Power-Up Sequence, - Removed references to the internal POR function. Internal

POR is not supported on the i.MX 6SoloX.”

- Deleted bullets 4 and 5

• Section 4.3.2.3, “LDO_USB, changed 5.25 to 5.5

• Section 4.6.1, “XTALI and RTC_XTALI (Clock Inputs) DC Parameters, added new NOTE.

• Table 23, XTALI and RTC_XTALI DC Parameters, added new footnote, “This voltage specification...”

• Section 4.10, “Multi-mode DDR Controller (MMDC) this new section added, replacing the original

section 4.9.4 DDR SRAM Specific Parameters (DDR3/DDR3L and LPDDR2).

• Table 56, SDR50/SDR104 Interface..., changed SD2 Min and max values to 0.46 and 0.54. Changed

SD5 Max to 0.74.

• Table 63, RGMII Signal Switching Specifications, deleted footnote 1.

• Table 75, Master Mode SAI Timing:

- changed S1 Min value to 20

- changed S3 Min value to 2 x S1

(continued on next page)

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Revision History

Table 121. i.MX 6SoloX Data Sheet Document Revision History (continued)

Date Substantive Change(s)

Rev.

Number

2

06/2016 (continued from previous next page)

• Table 76, Slave Mode SAI Timing:

- changed title from Master Mode Timing to Slave Mode SAI Timing

- changed S11 Min value to 20

- added new row, S19

- added new footnote

• Figure 62, SAI Timing — Slave Modes: added S19

• Table 90, 12-bit ADC Operating Conditions: changed Supply Voltage Min value to 3.0

• Table 104, SD/MMC boot through USDHC4, changed Signal Names from usdhc3.DATA4 -

usdhc3.DATA7, to usdhc4.DATA4 - usdhc4.DATA7

• Table 108, 19x19mmSuppliesContactAssignments:changedGPANAIORemarkfrom“Testsignal...”

to “Analog output for NXP use...”

• Table 109, 19x19 mm Functional Contact Assignments: DRAM_SDCLK_0, updated “Input” to

“Output” and Value to “0”

• Table 112, 17x17 mm NP (no PCIe) supplies contact assignments:

- GPANAIO: changed remark from “Test signal...” to “Analog output for NXP use...”

- VDD_SOC_CAP: deleted L9

- VDD_SOC_IN: added L9

- DRAM_SDCLK0_P: updated “Input” to “Output” and Value to “Low”

• Table 115, 17x17 mm WP (with PCIe) supplies contact assignments:

- GPANAIO: changed remark from “Test signal...” to “Analog output for NXP use...”

- VDD_SOC_IN: added L9

• Table 116 17x17 mm WP (with PCIe) Functional Contact Assignments, DRAM_SDCLK0_P: updated

“Input” to “Output” and Value to “Low”

• Table 118 14x14 mm supplies contact assignments:

- added rows ADC_VREFL and PCIE_CP_CAP

- VDD_HIGH_CAP: added N18

- VDD_HIGH_IN: added P18

- VDD_SOC_IN: added L9

• Table 119, 14x14 mm Functional Contact Assignments, DRAM_SDCLK0_P: updated “Input” to

“Output” and Value to “Low”

- RGMII1_TX_CTL: updated to D10

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Revision History

Table 121. i.MX 6SoloX Data Sheet Document Revision History (continued)

Date Substantive Change(s)

7/2015 • Throughout:

Rev.

Number

1

– Updated Arm Cortex-M4 core operation speed as 227 MHz

– Corrected signal name from NVCC_LVDS_2P5 to NVCC_LVDS

– For supply rail NVCC_LOW, corrected supply input voltage from 3.3 V to 1.8 V

• On page 2, in the list of i.MX 6SoloX features, updated the first bullet, adding that FreeRTOS can be

run on the Cortex-M4.

• Table 1, “Ordering Information,” on page 3:

– Updated Cortex-M4 core operation speed as 227 MHz

– Added footnote on “Cortex-A9 Speed” column

• In Section 1.2, “Features”:

– Corrected second bullet under “External memory interfaces” to say, “16-bit NAND-Flash, including

support for Raw MLC/SLC, 2 KB, 4 KB, and 8 KB page size, BA-NAND, PBA-NAND,

LBA-NAND, OneNAND and others. BCH ECC up to 62 bits. 16-bit boot is supported from

OneNAND. 8-bit boot is supported from other NAND types.”

– Corrected second bullet under “USB” to say, “One HS-IC USB (High Speed Inter-Chip USB) host”

– Corrected first bullet under “Miscellaneous IPs and interfaces” to say, “Three SSIs and two SAIs

supporting up to five I2S or AC97 ports”

– Updated ninth bullet under “Miscellaneous IPs and interfaces” to say, “Two Gigabit Ethernet

Controllers (designed to be compatible with IEEE AVB standards and IEEE Std 1588®),

10/100/1000 Mbps”

• Updated Section 2.1, “Block Diagram”:

– In “Shared Peripherals” block, corrected from UART(5) to UART(1) and added ASRC and ESAI. In

“AP Peripherals” block, added UART(5) and eCSPI(1).

– Updated note regarding number of module instances

• Updated Table 2, “i.MX 6SoloX Modules List,” on page 10

• In Table 3, “Special Signal Considerations,” on page 18:

– In XTALI/XTALO row, added references to engineering bulletin and reference manual

– In row for NVCC_LVDS_2P5, corrected signal name to NVCC_LVDS and updated remarks

• Updated Table 5, “Recommended Connections for Unused Analog Interfaces,” on page 21:

– Deleted row for RTC

– Added row for NVCC_USB_H

– Updated footnote pertaining to PCIe

• Updated Table 6, “Absolute Maximum Ratings,” on page 21:

– Added footnote pertaining to “Symbol” column

– Updated maximum value for VDD_SNVS_IN supply voltage

• Updated Table 9, “Operating Ranges,” on page 25. Table reformatted since previous release; not a

specification change.

• In Section 4.1.4, “External Clock Sources,” added caution about use of the internal RTC oscillator vs.

an external crystal.

• Updated Table 13, “Low Power Mode Current and Power Consumption (LDO Bypass Mode),” on page

30

• In Section 4.5.2, “OSC32K,”

– Added caution about use of the internal RTC oscillator vs. an external crystal

– Updated description of result when the clock monitor determines that the OSC32K is not present

– Removed text pertaining to ~3 V coin-cell battery

• Updated Table 23, “XTALI and RTC_XTALI DC Parameters,” on page 38

(continued on next page)

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Table 121. i.MX 6SoloX Data Sheet Document Revision History (continued)

Rev.

Number

Date

7/2015 (continued from previous page)

Substantive Change(s)

1

• Updated Table 44, “EIM Asynchronous Timing Parameters Relative to Chip Select^,,” on page 58.

Elaborated to show results of calculations. No specification change.

• In Table 64, “DDR3/DDR3L Read Cycle,” on page 93, updated minimum value for DDR26

• Added note regarding ECSPIx_MOSI to Figure 36, "ECSPI Master Mode Timing Diagram," on page

72

• Added note regarding ECSPIx_MISO to Figure 37, "ECSPI Slave Mode Timing Diagram," on page 73

• Updated Figure 42, "SDR50/SDR104 Timing," on page 80

• In Table 67, “LVDS Display Bridge (LDB) Electrical Specification,” on page 91:

– Corrected units for V_OHvalues from ‘mV’ to ‘V’

– Corrected units for V_OLvalues from ‘mV’ to ‘V’

• In Section 4.12.20, “USB PHY Parameters,” in list of amendments to Rev. 2 of the The USB PHY

meets the electrical compliance requirements defined in revision 2.0 of the USB On-The-Go and

Embedded Host Supplement to the USB 2.0 Specification, added “Portable device only” under

“Battery Charging Specification”

• Added Table 107, “Signals with Different States During Reset and After Reset,” on page 128

• In Table 109, “19x19 mm Functional Contact Assignments,” on page 134, corrected GPIO signal

names

• In Table 112, “17x17 mm NP (no PCIe) Supplies Contact Assignments,” on page 153, added ball L9

to the VDD_SOC_CAP row

• In Table 119, “14 x 14 Functional Contact Assignments,” on page 187, corrected power group for SD2

ball names to ‘NVCC_SD1_SD2’

0

2/2015 • Initial public release

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Information in this document is provided solely to enable system and software implementers to

use NXP products. There are no express or implied copyright licenses granted hereunder to

design or fabricate any integrated circuits based on the information in this document. NXP

reserves the right to make changes without further notice to any products herein.

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NXP makes no warranty, representation, or guarantee regarding the suitability of its products for

any particular purpose, nor does NXP assume any liability arising out of the application or use

of any product or circuit, and specifically disclaims any and all liability, including without limitation

consequential or incidental damages. “Typical” parameters that may be provided in NXP data

sheets and/or specifications can and do vary in different applications, and actual performance

may vary over time. All operating parameters, including “typicals,” must be validated for each

customer application by customer’s technical experts. NXP does not convey any license under

its patent rights nor the rights of others. NXP sells products pursuant to standard terms and

conditions of sale, which can be found at the following address:

nxp.com/SalesTermsandConditions.

While NXP has implemented advanced security features, all products may be subject to

unidentified vulnerabilities. Customers are responsible for the design and operation of their

applications and products to reduce the effect of these vulnerabilities on customer’s applications

and products, and NXP accepts no liability for any vulnerability that is discovered. Customers

should implement appropriate design and operating safeguards to minimize the risks associated

with their applications and products.

NXP, the NXP logo, NXP SECURE CONNECTIONS FOR A SMARTER WORLD, COOLFLUX,

EMBRACE, GREENCHIP, HITAG, I2C BUS, ICODE, JCOP, LIFE VIBES, MIFARE, MIFARE

CLASSIC, MIFARE DESFire, MIFARE PLUS, MIFARE FLEX, MANTIS, MIFARE ULTRALIGHT,

MIFARE4MOBILE, MIGLO, NTAG, ROADLINK, SMARTLX, SMARTMX, STARPLUG, TOPFET,

TRENCHMOS, UCODE, Freescale, the Freescale logo, AltiVec, C?5, CodeTEST, CodeWarrior,

ColdFire, ColdFire+, C?Ware, the Energy Efficient Solutions logo, Kinetis, Layerscape, MagniV,

mobileGT, PEG, PowerQUICC, Processor Expert, QorIQ, QorIQ Qonverge, Ready Play,

SafeAssure, the SafeAssure logo, StarCore, Symphony, VortiQa, Vybrid, Airfast, BeeKit,

BeeStack, CoreNet, Flexis, MXC, Platform in a Package, QUICC Engine, SMARTMOS, Tower,

TurboLink, and UMEMS are trademarks of NXP B.V. All other product or service names are the

property of their respective owners. Arm, AMBA, Artisan, Cortex, Jazelle, Keil, SecurCore,

Thumb, TrustZone, and µVision are registered trademarks of Arm Limited (or its subsidiaries) in

the EU and/or elsewhere. Arm7, Arm9, Arm11, big.LITTLE, CoreLink, CoreSight, DesignStart,

Mali, Mbed, NEON, POP, Sensinode, Socrates, ULINK and Versatile are trademarks of Arm

registered trademarks of Oracle and/or its affiliates. The Power Architecture and Power.org word

marks and the Power and Power.org logos and related marks are trademarks and service marks

licensed by Power.org.

Document Number: IMX6SXIEC

Rev. 4

11/2018


型号：	SCIMX6X4AVK10AB
厂家：	NXP
描述：	i.MX 6SoloX Applications Processors for Industrial Products
文件：	总205页 (文件大小：4401K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SCIMX6X4AVK10AB [NXP]

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