SCN68562C2N48 [NXP]
Dual universal serial communications controller DUSCC; 两个通用串行通信控制器DUSCC
| 型号： | SCN68562C2N48 |
| 厂家： | 
NXP |
| 描述： | Dual universal serial communications controller DUSCC |
| 文件： | 总18页 (文件大小：123K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
SCN68562
Dual universal serial communications
controller (DUSCC)
Product specification
IC19 Data Handbook
1995 May 01
Philips
Semiconductors
Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN68562
The transmitter and receiver each contain a four-deep FIFO with
appended transmitter command and receiver status bits and a shift
register. This permits reading and writing of up to four characters at
a time, minimizing the potential of receiver overrun or transmitter
underrun, and reducing interrupt or DMA overhead. In addition, a
flow control capability is provided to disable a remote transmitter
when the FIFO of the local receiving device is full.
DESCRIPTION
The Philips Semiconductors SCN68562 Dual Universal Serial
Communications Controller (DUSCC) is a single-chip MOS-LSI
communications device that provides two independent,
multi-protocol, full-duplex receiver/transmitter channels in a single
package. It supports bit-oriented and character-oriented (byte count
and byte control) synchronous data link controls as well as
asynchronous protocols. The SCN68562 interfaces to the 68000
MPUs via asynchronous bus control signals and is capable of
program-polled, interrupt driven, block-move or DMA data transfers.
The operating mode and data format of each channel can be
programmed independently.
Two modem control inputs (DCD and CTS) and three modem
control outputs are provided. These inputs and outputs can be
optionally programmed for other functions.
FEATURES
Each channel consists of a receiver, a transmitter, a 16-bit
multifunction counter/timer, a digital phase-locked loop (DPLL), a
parity/CRC generator and checker, and associated control circuits.
The two channels share a common bit rate generator (BRG),
operating directly from a crystal or an external clock, which provides
16 common bit rates simultaneously. The operating rate for the
receiver and transmitter of each channel can be independently
selected from the BRG, the DPLL, the counter/timer, or from an
external 1X or 16X clock, making the DUSCC well suited for
dual-speed channel applications. Data rates up to 4Mbits per
second are supported.
General Features
• Dual full-duplex synchronous/asynchronous receiver and
transmitter
• Multiprotocol operation
– BOP: HDLC/ADCCP, SDLC, SDLC loop, X.25 or X.75 link level,
etc.
– COP: BISYNC, DDCMP
– ASYNC: 5–8 bits plus optional parity
• Four character receiver and transmitter FIFOs
PIN CONFIGURATIONS
A PACKAGE
INDEX
CORNER
N PACKAGE
7
47
1
8
46
34
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
V
IACKN
A3
DD
A4
A5
A6
PLCC
A2
A1
RTxDAKBN/
GPI1BN
RTxDAKAN/
GPI1AN
20
IRQN
X1/CLK
21
33
TOP VIEW
RESETN
X2/IDCN
Pin Function
Pin Function
RTSBN/
SYNOUTBN
RTSAN/
SYNOUTAN
1
2
3
4
5
IACKN
A3
A2
27 CSN
28 R/WN
29 DONEN
30 D3
9
TRxCA
TRxCB
RTxCB
10
11
12
13
14
RTxCA
A1
RTxDAKBN/
GPI1BN
IRQN
31 D2
32 D1
33 D0
34 NC
DCDBN/
SYNIBN
DCDAN/
SYNIAN
DIP
6
7
8
9
RxDB
Rxda
TxDA
NC
RESETN
RTSBN/
SYNOUTBN
35 CTSAN/LCAN
36 TxDRQAN/
GPO2AN/RTSAN
37 RTxDRQAN/
GPO1AN
TxDB
TxDAKAN/
GPI2AN
RTxDRQAN/
GPO1AN
TxDRQAN/
GPO2AN/RTSAN
TxDAKBN/
GPI2BN
10 TRxCB
11 RTxCB
12 DCDBN/
SYNIBN
13 NC
14 RxDB
15 TxDB
16 TxDAKBN/
GPI2BN
17 RTxDRQBN/
GPO1BN
18 TxDRQBN/
GPO2BN/RTSBN
19 CTSBN/LCBN
20 D7
21 D6
22 D5
23 D4
24 DTACKN
25 DTCN
RTxDRQBN/ 15
38 TxDAKAN/
GPI2AN
GPO1BN
TxDRQBN/
GPO2BN/RTSBN
16
17
18
39 TxDA
40 RxDA
41 NC
CTSBN/LCBN
CTSAN/LCAN
42 DCDAN/
SYNIAN
D7
D6
D0
D1
43 RTxCA
44 TRxCA
45 RTSAN/
SYNOUTAN
46 X2/IDCN
47 X1/CLK
48 RTxDAKAN/
GPI1AN
19
20
21
22
D5
D2
D4
D3
DONEN
R/WN
CSN
DTACKN
DTCN
GND
23
24
49 A6
50 A5
51 A4
SD00222
26 GND
52 V
DD
Figure 1. Pin Configurations
2
1995 May 01
853-0831 15179
Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN68562
• 0 to 4MHz data rate
• Break generation with handshake for counting break characters
• Detection of start and end of received break
• Programmable bit rate for each receiver and transmitter selectable
from:
• Character compare with optional interrupt on match
• Transmits up to 4Mbs and receive up to 2Mbps data rates
– 16 fixed rates: 50 to 38.4k baud
– One user-defined rate derived from programmable
counter/timer
Character-Oriented Protocol Features
– External 1X or 16X clock
– Digital phase-locked loop
• Character length: 5 to 8 bits
• Odd or even parity, no parity, or force parity
• LRC or CRC generation and checking
• Optional opening PAD transmission
• One or two SYN characters
• Parity and FCS (frame check sequence LRC or CRC) generation
and checking
• Programmable data encoding/decoding: NRZ, NRZI, FM0, FM1,
Manchester
• Programmable channel mode: full- and half-duplex, auto-echo, or
• External sync capability
local loopback
• SYN detection and optional stripping
• SYN or MARK line-fill on underrun
• Idle in MARK or SYNs
• Programmable data transfer mode: polled, interrupt, DMA, wait
• DMA interface
– Compatible with the Philips Semiconductors SCB68430 Direct
Memory Access Interface (DMAI) and other DMA controllers
• Parity, FCS, overrun, and underrun error detection
– Single- or dual-address dual transfers
– Half- or full-duplex operation
BISYNC Features
– EBCDIC or ASCII header, text and control messages
– Automatic frame termination on counter/timer terminal count or
– SYN, DLE stripping
DMA DONE
– EOM (end of message) detection and transmission
– Auto transparent mode switching
• Interrupt capabilities
– Daisy chain option
– Auto hunt after receipt of EOM sequence (with closing PAD
check after EOT or NAK)
– Vector output (fixed or modified by status)
– Programmable internal priorities
– Maskable interrupt conditions
– Control character sequence detection for both transparent and
normal text
• Multi-function programmable 16-bit counter/timer
– Bit rate generator
Bit-Oriented Protocol Features
• Character length: 5 to 8 bits
– Event counter
• Detection and transmission of residual character: 0–7 bits
• Automatic switch to programmed character length for 1 field
• Zero insertion and deletion
– Count received or transmitted characters
– Delay generator
– Automatic bit length measurement
• Modem controls
– RTS, CTS, DCD, and up to four general I/O pins per channel
– CTS and DCD programmable autoenables for Tx and Rx
– Programmable interrupt on change of CTS or DCD
• Optional opening PAD transmission
• Detection and generation of FLAG, ABORT, and IDLE bit patterns
• Detection and generation of shared (single) FLAG between
frames
• On-chip oscillator for crystal
• TTL compatible
• Detection of overlapping (shared zero) FLAGs
• ABORT, ABORT-FLAGs, or FCS FLAGs line-fill on underrun
• Idle in MARK or FLAGs
• Single +5V power supply
Asynchronous Mode Features
• Character length: 5 to 8 bits
• Secondary address recognition including group and global
address
• Odd or even parity, no parity, or force parity
• Up to two stop bits programmable in 1/16-bit increments
• 1X or 16X Rx and Tx clock factors
• Single- or dual-octet secondary address
• Extended address and control fields
• Short frame rejection for receiver
• Parity, overrun, and framing error detection
• False start bit detection
• Detection and notification of received end of message
• CRC generation and checking
• Start bit search 1/2-bit time after framing error detection
• SDLC loop mode capability
3
1995 May 01
Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN68562
ORDERING INFORMATION
V
= +5V +5%, T = 0°C to +70°C
A
CC
DESCRIPTION
DWG #
Serial Data Rate = 4Mbps Maximum
SCN68562C4N48
48-Pin Plastic Dual In-Line Package (DIP)
SOT240-1
SOT238-3
52-Pin Plastic Leaded Chip Carrier (PLCC) Package
SCN68562C4A52
NOTE: See SCN26562/SCN68562 User’s Guide for detailed description of all the features.
BLOCK DIAGRAM
CHANNEL MODE
AND TIMING A/B
D0-D7
BUS
BUFFER
DPLL CLK
MUX A/B
INTERFACE/
OPERATION
CONTROL
DPLL A/B
BRG
ADDRESS
DECODE
COUNTER/
TIMER A/B
DTACKN
RWN
R/W
DECODE
C/T CLK
MUX A/B
MPU
INTERFACE
A1-A6
CSN
DMA
CONTROL
CTCRA/B
CTPRHA/B
CTPRLA/B
CTHA/B
RESETN
CCRA/B
PCRA/B
RSRA/B
RTxDRQAN/GPO1AN
RTxDRQBN/GPO1BN
TxDRQAN/GPO2AN
TxDRQBN/GPO2BN
RTxDAKAN/GPI1AN
RTxDAKBN/GPI1BN
TxDAKAN/GPI2AN
TxDAKBN/GPI2BN
DTCN
CTLA/B
TRSRA/B
ICTSRA/B
TRANSMIT A/B
GSR
TRANS CLK
MUX
DMA INTERFACE
CMR1A/B
CMR2A/B
OMRA/B
TPRA/B
TTRA/B
DONEN
TX SHIFT
REG
TxD A/B
TRANSMIT
4 DEEP
FIFO
TRxCA/B
RTxCA/B
RTSBN/SYNOUTBN
RTSAN/SYNOUTAN
CTSA/BN
SPECIAL
FUNCTION
PINS
CRC
GEN
CONTROL
SPEC CHAR
GEN LOGIC
DCDBN/SYNIBN
DCDAN/SYNIAN
RECEIVER A/B
RCVR CLK
MUX
INTERRRUPT
CONTROL
RPRA/B
RTRA/B
S1RA/B
S2RA/B
ICRA/B
IRQN
IERA/B
IVR
RxD A/B
IACKN
RCVR
SHIFT REG
IVRM
RECEIVER
4 DEEP
FIFO
DUSCC
LOGIC
CRC
ACCUM
X1/CLK
OSCILLATOR
X2/IDCN
BISYNC
COMPARE
LOGIC
SD00223
Figure 2. Block Diagram
4
1995 May 01
Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN68562
PIN DESCRIPTION
In this data sheet, signals are discussed using the terms ‘active’ and ‘inactive’ or ‘asserted’ and ‘negated’ independent of whether the signal is
active in the High (logic 1) or Low (logic 0) state. N at the end of a pin name signifies the signal associated with the pin is active-Low (see
individual pin description for the definition of the active level of each signal.) Pins which are provided for both channels are designated by A/B
after the name of the pin and the active-Low state indicator, N, if applicable. A similar method is used for registers provided for both channels:
these are designated by either an underline or by A/B after the name.
DIP
PIN NO.
MNEMONIC
A1 – A6
TYPE
NAME AND FUNCTION
4-2,
I
Address Lines: Active-High. Address inputs which specify which of the internal registers
45-47
is accessed for read/write operation.
D0 – D7
31-28,
21-18
I/O
Bidirectional Data Bus: Active High, 3-State. Bit 0 is the LSB and bit 7 is the MSB. All
data, command, and status transfers between the CPU and the DUSCC take place over
this bus. The data bus is enabled when CSN is Low, during interrupt acknowledge cycles
and single-address DMA acknowledge cycles.
R/WN
CSN
26
25
I
I
Read/Write: A High input indicates a read cycle and a Low input indicates a write cycle
when a cycle is initiated by assertion of the CSN input.
Chip Select: Active-Low input. When Low, data transfers between the CPU and the
DUSCC are enabled on D0 – D7 as controlled by the R/WN and A1 – A6 inputs. When
CSN is High, the DUSCC is isolated from the data bus (except during interrupt
acknowledge cycles and single-address DMA transfers) and D0 – D7 are placed in the
3-State condition.
DTACKN
22
O
Data Transfer Acknowledge: Active-Low, 3-State. DTACKN is asserted on a write cycle
to indicate that the data on the bus has been latched, and on a read cycle or interrupt
acknowledge cycle to indicate valid data is on the bus. The signal is negated when
completion of the cycle is indicated by negation of the CSN or IACKN input, and returns to
the inactive state (3-State) a short period after it is negated. In a single address DMA
mode, data is latched with the falling edge of DTCN. DTACKN is negated when
completion of the cycle is indicated by the assertion of DTCN or negation of DMA
acknowledge inputs (whichever occurs first), and returns to the inactive state (3-State) a
short period after it is negated. When negated, DTACKN becomes an open-drain output
and requires an external pull-up resistor.
IRQN
6
1
O
I
Interrupt Request: Active-Low, open-drain. This output is asserted upon occurrence of
any enabled interrupting condition. The CPU can read the general status register to
determine the interrupting condition(s), or can respond with an interrupt acknowledge cycle
to cause the DUSCC to output an interrupt vector on the data bus.
IACKN
X1/CLK
X2/IDCN
Interrupt Acknowledge: Active-Low. When IACKN is asserted, the DUSCC responds by
placing the contents of the interrupt vector register (modified or unmodified by status) on
the data bus and asserting DTACKN. If no active interrupt is pending, DTACKN is not
asserted.
43
42
I
Crystal or External Clock: When using the crystal oscillator, the crystal is connected
between pins X1 and X2. If a crystal is not used, and external clock is supplied at this
input. This clock is used to drive the internal bit rate generator, as an optional input to the
counter/timer or DPLL, and to provide other required clocking signals.
O
Crystal or Interrupt Daisy Chain: When a crystal is used as the timing source, the
crystal is connected between pins X1 and X2. This pin can be programmed to provide and
interrupt daisy chain active-Low output which propagates the IACKN signal to lower priority
devices, if no active interrupt is pending. This pin should be grounded when an external
clock is used on X1 and X2, is not used as an interrupt daisy chain output.
RESETN
7
I
I
Master Reset: Active-Low. A low on this pin resets the transmitters and receivers and
resets the registers shown in Table 1 of the CDUSCC Users’ Guide. Reset in
asynchronous, i.e., no clock is required.
RxDA, RxDB
TxDA, TxDB
37, 12
36, 13
Channel A (B) Receiver Serial Data Input: The least significant bit is received first. If
external receiver clock is specified for the channel, the input is sampled on the rising edge
of the clock.
O
Channel A (B) Transmitter Serial Data Output: The least significant bit is transmitted
first. This output is held in the marking (High) condition when the transmitter is disabled or
when the channel is operating in local loopback mode. If external transmitter clock is
specified for the channel, the data is shifted on the falling edge of the clock.
RTxCA, RTxCB
39, 10
I/O
Channel A (B) Receiver/Transmitter Clock: As an input, it can be programmed to
supply the receiver, transmitter, counter/timer, or DPLL clock. As an output, can supply the
counter/timer output, the transmitter shift clock (1X), or the receiver sampling clock (1X).
The maximum external receiver/transmitter clock frequency is 4MHz.
5
1995 May 01
Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN68562
PIN DESCRIPTION (Continued)
DIP
PIN NO.
MNEMONIC
TYPE
NAME AND FUNCTION
TRxCA, TRxCB
40, 9
I/O
Channel A (B) Transmitter/Receiver Clock: As an input, it can supply the receiver,
transmitter, counter/timer, or DPLL clock. As an output, it can supply the counter/timer
output, the DPLL output, the transmitter shift clock (1X), the receiver sampling clock (1X),
the transmitter BRG clock (16X), The receiver BRG clock (16X), or the internal system
clock (X1/2). The maximum external receiver/transmitter clock frequency is 4MHz.
CTSA/BN, LCA/BN
32, 17
38, 11
34, 15
I/O
Channel A (B) Clear-To-Send Input or Loop Control Output: Active-Low. The signal
can be programmed to act as an enable for the transmitter when not in loop mode. The
DUSCC detects logic level transitions on this input and can be programmed to generate an
interrupt when a transition occurs. When operating in the COP loop mode, this pin
becomes a loop control output which is asserted and negated by DUSCC commands.
This output provides the means of controlling external loop interface hardware to go on-line
and off-line without disturbing operation of the loop.
DCDA/BN,
SYNIA/BN
I
Channel A (B) Data Carrier Detected or External Sync Input: The function of this pin is
programmable. As a DCD active-Low input, it acts as an enable for the receiver or can be
used as a general purpose input for the DCD function, the DUSCC detects logic level
transitions on this input and can be programmed to generate an interrupt when a transition
occurs. As an active-Low external sync input, it is used in COP modes to obtain character
synchronization without receipt of a SYN character. This mode can be used in disc or
tape controller applications or for the optional byte timing lead in X.21.
RTxDRQA/BN,
GPO1A/BN
O
Channel A (B) Receiver/Transmitter DMA Service Request or General Purpose
Output: Active-Low. For half-duplex DMA operation, this output indicates to the DMA
controller that one or more characters are available in the receiver FIFO (when the
receiver is enabled) or that the transmit FIFO is not full (when the transmitter is enabled).
For full-duplex DMA operation, this output indicates to the DMA controller that data is
available in the receiver FIFO. In non-DMA mode, this pin is a general purpose output that
can be asserted and negated under program control.
TxDRQA/BN,
GPO2A/BN,
RTSA/BN
33, 16
44, 5
O
Channel A (B) Transmitter DMA Service Request, General Purpose Output, or
Request-to-Send: Active-Low. For full-duplex DMA operation, this output indicates to the
DMA controller that the transmit FIFO is not full and can accept more data. When not in
full-duplex DMA mode, this pin can be programmed as a general purpose or a Request-to
-Send output, which can be asserted and negated under program control (see Detailed
Operation).
RTxDAKA/BN,
GPI1A/BN
I
Channel A (B) Receiver/Transmitter DMA Acknowledge or General Purpose Input:
Active-Low. For half-duplex single address DMA operation, this input indicates to the
DUSCC that the DMA controller has acquired the bus and that the requested bus cycle
(read receiver FIFO or load transmitter FIFO) is beginning. For full-duplex single address
DMA operation, this input indicates to the DUSCC that the DMA controller has acquired
the bus and that the requested read receiver FIFO bus cycle is beginning. Because the
state of this input can be read under program control, it can be used as a general purpose
input when not in single address DMA mode.
TxDAKA/BN,
GP12A/BN
35, 14
I
Channel A (B) Transmitter DMA Acknowledge or General Purpose Input: Active-Low.
When the channel is programmed for full-duplex single address DMA operation, this input
is asserted to indicate to the DUSCC that the DMA controller has acquired the bus and
that the requested load transmitter FIFO bus cycle is beginning. Because the state of this
input can be read under program control, it can be used as a general purpose input when
not in full-duplex single address DMA mode.
DTCN
23
27
I
Device Transfer Complete: Active-Low. DTCN is asserted by the DMA controller to
indicate that the requested data transfer is complete.
DONEN
I/O
O
Done: Active-Low, open-drain. See Detailed Operation for a description of the function of
this pin.
RTSA/BN,
SYNOUTA/BN
41, 8
Channel A (B) Sync Detect or Request-to-Send: Active-Low. If programmed as a sync
output, it is asserted one bit time after the specified sync character (COP or BISYNC
modes) or a FLAG (BOP modes) is detected by the receiver. As a Request-to-Send
modem control signal, it functions as described previously for the TxDRQN/RTSN pin.
V
48
24
I
I
+5V + 10% power input.
DD
GND
Signal and power ground input.
6
1995 May 01
Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN68562
1
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
0 to +70
UNIT
°C
°C
V
2
T
Operating ambient temperature
Storage Temperature
Voltage from V to GND
A
T
-65 to +150
-0.5 to +7.0
STG
3
V
V
CC
CC
3
Voltage from any pin to ground
-0.5 to V +0.5
V
S
CC
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not
implied.
2. For operating at elevated temperatures, the device must be derated based on +150°C maximum junction temperature and thermal
resistance of 40°C/W for plastic DIP and 42°C/W for PLCC.
3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
1, 4
DC ELECTRICAL CHARACTERISTICS
T = 0 to +70°C, V = 5.0V + 5%
A
CC
LIMITS
Typ
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
Min
Max
V
IL
Input low voltage:
All except X1/CLK
X1/CLK
0.8
0.4
V
V
V
IH
Input high voltage:
All except X1/CLK
X1/CLK
2.0
2.4
V
V
V
CC
V
V
Output low voltage:
All except IRQN, DONEN
IRQN, DONEN
Output high voltage:
(Except open drain outputs)
OL
I
I
= 5.3mA
= 8.8mA
0.5
0.5
V
V
OL
OL
OH
I
= -400µA
2.4
V
OH
3
I
I
X1/CLK input low current
V
= 0, X2 = GND
= V , X2 = GND
CC
-5.5
0.0
1.0
mA
mA
ILX1
IN
3
X1/CLK input high current
V
IN
IHX1
3
I
I
X2 input low current
V
= 0, X1 = open
-100
µA
µA
ILX2
IN
3
X2 input high current
V
IN
= V , X1 = open
100
IHX2
CC
I
Input low current
DTCN, TxDAKA/BN, RTxDAKA/BN
IL
V
= 0
-40
-5
µA
µA
IN
I
L
Input leakage current
V
IN
= 0 to V
CC
5
5
I
I
Output off current high, 3-State data bus
Output off current low, 3-State data bus
V
IN
= V
CC
= 0
µA
µA
OZH
V
-5
OZL
ODL
IN
IN
I
Open drain output low current in off
V
= 0
state:
DONEN
IRQN, DTACKN
-120
-5
-25
µA
µA
I
I
Open drain output high current in off
state: DONEN, IRQN, DTACKN
V
= V
ODH
IN CC
5
µA
Power supply current
V
= 0 to V
275
mA
CC
O
CC
2
C
C
C
Input capacitance
V
V
V
= GND = 0
= GND = 0
= GND = 0
10
15
20
pF
pF
pF
IN
CC
CC
CC
2
Output capacitance
Input/output capacitance
OUT
I/O
2
NOTES:
1. Parameters are valid over specified temperature and voltage range.
2. These values were not explicitly tested; they are guaranteed by design and characterization data.
3. X1/CLK and X2 are not tested with a crystal installed.
4. This specification applies to revision D, revision E and later revisions.
7
1995 May 01
Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN68562
1, 2, 3, 4
AC ELECTRICAL CHARACTERISTICS
T = -55 to +110°c, V = 5V + 10%
A
CC
LIMITS
Typ
NO.
FIGURE
PARAMETER
UNIT
Max
Min
1.2
10
0
0
0
1
2
3
4
5
6
7
7A
8
9
10
11
12
12A
13
14
15
3
RESETN pulse width
µS
nS
nS
nS
nS
nS
nS
4,6
4,6
4,6
4,6
4,6
4,5
5
4,5
4
6
4,6
4,6
6
4,6
4,6
5
A1 - A6 set-up time to CSN Low
A1 - A6 hold time from CSN High
RWN set-up time to CSN Low
RWN hold time to CSN High
4
CSN High pulse width
160
30
CSN or IACKN High from DTACKN Low
IACKN High to DTACKN High
200
300
100
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
Data valid from CSN or IACKN Low
7
Data bus floating from CSN High
5
Data hold time from DTACKN Low
0
0
DTACKN Low from read data ready
DTACKN Low from CSN Low
560
50
150
185
550
CSN Low to write data valid
DTACKN High from CSN High
DTACKN high impedance from CSN High
DTACKN Low from IACKN Low
16
17
18
8
8
8
GPI input set-up time to CSN Low
GPI input hold time from CSN Low
GPO output valid from DTACKN Low
20
100
nS
nS
nS
300
19
9
IRQN High from:
Read RxFIFO (RxRDY interrupt)
Write TxFIFO (TxRDY interrupt)
450
450
400
400
400
nS
nS
nS
nS
nS
8
8
Write RSR (Rx condition interrupt)
8
Write TRSR (Rx/Tx interrupt)
8
Write ICTSR (port change and CT int.)
20
10
X1/CLK High or Low time
X1/CLK frequency
CTCLK High or Low time
CTCLK frequency
RxC High or Low time
RxC frequency (16X or 1X)
25
2.0
100
0
110
0
nS
MHz
nS
MHz
nS
MHz
nS
14.7456
16
4
9
4
TxC High or Low time
TxC frequency (16X or 1X)
110
0
4
MHz
21
22
11
11
TxD output from TxC input Low (1X)
(16X)
240
435
nS
nS
nS
TxD output from TxC output Low
50
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
40A
12
12
RxD data set-up time to RxC High
RxD data hold time from RxC High
IACKN Low to daisy chain Low
Data valid from receive DMA ACKN
DTCN width
50
50
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
13
15
200
300
14,15
14,15
15
14,15
14,15
14,15
15
15
14,15
14
100
80
RDYN Low to DTCN Low
Data bus float from DTCN Low
7
200
360
230
250
325
DMA ACKN Low to RDYN (DTACKN) Low
RDYN High from DTCN Low
RDYN High impedance from DTCN Low
Receive DMA REQN High from DMA ACKN Low
Receive DMA ACKN width
150
Receive DMA ACKN Low to DONEN Low
Data set-up to DTCN Low
250
340
50
50
6
14
14
14
14
Data hold from DTCN Low
Transmit DMA REQN High from ACKN Low
Transmit DMA ACKN width
Transmit DMA ACKN Low to DONEN Low output
DTCN Low DONEN output High
150
250
260
14
41
16
CSN Low to transmit DONEN Low output
300
nS
8
1995 May 01
Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN68562
LIMITS
Typ
NO.
FIGURE
PARAMETER
UNIT
Max
Min
42
43
44
16
16
16
CSN Low to transmit DMA REQ negated
CSN Low to receive DONEN Low
CSN Low to receive DMA REQ negated
400
300
400
nS
nS
nS
NOTES:
1. Parameters are valid over specified temperature range.
2. All voltage measurements are referenced to ground (GND). For DC and functional testing, all inputs except X1/CLK swing between 0.8V and
2.0V with a transition time of 20ns maximum. For X1/CLK, this swing is between 0.4V and 2.4V All time measurements are referenced at
input voltages of 0.4V and 2.4V for all inputs. Output levels are referenced at 1.2V and 2.0V, as appropriate.
3. Test conditions for outputs: C = 150pF, except open-drain outputs. Test condition for open-drain outputs: C = 50pF to GND, R = 2.7kΩ to V
CC
L
L
L
except DTACKN whose R = 820Ω to V
and C = 150pF to GND and DONEN which requires C = 50pF to GND and R = 1kΩ to V
.
L
CC
L
L
L
CC
4. This specification will impose maximum 68000 CPU CLK to 6MHz. Higher CPU CLK can be used if repeating bus cycles are not performed.
5. Execution of the valid command (after it is latched) requires three falling edges of X1 (see Figure 14).
6. In single address DMA mode write operation, data is latched by the falling edge of DTCN.
7. These values were not explicitly tested, they are guaranteed by design and characterization data.
8. These timings are from the falling edge of DTACKN (not CSN rising).
9. X1/CLK frequency must be at least four times the receiver serial data rate.
RESETN
1
SD00224
Figure 3. Reset Timing
2
4
3
A1–A6
5
R/WN
CSN
6
9
8
D0–D7
11
7
DTACKN
13
14
12
SD00225
Figure 4. Bus Timing (Read Cycle)
X1/CLK
DTACKN
COMMAND
VALID
SD00226
Figure 5. Command Timing
9
1995 May 01
Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN68562
3
2
A1–A6
5
4
RWN
6
12
CSN
12A
D0–D7
10
DTACKN
7
13
14
SD00228
Figure 6. Bus Timing (Write Cycle)
IRQN
15
IACKN
8
D0–D7
11
7
7A
DTACKN
SD00229
Figure 7. Interrupt Cycle Timing
10
1995 May 01
Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN68562
RWN
CSN
16
17
GPI1N
AND/OR GPI2N
RWN
CSN
18
GPO1N
AND/OR GPO2N
NEW DATA
OLD DATA
DTACK
SD00230
Figure 8. Port Timing
CSN
V
M
19
V
+0.5V
OL
IRQN
V
OL
SD00231
Figure 9. Interrupt Timing
+5V
1K
C1 = C2: 0-5pF + (STRAY < 5pF)
DRIVING FROM
EXTERNAL
SOURCE
CLOCK
TO OTHER
CHIPS
+5V
20
470Ω
X1
X1/CLK
CTCLK
RxC
X1
X2
C1
TxC
DUSCC
20
C2
X2
14.7456 MHz
CRYSTAL SERIES RESISTANCE3 SHOULD
BE LESS THAN 180Ω
SD00232
Figure 10. Clock Timing
11
1995 May 01
Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN68562
1 BIT TIME
(1 OR 16 CLOCKS)
TxC
(INPUT)
21
TxD
22
TxC
(1X OUTPUT)
SD00227
Figure 11. Transmit Timing
SYNOUT
SYNIN
RxC (1x)
INPUT
23
24
RxD
SD00233
Figure 12. Receive Timing
IACKN
IDCN
25
SD00234
Figure 13. Interrupt Daisy Chain Timing
12
1995 May 01
Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN68562
39
30
TxDAKN
36
37
D0–D7
32
RDYN
(DTACKN)
31
DTCN
28
27
DONEN
(INPUT)
TxDRQN
38
40A
DONEN
(OUTPUT)
40
SD000235
Figure 14. DMA Transmit Write Timing—Single Address DMA Mode
34
RTxDAKN
D0–D7
26
29
30
32
RDYN
(DTACKN)
31
DTCN
28
27
40A
DONEN
(OUTPUT)
35
RTxDRQN
33
SD00236
Figure 15. DMA Receive Read Timing—Single Address DMA Mode
13
1995 May 01
Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN68562
DONEN
(OUTPUT)
41
CSN
DTACKN
DONEN
(INPUT)
42
TxDRQN
TRANSMIT DUAL ADDRESS DMA MODE
43
DONEN (OUTPUT)
(EOM)
44
RTxDRQN
SD00237
Figure 16. Dual Address DMA Mode Timing
14
1995 May 01
Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN68562
DIP48: plastic dual in-line package; 48 leads (600 mil)
SOT240-1
15
1995 May 01
Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN68562
PLCC52: plastic leaded chip carrier; 52 leads; pedestal
SOT238-3
16
1995 May 01
Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN68562
NOTES
17
1995 May 01
Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN68562
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 2000
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 01-00
Document order number:
9397 750 06825
Philips
Semiconductors
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