SCN68652 [NXP]
Multi-protocol communications controller MPCC; 多协议通信控制器MPCC
| 型号： | SCN68652 |
| 厂家： | 
NXP |
| 描述： | Multi-protocol communications controller MPCC |
| 文件： | 总28页 (文件大小：632K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
SCN2652/SCN68652
Multi-protocol communications controller
(MPCC)
Product specification
IC19 Data Handbook
1995 May 01
Philips
Semiconductors
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
DESCRIPTION
FEATURES
The SCN2652/68652 Multi-Protocol Communications Controller
(MPCC) is a monolithic n-channel MOS LSI circuit that formats,
transmits and receives synchronous serial data while supporting
bit-oriented or byte control protocols. The chip is TTL compatible,
operates from a single +5V supply, and can interface to a processor
with an 8 or 16-bit bidirectional data bus.
• DC to 2Mbps data rate
• Bit-oriented protocols (BOP): SDLC, ADCCP, HDLC
• Byte-control protocols (BCP): DDCMP, BISYNC (external CRC)
• Programmable operation
– 8 or 16-bit tri-state data bus
– Error control – CRC or VRC or none
APPLICATIONS
• Intelligent terminals
– Character length – 1 to 8 bits for BOP or 5 to 8 bits for BCP
– SYNC or secondary station address comparison for BCP-BOP
– Idle transmission of SYNC/FLAG or MARK for BCP-BOP
• Line controllers
• Automatic detection and generation of special BOP control
• Network processors
sequences, i.e., FLAG, ABORT, GA
• Front end communications
• Remote data concentrators
• Communication test equipment
• Computer to computer links
• Zero insertion and deletion for BOP
• Short character detection for last BOP data character
• SYNC generation, detection, and stripping for BCP
• Maintenance mode for self-testing
• TTL compatible
• Single +5V supply
PIN CONFIGURATION
INDEX
CORNER
6
40
1
CE
RxC
RxSI
S/F
1
2
3
4
5
40
MM
7
39
39 TxC
38 TxSQ
37 TxE
PLCC
RxA
36 TxU
RxDA
RxSA
RxE
6
7
8
9
35 TxBE
34 TxA
29
17
18
28
33 RESET
TOP VIEW
GND
32
V
CC
Pin Function
Pin Function
DIP
DB08 10
DB09 11
DB10 12
31 DB00
30 DB01
29 DB02
1
2
3
4
5
6
7
8
9
NC
CE
23 NC
24 A0
RxC
RxSI
S/F
RxA
RxDA
RxSA
RxE
25 BYTE
26 DBEN
27 DB07
28 DB06
29 DB05
30 DB04
31 DB03
32 DB02
33 DB01
34 NC
DB11 13
DB12 14
DB13 15
DB14 16
DB15 17
R/W 18
28 DB03
27 DB04
26 DB05
25 DB06
24 DB07
23 DBEN
10 GND
11 DB08
12 NC
13 DB09
35 DB00
36 V
CC
14 DB10
15 DB11
16 DB12
17 DB13
18 DB14
19 DB15
20 R/W
21 A2
37 RESET
38 TxA
39 TxBE
40 TxU
41 TxE
42 TxSQ
43 TxC
44 MM
A2 19
A1 20
22 BYTE
21 A0
22 A1
TOP VIEW
NOTE: DB00 is least significant bit, highest number
(that is, DB15, A2) is most significant bit.
SD00057
Figure 1. Pin Configuration
2
1995 May 01
853-1068 15179
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
ORDERING CODE
V
CC
= 5V +5%
PACKAGES
DWG #
Commercial
Industrial
0°C to +70°C
-40°C to +85°C
40-Pin Ceramic Dual In-Line Package (DIP)
40-Pin Plastic Dual In-Line Package (DIP)
44-Pin Square Plastic Lead Chip Carrier (PLCC)
SCN2652AC2F40 / SCN68652AC2F40
SCN2652AC2N40 / SCN68652AC2N40
SCN2652AC2A44 / SCN68652AC2A44
0590B
Contact Factory
Contact Factory
SOT129-1
SOT187-2
1
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNIT
°C
2
T
Operating ambient temperature
Storage temperature
Note 4
A
T
–65 to +150
–0.3 to +7
°C
STG
3
V
All inputs with respect to GND
V
CC
NOTES:
1. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or at any other condition above those indicated in the operation sections of this specification
is not implied.
°
2. For operating at elevated temperatures the device must be derated based on +150 C maximum junction temperature.
3. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
4. Parameters are valid over operating temperature range unless otherwise specified. See ordering code table for applicable temperature
range and operating supply range.
BLOCK DIAGRAM
16 BITS
8 BITS
V
CC
PARAMETER CONTROL
SYNC/ADDRESS
REGISTER
PARAMETER
CONTROL
REGISTER
DATA
BUS
BUFFER
GND
PCSAR
PCR
DB15–
DB00
16
RECEIVER
DATA/STATUS
REGISTER
TRANSMITTER
DATA/STATUS
REGISTER
RDSR
TDSR
RESET
MM
INTERNAL
BUS
16
16
A2–A0
BYTE
READ/
WRITE
LOGIC
AND
CONTROL
R/W
CE
RECEIVER
LOGIC AND
CONTROL
TRANSMITTER
LOGIC AND
CONTROL
DBEN
S/F
RxE
RxA
RxDA
RxC RxSI
TxC TxSO
RxSA
TxE
TxA
TxBE
TxU
SD00058
Figure 2. Block Diagram
3
1995 May 01
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
PIN DESCRIPTION
MNEMONIC PIN NO.
TYPE NAME AND FUNCTION
Data Bus: DB07–DB00 contain bidirectional data while DB15–DB08 contain control and status
17–10
DB15–DB00
information to or from the processor. Corresponding bits of the high and low order bytes can be wire
OR’ed onto an 8-bit bus. The data bus is floating if either CE or DBEN are low.
I/O
24–31
Address Bus: A2–A0 select internal registers. The four 16-bit registers can be addressed on a word or
byte basis. See Register Address section.
A2–A0
19–21
I
Byte: Single byte (8-bit) data bus transfers are specified when this input is high. A low level specifies
16-bit data bus transfers.
BYTE
CE
22
1
I
I
Chip Enable: A high input permits a data bus operation when DBEN is activated.
Read/Write: R/W controls the direction of data bus transfer. When high, the data is to be loaded into the
addressed register. A low input causes the contents of the addressed register to be presented on the
data bus.
R/W
18
23
I
I
Data Bus Enable: After A2–A0, CE, BYTE and R/W are set up, DBEN may be strobed. During a read,
the 3-state data bus (DB) is enabled with information for the processor. During a write, the stable data is
loaded into the addressed register and TxBE will be reset if TDSR was addressed.
DBEN
RESET
MM
33
40
I
I
Reset: A high level initializes all internal registers (to zero) and timing.
Maintenance Mode: MM internally gates TxSO back to RxSI and TxC to RxC for off line diagnostic
purposes. The RxC and RxSI inputs are disabled and TxSO is high when MM is asserted.
Receiver Enable: A high level input permits the processing of RxSI data. A low level disables the
receiver logic and initializes all receiver registers and timing.
RxE
8
5
6
I
Receiver Active: RxA is asserted when the first data character of a message is ready for the processor.
In the BOP mode this character is the address. The received address must match the secondary station
address if the MPCC is a secondary station. In BCP mode, if strip-SYNC (PCSAR ) is set, the first
13
RxA
O
O
non-SYNC character is the first data character; if strip-SYNC is zero, the character following the second
SYNC is the first data character. In the BOP mode, the closing FLAG resets RxA. In the BCP mode, RxA
is reset by a low level at RxE.
Receiver Data Available: RxDA is asserted when an assembled character is in RDSR and is ready to
L
RxDA*
be presented to the processor. This output is reset when RDSR is read.
L
Receiver Clock: RxC (1X) provides timing for the receiver logic. The positive going edge shifts serial
data into the RxSR from RxSI.
RxC
2
4
7
3
I
S/F
O
O
I
SYNC/FLAG: S/F is asserted for one RxC clock time when a SYNC or FLAG character is detected.
Receiver Status Available: RxSA is asserted when there is a zero to one transition of any bit in RDSR
H
RxSA*
RxSI
except for RSOM. It is cleared when RDSR is read.
H
Receiver Serial Input: RxSI is the received serial data. Mark = ‘1’, space = ‘0’.
Transmitter Enable: A high level input enables the transmitter data path between TDSR and TxSO. At
L
the end of a message, a low level input causes TxSO = 1(mark) and TxA = 0 after the closing FLAG
(BOP) or last character (BCP) is output on TxSO.
TxE
37
I
Transmitter Active: TxA is asserted after TSOM (TDSR ) is set and TxE is raised. This output will reset
when TxE is low and the closing FLAG (BOP) or last character (BCP) has been output on TxSO.
8
TxA
34
35
O
O
Transmitter Buffer Empty: TxBE is asserted when theTDSR is ready to be loaded with new control
information or data. The processor should respond by loading theTDSR which resets TxBE.
TxBE*
Transmitter Underrun: TxU is asserted during a transmit sequence when the service of TxBE has been
delayed for one character time. This indicates the processor is not keeping up with the transmitter. Line
TxU*
36
39
O
I
fill depends on PCSAR . TxU is reset by RESET or setting of TSOM (TDSR ), synchronized by the
11
8
falling edge of TxC.
Transmitter Clock: TxC (1X) provides timing for the transmitter logic. The positive going edge shifts
data out of the TxSR to TxSO.
TxC
TxSO
38
32
9
O
I
Transmitter Serial Output: TxSO is the transmitted serial data. Mark = ‘1’, space = ‘0’.
+5V: Power supply.
V
CC
GND
I
Ground: 0V reference ground.
*Indicates possible interrupt signal
4
1995 May 01
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
Table 1.
Register Access
REGISTERS
NO. OF BITS
DESCRIPTION*
Addressable
PCSAR and PCR contain parameters common to the
H
Parameter control sync/
address register
receiver and transmitter. PCSAR contains a programmable
PCSAR
16
L
SYNC character (BCP) or secondary station address (BOP).
PCR
Parameter control register
Receive data/status register
8
RDSR contains receiver status information.
H
RDSR
16
RDSR = RxDB contains the received assembled character.
L
TDSR contains transmitter command and status
H
information. TDSRL = TxDB contains the character to be
transmitted
TDSR
Transmit data/status register
16
Non-Addressable
CCSR
Control character shift register
Holding shift register
8
16
8
HSR
RxSR
Receiver shift register
These registers are used for character assembly (CSSR,
HSR, RxSR), disassembly (TxSR), and CRC
accumulation/generation (RxCRC, TxCRC).
TxSR
Transmitter shift register
8
Receiver CRC accumulation
register
RxCRC
TxCRC
16
16
Transmitter CRC generation
register
NOTES:
*H = High byte – bits 15–8
L = Low byte – bits 7–0
Table 2.
CHARACTER
FCS
Error Control
Table 3.
Special Characters
DESCRIPTION
OPERATION
BOP
BIT PATTERN
FUNCTION
Frame check sequence is transmitted/received
as 16 bits following the last data character of a
BOP message. The divisor is usually
CRC–CCITT (X + X + X + 1) with dividend
preset to 1’s but can be other wise determined
by ECM. The inverted remainder is transmitter as
the FCS.
FLAG
01111110
Frame message
16
12
5
ABORT
11111111 generation Terminate communication
01111111 detection
Terminate loop mode
01111111
GA
repeater function
BCC
Block check character is transmitted/received as
two successive characters following the last data
character of a BCP message. The polynomial is
1
Address
(PCSAR )
Secondary station address
L
BCP
16
15
2
CRC–16 (X + X + X + 1) or CRC–CCITT
with dividend preset to 0’s (as specified by
ECM). The true remainder is transmitted as the
BCC.
(PCSAR ) or
(TxDB) generation
L
SYNC
Character synchronization
2
NOTES:
1. ( ) = contents of.
2. For IDLE = 0 or 1 respectively.
15
14
13
12
11
10
10
9
8
7
6
5
4
3
2
1
0
PCSAR
PCR
APA
PROTO
SS/GA SAM
IDLE
E C M
S/AR
15
14
13
12
12
11
9
8
T
R
x
x
TxCL
RxCL
C
C
L
L
E
E
15
14
13
11
10
9
8
RAB/
GA
RDSR
RERR
A B C
ROR
REOM RSOM
RxDB
TxDB
15
14
13
12
11
10
9
8
TDSR
TERR
NOT DEFINED
TGA
TABORT TEOM TSOM
NOTE:
Refer to Register Formats for mnemonics and description.
SD00059
Figure 3. Short Form Register Bit Formats
5
1995 May 01
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
.
TO
RDSR
L
BCP CRC
.
BOP CRC
.
BCP CRC
8
8
RxSI
M
M
U
X
SYNC
FF
U
X
CCSR (8)
HSR (16)
RxSR (8)
.
1-BIT
DELAY
BOP CRC
SEL
ZERO (BOP)
DELETION
LOGIC
ZERO
DELETION
CONTROL
1
SYNC/FLAG
FROM
XMITTER
COMPARATOR
MM
S/F
PARITY (BCP)
LOGIC
BOP
RERR
CRC–16 (BCP) OR
CCRC–CCITT
(BOP)
CRC–16 = 0
COMPARATOR
CRC–CCIT = F0B8
M
U
X
BCP
RxCRC ACC
RESET
RxE
RxA
RxDA
RECEIVER
CONTROL
LOGIC
RxSA
RxC
NOTES:
1. Detected in SYNC FF and 7 MS bits of CCSR.
2. In BOP mode, a minimum of two data characters must be received to turn the receiver active.
SD00060
Figure 4. MPCC Receiver Data Path
FROM
TDSAR
OR PCSAR (SYNC)
L
L
RESET
SYNC
FF
TxE
TxA
TxSO
TRANS-
MITTER
CONTROL
LOGIC
TXSR (8)
1 BIT
DELAY
TxBE
TxU
BOP
ZERO
INSERTION
LOGIC
M
U
X
ZERO
TXCRC ACC (16)
INSERTION
CONTROL
CRC–16 OR CRC–CCITT
BCP
PARITY
GENERATION
1, 2
SEL
TxC
CONTROL
CHARACTER
GENERATOR
FLAG ABORT
GA
NOTES:
1. TxCRC selected if TEOM = 1 and the last data character has been shifted out of TxSR.
2. In BCP parity selected will be generated after each character is shifted out of TxSR.
SD00088
Figure 5. MPCC Transmitter Data Path
6
1995 May 01
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
should check RDSR
each time RxSA is asserted. If RDSR is
should be examined.
FUNCTIONAL DESCRIPTION
9–15
9
set, then RDSR
12–15
The MPCC can be functionally partitioned into receiver logic,
transmitter logic, registers that can be read or loaded by the
processor, and data bus control circuitry. The register bit formats are
shown in Figure 3 while the receiver and transmitter data paths are
depicted in Figures 4 and 3.
Receiver character length may be changed dynamically in response
to RxDA: read the character in RxDB and write the new character
length into RxCL. The character length will be changed on the next
receiver character boundary. A received residual (short) character
will be transferred into RxDB after the previous character in RxDB
has been read, i.e. there will not be an overrun. In general the last
two characters are protected from overrun.
RECEIVER OPERATION
The CRC–CCITT, if specified by PCSAR
, is accumulated in
8–10
General
RxCRC on each character following the FLAG. When the closing
FLAG is detected in the CCSR, the received CRC is in the 16-bit
HSR. At that time, the Receive End of Message bit (REOM) will be
set; RxSA and RxDA will be asserted. The processor should read
After initializing the parameter control registers (PCSAR and PCR),
the RxE input must be set high to enable the receiver data path. The
serial data on the RxSI is synchronized and shifted into an 8-bit
Control Character Shift Register (CCSR) on the rising edge of RxC.
A comparison between CCSR contents and the FLAG (BOP) or
SYNC (BCP) character is made until a match is found. At that time,
the S/F output is asserted for one RxC time and the 16-bit Holding
Shift Register (HSR) is enabled. The receiver then operates as
described below.
the last data character in RDSR and the receiver status in
L
RDSR
. If RDSR = 1, there has been a transmission error; the
15
9–15
accumulated CRC–CCITT is incorrect. If RDSR
≠ 0, last data
12–14
character is not of prescribed length. Neither the received CRC nor
closing FLAG are presented to the processor. The processor may
drop RxE or leave it active at the end of the received message.
BOP Operation
RxBCP Operation
The operation of the receiver in BCP mode is shown in Figure 7.
The receiver initially searches for two successive SYNC characters,
of length specified by PCR
The next non-SYNC character or next SYNC character, if stripping is
A flowchart of receiver operation in BOP mode appears in Figure 6.
Zero deletion (after five ones are received) is implemented on the
received serial data so that a data character will not be interpreted
as a FLAG, ABORT, or GA. Bits following the FLAG are shifted
through the CCSR, HSR, and into the Receiver Shift Register
(RxSR). A character will be assembled in the RxSR and transferred
, that match the contents of PCSAR .
L
8–10
not specified (PCSAR = 0), causes RxA to be asserted and
13
enables the receiver data path. Once enabled, all characters are
assembled in RxSR and loaded into RDSR . RxDA is active when a
character is available in RDSR . RxSA is active on a 0 to 1
transition of any bit in RDSR . The signals are cleared when RDSRl
to the RDSR for presentation to the processor. At that time the
L
L
RxDA output will be asserted and the processor must take the
character no later than one RxC time after the next character is
assembled in the RxSR. If not, an overrun (RDSR = 1) will occur
L
H
11
or RDSR are read respectively.
H
and succeeding characters will be lost.
If CRC–16 error control is specified by PCSAR
, the processor
8–10
The first character following the FLAG is the secondary station
must determine the last character received prior to the CRC field.
When that character is loaded into RDSR and RxDA is asserted,
address. If the MPCC is a secondary station (PCSAR = 1), the
12
L
contents of RxSR are compared with the address stored in
the received CRC will be in CCSR and HSR . To check for a
L
PCSAR . A match indicates the forthcoming message is intended
L
transmission error, the processor must read the receiver status
for the station; the RxA output is asserted, the character is loaded
(RDSR ) and examine RDSR . This bit will be set for one
H
15
into RDSR , RxDA is asserted and the Receive Start of Message bit
L
character time if an error free message has been received. If
RDSR = 0, the CRC–16 is in error. The state of RDSR in BCP
(RSOM) is set. No match indicates that another station is being
addressed and the receiver searches for the next FLAG.
15
15
CRC mode does not set RxSA. Note that this bit should be
examined only at the end of a message. The accumulated CRC will
include all characters starting with the first non-SYNC character if
If the MPCC is a primary station, (PCSAR = 0), no secondary
address check is made; RxA is asserted and RSOM is set once the
12
first non-FLAG character has been loaded into RDSR and RxDA
L
PCSAR = 1, or the character after the opening two SYNCs if
13
has been asserted. Extended address field can be supported by
PCSAR = 0. This necessitates external CRC generation/checking
13
software if PCSAR = 0.
12
when supporting IBM’s
When the 8 bits following the address character have been loaded
BISYNC. This can be accomplished using the Philips
Semiconductors SCN2653 Polynomial Generator/Checker. See
Typical Applications.
into RDSR and RxDA has been asserted, RSOM will be cleared.
L
The processor should read this 8-bit character and interpret it as the
Control field.
If VRC has been selected for error control, parity (odd or even) is
regenerated on each character and checked when the parity bit is
Received serial data that follows is read and interpreted as the
information field by the processor. It will be assembled into character
received. A discrepancy causes RDSR to be set and RxSA to be
15
lengths as specified by PCR
. As before, RxDA is asserted each
8–10
asserted. This must be sensed by the processor. The received parity
bit is stripped before the character is presented to the processor.
time a character has been transferred into RDSR and is cleared
L
when RDSR is read by the processor. RDSR should only be read
L
H
When the processor has read the last character of the message, it
should drop RxE which disables the receiver logic and initializes all
receiver registers and timing.
when RxSA is asserted. This occurs on a zero to one transition of
any bit in RDSR except for RSOM. RxSA and all bits in RDSR
H
H
except RSOM are cleared when RDSR is read. The processor
H
7
1995 May 01
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
INITIALIZE PCSAR, PCR
PROCESSOR
A
RxE
= 1?
RxE = 1
NO
NO
YES
* TEST MADE
EVERY RxC TIME
FLAG
IN CCSR*
?
YES
S/F = 1
FOR ONE RxC
BIT TIME
FLAG
IN CCSR*
?
YES
NO
ASSEMBLE CHARACTER
(1) OVERRUN (ROVRN)
CAUSES LOSS OF
SUBSEQUENT
IN RxSR. ZERO DELETION,
ACCUMULATE CRC IF
SPECIFIED
CHARACTERS
IS
IT 1st
CHARACTER
AFTER FLAG
?
NO
SECONDARY
STATION
YES
ADDRESS
IS
SEC.
NO
CHARACTER
STATION
MODE
?
YES
= PCSAR
L
?
(PCSAR
= 1)
12
START OF
MESSAGE
NO
(PCSAR
YES
= 0)
12
RxA = 1
RSOM = 1
FOR ONE
CHARACTER
TIME
RxSR → RxDB
RxDA = 1
(PROCESSOR
SHOULD
READ RxDB)
RECEIVER
STATUS BIT 0 → 1
EXCEPT RSOM
?
NO
RXSA = 1
(PROCESSOR SHOULD
READ AND EXAMINE
YES
RDSR – REOM, RAB/GA,
H
ROVRN, ABC, RERR)
FLAG
IN CCSR*
?
RxE → 0
NO
?
NO
YES
A
YES – END OF MESSAGE
S/F = 1 FOR ONE RxC
BIT TIME
REOM = 1, RxA = 0
SD00061
Figure 6. BOP Receive
TRANSMITTER OPERATION
General
TxBOP Operation
Transmitter operation for BOP is shown in Figure 8. A FLAG is sent
after the processor sets the Transmit Start of Message bit (TSOM)
and raises TxE. The FLAG is used to synchronize the message that
follows. TxA will also be asserted. When TxBE is asserted by the
After the parameter control registers (PCSAR and PCR) have been
initialized, TxSO is held at mark until TSOM (TDSR ) is set and TxE
is raised. Then, transmitter operation depends on protocol mode.
8
8
1995 May 01
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
MPCC, the processor should load TDSR with the first character of
CRC–16, if specified by PCSAR
, is generated on each
L
8–10
the message. TSOM should be cleared at the same time TDSR is
character transmitted from TDSR when TSOM =0. The processor
L
L
loaded (16-bit data bus) or immediately thereafter (8-bit data bus).
FLAGS are sent as long as TSOM = 1. For counting the number of
FLAGs, the processor should reassert TSOM in response to the
assertion of TxBE.All succeeding characters are loaded into TDSR
by the processor when TxBE = 1. Each
must set TEOM = 1 after the last data character has been sent to
TxSR (TxBE = 1). The MPCC will finish transmitting the last data
character and the CRC–16 field before sending SYNC characters
which are transmitted as long as TEOM = 1. If SYNCs are not
desired after CRC–16 transmission, the processor should clear
TEOM and lower TxE when the TxBE corresponding to the start of
CRC–16 transmission is asserted. When TEOM = 0, the line is
marked and a new message may be initiated by setting TSOM and
raising TxE.
L
character is serialized in TxSR and transmitted on TxSO. Internal
zero insertion logic stuffs a “0” into the serial bit stream after five
successive “1s” are sent. This insures a data character will not
match a FLAG, ABORT, or GA reserved control character. As each
character is transmitted, the Frame Check Sequence (FCS) is
If VRC is specified, it is generated on each data character and the
data character length must not exceed 7 bits. For software LRC or
CRC, TEOM should be set only if SYNC’s are required at the end of
the message block.
generated as specified by Error Control Mode (PCSAR
FCS should be the CRC–CCITT polynomial (X + X + X + 1)
preset to 1s. If an underrun occurs (processor is not keeping up with
). The
8–10
12 5
16
the transmitter), TxU and TERR (TDSR ) will be asserted with
ABORT or FLAG used as the TxSO line fill depending on the state
15
SPECIAL CASE: The capability to transmit 16 spaces is provided
for line turnaround in half duplex mode or for a control recovery
situation. This is achieved by setting TSOM and TEOM, clearing
TEOM when TxBE = 1, and proceeding as required.
of IDLE (PCSAR ). The processor must set TSOM to reset the
11
underrun condition. To retransmit the message, the processor
should proceed with the normal start of message sequence.
PROGRAMMING
A residual character of 1 to 7 bits may be transmitted at the end of
the information field. In response to TxBE, write the residual
character length into TxCL and load TxDB with the residual
character. Dynamic alteration of character length should be done in
exactly the same sequence. The character length will be changed
on the next transmit character boundary.
Prior to initiating data transmission or reception, PCSAR and PCR
must be loaded with control information from the processor. The
contents of these registers (see Register Format section) will
configure the MPCC for the user’s specific data communication
environment. These registers should be loaded during power-on
initialization and after a reset operation. They can be changed at any
time that the respective transmitter or receiver is disabled.
After the last data character has been loaded into TDSR and sent
L
to TxSR (TxBE = 1), the processor should set TEOM (TDSR ). The
9
The default value for all registers is zero. This corresponds to BOP,
primary station mode, 8-bit character length, FCS = CRC–CCITT
preset to 1s.
MPCC will finish transmitting the last character followed by the FCS
and the closing FLAG. The processor should clear TEOM and drop
TxE when the next TxBE is asserted. This corresponds to the start
of closing FLAG transmission. When TxE has been dropped. TxA
will be low 1 1/2 bit times after the last bit of the closing FLAG has
been transmitted. TxSO will be marked after the closing FLAG has
been transmitted.
For BOP mode the character length register (PCR) may be set to
the desired values during system initialization. The address and
control fields will automatically be 8-bits. If a residual character is to
be transmitted, TxCL should be changed to the residual character
length prior to transmission of that character.
If TxE and TEOM are high, the transmitter continues to send
FLAGs. The processor may initiate the next message by resetting
DATA BUS CONTROL
TEOM and setting TSOM, or by loading TDSR with a data
L
The processor must set up the MPCC register address (A2–A0),
chip enable (CE), byte select (BYTE), and read/write (R/W) inputs
before each data bus transfer operation.
character and then simply resetting TSOM (without setting TSOM).
TxBCP Operation
Transmitter operation for BCP mode is shown in Figure 9. TxA will
be asserted after TSOM = 1 and TxE is raised. At that time SYNC
During a read operation (R/W = 0), the leading edge of DBEN will
initiate an MPCC read cycle. The addressed register will place its
contents on the data bus. If BYTE = 1, the 8-bit byte is placed on
DB15–08 or DB07–00 depending on the H/L status of the register
characters are sent from PCSAR or TDSR (IDLE = 0 or 1) as long
L
L
as TSOM = 1. TxBE is asserted at the start of transmission of the
first SYNC character. For counting the number of SYNCs, the
processor should reassert TSOM in response to the assertion of
addressed. Unused bits in RDSR are zero. If BYTE = 0, all 16 bits
L
(DB15–00) contain MPCC information. The trailing edge of DBEN
TxBE. When TSOM = 0 transmission is from TDSR , which must be
L
will reset RxDA and/or RxSA if RDSR or RDSR is addressed
L
H
loaded with characters from the processor each time TxBE is
asserted. If this loading is delayed for more than one character time,
an underrun results: TxU and TERR are asserted and the
respectively.
DBEN acts as the enable and strobe so that the MPCC will not
begin its internal read cycle until DBEN is asserted.
TxSO line fill depend on IDLE (PCSAR ). The processor must set
11
During a write operation (R/W = 1), data must be stable on DB
15–08
TSOM and retransmit the message to recover. This is not
compatible with IBM’s BISYNC, so that the user must not underrun
when supporting that protocol.
and/or DB
prior to the leading edge of DBEN. The stable data
07–00
is strobed into the addressed register by DBEN. TxBE will be
cleared if the addressed register was TDSR or TDSR .
H
L
9
1995 May 01
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
INITIALIZE PCSAR, PCR
PROCESSOR
RxE = 1
A
RxE
= 1?
NO
YES
SYNC
DETECT
1
NO
IN CCSR?
YES
SYNC
DETECT
IN CCSR?
S/F = 1 FOR ONE
RxC BIT TIME
2
NO
YES
SYNC
DETECT IN
CCSR?
STRIP
SYNC (PCSAR
= 1?
YES
YES
)
13
NO
NO
RxA = 1
(1) SYNCs ARE ASSEMBLED
ASSEMBLE CHARACTER
IN RxSR, STRIP VRC IF
SPECIFIED, ACCUMULATE
CRC IF SPECIFIED
(2) OVERRUN (ROVRN) CAUSES
LOSS OF SUBSEQUENT
CHARACTERS
RxDA = 1
(PROCESSOR
SHOULD READ
RxDB)
RxSR → RxDB
ANY
RECEIVER
STATUS BIT
0 → 1
NO
?
RxSA = 1
(PROCESSOR SHOULD
READ AND EXAMINE
YES
RDSR – ROVRN,
H
RERR (IF VRC
SPECIFIED)
NO
RxE
= 0?
RxE = 0
WHEN LAST
CHARACTER HAS
BEEN SERVICED
YES
A
NOTES:
1. Test made every RxC time.
2. Test made on Rx character boundary.
SD00062
Figure 7. BCP Receive
10
1995 May 01
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
(PROCESSOR MUST CLEAR
TABORT/GA IN RESPONSE
TO TxBE = 1)
INITIALIZE PCSAR, PCR, TDSR
H
A
TxSO = MARK
TSOM
TxE =
1?
TSOM = 1
TxE = 1
NO
YES
B
TxA = 1
TxBE = 1
PROCESSOR
SHOULD LOAD
TxDB AND
TRANSMIT FLAG
ON TxSO
TSOM = 0)
NO
TSOM
= 0?
(PROCESSOR MAY
SET TABORT, TGA,
AS REQUIRED)
YES
YES
TxSO = ABORT = 11111111 IF IDLE = 0
FLAG = 01111110 IF IDLE = 1
TABORT
= 1?
NO
ON UNDERRUN:
TxU = 1, TERR = 1
(PROCESSOR
SHOULD
YES
TxSO = ABORT IF IDLE = 0
FLAG IF IDLE = 1
UNDER
RUN?
SET TSOM)
NO
NO
TSOM
= 1?
SERIALIZE DATA CHARACTER
IN TxDB, ZERO INSERTION,
ACCUMULATE CRC IF
SPECIFIED BY ECM,
TxBE = 1
(PROCESSOR
SHOULD LOAD
TxDB WITH NEXT
DATA CHAR)
YES
B
TRANSMIT ON TxSO
NO
TEOM
= 1?
YES
TRANSMIT ACCUMULATED
FCS (IF SPECIFIED) AS
INVERTED REMAINDER
TxBE = 1
TRANSMIT FLAG ON TxSO*
NO
TEOM
= 0?
(PROCESSOR SHOULD
RESET TEOM AND SET
TSOM OR DROP TxE)
YES
TSOM
= 1?
B
YES
NO
TxE
= 0?
NO
TxA = 0
YES
A
*GA will be transmitted if TGA is set together with TEOM.
SD00063
Figure 8. BOP Transmit
11
1995 May 01
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
INITIALIZE PCSAR, PCR, TDSR
H
PROCESSOR
A
TxSO = MARK
TSOM,
TxE
= 1?
TSOM = 1
TxE = 1
NO
YES
B
TxA = 1
TRANSMIT SYNC ON TxSO
SYNC FROM PCSAR – IDLE = 0
L
TxBE = 1
SYNC FROM TxDB IDLE = 1
NO
TSOM
= 0?
AFTER SYNC(S), PROCESSOR
LOADS DATA CHARACTER
IN TxDB AND TSOM = 0
YES
SERIALIZE DATA CHARACTER
IN TxDB, GENERATE VRC
OR ACCUMULATE CRC AS
TxBE = 1
(PROCESSOR
SHOULD LOAD TxDB)
SPECIFIED, TRANSMIT ON TxSO
(PROCESSOR SHOULD
GET TEOM AT END OF
MESSAGE IF CRC
SPECIFIED)
NO
NO
TEOM
= 1?
UNDER-
RUN?
C
YES
YES
TxU = 1, TERR = 1
(PROCESSOR SHOULD
SET TSOM = 1)
TxSO = SYNC FROM PCSAR IF IDLE = 0
L
MARK IF IDLE = 1
UNTIL TSOM = 1
TRANSMIT ACCUMULATED
CRC SPECIFIED (IF NO
CRC, TEOM SHOULD = 0)
B
TxBE = 1
(PROCESSOR
SHOULD CLEAR
TEOM AND DROP
TxE)
NO
TxSO = SYNC OR TxDB DEPENDING ON
IDLE BIT
TEOM
= 0?
C
YES
NO
TxE
= 0?
TxA = 0
YES
A
SD00064
Figure 9. BCP Transmit
12
1995 May 01
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
Table 4. MPCC Register Addressing
A2
A1
A0
REGISTER
Byte = 0 (16-Bit Data Bus = DB – DB
)
00
15
0
0
1
1
0
1
0
1
X
X
X
X
RDSR
TDSR
PCSAR
PCR*
Byte = 1 (8-Bit Data Bus = DB
or DB
**)
7–0
15–8
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
RDSR
RDSR
TDSR
L
H
L
TDSR
H
PCSAR
PCSAR
PCR *
L
PCR
H
L
H
NOTES:
* PCR lower byte does not exist. It will be all “0”s when read.
** Corresponding high and low order pins must be tied together.
Table 5. Parameter Control Register (PCR)–(R/W)
BIT
NAME
Not Defined
RxCL
MODE
FUNCTION
00–07
08–10
BOP/BCP
Receiver character length is loaded by the processor when RxCLE = 0. The character length is
valid after transmission of single byte address and control fields have been received.
10
0
0
0
0
1
1
1
1
9
0
0
1
1
0
0
1
1
8
0
1
0
1
0
1
0
1
Char length (bits)
8
1
2
3
4
5
6
7
11
12
RxCLE
TxCLE
TxCL
BOP/BCP
BOP/BCP
BOP/BCP
Receiver character length enable should be zero when the processor loads RxCL. The
remaining bits of PCR are not affected during loading. Always 0 when read.
Transmitter character length enable should be zero when the processor loads TxCL. The
remaining bits of PCR are not affected during loading. Always 0 when read.
13–15
Transmitter character length is loaded by the processor when TxCLe = 0. Character bit length
specification format is identical to RxCL. It is valid after transmission of single byte address and
control fields.
13
1995 May 01
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
Table 6. Parameter Control SYNC/Address Register (PCSAR)–(R/W)
BIT
NAME
MODE
FUNCTION
00–07
S/AR
BOP
SYNC/address register. Contains the secondary station address if the MPCC is a secondary
station. The contents of this register is compared with the first received non-FLAG character
to determine if the message is meant for this station.
BCP
SYNC character is loaded into this register by the processor. It is used for receive and
transmit bit synchronization with bit length specified by RxCL and TxCL.
08–10
ECM
BOP/BCP
Error Control Mode
CRC–CCITT preset to 1’s
CRC–CCITT preset to 0’s
Not used
CRC–16 preset to 0’s
VRC odd
VRC even
Not used
No error control
10
0
0
0
0
1
1
1
1
9
0
0
1
1
0
0
1
1
8
0
1
0
1
0
1
0
1
Suggested Mode
Char. length
BOP
BCP
–––
BCP
BCP
BCP
–––
BCP/BOP
1–8
8
8
5–7
5–7
5–8
ECM should be loaded by the processor during initialization or when both data paths are idle.
11
IDLE
Determines line fill character to be used if transmitter underrun occurs (TxU asserted and
TERR set) and transmission of special characters for BOP/BCP.
BOP
BCP
IDLE = 0, transmit ABORT characters during underrun and when TABORT = 1.
IDLE = 1, transmit FLAG characters during underrun and when TABORT = 1.
IDLE = 0 transmit initial SYNC characters and underrun line fill characters from theS/AR.
IDLE = 1 transmit initial SYNC characters from TxDB and marks TxSO during underrun.
12
13
SAM
BOP
Secondary Address Mode = 1 if the MPCC is a secondary station. This facilitates automatic
recognition of the received secondary station address. When transmitting, the processor must
load the secondary address into TxDB.
SAM = 0 inhibits the received secondary address comparison which serves to activate the
receiver after the first non-FLAG character has been received.
SS/GA
Strip SYNC/Go Ahead. Operation depends on mode.
BOP
BCP
SS/GA = 1 is used for loop mode only and enables GA detection. When a GA is detected as a
closing character, REOM and RAB/GA will be set and the processor should terminate the
repeater function. SS/GA = 0 is the normal mode which enables ABORT detection. It causes
the receiver to terminate the frame upon detection of an ABORT or FLAG.
SS/GA = 1, causes the receiver to strip SYNC’s immediately following the first two SYNC’s
detected. SYNC’s in the middle of a message will not be stripped. SS/GA = 0, presents any
SYNC’s after the initial two SYNC’s to the processor.
14
15
PROTO
APA
Determines MPCC Protocol mode
PROTO = 0
PROTO = 1
BOP
BCP
BOP
All parties address. If this bit is set, the receiver data path is enabled by an address field of
‘11111111’ as well as the normal secondary station address.
14
1995 May 01
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
Table 7. Transmit Data/Status Register (TDSR) (R/W except TDSR15)
BIT
NAME
MODE
FUNCTION
00–07
TxDB
BOP/BCP
Transmit data buffer. Contains processor loaded characters to be serialized in TxSR and
transmitted on TxSO.
08
09
TSOM
TEOM
Transmitter start of message. Set by the processor to initiate message transmission provided
TxE = 1.
TSOM = 1 generates FLAGs. When TSOM = 0 transmission is from TxDB and FCS
BOP
BCP
generation (if specified) begins. FCS, as specified by PCSAR
preset to 1’s.
, should be CRC–CCITT
8–10
TSOM = 1 generates SYNCs from PCSAR or transmits from TxDB for IDLE = 0 or 1
L
respectively. When TSOM = 0 transmission is from TxDB and CRC generation (if specified)
begins.
Transmit end of message. Used to terminate a transmitted message.
BOP
BCP
TEOM = 1 causes the FCS and the closing FLAG to be transmitted following the transmission
of the data character in TxSR. FLAGs are transmitted until TEOM = 0. ABORT or GA are
transmitted if TABORT or TGA are set when TEOM = 1.
TEOM = 1 causes CRC–16 to be transmitted (if selected) followed by SYNCs from PCSAR
or TxDB (IDLE = 0 or 1). Clearing TEOM prior to the end of CRC–16 transmission (when
L
TxBE = 1) causes TxSO to be marked following the CRC–16. TxE must be dropped before a
new message can be initiated. If CRC is not selected, TEOM should not be set.
10
11
TABORT
TGA
BOP
BOP
Transmitter abort = 1 will cause ABORT or FLAG to be sent (IDLE = 1 or 1) after the current
character is transmitted. (ABORT = 11111111)
Transmit go ahead (GA) instead of FLAG when TEOM = 1. This facilitates repeater
termination in loop mode. (GA = 01111111)
12–14
15
Not Defined
TERR
Read
only
Transmitter error = 1 indicates the TxDB has not been loaded in time (one character time–1/2
TxC period after TxBE is asserted) to maintain continuous transmission. TxU will be asserted
to inform the processor of this condition. TERR is cleared by setting TSOM. See timing
diagram.
BOP
BCP
ABORT’s or FLAG’s are sent as fill characters (IDLE = 0 or 1)
SYNC’s or MARK’s are sent as fill characters (IDLE = 0 or 1). For IDLE = 1 the last character
before underrun is not valid.
15
1995 May 01
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
Table 8. Receiver Data/Status Register (RDSR)–(Read Only)
BIT
NAME
MODE
FUNCTION
00–07
RxDB
BOP/BCP
Receiver data buffer. Contains assembled characters from the RxSR. If VRC is specified, the
parity bit is stripped.
08
09
RSOM
REOM
RAB/GA
ROR
BOP
BOP
Receiver start of message = 1 when a FLAG followed by a non-FLAG has been received and
the latter character matches the secondary station if SAM = 1. RxA will be asserted when
RSOM = 1. RSOM resets itself after one character time and has no affect on RxSA.
Receiver end of message = 1 when the closing FLAG is detected and the last data character
is loaded into RxDB or when an ABORT/GA character is received. REOM is cleared on
reading RDSR , reset operation, or dropping of RxE.
H
10
BOP
Received ABORT or GA character = 1 when the receiver senses an ABORT character if
SS/GA = 0 or a GA character if SS/GA = 1. RAB/GA is cleared on reading RDSR , reset
H
operation, or dropping of RxE. A received abort does not set RxDA.
11
BOP/BCP
BOP
Receiver overrun = 1 indicates the processor has not read last character in the RxDB within
one character time + 1/2 RxC period after RxDA is asserted. Subsequent characters will be
lost. ROR is cleared on reading RDSR , reset operation, or dropping of RxE.
H
12–14
ABC
Assembled bit count. Specifies the number of bits in the last received data character of a
message and should be examined by the processor when REOM = 1(RxDA and RxSA
asserted). ABC = 0 indicates the message was terminated (by a flag or GA) on a character
boundary as specified by PCR
. Otherwise, ABC = number of bits in the last data
8–10
character. ABC is cleared when RDSR is read, reset operation, or dropping RxE. The
H
residual character is right justified inRDSR .
L
15
RERR
BOP/BCP
Receiver error indicator should be examined by the processor when REOm = 1 in BOP, or
when the processor determines the last data character of the message in BCP with CRC or
when RxSA is set in BCP with VRC.
CRC–CCITT preset to 1’s/0’s as specified by PCSAR
:
8–10
RERR = 1 indicates FCS error (CRC ≠ F0B8 or ≠ 0)
RERR = 0 indicates FCS received correctly (CRC = F0B8 or = 0)
CRC–16 preset to 0’s on 8-bit characters specified by PSCAR
:
8–10
RERR = 1 indicates CRC–16 received correctly (CRC = 0).
RERR = 0 indicates CRC–16 error (CRC≠0)
VRC specified by PCSAR
:
8–10
RERR = 1 indicates VRC error
RERR = 0 indicates VRC is correct.
1, 2
DC ELECTRICAL CHARACTERISTICS
LIMITS
Typ
PARAMETER
TEST CONDITIONS
UNIT
Min
2.0
2.4
Max
Input voltage
V
V
Low
High
0.8
V
IL
IH
Output voltage
V
V
Low
High
I
OL
= 1.6mA
0.4
V
OL
I
= –100µA
OH
OH
I
Power supply current
V
= 5.25V, T = 0°C
150
mA
µA
CC
CC
A
Leakage current
I
I
Input
Output
V
V
= 0 to 5.25V
10
10
IL
IN
= 0 to 5.25V
OL
OUT
Capacitance
C
C
Input
Output
V
= 0V, f = 1MHz
= 0V, f = 1MHz
20
20
pF
IN
IN
V
OUT
OUT
16
1995 May 01
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
1, 2, 3
AC ELECTRICAL CHARACTERISTICS
2MHz CLOCK
Typ
PARAMETER
UNIT
Max
Min
Set-up and hold time
t
t
t
t
t
t
Address/control set-up
Address/control hold
Data bus set-up (write)
Data bus hold (write)
Receiver serial data set-up
Receiver serial data hold
50
0
50
0
150
150
ACS
ACH
DS
ns
ns
DH
RXS
RxH
Pulse width
t
t
RESET
DBEN
250
250
RES
4
m
DBEN
Delay Time
t
t
t
Data bus (read)
Transmit serial data
DBEN to DBEN delay
170
250
DD
ns
TxD
200
DBEND
t
f
Data bus float time (read)
150
2.0
ns
DF
Clock (RxC, TxC) frequency
MHz
t
t
t
Clock high (MM = 0)
Clock high (MM = 1)
Clock low
165
240
240
CLK1
CLK2
CLK0
ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified. See ordering code table for applicable temperature
range and operating supply range.
2. All voltage measurements are referenced to ground. All time measurements are at 0.8V or 2.0V. Input voltage levels for testing are 0.4V and
2.4V.
3. Output load C = 100pF.
L
4. m = TxC low and applies to writing to TDSR only.
H
TIMING DIAGRAMS
RESET
RESET AND WRITE DATA BUS
DBEN
t
DBEN
A
A
2
,
0
t
t
t
t
ACS
ACH
CE, R/W,
BYTE
RESET
t
RES
ACS
ACH
NOT
D
–D
0
15
FLOATING
VALID
VALID
FLOATING
(READ)
t
t
DD
DF
D
–D
0
15
(WRITE)
t
t
DS
DH
SD00065
Figure 10. Timing Diagrams
17
1995 May 01
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
TIMING DIAGRAMS (Continued)
CLOCK
1/f
TxC
t
t
CLK0
CLK1
TxSO
TxD
RxC
t
CLK0
t
CLK1
t
t
RxH
RxS
RxSI
SD00066
Figure 11. Timing Diagrams (cont.)
TRANSMIT – START OF MESSAGE
TxC
TxSO
TxBE
1
8 TxC
MARK
1
1ST CHAR
SYNC/FLAG
3
SET TSOM
LOAD 1st CHAR
RESET TSOM
LOAD 2nd CHAR
DBEN
TxE
2
TxA
NOTES:
1. SYNC may be 5 to 8 bits and will contain parity bit as specified.
2. TxA goes high relative to TxC rising edge after TSOM has been set and TxE has been raised.
3. TxBE goes low relative to DBEN falling edge on the first write transfer into TDSR. It is reasserted 1 TxC time before the first bit of the transmitted SYNC/FLAG. TxBE then goes
low relative to DBEN falling edge when writing into TDSR and/or TDSR . It is reasserted on the rising edge of the TxC that corresponds to the transmission of the last bit of each
H
L
character, except in BOP mode when the CRC is to be sent as the next character (see Transmit Timing–End of Message).
SD00067
Figure 12. Timing Diagrams (cont.)
18
1995 May 01
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
TIMING DIAGRAMS (Continued)
TRANSMIT – END OF BOP MESSAGE
TxC
TxSO
NEXT TO LAST CHAR
LAST CHAR
CRC
FLAG
MARK
1
TxBE
LOAD LAST CHAR
SET TEOM
RESET TEOM
DBEN
2
TxE
3
TxA
NOTES:
1. TxBE goes low relative to the falling edge of DBEN corresponding to loading TDSR . It goes high one TxC before character transmission begins and also when TxA has been
H/L
dropped.
2. TxE can be dropped before resetting TEOM if TxBE (corresponding to the closing FLAG) is high. Alternatively TxE can remain high and a new message initiated.
3. TxA goes low after TxE has been dropped and 1 1/2 TxC’s after the last bit of the closing FLAG has been transmitted.
SD00068
Figure 13. Timing Diagrams (cont.)
TRANSMIT TIMING – END OF BCP MESSAGE
TxC
1
TxSO
TxBE
NEXT TO LAST CHAR
LAST CHAR
MARK
CRC
LOAD LAST CHAR
SET TEOM
RESET TEOM
DBEN
TxE
TxA
NOTE:
1. When SCN2652 generated CRC is not required. TEOM should only be set if SYNCs are to follow the message block. In that case, TxE should be dropped in response to TxBE
(which corresponds to the start of transmission of the last character). When CRC is required, TxE must be dropped before CRC transmission is complete. Otherwise, the contents
of TxDB will be shifted out on TxSO. This facilitates transmission of contiguous messages.
SD00069
Figure 14. Timing Diagrams (cont.)
19
1995 May 01
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
TIMING DIAGRAMS (Continued)
TRANSMIT UNDERRUN
TxC
1
TxU
SET TSOM
2
DBEN
NOTES:
1. TxU goes active relative to TxC falling edge if TxBE has not been serviced after n-1/2 TxC times (where n = transmit character length). TxU is reset on the TxC falling edge follow-
ing assertion of the TSOM command.
2. An underrun will occur at the next character boundary if TEOM is reset and the transmitter remains enabled, unless the TSOM command is asserted or a character is loaded into
the TxDB.
SD00070
Figure 15. Timing Diagrams (cont.)
RECEIVE – START OF MESSAGE
RxC
1
RxA
1st CHAR READY
TO BE READ
2nd CHAR READY
TO BE READ
2
RxDA
1st CHAR READ
2nd CHAR READ
DBEN
3
S/F
RxE
NOTES:
1. RxA goes high relative to falling edge of RxC when RxE is high and: a. A data character following two SYNC’s is in RxDB (BCP mode). b. Character following FLAG is in RxDB
(BOP primary station mode). c. Character following FLAG is in RxDB and character matches the secondary station address or all parties address (BOP secondary station mode).
2. RxDA goes high on RxC falling edge when a character in RxDB is ready to be read. It comes up before RxSA and goes low on the falling edge of DBEN when RxDB is read.
3. S/F goes high relative to rising edge of RxC anytime a SYNC (BCP) or FLAG (BOP) is detected.
SD00071
Figure 16. Timing Diagrams (cont.)
20
1995 May 01
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
TIMING DIAGRAMS (Continued)
RECEIVE END OF MESSAGE
RxC
RxDA
1
RxSA
READ
DATA
READ
STATUS
DBEN
(8-BIT)
S/F
2
RxE
3
RxA
NOTES:
1. At the end of a BOP message, RxSA goes high when FLAG detection (S/F 1) forces REOm to be set. Processor should read the last data character (RDSR ) and status (RDSR
)
L
H
which resets RxDA and RxSA respectively. For BCP end of message, RxSA may not be set and S/F = 0. The processor should read the last data character and status.
2. RxE must be dropped for BCP with non-contiguous messages. It may be left on at the end of a BOP message (see BOP Receive Operation).
3. RxA is reset relative to the falling edge of RxC after the closing FLAG of a BOP message (REOM = 1 and RxSA active.) or when RxE is dropped.
SD00072
Figure 17. Timing Diagrams (cont.)
TYPICAL APPLICATIONS
SCN2652 MPCC MICROPROCESSOR INTERFACE
RESET
TS BUFFER
TxC
STATUS
LR
RESET
DATA BUS
RxC
DB0–DB7
LR
8-BIT
µP
MPCC
SCN2652
SYNCHRO-
NOUS
MODEM
ADDRESS CONTROL
A2–A0, R/W DBEN CE
CLOCK
TxSO
RxSI
Φ
LD
LR
“1”
BYTE
RTS, CTS,
DTR, DSR,
DCD
RxE
TxE
CTS
MODEM
CONTROL
LOGIC
DCD
NOTES:
1. Possible µP interrupt requests are: RxDA RxSA TxBE TxU
2. Other SCN2652 status signals and possible uses are S F line idle indicator, frame delimiter. RxA handshake on RxE, line turn around control. TxA handshake on TxE, line turn
around control.
3. Line drivers/receivers (LD/LR) convert EIA to TTL voltages and vice-versa.
4. RTS should be dropped after the CRC (BCP) or FLAG (BOP) has been transmitted. This forces CTS low and TxE low.
5. Corresponding high and low order bits of DB must be OR tied.
SD00073
Figure 18. Typical Applications
21
1995 May 01
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
TYPICAL APPLICATIONS (Continued)
DMA/PROCESSOR INTERFACE
DATA BUS
8 OR 16 BITS
DB15–DB00
DB15–DB00
DATA BUS
RDREQ
WORD COUNT
ADDRESS PTR
R/W CONTROL
RxDA
RxA
RxE
TO PROCESSOR
WRREQ
RxSA
TxA
TxBE
PROCESSOR (P)
AND
SUPPORT LOGIC:
1. INITIALIZES
SCN2652
TxE
RxDA
R/W
SCN2652
TxU
S/F
DMA
CONTROLLER
TxBE
MEMORY
2. SETS/RESETS
TSOM, TEOM
3. RESPONDS
TO RxSA
A2–A0
BYTE
R/W
CE
DBEN
SCN2652
ADDRESS AND
CONTROL
RESET
MM
ADDRESS
R/W CONTROLS
ADDRESS, R/W,
CONTROL
ADDRESS,
CE, R/W
RxC TxC RxSI TxSO
MODEM OR DCE
SYSTEM ADDRESS AND CONTROL BUS
For non-DMA operation TxBE and RxDA are set to the processor which then loads or reads data characters as required.
SD00074
Figure 19. Typical Applications (cont.)
CHANNEL INTERFACE
BAUD
RATE
GENERATOR
BAUD
RATE
GENERATOR
LD
LR
LR
LD
TxC
RxC
TxC
RxC
COMPUTER
OR
TERMINAL
COMPUTER
OR
TERMINAL
MPCC
SCN2652
MPCC
SCN2652
TxSO
RxSI
RxSI
LD
LR
LR
LD
TxSO
No Modem – DC Baseband Transmission
Figure 20. Typical Applications (cont.)
SD00075
22
1995 May 01
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
SCN2652/SCN2653 INTERFACE TYPICAL PROTOCOLS:
BISYNC, DDCMP, SDLC, HDLC
INTERRUPTS
TxBE, TxU, RxDA, RxSA
DB7–DB0
MPCC
SCN2652
TxD
A2
A1
A0
RxD
TxC
R/W
RxC
DBEN
CE
DB7–DB0
CPU
CE0
PGC
SCN2653
A1
R/W
A0
CE1
INT
(OPEN DRAIN)
5V
SD00076
Figure 21. Typical Applications (cont.)
23
1995 May 01
NOTES:
0.098 (2.49)
0.040 (1.02)
0.098 (2.49)
0.040 (1.02)
SEE NOTE 6
1. Controlling dimension: Inches. Millimeters are
shown in parentheses.
2. Dimension and tolerancing per ANSI Y14. 5M-1982.
3. “T”, “D”, and “E” are reference datums on the body
and include allowance for glass overrun and meniscus
on the seal line, and lid to base mismatch.
4. These dimensions measured with the leads
constrained to be perpendicular to plane T.
0.598 (15.19)
0.571 (14.50)
– E –
5. Pin numbers start with Pin #1 and continue
counterclockwise to Pin #40 when viewed
from the top.
6. Denotes window location for EPROM products.
PIN # 1
– D –
0.100 (2.54) BSC
2.087 (53.01)
2.038 (51.77)
0.620 (15.75)
0.070 (1.78)
0.050 (1.27)
0.590 (14.99)
(NOTE 4)
0.175 (4.45)
0.225 (5.72) MAX.
0.145 (3.68)
– T –
SEATING
PLANE
0.165 (4.19)
0.125 (3.18)
0.055 (1.40)
0.020 (0.51)
BSC
0.600 (15.24)
(NOTE 4)
0.023 (0.58)
0.015 (0.38)
T
E
D
0.010 (0.254)
0.695 (17.65)
0.600 (15.24)
0.015 (0.38)
0.010 (0.25)
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68562
DIP40: plastic dual in-line package; 40 leads (600 mil)
SOT129-1
25
1998 May 01
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68562
PLCC44: plastic leaded chip carrier; 44 leads
SOT187-2
26
1998 May 01
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68562
NOTES
27
1998 May 01
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68562
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 08-98
Document order number:
Philips
Semiconductors
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