SI4884 [NXP]
TrenchMOS⑩ logic level FET; 的TrenchMOS ™逻辑电平FET
| 型号： | SI4884 |
| 厂家： | 
NXP |
| 描述： | TrenchMOS⑩ logic level FET |
| 文件： | 总12页 (文件大小：90K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SI4884
TrenchMOS™ logic level FET
M3D315
Rev. 02 — 12 April 2002
Product data
1. Product profile
1.1 Description
N-channel enhancement mode field-effect transistor in a plastic package using
TrenchMOS™ technology.
Product availability:
SI4884 in SOT96-1 (SO8).
1.2 Features
■ Low on-state resistance
■ Fast switching.
1.3 Applications
■ DC to DC converters
■ Portable equipment applications.
1.4 Quick reference data
■ VDS = 30 V
■ Ptot = 2.5 W
■ ID = 12 A
■ RDSon = 16.5 mΩ.
2. Pinning information
Table 1:
Pin
Pinning - SOT96-1, simplified outline and symbol
Description
source (s)
gate (g)
Simplified outline
Symbol
1,2,3
4
d
8
5
5,6,7,8
drain (d)
g
1
4
s
MBB076
Top view
MBK187
SOT96-1 (SO8)
SI4884
TrenchMOS™ logic level FET
Philips Semiconductors
3. Limiting values
Table 2:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
30
Unit
V
VDS
VGS
ID
drain-source voltage (DC)
Tj = 25 to 150 °C
-
gate-source voltage
drain current
-
±20
12
V
Tsp = 25 °C; Figure 2 and 3
Tsp = 25 °C; pulsed; Figure 3
Tsp = 25 °C; Figure 1
-
A
IDM
Ptot
Tstg
Tj
peak drain current
total power dissipation
storage temperature
junction temperature
-
45
A
-
2.5
W
°C
°C
−55
−55
+150
+150
Source-drain diode
IS
source (diode forward) current
Tsp = 25 °C
-
12
A
9397 750 09582
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 02 — 12 April 2002
2 of 12
SI4884
TrenchMOS™ logic level FET
Philips Semiconductors
03aa17
03aa25
120
120
P
der
I
der
(%)
(%)
80
80
40
40
0
0
0
200
0
150
200
(oC)
50
100
50
100
150
T
(ºC)
T
sp
sp
V
GS ≥ 5 V
Ptot
Pder
=
× 100%
-----------------------
ID
P
°
tot(25 C)
Ider
=
× 100%
-------------------
I
°
D(25 C)
Fig 1. Normalized total power dissipation as a
function of solder point temperature.
Fig 2. Normalized continuous drain current as a
function of solder point temperature.
003aaa160
2
10
Limit R
DSon
= V / I
DS D
I
D
(A)
10
1
t
=
p
10 µs
100 µs
1 ms
10 ms
DC
1 s
-1
10
-2
10
-1
10
1
2
10
10
V
(V)
DS
Tsp = 25 °C; IDM is single pulse
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 09582
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 02 — 12 April 2002
3 of 12
SI4884
TrenchMOS™ logic level FET
Philips Semiconductors
4. Thermal characteristics
Table 3:
Thermal characteristics
Symbol Parameter
Conditions
Min Typ Max
Unit
Rth(j-a)
thermal resistance from junction to ambient mounted on a printed circuit board;
-
60
-
K/W
tp ≤ 10 s; minimum footprint;
Figure 4
4.1 Transient thermal impedance
003aaa161
2
10
Z
th(j-a)
(K/W)
δ = 0.5
0.2
10
0.1
0.05
0.02
t
p
P
δ =
T
single pulse
t
t
p
T
1
2
-4
10
-3
10
-1
10
-2
10
10
1
10
t
(s)
p
Fig 4. Transient thermal impedance from junction to ambient as a function of pulse duration.
9397 750 09582
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 02 — 12 April 2002
4 of 12
SI4884
TrenchMOS™ logic level FET
Philips Semiconductors
5. Characteristics
Table 4:
Characteristics
Tj = 25 °C unless otherwise specified
Symbol Parameter
Conditions
Min Typ Max Unit
Static characteristics
V(BR)DSS drain-source breakdown voltage
ID = 250 µA; VGS = 0 V
ID = 250 µA; VDS = VGS; Figure 9
VDS = 24 V; VGS = 0 V
Tj = 25 °C
30
1
-
-
-
V
V
VGS(th)
IDSS
gate-source threshold voltage
drain-source leakage current
2
-
-
-
-
-
-
-
1
5
µA
µA
Tj = 100 °C
IGSS
gate-source leakage current
VGS = ±20 V; VDS = 0 V
VGS = 4.5 V; ID = 10 A; Figure 7 and 8
VGS = 10 V; ID = 12 A;
100 nA
16.5 mΩ
10.5 mΩ
RDSon
drain-source on-state resistance
11
8.9
Dynamic characteristics
gfs
forward transconductance
VDS = 15 V; ID = 10 A;
-
-
-
-
-
-
-
-
-
-
-
34
-
-
-
-
S
Qg(tot)
Qgs
Qgd
Ciss
Coss
Crss
td(on)
tr
total gate charge
gate-source charge
gate-drain (Miller) charge
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
ID = 15 A; VDD = 16 V; VGS = 5 V; Figure 13
17.6
4
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
4.4
VGS = 0 V; VDS = 16 V; f = 1 MHz; Figure 11
1335 -
391
190
10.6
11.7
37
-
-
-
-
-
-
VDD = 16 V; RD = 10 Ω; VGS = 10 V
td(off)
tf
turn-off delay time
fall time
19
Source-drain (reverse) diode
VSD
trr
source-drain (diode forward) voltage IS = 1 A; VGS = 0 V; Figure 12
-
-
0.7
70
1.0
-
V
reverse recovery time
IS = 2.3 A; dIS/dt = −100 A/µs; VGS = 0 V
ns
9397 750 09582
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 02 — 12 April 2002
5 of 12
SI4884
TrenchMOS™ logic level FET
Philips Semiconductors
003aaa163
003aaa162
20
16
5 V
I
D
I
D
(A)
16
(A)
4 V
2.8 V
12
8
12
8
ο
150
C
ο
25
C
2.5 V
4
0
4
V
= 2.2 V
GS
0
0
0.4
0.8
1.2
1.6
2.0
(V)
0
1
2
3
4
V
(V)
V
GS
DS
Tj = 25 °C
Tj = 25 °C and 150 °C; VDS > ID × RDSon
Fig 5. Output characteristics: drain current as a
function of drain-source voltage; typical values.
Fig 6. Transfer characteristics: drain current as a
function of gate-source voltage; typical values.
03aa27
2
003aaa164
200
a
R
DSon
(mΩ)
V
= 2.5 V
2.2 V
GS
1.6
160
1.2
0.8
0.4
0
120
80
5 V
40
0
4 V
I
0
4
8
12
16
-60
0
60
120
180
(A)
T (oC)
j
D
Tj = 25 °C
RDSon
-----------------------------
RDSon(25°C)
a=
Fig 7. Drain-source on-state resistance as a function
of drain current; typical values.
Fig 8. Normalized drain source on-state resistance
factor as a function of junction temperature.
9397 750 09582
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 02 — 12 April 2002
6 of 12
SI4884
TrenchMOS™ logic level FET
Philips Semiconductors
03aa33
03aa36
-1
-2
-3
-4
-5
-6
2.5
10
I
V
D
GS(th)
(V)
(A)
2
1.5
1
10
10
10
10
10
max
typ
min
typ
max
min
0.5
0
-60
0
60
120
180
0
1
2
3
T (oC)
V
(V)
GS
j
ID = 1 mA; VDS = VGS
Tj = 25 °C; VDS = 5 V
Fig 9. Gate-source threshold voltage as a function of
junction temperature.
Fig 10. Sub-threshold drain current as a function of
gate-source voltage.
003aaa166
003aaa165
20
4
10
I
S
(A)
C
(pF)
16
C
12
iss
3
10
ο
150
C
8
ο
25
C
C
oss
4
0
C
rss
2
10
0.6
1
0.4
0.8
2
-1
10
10
1
10
V
(V)
SD
V
(V)
DS
VGS = 0 V; f = 1 MHz
Tj = 25 °C and 150 °C; VGS = 0 V
Fig 11. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values.
Fig 12. Source (diode forward) current as a function of
source-drain (diode forward) voltage; typical
values.
9397 750 09582
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 02 — 12 April 2002
7 of 12
SI4884
TrenchMOS™ logic level FET
Philips Semiconductors
003aa167
10
V
GS
(V)
8
6
4
2
0
0
10
20
30
40
Q
(nC)
G
ID = 15 A; VDD = 16 V
Fig 13. Gate-source voltage as a function of gate charge; typical values.
9397 750 09582
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 02 — 12 April 2002
8 of 12
SI4884
TrenchMOS™ logic level FET
Philips Semiconductors
6. Package outline
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
8
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
4
e
w
M
detail X
b
p
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(2)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
5.0
4.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.050
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.20
0.014 0.0075 0.19
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches 0.069
0.01 0.004
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-02-04
97-05-22
SOT96-1
076E03S
MS-012AA
Fig 14. SOT96-1 (SO8).
9397 750 09582
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 02 — 12 April 2002
9 of 12
SI4884
TrenchMOS™ logic level FET
Philips Semiconductors
7. Revision history
Table 5:
Revision history
CPCN
Rev Date
Description
02 20020412
-
Product data; version 02. Supersedes data of 15 March 2002.
Figure 3 tp label error corrected.
01 20020315
-
Product data; initial version
9397 750 09582
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 02 — 12 April 2002
10 of 12
SI4884
TrenchMOS™ logic level FET
Philips Semiconductors
8. Data sheet status
Data sheet status[1]
Product status[2]
Definition
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips Semiconductors
reserves the right to change the specification in any manner without notice.
Preliminary data
Product data
Qualification
Production
This data sheet contains data from the preliminary specification. Supplementary data will be published at a
later date. Philips Semiconductors reserves the right to change the specification without notice, in order to
improve the design and supply the best possible product.
This data sheet contains data from the product specification. Philips Semiconductors reserves the right to
make changes at any time in order to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change Notification (CPCN) procedure
SNW-SQ-650A.
[1]
[2]
Please consult the most recently issued data sheet before initiating or completing a design.
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
9. Definitions
10. Disclaimers
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Right to make changes — Philips Semiconductors reserves the right to
make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve
design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
11. Trademarks
TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V.
Contact information
For additional information, please visit http://www.semiconductors.philips.com.
For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.
Fax: +31 40 27 24825
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
11 of 12
9397 750 09582
Product data
Rev. 02 — 12 April 2002
SI4884
TrenchMOS™ logic level FET
Philips Semiconductors
Contents
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data. . . . . . . . . . . . . . . . . . . . . 1
1.1
1.2
1.3
1.4
2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 1
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
Thermal characteristics. . . . . . . . . . . . . . . . . . . 4
Transient thermal impedance . . . . . . . . . . . . . . 4
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 10
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3
4
4.1
5
6
7
8
9
10
11
© Koninklijke Philips Electronics N.V. 2002.
Printed in The Netherlands
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 12 April 2002
Document order number: 9397 750 09582
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