SL3S1204FTB0X [NXP]
SL3S1204 - UCODE 7 SON 6-Pin;![SL3S1204FTB0X](http://pdffile.icpdf.com/pdf2/p00276/img/icpdf/SL3S1204FTB0_1649633_icpdf.jpg)
型号: | SL3S1204FTB0X |
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描述: | SL3S1204 - UCODE 7 SON 6-Pin |
文件: | 总34页 (文件大小:862K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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SL3S1204
UCODE 7
Rev. 3.9 — 21 March 2017
241339
Product data sheet
COMPANY PUBLIC
1. General description
NXP’s UCODE 7 IC is the leading-edge EPC Gen2 RFID chip that offers best-in-class
performance and features for use in the most demanding RFID tagging applications.
Particularly well suited for inventory management application, like e.g Retail and Fashion,
with its leading edge RF performance for any given form factor, UCODE 7 enables long
read distance and fast inventory of dense RFID tag population. With its broadband design,
it offers the possibility to manufacture true global RFID label with best-in-class
performance over worldwide regulations.
The device also provides a pre-serialized 96-bit EPC and a Parallel encoding feature. For
applications where the same 58-bit Stock Keeping Unit (SKU) needs to be encoded on
multiple tags, at the same time, a combination of both features improves and simplifies the
tag initialization process.
On top UCODE 7 offers a Tag Power Indicator for RFID tag initialization optimization and
a Product Status Flag for Electronic Article Surveillance (EAS) application.
2. Features and benefits
2.1 Key features
Read sensitivity 21 dBm
Write sensitivity 16 dBm
Parallel encoding mode: 100 items in 60ms
Encoding speed: 16 bits per millisecond
Innovative functionalities
Tag Power Indicator
Pre-serialization for 96-bit EPC
Integrated Product Status Flag (PSF)
Compatible with single-slit antenna
Up to 128-bit EPC
96-bit Unique Tag Identifier (TID) factory locked,
including 48-bit unique serial number
EPC Gen2 v2.0 ready
SL3S1204
NXP Semiconductors
UCODE 7
2.1.1 Memory
Up to 128-bit of EPC memory
Supports pre-serialization for 96-bit EPC
96-bit Tag IDentifier (TID) factory locked
48-bit unique serial number factory-encoded into TID
No User Memory
32-bit kill password to permanently disable the tag
32-bit access password
Wide operating temperature range: 40 C up to +85 C
Minimum 100.000 write cycle endurance
2.2 Key benefits
2.2.1 End user benefit
Long READ and WRITE ranges due to leading edge chip sensitivity
Very fast bulk encoding
Product identification through unalterable extended TID range, including a 48-bit serial
number
Reliable operation in dense reader and noisy environments through high interference
rejection
2.2.2 Antenna design benefits
High sensitivity enables smaller and cost efficient antenna designs for the same retail
category
Tag Power Indicator features enables very high density of inlay on rolls without cross-
talk issues during writing/encoding
The different input capacitance for the single slit antenna solution provides an
additional possibility in tuning of the impedance for the antenna design
2.2.3 Label manufacturer benefit
Large RF pad-to-pad distance to ease antenna design
Symmetric RF inputs are less sensitive to process variation
Single slit antenna for a more mechanically stable antenna connection
Pre-serialization of the 96-bit EPC
Extremely fast encoding of the EPC content
2.3 Supported features
All mandatory commands of EPC global specification V.1.2.0 are implemented
including:
(Perma)LOCK
Kill Command
The following optional commands are implemented in conformance with the EPC
specification:
Access
BlockWrite (2 words, 32-bit)
SL3S1204
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Product data sheet
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Rev. 3.9 — 21 March 2017
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SL3S1204
NXP Semiconductors
UCODE 7
Product Status Flag bit: enables the UHF RFID tag to be used as EAS
(Electronic Article Surveillance) tag without the need for a back-end data base.
Tag Power Indicator: enables the reader to select only ICs/tags that have enough
power to be written to.
Parallel encoding: allows for the ability to bring (multiple) tag(s) quickly to the OPEN
state and hence allowing single tags to be identified simply, without timing restrictions,
or multiple tags to be e.g. written to at the same time, considerably reducing the
encoding process
All supported features of UCODE 7 can be activated using standard EPCglobal READ /
WRITE / ACCESS / SELECT commands. No custom commands are needed to take
advantage of all the features in case of unlocked EPC memory. The parallel encoding
feature may however require a firmware upgrade of the reader to use its full potential.
3. Applications
3.1 Markets
Retail/Fashion (apparel, footwear, jewelry, cosmetics)
Fast Moving Consumer Goods
3.2 Applications
Retail Inventory management
Supply chain management
Loss prevention
Asset management
Outside the applications mentioned above, please contact NXP Semiconductors for
support.
4. Ordering information
Table 1.
Ordering information
Type number
Package
Name
IC type
Description
Version
SL3S1204FUD/BG1
SL3S1204FUD/HA1
SL3S1204FUD2/BG1
SL3S1204FTB0/1
Wafer
UCODE 7 bumped die on sawn 8” 120 m wafer 7 m Polyimide not applicable
spacer
Wafer
Wafer
XSON6
UCODE 7 die with large pads 3 m Au, 10 m Polyimide spacer not applicable
on sawn 8” 120 m wafer
UCODE 7 bumped die on sawn 12” 120 m wafer 7 m
not applicable
Polyimide spacer
UCODE 7 plastic extremely thin small outline package; no leads; SOT886F1
6 terminals; body 1 1.45 0.5 mm
SL3S1204
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© NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet
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SL3S1204
NXP Semiconductors
UCODE 7
5. Marking
Table 2.
Marking codes
Type number
Marking code
Comment
Version
SL3S1204FTB0/1
YM
UCODE 7
SOT886
6. Block diagram
The SL3S1204 IC consists of three major blocks:
- Analog Interface
- Digital Control
- EEPROM
The analog part provides stable supply voltage and demodulates data received from the
reader which is then processed by the digital part. Further, the modulation transistor of the
analog part transmits data back to the reader.
The digital section includes the state machines, processes the protocol and handles
communication with the EEPROM, which contains the EPC and the user data.
ANALOG
DIGITAL CONTROL
ANTICOLLISION
EEPROM
RF INTERFACE
VREG
VDD
RF1
READWRITE
CONTROL
data
in
RECT
RF2
DEMOD
MOD
MEMORY
antenna
ACCESS CONTROL
data
out
R/W
EEPROM INTERFACE
CONTROL
RF INTERFACE
CONTROL
SEQUENCER
CHARGE PUMP
aaa-005856
Fig 1. Block diagram of UCODE 7 IC
SL3S1204
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Product data sheet
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SL3S1204
NXP Semiconductors
UCODE 7
7. Pinning information
TP1
RF2
SL3S1204 trademark
SL3S12x4FTB0
RF2
n.c.
n.c.
1
2
3
6
5
4
RF1
n.c.
n.c.
TP2
RF1
aaa-018831
Transparent top view
aaa-005611
Fig 2. Pinning bare die
Fig 3. Pin configuration for SOT886
7.1 Pin description
Table 3.
Symbol
TP1
Pin description bare die
Description
test pad 1
RF1
antenna connector 1
test pad 2
TP2
RF2
antenna connector 2
Table 4.
Pin description SOT886
Pin
1
Symbol
RF2
n.c.
Description
antenna connector
not connected
not connected
not connected
not connected
antenna connector
2
3
n.c.
4
n.c.
5
n.c.
6
RF1
SL3S1204
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Product data sheet
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UCODE 7
8. Wafer layout
8.1 Wafer layout 8 inch
(1)
TP1
RF2
(5)
Y
(4)
(6)
X
(7)
TP2
RF1
(8)
(2)
(3)
not to scale!
aaa-005606
(1) Die to Die distance (metal sealring - metal sealring) 21,4 m, (X-scribe line width: 15 m)
(2) Die to Die distance (metal sealring - metal sealring) 21,4 m, (Y-scribe line width: 15 m)
(3) Chip step, x-length: 460 m
(4) Chip step, y-length: 505 m
(5) Bump to bump distance X (TP1 - RF2): 358 m
(6) Bump to bump distance Y (RF1 - RF2): 403 m
(7) Distance bump to metal sealring X: 40,3m (outer edge - top metal)
(8) Distance bump to metal sealring Y: 40,3 m
Bump size X x Y: 60 m x 60 m
Remark: TP1 and TP2 are electrically disconnected after dicing
Fig 4. UCODE 7 8 inch wafer layout
SL3S1204
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SL3S1204
NXP Semiconductors
UCODE 7
8.2 Wafer layout 8 inch with large pads
(2)
(1)
TP1
RF2
(4)
(5)
(13)
(12)
(11)
TP2
RF1
(10)
Y
(6)
(8)
(7)
(9)
X
(3)
not to scale!
aaa-026778
(1) Die to Die distance (metal sealring - metal sealring) 21,4 m, (Y-scribe line width: 15 m)
(2) Die to Die distance (metal sealring - metal sealring) 21,4 m, (X-scribe line width: 15 m)
(3) Chip step, x-length: 460 m
(4) Chip step, y-length: 505 m
(5) Bump to bump distance Y (RF1 - RF2): 115 m
(6) Distance bump to metal sealring X: 23,5 m
(7) Bump size (TP1, TP2) X: 130m
(8) Bump to bump distance X (RF1 - TP2): 50 m
(9) Bump size (RF1, RF2) X: 218m
(10) Distance bump to metal sealring Y: 23,5 m
(11) Bump size (TP1, TP2) Y: 153,1m
(12) Bump size (RF1, RF2) Y: 164m
(13) Distance bump to metal sealring Y: 466,5 m
Remark: TP1 and TP2 are electrically disconnected after dicing
Fig 5. UCODE 7 8 inch wafer layout with large pads
SL3S1204
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Product data sheet
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SL3S1204
NXP Semiconductors
UCODE 7
8.3 Wafer layout 12 inch
(1)
TP1
RF2
(5)
Y
(4)
(6)
X
(7)
TP2
RF1
(8)
(2)
(3)
not to scale!
aaa-005606
(1) Die to Die distance (metal sealring - metal sealring) 39 m, (X-scribe line width: 35 m)
(2) Die to Die distance (metal sealring - metal sealring) 39 m, (Y-scribe line width: 35 m)
(3) Chip step, x-length: 480 m
(4) Chip step, y-length: 525m
(5) Bump to bump distance X (TP1 - RF2): 358 m
(6) Bump to bump distance Y (RF1 - RF2): 403 m
(7) Distance bump to metal sealring X: 40,3m (outer edge - top metal)
(8) Distance bump to metal sealring Y: 40,3 m
Bump size X x Y: 60 m x 60 m
Remark: TP1 and TP2 are electrically disconnected after dicing
Fig 6. UCODE 7 12 inch wafer layout
SL3S1204
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Product data sheet
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SL3S1204
NXP Semiconductors
UCODE 7
9. Mechanical specification
The UCODE 7 wafers are available in 120 m thickness. The 120 m thick wafer is
enhanced with 7m /10m Polyimide spacer resulting in less coupling between the
antenna and the active circuit, leaving more room for process control (like pressure).
9.1 Wafer specification
9.1.1 8 inch Wafer, Standard bumps
See Ref. 21 “Data sheet - Delivery type description – General specification for 8” wafer on
UV-tape with electronic fail die marking, BU-S&C document number: 1093**”.
Table 5.
Wafer
Specifications
Designation
each wafer is scribed with batch number and
wafer number
Diameter
200 mm (8”) unsawn - 205 mm typical sawn
on foil
Thickness
SL3S1204FUD/BG
Number of pads
Pad location
120 m 15 m
4
non diagonal / placed in chip corners
Distance pad to pad RF1-RF2
Distance pad to pad TP1-RF2
Process
403.0 m
358.0 m
CMOS 0.14 m
25 wafers
126.524
Batch size
Potential good dies per wafer
Wafer backside
Material
Si
Treatment
ground and stress release
Ra max. 0.5 m, Rt max. 5 m
Roughness
Chip dimensions
Die size excluding scribe
Scribe line width:
0.490 mm 0.445 mm = 0.218 mm2
x-dimension = 15 m
y-dimension = 15 m
Passivation on front
Type
Sandwich structure
Material
PE-Nitride (on top)
Thickness
1.75 m total thickness of passivation
7 m 1 m
Polyimide spacer
Au bump
Bump material
Bump hardness
Bump shear strength
Bump height
> 99.9 % pure Au
35 – 80 HV 0.005
> 70 MPa
SL3S1204
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Product data sheet
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NXP Semiconductors
UCODE 7
Table 5.
Specifications
SL3S1204FUD/BG
25 m[1]
Bump height uniformity
within a die
2 m
3 m
4 m
1.5 m
– within a wafer
– wafer to wafer
Bump flatness
Bump size
– RF1, RF2
60 60 m
60 60 m
5 m
– TP1, TP2
Bump size variation
[1] Because of the 7 m spacer, the bump will measure 18 m relative height protruding the spacer.
9.1.2 8 inch Wafer, Large pads
See Ref. 21 “Data sheet - Delivery type description – General specification for 8” wafer on
UV-tape with electronic fail die marking, BU-S&C document number: 1093**”.
Table 6.
Wafer
Specifications
Designation
each wafer is scribed with batch number and
wafer number
Diameter
200 mm (8”) unsawn - 205 mm typical sawn
on foil
Thickness
SL3S1204FUD/HA
Number of pads
Pad location
120 m 15 m
4
non diagonal / placed in chip corners
CMOS 0.14 m
Process
Batch size
25 wafers
Potential good dies per wafer
Wafer backside
Material
126.524
Si
Treatment
ground and stress release
Ra max. 0.5 m, Rt max. 5 m
Roughness
Chip dimensions
Die size excluding scribe
Scribe line width:
0.490 mm 0.445 mm = 0.218 mm2
x-dimension = 15 m
y-dimension = 15 m
Passivation on front
Type
Sandwich structure
Material
PE-Nitride (on top)
Thickness
1.75 m total thickness of passivation
10 m 2 m
Polyimide spacer
SL3S1204
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UCODE 7
Table 6.
Au Pad
Specifications
Pad material
> 99.9 % pure Au
35 – 80 HV 0.005
> 70 MPa
Pad hardness
Pad shear strength
Pad height
SL3S1204FUD/HA
Pad height uniformity
within a die
3 m
max. 2 m
max. 4 m
max. 3 m
– within a wafer
Pad flatness
Pad size
– RF1, RF2 (max. details see wafer layout)
– TP1, TP2 (max. details see wafer layout)
Pad size variation
218 164 m
130 153.1 m
5 m
9.1.3 12 inch Wafer
See Ref. 23 “Data sheet - Delivery type description – General specification for 12” wafer
on UV-tape with electronic fail die marking, BU-S&C document number: 1862**”
Table 7.
Wafer
Specifications
Designation
each wafer is scribed with batch number and
wafer number
Diameter
300 mm (12”) unsawn and sawn on foil
Thickness
SL3S1204FUD2
Number of pads
Pad location
120 m 15 m
4
non diagonal / placed in chip corners
Distance pad to pad RF1-RF2
Distance pad to pad TP1-RF2
Process
403.0 m
358.0 m
CMOS 0.14 m
25 wafers
264.696
Batch size
Potential good dies per wafer
Wafer backside
Material
Si
Treatment
ground and stress release
Ra max. 0.5 m, Rt max. 5 m
Roughness
Chip dimensions
Die size excluding scribe
Scribe line width:
0.490 mm 0.445 mm = 0.218 mm2
x-dimension = 35 m
y-dimension = 35 m
Passivation on front
Type
Sandwich structure
SL3S1204
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Product data sheet
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NXP Semiconductors
UCODE 7
Table 7.
Specifications
Material
PE-Nitride (on top)
Thickness
1.75 m total thickness of passivation
7 m 1 m
Polyimide spacer
Au bump
Bump material
Bump hardness
Bump shear strength
Bump height
> 99.9 % pure Au
35 – 80 HV 0.005
> 70 MPa
SL3S1204FUD2
Bump height uniformity
within a die
25 m[1]
2 m
3 m
4 m
1.5 m
– within a wafer
– wafer to wafer
Bump flatness
Bump size
– RF1, RF2
60 60 m
60 60 m
5 m
– TP1, TP2
Bump size variation
[1] Because of the 7 m spacer, the bump will measure 18 m relative height protruding the spacer.
9.1.4 Fail die identification
No inkdots are applied to the wafer.
Electronic wafer mapping (SECS II format) covers the electrical test results and
additionally the results of mechanical/visual inspection.
See Ref. 21 “Data sheet - Delivery type description – General specification for 8” wafer on
UV-tape with electronic fail die marking, BU-S&C document number: 1093**”
See Ref. 23 “Data sheet - Delivery type description – General specification for 12” wafer
on UV-tape with electronic fail die marking, BU-S&C document number: 1862**”
9.1.5 Map file distribution
See Ref. 21 “Data sheet - Delivery type description – General specification for 8” wafer on
UV-tape with electronic fail die marking, BU-S&C document number: 1093**”
See Ref. 23 “Data sheet - Delivery type description – General specification for 12” wafer
on UV-tape with electronic fail die marking, BU-S&C document number: 1862**”
SL3S1204
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Product data sheet
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SL3S1204
NXP Semiconductors
UCODE 7
10. Functional description
10.1 Air interface standards
The UCODE 7 fully supports all parts of the "Specification for RFID Air Interface
EPCglobal, EPC Radio-Frequency Identity Protocols, Class-1 Generation-2 UHF RFID,
Protocol for Communications at 860 MHz to 960 MHz, Version 1.2.0".
10.2 Power transfer
The interrogator provides an RF field that powers the tag, equipped with a UCODE 7. The
antenna transforms the impedance of free space to the chip input impedance in order to
get the maximum possible power for the UCODE 7 on the tag.
The RF field, which is oscillating on the operating frequency provided by the interrogator,
is rectified to provide a smoothed DC voltage to the analog and digital modules of the IC.
The antenna that is attached to the chip may use a DC connection between the two
antenna pads. Therefore the UCODE 7 also enables loop antenna design.
10.3 Data transfer
10.3.1 Interrogator to tag Link
An interrogator transmits information to the UCODE 7 by modulating an UHF RF signal.
The UCODE 7 receives both information and operating energy from this RF signal. Tags
are passive, meaning that they receive all of their operating energy from the interrogator's
RF waveform.
An interrogator is using a fixed modulation and data rate for the duration of at least one
inventory round. It communicates to the UCODE 7 by modulating an RF carrier.
For further details refer to Ref. 1. Interrogator-to-tag (R=>T) communications.
10.3.2 Tag to interrogator Link
Upon transmitting a valid command an interrogator receives information from a UCODE 7
tag by transmitting an unmodulated RF carrier and listening for a backscattered reply. The
UCODE 7 backscatters by switching the reflection coefficient of its antenna between two
states in accordance with the data being sent. For further details refer to Ref. 1, chapter
6.3.1.3.
The UCODE 7 communicates information by backscatter-modulating the amplitude and/or
phase of the RF carrier. Interrogators shall be capable of demodulating either
demodulation type.
The encoding format, selected in response to interrogator commands, is either FM0
baseband or Miller-modulated subcarrier.
SL3S1204
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UCODE 7
10.4 Supported commands
The UCODE 7 supports all mandatory EPCglobal V1.2.0 commands including
• Kill command
• (perma) LOCK command
In addition the UCODE7 supports the following optional commands:
• ACCESS
• Block Write (32 bit)
10.5 UCODE 7 memory
The UCODE 7 memory is implemented according EPCglobal
Class1Gen2 and organized in three banks:
Table 8.
Name
UCODE 7 memory sections
Size
Bank
00b
01b
01b
10b
Reserved memory (32 bit ACCESS and 32 bit KILL password)
EPC (excluding 16 bit CRC-16 and 16 bit PC)
UCODE 7 Configuration Word
64 bit
128 bit
16 bit
96 bit
TID (including permalocked unique 48 bit serial number)
The logical address of all memory banks begin at zero (00h).
In addition to the three memory banks one configuration word to handle the UCODE 7
specific features is available at EPC bank 01 address bit-200h. The configuration word is
described in detail in 9.6.
The TID complies to the extended tag Identification scheme according GS1 EPC Tag Data
Standard 1.6.
SL3S1204
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UCODE 7
10.5.1 UCODE 7 overall memory map
Table 9.
UCODE 7 overall memory map
Bank
address
Memory
address
Type
Content
Initial
Remark
Bank 00
00h to 1Fh
20h to 3Fh
00h to 0Fh
reserved
reserved
EPC
kill password
all 00h
all 00h
unlocked memory
unlocked memory
access password
CRC-16: refer to Ref. 17
Bank 01
EPC
memory mapped
calculated CRC
10h to 14h
15h
EPC
EPC
EPC
EPC
EPC
EPC
EPC
EPC
EPC
EPC
EPC
EPC
EPC
EPC
EPC
EPC
EPC
EPC
EPC
EPC
EPC
TID
EPC length
UMI
00110b
0b
unlocked memory
unlocked memory
hardwired to 0
unlocked memory
unlocked memory
locked memory
locked memory
Action bit[4]
16h
XPC indicator
0b
17h to 1Fh
20h to 9Fh
200h
numbering system indicator 00h
[1]
EPC
Bank 01
Config Word
RFU
0b
201h
RFU
0b
202h
Parallel encoding
0b
203h
RFU
0b
locked memory
Action bit[4]
204h
Tag Power Indicator
0b
205h
RFU
0b
locked memory
locked memory
locked memory
locked memory
permanent bit[5]
locked memory
locked memory
locked memory
locked memory
locked memory
Permanent bit[5]
locked memory
locked memory
locked memory
locked memory
locked memory
locked memory
206h
RFU
0b
207h
RFU
0b
208h
RFU
0b
209h
max. backscatter strength
1b
20Ah
RFU
0b
20Bh
RFU
0b
20Ch
RFU
0b
20Dh
RFU
0b
20Eh
RFU
0b
20Fh
PSF alarm flag
allocation class identifier
0b
Bank 10
TID
00h to 07h
08h to 13h
14h
1110 0010b
TID
tag mask designer identifier 1000 0000 0110b
TID
config word indicator
tag model number
XTID header
1b[2]
14h to 1Fh
20h to 2Fh
30h to 5Fh
TID
TMNR[3]
2000h
SNR
TID
TID
serial number
[1] HEX E280 6890 0000 nnnn nnnn nnnn
where n are the nibbles of the SNR from the TID
[2] Indicates the existence of a Configuration Word at the end of the EPC number
[3] See Figure 7
[4] Action bits: meant to trigger a feature upon a SELECT command on the related bit ref feature control
mechanism, seeSection 10.6.1
[5] Permanent bit: permanently stored bits in the memory; Read/Writeable according EPC bank lock status,
see Section 10.6.1
SL3S1204
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10.5.2 UCODE 7 TID memory details
Model Number
Mask
First 48 bit of TID
memory
Config
Word
Class ID
E2h
Designer
ID
Sub
Version
XTID
Header
Version Nr. (Silicon) Nr.
Indicator
UCODE 7
E28068902000
806h
1b
0001b
0010000b
2000h
Addresses 00h
5Fh
TID
MS Byte
MSBit LSBit
LS Byte
MSBit
LSBit
Bit
Address
00h
07h 08h
13h 14h
1Fh 20h
2Fh 30h
5Fh
Class Identifier
Mask-Designer Identifier
Model Number
XTID
Serial Number
11
15
Bits
7
0
11
0
0
0
47
0
E2h
806h
890h
2000h
000000000000h to FFFFFFFFFFFFh
(EAN.UCC)
(NXP; with XTID)
(UCODE 7)
(indication of 48bit
unique SNR)
Address 14h
Bits
18h 19h
1Fh
0
C.
W.
I.
Sub Version Number
Model Number
0
3
6
0
1b
0001b
0010000b
(UCODE 7)
aaa-005659
Fig 7. UCODE 7 TID memory structure
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UCODE 7
10.6 Supported features
The UCODE 7 is equipped with a number of additional features, which are implemented in
such a way that standard EPCglobal READ / WRITE / ACCESS / SELECT commands
can be used to operate these features.
The Configuration Word, as mentioned in the memory map, describes the additional
features located at address 200h of the EPC memory.
Bit 14h of the TID indicates the existence of a Configuration Word. This flag will enable the
selection of configuration word enhanced transponders in mixed tag populations.
Please refer to Ref. 22 for additional reference.
10.6.1 UCODE 7 features control mechanism
The different features of the UCODE 7 can be activated / de-activated by addressing or
changing the content of the corresponding bit in the configuration word located at address
200h in the EPC memory bank (see Table 10). The de-activation of the action bit features
will only happen after chip reset.
Table 10. Configuration word UCODE 7
Locked memory
Action bit
Locked memory Action bit
Locked memory
RFU
RFU
Parallel
encoding
RFU
Tag Power
Indicator
RFU
RFU
RFU
0
1
2
3
4
5
6
7
Table 11. Configuration word UCODE 7 ... continued
Locked Permanent
memory bit
Locked memory
Permanent
bit
RFU
max.
RFU
RFU
RFU
RFU
RFU
PSF Alarm bit
backscatter
strength
8
9
10
11
12
13
14
15
The configuration word contains 2 different type of bits:
• Action bits: meant to trigger a feature upon a SELECT command on the related bit:
Parallel encoding
Tag Power indicator
• Permanent bits: permanently stored bits in the memory
Max. Backscatter Strength
PSF Alarm bit
The activation or the de-activation of the feature behind the permanent bits happens only
when attempting to write a “1” value to the related bit (value toggling) - writing “0” value
will have no effect.
If the feature is activated, the related bit will be read with a “1” value and, if de-activated,
with a “0” value.
The permanent bits can only be toggled by using standard EPC WRITE (not a BlockWrite)
if the EPC bank is unlocked or within the SECURED state if the EPC is locked. If the EPC
is perma locked, they cannot be changed.
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UCODE 7
Action bits will trigger a certain action only if the pointer of the SELECT command exactly
matches the action-bit address (i.e. 202h or 204h), if the length=1 and if mask=1b
(no multiple trigger of actions possible within one single SELECT command).
After issuing a SELECT to any action bits an interrogator shall transmit CW for RTCal
Ref. 9 + 80 s before sending the next command.
If the truncate bit in the SELECT command is set to "1" the SELECT will be ignored.
A SELECT on action bits will not change the digital state of the chip.
The action bits can be triggered regardless if the EPC memory is unlocked, locked or
permalocked.
10.6.2 Backscatter strength reduction
The UCODE 7 features two levels of backscatter strengths. Per default maximum
backscatter is enabled in order to enable maximum read rates. When clearing the flag the
strength can be reduced if needed.
10.6.3 Pre-serialization of the 96-bit EPC
Description
The 96-bit EPC, which is the initial EPC length settings of UCODE7, will be delivered
pre-serialized with the 48-bit serial number from the TID.
Use cases and benefits
With a pre-serialized EPC, the encoding process of the tags with UCODE 7 gets simpler
and faster as it only needs to encode the SKU (58-bit header of the EPC).
10.6.4 Parallel encoding
Description
This feature of the UCODE 7 can be activated by the “Parallel encoding bit” in the
Configuration-Word located at (202h).
Upon issuing a EPC SELECT command on the “Parallel encoding bit”, in a population of
UCODE 7 tags, a subsequent QUERY brings all tags go the OPEN state with a specific
handle (“AAAAh”).
Once in the OPEN state, for example a WRITE command will apply to all tags in the
OPEN state (see Figure 9). This parallel encoding is considerably lowering the encoding
time compared to a standard implementation (see Figure 8).
The amount of tags that can be encoded at the same time will depend on the strength of
the reader signal. Since all tags will backscatter their ACKNOWLEDGE (ACK) response
at the same time, the reader will observe collision in the signal from the tags.
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QUERY/Adjust/Rep
QUERY/Adjust/Rep
READER
(16-bit)
(16-bit)
TAG 1
TAG 2
Tags
Only TAG 1 is being addressed
Only TAG 2 is being addressed
aaa-006843
Fig 8. Example of 16-bit Write command with standard EPC Gen 2 commands
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UCODE 7
SELECT on
Parallel
encoding bit
QUERY (Q=0)
(16-bit)
READER
TAG 1
TAG 2
Tags
TAG n
All UCODE 7 tags receive the Command
aaa-006844
Fig 9. Illustration of Parallel encoding for 16-bit Write command
Use cases and benefits
Parallel encoding feature of UCODE 7 can enable ultra fast bulk encoding.
Taking in addition advantage of the pre-serialization scheme of UCODE 7, the same SKU
can be encoded in multiple tags as the EPC will be delivered pre-serialized already.
In the case of only one tag answering (like in printer encoding), this feature could be used
to save some overhead in commands to do direct EPC encoding after the handle reply.
Since this is a UCODE 7 specific feature the use of this features requires support on the
reader side.
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UCODE 7
10.6.5 Tag Power Indicator
Description
Upon a SELECT command on the “Tag Power Indicator”, located in the config word 204h,
an internal power check on the chip is performed to see if the power level is sufficient to
perform a WRITE command. The decision level is defined as nominal WRITE sensitivity
minus 1dB. In the case there is enough power, the SELECT command is matching and
non-matching if not enough power. The tag can then be singulated by the standard
inventory procedure.
Use cases and benefits
This feature gives the possibility to select only the tag(s) that receive enough power to be
written during e.g. printer encoding in a dense environment of tags even though the
reader may read more than one tag (see Figure 10 for illustration). The power level still
needs to be adjusted to transmit enough writing power to one tag only to do one tag
singulation.
Power level for READ/WRITE
too low/too low
OK/too low
OK/too low
Only this tag will select itself
OK/OK
OK/too low
OK/too low
too low/too low
aaa-005662
Fig 10. Selection of tags with Tag Power Indicator feature
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UCODE 7
10.6.6 Product Status Flag (PSF)
Description
The PSF is a general purpose bit located in the Configuration word at address 20Fh with a
value that can be freely changed.
Use cases and benefits
The PSF bit can be used as an EAS (Electronic Article Surveillance) flag, quality checked
flag or similar.
In order to detect the tag with the PSF activated, a EPC SELECT command selecting the
PSF flag of the Configuration word can be used. In the following inventory round only PSF
enabled chips will reply their EPC number.
10.6.7 Single-slit antenna solution
Description
In UCODE 7 the test pads TP1 and TP2 are electrically disconnected meaning they are
not electrically active and can be safely short-circuited to the RF pads RF1 and RF2 (see
Figure 11).
Standard assembly
Single-slit assembly
Supporting pads
aaa-005857
Fig 11. Standard antenna design versus single-slit antenna
Uses cases and benefits
Using single-slit antenna enables easier assembly and antenna design. Inlay
manufacturer will only have to take care about one slit of the antenna instead of two in
case all pads need to be disconnected from each other.
Additionally single-slit antenna assembly and the related increased input capacitance (see
Table 13) can be used advantageously over the standard antenna design as additional
room for optimization to different antenna design.
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UCODE 7
11. Limiting values
Table 12. Limiting values[1][2]
In accordance with the Absolute Maximum Rating System (IEC 60134).
Voltages are referenced to RFN
Symbol
Parameter
Conditions
Min
Max
Unit
Bare die limitations
Tstg
storage temperature
55
40
-
+125
+85
± 2
C
C
kV
Tamb
VESD
ambient temperature
[3]
electrostatic discharge
voltage
Human body model
Pad limitations
Pi input power
maximum power
-
100
mW
dissipation, RFP pad
[1] Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any conditions other
than those described in the Operating Conditions and Electrical Characteristics section of this specification
is not implied.
[2] This product includes circuitry specifically designed for the protection of its internal devices from the
damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be
taken to avoid applying greater than the rated maxima.
[3] For ESD measurement, the die chip has been mounted into a CDIP20 package.
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UCODE 7
12. Characteristics
12.1 UCODE 7 bare die characteristics
Table 13. UCODE 7 RF interface characteristics (RF1, RF2)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fi
input frequency
840
-
960
MHz
[1][3][8]
[2]
Pi(min)
Pi(min)
t 16bit
minimum input power
minimum input power
Encoding speed
READ sensitivity
WRITE sensitivity
16-bit
-
-
-
-
-
-
-
-
-
-
21
-16
1
-
-
-
-
-
dBm
dBm
ms
ms
pF
[5]
[5]
32-bit (block write)
parallel
1.8
0.63
[3][4]
[3][4]
[3][4]
[3][4]
[6]
Ci
Z
Chip input capacitance
Chip impedance
866 MHz
14.5-j293 -
12.5-j277 -
12.5-j267 -
18-j245
915 MHz
953 MHz
Z
Z
Typical assembled impedance [9]
Typical assembled impedance [9] in 915MHz
case of single-slit antenna assembly
915MHz
[6][7]
13.5-j195 -
[3][4]
[3][4]
[3][4]
[3][4]
Ci
Z
Chip input capacitance, Large Pads parallel
-
-
-
-
0.68
-
pF
Chip impedance, Large Pads
866 MHz
915 MHz
953 MHz
12.6-j267 -
11.8-j254
11.5-j244
-
-
Tag Power Indicator mode
Pi(min) minimum input power level to be
able to select the tag
[2]
-
-15
-
dBm
[1] Power to process a QUERY command
[2] Tag sensitivity on a 2dBi gain antenna
[3] Measured with a 50 source impedance directly on the chip
[4] At minimum operating power
[5] When the memory content is “0000...”.
[6] The antenna shall be matched to this impedance
[7] Depending on the specific assembly process, sensitivity losses of few tenths of dB might occur
[8] Results in approximately -21,5dBm tag sensitivity with a 2dBi gain antenna
[9] Assuming a 80fF additional input capacitance, 250fF in case of single slit antenna
Table 14. UCODE 7 memory characteristics
Symbol
Parameter
Conditions
Min
Typ
Max Unit
EEPROM characteristics
tret
retention time
Tamb 55 C
20
-
-
-
-
year
Nendu(W)
write endurance
100k
cycle
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UCODE 7
12.2 UCODE 7 SOT886 characteristics
Table 15. UCODE 7 RF interface characteristics (RF1, RF1)
Symbol Parameter
Pi(min) minimum input power
Conditions
Min
Typ
Max Unit
[1][2]
[3]
READ
sensitivity
-
21
-
dBm
Z
impedance
915 MHz
-
12.8 -j248
-
[1] Power to process a Query command.
[2] Measured with a 50 source impedance.
[3] At minimum operating power.
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UCODE 7
13. Package outline
XSON6: plastic, extremely thin small outline package; no leads;
6 terminals; body 1.0 x 1.45 x 0.5 mm
SOT886-1
X
A
A
1
D
B
A
E
detail X
terminal 1
index area
terminal 1
e
C
y
1
index area
v
w
C A
C
B
y
b
C
1
L
2
1
6
3
L
1
e
L
4
0
2 mm
scale
Dimensions (mm are the original dimensions)
Unit
A
A
1
b
D
E
e
e
L
L
L
v
w
y
y
1
1
1
2
max 0.50 0.05 0.25 1.50 1.05
0.35 0.40 0.10
0.20 1.45 1.00 0.6 1.0 0.30 0.35 0.05 0.10 0.05 0.05 0.05
0.00 0.17 1.40 0.95 0.27 0.32 0.02
mm nom
min
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
sot886-1_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
13-07-03
13-07-10
SOT886-1
Fig 12. Package outline SOT886
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UCODE 7
14. Packing information
14.1 Wafer
See Ref. 21 “Data sheet - Delivery type description – General specification for 8” wafer on
UV-tape with electronic fail die marking, BU-S&C document number: 1093**”
See Ref. 23 “Data sheet - Delivery type description – General specification for 12” wafer
on UV-tape with electronic fail die marking, BU-S&C document number: 1862**”
14.2 SOT886
See: www.nxp.com/packages/SOT886.html
15. Abbreviations
Table 16. Abbreviations
Acronym
CRC
Description
Cyclic Redundancy Check
CW
Continuous Wave
DSB-ASK
DC
Double Side Band-Amplitude Shift Keying
Direct Current
EAS
Electronic Article Surveillance
Electrically Erasable Programmable Read Only Memory
EEPROM
EPC
Electronic Product Code (containing Header, Domain Manager, Object Class
and Serial Number)
FM0
G2
Bi phase space modulation
Generation 2
IC
Integrated Circuit
PIE
PSF
RF
Pulse Interval Encoding
Product Status Flag
Radio Frequency
UHF
SECS
TID
Ultra High Frequency
Semi Equipment Communication Standard
Tag IDentifier
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UCODE 7
16. References
[1] EPCglobal: EPC Radio-Frequency Identity Protocols Class-1 Generation-2 UHF
RFID Protocol for Communications at 860 MHz – 960 MHz, Version 1.1.0
(December 17, 2005)
[2] EPCglobal: EPC Tag Data Standards
[3] EPCglobal (2004): FMCG RFID Physical Requirements Document (draft)
[4] EPCglobal (2004): Class-1 Generation-2 UHF RFID Implementation Reference
(draft)
[5] European Telecommunications Standards Institute (ETSI), EN 302 208:
Electromagnetic compatibility and radio spectrum matters (ERM) – Radio-frequency
identification equipment operating in the band 865 MHz to 868 MHz with power
levels up to 2 W, Part 1 – Technical characteristics and test methods
[6] European Telecommunications Standards Institute (ETSI), EN 302 208:
Electromagnetic compatibility and radio spectrum matters (ERM) – Radio-frequency
identification equipment operating in the band 865 MHz to 868 MHz with power
levels up to 2 W, Part 2 – Harmonized EN under article 3.2 of the R&TTE directive
[7] [CEPT1]: CEPT REC 70-03 Annex 1
[8] [ETSI1]: ETSI EN 330 220-1, 2
[9] RTCal is the Interrogator-to-Tag calibration symbol length defined in the EPCglobal
specification
[10] [ETSI3]: ETSI EN 302 208-1, 2 V<1.1.1> (2004-09-Electromagnetic compatibility
And Radio spectrum Matters (ERM) Radio Frequency Identification Equipment
operating in the band 865 - MHz to 868 MHz with power levels up to 2 W Part 1:
Technical characteristics and test methods.
[11] [FCC1]: FCC 47 Part 15 Section 247
[12] ISO/IEC Directives, Part 2: Rules for the structure and drafting of International
Standards
[13] ISO/IEC 3309: Information technology – Telecommunications and information
exchange between systems – High-level data link control (HDLC) procedures –
Frame structure
[14] ISO/IEC 15961: Information technology, Automatic identification and data capture –
Radio frequency identification (RFID) for item management – Data protocol:
application interface
[15] ISO/IEC 15962: Information technology, Automatic identification and data capture
techniques – Radio frequency identification (RFID) for item management – Data
protocol: data encoding rules and logical memory functions
[16] ISO/IEC 15963: Information technology — Radio frequency identification for item
management — Unique identification for RF tags
[17] ISO/IEC 18000-1: Information technology — Radio frequency identification for item
management — Part 1: Reference architecture and definition of parameters to be
standardized
[18] ISO/IEC 18000-6: Information technology automatic identification and data capture
techniques — Radio frequency identification for item management air interface —
Part 6: Parameters for air interface communications at 860–960 MHz
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UCODE 7
[19] ISO/IEC 19762: Information technology AIDC techniques – Harmonized vocabulary
– Part 3: radio-frequency identification (RFID)
[20] U.S. Code of Federal Regulations (CFR), Title 47, Chapter I, Part 15:
Radio-frequency devices, U.S. Federal Communications Commission.
[21] Data sheet - Delivery type description – General specification for 8” wafer on
UV-tape with electronic fail die marking, BU-S&C document number: 1093**1
[22] Application note - AN11274 – FAQ on UCODE 7
[23] Data sheet - Delivery type description – General specification for 12” wafer on
UV-tape with electronic fail die marking, BU-S&C document number: 1862**
1. ** ... document version number
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17. Revision history
Table 17. Revision history
Document ID
SL3S1204 v. 3.9
Modifications:
Release date
20170321
Data sheet status
Change notice Supersedes
- SL3S1204 v. 3.8
Product data sheet
• Introduction of Large Pads
• Table 1 “Ordering information” :updated
• Section 8.2 “Wafer layout 8 inch with large pads”: added
• Section 9.1.2 “8 inch Wafer, Large pads”: added
• Table 13 “UCODE 7 RF interface characteristics (RF1, RF2)”: updated
SL3S1204 v. 3.8
Modifications:
20161011
Product data sheet
-
SL3S1204 v. 3.7
• Figure 7 “UCODE 7 TID memory structure”: updated
• Figure 12 “Package outline SOT886”: updated
• Editorial changes
SL3S1204 v. 3.7
Modifications:
20160718
• Update Automatic Pre-serialization functionality
• Figure 7 “UCODE 7 TID memory structure” - change of TID
20160524 Product data sheet
Product data sheet
-
SL3S1204 v. 3.6
SL3S1204 v. 3.5
SL3S1204 v. 3.6
Modifications:
-
• Introduction of 12 inch wafer delivery
• Section 8.3 “Wafer layout 12 inch”: added
• Section 9.1.3 “12 inch Wafer”: added
• Section 14.2 “SOT886”: added
• Table 15 “UCODE 7 RF interface characteristics (RF1, RF1)”: impedance value added
SL3S1204 v. 3.5
Modifications:
SL3S1204 v. 3.4
Modifications:
20150706
Product data sheet
-
SL3S1204 v. 3.4
• SOT886 package added
20141017
Product data sheet
-
SL3S1204 v. 3.3
• Table 9 “UCODE 7 overall memory map”: corrected
• Editorial changes
SL3S1204 v. 3.3
Modifications:
SL3S1204 v. 3.2
Modifications:
SL3S1204 v. 3.1
Modifications:
241330
20131217
Product data sheet
-
SL3S1204 v. 3.2
• Figure 7 “Automatic self pre-serialization scheme for 96-bit EPC”: corrected
20131120 Product data sheet SL3S1204 v. 3.1
• Security level changed from “COMPANY PROPRIETARY” to “COMPANY PUBLIC”
20130603 Product data sheet 241330
• Security level changed from “COMPANY CONFIDENTIAL” to “COMPANY PROPRIETARY”
-
-
20130522
Product data sheet
-
241312
Modifications
• Editorial changes
• Figure 4 “UCODE 7 8 inch wafer layout”: updated
• Table 9 “UCODE 7 overall memory map”: updated
• Table 10 “Configuration word UCODE 7”: updated
• Table 13 “UCODE 7 RF interface characteristics (RF1, RF2)”: updated
241312
20130422
Objective data sheet
241311
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UCODE 7
Table 17. Revision history …continued
Document ID
Release date
Data sheet status
Change notice Supersedes
Modifications
• Editorial changes
• Figure 7 “UCODE 7 TID memory structure”: updated
• Figure 7 “Automatic self pre-serialization scheme for 96-bit EPC”: updated
• Figure 10 “Selection of tags with Tag Power Indicator feature”: updated
• Figure 11 “Standard antenna design versus single-slit antenna”: updated
241311
20130325
Objective data sheet
241310
Modifications
241310
General Update
20130226
Objective data sheet
-
-
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18. Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
18.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
18.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
SL3S1204
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.9 — 21 March 2017
241339
32 of 34
SL3S1204
NXP Semiconductors
UCODE 7
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
18.4 Trademarks
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
UCODE — is a trademark of NXP Semiconductors N.V.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
SL3S1204
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.9 — 21 March 2017
241339
33 of 34
SL3S1204
NXP Semiconductors
UCODE 7
20. Contents
1
General description. . . . . . . . . . . . . . . . . . . . . . 1
Use cases and benefits . . . . . . . . . . . . . . . . . . 21
Tag Power Indicator . . . . . . . . . . . . . . . . . . . . 22
Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Use cases and benefits . . . . . . . . . . . . . . . . . . 22
Product Status Flag (PSF) . . . . . . . . . . . . . . 23
Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Use cases and benefits . . . . . . . . . . . . . . . . . . 23
Single-slit antenna solution . . . . . . . . . . . . . . 23
Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Uses cases and benefits . . . . . . . . . . . . . . . . . 23
10.6.5
10.6.6
10.6.7
2
2.1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Key benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
End user benefit . . . . . . . . . . . . . . . . . . . . . . . . 2
Antenna design benefits . . . . . . . . . . . . . . . . . . 2
Label manufacturer benefit. . . . . . . . . . . . . . . . 2
Supported features. . . . . . . . . . . . . . . . . . . . . . 2
2.1.1
2.2
2.2.1
2.2.2
2.2.3
2.3
3
3.1
3.2
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Markets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
11
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 24
12
12.1
12.2
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 25
UCODE 7 bare die characteristics. . . . . . . . . 25
UCODE 7 SOT886 characteristics. . . . . . . . . 26
4
Ordering information. . . . . . . . . . . . . . . . . . . . . 3
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pinning information. . . . . . . . . . . . . . . . . . . . . . 6
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
5
13
Package outline. . . . . . . . . . . . . . . . . . . . . . . . 27
6
14
14.1
14.2
Packing information . . . . . . . . . . . . . . . . . . . . 28
Wafer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
SOT886 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7
7.1
8
Wafer layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Wafer layout 8 inch. . . . . . . . . . . . . . . . . . . . . . 7
Wafer layout 8 inch with large pads . . . . . . . . . 8
Wafer layout 12 inch. . . . . . . . . . . . . . . . . . . . . 9
15
16
17
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 28
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Revision history . . . . . . . . . . . . . . . . . . . . . . . 31
8.1
8.2
8.3
18
Legal information . . . . . . . . . . . . . . . . . . . . . . 33
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 33
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9
9.1
9.1.1
9.1.2
9.1.3
9.1.4
9.1.5
Mechanical specification . . . . . . . . . . . . . . . . 10
Wafer specification . . . . . . . . . . . . . . . . . . . . . 10
8 inch Wafer, Standard bumps . . . . . . . . . . . . 10
8 inch Wafer, Large pads . . . . . . . . . . . . . . . . 11
12 inch Wafer . . . . . . . . . . . . . . . . . . . . . . . . . 12
Fail die identification . . . . . . . . . . . . . . . . . . . 13
Map file distribution. . . . . . . . . . . . . . . . . . . . . 13
18.1
18.2
18.3
18.4
19
20
Contact information . . . . . . . . . . . . . . . . . . . . 34
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10
10.1
10.2
10.3
10.3.1
10.3.2
10.4
Functional description . . . . . . . . . . . . . . . . . . 14
Air interface standards . . . . . . . . . . . . . . . . . . 14
Power transfer . . . . . . . . . . . . . . . . . . . . . . . . 14
Data transfer. . . . . . . . . . . . . . . . . . . . . . . . . . 14
Interrogator to tag Link . . . . . . . . . . . . . . . . . . 14
Tag to interrogator Link. . . . . . . . . . . . . . . . . . 14
Supported commands . . . . . . . . . . . . . . . . . . 15
UCODE 7 memory . . . . . . . . . . . . . . . . . . . . . 15
UCODE 7 overall memory map . . . . . . . . . . . 16
UCODE 7 TID memory details . . . . . . . . . . . . 17
Supported features. . . . . . . . . . . . . . . . . . . . . 18
UCODE 7 features control mechanism. . . . . . 18
Backscatter strength reduction. . . . . . . . . . . . 19
Pre-serialization of the 96-bit EPC . . . . . . . . . 19
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Use cases and benefits . . . . . . . . . . . . . . . . . .19
Parallel encoding . . . . . . . . . . . . . . . . . . . . . . 19
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
10.5
10.5.1
10.5.2
10.6
10.6.1
10.6.2
10.6.3
10.6.4
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2017.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 21 March 2017
241339
相关型号:
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