SPC5516EACMG48 [NXP]
32-BIT, FLASH, 66MHz, MICROCONTROLLER, PBGA208, 17 X 17 MM, 0.80 HEIGHT, 1 MM PITCH, MAPBGA-208;
| 型号： | SPC5516EACMG48 |
| 厂家： | 
NXP |
| 描述： | 32-BIT, FLASH, 66MHz, MICROCONTROLLER, PBGA208, 17 X 17 MM, 0.80 HEIGHT, 1 MM PITCH, MAPBGA-208 时钟 微控制器 外围集成电路 |
| 文件： | 总54页 (文件大小：616K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MPC5510
Rev. 4, 7/2014
MPC5510
LQFP–144
MAPBGA–208
20 mm x 20 mm
17mmx17mm
LQFP–176
24 mm x 24 mm
MPC5510 Microcontroller
Family Data Sheet
MPC5510 Family Features
• Up to 144 configurable general purpose pins supporting
input and output operations and 3.0V through 5.5V supply
levels
• Real-time counter (RTC_API) with clock source from
external 32-kHz crystal oscillator, internal 32-kHz or
16-MHz oscillator and supporting wake-up with selectable
1-second resolution and > 1-hour timeout, or 1-millisecond
resolution with maximum timeout of one second
• Up to eight periodic interrupt timers (PIT) with 32-bit
counter resolution
• Single issue, 32-bit CPU core complex (e200z1)
– Compliant with the Power Architecture™ embedded
category
– Includes an instruction set enhancement allowing
variable length encoding (VLE) for code size footprint
reduction. With the optional encoding of mixed 16-bit
and 32-bit instructions, it is possible to achieve
significant code size footprint reduction.
• Up to 1.5-Mbyte on-chip flash with flash control unit
(FCU)
• Up to 80 Kbytes on-chip SRAM
• Nexus development interface (NDI) per IEEE-ISTO
5001-2003 Class Two Plus standard
• Device/board test support per Joint Test Action Group
(JTAG) of IEEE (IEEE 1149.1)
• On-chip voltage regulator (VREG) for regulation of 5V
input to 1.5V and 3.3V internal supply levels
• Optional e200z0, second Power Architecture based I/O
processor with VLE instruction set
• Memory protection unit (MPU) with up to sixteen region
descriptors and 32-byte region granularity
• Interrupt controller (INTC) capable of handling
selectable-priority interrupt sources
• Frequency modulated Phase-locked loop (FMPLL)
• Crossbar switch architecture for concurrent access to
peripherals, flash, or RAM from multiple bus masters
• 16-channel enhanced direct memory access controller
(eDMA)
• Optional FlexRAY controller
• Optional external bus interface (EBI) module
• Boot assist module (BAM) supports internal flash
programming via a serial link (CAN or SCI)
• Timer supports input/output channels providing a range of
16-bit input capture, output compare, and pulse width
modulation functions (eMIOS200)
• Up to 40-channel 12-bit analog-to-digital converter (ADC)
• Up to four serial peripheral interface (DSPI) modules
• Media Local Bus (MLB) emulation logic (works with two
DSPIs, the e200z0, the eDMA, and system RAM to create
a 3-pin or 5-pin 256Fs MLB protocol)
• Up to eight serial communication interface (eSCI) modules
• Up to six enhanced full CAN (FlexCAN) modules with
configurable buffers
2
• One inter IC communication interface (I C) module
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2007-2014. All rights reserved.
Table of Contents
1
2
Pin Assignments and Reset States . . . . . . . . . . . . . . . . . . . . .4
Table 13. 5V Low Frequency (32 kHz) Internal RC Oscillator . . . 32
Table 14. FMPLL Electrical Specifications . . . . . . . . . . . . . . . . . 33
Table 15. eQADC Conversion Specifications (Operating) . . . . . . 34
Table 16. Flash Program and Erase Specifications . . . . . . . . . . . 35
Table 17. Flash EEPROM Module Life (Full Temperature Range) 35
Table 18. Pad AC Specifications (VDDE = 3.0V - 5.5V) . . . . . . . 36
Table 19. Reset and Boot Configuration Timing . . . . . . . . . . . . . 37
Table 20. IRQ/NMI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 21. JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 22. Nexus Debug Port Timing . . . . . . . . . . . . . . . . . . . . . . 41
Table 23. External Bus Operation Timing . . . . . . . . . . . . . . . . . . 43
Table 24. eMIOS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 25. DSPI Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 26. Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 27. Revision History of MPC5510 Data Sheet . . . . . . . . . . 53
1.1 Signal Properties and Multiplexing Summary . . . . . . . . .4
1.2 Power and Ground Supply Summary . . . . . . . . . . . . . .15
1.3 Pinout – 144 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
1.4 Pinout – 176 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
1.5 Pinout – 208 PBGA. . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .21
2.2.1 General Notes for Specifications at Maximum
Junction Temperature . . . . . . . . . . . . . . . . . . . .21
2.3 ESD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .24
2.4 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .25
2.5 Operating Current Specifications
. . . . . . . . . . . . . .27
2.6 I/O Pad Current Specifications . . . . . . . . . . . . . . . . . . .29
2.7 Low Voltage Characteristics . . . . . . . . . . . . . . . . . . . . .30
2.8 Oscillators Electrical Characteristics. . . . . . . . . . . . . . .31
2.9 FMPLL Electrical Characteristics . . . . . . . . . . . . . . . . .33
2.10 eQADC Electrical Characteristics . . . . . . . . . . . . . . . . .34
2.11 Flash Memory Electrical Characteristics. . . . . . . . . . . .35
2.12 Pad AC Specifications. . . . . . . . . . . . . . . . . . . . . . . . . .36
2.13 AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
2.13.1 Reset and Boot Configuration Pins . . . . . . . . . .37
2.13.2 External Interrupt (IRQ) and Non-Maskable
List of Figures
Figure 1. MPC5510 Family Block Diagram . . . . . . . . . . . . . . . . . . 3
Figure 2. MPC5510 Pinout – 144 LQFP . . . . . . . . . . . . . . . . . . . 17
Figure 3. MPC5510 Pinout – 176 LQFP . . . . . . . . . . . . . . . . . . . 18
Figure 4. MPC5510 Pinout – 208 PBGA . . . . . . . . . . . . . . . . . . . 19
Figure 5. Pad Output Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 6. Reset and Boot Configuration Timing. . . . . . . . . . . . . . 37
Figure 7. IRQ and NMI Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 8. JTAG Test Clock Input Timing. . . . . . . . . . . . . . . . . . . . 38
Figure 9. JTAG Test Access Port Timing . . . . . . . . . . . . . . . . . . . 39
Figure 10. JTAG JCOMP Timing . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 11. JTAG Boundary Scan Timing . . . . . . . . . . . . . . . . . . . 40
Figure 12. Nexus Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 13. Nexus TDI, TMS, TDO Timing . . . . . . . . . . . . . . . . . . 42
Figure 14. CLKOUT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 15. Synchronous Output Timing. . . . . . . . . . . . . . . . . . . . 44
Figure 16. Synchronous Input Timing . . . . . . . . . . . . . . . . . . . . . 45
Figure 17. Address Latch Enable (ALE) Timing . . . . . . . . . . . . . 46
Figure 18. DSPI Classic SPI Timing — Master, CPHA = 0 . . . . . 48
Figure 19. DSPI Classic SPI Timing — Master, CPHA = 1 . . . . . 48
Figure 20. DSPI Classic SPI Timing — Slave, CPHA = 0 . . . . . . 49
Figure 21. DSPI Classic SPI Timing — Slave, CPHA = 1 . . . . . . 49
Figure 22. DSPI Modified Transfer Format Timing — Master,
CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Interrupt (NMI) Pins . . . . . . . . . . . . . . . . . . . . .37
2.13.3 JTAG (IEEE 1149.1) Interface . . . . . . . . . . . . . .38
2.13.4 Nexus Debug Interface . . . . . . . . . . . . . . . . . . .41
2.13.5 External Bus Interface (EBI) . . . . . . . . . . . . . . .43
2.13.6 Enhanced Modular I/O Subsystem (eMIOS) . . .46
2.13.7 Deserial Serial Peripheral Interface (DSPI) . . . .47
Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
4.1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
3
4
List of Tables
Table 1. MPC5510 Signal Properties . . . . . . . . . . . . . . . . . . . . . . .4
Table 2. MPC5510 Power/Ground . . . . . . . . . . . . . . . . . . . . . . . .15
Table 3. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . .20
Table 4. Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 5. ESD Ratings, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 6. DC Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . .25
Table 7. Operating Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Table 8. I/O Pad Average DC Current . . . . . . . . . . . . . . . . . . . . . .29
Table 9. Low Voltage Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 10. 3.3V High Frequency External Oscillator. . . . . . . . . . . .31
Table 11. 5V Low Frequency (32 kHz) External Oscillator . . . . . .31
Table 12. 5V High Frequency (16 MHz) Internal RC Oscillator. . .32
Figure 23. DSPI Modified Transfer Format Timing — Master,
CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 24. DSPI Modified Transfer Format Timing — Slave, CPHA = 0
51
Figure 25. DSPI Modified Transfer Format Timing — Slave, CPHA = 1
51
Figure 26. DSPI PCS Strobe (PCSS) Timing . . . . . . . . . . . . . . . 51
MPC5510 Microcontroller Family Data Sheet, Rev. 4
2
Freescale Semiconductor
Oscillators
FMPLL
VREG
MPC5510
e200z1 Core
General Purpose
Registers
Integer
Execution
Unit
(32 x 32-bit)
e200z0 Core
General Purpose
Registers
INTC
Integer
Execution
Unit
(32 x 32-bit)
Timers
JTAG
NDI
Multiply
Unit
Branch
Unit
Multiply
Unit
Branch
Unit
Instruction
Unit
PPC & VLE
Load/Store
Unit
Instruction
Unit
Load/Store
Unit
FlexRay
eDMA
VLE
Instruction Bus
Data Bus
Crossbar Switch (XBAR)
Private
Instruction
Bus
Memory Protection Unit (MPU)
Peripheral Bridge
RAM
Controller
FCU
EBI
eSCI
ADC
DSPI
I2C
FlexCAN
BAM
SRAM
(ECC)
Flash
(ECC)
eMIOS200
SIU
PIT
MLB
LEGEND
ADC
BAM
EBI
ECC
DSPI
eDMA
– Analog to Digital Converter modules
– Boot Assist Module
– External Bus Interface module
– Error Correction Code
– Serial Peripherals Interface controller module JTAG – Joint Test Action Group interface
– enhanced Direct Memory Controller module MLB
FlexRay – Dual Channel FlexRay controller
FMPLL – Frequency Modulated Phase Locked Loop module
I2C
INTC
– Inter IC Controller modules
– Interrupt Controller module
– Media Local Bus emulation logic
– Nexus Debug Interface module
– Periodic Interrupt Timer module
– System Integration module
eMIOS200 – Timed Input Output module
eSCI
FCU
NDI
PIT
SIU
– Serial Communications Interface modules
– Flash Controller Unit
FlexCAN – Controller Area Network controller modules
VREG – Voltage Regulator
Figure 1. MPC5510 Family Block Diagram
MPC5510 Microcontroller Family Data Sheet, Rev. 4
Freescale Semiconductor
3
Pin Assignments and Reset States
1
Pin Assignments and Reset States
1.1
Signal Properties and Multiplexing Summary
Table 1 shows the signal properties for each pin on the MPC5510. For all port pins, which have an associated pad configuration
register (SIU_PCRn register) to control its pin properties, the “Supported Pin Functions” column lists the functions associated
with the programming of the SIU_PCRn[PA] bit field in the following order: GPIO, Function1, Function2 and Function3. If
fewer than three functions plus GPIO are supported by a given pin, then the unused functions begin with Function3, then
Function2, then Function1. Note that the GPIO number is the same number as the corresponding pad configuration register
(SIU_PCRn) number.
Table 1. MPC5510 Signal Properties
Package Pin
Locations
GPIO
(PCR)
Num1
Status
During
Reset5
Status
After
Pin
Name
Supported
Functions2
I/O
Type
Pad4
Type
Description
Voltage3
Reset5
144 176 208
Port A (16)
PA0
AN0
GPI
I
I
PA0
PA1
0
1
VDDA
VDDA
VDDA
VDDA
VDDA
VDDA
VDDA
VDDA
VDDA
VDDA
VDDA
VDDA
VDDA
VDDA
AE + IH
AE + IH
AE + IH
AE + IH
AE + IH
AE + IH
AE + IH
AE + IH
AE + IH
AE + IH
AE + IH
AE + IH
AE + IH
AE + IH
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
9
8
7
6
5
4
3
2
9
8
7
6
5
4
3
2
E3
E2
E1
D3
D2
D1
C2
C1
eQADC Analog Input
PA1
AN1
GPI
I
I
eQADC Analog Input
PA2
AN2
GPI
I
I
PA2
2
eQADC Analog Input
PA3
AN3
GPI
I
I
PA3
3
eQADC Analog Input
PA4
AN4
GPI
I
I
PA4
4
eQADC Analog Input
PA5
AN5
GPI
I
I
PA5
5
eQADC Analog Input
PA6
AN6
GPI
I
I
PA6
6
eQADC Analog Input
PA7
AN7
GPI
I
I
PA7
7
eQADC Analog Input
PA8
AN8/ANW
GPI
I
I
PA8
8
143 175 A3
142 174 C4
140 172 D5
139 171 C5
138 170 B5
137 169 A5
eQADC Analog Input
PA9
AN9/ANX
GPI
I
I
PA9
9
eQADC Analog Input
PA10
AN10/ANY
GPI
I
I
PA10
PA11
PA12
PA13
10
11
12
13
eQADC Analog Input
PA11
AN11/ANZ
GPI
I
I
eQADC Analog Input
PA12
AN12
GPI
I
I
eQADC Analog Input
PA13
AN13
GPI
I
I
eQADC Analog Input
PA14
AN14
GPI
I
I
I
PA14
14
eQADC Analog Input
32 kHz Crystal Oscillator Input
VDDA
AE + IH
—
—
136 167 D6
EXTAL326
MPC5510 Microcontroller Family Data Sheet, Rev. 4
4
Freescale Semiconductor
Pin Assignments and Reset States
Table 1. MPC5510 Signal Properties (continued)
Package Pin
Locations
GPIO
(PCR)
Num1
Status
During
Reset5
Status
After
Pin
Name
Supported
Functions2
I/O
Type
Pad4
Type
Description
Voltage3
Reset5
144 176 208
PA15
AN15
GPI
I
I
O
PA15
15
eQADC Analog Input
32 kHz Crystal Oscillator Output
VDDA
AE + IH
—
—
135 165 C6
XTAL326
Port B (16)
PB0
AN28
eMIOS16
PCS_C5
GPIO
I/O
I
O
O
eQADC Analog Input7
eMIOS Channel
PB0
PB1
PB2
16
17
18
VDDE1
VDDE1
VDDE1
A + SH
A + SH
A + SH
—
—
—
—
—
—
134 162 C7
133 161 D7
132 160 A8
DSPI_C Peripheral Chip Select
PB1
AN29
eMIOS17
PCS_C4
GPIO
I/O
I
O
O
eQADC Analog Input7
eMIOS Channel
DSPI_C Peripheral Chip Select
PB2
AN30
eMIOS18
PCS_C3
GPIO
I/O
I
O
O
eQADC Analog Input7
eMIOS Channel
DSPI_C Peripheral Chip Select
PB3
AN31
PCS_C2
GPIO
I/O
I
O
PB3
PB4
PB5
PB6
PB7
PB8
19
20
21
22
23
24
eQADC Analog Input7
DSPI_C Peripheral Chip Select
VDDE1
VDDE1
VDDE1
VDDE1
VDDE1
VDDE1
A + SH
A + SH
A + SH
A + SH
A + SH
A + SH
—
—
—
—
—
—
—
—
—
—
—
—
131 159 B8
130 158 C8
129 157 D8
128 156 A9
127 153 B9
126 152 C9
PB4
AN32
PCS_C1
GPIO
I/O
I
O
eQADC Analog Input7
DSPI_C Peripheral Chip Select
PB5
AN33
PCS_C0
GPIO
I/O
I
I/O
eQADC Analog Input7
DSPI_C Peripheral Chip Select
PB6
AN34
SCK_C
GPIO
I/O
I
I/O
eQADC Analog Input7
DSPI_C Clock
PB7
AN35
SOUT_C
GPIO
I/O
I
O
eQADC Analog Input7
DSPI_C Data Output
PB8
AN36
SIN_C
GPIO
I/O
I
I
eQADC Analog Input7
DSPI_C Data Input
PB9
AN37
CNTX_D
PCS_B4
GPIO
I/O
I
O
O
eQADC Analog Input7
CAN_D Transmit
PB9
PB10
PB11
25
26
27
VDDE1
VDDE1
VDDE1
A + SH
A + SH
A + SH
—
—
—
—
—
—
125 151 D9
124 150 A10
123 149 B10
DSPI_B Peripheral Chip Select
PB10
AN38
CNRX_D
PCS_B3
GPIO
I/O
I
I
eQADC Analog Input7
CAN_D Receive
DSPI_B Peripheral Chip Select
O
PB11
AN39
eMIOS19
PCS_B5
GPIO
I/O
I
O
O
eQADC Analog Input7
eMIOS Channel
DSPI_B Peripheral Chip Select
MPC5510 Microcontroller Family Data Sheet, Rev. 4
Freescale Semiconductor
5
Pin Assignments and Reset States
Table 1. MPC5510 Signal Properties (continued)
Package Pin
Locations
GPIO
(PCR)
Num1
Status
During
Reset5
Status
After
Pin
Name
Supported
Functions2
I/O
Type
Pad4
Type
Description
Voltage3
Reset5
144 176 208
PB12
TXD_G
PCS_B4
GPIO
SCI_G Transmit
DSPI_B Peripheral Chip Select
I/O
O
O
PB12
PB13
28
29
VDDE1
SH
SH
—
—
—
—
—
—
164 A7
163 B7
PB13
RXD_G
PCS_B3
GPIO
SCI_G Receive
DSPI_B Peripheral Chip Select
I/O
I
O
VDDE1
PB14
TXD_H
GPIO
SCI_H Transmit
I/O
O
PB14
PB15
30
31
VDDE1
SH
SH
—
—
—
—
—
—
148 C10
147 A11
PB15
RXD_H
GPIO
SCI_H Receive
I/O
I
VDDE1
Port C (16)
PC0
eMIOS0
FR_A_TX_EN
AD24
GPIO
eMIOS Channel
FlexRay Channel A Transmit Enable
EBI Muxed Address/Data
I/O
I/O
O
PC0
PC1
PC2
32
33
34
VDDE1
VDDE1
VDDE1
MH
MH
MH
—
—
—
—
—
—
122 146 B11
121 145 C11
120 144 D11
I/O
PC1
eMIOS1
FR_A_TX
AD16
GPIO
eMIOS Channel
FlexRay Channel A Transmit
EBI Muxed Address/Data
I/O
I/O
O
I/O
PC2
eMIOS2
FR_A_RX
TS
GPIO
eMIOS Channel
FlexRay Channel A Receive
EBI Transfer Start
I/O
I/O
I
I/O
PC3
eMIOS3
FR_DBG0
GPIO
eMIOS Channel
FlexRay Debug
I/O
I/O
O
PC3
PC4
PC5
PC6
PC7
35
36
37
38
39
VDDE1
VDDE1
VDDE1
VDDE1
VDDE1
MH
SH
SH
SH
SH
—
—
—
—
—
—
—
—
—
—
117 141 A12
116 140 B12
115 139 C12
114 138 D12
113 137 A13
PC4
eMIOS4
FR_DBG1
GPIO
eMIOS Channel
FlexRay Debug
I/O
I/O
O
PC5
eMIOS5
FR_DBG2
GPIO
eMIOS Channel
FlexRay Debug
I/O
I/O
O
PC6
eMIOS6
FR_DBG3
GPIO
eMIOS Channel
FlexRay Debug
I/O
I/O
O
PC7
eMIOS7
FR_B_RX
GPIO
eMIOS Channel
FlexRay Channel B Receive
I/O
I/O
I
PC8
eMIOS8
FR_B_TX
AD15
GPIO
eMIOS Channel
FlexRay Channel B Transmit
EBI Muxed Address/Data
I/O
I/O
O
PC8
PC9
40
41
VDDE1
MH
MH
—
—
—
—
112 136 B13
111 135 C13
I/O
PC9
eMIOS9
FR_B_TX_EN
AD14
GPIO
eMIOS Channel
FlexRay Channel B Transmit Enable
EBI Muxed Address/Data
I/O
I/O
O
VDDE1
I/O
MPC5510 Microcontroller Family Data Sheet, Rev. 4
6
Freescale Semiconductor
Pin Assignments and Reset States
Table 1. MPC5510 Signal Properties (continued)
Package Pin
Locations
GPIO
(PCR)
Num1
Status
During
Reset5
Status
After
Pin
Name
Supported
Functions2
I/O
Type
Pad4
Type
Description
Voltage3
Reset5
144 176 208
PC10
GPIO
eMIOS Channel
DSPI_C Peripheral Chip Select
DSPI_D Clock
I/O
I/O
O
eMIOS10
PCS_C5
SCK_D
PC10
PC11
PC12
PC13
PC14
PC15
42
43
44
45
46
47
VDDE1
VDDE1
VDDE1
VDDE1
VDDE1
VDDE1
SH
SH
SH
SH
SH
SH
—
—
—
—
—
—
—
—
—
—
—
—
110 134 A14
I/O
PC11
GPIO
eMIOS Channel
DSPI_C Peripheral Chip Select
DSPI_D Serial Out
I/O
I/O
O
eMIOS11
PCS_C4
SOUT_D
109 133 B14
108 132 B16
107 131 C15
106 130 C16
105 129 D14
O
PC12
eMIOS12
PSC_C3
SIN_D
GPIO
eMIOS Channel
DSPI_C Peripheral Chip Select
DSPI_D Serial In
I/O
I/O
O
I
PC13
GPIO
eMIOS Channel
DSPI_A Peripheral Chip Select
DSPI_D Peripheral Chip Select
I/O
I/O
O
eMIOS13
PCS_A5
PCS_D0
O
PC14
GPIO
eMIOS Channel
DSPI_A Peripheral Chip Select
DSPI_D Peripheral Chip Select
I/O
I/O
O
eMIOS14
PCS_A4
PCS_D1
O
PC15
GPIO
eMIOS Channel
DSPI_A Peripheral Chip Select
DSPI_D Peripheral Chip Select
I/O
I/O
O
eMIOS15
PCS_A3
PCS_D2
O
Port D (16)
PD0
CNTX_A
PCS_D3
GPIO
CAN_A Transmit
DSPI_D Peripheral Chip Select
I/O
O
O
PD0
PD1
48
49
VDDE1
SH
SH
—
—
—
—
104 128 D15
103 127 D16
PD1
CNRX_A
PCS_D4
GPIO
CAN_A Receive
DSPI_D Peripheral Chip Select
I/O
I
O
VDDE1
PD2
GPIO
CAN_B Receive
eMIOS Channel
I/O
I
O
I
CNRX_B
eMIOS10
BOOTCFG
PCS_D5
BOOTCFG
(Pulldown) (Pulldown)
GPI
PD2
50
VDDE1
SH
102 126 E14
Boot Configuration
DSPI_D Peripheral Chip Select
O
PD3
CNTX_B
eMIOS11
GPIO
CAN_B Transmit
eMIOS Channel
I/O
O
O
PD3
PD4
PD5
51
52
53
VDDE1
VDDE1
VDDE1
SH
SH
SH
—
—
—
—
—
—
101 125 E15
100 124 E16
99 123 F13
PD4
CNTX_C
eMIOS12
GPIO
CAN_C Transmit
eMIOS Channel
I/O
O
O
PD5
CNRX_C
eMIOS13
GPIO
CAN_C Receive
eMIOS Channel
I/O
I
O
MPC5510 Microcontroller Family Data Sheet, Rev. 4
Freescale Semiconductor
7
Pin Assignments and Reset States
Table 1. MPC5510 Signal Properties (continued)
Package Pin
Locations
GPIO
(PCR)
Num1
Status
During
Reset5
Status
After
Pin
Name
Supported
Functions2
I/O
Type
Pad4
Type
Description
Voltage3
Reset5
144 176 208
PD6
TXD_A
eMIOS14
GPIO
SCI_A Transmit
eMIOS Channel
I/O
O
O
PD6
PD7
PD8
PD9
54
55
56
57
VDDE1
VDDE1
VDDE1
VDDE1
SH
SH
SH
SH
—
—
—
—
—
—
—
—
98 122 F14
PD7
RXD_A
eMIOS15
GPIO
SCI_A Receive
eMIOS Channel
I/O
I
O
97 121 F15
94 118 G13
93 117 F16
PD8
TXD_B
SCL_A
GPIO
I/O
O
I/O
SCI_B Transmit
I2C Serial Clock Line
PD9
RXD_B
SDA_A
GPIO
I/O
I
I/O
SCI_B Receive
I2C Serial Data Line
PD10
PCS_B2
CNTX_F
NMI0
GPIO
I/O
O
O
I
DSPI_B Peripheral Chip Select
CAN_F Transmit
PD10
PD11
58
59
VDDE1
SH
SH
—
—
—
—
92 116 G14
91 115 G15
NMI Input for Z1 Core
PD11
PCS_B1
CNRX_F
NMI1
GPIO
I/O
O
I
DSPI_B Peripheral Chip Select
CAN_F Receive
VDDE1
NMI Input for Z0 Core
I
PD12
PCS_B0
eMIOS9
GPIO
I/O
I/O
O
PD12
PD13
PD14
PD15
60
61
62
63
DSPI_B Peripheral Chip Select
eMIOS Channel
VDDE1
VDDE1
VDDE1
VDDE1
SH
SH
SH
SH
—
—
—
—
—
—
—
—
90 114 H14
89 113 H15
88 110 J14
87 107 K14
PD13
SCK_B
eMIOS8
GPIO
DSPI_B Clock
eMIOS Channel
I/O
I/O
O
PD14
SOUT_B
eMIOS7
GPIO
DSPI_B Data Output
eMIOS Channel
I/O
O
O
PD15
SIN_B
eMIOS6
GPIO
DSPI_B Data Input
eMIOS Channel
I/O
I
O
Port E (16)
PE0
GPIO
DSPI_A Peripheral Chip Select
eMIOS Channel
I/O
O
O
I
PCS_A2
eMIOS5
MLBCLK
PE0
PE1
64
65
VDDE1
SH
—
—
—
—
86 106 K16
MLB Clock
PE1
GPIO
I/O
O
O
PCS_A1
eMIOS4
MLBSI /
MLBSIG
DSPI_A Peripheral Chip Select
eMIOS Channel
MLB Signal In (5-pin) /
MLB Bi-directional Signal (3-pin)
VDDE1
MH
85 103 L14
I
I/O
PE2
GPIO
I/O
I/O
O
PCS_A0
eMIOS3
MLBDI /
MLBDAT
DSPI_A Peripheral Chip Select
eMIOS Channel
MLB Data In (5-pin) /
MLB Bi-directional Data (3-pin)
PE2
66
VDDE1
MH
—
—
84 101 L15
I
I/O
MPC5510 Microcontroller Family Data Sheet, Rev. 4
8
Freescale Semiconductor
Pin Assignments and Reset States
Table 1. MPC5510 Signal Properties (continued)
Package Pin
Locations
GPIO
(PCR)
Num1
Status
During
Reset5
Status
After
Pin
Name
Supported
Functions2
I/O
Type
Pad4
Type
Description
Voltage3
Reset5
144 176 208
GPIO
DSPI_A Clock
eMIOS Channel
I/O
I/O
O
PE3
SCK_A
eMIOS2
PE3
PE4
67
68
VDDE1
MH
MH
—
—
—
—
83 100 M13
MLB Signal Out (5-pin) /
MLB Signal Level Shifter Enable (3-pin)
O
O
MLBSO /
MLBSIG_BUFEN
GPIO
DSPI_A Data Out
eMIOS Channel
I/O
O
O
PE4
SOUT_A
eMIOS1
MLBDO /
VDDE1
82
98 N14
MLB Data Out (5-pin) /
O
MLBDAT_BUFEN MLB Data Level Shifter Enable (3-pin)
O
GPIO
PE5
I/O
I
O
O
O
O
DSPI_A Data In
SIN_A
eMIOS Channel
MLB Slot Debug /
eMIOS0
PE5
PE6
69
70
VDDE1
MH
MH
—
—
—
—
81
67
97 M15
83 P13
MLB_SLOT /
MLB_SIGOBS /
MLB_DATOBS
MLB Clock Adjust Observe Signal /
MLB Clock Adjust Observe Data
PE6
CLKOUT
GPIO
System Clock Output
I/O
O
VDDE3
PE7
PE8
71
72
72
74
75
76
77
78
79
PE7
PE8
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDE1
VDDE1
VDDE1
VDDE1
VDDE1
VDDE1
VDDE1
VDDE1
VDDE1
SH
SH
SH
SH
SH
SH
SH
SH
SH
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
H13
H16
J13
PE9
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PE10
PE11
PE12
PE13
PE14
PE15
112 J16
111 J15
109 K13
108 L13
102 L16
99 M14
Port F (16)
PF0
RD_WR
EVTI8
GPIO
EBI Read/Write
Nexus Event In
I/O
I/O
I
PF0
PF1
80
81
VDDE3
MH
MH
—
—
—
—
66
65
82 N12
81 P12
PF1
TA
GPIO
EBI Transfer Acknowledge
MLB Clock
I/O
I/O
I
VDDE3
MLBCLK
EVTO8
Nexus Event Out
O
PF2
AD8
ADDR8
MLBSI /
MLBSIG
MSEO8
GPIO
I/O
I/O
O
EBI Muxed Address/Data
EBI Non Muxed Address
MLB Signal In (5-pin) /
PF2
82
VDDE3
MH
—
—
64
80 R12
I
MLB Bi-Directional Signal (3-pin)
Nexus Message Start/End Out
I/O
O
MPC5510 Microcontroller Family Data Sheet, Rev. 4
Freescale Semiconductor
9
Pin Assignments and Reset States
Table 1. MPC5510 Signal Properties (continued)
Package Pin
Locations
GPIO
(PCR)
Num1
Status
During
Reset5
Status
After
Pin
Name
Supported
Functions2
I/O
Type
Pad4
Type
Description
Voltage3
Reset5
144 176 208
PF3
AD9
ADDR9
MLBDI /
MLBDAT
MCKO8
GPIO
I/O
I/O
O
EBI Muxed Address/Data
EBI Non Muxed Address
MLB Data In (5-pin) /
MLB Bi-directional Data (3-pin)
Nexus Message Clock Out
PF3
PF4
PF5
83
84
85
VDDE3
MH
MH
MH
—
—
—
—
—
—
63
59
58
79 T12
I
I/O
O
GPIO
I/O
I/O
O
O
O
PF4
AD10
ADDR10
MLBSO /
MLBSIG_BUFEN
MDO08
EBI Muxed Address/Data
EBI Non Muxed Address
MLB Signal Out (5-pin) /
VDDE3
74 T10
MLB Signal Level Shifter Enable (3-pin)
Nexus Message Data Out
O
GPIO
I/O
I/O
O
O
O
PF5
AD11
ADDR11
MLBDO /
MLBDAT_BUFEN
MDO18
EBI Muxed Address/Data
EBI Non Muxed Address
MLB Data Out (5-pin) /
VDDE3
72
68
R9
T8
MLB Data Level Shifter Enable (3-pin)
Nexus Message Data Out
O
GPIO
I/O
I/O
O
O
O
PF6
AD12
ADDR12
EBI Muxed Address/Data
EBI Non Muxed Address
MLB Slot Debug /
PF6
86
VDDE3
MH
—
—
57
MLB_SLOT /
MLB_SIGOBS /
MLB_DATOBS
MDO28
MLB Clock Adjust Observe Signal /
MLB Clock Adjust Observe Data
Nexus Message Data Out
O
O
PF7
AD13
GPIO
I/O
I/O
O
EBI Muxed Address/Data
EBI Non Muxed Address
Nexus Message Data Out
PF7
PF8
87
88
89
90
91
92
VDDE3
VDDE2
VDDE2
VDDE2
VDDE2
VDDE2
MH
MH
MH
MH
MH
MH
—
—
—
—
—
—
—
—
—
—
—
—
56
55
54
52
51
50
66
65
64
62
61
60
P8
N8
T7
R7
P7
N7
ADDR13
MDO38
O
PF8
AD14
GPIO
I/O
I/O
O
EBI Muxed Address/Data
EBI Non Muxed Address
Nexus Message Data Out
ADDR14
MDO48
O
PF9
AD15
GPIO
I/O
I/O
O
EBI Muxed Address/Data
EBI Non Muxed Address
Nexus Message Data Out
PF9
ADDR15
MDO58
O
PF10
CS1
GPIO
EBI Chip Select
SCI_C Transmit
I/O
O
O
PF10
PF11
PF12
TXD_C
MDO68
Nexus Message Data Out
O
PF11
CS0
GPIO
EBI Chip Select
SCI_C Receive
I/O
O
I
RXD_C
MDO78
Nexus Message Data Out
O
PF12
TS
TXD_D
ALE
GPIO
EBI Transfer Start
SCI_D Transmit
I/O
I/O
O
EBI Address Latch Enable
O
MPC5510 Microcontroller Family Data Sheet, Rev. 4
10
Freescale Semiconductor
Pin Assignments and Reset States
Table 1. MPC5510 Signal Properties (continued)
Package Pin
Locations
GPIO
(PCR)
Num1
Status
During
Reset5
Status
After
Pin
Name
Supported
Functions2
I/O
Type
Pad4
Type
Description
Voltage3
Reset5
144 176 208
PF13
OE
RXD_D
GPIO
EBI Output Enable
SCI_D Receive
I/O
O
I
PF13
PF14
93
94
VDDE2
MH
MH
—
—
—
—
49
45
59
55
R6
P6
PF14
WE0
BDIP
GPIO
EBI Write Enable
EBI Burst Data In Progress
CAN_D Transmit
I/O
O
O
VDDE2
CNTX_D
O
PF15
WE1
TEA
GPIO
EBI Write Enable
EBI Transfer Error Acknowledge
CAN_D Receive
I/O
O
I/O
I
PF15
95
VDDE2
MH
—
—
44
54
N6
CNRX_D
Port G (16)
PG0
AD16
eMIOS16
GPIO
I/O
I/O
I/O
PG0
PG1
96
97
EBI Muxed Address/Data
eMIOS Channel
VDDE2
MH
MH
—
—
—
—
43
42
51
50
P5
T4
PG1
AD17
eMIOS17
SIN_C
GPIO
I/O
I/O
I/O
I
EBI Muxed Address/Data
eMIOS Channel
VDDE2
DSPI_C Serial In
PG2
AD18
eMIOS18
SOUT_C
GPIO
I/O
I/O
I/O
O
EBI Muxed Address/Data
eMIOS Channel
PG2
PG3
PG4
98
99
VDDE2
VDDE2
VDDE2
MH
MH
MH
—
—
—
—
—
—
41
40
39
49
48
47
R4
P4
T3
DSPI_C Serial Out
PG3
AD19
eMIOS19
SCK_C
GPIO
I/O
I/O
I/O
I/O
EBI Muxed Address/Data
eMIOS Channel
DSPI_C Serial Clock
PG4
AD20
eMIOS20
PCS_C0
GPIO
I/O
I/O
I/O
I/O
EBI Muxed Address/Data
eMIOS Channel
DSPI_C Peripheral Chip Select
100
PG5
AD21
eMIOS21
GPIO
I/O
I/O
I/O
PG5
PG6
101
102
EBI Muxed Address/Data
eMIOS Channel
VDDE2
MH
MH
—
—
—
—
38
37
46
45
R3
T2
PG6
AD22
eMIOS22
GPIO
I/O
I/O
I/O
EBI Muxed Address/Data
eMIOS Channel
VDDE2
PG7
AD23
eMIOS23
RXD_C
GPIO
I/O
I/O
I/O
I
EBI Muxed Address/Data
eMIOS Channel
PG7
PG8
103
104
VDDE2
MH
MH
—
—
—
—
36
35
44
43
R1
P2
SCI_C Receive
PG8
AD24
PCS_A4
GPIO
I/O
I/O
O
EBI Muxed Address/Data
DSPI_A Peripheral Chip Select
VDDE2
MPC5510 Microcontroller Family Data Sheet, Rev. 4
Freescale Semiconductor
11
Pin Assignments and Reset States
Table 1. MPC5510 Signal Properties (continued)
Package Pin
Locations
GPIO
(PCR)
Num1
Status
During
Reset5
Status
After
Pin
Name
Supported
Functions2
I/O
Type
Pad4
Type
Description
Voltage3
Reset5
144 176 208
PG9
AD25
PCS_A3
TXD_C
GPIO
I/O
I/O
O
EBI Muxed Address/Data
DSPI_A Peripheral Chip Select
SCI_C Transmit
PG9
105
VDDE2
MH
—
—
34
42
N3
O
PG10
AD26
PCS_A2
GPIO
I/O
I/O
O
PG10
PG11
PG12
PG13
PG14
PG15
106
107
108
109
110
111
EBI Muxed Address/Data
DSPI_A Peripheral Chip Select
VDDE2
VDDE2
VDDE2
VDDE2
VDDE2
VDDE2
MH
MH
MH
MH
MH
MH
—
—
—
—
—
—
—
—
—
—
—
—
30
29
28
27
26
25
38
37
36
35
34
33
N2
N1
M4
M3
M2
M1
PG11
AD27
PCS_A1
GPIO
I/O
I/O
O
EBI Muxed Address/Data
DSPI_A Peripheral Chip Select
PG12
AD28
PCS_A0
GPIO
I/O
I/O
I/O
EBI Muxed Address/Data
DSPI_A Peripheral Chip Select
PG13
AD29
SCK_A
GPIO
I/O
I/O
I/O
EBI Muxed Address/Data
DSPI_A Clock
PG14
AD30
SOUT_A
GPIO
I/O
I/O
O
EBI Muxed Address/Data
DSPI_A Data Out
PG15
AD31
SIN_A
GPIO
I/O
I/O
I
EBI Muxed Address/Data
DSPI_A Data In
Port H (16)
PH0
AN27
eMIOS20
SCL_A
GPIO
I/O
I
O
eQADC Analog Input7
eMIOS Channel
PH0
PH1
PH2
PH3
PH4
PH5
112
113
114
115
116
117
VDDE2
VDDE2
VDDE2
VDDE2
VDDE2
VDDE2
A + SH
A + SH
A + MH
A + MH
A + SH
A + SH
—
—
—
—
—
—
—
—
—
—
—
—
24
23
22
21
20
19
32
31
30
29
28
24
L3
L2
L1
K4
K3
J3
I2C_A Serial Clock
I/O
PH1
AN26
eMIOS21
SDA_A
GPIO
I/O
I
O
eQADC Analog Input7
eMIOS Channel
I2C_A Serial Data
I/O
PH2
AN25
eMIOS22
CS3
GPIO
I/O
I
O
O
eQADC Analog Input7
eMIOS Channel
EBI Chip Select
PH3
AN24
eMIOS23
CS2
GPIO
I/O
I
O
O
eQADC Analog Input7
eMIOS Channel
EBI Chip Select
PH4
AN23
TXD_E
MA2
GPIO
I/O
I
O
O
eQADC Analog Input7
SCI_E Transmit
eQADC External Mux Address
PH5
AN22
RXD_E
MA1
GPIO
I/O
I
I
eQADC Analog Input7
SCI_E Receive
eQADC External Mux Address
O
MPC5510 Microcontroller Family Data Sheet, Rev. 4
12
Freescale Semiconductor
Pin Assignments and Reset States
Table 1. MPC5510 Signal Properties (continued)
Package Pin
Locations
GPIO
(PCR)
Num1
Status
During
Reset5
Status
After
Pin
Name
Supported
Functions2
I/O
Type
Pad4
Type
Description
Voltage3
Reset5
144 176 208
PH6
AN21
TXD_F
GPIO
I/O
I
O
PH6
PH7
118
119
eQADC Analog Input7
SCI_F Transmit
VDDE2
A + SH
A + SH
—
—
—
—
18
17
23
22
J2
J1
PH7
AN20
RXD_F
GPIO
I/O
I
I
eQADC Analog Input7
SCI_F Receive
VDDE2
PH8
AN19
CNTX_E
MA0
GPIO
I/O
I
O
O
eQADC Analog Input7
CAN_E Transmit
PH8
120
VDDE2
A + SH
—
—
14
17
H1
eQADC External Mux Address
PH9
AN18/ANT
CNRX_E
GPIO
I/O
I
I
PH9
PH10
PH11
121
122
123
eQADC Analog Input7
CAN_E Receive
VDDE2
VDDE2
VDDE2
A + SH
A + SH
A + SH
—
—
—
—
—
—
13
12
11
14
12
11
G2
F4
F3
PH10
AN17/ANS
CNRX_F
GPIO
I/O
I
I
eQADC Analog Input7
CAN_F Receive
PH11
AN16/ANR
CNTX_F
GPIO
I/O
I
O
eQADC Analog Input7
CAN_F Transmit
PH12
PCS_D5
GPIO
I/O
O
PH12
PH13
PH14
124
125
126
VDDE2
VDDE2
VDDE2
SH
SH
MH
—
—
—
—
—
—
—
—
—
—
—
53
F2
F1
T5
DSPI_D Peripheral Chip Select
PH13
GPIO
I/O
PH14
WE2
GPIO
EBI Write Enable
I/O
O
PH15
WE3
GPIO
EBI Write Enable
I/O
O
PH15
127
VDDE2
MH
—
—
—
52
R5
Port J (16)
PJ0
AD0
GPIO
I/O
I/O
PJ0
PJ1
PJ2
PJ3
PJ4
PJ5
PJ6
PJ7
128
129
130
131
132
133
134
135
VDDE3
VDDE3
VDDE3
VDDE3
VDDE3
VDDE3
VDDE3
VDDE3
MH
MH
MH
MH
MH
MH
MH
MH
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
N11
P11
N10
R10
EBI Muxed Address/Data
PJ1
AD1
GPIO
I/O
I/O
EBI Muxed Address/Data
PJ2
AD2
GPIO
I/O
I/O
EBI Muxed Address/Data
PJ3
AD3
GPIO
I/O
I/O
EBI Muxed Address/Data
PJ4
AD4
GPIO
I/O
I/O
75 P10
EBI Muxed Address/Data
PJ5
AD5
GPIO
I/O
I/O
73
69
67
T9
P9
R8
EBI Muxed Address/Data
PJ6
AD6
GPIO
I/O
I/O
EBI Muxed Address/Data
PJ7
AD7
GPIO
I/O
I/O
EBI Muxed Address/Data
MPC5510 Microcontroller Family Data Sheet, Rev. 4
Freescale Semiconductor
13
Pin Assignments and Reset States
Table 1. MPC5510 Signal Properties (continued)
Package Pin
Locations
GPIO
(PCR)
Num1
Status
During
Reset5
Status
After
Pin
Name
Supported
Functions2
I/O
Type
Pad4
Type
Description
Voltage3
Reset5
144 176 208
PJ8
PCS_D4
GPIO
I/O
I/O
PJ8
PJ9
136
137
138
139
140
141
142
143
VDDE2
VDDE2
VDDE2
VDDE2
VDDE2
VDDE2
VDDE2
VDDE2
SH
SH
SH
SH
SH
SH
SH
SH
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
27
26
25
19
18
16
15
13
K2
K1
J4
DSPI_D Peripheral Chip Select
PJ9
PCS_D3
GPIO
I/O
I/O
DSPI_D Peripheral Chip Select
PJ10
PCS_D2
GPIO
I/O
I/O
PJ10
PJ11
PJ12
PJ13
PJ14
PJ15
DSPI_D Peripheral Chip Select
PJ11
PCS_D1
GPIO
I/O
I/O
H3
H2
G4
G3
G1
DSPI_D Peripheral Chip Select
PJ12
PCS_D0
GPIO
I/O
I/O
DSPI_D Peripheral Chip Select
PJ13
SCK_D
GPIO
DSPI_D Clock
I/O
I/O
PJ14
SOUT_D
GPIO
DSPI_D Serial Out
I/O
O
PJ15
SIN_D
GPIO
DSPI_D Serial In
I/O
I
Port K (2)
PK0
EXTAL32
GPIO
I
I
PK0
PK1
144
145
VDDA
AE + IH
AE + IH
—
—
—
—
—
—
168 B6
166 A6
32 kHz Crystal Oscillator Input
PK1
XTAL32
GPIO
I
O
VDDA
32 kHz Crystal Oscillator Output
Miscellaneous Pins (9)
EXTAL
EXTCLK
Main Crystal Oscillator Input
I
I
EXTAL
—
VDDSYN
AE
EXTAL
75
91 N16
External Clock Input
Main Crystal Oscillator Output
JTAG Test Mode Select Input
JTAG Test Clock Input
JTAG Test Data Output
JTAG Test Data Input
JTAG Compliancy
XTAL
TMS
—
—
—
—
—
—
—
—
XTAL
TMS
O
VDDSYN
VDDE3
VDDE3
VDDE3
VDDE3
VDDE3
VDDE3
VDDE2
AE
SH
IH
XTAL
74
72
71
70
69
68
62
10
90 P16
88 T15
87 R14
86 T14
85 R13
84 T13
78 R11
I
TMS (Pull Up)
TCK (Pull Down)
TDO (Pull Up9)
TDI (Pull Up)
TCK
TCK
I
O
I
TDO
TDO
MH
IH
TDI
TDI
JCOMP
TEST10
RESET
JCOMP
TEST
RESET
I
IH
JCOMP (Pull Down)
TEST
Test Mode Select
I
IH
External Reset
I/O
SH
RESET (Pull Up)
10
E4
1
2
The GPIO number is the same as the corresponding pad configuration register (SIU_PCRn) number.
This column lists the functions associated with the programming of the SIU_PCRn[PA] bit field in the following order: GPIO, function
1, function 2, and function 3. The unused functions by a given pin begin with function 3, then function 2, then function 1.
3
4
These are nominal voltages. Each segment provides the power and ground for the given set of I/O pins.
Pad types: SH - Bi-directional slow speed pad with input hysteresis; MH - Bi-directional medium speed pad with input hysteresis; IH
- Input only pad with input hysteresis; AE/A - Analog pad.
5
A dash for the function in this column denotes the input and output buffer are turned off.
MPC5510 Microcontroller Family Data Sheet, Rev. 4
14
Freescale Semiconductor
Pin Assignments and Reset States
6
7
8
Port A[14:15]—EXTAL32 and XTAL32 functions only apply on the 144LQFP. These functions are on PortK[0:1] for the 176LQFP and
208BGA. In the 176 LQFP and 208 BGA packages, activity on PA14 should be minimized if the 32kHz XTAL is enabled.
This analog input pin has reduced analog-to-digital conversion accuracy compared to PA0–PA15. See eQADC spec #11 (Total
Unadjusted Error for single ended conversions with calibration) for further notes on this.
The NEXUS function is selected when the JTAG TAP controller is enabled via the JCOMP pin and the appropriate bits in the NP
PCR register. The value of the PA field in the associated PCR register has no effect on the pin function when the NEXUS function
is selected.
9
Pullup is enabled only when JCOMP is negated.
10 Always connect the TEST pin to Ground (Vss).
1.2
Power and Ground Supply Summary
Table 2. MPC5510 Power/Ground
Package Pin Locations
Pin
Name
Function Description
Voltage1
144
176
208
VDDR
VDDA
Voltage Regulator Supply
Analog Power
5.0 V
5.0 V
5.0 V
–
46
56
T6
A2
144
141
176
173
2
VRH
eQADC Voltage Reference High
Analog Ground
B3
VSSA
A4
3
VRL
B4
eQADC Voltage Reference Low
eQADC Reference Bypass Capacitor
Flash Program/Erase Power
Clock Synthesizer Power
Clock Synthesizer Ground
–
VSSA
5.0 V
3.3 V
–
REFBYPC
1
1
B1
4
VPP
78
73
76
94
89
92
P15
R16
M16
5
VDDSYN
VSSSYN
VDDE1
105,120,
143,155
A15,D10,E13,
G16,K15
96,119
3.3 V –
5.0 V
External I/O Power
VDDE2
VDDE3
16,33,48 21,41,58
H4,L4,N5,P1
N9,T11
61
71,77
104,119, Shorted to VSS in
VSSE1
VSSE2
VSSE3
95,118
142,154
the package
Shorted to VSS in
the package
15,32,47 20,40,57
External I/O Ground
–
Shorted to VSS in
the package
60
77
70,76
93
5
VDD33
3.3 V I/O Power
N15
3.3 V
1.5 V
5, 6
VFLASH
Flash Read Power
A1,A16,B2,B15,
R2,R15,T1,T16
5
VDD
Internal Logic Power
31,53,79 39,63,95
ShortedtoVDD in
the package
5
VDDF
Flash Internal Logic Power
79
95
C3,C14,D4,D13,
G7-G10,H7-H10,
J7-J10,K7-K10,
N4,N13,P3,P14
VSS
Ground
80
96
–
Shorted to VSS in
the package
VSSF
Flash Internal Logic Ground
1
These are nominal voltages.
2
VRH is shorted to VDDA in the 144LQFP and 176 LQFP packages.
MPC5510 Microcontroller Family Data Sheet, Rev. 4
Freescale Semiconductor
15
Pin Assignments and Reset States
3
VRL is shorted to VSSA in the 144LQFP and 176 LQFP packages.
4
5
6
VPP requires 5V for program/erase operations, but may be 0-5V otherwise. VPP should not go high
or low when the device is in Sleep mode.
Voltage generated from internal voltage regulator and no external connection or load allowed
except the required bypass capacitors.
VFLASH is shorted to VDD33 in the package.
MPC5510 Microcontroller Family Data Sheet, Rev. 4
16
Freescale Semiconductor
Pin Assignments and Reset States
1.3
Pinout – 144 LQFP
REFBYPC
AN7/PA7
AN6/PA6
AN5/PA5
AN4/PA4
AN3/PA3
AN2/PA2
AN1/PA1
AN0/PA0
RESET
PC12/eMIOS12/PCS_C3/SIN_D
PC13/eMIOS13/PCS_A5/PCS_D0
PC14/eMIOS14/PCS_A4/PCS_D1
PC15/eMIOS15/PCS_A3/PCS_D2
PD0/CNTX_A/PCS_D3
PD1/CNRX_A/PCS_D4
PD2/CNRX_B/eMIOS10/BOOTCFG*/PCS_D5
PD3/CNTX_B/eMIOS11
PD4/CNTX_C/eMIOS12
PD5/CNRX_C/eMIOS13
PD6/TXD_A/eMIOS14
PD7/RXD_A/eMIOS15
1
2
3
4
5
6
7
8
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
CNTX_F/AN16/ANR/PH11
CNRX_F/AN17/ANS/PH10
CNRX_E/AN18/ANT/PH9
MA0/CNTX_E/AN19/PH8
V
DDE1
V
SSE1
V
PD8/TXD_B/SCL_A
PD9/RXD_B/SDA_A
PD10/PCS_B2/CNTX_F/NMI0
PD11/PCS_B1/CNRX_F/NMI1
PD12/PCS_B0/eMIOS9
PD13/SCK_B/eMIOS8
PD14/SOUT_B/eMIOS7
PD15/SIN_B/eMIOS6
PE0/PCS_A2/eMIOS5/MLBCLK
PE1/PCS_A1/eMIOS4/MLBSI
PE2/PCS_A0/eMIOS3/MLBDI
PE3/SCK_A/eMIOS2//MLBSO
PE4/SOUT_A/eMIOS1/MLBDO
PE5/SIN_A/eMIOS0/MLB_SLOT
SSE2
V
DDE2
RXD_F/AN20/PH7
TXD_F/AN21/PH6
144 LQFP
MA1/RXD_E/AN22/PH5
MA2/TXD_E/AN23/PH4
CS2/eMIOS23/AN24/PH3
CS3/eMIOS22/AN25/PH2
SDA_A/eMIOS21/AN26/PH1
SCL_A/eMIOS20/AN27/PH0
SIN_A/AD31/PG15
SOUT_A/AD30/PG14
SCK_A/AD29/PG13
PCS_A0/AD28/PG12
PCS_A1/AD27/PG11
PCS_A2/AD26/PG10
V
V
V
V
V
/V
SS SSF
/V
DD DDF
V
PP
DD
V
/V
SSE2
DD33 FLASH
V
DDE2
SSSYN
TXD_C/PCS_A3/AD25/PG9
PCS_A4/AD24/PG8
RXD_C/eMIOS23/AD23/PG7
EXTAL/EXTCLK
XTAL
V
DDSYN
74
73
* Denotes active during RESET only
Figure 2. MPC5510 Pinout – 144 LQFP
MPC5510 Microcontroller Family Data Sheet, Rev. 4
Freescale Semiconductor
17
Pin Assignments and Reset States
1.4
Pinout – 176 LQFP
REFBYPC
AN7/PA7
AN6/PA6
AN5/PA5
AN4/PA4
AN3/PA3
AN2/PA2
AN1/PA1
AN0/PA0
RESET
1
2
3
4
5
6
7
8
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
PC12/eMIOS12/PCS_C3/SIN_D
PC13/eMIOS13/PCS_A5/PCS_D0
PC14/eMIOS14/PCS_A4/PCS_D1
PC15/eMIOS15/PCS_A3/PCS_D2
PD0/CNTX_A/PCS_D3
PD1/CNRX_A/PCS_D4
PD2/CNRX_B/eMIOS10/BOOTCFG*/PCS_D5
PD3/CNTX_B/eMIOS11
PD4/CNTX_C/eMIOS12
PD5/CNRX_C/eMIOS13
PD6/TXD_A/eMIOS14
PD7/RXD_A/eMIOS15
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
CNTX_F/AN16/ANR/PH11
CNRX_F/AN17/ANS/PH10
SIN_D/PJ15
CNRX_E/AN18/ANT/PH9
SOUT_D/PJ14
SCK_D/PJ13
MA0/CNTX_E/AN19/PH8
PCS_D0/PJ12
V
DDE1
V
SSE1
PD8/TXD_B/SCL_A
PD9/RXD_B/SDA_A
PD10/PCS_B2/CNTX_F/NMI0
PD11/PCS_B1/CNRX_F/NMI1
PD12/PCS_B0/eMIOS9
PD13/SCK_B/eMIOS8
PE10
PCS_D1/PJ11
V
SSE2
V
DDE2
RXD_F/AN20/PH7
TXD_F/AN21/PH6
MA1/RXD_E/AN22/PH5
PCS_D2/PJ10
176 LQFP
PE11
PCS_D3/PJ9
PCS_D4/PJ8
PD14/SOUT_B/eMIOS7
PE12
PE13
PD15/SIN_B/eMIOS6
PE0/PCS_A2/eMIOS5/MLBCLK
MA2/TXD_E/AN23/PH4
CS2/eMIOS23/AN24/PH3
CS3/eMIOS22/AN25/PH2
SDA_A/eMIOS21/AN26/PH1
SCL_A/eMIOS20/AN27/PH0
SIN_A/AD31/PG15
V
DDE1
V
SSE1
PE1/PCS_A1/eMIOS4/MLBSI
PE14
PE2/PCS_A0/eMIOS3/MLBDI
PE3/SCK_A/eMIOS2//MLBSO
PE15
SOUT_A/AD30/PG14
SCK_A/AD29/PG13
PCS_A0/AD28/PG12
PCS_A1/AD27/PG11
PCS_A2/AD26/PG10
98
97
96
95
94
93
92
PE4/SOUT_A/eMIOS1/MLBDO
PE5/SIN_A/eMIOS0/MLB_SLOT
V
DD
V
SSE2
V
V
V
V
V
/V
SS SSF
V
DDE2
/V
DD DDF
TXD_C/PCS_A3/AD25/PG9
PCS_A4/AD24/PG8
RXD_C/eMIOS23/AD23/PG7
PP
/V
DD33 FLASH
SSSYN
91
90
EXTAL/EXTCLK
XTAL
89
V
DDSYN
* Denotes active during RESET only
Figure 3. MPC5510 Pinout – 176 LQFP
MPC5510 Microcontroller Family Data Sheet, Rev. 4
18
Freescale Semiconductor
Pin Assignments and Reset States
1.5
Pinout – 208 PBGA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PB15
PA13
PK1
PB2
PB6
PB10
PC3
PC7
PC10
V
V
DD
PB12
A
B
C
D
E
F
V
V
PA8
V
A
B
C
D
E
F
DDE1
DD
DDA
SSA
REF
BYPC
PB13
PB0
PB1
PB3
PB4
PB5
PB7
PB8
PB9
PB11
PB14
PC0
PC1
PC2
PC4
PC5
PC6
PC8
PC9
PC11
V
PC12
PC14
PD1
V
V
V
RL
PA12
PA11
PA10
PK0
PA15
PA14
DD
DD
RH
V
PC13
PD0
PA7
PA5
PA6
PA4
V
PA9
SS
SS
V
V
PC15
PD2
PA3
V
DDE1
SS
SS
PA2
PA1
PA0 RESET
V
PD3
PD4
DDE1
208 PBGA Ball Map
(as viewed from top through the package)
PH13
PJ15
PH8
PH7
PJ9
PH12
PH9
PJ12
PH6
PJ8
PH11
PJ14
PJ11
PH5
PH4
PH0
PH10
PJ13
PD5
PD6
PD7
PD9
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
PD8
PE7
PD10
PD12
PD14
PD15
PE1
PD11
PD13
PE11
V
G
H
J
G
H
J
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DDE1
V
PE8
PE10
PE0
DDE2
PJ10
PH3
PE9
PE12
PE13
PE3
V
K
L
K
L
DDE1
PH2
PH1
V
PE2
PE5
PE14
VSSSYN
EXTAL
XTAL
VDDSYN
DDE2
PG15 PG14 PG13 PG12
PE15
PE4
M
N
P
R
T
M
N
P
R
T
PF15
PF12
PF8
V
PJ2
PJ0
PF0
PF1
PF2
V
V
PG11
PG10
PG8
PG9
V
V
DDE3
SS
DD33
SS
DDE2
PE6
TDI
V
V
V
V
PG3
PG2
PG0
PF14
PF13
PF11
PF10
PF7
PJ7
PJ6
PJ4
PJ3
PJ1
SS
PP
DDE2
SS
PH15
PF5
TEST
TCK
V
PG7
V
PG5
DD
DD
PF3 JCOMP TDO
12 13 14
TMS
15
V
V
PG6
2
PG4
3
PG1
4
PH14
5
V
PF9
7
PF6
8
PJ5
9
PF4
10
V
DD
DD
DDR
DDE3
1
6
11
16
Figure 4. MPC5510 Pinout – 208 PBGA
MPC5510 Microcontroller Family Data Sheet, Rev. 4
Freescale Semiconductor
19
Electrical Characteristics
2
Electrical Characteristics
This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing
specifications for the MCU.
2.1
Maximum Ratings
1
Table 3. Absolute Maximum Ratings
Num
Characteristic
Symbol
Min
Max2
Unit
1
2
3
4
5.0V Voltage Regulator Reference Voltage
5.0V Analog Supply Voltage (reference to VSSA
5.0V Flash Program/Erase Voltage
VDDR
VDDA
VPP
– 0.3
– 0.3
– 0.3
6.5
6.5
6.5
V
V
V
V
)
3.3V – 5.0V External I/O Supply Voltage 3
4
VDDE1
VDDE2
– 0.3
– 0.3
– 0.3
6.5
6.5
6.5
4
4
VDDE3
5
6
7
8
9
DC Input Voltage 5
VIN
–1.06
– 0.3
– 5.5
– 0.3
– VDDA
–2
6.57
5.5
5.5
0.3
0.3
2
V
V
VREF Differential Voltage
VRH – VRL
VRH – VDDA
VRL – VSSA
VDDR – VDDA
IMAXD
VRH to VDDA Differential Voltage
V
V
RL to VSSA Differential Voltage
DDR to VDDA Differential Voltage
V
V
V
10 Maximum DC Digital Input Current 8 (per pin, applies to all
digital MH, SH, and IH pins)
mA
11 Maximum DC Analog Input Current 9 (per pin, applies to all
analog AE and A pins)
IMAXA
–3
3
mA
12 Storage Temperature Range
13 Maximum Solder Temperature 10
14 Moisture Sensitivity Level 11
TSTG
TSDR
MSL
– 55.0
—
150.0
260.0
3
oC
oC
—
1
2
Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only,
and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device reliability or
cause permanent damage to the device.
Absolute maximum voltages are currently maximum burn–in voltages. Absolute maximum specifications for device stress have
not yet been determined.
3
4
All functional non-supply I/O pins are clamped to VSS and VDDE
.
VDDE1, VDDE2, and VDDE3 are separate power segments and may be powered independently with no differential voltage
constraints between the power segments.
5
AC signal over and undershoot of the input voltages of up to +/– 2.0 volts is permitted for a cumulative duration of 60 hours
over the complete lifetime of the device (injection current does not need to be limited for this duration).
6
7
Internal structures will hold the input voltage above -1.0 volt if the injection current limit of 2mA is met.
Internal structures hold the input voltage below this maximum voltage on all pads powered by VDDE supplies, if the maximum
injection current specification is met (2 mA for all pins) and VDDE is within Operating Voltage specifications.
8
9
Total injection current for all pins (including both digital and analog) must not exceed 25mA.
Total injection current for all analog input pins must not exceed 15mA.
10 Solder profile per CDF-AEC-Q100.
11 Moisture sensitivity per JEDEC test method A112.
MPC5510 Microcontroller Family Data Sheet, Rev. 4
20
Freescale Semiconductor
Electrical Characteristics
2.2
Thermal Characteristics
Table 4. Thermal Characteristics
Value
208 MAPBGA 176 LQFP
Num
Characteristic
Junction to Ambient 1, 2
Natural Convection
(Single layer board)
Junction to Ambient 1, 3
Natural Convection
Symbol Unit
144 LQFP
1
2
RJA °C/W
44
38
43
RJA °C/W
27
31
34
(Four layer board 2s2p)
3
4
Junction to Ambient 1, 3
(@200 ft./min., Single layer board)
Junction to Ambient 1, 3
RJMA °C/W
RJMA °C/W
35
24
30
25
34
28
(@200 ft./min., Four layer board 2s2p)
5
6
7
Junction to Board 4
Junction to Case 5
Junction to Package Top 6
Natural Convection
RJB °C/W
RJC °C/W
JT °C/W
16
8
20
6
22
7
2
2
2
1
Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2
3
4
Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
Per JEDEC JESD51-6 with the board horizontal.
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on
the top surface of the board near the package.
5
6
Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method
(MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature.
Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2.
2.2.1
General Notes for Specifications at Maximum Junction Temperature
An estimation of the chip junction temperature, T , can be obtained from the equation:
J
T = T + (R
P )
Eqn. 1
J
A
JA
D
where:
o
T = ambient temperature for the package ( C)
Eqn. 2
A
o
R
= junction to ambient thermal resistance ( C/W)
Eqn. 3
Eqn. 4
JA
P = power dissipation in the package (W)
D
The supplied thermal resistances are provided based on JEDEC JESD51 series of standards to provide consistent values for
estimations and comparisons. The difference between the values determined on the single-layer (1s) board and on the four-layer
board with two signal layers and a power and a ground plane (2s2p) clearly demonstrate that the effective thermal resistance of
MPC5510 Microcontroller Family Data Sheet, Rev. 4
Freescale Semiconductor
21
Electrical Characteristics
the component is not a constant. It depends on the construction of the application board (number of planes), the effective size
of the board which cools the component, how well the component is thermally and electrically connected to the planes, and the
power being dissipated by adjacent components.
Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to connect the package
to the planes reduces the thermal performance. Thinner planes also reduce the thermal performance. When the clearance
between through vias leave the planes virtually disconnected, the thermal performance is also greatly reduced.
As a general rule, the value obtained on a single layer board is appropriate for the tightly packed printed circuit board. The value
obtained on the board with the internal planes is usually appropriate if the application board has one oz (35 micron nominal
thickness) internal planes, the components are well separated, and the overall power dissipation on the board is less than 0.02
2
W/cm .
The thermal performance of any component depends strongly on the power dissipation of surrounding components. In addition,
the ambient temperature varies widely within the application. For many natural convection and especially closed box
applications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature
near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description
of the local ambient conditions that determine the temperature of the device.
At a known board temperature, the junction temperature is estimated using the following equation:
T = T + (R
P )
Eqn. 5
J
B
JB
D
where:
o
T = junction temperature ( C)
Eqn. 6
Eqn. 7
J
o
T = board temperature at the package perimeter ( C/W)
B
o
R
= junction to board thermal resistance ( C/W) per JESD51-8
Eqn. 8
Eqn. 9
JB
P = power dissipation in the package (W)
D
When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made.
The application board should be similar to the thermal test condition, with the component soldered to a board with internal
planes.
Historically, the thermal resistance has frequently been expressed as the sum of a junction to case thermal resistance and a case
to ambient thermal resistance:
R
= R
+ R
CA
Eqn. 10
JA
JC
where:
o
R
= junction to ambient thermal resistance ( C/W)
Eqn. 11
Eqn. 12
Eqn. 13
JA
o
R
R
= junction to case thermal resistance ( C/W)
JC
o
= case to ambient thermal resistance ( C/W)
CA
R
is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to
JC
ambient thermal resistance, R
. For instance, the user can change the air flow around the device, add a heat sink, change the
CA
mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the
MPC5510 Microcontroller Family Data Sheet, Rev. 4
22
Freescale Semiconductor
Electrical Characteristics
device. This description is most useful for packages with heat sinks where some 90% of the heat flow is through the case to the
heat sink to ambient. For most packages, a better model is required.
A more accurate two-resistor thermal model can be constructed from the junction to board thermal resistance and the junction
to case thermal resistance. The junction to case covers the situation where a heat sink will be used or where a substantial amount
of heat is dissipated from the top of the package. The junction to board thermal resistance describes the thermal performance
when most of the heat is conducted to the printed circuit board. This model can be used for either hand estimations or for a
computational fluid dynamics (CFD) thermal model.
To determine the junction temperature of the device in the application after prototypes are available, the Thermal
Characterization Parameter ( ) can be used to determine the junction temperature with a measurement of the temperature at
JT
the top center of the package case using the following equation:
T = T + ( P )
Eqn. 14
J
T
JT
D
where:
o
T = thermocouple temperature on top of the package ( C)
Eqn. 15
T
o
= thermal characterization parameter ( C/W)
Eqn. 16
Eqn. 17
JT
P = power dissipation in the package (W)
D
The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied
to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the
package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the
junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects
of the thermocouple wire.
References:
Semiconductor Equipment and Materials International
805 East Middlefield Rd
Mountain View, CA 94043
(415) 964-5111
MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or
303-397-7956.
JEDEC specifications are available on the WEB at http://www.jedec.org.
1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive Engine
Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47–54.
2. G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled Applications,” Electronic
Packaging and Production, pp. 53–58, March 1998.
3. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its Application
in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212–220.
MPC5510 Microcontroller Family Data Sheet, Rev. 4
Freescale Semiconductor
23
Electrical Characteristics
2.3
ESD Characteristics
1, 2
Table 5. ESD Ratings
Characteristic
Symbol
Value
Unit
ESD for Human Body Model (HBM)
HBM Circuit Description
2000
1500
V
R1
C
Ohm
pF
100
ESD for Field Induced Charge Model (FDCM)
500 (all pins)
750 (corner pins)
V
Number of Pulses per pin:
Positive Pulses (HBM)
Negative Pulses (HBM)
—
—
1
1
—
—
Interval of Pulses
—
1
second
1
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
2
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification
requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at room
temperature followed by hot temperature, unless specified otherwise in the device specification
MPC5510 Microcontroller Family Data Sheet, Rev. 4
24
Freescale Semiconductor
Electrical Characteristics
2.4
DC Electrical Specifications
Table 6. DC Electrical Specifications
Num
Characteristic
Symbol
Min
Max
Unit
1a C parts
Operating junction temperature range
Operating ambient temperature range1
TJ
TA
– 40
– 40
105
85
oC
oC
1b V parts
Operating junction temperature range
TJ
TA
– 40
– 40
120
105
oC
oC
Operating ambient temperature range1
1c M parts2
Operating junction temperature range
TJ
TA
– 40
– 40
145
125
oC
oC
Operating ambient temperature range1
2
3
4
5
5.0V Voltage Regulator Reference Voltage
5.0V Analog Supply Voltage
VDDR
VDDA
VPP
4.5
4.5
4.5
5.25
5.25
5.25
V
V
V
V
5.0V Flash Program/Erase Voltage 3
3.3V – 5.0V External I/O Supply Voltage
4,5
VDDE1
3.0
3.0
3.0
5.5
5.5
5.5
4
VDDE2
4
VDDE3
6
7
8
9
Pad (SH/MH/IH) Input High Voltage
Pad (SH/MH/IH) Input Low Voltage
Pad (SH/MH/IH) Input Hysteresis
Analog (AE/A) Input Voltage
VIH
VIL
0.65 VDDE VDDE + 0.3
VSS – 0.3 0.35 VDDE
0.1 VDDE 0.2 VDDE
V
V
V
V
VHYS
VINDC
VSSA – 0.3 VDDA + 0.3
see note5
10 Slow/Medium I/O Output High Voltage
IOH = –1.0 mA
VOH
V
V
0.80 VDDE
0.95 VDDE
—
IOH = –0.2 mA
11 Slow/Medium I/O Output Low Voltage
IOL = 1.0 mA
VOL
—
0.20 VDDE
0.05 VDDE
IOH = 0.2 mA
12 Input Capacitance (Digital Pins: Pad type MH,SH, IH with no A or AE)
13 Input Capacitance (Analog Pins: Pad type A, AE, and AE+IH)
14 Input Capacitance (Shared digital and analog pins: A with SH or MH)
15 Slow/Medium I/O Weak Pull Up/Down Absolute Current 6
16 I/O Input Leakage Current 7
CIN
CIN_A
—
—
7
pF
pF
pF
A
A
mA
nA
A
10
CIN_M
IACT
IINACT_D
IIC
IINACT_A
IINACT_AD
—
12
10
170
1.5
2.0
200
1.5
– 1.5
– 2.0
– 200
–1.5
17 DC Injection Current (per pin)
18 Analog Input Current, Channel Off 8 (Analog pins AE and AE+IH)
19 Analog Input Current (Shared digital and analog pins: A with SH or
MH)
20 VRH to VDDA Differential Voltage
VRH – VDDA
– 100
100
mV
MPC5510 Microcontroller Family Data Sheet, Rev. 4
Freescale Semiconductor
25
Electrical Characteristics
Num
Table 6. DC Electrical Specifications (continued)
Characteristic
Symbol
Min
Max
Unit
21 VRL to VSSA Differential Voltage
VRL – VSSA
VSS – VSSA
VSSSYN – VSS
VDDR – VDDA
Vramp
– 100
– 100
–50
100
100
50
mV
mV
mV
mV
V/ms
nF
22 VSS to VSSA Differential Voltage
23 VSSSYN to VSS Differential Voltage
24 VDDR to VDDA Differential Voltage
– 100
1
100
100
25 Slew rate on VDDA, VDDR, and VDDE power supply pins9
26 Capactive Supply Load
Vload
VDD
VDD33
VDDSYN
800
200
200
—
—
1
Please refer to Section 2.2.1, “General Notes for Specifications at Maximum Junction Temperature” for more details about the
relation between ambient temperature TA and device junction temperature TJ.
2
3
4
M parts can’t go above 66 MHz.
VPP can drop to 0 volts during read-only operations and before entry to Sleep mode, to reduce power consumption.
VDDE1, VDDE2, and VDDE3 are separate power segments and may be powered independently with no differential voltage
constraints between the power segments.
5
If VDDE1 is below VDDA than the analog input limits (spec #9 (Analog (AE/A) Input Voltage) in Table 6) will be based on the
VDDE1 voltage level.
6
7
8
Absolute value of current, measured at VIL and VIH.
Weak pull up/down inactive. Measured at VDDE = 5.25 V. Applies to pad types: SH and MH.
Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately one-half for each
8 to 12 oC, in the ambient temperature range of 50 to 125 oC. Applies to pad types: A and AE.
9
This applies to the ramp up rate from 0.3 volts to 3.0 volts.
MPC5510 Microcontroller Family Data Sheet, Rev. 4
26
Freescale Semiconductor
Electrical Characteristics
2.5
Operating Current Specifications
Table 7. Operating Currents
Typ1
25C
Typ1
70C
Max1
-40–145C
Num
Characteristic
Symbol
Unit
Ambient Ambient Junction
Equations
1
I
TOTAL = IDDE + IPP + IDDA + IDDR
IDDE = IDDE1 + IDDE2 + IDDE3
VDDE(1,2,3) Current
IDDE
VDDE(1,2,3) @ 3.0V - 5.5V
Static2, or when in SLEEP or STOP
Dynamic3
1
3
30
µA
mA
Note 3
Note 3
Note 3
2
3
4
VPP Current
IPP
VPP @ 0V (All modes)
1
1
1
µA
VPP @ 5.25V
SLEEP mode
STOP mode
RUN mode
15
15
1
20
20
1
30
30
25
µA
µA
mA
VDDA Current
IDDA
VDDA @ 4.5V - 5.25V
RUN mode4
5
12
12
111
5
16
16
165
10
26
28
mA
µA
µA
µA
SLEEP/STOP5 mode with 32KIRC
SLEEP/STOP5 mode with 32KOSC
SLEEP/STOP5 mode with 16MIRC
225
VDDR Current
IDDR
VDDR@ 4.5V - 5.25V
SLEEP mode
20
500
1
0.8
170
500
30
50
105
120
25
600
1
360
900
3
µA
µA
µA
µA
µA
with XOSC6 (additonal)
with RTC/API (additonal)
each 8K RAM block (additional)
STOP mode
7
45
600
600
35
75
110
130
1500
900
40
90
120
135
with XOSC6 (additonal)
RUN mode (Using 16 MHz IRC)
RUN mode (Maximum @ 48 MHz)7
RUN mode (Maximum @ 66 MHz)8
RUN mode (Maximum @ 80MHz)9
µA
mA
mA
mA
mA
1
Typ - Nominal voltage levels and functional activity. Max - Maximum voltage levels and functional activity.
2
Static state of pins is when input pins are disabled or not being toggled and driven to a valid input level, output
pins are not toggling or driving against any current loads, and internal pull devices are disabled or not pulling
against any current loads.
3
Dynamic current from pins is application specific and depends on active pull devices, switching outputs, output
capacitive and current loads, and switching inputs. Refer to Table 8 for more information.
4
5
6
RUN mode is a typical application with the ADC, 16MIRC, 32KIRC running.
SLEEP/STOP mode means that only the listed peripherals are on. All others are diabled.
XOSC: optionally enabled in SLEEP and STOP modes (oscillator remains running from crystal but XOSC clock
output disabled).
7
RUN mode condition includes PLL selected as source of system clock, XOSC enabled with 40MHz crystal, all
peripherals enabled, both cores running, and running a typical application using both SRAM and flash.
MPC5510 Microcontroller Family Data Sheet, Rev. 4
Freescale Semiconductor
27
Electrical Characteristics
8
RUN mode condition includes PLL selected as source of system clock, XOSC enabled with 40MHz crystal; all
peripheral and cores enabled and running a typical application using both SRAM and flash. Be sure to calculate
the junction temperature, as the maximum current at maximum ambient temperature can exceed the maximum
junction temperature.
9
RUN mode condition includes PLL selected as source of system clock, XOSC enabled with 40MHz crystal, all
peripheral and cores enabled and running a typical application using both SRAM and flash. Only for 208
MAPBGA and only 120C junction or lower. Be sure to calculate the junction temperature, as the maximum current
at maximum ambient temperature can exceed the maximum junction temperature
MPC5510 Microcontroller Family Data Sheet, Rev. 4
28
Freescale Semiconductor
Electrical Characteristics
2.6
I/O Pad Current Specifications
The power consumption of an I/O segment depends on the usage of the pins on a particular segment. The power consumption
is the sum of all output pin currents for a particular segment. The output pin current can be calculated from Table 8 based on
the voltage, frequency, and load on the pin. Use linear scaling to calculate pin currents for voltage, frequency, and load
parameters that fall outside the values given in Table 8.
1
Table 8. I/O Pad Average DC Current
Frequency
(MHz)
Load2
(pF)
Slew Rate
Control
Num
Pad Type
Symbol
Voltage (V)
Current (mA)
1
2
3
4
5
6
7
8
Slow
(Pad Type SH)
IDRV_SH
25
10
50
50
5.25
5.25
5.25
5.25
5.25
5.25
5.25
5.25
11
01
00
00
11
01
00
00
8.0
3.2
0.7
2.4
17.3
6.5
1.1
3.9
2
50
2
200
50
Medium
(Pad Type MH)
IDRV_MH
50
20
50
3.33
3.33
50
200
1
2
These values are estimated from simulation and are not tested. Currents apply to output pins only.
All loads are lumped.
MPC5510 Microcontroller Family Data Sheet, Rev. 4
Freescale Semiconductor
29
Electrical Characteristics
2.7
Low Voltage Characteristics
Table 9. Low Voltage Monitors
Num
Characteristic
Symbol
Min
Typical
Max
Unit
1
2
Power-on-Reset Assert Level 1
VPOR
—
0.70
—
V
Low Voltage Monitor 1.5V 1
Assert Level
VLV15A
VLV15D
—
—
1.40
1.45
—
—
V
V
V
V
V
V
De-assert Level
3
4
5
6
7
Low Voltage Monitor 3.3V 2
Assert Level
VLV33A
VLV33D
—
—
3.05
3.10
—
—
De-assert Level
Low Voltage Monitor Synthesizer 3
Assert Level
VLVSYNA
VLVSYND
—
—
3.05
3.10
—
—
De-assert Level
Low Voltage Monitor 5.0V Low Threshold 4
Assert Level
VLV5LA
VLV5LD
3.30
3.35
3.35
3.40
3.40
3.45
De-assert Level
Low Voltage Monitor 5.0V 4
Assert Level
VLV5A
VLV5D
4.50
4.55
4.55
4.60
4.70
4.75
De-assert Level
Low Voltage Monitor 5.0V High Threshold 4
Assert Level
VLV5HA
VLV5HD
4.70
4.75
4.75
4.80
4.80
4.85
De-assert Level
1
2
3
4
Monitors VDD
Monitors VDD33
Monitors VDDSYN
Monitors VDDA
MPC5510 Microcontroller Family Data Sheet, Rev. 4
30
Freescale Semiconductor
Electrical Characteristics
2.8
Oscillators Electrical Characteristics
Table 10. 3.3V High Frequency External Oscillator
Min.
Value
Max.
Unit
Num
Characteristic
Frequency Range1
Symbol
Value
1
2
3
fref
tdc
42
40
60
MHz
%
Duty Cycle of reference
40
EXTAL Input High Voltage
External crystal mode 3
External clock mode
VIHEXT
V
VXTAL + 0.4
0.65 x VDDSYN
VDDSYN + 0.3
DDSYN + 0.3
V
4
EXTAL Input Low Voltage
External crystal mode 3
External clock mode
VILEXT
V
VDDSYN – 0.3
VDDSYN – 0.3
VXTAL – 0.4
0.35 x VDDSYN
5
6
7
8
XTAL Current 4
IXTAL
CS_XTAL
CS_EXTAL
CL
2
6
3
3
mA
pF
pF
pF
Total On-chip stray capacitance on XTAL
Total On-chip stray capacitance on EXTAL
—
—
Crystal manufacturer’s recommended
capacitive load
See crystal
specification
See crystal
specification
9
Discrete load capacitance to be connected
to EXTAL
CL_EXTAL
CL_XTAL
tstartup
—
—
—
2CL – CS_EXTAL
–
pF
pF
ms
5
CPCB_EXTAL
10
11
Discrete load capacitance to be connected
to XTAL
2CL – CS_XTAL
–
5
CPCB_XTAL
Startup Time
10
1
2
3
Since this is an amplitude controlled oscillator the use of overtone oscillators is not recommended. Only use fundamental
frequency oscillators.
When PLL frequency modulation is active, reference frequencies less than 8MHz will distort the modulated waveform and the
effects of this on emissions is not characterized.
This parameter is meant for those who do not use quartz crystals or resonators, but CAN osc, in crystal mode. In that case,
Vextal – Vxtal 400mV criteria has to be met for oscillator’s comparator to produce output clock.
Ixtal is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded.
4
5
CPCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively
Table 11. 5V Low Frequency (32 kHz) External Oscillator
Min.
Value
Max.
Value
Num
Characteristic
Frequency Range
Symbol
Unit
1
2
3
4
fref32
tdc32
IXTAL32
CL32
32
40
38
60
3
kHz
%
Duty Cycle of reference
XTAL32 Current 1
0.5
A
pF
Crystal manufacturer’s recommended
capacitive load
See crystal
specification
See crystal
specification
5
Startup Time
tstartup
—
2
s
1
Ixtal32 is the oscillator bias current out of the XTAL32 pin with both EXTAL32 and XTAL32 pins grounded.
MPC5510 Microcontroller Family Data Sheet, Rev. 4
Freescale Semiconductor
31
Electrical Characteristics
Table 12. 5V High Frequency (16 MHz) Internal RC Oscillator
Num
Characteristic
Symbol
Min
Typ
Max
Unit
Frequency before trim1
1
2
3
4
5
Fut
Ft
12.8
15.1
—
16
16
—
22.3
16.9
05
—
MHz
MHz
%
Frequency after loading factory trim2
Application trim resolution3
Ts
Fs
St
Application frequency trim step3
Start up time
—
300
—
kHz
ns
—
500
1
2
3
Across process, voltage, and temperature
Across voltage and temperature
Fixed voltage and temperature
Table 13. 5V Low Frequency (32 kHz) Internal RC Oscillator
Num
Characteristic
Frequency before trim1
Symbol
Min
Typ
Max
Unit
1
2
3
4
5
Fut32
Ft32
Ts32
Fs32
St32
20.8
26
—
32.0
32.0
—
43.2
38
kHz
kHz
%
Frequency after loading factory trim2
Application trim resolution3
2
—
Application frequency trim step3
Start up time
—
1
kHz
s
—
—
100
1
2
3
Across process, voltage, and temperature
Across voltage and temperature
Fixed voltage and temperature
MPC5510 Microcontroller Family Data Sheet, Rev. 4
32
Freescale Semiconductor
Electrical Characteristics
2.9
FMPLL Electrical Characteristics
1
Table 14. FMPLL Electrical Specifications
Min.
Value
Max.
Unit
Num
Characteristic
Symbol
Value
1
System frequency2
fsys
kHz
80000 3
66000
-40 oC TJ 120 oC
375
375
-40 oC TJ 145 oC
2
3
4
PLL Reference Frequency (output of predivider)
VCO Frequency4
fpllref
fvco
fpll
4
10
MHz
MHz
MHz
250
500
PLL Frequency 5
-40 oC TJ 120 oC
3
3
80 3
66
-40 oC TJ 145 oC
5
6
Loss of Reference Frequency 6
Self Clocked Mode Frequency 7
PLL Lock Time 8
fLOR
fSCM
tlpll
100
13
1000
35
kHz
MHz
7
—
750
4.0
2.0
5
s
8
Frequency un-LOCK Range
fUL
– 4.0
– 2.0
– 5
% fsys
% fsys
% fclkout
% fclkout
%fsys
9
Frequency LOCK Range
fLCK
Cjitter
Cjitter
Cmod
10
10a
11
CLKOUT Cycle-to-cycle Jitter,9, 10
CLKOUT Jitter at 10 µs period 9,10, 11
Frequency Modulation Depth 1% Setting 12,13
(fsysMax must not be exceeded)
– 0.05
0.5
0.05
2
12
Frequency Modulation Depth 2% Setting 12,13
(fsysMax must not be exceeded)
Cmod
1
3
%fsys
1
2
VDDSYN = 3.0V to 3.6 V, VSSSYN = 0 V, TA = TL to TH
The maximum value is without frequency modulation turned on. If frequency modulation is turned on, the maximum value
(average frequency) must be de-rated by the percentage of modulation enabled.
3
4
80 MHz is only available in the 208 pin package.
Optimum performance is achieved with the highest VCO frequency feasible based on the highest ERFD that results in the desired
PLL frequency.
5
The VCO frequency range is higher than the maximum allowable PLL frequency. The synthesizer control register 2’s enchanced
reduced frequency divider (FMPLL_SYNCR2[ERFD]) in enhanced operation mode must be programmed to divide the VCO
frequency within the PLL frequency range.
6
7
8
Loss of reference frequency is the reference frequency detected by the PLL which then transitions into self clocked mode.
Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls below fLOR
.
This specification applies to the period required for the PLL to relock after changing the enhanced multiplication factor divider
(EMFD) bits in the synthesizer control register 1 (SYNCR1) in enhanced operation mode.
9
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys
.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the PLL circuitry via VDDSYN and VSSSYN and variation in crystal oscillator frequency increase the jitter percentage
for a given interval. CLKOUT divider set to divide-by-2.
10 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of Cjitter + Cmod
.
11 The PLL % jitter reduces with more cycles. 10 µs was picked for a reference point for LIN (100 Kbits), slower speeds will have
even less % jitter.
12 Modulation depth selected must not result in fsys value greater than the fsys maximum specified value.
13 These depth ranges are obtained by filtering the raw cycle-to-cycle clock frequency data to eliminate the presence of the the
normal clock jitter riding on top of the FM waveform. The allowable modulation rates are 400 kHz to 1 MHz.
MPC5510 Microcontroller Family Data Sheet, Rev. 4
Freescale Semiconductor
33
Electrical Characteristics
2.10 eQADC Electrical Characteristics
Table 15. eQADC Conversion Specifications (Operating)
Num
Characteristic
ADC Clock (ADCLK) Frequency1
Symbol
Min
Max
Unit
1
2
FADCLK
CC
1
12
MHz
Conversion Cycles
14+2 (or 16) 14+128 (or 142)
ADCLK
cycles
3
4
5
6
7
8
9
Stop Mode Recovery Time2
Resolution
INL: 12 MHz ADC Clock3
DNL: 12 MHz ADC Clock3
Offset Error with Calibration3
Full Scale Gain Error with Calibration
Disruptive Input Injection Current 4, 5, 6, 7
TSR
—
20
1.25
—
—
—
10
10
10
10
1
s
mV
INL12
DNL12
OFFWC
GAINWC
IINJ
Counts
Counts
Counts
Counts
mA
—
—
—
—
10 Incremental Error due to injection current. All channels have
same 10k < Rs <100k8
EINJ
—
6
Counts
Channel under test has Rs=10k,
IINJ=IINJMAX,IINJMIN
11 Total Unadjusted Error for single ended conversions with
calibration3, 9, 10, 11, 12
12 Source Impedance13
TUE
RS
—
—
10
100k
Counts
Ohm
1
2
Conversion characteristics vary with FADCLK rate. Reduced conversion accuracy occurs at maximum FADCLK rate. The
maximum value is based on 800KS/s and the minimum value is based on 20MHz oscillator clock frequency divided by a
maximum 16 factor.
The specified value is for the case when the 100nF capacitor is not connected to the REFBYPC pin. When the capacitor is
connected to the REFBPYC pin, the recovery time is 10ms.
3
4
At VRH – VRL = 5.12 V, one lsb = 1.25 mV = one count.
Below disruptive current conditions, the channel being stressed has conversion values of 0x3FF for analog inputs greater than
VRH and 0x000 for values less than VRL. This assumes that VRH VDDA and VRL VSSA due to the presence of the sample
amplifier. Other channels are not affected by non-disruptive conditions.
5
6
Exceeding limit may cause conversion error on stressed channels and on unstressed channels. Transitions within the limit do
not affect device reliability or cause permanent damage.
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values using VPOSCLAMP = VDDA + 0.5V and VNEGCLAMP = – 0.3 V, then use the larger of the calculated values.
7
8
9
Condition applies to two adjacent pads on the internal pad.
At VRH – VRL = 5.12 V, one lsb = 1.25 mV = one count. This count error is in addition to the TUE count error.
The TUE specification will always be better than the sum of the INL, DNL, offset, and gain errors due to canceling errors.
10 TUE includes all internal device error such as internal reference variation (75% Ref, 25% Ref)
11 Depending on the customer input impedance, the Analog Input Leakage current (DC Electrical specification) may affect the
actual TUE measured on analog channels shared digital pins.
12 It is possible to see up to one additional count added for the 144 pin packages since the VRL and VRH functions are shared
with the VSSA and VDDA, respectively. On Analog pins above PA15, the accuracy effects from adjacent digital port pin activity
is application dependent because of frequency, level, noise, etc.
13 If RS is greater than 1 k Ohm, be sure to calculate the affect of pin leakage and use the proper sampling time, to ensure that
you get the accuracy required.
MPC5510 Microcontroller Family Data Sheet, Rev. 4
34
Freescale Semiconductor
Electrical Characteristics
2.11 Flash Memory Electrical Characteristics
1
Table 16. Flash Program and Erase Specifications
Initial
Num
Characteristic
Symbol
Min
Typ
Max3
Unit
Max2
1
2
3
4
5
6
Double Word (64 bits) Program Time 4
Page (128 bits) Program Time 4
Tdwprogram
Tpprogram
T16kpperase
T64kpperase
T128kpperase
—
—
—
—
—
—
25
10
15
—
44
500
500
s
s
16 Kbyte Block Pre-program and Erase Time
64 Kbyte Block Pre-program and Erase Time
128 Kbyte Block Pre-program and Erase Time
325
525
675
—
525
675
1800
—
5000
5000
7500
—
ms
ms
ms
MHz
Minimum operating frequency for program and erase
operations
7
Wait States Relative to System Frequency
T
MHz
rwsc
PFCRPn[RWSC] = 0b000; PFCRPn[WWSC] = 0b01
PFCRPn[RWSC] = 0b001; PFCRPn[WWSC] = 0b01
PFCRPn[RWSC] = 0b010; PFCRPn[WWSC] = 0b01
—
—
—
—
—
—
—
—
—
25
50
80
8
Recovery Time
T
recover
Stop mode exit or STOP bit negated
—
—
—
—
—
—
20
120
s
s
Sleep mode exit (with CRP_RECPTR[FASTREC]=1) 5
1
2
3
Typical program and erase times assume nominal supply values and operation at 25 oC.
Initial factory condition: 100program/erase cycles, nomial supply values and operation at 25 oC.
The maximum time is at worst case conditions after the specified number of program/erase cycles. This maximum value is
characterized but not guaranteed.
4
5
This does not include software overhead.
If CRP_RECPTR[FASTREC]=0, then hardware will wait 2340 system clocks before exiting from Sleep mode to account for the
flash recovery time. The default system clock source after Sleep is the 16MIRC. A nominal frequency of 16MHz equates to a
hardware wait of 146s.
Table 17. Flash EEPROM Module Life (Full Temperature Range)
Num
Characteristic
Symbol
Min
Typical1 Unit
1
Number of Program/Erase cycles per block over the operating
temperature range (TJ)
P/E
cycles
16 Kbyte and 64 Kbyte blocks
128 Kbyte blocks
100,000
1000
—
100,000
2
Data retention
Retention
—
years
Blocks with 0 – 1,000 P/E cycles
Blocks with 1,001 – 100,000 P/E cycles
20
5
1
Typical endurance is evaluated at 25C. Product qualification is performed to the minimum specification. For additional
information on the Freescale definition of Typical Endurance, please refer to Engineering Bulletin EB619 “Typical Endurance
for Nonvolatile Memory.”
MPC5510 Microcontroller Family Data Sheet, Rev. 4
Freescale Semiconductor
35
Electrical Characteristics
2.12 Pad AC Specifications
1
Table 18. Pad AC Specifications (VDDE = 3.0V - 5.5V)
Out Delay2, 3
(ns)
Rise/Fall3, 4
(ns)
Load Drive
(pF)
Num
Pad Type
SRC
1
Slow (SH)
11
39
120
101
188
507
597
23
23
87
50
200
50
01
00
11
01
00
52
111
248
312
12
200
50
200
50
2
Medium (MH)
64
44
200
50
50
22
90
50
200
50
261
305
—
123
156
7500
9500
200
50
4
5
Pull Up/Down (3.6V max)
Pull Up/Down (5.5V max)
—
—
—
50
1
2
These are worst case values that are estimated from simulation and not tested. The values in the table are simulated at VDDE
= 3.0V to 5.5V, TA = TL to TH.
This parameter is supplied for reference and is not tested. Add a maximum of one system clock to the output delay for delay
with respect to system clock.
3
4
Delay and rise/fall are measured to 20% or 80% of the respective signal.
This parameter is guaranteed by characterization before qualification rather than 100% tested.
VDD/2
Pad
Internal Data Input Signal
Rising
Edge
Out
Falling
Edge
Out
Delay
Delay
VOH
VOL
Pad
Output
Figure 5. Pad Output Delay
MPC5510 Microcontroller Family Data Sheet, Rev. 4
36
Freescale Semiconductor
Electrical Characteristics
2.13 AC Timing
2.13.1 Reset and Boot Configuration Pins
Table 19. Reset and Boot Configuration Timing
Num
Characteristic Symbol
Min
Max
Unit
1
2
3
RESET Pulse Width
tRPW
tRCSU
tRCH
150
—
0
—
100
—
ns
s
s
BOOTCFG Setup Time after RESET Valid
BOOTCFG Hold Time from RESET Valid
RESET
1
2
BOOTCFG
3
Figure 6. Reset and Boot Configuration Timing
2.13.2 External Interrupt (IRQ) and Non-Maskable Interrupt (NMI) Pins
Table 20. IRQ/NMI Timing
Num
Characteristic
IRQ/NMI Pulse Width Low
Symbol
Min
Max
Unit
1
2
3
tIPWL
TIPWH
tICYC
3
3
6
—
—
—
tSYS
tSYS
tSYS
IRQ/NMI Pulse Width High
IRQ/NMI Edge to Edge Time1
1
Applies when IRQ/NMI pins are configured for rising edge or falling edge events, but not both.
IRQ/NMI
1,2
1,2
3
Figure 7. IRQ and NMI Timing
MPC5510 Microcontroller Family Data Sheet, Rev. 4
Freescale Semiconductor
37
Electrical Characteristics
2.13.3 JTAG (IEEE 1149.1) Interface
1
Table 21. JTAG Interface Timing
Num
Characteristic
Symbol
Min
Max
Unit
1
2
3
4
5
6
7
8
9
TCK Cycle Time
tJCYC
tJDC
100
40
—
5
—
60
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCK Clock Pulse Width (Measured at VDDE/2)
TCK Rise and Fall Times (40% – 70%)
TMS, TDI Data Setup Time
tTCKRISE
tTMSS, TDIS
TMSH, tTDIH
tTDOV
tTDOI
t
—
—
20
—
20
—
—
50
50
50
—
—
TMS, TDI Data Hold Time
t
25
—
0
TCK Low to TDO Data Valid
TCK Low to TDO Data Invalid
TCK Low to TDO High Impedance
JCOMP Assertion Time
tTDOHZ
tJCMPPW
tJCMPS
tBSDV
—
100
40
—
—
—
50
50
10 JCOMP Setup Time to TCK Low
11 TCK Falling Edge to Output Valid
12 TCK Falling Edge to Output Valid out of High Impedance
13 TCK Falling Edge to Output High Impedance
14 Boundary Scan Input Valid to TCK Rising Edge
15 TCK Rising Edge to Boundary Scan Input Invalid
tBSDVZ
tBSDHZ
tBSDST
tBSDHT
1
These specifications apply to JTAG boundary scan only. JTAG timing specified at VDDE = 3.0V to 5.5V, TA = TL to TH, and CL
= 30pF with SRC = 0b11.
TCK
2
2
3
1
3
Figure 8. JTAG Test Clock Input Timing
MPC5510 Microcontroller Family Data Sheet, Rev. 4
38
Freescale Semiconductor
Electrical Characteristics
TCK
4
5
TMS, TDI
6
8
7
TDO
Figure 9. JTAG Test Access Port Timing
TCK
10
JCOMP
9
Figure 10. JTAG JCOMP Timing
MPC5510 Microcontroller Family Data Sheet, Rev. 4
Freescale Semiconductor
39
Electrical Characteristics
TCK
11
13
Output
Signals
12
Output
Signals
14
15
Input
Signals
Figure 11. JTAG Boundary Scan Timing
MPC5510 Microcontroller Family Data Sheet, Rev. 4
40
Freescale Semiconductor
Electrical Characteristics
2.13.4 Nexus Debug Interface
1
Table 22. Nexus Debug Port Timing
Num
Characteristic
Symbol
Min
Max
Unit
1
2
3
4
5
6
7
8
9
MCKO Cycle Time
MCKO Duty Cycle
MCKO Low to MDO Data Valid2
MCKO Low to MSEO Data Valid2
MCKO Low to EVTO Data Valid2
EVTI Pulse Width
tMCYC
tMDC
40
40
–2
–2
–2
4.0
1
—
60
ns
%
tMDOV
4.0
4.0
4.0
—
ns
tMSEOV
tEVTOV
ns
ns
tEVTIPW
tEVTOPW
tTCYC
tTCYC
tMCYC
ns
EVTO Pulse Width
TCK Cycle Time3
40
40
8
—
60
—
—
8
TCK Duty Cycle
tTDC
%
10 TDI, TMS Data Setup Time
11 TDI, TMS Data Hold Time
12 TCK Low to TDO Data Valid
t
NTDIS, tNTMSS
ns
t
NTDIH, tNTMSH
4
ns
tJOV
0
ns
1
JTAG specifications in this table apply when used for debug functionality. All Nexus timing relative to MCKO is measured from
50% of MCKO and 50% of the respective signal. Nexus timing specified at VDDE = 3.0V to 5.5V, TA = TL to TH, and CL = 30pF
with SRC = 0b11.
2
3
MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.
The system clock frequency needs to be three times faster that the TCK frequency.
1
2
MCKO
4
5
3
MDO
MSEO
EVTO
Output Data Valid
Figure 12. Nexus Output Timing
MPC5510 Microcontroller Family Data Sheet, Rev. 4
Freescale Semiconductor
41
Electrical Characteristics
TCK
10
11
TMS, TDI
12
TDO
Figure 13. Nexus TDI, TMS, TDO Timing
MPC5510 Microcontroller Family Data Sheet, Rev. 4
42
Freescale Semiconductor
Electrical Characteristics
2.13.5 External Bus Interface (EBI)
1
Table 23. External Bus Operation Timing
Num
Characteristic
Symbol
Min
Max
Unit
1
2
3
4
5
6
7
8
9
CLKOUT Period2
CLKOUT duty cycle
CLKOUT rise time
CLKOUT fall time
TC
tCDC
tCRT
40.0
45%
—
—
ns
TC
ns
ns
ns
ns
ns
ns
ns
ns
55%
3
—
3
tCFT
—
—
CLKOUT Positive Edge to Output Signal Invalid or High Z (Hold Time)
CLKOUT Positive Edge to Output Signal Valid (Output Delay)
Input Signal Valid to CLKOUT Posedge (Setup Time)
CLKOUT Posedge to Input Signal Invalid (Hold Time)
ALE Pulse Width High Time
tCOH
tCOV
2.0
—
—
10.0
—
tCIS
20.0
0
tCIH
—
tALEPWH
tALEAD
20
—
10 ALE Fall to AD Invalid
2
—
1
2
3
EBI timing specified at VDDE = 3.0V to 5.5V, TA = TL to TH, and CL = 50pF with SIU_PCRn[SRC] = 0b11.
Initialize SIU_ECCR[EBDF] to meet maximum external bus frequency.
Refer to Medium High Voltage (MH) pad AC specification in Table 18.
Voh_f
VDDE/2
Vol_f
CLKOUT
2
3
2
4
1
Figure 14. CLKOUT Timing
MPC5510 Microcontroller Family Data Sheet, Rev. 4
Freescale Semiconductor
43
Electrical Characteristics
VDDE/2
CLKOUT
6
5
VDDE/2
5
OUTPUT
BUS
VDDE/2
AD[0:31]
ADDR[8:15]
6
5
5
OUTPUT
SIGNAL
VDDE/2
BDIP
CS[0:3]
OE
RD_WR
TA
6
TEA
TS
VDDE/2
WE[0:3]
Figure 15. Synchronous Output Timing
MPC5510 Microcontroller Family Data Sheet, Rev. 4
44
Freescale Semiconductor
Electrical Characteristics
CLKOUT
VDDE/2
7
8
INPUT
BUS
VDDE/2
AD[0:31]
7
INPUT
SIGNAL
8
RD_WR
TA
VDDE/2
TEA
TS
Figure 16. Synchronous Input Timing
MPC5510 Microcontroller Family Data Sheet, Rev. 4
Freescale Semiconductor
45
Electrical Characteristics
CLKOUT
VDDE/2
TS
10
VDDE/2
AD[0:31]
9
ALE
VDDE/2
Figure 17. Address Latch Enable (ALE) Timing
2.13.6 Enhanced Modular I/O Subsystem (eMIOS)
Table 24. eMIOS Timing
Num
Characteristic
Symbol
Min
Max
Unit
1
2
eMIOS Input Pulse Width
eMIOS Output Pulse Width
tMIPW
4
1
—
—
tCYC
tCYC
tMOPW
MPC5510 Microcontroller Family Data Sheet, Rev. 4
46
Freescale Semiconductor
Electrical Characteristics
2.13.7 Deserial Serial Peripheral Interface (DSPI)
1
Table 25. DSPI Timing
66 MHz
Num
Characteristic
Symbol
Unit
Min
Max
1
2
3
4
SCK Cycle TIme2,3
PCS to SCK Delay4
After SCK Delay5
SCK Duty Cycle
tSCK
tCSC
tASC
tSDC
60
20
20
—
—
—
ns
ns
ns
ns
tSCK/2
–2ns
tSCK/2
+ 2ns
5
6
Slave Access Time
(SS active to SOUT driven)
tA
—
25
ns
ns
Slave SOUT Disable Time
tDIS
—
25
(SS inactive to SOUT High-Z or invalid)
7
8
9
PCSx to PCSS time
PCSS to PCSx time
tPCSC
tPASC
tSUI
4
5
—
—
ns
ns
Data Setup Time for Inputs
Master (MTFE = 0)
35
5
5
—
—
—
—
ns
ns
ns
ns
Slave
Master (MTFE = 1, CPHA = 0)6
Master (MTFE = 1, CPHA = 1)
35
10
11
12
Data Hold Time for Inputs
Master (MTFE = 0)
tHI
tSUO
tHO
–4
10
26
–4
—
—
—
—
ns
ns
ns
ns
Slave
Master (MTFE = 1, CPHA = 0)6
Master (MTFE = 1, CPHA = 1)
Data Valid (after SCK edge)
Master (MTFE = 0)
—
—
—
—
15
35
30
15
ns
ns
ns
ns
Slave
Master (MTFE = 1, CPHA=0)
Master (MTFE = 1, CPHA=1)
Data Hold Time for Outputs
Master (MTFE = 0)
–15
5.5
0
—
—
—
—
ns
ns
ns
ns
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
–15
1
2
DSPI timing specified at VDDE = 3.0V to 5.5V, TA = TL to TH, and CL = 50pF with SRC = 0b11.
The minimum SCK Cycle Time restricts the baud rate selection for given system clock rate. These numbers are calculated
based on two MPC55xx devices communicating over a DSPI link.
3
4
5
6
The actual minimum SCK Cycle Time is limited by pad performance.
The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]
The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC]
This number is calculated assuming the SMPL_PT bit field in DSPI_MCR is set to 0b10.
MPC5510 Microcontroller Family Data Sheet, Rev. 4
Freescale Semiconductor
47
Electrical Characteristics
2
3
PCSx
1
4
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
10
9
Last Data
SIN
First Data
Data
Data
12
11
First Data
Last Data
SOUT
Figure 18. DSPI Classic SPI Timing — Master, CPHA = 0
PCSx
SCK Output
(CPOL=0)
10
SCK Output
(CPOL=1)
9
Data
Data
First Data
Last Data
SIN
12
11
SOUT
Last Data
First Data
Figure 19. DSPI Classic SPI Timing — Master, CPHA = 1
MPC5510 Microcontroller Family Data Sheet, Rev. 4
48
Freescale Semiconductor
Electrical Characteristics
3
2
SS
1
4
SCK Input
(CPOL=0)
4
SCK Input
(CPOL=1)
5
11
12
Data
6
First Data
Last Data
SOUT
9
10
Data
Last Data
First Data
SIN
Figure 20. DSPI Classic SPI Timing — Slave, CPHA = 0
SS
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
11
5
6
12
Last Data
Data
Data
SOUT
SIN
First Data
10
9
Last Data
First Data
Figure 21. DSPI Classic SPI Timing — Slave, CPHA = 1
MPC5510 Microcontroller Family Data Sheet, Rev. 4
Freescale Semiconductor
49
Electrical Characteristics
3
PCSx
4
1
2
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
9
10
SIN
First Data
Last Data
Last Data
Data
12
11
SOUT
First Data
Data
Figure 22. DSPI Modified Transfer Format Timing — Master, CPHA = 0
PCSx
SCK Output
(CPOL=0)
SCK Output
(CPOL=1)
10
9
SIN
Last Data
First Data
Data
12
Data
11
First Data
Last Data
SOUT
Figure 23. DSPI Modified Transfer Format Timing — Master, CPHA = 1
MPC5510 Microcontroller Family Data Sheet, Rev. 4
50
Freescale Semiconductor
Electrical Characteristics
3
2
SS
1
SCK Input
(CPOL=0)
4
4
SCK Input
(CPOL=1)
12
11
6
5
First Data
9
Data
Data
Last Data
10
SOUT
Last Data
First Data
SIN
Figure 24. DSPI Modified Transfer Format Timing — Slave, CPHA = 0
SS
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
11
5
6
12
Last Data
First Data
10
Data
Data
SOUT
SIN
9
First Data
Last Data
Figure 25. DSPI Modified Transfer Format Timing — Slave, CPHA = 1
8
7
PCSS
PCSx
Figure 26. DSPI PCS Strobe (PCSS) Timing
MPC5510 Microcontroller Family Data Sheet, Rev. 4
Freescale Semiconductor
51
Package Information
3
Package Information
The latest package outline drawings are available on the product summary pages on our web site:
http://www.freescale.com/powerpc. The following table lists the package case number per device. Use these numbers in the web
page’s “keyword” search engine to find the latest package outline drawings.
Table 26. Package Information
Package
Package Case Number
144 LQFP
176 LQFP
98ASS23177W
98ASS23479W
98ARS23882W
208 MAPBGA
4
Product Documentation
Documentation is available from a local Freescale distributor, a Freescale sales office, the Freescale Literature Distribution
Center, or through the Freescale world-wide web address at http://www.freescale.com/powerpc.
MPC5510 Microcontroller Family Data Sheet, Rev. 4
52
Freescale Semiconductor
Product Documentation
4.1
Revision History
Table 27 summarizes revisions to this document.
Table 27. Revision History of MPC5510 Data Sheet
Revision
Date
Substantive Changes
Rev. 0
Rev. 1
9/2007
6/2008
Initial Release. Preliminary content.
(Note: Change descriptions refer to locations in Rev. 0.)
Changed MPC5516 to MPC5510 Family where appropriate.
Modified Figure 1. MPC5510 Family Block Diagram.
Deleted Table 1. MPC5510 Family Comparison, Maximum Feature Set
Deleted Table 2. MPC5510 Peripheral Multiplexing Examples
Corrected PK0 and PK1 pin assignments on 208 MAPBGA (Table 3 and Figure 4).
Modified Table 4, footnote 4.
Modified Table 8. DC Electrical Specifications and table footnotes.
Modified Table 9. Operating Currents and table footnotes.
Modified Table 12. 3.3V High Frequency External Oscillator, row 5.
Modified Table 14. 5V High Frequency (16 MHz) Internal RC Oscillator, row 2.
Modified Table 16. FMPLL Electrical Specifications, row 4.
Modified Table 17. eQADC Conversion Specifications (Operating) and table footnotes.
Modified Table 18. Flash Program and EraseSpecifications, row 5.
Modified Table 19. Flash EEPROM Module Life (Full Temperature Range), row 1
Modified Table 28. Package Information.
Rev. 2
12/2008
(Note: Change descriptions refer to locations in Rev. 1.)
Modified Table 1. MPC5510 Signal Properties: added note to TEST signal.
Modified Table 6. DC Electrical Specifications: rows 1b, 5, 8, 9, 10, 11, 16, 19, 25, and footnotes.
Modified Table 7. Operating Currents: Max column header, rows 1, 2, 3, 4, and footnotes.
Modified Table 9. Low Voltage Monitors: rows 2, 3, 4, 6.
Modified Table 10. 3.3V High Frequence External Oscillator: row 1 added footnote, removed
duplicate footnote #3.
Modified Table 11. 5V Low Frequency (32 kHz) External Oscillator: row 1.
Modified Table 12. 5V High Frequency (16 MHz) Internal RC Oscillator: row 2.
Modified Table 13. 5V Low Frequency (32 kHz) Internal RC Oscillator: row 2.
Modified Table 14. FMPLL Electrical Specifications: rows 1 and 4; added two new rows.
Modified Table 15. eQADC Conversion Specifications (Operating): rows 5, 6, 7, 8, 10, 11, and
footnotes.
Modified Figure 5. Pad Output Delay: moved the dashed horizontal line up so that it crosses the
signal midway between top and bottom.
Rev. 3
3/2009
(Note: Change descriptions refer to locations in Rev. 2.)
Modified Table 4. Thermal Characteristics: all values in 208 MAPBGA column.
Modified Table 6. DC Electrical Specifications: spec #1c, added footnote; spec #25, added
footnote.
Modified Table 7. Operating Currents; spec #5.
Modified Table 9. Low Voltage Monitors; spec #1.
Modified Table 14. FMPLL Electrical Specifications: updated footnote 3; added spec #10a.
Modified Table 15. eQADC Conversion Specifications (Operating): added another footnote.
Modified Table 16: Flash Program and Erase Specifications: updated spec #7.
Modified Figure 5: Pad Output Delay: adjusted lower timing diagram.
Modified Figure 8: JTAG Test Clock Input Timing; updated so that it matches the spec definitions.
Rev. 4
7/2014
Updated the VCO Min. value from 192 to 250 MHz in Table 14., “FMPLL Electrical Specifications.
MPC5510 Microcontroller Family Data Sheet, Rev. 4
Freescale Semiconductor
53
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Document Number: MPC5510
Rev. 4
7/2014
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