SPC5676RDK2MVU1 [NXP]

MPC5676R Microcontroller Data Sheet;


型号：	SPC5676RDK2MVU1
厂家：	NXP
描述：	MPC5676R Microcontroller Data Sheet PC 微控制器
文件：	总111页 (文件大小：2164K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Freescale Semiconductor

Data Sheet: Advance Information

Document Number: MPC5676R

Rev. 4, 16 Feb 2016

MPC5676R

MPC5676R Microcontroller

Data Sheet

TEPBGA–416

27 mm x 27 mm

TEPBGA–516

27mm x 27mm

On-chip modules available within the family include the

following features:

– Up to 96 eTPU2 channels (32 channels per eTPU2)

– total of 36 KB code RAM

– total of 9 KB parameter RAM

• Two identical dual issue, 32-bit CPU core complexes

(e200z7), each with

• Enhanced modular input output system supporting 32

unified channels (eMIOS) with each channel capable of

single action, double action, pulse width modulation

(PWM) and modulus counter operation

• Two enhanced queued analog-to-digital converter

(eQADC) modules with

– Power Architecture embedded specification compliance

– Instruction set enhancement allowing variable length

encoding (VLE), optional encoding of mixed 16-bit and

32-bit instructions, for code size footprint reduction

– Signal processing extension (SPE) instruction support

for digital signal processing (DSP)

– two separate analog converters per eQADC module

– support for a total of 64 analog input pins, expandable to

176 inputs with off-chip multiplexers

– Single-precision floating point operations (FPU)

– 16 KB I-Cache and 16 KB D-Cache

– Hardware cache coherency between cores

• 16 Hardware semaphores

• 3 channel CRC module

• 6MB on-chip flash

– Supports read during program and erase operations, and

multiple blocks allowing EEPROM emulation

• 384KB on-chip general-purpose SRAM including 48KB of

standby RAM

• Two multi-channel direct memory access controllers

(eDMA)

– one absolute reference ADC channel

– interface to twelve hardware decimation filters

– enhanced ‘Tap’ command to route any conversion to two

separate decimation filters

– Temperature sensor

• Five deserial serial peripheral interface (DSPI) modules

• Three enhanced serial communication interface (eSCI)

modules

• Four controller area network (FlexCAN) modules

• Dual-channel FlexRay controller

• Nexus development interface (NDI) per IEEE-ISTO

5001-2003 standard, with some support for 2010 standard.

• Device and board test support per Joint Test Action Group

(JTAG) (IEEE 1149.1)

• On-chip voltage regulator controller regulates supply

voltage down to 1.2 V for core logic

– 64 channels per eDMA

• Dual core Interrupt controller (INTC)

• Phase-locked loop with FM modulation (FMPLL)

• Crossbar switch architecture for concurrent access to

peripherals, flash, or RAM from multiple bus masters

• External Bus Interface (EBI) for calibration and

application development

• Self Test capability

• System integration unit (SIU) with error correction status

module (ECSM)

• Four protected port output pins (PPO)

• Boot assist module (BAM) supports serial bootload via

CAN or SCI

• Three second-generation enhanced time processor units

(eTPU2)

This document contains information on a product under development. Freescale reserves

the right to change or discontinue this product without notice.

Table of Contents

Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

4.7.2 I/O Pad V_DD33Current Specifications . . . . . . . 24

4.7.3 LVDS Pad Specifications . . . . . . . . . . . . . . . . . 25

4.8 Oscillator and FMPLL Electrical Characteristics . . . . . 27

4.9 eQADC Electrical Characteristics . . . . . . . . . . . . . . . . 29

4.10 C90 Flash Memory Electrical Characteristics . . . . . . . 31

4.11 AC Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.11.1 Clocking Modes . . . . . . . . . . . . . . . . . . . . . . . . 32

4.11.2 Pad AC Specifications . . . . . . . . . . . . . . . . . . . 33

4.12 AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.12.1 Generic Timing Diagrams. . . . . . . . . . . . . . . . . 34

4.12.2 Reset and Configuration Pin Timing. . . . . . . . . 35

4.12.3 IEEE 1149.1 Interface Timing. . . . . . . . . . . . . . 36

4.12.4 Nexus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4.12.5 External Bus Interface (EBI) Timing. . . . . . . . . 41

4.12.6 External Interrupt Timing (IRQ Pin) . . . . . . . . . 46

4.12.7 eTPU Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4.12.8 eMIOS Timing . . . . . . . . . . . . . . . . . . . . . . . . . 47

4.12.9 DSPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5.1 416-Pin Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5.2 516-Pin Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

1.1 Orderable Parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

MPC5676R Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

3.1 416-ball TEPBGA Pin Assignments . . . . . . . . . . . . . . . .6

3.2 516-ball TEPBGA Pin Assignments . . . . . . . . . . . . . . . .7

3.3 Pin Muxing and Reset States . . . . . . . . . . . . . . . . . . . . .8

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

4.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

4.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .9

4.2.1 General Notes for Specifications at

Maximum Junction Temperature . . . . . . . . . . . .11

4.3 EMI (Electromagnetic Interference) Characteristics . . .12

4.4 ESD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .13

4.5 PMC/POR/LVI Electrical Specifications . . . . . . . . . . . .13

4.5.1 Regulator Example . . . . . . . . . . . . . . . . . . . . . .16

4.6 Power Up/Down Sequencing . . . . . . . . . . . . . . . . . . . .18

4.6.1 Power-Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

4.6.2 Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . .19

4.6.3 Power Sequencing and POR Dependent

on V_DDA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

4.7 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .20

4.7.1 I/O Pad Current Specifications . . . . . . . . . . . . .23

Appendix ASignal Properties and Muxing . . . . . . . . . . . . . . . . . . 59

Appendix BRevision History . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Ordering Information

1.1

Orderable Parts

Figure 1 and Table 1describe and list the orderable part numbers for the MPC5676R.

PC 5676R K2 M VU 1

Qualification status

Core code

Device number

(Optional) Dual-core identifier

Fab/Revision

Temperature range

Package identifier

Operating frequency

Tape and reel status

Temperature Range

M = –40 °C to 125 °C

Package Identifier

VU = 416 TEPBGA

Pb-Free

Operating Frequency Tape and Reel Status

1 = 2 x 180 MHz

R = Tape and reel

(blank) = Trays

VY = 516 TEPBGA

Pb-Free

Qualification Status

P = Pre qualification

M = Fully spec. qualified, general market flow

S = Fully spec. qualified, automotive flow

Note: Not all options are available on all devices. Refer to Table 1.

Figure 1. MPC5676R Orderable Part Number Description

Table 1. Orderable Part Numbers

Speed (MHz)²

Operating Temperature³

NXP Part Number¹

SPC5676RDK2MVU1R

SPC5676RDK2MVY1R

Package Description

Nominal

Max⁴(f_MAX

)

Min (T_L)

Max (T_H)

MPC5676R 416 package

Lead-free (Pb-free)

180

184

–40 °C

125 °C

MPC5676R 516 package

Lead-free (Pb-free)

180

184

–40 °C

125 °C

All packaged devices are PPC5676R, rather than MPC5676R or SPC5676R, until product qualifications are complete. The

unpackaged device prefix is PCC, rather than SCC, until product qualification is complete.

Not all configurations are available in the PPC parts.

For the operating mode frequency of various blocks on the device, see Table 28.

The lowest ambient operating temperature is referenced by T_L; the highest ambient operating temperature is referenced by T_H.

Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including frequency modulation (FM).

180 MHz parts allow for 180 MHz system clock + 2% FM.

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

MPC5676R Blocks

2.1

Block Diagram

The following figure shows a top-level block diagram of the MPC5676R. The purpose of the block diagram is to show the

general interconnection of functional modules through the crossbar switch and from the Dual Interrupt Controller, and provide

an indication of the modules that connect to external pins. For clarity, the following modules are omitted from the diagram:

PMU, SWT, STM, PIT, ECSM, DTS, and CRC.

Power Architecture

e200z7 Core

Power Architecture

e200z7 Core

JTAG

MPC5676R

SPE

VLE

SPE

VLE

Nexus

IEEE-ISTO

5001-2003

Dual Interrupt

Controller

MMU

16K

eDMA2

64 Channels

eDMA2

64 Channels

EBI

(Calibration)

FlexRay

I-Cache D-Cache

Crossbar Switch

MPU

384KB

I/O

BridgeA

I/O

BridgeB

Boot Assist

Module

6MB

FLASH

FMPLL

STCU

SIUA

SRAM

Semaphores

(48KB S/B)

eQADC eQADC

6KB

Data

RAM

3KB

Data

RAM

SIUB

12 x DECFILT

eMIOS

eTPU2

Channel

eTPU2

Channel

Channel Channel

24KB

Code

RAM

12KB

Code

RAM

PPO

AMux

LEGEND

I-Cache – Instruction Cache

ADC

– Analog to Digital Convertor

AMux – Analog Pin Multiplexer

D-Cache– Data Cache

DECFILT– Decimation Filter

DSPI

EBI

eDMA2 – Enhanced Direct Memory Access controller version 2

eMIOS – Enhanced Modular I/O System

eQADC – Enhanced Queued Analog to Digital Converter

IRC

– Internal RC Oscillator

JTAG

MMU

MPU

PPO

S/B

– Joint Test Action Group controller

– Memory Management Unit

– Memory Protection Unit

– Protected Port Output

– Stand-by

– Deserial/Serial Peripheral Interface

– External Bus Interface

SIUA

SIUB

SPE

– System Integration Unit A

– System Integration Unit B

– Signal Processing Engine

eSCI

– Enhanced Serial Communications Interface

eTPU2 – Enhanced Time Processing Unit version 2

FlexCAN– Flexible Controller Area Network controller

FMPLL – Frequency Modulated Phase Lock Loop clock generator

SRAM – Static RAM

STCU – Self Test Control Unit

VLE

– Variable Length instruction Encoding

Figure 2. MPC5676R Block Diagram

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Pin Assignments

3.1

416-ball TEPBGA Pin Assignments

Figure 3 shows the 416-ball TEPBGA pin assignments.

CAUTION

This ball map is preliminary and subject to change. Do not use it for board design.

REF–

ANA4

ANA8

ANA11

ANA15 VDDA_A0

VRL_A VRH_A

AN28

AN32

AN36 VDDA_B0

AN33 VDDA_B1

VRL_B VRH_B

ANB7

ANB11

ANB14 ANB17 ANB21 ANB23

VSS

VDD

RSTOUT ANA0

BYPCA1

BYPCB1

REF–

AN24

REF–

ANB6

ANA14 VDDA_A1 VSSA_A1

AN27

AN26

AN25

AN29

AN30

AN31

ANB8

ANB5

ANB9

ANB10 ANB15 ANB18 ANB22

VSS

TCRCLKC

VDDEH1

VSS

VDD

TEST

VDD

ANA1

ANA2

VDD

ANA5

ANA6

ANA3

ANA10

ANA9

ANA7

VSSA_B0

AN38

BYPCA

BYPCB

ANA13 ANA17 ANA19 ANA21 ANA23

ANA12 ANA16 ANA18 ANA20 ANA22

AN34

AN35

AN37

AN39

ANB0

ANB2

ANB4

ANB3

ANB12 ANB16 ANB19

VSS

ETPUC0 ETPUC1

ETPUC2 ETPUC3

ETPUA30 ETPUA31 VSS

ANB1

ANB13 ANB20

VSS

VDDEH7

ETPUA27 ETPUA28 ETPUA29 VSS

ETPUA23 ETPUA24 ETPUA25 ETPUA26

ETPUA19 ETPUA20 ETPUA21 ETPUA22

ETPUA15 ETPUA16 ETPUA17 ETPUA18

ETPUA11 ETPUA12 ETPUA14 ETPUA13

ETPUA7 ETPUA8 ETPUA9 ETPUA10

ETPUA3 ETPUA4 ETPUA5 ETPUA6

TCRCLKA ETPUA0 ETPUA1 ETPUA2

VDDEH7 ETPUC4 ETPUC5 ETPUC6

ETPUC7 ETPUC8 ETPUC9 ETPUC10

ETPUC11 ETPUC12 ETPUC13 ETPUC14

ETPUC15 ETPUC16 ETPUC17 ETPUC18

ETPUC19 ETPUC20 ETPUC21ETPUC22

ETPUC23 ETPUC24ETPUC25ETPUC26

ETPUC27ETPUC28ETPUC29ETPUC30

ETPUC31ETPUB15 ETPUB14 VDDEH7

VDDEH6 ETPUB11 ETPUB12 ETPUB13

ETPUB7 ETPUB8 ETPUB9 ETPUB10

ETPUB3 ETPUB4 ETPUB5 ETPUB6

TCRCLKB ETPUB0 ETPUB1 ETPUB2

ETPUB19 ETPUB18 ETPUB17 ETPUB16

ETPUB26 ETPUB22 ETPUB21 ETPUB20

REGSEL ETPUB25 ETPUB24 ETPUB23

ETPUB29 ETPUB28 ETPUB27 REGCTL

VDD33_3 ETPUB30 VDDREG VSSSYN

MPC5676R 416-ball TEPBGA

(as viewed from top through the package)

VSS

VDD33_1 TXDA

RXDA

VSTBY

VSS

BOOT–

RXDB

VDDE2

WKPCFG VDD

CFG1

VDDE2 VDDE2

TXDB

PLLCFG2 VDDEH1

PLLCFG1

JCOMP RESET PLLCFG0 RDY

VDDE2 MCKO MSEO1

EVTO MSEO0 MDO0

EVTI

MDO1

MDO5

VDDE2 VDDE2 VDDE2

MDO2

MDO6

MDO3

MDO7

MDO4

MDO8 VDDE2

MDO9 MDO10 MDO11 MDO15

MDO12 MDO13 MDO14 VDD33_2

VSSFL

TDO

TCK

TDI

TMS

VDD

VSS

VDD

VSS

VDD ETPUB31

EXTAL

PCSA1 PCSA2 PCSB4 PCSB1 VDDEH3 VDDEH4

VDD

EMIOS8 EMIOS14 EMIOS18 EMIOS22 EMIOS27 EMIOS31 CNRXB CNRXD VDDEH5 PCSC1

VSS

VDD

VSS

VDDEH6 XTAL

VDD VDDSYN

AC VDDE2

VDDE2

FR_A_ FR_B_

TX TX

EMIOS5 EMIOS9 EMIOS15 EMIOS19 EMIOS23 EMIOS26 EMIOS30

RXDC

SINC

PCSC3

AD ENGCLK VDD

PCSA5 SOUTA

SCKA

SCKB

PCSB0 PCSB3 EMIOS2

CNTXB CNTXD

SCKC

FR_A_ FR_B_

RX RX

PCSA4 PCSA0 PCSA3

SINB

EMIOS0 EMIOS3 EMIOS6 EMIOS10 EMIOS13 EMIOS17 EMIOS21 EMIOS25 EMIOS29 CNRXA CNRXC PCSC0

PCSC2 PCSC5

VSS

VDD

VSS

FR_A_ FR_B_

TX_EN TX_EN

EMIOS7 EMIOS11 EMIOS12 EMIOS16 EMIOS20 EMIOS24 EMIOS28

VDDEH4 TXDC

PCSC4 VDDEH5

VSS

VDDE2

VDDEH3 PCSB5

SINA

PCSB2 SOUTB EMIOS1 EMIOS4

10 11

CNTXA CNTXC SOUTC

19 20 21

Figure 3. MPC5676R 416-ball TEPBGA (full diagram)

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Pin Assignments

3.2

516-ball TEPBGA Pin Assignments

Figure 4 shows the 516-ball TEPBGA pin assignments.

REF–

VDD

RSTOUT ANA0

ANA4

ANA9

ANA11

ANA15 VDDA_A0

VRL_A VRH_A

AN28

AN29

AN36 VDDA_B0

VRL_B VRH_B

ANB5

ANB9

ANB12 ANB18 ANB21

VSS

BYPCA1

BYPCB1

REF–

AN24

REF–

ANB4

VDDEH1

VSS

VDD

TEST

VDD

ANA1

ANA2

VDD

ANA5

ANA6

ANA3

VDD

ANA10 ANA14 VDDA_A1 VSSA_A1

AN27

AN25

AN26

VSS

AN30

AN31

AN33

VSS

AN32 VDDA_B1 VSSA_B0

ANB8

ANB6

ANB10 ANB13 ANB19 ANB22

VSS

BYPCA

BYPCB

ETPUA30 ETPUA31 VSS

ANA7

ANA8

VSS

ANA13 ANA17 ANA19 ANA21 ANA22

ANA12 ANA16 ANA18 ANA20 ANA23

AN34

AN35

VSS

AN39

AN38

VSS

AN37

ANB1

VSS

ANB0

ANB2

VSS

ANB7

ANB3

ANB11

ANB15 ANB20

VSS

ETPUC0 ETPUC1

ETPUA27 ETPUA28 ETPUA29 VSS

ANB14 ANB16 ANB17

VSS

VDDEH7 ETPUC2 ETPUC3

ETPUA23 ETPUA24 ETPUA25 ETPUA26 VSS

ETPUA19 ETPUA20 ETPUA21 ETPUA22 VSS

ETPUA11 ETPUA13 ETPUA15 ETPUA17 ETPUA18

VSS

ANB23

VSS

VDDEH7 ETPUC4 ETPUC5 ETPUC6

VDDE8

VDDE8 VDDE8

VSS

VDDE10 VDDE10

VDDE10

VDDE10 TCRCLKC ETPUC7 ETPUC8 ETPUC9 ETPUC10

ETPUC11 ETPUC12 ETPUC13 ETPUC14 ETPUC15

MPC5676R 516-ball TEPBGA

ETPUA5 ETPUA7 ETPUA8 ETPUA3 ETPUA14 ETPUA16

ETPUA1 ETPUA2 ETPUA9 ETPUA4 ETPUA12

ETPUC19 ETPUC16 ETPUC17 ETPUC18 ETPUC20 ETPUC21

ETPUC22 ETPUC23 ETPUC24 ETPUC26 ETPUC27

(as viewed from top through the package)

TXDB

TXDA

RXDA TCRCLKA ETPUA6 ETPUA10

VSS

ETPUC25 ETPUC28 ETPUC29 ETPUC30 ETPUC31 D_DAT15

VDD33_6 D_DAT14 D_DAT13 D_DAT12 D_DAT11 D_DAT10

D_DAT9 D_DAT8 D_DAT7 D_DAT5 VDDEH7

BOOT– BOOT–

RXDB ETPUA0

PLLCFG1 PLLCFG2

CFG1

CFG0

VSS

VDD33_1 D_BDIP PLLCFG0 VSTBY WKPCFG

D_WE0 D_WE2 D_WE3

VDD

RESET VDDE8

VDDE2

VDDE10 D_DAT6 VDDEH6 D_DAT2 D_DAT3 D_DAT4

D_ADD9 D_ADD10 D_ADD11 VDDEH1 D_WE1 VDD33_1

D_ADD12 D_ADD13 D_ADD14 D_ADD15 D_ADD16

VDDE2 VDDE2

VDDE10 ETPUB13 D_OE

D_ALE D_DAT0 D_DAT1

D_RD_

ETPUB9 ETPUB12 ETPUB14 ETPUB15

VDDE2

D_ADD18 D_ADD19 D_ADD20 D_ADD17 D_CS3

VDDE2 VDDE2 VDDE2

ETPUB17 ETPUB3 ETPUB7 ETPUB8 ETPUB10 ETPUB11

ETPUB23 ETPUB1 ETPUB2 ETPUB4 ETPUB5 ETPUB6

ETPUB21 ETPUB22 ETPUB16 TCRCLKB ETPUB0

D_CS2 JCOMP

RDY

MDO0

MDO6

MCKO MSEO1 MSEO0

EVTI

MDO4

MDO7

EVTO

MDO5

MDO2

MDO3

MDO8

VDDE2

MDO1

VSS

ETPUB25 ETPUB29 REGSEL ETPUB20 ETPUB19 ETPUB18

ETPUB31 ETPUB26 ETPUB27 ETPUB24 REGCTL

MDO9 MDO10 MDO11 MDO12

AA MDO13 MDO14 MDO15 VDD33_1 VDDE8

PCSA5

SCKA

SCKB

SOUTB VDD33_4

VDDE9 VDD33_4

EMIOS23 EMIOS31

CNRXB

VSS

VDDE10 VDD33_3 ETPUB28 VDDREG VSSSYN AA

TDO

TCK

TDI

TMS

VDD

VSS

VDD

VSS

VDDE9 VDDE9

SINB

D_CS1 D_ADD21 D_ADD29 EMIOS1 EMIOS11 EMIOS17 EMIOS19 EMIOS29 VDDE9 VDDE9 VDDE9 VDDE9

VSS

VDD ETPUB30 VSSFL

EXTAL AB

EMIOS0 EMIOS8 EMIOS13 EMIOS22 EMIOS24 EMIOS28 CNTXB CNRXD VDDEH5 PCSC1

VSS

VDD

VSS

VDDEH6 XTAL

AC VDDE2

AD ENGCLK

VDDE2 PCSA1 SOUTA

FR_B_

PCSB3 VDDEH3 VDDEH4

VDD

FR_A_

VDD

VSS

PCSA0 PCSA3 PCSB2 D_CS0 D_ADD22 D_ADD25 D_ADD28 EMIOS2 EMIOS7 EMIOS12 EMIOS16 EMIOS18 EMIOS27 CNRXA CNTXD

SCKC

RXDC

SINC

PCSC3

VDD VDDSYN AD

FR_A_

FR_B_

VDD

PCSA4 PCSB5

SINA

PCSB1

D_TS D_ADD23 D_ADD26 D_ADD30 EMIOS3 EMIOS6 EMIOS10 EMIOS15 EMIOS21 EMIOS26 CNTXA CNRXC PCSC0

PCSC2 PCSC5

VSS

VDD

CLKOUT

FR_A_

FR_B_

VDDE2

VDDEH3 PCSA2 PCSB4 PCSB0

D_TA D_ADD24 D_ADD27

EMIOS4 EMIOS5 EMIOS9 EMIOS20 EMIOS14 EMIOS25 EMIOS30 CNTXC SOUTC VDDEH4 TXDC

PCSC4 VDDEH5

TX_EN TX_EN

Figure 4. MPC5676R 516-ball TEPBGA (full diagram)

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

3.3

Pin Muxing and Reset States

See Appendix A, Signal Properties and Muxing, for a listing and description of the pin functions and properties.

Electrical Characteristics

This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing

specifications for the MPC5676R.

The electrical specifications are preliminary and are from previous designs, design simulations, or initial evaluation. These

specifications may not be fully tested or guaranteed at this early stage of the product life cycle, however for production silicon

these specifications will be met. Finalized specifications will be published after complete characterization and device

qualifications have been completed.

4.1

Maximum Ratings

Table 2. Absolute Maximum Ratings

Spec

Characteristic

1.2 V Core Supply Voltage³

Symbol

Min

Max²

Unit

V_DD

V_STBY

V_DDSYN

V_DD33

–0.3

–0.1

–0.3

–0.1

–3 ¹³

1.65 ⁴

5,6

SRAM Standby Voltage

5.5

Clock Synthesizer Voltage

4.5 ^6,7

5.5 ^5,6

4.5 ⁶

5.5 ^5,6

5.5^5,6

5.5 ^5,6

0.1

I/O Supply Voltage (I/O buffers and predrivers)

Analog Supply Voltage (reference to V_SSA

)

V_DDA

I/O Supply Voltage (fast I/O pads)

V_DDE

V_DDEH

V_DDREG

I/O Supply Voltage (medium I/O pads)

Voltage Regulator Input Supply Voltage

Analog Reference High Voltage (reference to V_RL

)

V_RH

_SSto V_SSA⁸Differential Voltage

V_SS– V_SSA

V_RH– V_RL

_REFDifferential Voltage

5.5 ^5,6

0.3

V_RLto V_SSADifferential Voltage

V_RL– V_SSA

V_DD33– V_DDSYN

V_SSSYN– V_SS

I_MAXD

_DD33to V_DDSYNDifferential Voltage

_SSSYNto V_SSDifferential Voltage

0.1

Maximum Digital Input Current ¹²(per pin, applies to all

digital pins)

3 ¹³

Maximum Analog Input Current ¹⁴(per pin, applies to all

analog pins)

I_MAXA

–3 ^9,13

3 ^9,13

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

Spec

Table 2. Absolute Maximum Ratings (continued)

Characteristic

Symbol

Min

Max²

Unit

Maximum Operating Temperature Range ¹⁵– Die Junction

Temperature

T_J

–40.0

150.0

^oC

Storage Temperature Range

T_stg

T_sdr

–55.0

150.0

^oC

Maximum Solder Temperature ¹⁶

Pb-free package

—

260.0

245.0

SnPb package

Moisture Sensitivity Level ¹⁷

MSL

—

Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only,

and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device reliability or

cause permanent damage to the device.

Absolute maximum voltages are currently maximum burn-in voltages. Absolute maximum specifications for device stress have

not yet been determined.

1.2 V ±10% for proper operation. This parameter is specified at a maximum junction temperature of 150 °C.

2.0 V for 10 hours cumulative time, 1.2 V +10% for time remaining.

6.4 V for 10 hours cumulative time, 5.0 V +10% for time remaining.

Voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance.

4.5 V for 10 hours cumulative time, 3.3 V +10% for time remaining.

MPC5676R has two analog power supply pins on the pinout: VDDA_A and VDDA_B.

MPC5676R has two analog ground supply pins on the pinout: VSSA_A and VSSA_B.

¹⁰MPC5676R has two analog low reference voltage pins on the pinout: VRL_A and VRL_B.

¹¹MPC5676R has two analog high reference voltage pins on the pinout: VRH_A and VRH_B.

¹²Total injection current for all pins must not exceed 25 mA at maximum operating voltage.

¹³Injection current of ±5 mA allowed for limited duration for analog (ADC) pads and digital 5 V pads. The maximum accumulated

time at this current shall be 60 hours. This includes an assumption of a 5.25 V maximum analog or V_DDEHsupply when under

this stress condition.

¹⁴Total injection current for all analog input pins must not exceed 15 mA.

¹⁵Lifetime operation at these specification limits is not guaranteed.

¹⁶Solder profile per CDF-AEC-Q100.

¹⁷Moisture sensitivity per JEDEC test method A112.

4.2

Thermal Characteristics

Table 3. Thermal Characteristics, 416-pin TEPBGA Package

Characteristic

Symbol

Value

Unit

Junction to Ambient ^2,3Natural Convection (Single layer board)

Junction to Ambient ^2,4Natural Convection (Four layer board 2s2p)

Junction to Ambient (@200 ft./min., Single layer board)

R_JA

°C/W

R_JMA

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

Table 3. Thermal Characteristics, 416-pin TEPBGA Package (continued)

Characteristic

Symbol

Value

Unit

Junction to Ambient (@200 ft./min., Four layer board 2s2p)

Junction to Board ⁵

R_JMA

R_JB

R_JC

_JT

°C/W

Junction to Case ⁶

Junction to Package Top ⁷Natural Convection

Thermal characteristics are targets based on simulation that are subject to change per device

characterization.

Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting

site (board) temperature, ambient temperature, air flow, power dissipation of other components on the

board, and board thermal resistance.

Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification.

Per JEDEC JESD51-6 with the board horizontal.

Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board

temperature is measured on the top surface of the board near the package.

Indicates the average thermal resistance between the die and the case top surface as measured by the

cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case

temperature.

Thermal characterization parameter indicating the temperature difference between package top and the

junction temperature per JEDEC JESD51-2.

Table 4. Thermal Characteristics, 516-pin TEPBGA Package

Characteristic

Symbol

Value

Unit

Junction to Ambient ^2,3Natural Convection (Single layer board)

Junction to Ambient ^2,4Natural Convection (Four layer board 2s2p)

Junction to Ambient (@200 ft./min., Single layer board)

Junction to Ambient (@200 ft./min., Four layer board 2s2p)

Junction to Board ⁵

R_JA

R_JMA

R_JB

R_JC

_JT

°C/W

Junction to Case ⁶

Junction to Package Top ⁷Natural Convection

Thermal characteristics are targets based on simulation that are subject to change per device

characterization.

Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting

site (board) temperature, ambient temperature, air flow, power dissipation of other components on the

board, and board thermal resistance.

Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification.

Per JEDEC JESD51-6 with the board horizontal.

Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board

temperature is measured on the top surface of the board near the package.

Indicates the average thermal resistance between the die and the case top surface as measured by the

cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case

temperature.

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

Thermal characterization parameter indicating the temperature difference between package top and the

junction temperature per JEDEC JESD51-2.

4.2.1

General Notes for Specifications at Maximum Junction Temperature

An estimation of the chip junction temperature, T , can be obtained from the equation:

T = T + (R

* P )

Eqn. 1

JA

where:

T = ambient temperature for the package ( C)

= junction to ambient thermal resistance ( C/W)

JA

P = power dissipation in the package (W)

The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal

performance. Unfortunately, there are two values in common usage: the value determined on a single layer board and the value

obtained on a board with two planes. For packages such as the TEPBGA, these values can be different by a factor of two. Which

value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a

single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal

planes is usually appropriate if the board has low power dissipation and the components are well separated.

When a heat sink is used, the thermal resistance is expressed as the sum of a junction to case thermal resistance and a case to

ambient thermal resistance:

= R

+ R

CA

Eqn. 2

JA

JC

where:

= junction to ambient thermal resistance ( C/W)

JA

JC

CA

= junction to case thermal resistance ( C/W)

= case to ambient thermal resistance ( C/W)

is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to

JC

ambient thermal resistance, R

. For instance, the user can change the size of the heat sink, the air flow around the device, the

CA

interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit

board surrounding the device.

To determine the junction temperature of the device in the application when heat sinks are not used, the Thermal

Characterization Parameter ( ) can be used to determine the junction temperature with a measurement of the temperature at

the top center of the package case using the following equation:

T = T + ( x P )

Eqn. 3

where:

T = thermocouple temperature on top of the package ( C)



= thermal characterization parameter ( C/W)

P = power dissipation in the package (W)

The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied

to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the

package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm. of wire extending from the

junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects

of the thermocouple wire.

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

References:

Semiconductor Equipment and Materials International

3081 Zanker Road

San Jose, CA 95134

(408) 943-6900

MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or

303-397-7956.

JEDEC specifications are available on the WEB at http://www.jedec.org.

•

C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive Engine

Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47-54.

G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled Applications,” Electronic

Packaging and Production, pp. 53-58, March 1998.

B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its Application

in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212-220.

4.3

EMI (Electromagnetic Interference) Characteristics

To find application notes that provide guidance on designing your system to minimize interference from radiated emissions, go

to www.nxp.com and perform a keyword search for “radiated emissions.” The following tables list the values of the device's

radiated emissions operating behaviors.

Table 5. EMC Radiated Emissions Operating Behaviors: 416 BGA

f_OSC

f_SYS

Frequency

band (MHz)

Level

(max.)

Symbol

Description

Conditions

Unit Notes

V_{RE_TEM}

Radiated emissions,

electric field and

magnetic field

V_DD= 1.2 V

V_DDE= 3.3 V

V_DDEH= 5 V

T_A= 25 °C

416 BGA

EBI off

40 MHz crystal

180 MHz

(f_{EBI_CAL}= 46

MHz)

0.15–50

50–150

I²

dBV

150–500

500–1000

1, 3

CLK off

FM off

IEC and SAE level

—

V_{RE_TEM}

Radiated emissions,

electric field and

magnetic field

V_DD= 1.2 V

V_DDE= 3.3 V

40 MHz crystal

180 MHz

(f_{EBI_CAL}= 46

MHz)

0.15–50

50–150

K⁵

dBV

V_DDEH= 5 V

T_A= 25 °C

416 BGA

EBI off

150–500

500–1000

1,3

CLK off

IEC and SAE level

—

FM on⁴

Determined according to IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell

Method, and SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated Circuits—TEM/Wideband TEM

(GTEM) Cell Method.

I = 36 dBV

Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband

TEM Cell Method, and Appendix D of SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated

Circuits—TEM/Wideband TEM (GTEM) Cell Method.

“FM on” = FM depth of ±2%

K = 30 dBV

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

4.4

ESD Characteristics

1,2

Table 6. ESD Ratings

Spec

Characteristic

Symbol

Value

Unit

ESD for Human Body Model (HBM)

ESD for Charged Device Model (CDM)

V_HBM

V_CDM

2000

750 (corners)

500 (other)

All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade

Integrated Circuits.

A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device

specification requirements. Complete DC parametric and functional testing shall be performed per applicable

device specification at room temperature followed by hot temperature, unless specified otherwise in the

device specification.

4.5

PMC/POR/LVI Electrical Specifications

Table 7. PMC Operating conditions

Spec

Name

Parameter

Condition

Min

Typ

Max

Unit

V_DDREG

Supply voltage VDDREG LDO5V / SMPS5V mode

5 V nominal¹

4.5

5.5

V_DDREG

V_DD33

V_DD

Supply voltage VDDREG LDO3V mode

3 V nominal¹

3.0

3.3

1.2

3.6

Supply voltage VDDSYN / LDO3V mode

V_DD333.3 V nominal²

Supply voltage VDD

1.2 V nominal³

—

1.14

1.32

Voltage should be higher than maximum V_LVDREGto avoid LVD event

Applies to both V_DD33(flash supply) and VDDSYN (PLL supply) pads. Voltage should be higher than maximum V_LVD33

to avoid LVD event

Voltage should be higher than maximum V_LVD12to avoid LVD event

NOTE

In the following table, “untrimmed” means “at reset” and “trimmed” means “after reset”.

Table 8. PMC Electrical Specifications

Spec

Name

Symbol

Condition

Min

Typ

Max

Unit

Nominal bandgap reference

voltage

V_BG

—

0.59

0.620

0.65

1a Bandgap reference voltage

during power on reset

—

V_BG– 5%

V_BG– 2%

V_BG

V_BG+ 5%

V_BG+ 2%

1b Bandgap reference voltage at

nominal voltage / nominal

temperature after power on

reset

V_BG

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

Table 8. PMC Electrical Specifications

Spec

Name

Symbol

Condition

Min

Typ

Max

Unit

1c Bandgap reference voltage /

temperature dependence after

power on reset

—

300

—

ppm/C

1d Bandgap reference voltage /

—

1500

1.2

—

voltage dependence (V_DDREG

after power on reset

)

Nominal VRC regulated 1.2V

output VDD¹

V_DD12OUT

—

2a VRC 1.2V output variation at

reset (unloaded)²

—

At POR

V_DD12OUT– 8% V_DD12OUTV_DD12OUT+ 10%

2b VRC 1.2V output variation after

reset(REGCTL load max.

After POR V_DD12OUT– 5% V_DD12OUTV_DD12OUT+ 10%

20mA, VDD load max. 1A)

2c Trimming step Vdd1p2

V_STEPV12

V_PORC

—

0.7

—

POR rising VDD 1.2V

V_PORC– 30%

—

V_PORC+ 30%

—

3a POR VDD 1.2V variation

3b POR 1.2V hysteresis

—

V_PORC

—

Nominal rising LVD 1.2V³

V_LVD12

—

1.100

V_LVD12

—

4a LVD 1.2V variation before band

gap trim⁴

At POR

V_LVD12– 6%

V_LVD12+ 6%

4b LVD 1.2V variation after band

gap trim⁴

—

After POR

V_LVD12– 3%

V_LVD12

V_LVD12+ 3%

4c LVD 1.2V Hysteresis

—

4d Trimming step LVD 1.2V

V_LVDSTEP12

I_REGCTL

VRC 1.2V max DC output

current

Voltage regulator 1.2V current

consumption VDDREG

—

Nominal Vreg 3.3V output⁵

V_DD33OUT

—

3.3

—

7a Vreg 3.3V output variation at

reset (unloaded)⁶

At POR

V_DD33OUT– 6% V_DD33OUTV_DD33OUT+ 10%

7b Vreg 3.3V output variation after

reset (max. load 60mA)

—

After POR V_DD33OUT– 5% V_DD33OUTV_DD33OUT+ 10%

7c Trimming step VDDSYN

V_STEPV33

V_LVD33

—

Nominal rising LVD 3.3V⁷

2.950

V_LVD33

8a LVD 3.3V variation before band

gap trim⁶

At POR

V_LVD33– 5%

V_LVD33+ 5%

8b LVD 3.3V variation after bad gap

trim⁶

—

After POR

V_LVD33– 3%

V_LVD33

V_LVD33+ 3%

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

Table 8. PMC Electrical Specifications

Spec

Name

Symbol

Condition

Min

Typ

Max

Unit

8c LVD 3.3V Hysteresis

—

8d Trimming step LVD 3.3V

V_LVDSTEP33

I_DD33

Vreg 3.3V minimum peak DC

output current supplied by

regulator without causing

V_LVD33

10 Voltage regulator 3.3V current

consumption VDDREG⁹

—

11 POR rising on VDDREG

11a POR VDDREG variation

11b POR VDDREG hysteresis

12 Nominal rising LVD VDDREG

V_PORREG

—

2.00

V_PORREG– 30% V_PORREGV_PORREG+ 30%

—

250

—

V_LVDREG

LDO3V /

LDO5V

mode

2.950

12a LVD VDDREG variation at

reset¹⁰

—

At POR

V_LVDREG– 5% V_LVDREGV_LVDREG+ 5%

12b LVD VDDREG variation after

reset¹⁰

After POR

V_LVDREG– 3% V_LVDREGV_LVDREG+ 3%

12c LVD VDDREG Hysteresis

12d Trimming step LVD VDDREG

13 Nominal rising LVD VDDREG

LDO3V /

LDO5V

mode

—

V_LVDSTEPREG

LDO3V /

LDO5V

mode

V_LVDREG

SMPS5V

mode

4.360

13a LVD VDDREG variation at

reset¹⁰

—

At POR

After POR

—

V_LVDREG– 5% V_LVDREGV_LVDREG+ 5%

13b LVD VDDREG variation after

reset¹⁰

V_LVDREG– 3% V_LVDREGV_LVDREG+ 3%

14 SMPS regulator output

resistance¹¹

—

Ohm

15 SMPS regulator clock frequency

—

After POR

1.0

—

1.5

—

MHz

16 SMPS regulator overshoot at

start-up¹²

GBD/GBC¹³

1.32

1.4

17 SMPS maximum output current,

as required by SoC¹⁴

—

1.0

—

18 Voltage variation on current step

(20% to 80% of maximum

current with 4 usec constant

time)¹⁴

GBD/GBC¹³

0.1

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

Nominal internal regulator output voltage is 1.27V

Voltage should be higher than maximum VLVD12 to avoid LVD event

~VDD12OUT *0.87

Rising VDD

Nominal internal regulator output voltage is 3.4V

Rising VDDSYN

~VDD33OUT *0.872

VDDSYN

Except IDD33

¹⁰Rising VDDREG

¹¹Pull up to VDDREG when high, pull down to VSSREG when low.

¹²Depends on external device, can be as high as 1.6V for short time (<100 usec each start-up)

¹³GBD — Guaranteed By Design; GBC — Guaranteed by Characterization

¹⁴Proper external devices required

4.5.1

Regulator Example

VDDREG

The resistor may or may

not be required.

This depends on the

allowable power dissipation of

the npn bypass transistor

device.

IPP_INA_SMPS_SEL5

The bypass transistor

MUST be operated out

of saturation region.

VRCCTL

VDD1p2

MCU

Mandatory decoupling capacitor

network

VSS

VRCCTL capacitor: may or

may not be required

Figure 5. VRC 1.2 V LDO configuration with external bipolar

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

VDDREG

IPP_INA_SMPS_SEL5

VRCCTL

MCU

VDD1p2

VSS

Mandatory decoupling capacitor

network

No VRCCTL capacitor is allowed

Figure 6. VRC 1.2V buck SMPS LDO configuration with external MOS - Schottky diode

Table 9. VRC LDO recommended external devices

Part Name

Part Type

Nominal

Description

ON Semiconductor TM

NJD2873

Beta (Bf)

Vbe

NPN

From 60 to 550

From 0.4 V to 1.0 V

Vce

From 0.2 V to 0.6 V depends on package / power

Capacitor 6 x 4.7 uF - 20 V Ceramic low ESR—One for each VDD pin

Capacitor 6 x 0.1 uF - 20 V Ceramic —One capacitor for each VDD pin

Capacitor 20 uF

Capacitor 2.2 uF

Supply decoupling cap (close to bipolar collector)

Snubber cap, required with NJD2873 (on bipolar base)

Optional ESR for snubber cap

Resistor

12 

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

Table 10. VRC SMPS recommended external devices

Part Name

Part Type

Nominal

Description

IR7353

HS nMOS +

Schottky

Low threshold n-MOS/Low Vf Schottky diode

SS8P3L

Schottky

Low Vf Schottky diode

From 0.4V to 0.6 V

SI3460 or equivalent

Vth

nMOS

Low threshold n-MOS

Less than 2 V

Ids

More than 1.5 A

Vds

More than 12 V

Rdson

Less than 100 Ohms

Less than 5 nF

Turn on / off delay

Rise time

Less than 50 ns

Less than 90 ns

LQH66SN2R2M03

C3225X7R1E106M

C3225X7R1E225K

inductor

2.2 uH—3.2 A

22 uF — 25 V

muRata TM shielded coil, preferred f_max> 40 MHz

TDK high capacitance ceramic SMD (on VDD close to coil)

TDK ceramic SMD (on VDD close to MCU)

capacitor

capacitor 2 to 6 x 2.2 uF

— 25 V

capacitor

6 x 0.1 uF

— 20 V

Ceramic -One capacitor for each VDD pin

C3225X7R1E106M

capacitor

resistor

22 uF — 25 V

20 K

Supply decoupling cap—close to n-MOS drain

Pull down for power n—MOS gate

4.6

Power Up/Down Sequencing

There is no power sequencing required among power sources during power up and power down in order to operate within

specification as long as the following two rules are met:

•

When VDDREG is tied to a nominal 3.3V supply, VDD33 and VDDSYN must be both shorted to VDDREG.

When VDDREG is tied to a 5V supply, VDD33 and VDDSYN must be tied together and shall be powered by the

internal 3.3V regulator.

The recommended power supply behavior is as follows: Use 25 V/millisecond or slower rise time for all supplies. Power up

each V /V first and then power up V . For power down, drop V to 0 V first, and then drop all V /V

DDE DDEH

supplies. There is no limit on the fall time for the power supplies.

Although there are no power up/down sequencing requirements to prevent issues like latch-up, excessive current spikes, etc.,

the state of the I/O pins during power up/down varies according to Table 11 and Table 12.

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

Table 11. Power Sequence Pin States for MH and AE pads

VDD

VDD33

VDDE

MH Pad

MH+LVDS Pads¹

AE/up-down Pads

High

—

High

Low

High

Normal operation

Pin is tri-stated (output buffer,

input buffer, and weak pulls

disabled)

Outputs driven high

Pull-ups enabled,

pull-downs disabled

Low

High

Low

Output low,

pin unpowered

Outputs disabled

Output low,

pin unpowered

High

Pin is tri-stated (output buffer,

input buffer, and weak pulls

disabled)

Pull-ups enabled,

pull-downs disabled

MH+LVDS pads are output-only.

Table 12. Power Sequence Pin States for F and FS pads

VDD

VDD33

VDDE

F and FS pads

low

high

low

high

—

Outputs drive high

Outputs Disabled

Outputs drive high

high

low

high

low

high

Normal operation - except no drive current

and input buffer output is unknown.¹

high

Normal Operation

The pad pre-drive circuitry will function normally but since VDDE is unpowered

the outputs will not drive high even though the output pmos can be enabled.

4.6.1

Power-Up

If V

is powered up first, then a threshold detector tristates all drivers connected to V

. There is no limit

DDE DDEH

to how long after V

powers up before V must power up. If there are multiple V

supplies, they can

DDE DDEH

be powered up in any order. For each V

supply not powered up, the drivers in that V

segment exhibit

DDE DDEH

the characteristics described in the next paragraph.

If V is powered up first, then all pads are loaded through the drain diodes to V

/V . This presents a heavy load that

DDE DDEH

pulls the pad down to a diode above V . Current injected by external devices connected to the pads must meet the current

injection specification. There is no limit to how long after V powers up before V

must power up.

DDE DDEH

The rise times on the power supplies are to be no faster than 25 V/millisecond.

4.6.2

Power-Down

If V is powered down first, then all drivers are tristated. There is no limit to how long after V powers down before

must power down.

DDE DDEH

If V

is powered down first, then all pads are loaded through the drain diodes to V

. This presents a heavy

DDE DDEH

load that pulls the pad down to a diode above V . Current injected by external devices connected to the pads must meet the

current injection specification. There is no limit to how long after V

powers down before V must power down.

DDE DDEH DD

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

There are no limits on the fall times for the power supplies.

4.6.3

Power Sequencing and POR Dependent on V_DDA

During power up or down, V

can lag other supplies (of magnitude greater than V

/2) within 1 V to prevent any

DDA

DDEH

forward-biasing of device diodes that causes leakage current and/or POR. If the voltage difference between V

is more than 1 V, the following will result:

and V

DDEH

DDA

•

Triggers POR (ADC monitors on V

segment which powers the RESET pin) if the leakage current path created,

DDEH1

when V

level.

is sufficiently low, causes sufficient voltage drop on V

node monitored crosses low-voltage detect

DDA

DDEH1

•

If V

out of reset.

is between 0–2 V, powering all the other segments (especially V

) will not be sufficient to get the part

DDEH1

DDA

Each V

up to (V

will have a leakage current to V

of a magnitude of ((V

– V

– 1 V(diode drop)/200 KOhms)

DDA

DDEH

DDA

DDEH

/2 = V

+ 1 V). .

DDEH

DDA

Each V has the same behavior; however, the leakage will be small even though there is no current limiting resistor

since V = 1.32 V max.

4.7

DC Electrical Specifications

Table 13. DC Electrical Specifications

Spec

Characteristic

Symbol

Min

Max

Unit

Core Supply Voltage (External Regulation)

Core Supply Voltage (Internal Regulation)⁴

I/O Supply Voltage (fast I/O pads)

I/O Supply Voltage (medium I/O pads)

3.3 V I/O Buffer Voltage

V_DD

1.14

1.08

3.0

1.32^{2, 3}

1.32

V_DDE

3.6²

V_DDEH

V_DD33

3.0

5.25²

3.6²

3.0

Analog Supply Voltage

V_DDA

4.75

0.95⁵

5.25²

1.2

SRAM Standby Voltage low range

SRAM Standby Voltage high range

Voltage Regulator Control Input Voltage⁶

Clock Synthesizer Operating Voltage⁸

V_{STBY_LOW}

V_{STBY_HIGH}

V_DDREG

V_DDSYN

V_{IH_F}

2.7⁷

3.0

5.5²

3.6²

Fast I/O Input High Voltage

Hysteresis enabled

_DDE+ 0.3

0.65 × V_DDE

0.55 × V_DDE

Hysteresis disabled

Fast I/O Input Low Voltage

Hysteresis enabled

V_{IL_F}

V_SS– 0.3

0.35 × V_DDE

0.40 × V_DDE

Hysteresis disabled

Medium I/O Input High Voltage

Hysteresis enabled

V_{IH_S}

V_DDEH+ 0.3

0.65 × V_DDEH

Hysteresis disabled

0.55 × V

DDEH

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

Spec

Table 13. DC Electrical Specifications (continued)

Characteristic

Symbol

Min

Max

Unit

Medium I/O Input Low Voltage

V_{IL_S}

V_SS– 0.3

Hysteresis enabled

Hysteresis disabled

0.35 × V_DDEH

0.40 × V_DDEH

Fast I/O Input Hysteresis

V_{HYS_F}

V_{HYS_S}

V_INDC

V_{OH_F}

V_{OH_S}

V_{OL_F}

V_{OL_S}

0.1 × V_DDE

0.1 × V_DDEH

V_SSA– 0.1

0.8 × V_DDE

0.8 × V_DDEH

—

Medium I/O Input Hysteresis

Analog Input Voltage

—

V_DDA+ 0.1

—

Fast I/O Output High Voltage⁹

Medium I/O Output High Voltage¹⁰

Fast I/O Output Low Voltage⁹

Medium I/O Output Low Voltage

—

0.2 × V_DDE

—

0.2 × V_DDEH

0.15 × V_DDEH

Load Capacitance (Fast I/O)¹²

DSC(PCR[8:9]) = 0b00

DSC(PCR[8:9]) = 0b01

DSC(PCR[8:9]) = 0b10

DSC(PCR[8:9]) = 0b11

C_L

—

Input Capacitance (Digital Pins)

C_IN

—

Input Capacitance (Analog Pins)

C_{IN_A}

C_{IN_M}

Input Capacitance (Digital and Analog Pins¹³

)

Operating Current 1.2 V Supplies @ f_sys= 180 MHz

V_DD(including V_DDFcurrent)@1.32 V

V_STBY¹⁴@1.2 V and 85^oC

V_STBY@6.0 V and 85^oC

V_DDF¹⁵(P/E)

I_DD

I_DDSTBY

—

1.0¹⁶

0.10

I_DDSTBY6

I_DDFPE

I_DDFREAD

I_DDFRWW

I_DDplTANDBY

I_DDFDISABLED

0.15

36¹⁷

V_DDF¹⁵(Read)

50¹⁷

V_DDF¹⁵(RWW)

90¹⁷

V_DDF¹⁵(Standby)

0.20¹⁷

0.10¹⁷

V_DDF¹⁵(Disabled)

Operating Current 3.3 V Supplies @ f_sys= 180 MHz

note¹⁸

7²⁰

V_DD33

V_DDSYN

I_DD33

I_DDSYN

I_DDFLASHPE

—

V_FLASH¹⁹(P/E)

V_FLASH¹⁹(Read)

V_FLASH¹⁹(RWW)

V_FLASH¹⁹(Standby)

V_FLASH¹⁹(Disabled)

32²¹

I_DDFLASHREADS

I_DDFLASHRWW

I_{DDFLASHSTANDBY}

I_{DDFLASHDISABLED}

6.4²¹

40²¹

3.4²¹

0.10²¹

Operating Current 5.0 V Supplies @ f_sys= 180 MHz

V_DDA

I_DDA

I_REF

I_REG

—

50²²

1.0

Analog Reference Supply Current (Transient)

V_DDREG

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

Table 13. DC Electrical Specifications (continued)

Spec

Characteristic

Symbol

Min

Max

Unit

Operating Current V_DDE/V_DDEH²³Supplies

V_DDE2

I_DD2

I_DD1

I_DD3

I_DD4

I_DD5

I_DD6

I_DD7

—

V_DDEH1

V_DDEH3

V_DDEH4

V_DDEH5

V_DDEH6

V_DDEH7

note²³

Fast I/O Weak Pull Up/Down Current²⁴

3.0 V–3.6 V

I_{ACT_F}

I_{ACT_S}

158

A

Medium I/O Weak Pull Up/Down Current²⁵

3.0 V–3.6 V

4.5 V–5.5 V

200

A

I/O Input Leakage Current²⁶

DC Injection Current (per pin)

I_{INACT_D}

I_IC

–2.5

–1.0

–250

2.5

1.0

A

Analog Input Current, Channel Off²⁷, AN[0:7], AN38,

AN39

I_{INACT_A}

250

Analog Input Current, Channel Off, all other analog

inputs AN[x] = -/+ 150nA

–150

150

_SSDifferential Voltage

Analog Reference Low Voltage

_RLDifferential Voltage

Analog Reference High Voltage

V_SS– V_SSA

V_RL

V_RL– V_SSA

V_RH

–100

V_SSA

–100

V_DDA– 100

4.75

100

V_SSA+ 100

100

V_DDA

5.25

_REFDifferential Voltage

V_RH– V_RL

V_SSSYN– V_SS

T_A(T_Lto T_H)

—

_SSSYNto V_SSDifferential Voltage

–100

–40.0

—

100

^C

Operating Temperature Range—Ambient (Packaged)

Slew rate on power supply pins

125.0

V/ms

k

Weak Pull-Up/Down Resistance^28,29200 k Option

Weak Pull-Up/Down Resistance^28,29100 k Option

R_PUPD200K

R_PUPD100K

R_PUPD5K

130

280

140

k

Weak Pull-Up/Down Resistance²⁸(5 k Option)

5 V ± 10% supply

k

1.4

1.7

5.2

7.7

3.3 V ± 10% supply

Pull-Up/Down Resistance Matching Ratios

(100K/200K)

R_PUPDMATCH

–2.5

2.5

(Pull-up and pull-down resistances both enabled and

settings are equal)

These specifications are design targets and subject to change per device characterization.

Voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance.

2.0 V for 10 hours cumulative time, 1.2 V +10% for time remaining.

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

Assumed with DC load.

V_STBYbelow 0.95 V the RAM will not retain states, but will be operational. V_STBYcan be 0 V when bypass standby mode.

Regulator is functional with derated performance, with supply voltage down to 4.0 V for system with V_DDREG= 4.5 V (min).

2.7 V minimum operating voltage allowed during vehicle crank for system with V_DDREG= 3.0 V (min). Normal operating voltage

should be either V_DDREG= 3.0 V (min) or 4.5 V (min) depending on the user regulation voltage system selected.

Required to be supplied when 3.3 V regulator is disabled. See Section 4.5, “PMC/POR/LVI Electrical Specifications.”

I_{OH_F}= {12,20,30,40} mA and I_{OL_F}= {24,40,50,65} mA for {00,01,10,11} drive mode with V_DDE= 3.0 V.

= {11.6} mA and IOL_S = {17.7} mA for {medium} I/O with V_DDEH= 4.5 V;

OH_S

I_{OH_S}= {5.4} mA and IOL_S = {8.1} mA for {medium} I/O with V_DDEH= 3.0 V

I = 2 mA

OL_S

¹²Applies to D_CLKOUT, external bus pins, and Nexus pins.

¹³Applies to the FCK, SDI, SDO, and SDS_B pins.

current specified at 1.0 V at a junction temperature of 85 ^oC. V_STBYcurrent is 700 µA maximum at a junction

STBY

temperature of 150 ^oC.

¹⁵VDDF pin is shorted to V_DDon the package substrate.

¹⁶Preliminary. Specification pending typical and/or high-use Runidd pattern simulation as well as final silicon characterization.

1.0 A based on transistor count estimate at Worst Case (wcs) process and temperature condition.

¹⁷Typical values from the simulation.

¹⁸Power requirements for the V_DD33supply depend on the frequency of operation and load of all I/O pins, and the voltages on

the I/O segments. See Section 4.7.2, “I/O Pad V_DD33Current Specifications,” for information on both fast (F, FS) and medium

(MH) pads. Also refer to Table 15 for values to calculate power dissipation for specific operation.

¹⁹VFLSH pin is shorted to V_DD33on the package substrate.

²⁰This value is a target that is subject to change.

²¹Typical values from the simulation.

²²These value allows a 5 V 20 mA reference to supply ADC + REF.

²³Power requirements for each I/O segment depend on the frequency of operation and load of the I/O pins on a particular I/O

segment, and the voltage of the I/O segment. See Section 4.7.1, “I/O Pad Current Specifications,” for information on I/O pad

power. Also refer to Table 14 for values to calculate power dissipation for specific operation. The total power consumption of

an I/O segment is the sum of the individual power consumptions for each pin on the segment.

²⁴Absolute value of current, measured at V_ILand V_IH.

²⁵Absolute value of current, measured at V_ILand V_IH.

²⁶Weak pull up/down inactive. Measured at V_DDE= 3.6 V and V_DDEH= 5.25 V. Applies to pad types F and MH.

²⁷Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately one-half for each

8 to 12 ^oC, in the ambient temperature range of 50 to 125 ^oC. Applies to pad types AE and AE/up-down.

²⁸This programmable option applies only to eQADC differential input channels and is used for biasing and sensor diagnostics.

²⁹When the pull-up and pull-down of the same nominal 200 k or 100 k value are both enabled, assuming no interference from

external devices, the resulting pad voltage will be 0.5*V_DDEH± 2.5%.

4.7.1

I/O Pad Current Specifications

The power consumption of an I/O segment is dependent on the usage of the pins on a particular segment. The power

consumption is the sum of all output pin currents for a particular segment. The output pin current can be calculated from

Table 14 based on the voltage, frequency, and load on the pin. Use linear scaling to calculate pin currents for voltage, frequency,

and load parameters that fall outside the values given in Table 14.

The AC timing of these pads are described in the Section 4.11.2, “Pad AC Specifications.”

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

Table 14. V

I/O Pad Average DC Current

DDE DDEH

Frequency

(MHz)

Load²

(pF)

Voltage

(V)

Drive/Slew

Rate Select

Spec

Pad Type

Symbol

Current (mA)

Medium

I_{DRV_MH}

200

5.25

3.6

16.0

6.3

3.0

2.0

1.1

2.4

Fast

I_{DRV_FC}

6.5

3.6

9.4

3.6

10.8

33.3

2.0

3.6

1.98

3.6

3.0

4.4

15.1

12.0

6.2

Fast w/ Slew

Control

I_{DRV_FSR}

3.6

33.33

3.6

4.0

3.6

2.4

3.6

8.9

These are average IDDE numbers for worst case PVT from simulation. Currents apply to output pins only.

All loads are lumped.

4.7.2

I/O Pad V_DD33Current Specifications

The power consumption of the V_DD33supply is dependent on the usage of the pins on all I/O segments. The power consumption

is the sum of all input and output pin V_DD33currents for all I/O segments. The V_DD33current draw on fast speed pads can be

calculated from Table 15 dependent on the voltage, frequency, and load on all F type pins. The V_DD33current draw on medium

pads can be calculated from Table 15 dependent on voltage and independent on the frequency and load on all MH type pins.

Use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in

Table 15.

The AC timing of these pads are described in the Section 4.11.2, “Pad AC Specifications.”

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

Table 15. V

Pad Average DC Current

DD33

Frequency

(MHz)

Load²

(pF)

V_DD33

(V)

V_DDE

(V)

Drive/Slew

Rate Select

Spec

Pad Type

Symbol

Current (mA)

Medium

Fast

I_{33_MH}

I_{33_FC}

—

200

3.6

5.5

3.6

—

0.0007

0.92

1.14

1.50

2.19

0.70

0.90

1.08

1.52

0.74

0.52

0.36

0.19

3.6

1.98

3.6

Fast w/

Slew

Control

I_{33_FSR}

3.6

33.33

3.6

These are average IDD33 for worst case PVT from simulation. Currents apply to output pins only for the fast pads and to input

pins only for the medium pads.

All loads are lumped.

4.7.3

LVDS Pad Specifications

LVDS pads are implemented to support the MSC (Microsecond Channel) protocol, which is an enhanced feature of the DSPI

module.

1, 2

Table 16. DSPI LVDS Pad Specification

(V_DD33= 3.0 V to 3.6 V, V_DDEH= 4.75 V to 5.25 V, T_A= T_Lto T_H)

Spec

Characteristic

Symbol

Min

Typical

Max

Unit

Data Rate

Data Frequency

f_LVDSCLK

—

MHz

Driver Specs

Differential Output Voltage

SRC=0b00 or 0b11

V_OD

215

170

260

—

400

320

480

SRC=0b01

SRC=0b10

Common Mode Voltage (LVDS), VOS

Rise/Fall Time

V_OS

t_Ror t_F

t_DZ

1.075

—

1.2

—

1.325

2.5

Delay, Z to Normal (High/Low)

—

100

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

1, 2

Table 16. DSPI LVDS Pad Specification

(continued)

(V_DD33= 3.0 V to 3.6 V, V_DDEH= 4.75 V to 5.25 V, T_A= T_Lto T_H)

Differential Skew between Positive and Negative

LVDS Pair

t_Skew

—

0.5

I t_phla– t_plhbI or I t_plhb– t_phla

Termination

Termination Resistance³

Load

R_Load

—

100

—

105

ohm

These are typical values that are estimated from simulation.

These specifications are subject to change per device characterization.

The termination resistance spec is not meant to specify the receiver termination requirements. They are there to establish the

measurement criteria for the specs in this table. As per the TIA/EIA-644A standard, the LVDS receiver termination resistance

can vary from 90 to 132  .

4.8

Oscillator and FMPLL Electrical Characteristics

Table 17. FMPLL Electrical Specifications

(V_DDSYN= 3.0 V to 3.6 V, V_SS= V_SSSYN= 0 V, T_A= T_Lto T_H)

Spec

Characteristic

Symbol

Min

Max

Unit

PLL Reference Frequency Range²(Normal Mode)

Crystal Reference (PLLCFG2 = 0b0)

Crystal Reference (PLLCFG2 = 0b1)

External Reference (PLLCFG2 = 0b0)

External Reference(PLLCFG2 = 0b1)

MHz

f_{ref_crystal}

f_{ref_ext}

40³

f_{ref_ext}

PLL Frequency ⁴

Enhanced Mode

f_PLL

f_LOR

f_SCM

t_LPLL

t_DC

f_vco(min) 64

f_max

1000

MHz

kHz

Loss of Reference Frequency⁵

Self Clocked Mode Frequency⁶

PLL Lock Time⁷

100

MHz

s

—

<750

Duty Cycle of Reference ^{8, 9}

Frequency un-LOCK Range

Frequency LOCK Range

f_UL

–4.0

–2.0

–5

4.0

2.0

% f_sys

f_LCK

C_Jitter

D_CLKOUT Period Jitter^{10, 11}Measured at f_SYSMax

Cycle-to-cycle Jitter

%f_clko

12,13

Peak-to-Peak Frequency Modulation Range Limit

C_mod

%f_sys

(f_sysMax must not be exceeded)

FM Depth Tolerance¹⁴

C_{mod_err}

f_VCO

–0.25

192

0.400

0.25

600

%f_sys

MHz

VCO Frequency

Modulation Rate Limits¹⁵

Predivider Operating Frequency

f_mod

f_prediv

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

All values given are initial design targets and subject to change.

Crystal and External reference frequency limits depend on device relying on PLL to lock prior to release of reset, default

PREDIV/EPREDIV, MFD/EMFD default settings, and VCO frequency range. Absolute minimum loop frequency is 4 MHz.

Upper tolerance of less than 1% is allowed on 40MHz crystal.

All internal registers retain data at 0 Hz.

“Loss of Reference Frequency” is the reference frequency detected internally, which transitions the PLL into self clocked mode.

Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls below f_LOR. This

frequency is measured at D_CLKOUT with the divider set to divide-by-2 of the system clock. NOTE: in SCM, the PLL is running

open loop at a centercode 0x4. The MFD has no effect and the RFD is bypassed.

This specification applies to the period required for the PLL to re-lock after changing the MFD frequency control bits in the

synthesizer control register (SYNCR). From power up with crystal oscillator reference, lock time will be additive with crystal

startup time.

For FlexRay operation, duty cycle requirements are higher.

Duty cycle can be 20–80% when PLL is used with a pre-divider greater than 1.

¹⁰Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f_sys

Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise

injected into the PLL circuitry via V_DDSYNand V_SSSYNand variation in crystal oscillator frequency increase the Cjitter

percentage for a given interval. D_CLKOUT divider set to divide-by-2.

¹¹Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of C_jitter+ C_mod

¹²Modulation depth selected must not result in f_pllvalue greater than the f_pllmaximum specified value.

¹³Maximum and minimum variation from programmed modulation depth is pending characterization. Depth settings available in

control register are: 1%, 2%, 3%, and 4% peak-to-peak.

¹⁴Depth tolerance is the programmed modulation depth ±0.25% of F_sys. Initial design target pending silicon evaluation.

¹⁵Modulation rates less than 400 kHz will result in exceedingly long FM calibration durations. Modulation rates greater than 1 MHz

will result in reduced calibration accuracy.

Table 18. Oscillator Electrical Specifications

(V_DDSYN= 3.0 V to 3.6 V, V_SS= V_SSSYN= 0 V, T_A= T_Lto T_H)

Spec

Characteristic

Symbol

Min

Max

Unit

| V_extal– V_xtal

> 0.4 V

Crystal Mode Differential Amplitude²

(Min differential voltage between EXTAL and XTAL)

crystal_diff_amp

—

Crystal Mode: Internal Differential Amplifier Noise

Rejection

V_{crystal_diff_amp_nr}

—

| V_extal– V_xtal

< 0.2 V

EXTAL Input High Voltage

V_IHEXT

((V

/2) + 0.4 V)

—

DD33

Bypass mode, External Reference

—

EXTAL Input Low Voltage

V_ILEXT

/2) – 0.4 V

DD33

Bypass mode, External Reference

XTAL Current³

I_XTAL

—

Total On-chip stray capacitance on XTAL

C_{S_XTAL}

1.5

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

Table 18. Oscillator Electrical Specifications (continued)

(V_DDSYN= 3.0 V to 3.6 V, V_SS= V_SSSYN= 0 V, T_A= T_Lto T_H)

Spec

Characteristic

Symbol

Min

—

Max

Unit

Total On-chip stray capacitance on EXTAL

C_{S_EXTAL}

C_L

1.5

Crystal manufacturer’s recommended capacitive

load

See crystal spec

—

Discrete load capacitance to be connected to EXTAL

C_{L_EXTAL}

(2 × C – C

S_EXTA

– C

PCB_EXTAL )

Discrete load capacitance to be connected to XTAL

C_{L_XTAL}

(2 × C – C

L S_XTAL

– C

PCB_XTAL )

All values given are initial design targets and subject to change.

This parameter is meant for those who do not use quartz crystals or resonators, but instead use CAN oscillators in crystal mode. In

that case, V_extal– V_xtal 400 mV criterion has to be met for oscillator’s comparator to produce output clock.

I_xtalis the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded.

C_{PCB_EXTAL}and C_{PCB_XTAL}are the measured PCB stray capacitances on EXTAL and XTAL, respectively.

4.9

eQADC Electrical Characteristics

Table 19. eQADC Conversion Specifications (Operating)

Spec

Characteristic

Symbol

Min

Max

Unit

ADC Clock (ADCLK) Frequency

Conversion Cycles

f_ADCLK

2 + 13

128 + 14

—

MHz

ADCLK cycles

s

Stop Mode Recovery Time¹

T_SR

Resolution²

—

1.25

–4⁴

–8⁴

–3⁴

0⁴

—

INL: 8 MHz ADC Clock³

INL8

4⁴

LSB⁵

LSB

INL: 16 MHz ADC Clock³

INL16

DNL8

DNL16

OFFNC

OFFWC

GAINNC

GAINWC

I_INJ

8⁴

DNL: 8 MHz ADC Clock³

3⁴

LSB

DNL: 16 MHz ADC Clock³

3⁴

LSB

Offset Error without Calibration

Offset Error with Calibration

Full Scale Gain Error without Calibration

Full Scale Gain Error with Calibration

Disruptive Input Injection Current ^{7, 8, 9, 10}

Incremental Error due to injection current^{11, 12}

TUE value at 8 MHz ^{13, 14}(with calibration)

100⁴

4⁴

LSB

–4⁴

–120⁴

–4^4,6

–1

LSB

0⁴

LSB

4^4,6

LSB

m

E_INJ

—

+4⁴

+4^4,6

Counts

TUE8

—

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

Table 19. eQADC Conversion Specifications (Operating) (continued)

Spec

Characteristic

Symbol

Min

Max

Unit

TUE value at 16 MHz ^{13, 14}(with calibration)

TUE16

—

Counts

Variable gain amplifier accuracy (gain=1)¹⁵

INL, 8 MHz ADC

GAINVGA1

Counts¹⁷

–4

–8

INL, 16 MHz ADC

DNL, 8 MHz ADC

DNL, 16 MHz ADC

–3¹⁶

3¹⁶

Variable gain amplifier accuracy (gain=2)¹⁵

INL, 8 MHz ADC

GAINVGA2

GAINVGA4

Counts

–5

–8

–3

INL, 16 MHz ADC

DNL, 8 MHz ADC

DNL, 16 MHz ADC

Variable gain amplifier accuracy (gain=4)¹⁵

INL, 8 MHz ADC

–7

–8

–4

INL, 16 MHz ADC

DNL, 8 MHz ADC

DNL, 16 MHz ADC

Stop mode recovery time is the time from the setting of either of the enable bits in the ADC Control Register to the time

that the ADC is ready to perform conversions.Delay from power up to full accuracy = 8 ms.

At V_RH– V_RL= 5.12 V, one count = 1.25 mV without using pregain.

INL and DNL are tested from V_RL+ 50 LSB to V_RH– 50 LSB.

New design target. Actual specification will change following characterization. Margin for manufacturing has not been fully

included.

At V_RH– V_RL= 5.12 V, one LSB = 1.25 mV.

The value is valid at 8 MHz, it is ±8 counts at 16 Mhz.

Below disruptive current conditions, the channel being stressed has conversion values of $3FF for analog inputs greater

than V_RHand $000 for values less than V_RL. Other channels are not affected by non-disruptive conditions.

Exceeding limit may cause conversion error on stressed channels and on unstressed channels. Transitions within the limit

do not affect device reliability or cause permanent damage.

Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,

calculate resistance values using V_POSCLAMP= V_DDA+ 0.5 V and V_NEGCLAMP= –0.3 V, then use the larger of the

calculated values.

¹⁰Condition applies to two adjacent pins at injection limits.

¹¹Performance expected with production silicon.

All channels have same 10 k < Rs < 100 kChannel under test has Rs = 10 k, I_INJ=I_{INJMAX INJMIN}.

¹³The TUE specification is always less than the sum of the INL, DNL, offset, and gain errors due to cancelling errors.

¹⁴TUE does not apply to differential conversions.

¹⁵Variable gain is controlled by setting the PRE_GAIN bits in the ADC_ACR1-8 registers to select a gain factor of 1, 2, or

4. Settings are for differential input only. Tested at 1 gain. Values for other settings are guaranteed by as indicated.

¹⁶Guaranteed 10-bit mono tonicity.

¹⁷At V_RH– V_RL= 5.12 V, one LSB = 1.25 mV.

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

4.9.1

ADC Internal Resource Measurements

Table 20. Power Management Control (PMC) Specification

Spec

Characteristic

Symbol

Min

Typical

Max

Unit

PMC Normal Mode

Bandgap 0.62 V

ADC0 channel 145

V_ADC145

V_ADC146

V_ADC147

V_ADC180

V_ADC181

V_ADC182

V_ADC183

0.59

0.62

1.22

0.65

Bandgap 1.2 V

ADC0 channel 146

1.10

1.34

Vreg1p2 Feedback

ADC0 channel 147

V_DD/2.147

V_DD/1.863

V_DD/ 2.045

V_DD/ 1.774

V_DD/1.943

V_DD/1.685

LVD 1.2 V

ADC0 channel 180

Vreg3p3 Feedback

ADC0 channel 181

Vreg3p3 /

5.733—

Vreg3p3 / 5.460 Vreg3p3 / 5.187

LVD 3.3 V

ADC0 channel 182

Vreg3p3 / 4.996 Vreg3p3 / 4.758 Vreg3p3 / 4.520

LVD 5.0 V

V_DDREG/ 4.996

V_DDREG/ 7.384

V_DDREG/ 4.520

V_DDREG/ 6.680

ADC0 channel 183

— LDO mode

— SMPS mode

V_DDREG/ 4.758

V_DDREG/7.032

Table 21. Standby RAM Regulator Electrical Specifications

Spec

Characteristic

Symbol

Min

Typ

Max

Unit

Normal Mode

—

Standby Regulator Output

ADC1 channel 194

V_ADC194

1.2

—

Standby Source Bias

ADC1 channel 195

V_ADC195

150

360

Table 22. ADC Band Gap Reference / LVI Electrical Specifications

Spec

Characteristic

Symbol

Min

Typ

Max

Unit

4.75 LVD (from V_DDA

)

V_ADC196

—

4.75

—

ADC1 channel 196

ADC Bandgap

V_ADC45

—

1.220

—

ADC0 channel 45

ADC1 channel 45

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

Table 23. Temperature Sensor Electrical Specifications

Spec

Characteristic

Symbol

Min

Typ

Max

Unit

Slope

—

5.8

—

mV/ C

SADC128

–40 C to 100 C ±1.0 C

100 C to 150 C ±1.6 C

ADC0 channel 128

ADC1 channel 128

Accuracy

—

-20

—

+20

C

–40 C to 150 C

ADC0 channel 128

ADC1 channel 128

Slope is the measured voltage change per °C.

4.10 C90 Flash Memory Electrical Characteristics

Table 24. Flash Program and Erase Specifications (Pending Si characterization)

Initial

Max²

Lifetime

Spec

Characteristic

Symbol

Typ¹

Unit

Max³

Double Word (64 bits) Program Time⁴

Page (128 bits) Program Time⁴

t_dwprogram

t_pprogram

—

500

s

160

16 KB Block Pre-program and Erase Time

48 KB Block Pre-program and Erase Time

64 KB Block Pre-program and Erase Time

128 KB Block Pre-program and Erase Time

256 KB Block Pre-program and Erase Time

t_16kpperase

t_48kpperase

t_64kpperase

t_128kpperase

t_256kpperase

270

625

800

1500

3000

1000

1500

1800

2600

5200

5000

7500

15000

Typical program and erase times represent the median performance and assume nominal supply values and operation at

25 ^oC. These values are characterized, but not tested.

Initial Max program and erase times provide guidance for time-out limits used in the factory and apply for < 100 program/erase

cycles, nominal supply values and operation at 25 ^oC. These values are verified at production test.

Lifetime Max program and erase times apply across the voltage, temperature, and cycling range of product life. These values

are characterized, but not tested.

Program times are actual hardware programming times and do not include software overhead.

NOTE

The low, mid, and high address blocks of the flash arrays are erased (all bits set to 1) before

leaving the factory.

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

Table 25. Flash Memory AC Timing Specifications

Parameter

Value

Symbol

Unit

Min

Typ

Max

T_RES

T_DONE

T_PSRT

Time from clearing the MCR-ESUS or PSUS bit with EHV = 1

until DONE goes low

—

100

 s

Time from 0 to 1 transition on the MCR-EHV bit initiating a

program/erase until the MCR-DONE bit is cleared

—

Time between program suspend resume and the next program

suspend request.²

100

—

T_ESRT

Time between erase suspend resume and the next erase

suspend request.³

This parameter is guaranteed by characterization before qualification rather than 100% tested.

Repeated suspends at a high frequency may result in the operation timing out, and the flash module will respond by

completing the operation with a fail code (MCR[PEG] = 0), or the operation not able to finish (MCR[DONE] = 1 during Program

operation). The minimum time between suspends to ensure this does notoccur is T_PSRT

If Erase suspend rate is less than T_ESRT, an increase of slope voltage ramp occurs during erase pulse. This improves erase

time but reduces cycling figure due to overstress.

Table 26. Flash EEPROM Module Life

Spec

Characteristic

Symbol

Min

Typical¹

Unit

Number of Program/Erase cycles per block for 16 KB and 64

KB blocks over the operating temperature range (T_J)

P/E

100,000

—

cycles

Number of Program/Erase cycles per block for 128 KB and

256 KB blocks over the operating temperature range (T_J)

P/E

1,000

100,000

—

cycles

years

Minimum Data Retention at 85 °C ambient temperature²

Blocks with 0–1,000 P/E cycles

Retention

Blocks with 1,001–10,000 P/E cycles

Blocks with 10,001–100,000 P/E cycles

1 – 5

Typical endurance is evaluated at 25 °C. Product qualification is performed to the minimum specification. For additional

information on the NXP definition of Typical Endurance, please refer to Engineering Bulletin EB619, Typical Endurance for

Nonvolatile Memory.

Ambient temperature averaged over duration of application, not to exceed product operating temperature range.

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

Table 27. BIUCR1/BIUCR3 Settings

Maximum Frequency

(MHz)

APC =

RWSC

Spec

WWSC DPFEN¹IPFEN¹

PFLIM²

BFEN³

Core

f_sys

Platform

f_platf

180 MHz

90 MHz

0b010

0b01

0b11

0b0

0b1

0b0

0b1

0b00

0b01

0b1x

0b0

0b1

Default setting after reset:

0b111

0b00

0b0

For maximum flash performance, set to 0b1.

For maximum flash performance, set to 0b10.

For maximum flash performance, set to 0b1.

4.11 AC Specifications

4.11.1 Clocking Modes

There are two main modes of operating frequency settings:

•

Double 2:1 (Core:Platform) Mode—the core is running at the system frequency setting while the platform and eTPU

are running at half the core frequency (system frequency divided by 2).

•

eTPU Mode—the core and eTPU are running at the system frequency setting while the platform is running at half the

core frequency (system frequency divided by 2).

Table 28 shows the operating frequencies of various blocks depending on the device’s clocking mode configuration settings.

1, 2

Table 28. MPC5676R Block Operating Frequency

Double Mode Freq eTPU Mode Freq

Spec

Blocks

Symbol

(MHz)

Cores

f_sys

f_sys= 180

(t_cycsys= 1/f_sys

)

Platform

f_platf

_sys/ 2

f_sys/ 2

(t_cyc= 1/f_platf

)

eTPU

EBI

f_eTPU

f_sys/ 2

f_sys/ 4

f_sys

f_ebi

f_sys/ 4

The values in the table are specified at V_DD= 1.02 V to 1.32 V, V_DDE= 3.0 V to 3.6 V, V_DDEH= 4.5 V to 5.5 V, V_DD33and

V_DDSYN= 3.0 V to 3.6 V, T_A= T_Lto T_H.

Up to the maximum frequency rating of the device (refer to Table 1). The f_sysspeed is the nominal maximum frequency.

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

4.11.2 Pad AC Specifications

Table 29. Pad AC Specifications (V

= 5.0 V, V

= 3.3 V)

DDE

DDEH

Out Delay^2,4

H/H L (ns)

Rise/Fall^3,4

Load Drive

(pF)

Spec

Pad

SRC/DSC



(ns)

Medium⁵

152/165

205/220

28/34

70/74

96/96

12/15

28/31

5.3/5.9

22/22

200

52/59

200

12/12

32/32

200

Fast⁶

2.5

1.2

Fast with Slew Rate

40/40

50/50

13/13

19/19

8/8

16/16

21/21

5/5

200

8/8

200

2.4/2.4

5/5

12/12

5/5

200

1.1/1/1

2.6

8/8

200

Pull Up/Down (3.6 V max)

Pull Up/Down (5.25 V max)

—

7500

6000

5000/5000

These are worst case values that are estimated from simulation and not tested. The values in the table are simulated at

V_DD= 1.02 V to 1.32 V, V_DDE= 3.0 V to 3.6 V, V_DDEH= 4.75 V to 5.25 V, V_DD33and V_DDSYN= 3.0 V to 3.6 V, T_A= T_Lto T_H.

This parameter is supplied for reference and is not guaranteed by design and not tested.

This parameter is guaranteed by characterization before qualification rather than 100% tested.

Delay and rise/fall are measured to 20% or 80% of the respective signal.

Out delay is shown in Figure 7. Add a maximum of one system clock to the output delay for delay with respect to system clock.

Table 30. Derated Pad AC Specifications (V

= 3.3 V)

DDEH

Out Delay^2,3

H/H L (ns)

Rise/Fall^4,3

Load Drive

(pF)

Spec

Pad

SRC/DSC



(ns)

Medium⁵

200/210

270/285

37/45

86/86

120/120

15.5/19

38/43

200

69/82

200

18/17

7.6/8.5

30/34

46/49

200

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

These are worst case values that are estimated from simulation and not tested. The values in the table are simulated at

_DD= 1.08 V to 1.32 V, V_DDE= 3.0 V to 3.6 V, V_DDEH= 3.0 V to 3.6 V, V_DD33and V_DDSYN= 3.0 V to 3.6 V, T_A= T_Lto T_H.

This parameter is supplied for reference and is not guaranteed by design and not tested.

Delay and rise/fall are measured to 20% or 80% of the respective signal.

This parameter is guaranteed by characterization before qualification rather than 100% tested.

Out delay is shown in Figure 7. Add a maximum of one system clock to the output delay for delay with respect to system clock.

V_DDEn/ 2

V_DDEHn/ 2

Pad

Data Input

Rising

Edge

Falling

Edge

Output

Delay

Output

Delay

V_OH

Pad

Output

V_OL

Figure 7. Pad Output Delay

4.12 AC Timing

4.12.1 Generic Timing Diagrams

The generic timing diagrams in Figure 8 and Figure 9 apply to all I/O pins with pad types F and MH. See Table 39 for the pad

type for each pin.

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

D_CLKOUT

V_DDE/ 2

I/O Outputs

V_DDEn/ 2

V_DDEHn/ 2

A – Maximum Output Delay Time

Figure 8. Generic Output Delay/Hold Timing

B – Minimum Output Hold Time

D_CLKOUT

V_DDE/ 2

I/O Inputs

V_DDEn/ 2

V_DDEHn/ 2

A – Minimum Input Setup Time

B – Minimum Input Hold Time

Figure 9. Generic Input Setup/Hold Timing

4.12.2 Reset and Configuration Pin Timing

Table 31. Reset and Configuration Pin Timing

Spec

Characteristic Symbol

Min

Max

Unit

RESET Pulse Width

t_RPW

t_GPW

t_RCSU

t_RCH

—

t_cyc

RESET Glitch Detect Pulse Width

PLLCFG, BOOTCFG, WKPCFG Setup Time to RSTOUT Valid

PLLCFG, BOOTCFG, WKPCFG Hold Time to RSTOUT Valid

Reset timing specified at: V_DDEH= 3.0 V to 5.25 V, V_DD= 1.08 V to 1.32 V, T_A= T_Lto T_H.

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

See Notes on t_cycon Table 28.

RESET

RSTOUT

PLLCFG

BOOTCFG

WKPCFG

Figure 10. Reset and Configuration Pin Timing

4.12.3 IEEE 1149.1 Interface Timing

Table 32. JTAG Pin AC Electrical Characteristics

Spec

Characteristic

Symbol

Min

Max

Unit

TCK Cycle Time

t_JCYC

t_JDC

100

—

TCK Clock Pulse Width (Measured at V_DDE/ 2)

TCK Rise and Fall Times (40%–70%)

TMS, TDI Data Setup Time

t_TCKRISE

t_{TMSS, TDIS}

_TMSH,t_TDIH

t_TDOV

t_TDOI

—

TMS, TDI Data Hold Time

—

TCK Low to TDO Data Valid

TCK Low to TDO Data Invalid

TCK Low to TDO High Impedance

JCOMP Assertion Time

t_TDOHZ

t_JCMPPW

t_JCMPS

t_BSDV

—

100

—

JCOMP Setup Time to TCK Low

TCK Falling Edge to Output Valid

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

Table 32. JTAG Pin AC Electrical Characteristics (continued)

Spec

Characteristic

Symbol

Min

Max

Unit

TCK Falling Edge to Output Valid out of High Impedance

TCK Falling Edge to Output High Impedance

t_BSDVZ

t_BSDHZ

t_BSDST

t_BSDHT

—

Boundary Scan Input Valid to TCK Rising Edge

TCK Rising Edge to Boundary Scan Input Invalid

JTAG timing specified at V_DD= 1.08 V to 1.32 V, V_DDE= 3.0 V to 3.6 V, V_DD33and V_DDSYN= 3.0 V to 3.6 V, T_A= T_Lto T_H, and

C_L= 30 pF with DSC = 0b10, SRC = 0b00. These specifications apply to JTAG boundary scan only. See Table 33 for

functional specifications.

TCK

Figure 11. JTAG Test Clock Input Timing

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

TCK

TMS, TDI

TDO

Figure 12. JTAG Test Access Port Timing

TCK

JCOMP

Figure 13. JTAG JCOMP Timing

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

TCK

Output

Signals

Output

Signals

Input

Signals

Figure 14. JTAG Boundary Scan Timing

4.12.4 Nexus Timing

Table 33. Nexus Debug Port Timing

Spec

Characteristic

Symbol

Min

Max

Unit

MCKO Cycle Time

t_MCYC

t_MDC

2²

t_CYC

MCKO Duty Cycle

0.2

—

MCKO Low to MDO Data Valid³

MCKO Low to MSEO Data Valid³

MCKO Low to EVTO Data Valid³

EVTI Pulse Width

t_MDOV

–0.1

4.0

t_MCYC

t_TCYC

t_MCYC

t_CYC

t_MSEOV

t_EVTOV

t_EVTIPW

t_EVTOPW

t_TCYC

EVTO Pulse Width

—

TCK Cycle Time

4⁴

—

TCK Duty Cycle

t_TDC

—

10 TDI, TMS Data Setup Time

_NTDIS,t_NTMSS

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

Spec

Table 33. Nexus Debug Port Timing (continued)

Characteristic

Symbol

T_{NTDIH, NTMSH}

t_NTDOV

—

Min

Max

Unit

11 TDI, TMS Data Hold Time

12 TCK Low to TDO Data Valid

13 RDY Valid to MCKO⁵

—

14 TDO hold time after TCLK low

t_NTDOH

All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal. Nexus timing specified

at V_DD= 1.08 V to 1.32 V, V_DDE= 3.0 V to 3.6 V, V_DD33and V_DDSYN= 3.0 V to 3.6 V, T_A= T_Lto T_H, and C_L= 30 pF with

DSC = 0b10.

The Nexus AUX port runs up to 82 MHz (pending characterization). Set NPC_PCR[MKCO_DIV] to correct division depending

on the system frequency, not to exceed maximum Nexus AUX port frequency.

MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.

Lower frequency is required to be fully compliant to standard.

The RDY pin timing is asynchronous to MCKO. The timing is guaranteed by design to function correctly.

MCKO

MDO

Output Data Valid

MSEO

EVTO

EVTI

Figure 15. Nexus Timings

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

TCK

TMS, TDI

TDO

Figure 16. Nexus TCK, TDI, TMS, TDO Timing

4.12.5 External Bus Interface (EBI) Timing

Table 34. Bus Operation Timing

66 MHz (Ext. Bus Freq)^{2 3}

Spec

Characteristic

D_CLKOUT Period

Symbol

Unit

Notes

Min

Max

t_C

15.2

—

ns Signals are measured at 50% V_DDE

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

Table 34. Bus Operation Timing (continued)

66 MHz (Ext. Bus Freq)^{2 3}

Spec

Characteristic

Symbol

Unit

Notes

Min

Max

D_CLKOUT Duty Cycle

D_CLKOUT Rise Time

D_CLKOUT Fall Time

t_CDC

t_CRT

t_CFT

t_COH

45%

—

55%

t_C

—

D_CLKOUT Posedge to Output

Signal Invalid or High Z (Hold Time)

1.0/1.5

—

ns Hold time selectable via

SIU_ECCR[EBTS] bit:

EBTS = 0: 1.0 ns

D_ADD[9:30]

D_BDIP

EBTS = 1: 1.5 ns

D_CS[0:3]

D_DAT[0:15]

D_OE

D_RD_WR

D_TA

D_TS

D_WE[0:3]/D_BE[0:3]

D_CLKOUT Posedge to Output

Signal Valid (Output Delay)

t_COV

—

8.5/9.0

ns Output valid time selectable via

SIU_ECCR[EBTS] bit:

EBTS = 0: 8.5 ns

D_ADD[9:30]

D_BDIP

EBTS = 1: 9.0 ns

D_CS[0:3]

D_DAT[0:15]

D_OE

D_RD_WR

D_TA

D_TS

D_WE[0:3]/D_BE[0:3]

Input Signal Valid to D_CLKOUT

Posedge (Setup Time)

t_CIS

5.0/4.5

—

ns Input setup time selectable via

SIU_ECCR[EBTS] bit:

EBTS = 0; 5.0ns

D_ADD[9:30]

D_DAT[0:15]

D_RD_WR

D_TA

EBTS = 1; 4.5ns

D_TS

D_CLKOUT Posedge to Input

Signal Invalid (Hold Time)

t_CIH

1.0

—

D_ADD[9:30]

D_DAT[0:15]

D_RD_WR

D_TA

D_TS

D_ALE Pulse Width

t_APW

t_AAI

6.5

—

ns The timing is for Asynchronous

external memory system.

10 D_ALE Negated to Address Invalid

2.0/1.0 ⁵

ns The timing is for Asynchronous

external memory system.

ALE is measured at 50% of VDDE.

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

EBI timing specified at V_DD= 1.08 V to 1.32 V, V_DDE= 3.0 V to 3.6 V, V_DD33and V_DDSYN= 3.0 V to 3.6 V, T_A= T_Lto T_H, and

C_L= 30 pF with DSC = 0b10.

Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including frequency modulation (FM).

Depending on the internal bus speed, set the SIU_ECCR[EBDF] bits correctly not to exceed maximum external bus frequency.

The maximum external bus frequency is 66 MHz.

Refer to Fast pad timing in Table 29 and Table 30.

ALE hold time spec is temperature dependant. 1.0ns spec applies for temperature range -40 to 0 C. 2.0ns spec applies to

temperatures > 0 C. This spec has no dependency on SIU_ECCR[EBTS] bit.

V_{OH_F}

V_DDE/ 2

V_{OL_F}

D_CLKOUT

Figure 17. D_CLKOUT Timing

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

V_DDE/ 2

D_CLKOUT

Output

Bus

V_DDE/ 2

Output

Signal

V_DDE/ 2

Output

Signal

V_DDE/ 2

Figure 18. Synchronous Output Timing

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

D_CLKOUT

V_DDE/ 2

Input

Bus

V_DDE/ 2

Input

Signal

V_DDE/ 2

Figure 19. Synchronous Input Timing

ipg_clk

D_CLKOUT

D_ALE

D_TS

D_ADD/D_DAT

DATA

ADDR

Figure 20. ALE Signal Timing

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

4.12.6 External Interrupt Timing (IRQ Pin)

Table 35. External Interrupt Timing

Spec

Characteristic

IRQ Pulse Width Low

Symbol

Min

Max

Unit

t_IPWL

t_IPWH

t_ICYC

—

t_cyc

IRQ Pulse Width High

IRQ Edge to Edge Time³

t_cyc

IRQ timing specified at V_DD= 1.08 V to 1.32 V, V_DDEH= 3.0 V to 5.5 V, V_DD33and V_DDSYN= 3.0 V to 3.6 V, T_A= T_L

to T_H.

See Notes on t_cycTable 28.

Applies when IRQ pins are configured for rising edge or falling edge events, but not both.

IRQ

Figure 21. External Interrupt Timing

4.12.7 eTPU Timing

Table 36. eTPU Timing

Spec

Characteristic

Symbol

Min

Max

Unit

eTPU Input Channel Pulse Width

eTPU Output Channel Pulse Width

t_ICPW

1³

—

t_cyc

t_OCPW

t_cyc

eTPU timing specified at V_DD= 1.08 V to 1.32 V, V_DDEH= 3.0 V to 5.5 V, V_DD33and V_DDSYN= 3.0 V to 3.6 V, T_A= T_Lto T_H,

and C_L= 200 pF with SRC = 0b00.

See Notes on t_cycTable 28.

This specification does not include the rise and fall times. When calculating the minimum eTPU pulse width, include the rise

and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR).

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

eTPU Input

and TCRCLK

eTPU

Output

Figure 22. eTPU Timing

4.12.8 eMIOS Timing

Table 37. eMIOS Timing

Spec

Characteristic

Symbol

Min

Max

Unit

eMIOS Input Pulse Width

eMIOS Output Pulse Width

t_MIPW

1³

—

t_cyc

t_MOPW

t_cyc

eMIOS timing specified at V_DD= 1.08 V to 1.32 V, V_DDEH= 3.0 V to 5.5 V, V_DD33and V_DDSYN= 3.0 V to 3.6 V, T_A= T_Lto T_H,

and C_L= 50 pF with SRC = 0b00.

See Notes on t_cycon Table 28.

This specification does not include the rise and fall times. When calculating the minimum eMIOS pulse width, include the rise

and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR).

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

eMIOS Input

eMIOS

Output

Figure 23. eMIOS Timing

4.12.9 DSPI Timing

1,2

Table 38. DSPI Timing

Peripheral Bus Freq:

92 MHz

Spec

Characteristic

Symbol

Unit

Min

Max

DSPI Cycle Time^{3, 4}

Master (MTFE = 0)

Slave (MTFE = 0)

Master (MTFE = 1)

Slave (MTFE = 1)

t_SCK

23.8

1800

PCS to SCK Delay⁵

After SCK Delay⁶

SCK Duty Cycle

t_CSC

t_ASC

t_SDC

t_A

—

0.4 * t_SCK

—

0.6 * t_SCK

Slave Access Time

(SS active to SOUT valid)

Slave SOUT Disable Time

t_DIS

—

(SS inactive to SOUT High-Z or invalid)

PCSx to PCSS time

PCSS to PCSx time

t_PCSC

t_PASC

—

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

1,2

Table 38. DSPI Timing (continued)

Peripheral Bus Freq:

92 MHz

Spec

Characteristic

Symbol

Unit

Min

Max

Data Setup Time for Inputs

Master (MTFE = 0)

t_SUI

—

Slave

Master (MTFE = 1, CPHA = 0)⁷

Master (MTFE = 1, CPHA = 1)

Data Hold Time for Inputs

Master (MTFE = 0)

t_HI

–3

—

Slave

Master (MTFE = 1, CPHA = 0)⁷

Master (MTFE = 1, CPHA = 1)

Data Valid (after SCK edge)

Master (MTFE = 0)

t_SUO

—

Slave

Master (MTFE = 1, CPHA = 0)

Master (MTFE = 1, CPHA = 1)

Master (LVDS)

Data Hold Time for Outputs

Master (MTFE = 0)

t_HO

–6

2.5

–7

–5

—

Slave

Master (MTFE = 1, CPHA = 0)

Master (MTFE = 1, CPHA = 1)

Master (LVDS)

DSPI timing specified at V_DD= 1.08 V to 1.32 V, V_DDEH= 3.0 V to 5.5 V, V_DD33and V_DDSYN= 3.0 V to 3.6 V, and T_A= T_Lto T_H

Speed is the nominal maximum frequency of platform clock (f_platf). Max speed is the maximum speed allowed including

frequency modulation (FM).

The minimum DSPI Cycle Time restricts the baud rate selection for given system clock rate. These numbers are calculated

based on two devices communicating over a DSPI link.

The actual minimum SCK cycle time is limited by pad performance.

The maximum value is programmable in DSPI_CTARn[PSSCK] and DSPI_CTARn[CSSCK].

The maximum value is programmable in DSPI_CTARn[PASC] and DSPI_CTARn[ASC].

This number is calculated assuming the SMPL_PT bit-field in DSPI_MCR is set to 0b10.

The DSPI in this device can be configured to serialize data to an external device that implements the Microsecond Bus protocol.

DSPI pins support 5 V logic levels or Low Voltage Differential Signalling (LVDS) for data and clock signals to improve high

speed operation.

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

PCSx

SCK Output

(CPOL = 0)

SCK Output

(CPOL = 1)

Last Data

SIN

First Data

Data

First Data

Last Data

SOUT

Figure 24. DSPI Classic SPI Timing — Master, CPHA = 0

PCSx

SCK Output

(CPOL=0)

SCK Output

(CPOL=1)

Data

First Data

Last Data

SIN

SOUT

Last Data

First Data

Figure 25. DSPI Classic SPI Timing — Master, CPHA = 1

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

SCK Input

(CPOL = 0)

SCK Input

(CPOL = 1)

Data

First Data

Last Data

SOUT

SIN

Data

Last Data

First Data

Figure 26. DSPI Classic SPI Timing — Slave, CPHA = 0

SCK Input

(CPOL = 0)

SCK Input

(CPOL = 1)

Last Data

Data

SOUT

SIN

First Data

Last Data

First Data

Figure 27. DSPI Classic SPI Timing — Slave, CPHA = 1

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

PCSx

SCK Output

(CPOL = 0)

SCK Output

(CPOL = 1)

SIN

First Data

Last Data

Data

SOUT

First Data

Data

Figure 28. DSPI Modified Transfer Format Timing — Master, CPHA = 0

PCSx

SCK Output

(CPOL = 0)

SCK Output

(CPOL = 1)

SIN

Last Data

First Data

Data

First Data

Last Data

SOUT

Figure 29. DSPI Modified Transfer Format Timing — Master, CPHA = 1

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

SCK Input

(CPOL = 0)

SCK Input

(CPOL = 1)

First Data

Data

Last Data

SOUT

SIN

Last Data

First Data

Figure 30. DSPI Modified Transfer Format Timing — Slave, CPHA = 0

SCK Input

(CPOL = 0)

SCK Input

(CPOL = 1)

Last Data

First Data

Data

SOUT

SIN

First Data

Data

Last Data

Figure 31. DSPI Modified Transfer Format Timing — Slave, CPHA = 1

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Electrical Characteristics

PCSS

PCSx

Figure 32. DSPI PCS Strobe (PCSS) Timing

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Package Information

5.1

416-Pin Package

The package drawings of the 416-pin TEPBGA package are shown in Figure 33 and Figure 34.

Figure 33. 416 TEPBGA Package (1 of 2)

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Package Information

Figure 34. 416 TEPBGA Package (2 of 2)

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Package Information

5.2

516-Pin Package

The package drawings of the 516-pin TEPBGA package are shown in Figure 35 and Figure 36.

Figure 35. 516 TEPBGA Package (1 of 2)

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Package Information

Figure 36. 516 TEPBGA Package (2 of 2)

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Product Documentation

This data sheet is labeled as a particular type: Product Preview, Advance Information, or Technical Data. Definitions of these

types are available at: http://www.nxp.com.

The following documents are required for a complete description of the device and are necessary to design properly with the

parts:

•

MPC5676R RM Microprocessor Reference Manual (document number MPC5676RRM)

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Appendix A Signal Properties and Muxing

The following table shows the signals properties for each pin on the MPC5676R. For each port pin that has an associated SIU_PCRn register to control its pin

properties, the supported functions column lists the functions associated with the programming of the SIU_PCRn[PA] bit in the order: Primary function (P),

Function 2 (F2), Function 3 (F3), and GPIO (G). See Figure 37.

Table 2. Signal Properties and Muxing Summar

GPIO/

PCR¹

Pad

I/O Type

Signal Name²

Function³

TCRCLKA

Function Summary

Primary Functions

are listed First

113 TCRCLKA_IRQ7_GPIO113

eTPU A TCR clock

5V M

IRQ7

—

External interrupt request

Secondary Functions

are alternate functions

—

I/O

GPIO Functions are

GPIO113

GPIO

listed Last

Function not implemented on this device

Figure 37. Supported Functions Example

Table 39. Signal Properties and Muxing Summary

Package

Location

State

Stateduring

RESET⁷

Signal Name²

Function⁴

Function Summary

eTPU_A

after

RESET⁸

113 TCRCLKA_IRQ7_

GPIO113

TCRCLKA

IRQ7

eTPU A TCR clock

V_DDEH1

—/Up

External interrupt request

—

I/O

GPIO113

ETPUA0

ETPUA12

—

GPIO

114 ETPUA0_ETPUA12_

GPIO114

eTPU A channel

V_DDEH1

—/WKPCFG

eTPU A channel (output only)

—

I/O

GPIO114

GPIO

Table 39. Signal Properties and Muxing Summary (continued)

Package

Location

State

after

Stateduring

RESET⁷

Signal Name²

Function⁴

Function Summary

RESET⁸

115 ETPUA1_ETPUA13_

GPIO115

ETPUA1

eTPU A channel

I/O

V_DDEH1

—/WKPCFG

ETPUA13

—

eTPU A channel (output only)

—

GPIO115

ETPUA2

ETPUA14

—

GPIO

I/O

116 ETPUA2_ETPUA14_

GPIO116

eTPU A channel

eTPU A channel (output only)

—

GPIO116

ETPUA3

ETPUA15

—

GPIO

I/O

117 ETPUA3_ETPUA15_

GPIO117

eTPU A channel

eTPU A channel (output only)

—

GPIO117

ETPUA4

ETPUA16

—

GPIO

I/O

118 ETPUA4_ETPUA16_

GPIO118

eTPU A channel

eTPU A channel (output only)

—

GPIO118

ETPUA5

ETPUA17

—

GPIO

I/O

119 ETPUA5_ETPUA17_

GPIO119

eTPU A channel

eTPU A channel (output only)

—

GPIO119

ETPUA6

ETPUA18

—

GPIO

I/O

120 ETPUA6_ETPUA18_

GPIO120

eTPU A channel

eTPU A channel (output only)

—

GPIO120

GPIO

I/O

Table 39. Signal Properties and Muxing Summary (continued)

Package

Location

State

after

Stateduring

RESET⁷

Signal Name²

Function⁴

Function Summary

RESET⁸

121 ETPUA7_ETPUA19_

GPIO121

ETPUA7

eTPU A channel

I/O

V_DDEH1

—/WKPCFG

ETPUA19

—

eTPU A channel (output only)

—

GPIO121

ETPUA8

ETPUA20

—

GPIO

I/O

122 ETPUA8_ETPUA20_

GPIO122

eTPU A channel

eTPU A channel (output only)

—

GPIO122

ETPUA9

ETPUA21

—

GPIO

I/O

123 ETPUA9_ETPUA21_

GPIO123

eTPU A channel

eTPU A channel (output only)

—

GPIO123

ETPUA10

ETPUA22

—

GPIO

I/O

124 ETPUA10_ETPUA22_

GPIO124

eTPU A channel

eTPU A channel (output only)

—

GPIO124

ETPUA11

ETPUA23

—

GPIO

I/O

125 ETPUA11_ETPUA23_

GPIO125

eTPU A channel

eTPU A channel (output only)

—

GPIO125

ETPUA12

PCSB1

—

GPIO

I/O

126 ETPUA12_PCSB1_

GPIO126

eTPU A channel

DSPI B peripheral chip select

—

GPIO126

GPIO

I/O

Table 39. Signal Properties and Muxing Summary (continued)

Package

Location

State

after

Stateduring

RESET⁷

Signal Name²

Function⁴

Function Summary

RESET⁸

127 ETPUA13_PCSB3_

GPIO127

ETPUA13

eTPU A channel

I/O

V_DDEH1

—/WKPCFG

PCSB3

—

DSPI B peripheral chip select

—

GPIO127

ETPUA14

PCSB4

—

GPIO

I/O

128 ETPUA14_PCSB4_

GPIO128

eTPU A channel

DSPI B peripheral chip select

—

GPIO128

ETPUA15

PCSB5

—

GPIO

I/O

129 ETPUA15_PCSB5_

GPIO129

eTPU A channel

DSPI B peripheral chip select

—

GPIO129

ETPUA16

PCSD1

—

GPIO

I/O

130 ETPUA16_PCSD1_

GPIO130

eTPU A channel

DSPI D peripheral chip select

—

GPIO130

ETPUA17

PCSD2

—

GPIO

I/O

131 ETPUA17_PCSD2_

GPIO131

eTPU A channel

DSPI D peripheral chip select

—

GPIO131

ETPUA18

PCSD3

—

GPIO

I/O

132 ETPUA18_PCSD3_

GPIO132

eTPU A channel

DSPI D peripheral chip select

—

GPIO132

GPIO

I/O

Table 39. Signal Properties and Muxing Summary (continued)

Package

Location

State

after

Stateduring

RESET⁷

Signal Name²

Function⁴

Function Summary

RESET⁸

133 ETPUA19_PCSD4_

GPIO133

ETPUA19

eTPU A channel

I/O

V_DDEH1

—/WKPCFG

PCSD4

—

DSPI D peripheral chip select

—

I/O

GPIO133

ETPUA20

IRQ8

GPIO

134 ETPUA20_IRQ8_

GPIO134

eTPU A channel

External interrupt request

—

I/O

GPIO134

ETPUA21

IRQ9

GPIO

135 ETPUA21_IRQ9_

GPIO135

eTPU A channel

External interrupt request

—

I/O

GPIO135

ETPUA22

IRQ10

—

GPIO

136 ETPUA22_IRQ10_

GPIO136

eTPU A channel

External interrupt request

—

I/O

GPIO136

ETPUA23

IRQ11

—

GPIO

137 ETPUA23_IRQ11_

GPIO137

eTPU A channel

External interrupt request

—

I/O

GPIO137

ETPUA24

IRQ12

—

GPIO

138 ETPUA24_IRQ12_

GPIO138

eTPU A channel

External interrupt request

—

I/O

GPIO138

GPIO

Table 39. Signal Properties and Muxing Summary (continued)

Package

Location

State

after

Stateduring

RESET⁷

Signal Name²

Function⁴

Function Summary

RESET⁸

139 ETPUA25_IRQ13_

GPIO139

ETPUA25

eTPU A channel

I/O

V_DDEH1

—/WKPCFG

IRQ13

—

External interrupt request

—

I/O

GPIO139

ETPUA26

IRQ14

—

GPIO

140 ETPUA26_IRQ14_

GPIO140

eTPU A channel

External interrupt request

—

I/O

GPIO140

ETPUA27

IRQ15

—

GPIO

141 ETPUA27_IRQ15_

GPIO141

eTPU A channel

External interrupt request

—

I/O

GPIO141

ETPUA28

PCSC1

—

GPIO

142 ETPUA28_PCSC1_

GPIO142

eTPU A channel

DSPI C peripheral chip select

—

I/O

GPIO142

ETPUA29

PCSC2

—

GPIO

143 ETPUA29_PCSC2_

GPIO143

eTPU A channel

DSPI C peripheral chip select

—

I/O

GPIO143

ETPUA30

PCSC3

—

GPIO

144 ETPUA30_PCSC3_

GPIO144

eTPU A channel

DSPI C peripheral chip select

—

I/O

GPIO144

GPIO

Table 39. Signal Properties and Muxing Summary (continued)

Package

Location

State

after

Stateduring

RESET⁷

Signal Name²

Function⁴

Function Summary

RESET⁸

145 ETPUA31_PCSC4_

GPIO145

ETPUA31

eTPU A channel

I/O

V_DDEH1

—/WKPCFG

PCSC4

—

DSPI C peripheral chip select

—

GPIO145

GPIO

I/O

eTPU_B

146 TCRCLKB_IRQ6_

GPIO146

TCRCLKB

IRQ6

eTPU B TCR clock

V_DDEH6

—/Up

T23

T24

T25

T26

R23

V25

V26

U22

U23

T22

External interrupt request

—

I/O

GPIO146

ETPUB0

ETPUB16

—

GPIO

147 ETPUB0_ETPUB16_

GPIO147

eTPU B channel

—/WKPCFG

eTPU B channel (output only)

—

I/O

GPIO147

ETPUB1

ETPUB17

—

GPIO

148 ETPUB1_ETPUB17_

GPIO148

eTPU B channel

eTPU B channel (output only)

—

I/O

GPIO148

ETPUB2

ETPUB18

—

GPIO

149 ETPUB2_ETPUB18_

GPIO149

eTPU B channel

eTPU B channel (output only)

—

I/O

GPIO149

ETPUB3

ETPUB19

—

GPIO

150 ETPUB3_ETPUB19_

GPIO150

eTPU B channel

eTPU B channel (output only)

—

I/O

GPIO150

GPIO

Table 39. Signal Properties and Muxing Summary (continued)

Package

Location

State

after

Stateduring

RESET⁷

Signal Name²

Function⁴

Function Summary

RESET⁸

151 ETPUB4_ETPUB20_

GPIO151

ETPUB4

eTPU B channel

I/O

V_DDEH6

—/WKPCFG

R24

R25

R26

P23

P24

P25

U24

U25

U26

T23

T24

R22

ETPUB20

—

eTPU B channel (output only)

—

GPIO151

ETPUB5

ETPUB21

—

GPIO

I/O

152 ETPUB5_ETPUB21_

GPIO152

eTPU B channel

eTPU B channel (output only)

—

GPIO152

ETPUB6

ETPUB22

—

GPIO

I/O

153 ETPUB6_ETPUB22_

GPIO153

eTPU B channel

eTPU B channel (output only)

—

GPIO153

ETPUB7

ETPUB23

—

GPIO

I/O

154 ETPUB7_ETPUB23_

GPIO154

eTPU B channel

eTPU B channel (output only)

—

GPIO154

ETPUB8

ETPUB24

—

GPIO

I/O

155 ETPUB8_ETPUB24_

GPIO155

eTPU B channel

eTPU B channel (output only)

—

GPIO155

ETPUB9

ETPUB25

—

GPIO

I/O

156 ETPUB9_ETPUB25_

GPIO156

eTPU B channel

eTPU B channel (output only)

—

GPIO156

GPIO

I/O

Table 39. Signal Properties and Muxing Summary (continued)

Package

Location

State

after

Stateduring

RESET⁷

Signal Name²

Function⁴

Function Summary

RESET⁸

157 ETPUB10_ETPUB26_

GPIO157

ETPUB10

eTPU B channel

I/O

V_DDEH6

—/WKPCFG

P26

N24

N25

N26

M25

M24

T25

T26

R23

P22

R24

R25

ETPUB26

—

eTPU B channel (output only)

—

GPIO157

ETPUB11

ETPUB27

—

GPIO

I/O

158 ETPUB11_ETPUB27_

GPIO158

eTPU B channel

eTPU B channel (output only)

—

GPIO158

ETPUB12

ETPUB28

—

GPIO

I/O

159 ETPUB12_ETPUB28_

GPIO159

eTPU B channel

eTPU B channel (output only)

—

GPIO159

ETPUB13

ETPUB29

—

GPIO

I/O

160 ETPUB13_ETPUB29_

GPIO160

eTPU B channel

eTPU B channel (output only)

—

GPIO160

ETPUB14

ETPUB30

—

GPIO

I/O

161 ETPUB14_ETPUB30_

GPIO161

eTPU B channel

eTPU B channel (output only)

—

GPIO161

ETPUB15

ETPUB31

—

GPIO

I/O

162 ETPUB15_ETPUB31_

GPIO162

eTPU B channel

eTPU B channel (output only)

—

GPIO162

GPIO

I/O

Table 39. Signal Properties and Muxing Summary (continued)

Package

Location

State

after

Stateduring

RESET⁷

Signal Name²

Function⁴

Function Summary

RESET⁸

163 ETPUB16_PCSA1_

GPIO163

ETPUB16

eTPU B channel

I/O

V_DDEH6

—/WKPCFG

U26

U25

U24

U23

V26

V25

V24

T21

PCSA1

—

DSPI A peripheral chip select

—

GPIO163

ETPUB17

PCSA2

—

GPIO

I/O

164 ETPUB17_PCSA2_

GPIO164

eTPU B channel

DSPI A peripheral chip select

—

GPIO164

ETPUB18

PCSA3

—

GPIO

I/O

165 ETPUB18_PCSA3_

GPIO165

eTPU B channel

W26

W25

W24

V22

DSPI A peripheral chip select

—

GPIO165

ETPUB19

PCSA4

—

GPIO

I/O

166 ETPUB19_PCSA4_

GPIO166

eTPU B channel

DSPI A peripheral chip select

—

GPIO166

ETPUB20

—

GPIO

I/O

—

167 ETPUB20_

GPIO167

eTPU B channel

—

GPIO167

ETPUB21

—

GPIO

I/O

—

168 ETPUB21_

GPIO168

eTPU B channel

—

GPIO168

GPIO

I/O

Table 39. Signal Properties and Muxing Summary (continued)

Package

Location

State

after

Stateduring

RESET⁷

Signal Name²

Function⁴

Function Summary

RESET⁸

169 ETPUB22_

ETPUB22

eTPU B channel

I/O

—

V_DDEH6

—/WKPCFG

V24

W26

W25

V23

U21

Y25

GPIO169

—

GPIO169

ETPUB23

—

GPIO

I/O

—

170 ETPUB23_

GPIO170

eTPU B channel

—

GPIO170

ETPUB24

—

GPIO

I/O

—

171 ETPUB24_

GPIO171

eTPU B channel

—

GPIO171

ETPUB25

—

GPIO

I/O

—

172 ETPUB25_

GPIO172

eTPU B channel

W24 W21

—

GPIO172

ETPUB26

—

GPIO

I/O

—

173 ETPUB26_

GPIO173

eTPU B channel

V23

Y25

Y23

Y24

—

GPIO173

ETPUB27

—

GPIO

I/O

—

174 ETPUB27_

GPIO174

eTPU B channel

—

GPIO174

GPIO

I/O

Table 39. Signal Properties and Muxing Summary (continued)

Package

Location

State

after

Stateduring

RESET⁷

Signal Name²

Function⁴

Function Summary

RESET⁸

175 ETPUB28_

ETPUB28

eTPU B channel

I/O

—

V_DDEH6

—/WKPCFG

Y24 AA24

GPIO175

—

GPIO175

ETPUB29

—

GPIO

I/O

—

176 ETPUB29_

GPIO176

eTPU B channel

—/WKPCFG

Y23

W22

—

GPIO176

ETPUB30

—

GPIO

I/O

—

177 ETPUB30_

GPIO177

eTPU B channel

—/WKPCFG AA24 AB24

—

GPIO177

ETPUB31

—

GPIO

I/O

—

178 ETPUB31_

GPIO178

eTPU B channel

—/WKPCFG AB24 Y22

—

GPIO178

GPIO

I/O

eTPU_C

440 TCRCLKC_

GPIO440

TCRCLKC

—

eTPU C TCR clock

V_DDEH7

—/Up

B26

C25

F22

C25

—

GPIO440

ETPUC0

—

GPIO

I/O

—

441 ETPUC0_

GPIO441

eTPU C channel

V_DDEH7

—/WKPCFG

—

GPIO441

GPIO

I/O

Table 39. Signal Properties and Muxing Summary (continued)

Package

Location

State

after

Stateduring

RESET⁷

Signal Name²

Function⁴

Function Summary

RESET⁸

442 ETPUC1_

ETPUC1

eTPU C channel

I/O

—

V_DDEH7

—/WKPCFG

C26

D25

D26

E24

E25

E26

C26

D25

D26

E24

E25

E26

GPIO442

—

GPIO442

ETPUC2

—

GPIO

I/O

—

443 ETPUC2_

GPIO443

eTPU C channel

—

GPIO443

ETPUC3

—

GPIO

I/O

—

444 ETPUC3_

GPIO444

eTPU C channel

—

GPIO444

ETPUC4

GPIO

I/O

445 ETPUC4_

eTPU C channel

PCSE1_GPIO445

DSPI E peripheral chip select

—

I/O

GPIO445

ETPUC5

GPIO

446 ETPUC5_

PCSE2_GPIO446

eTPU C channel

DSPI E peripheral chip select

—

I/O

GPIO446

ETPUC6

GPIO

447 ETPUC6_

PCSE3_GPIO447

eTPU C channel

DSPI E peripheral chip select

—

GPIO447

GPIO

I/O

Table 39. Signal Properties and Muxing Summary (continued)

Package

Location

State

after

Stateduring

RESET⁷

Signal Name²

Function⁴

Function Summary

RESET⁸

448 ETPUC7_

PCSE4_GPIO448

ETPUC7

eTPU C channel

I/O

V_DDEH7

—/WKPCFG

F23

F24

F25

F26

G23

G24

F23

F24

F25

F26

G22

G23

DSPI E peripheral chip select

—

I/O

GPIO448

ETPUC8

GPIO

449 ETPUC8_

PCSE5_GPIO449

eTPU C channel

DSPI E peripheral chip select

—

I/O

GPIO449

ETPUC9

IRQ0

GPIO

450 ETPUC9_IRQ0_

GPIO450

eTPU C channel

External interrupt request

—

I/O

GPIO450

ETPUC10

IRQ1

GPIO

451 ETPUC10__IRQ1_

GPIO451

eTPU C channel

External interrupt request

—

I/O

GPIO451

ETPUC11

IRQ2

GPIO

452 ETPUC11_IRQ2_

GPIO452

eTPU C channel

External interrupt request

—

I/O

GPIO452

ETPUC12

IRQ3

GPIO

453 ETPUC12_IRQ3_

GPIO453

eTPU C channel

External interrupt request

—

I/O

GPIO453

GPIO

Table 39. Signal Properties and Muxing Summary (continued)

Package

Location

State

after

Stateduring

RESET⁷

Signal Name²

Function⁴

Function Summary

RESET⁸

454 ETPUC13_3_IRQ4_

GPIO454

ETPUC13

eTPU C channel

I/O

V_DDEH7

—/WKPCFG

G25

G26

H23

H24

H25

H26

G24

G25

G26

H22

H23

H24

IRQ4

External interrupt request

—

I/O

GPIO454

ETPUC14

IRQ5

GPIO

455 ETPUC14_4_IRQ5_

GPIO455

eTPU C channel

External interrupt request

—

I/O

—

I/O

GPIO455

ETPUC15

—

GPIO

456 ETPUC15__

GPIO456

eTPU C channel

—

GPIO456

ETPUC16

FR_A_TX

—

GPIO

457 ETPUC16_FR_A_TX_

GPIO457

eTPU C channel

FlexRay A transfer

—

I/O

GPIO457

ETPUC17

FR_A_RX

—

GPIO

458 ETPUC17_FR_A_RX_

GPIO458

eTPU C channel

FlexRay A receive

—

I/O

GPIO458

ETPUC18

FR_A_TX_EN

—

GPIO

459 ETPUC18_FR_A_TX_EN_

GPIO459

eTPU C channel

FlexRay A transfer enable

—

I/O

GPIO459

GPIO

Table 39. Signal Properties and Muxing Summary (continued)

Package

Location

State

after

Stateduring

RESET⁷

Signal Name²

Function⁴

Function Summary

RESET⁸

460 ETPUC19_TXDA_

GPIO460

ETPUC19

eTPU C channel

I/O

V_DDEH7

—/WKPCFG

J23

J24

J25

J26

K23

H21

H25

H26

J22

J23

TXDA

eSCI A transmit

—

I/O

GPIO460

ETPUC20

RXDA

GPIO

461 ETPUC20_RXDA _

GPIO461

eTPU C channel

eSCI A receive

—

I/O

GPIO461

ETPUC21

TXDB

GPIO

462 ETPUC21_TXDB_

GPIO462

eTPU C channel

eSCI B transmit

—

I/O

GPIO462

ETPUC22

RXDB

GPIO

463 ETPUC22_RXDB_

GPIO463

eTPU C channel

eSCI B receive

—

I/O

GPIO463

ETPUC23

PCSD5

MAA0

GPIO

464 ETPUC23_PCSD5_

GPIO464

eTPU C channel

DSPI D peripheral chip select

ADC A Mux Address 0

ADC B Mux Address 0

GPIO

MAB0

GPIO464

ETPUC24

PCSD4

MAA1

I/O

465 ETPUC24_PCSD4_

GPIO465

eTPU C channel

DSPI D peripheral chip select

ADC A Mux Address 1

ADC B Mux Address 1

GPIO

V_DDEH7

—/WKPCFG

K24

J24

MAB1

GPIO465

I/O

Table 39. Signal Properties and Muxing Summary (continued)

Package

Location

State

after

Stateduring

RESET⁷

Signal Name²

Function⁴

Function Summary

RESET⁸

466 ETPUC25_PCSD3_

GPIO466

ETPUC25

eTPU C channel

I/O

V_DDEH7

—/WKPCFG

K25

K21

PCSD3

MAA2

DSPI D peripheral chip select

ADC A Mux Address 2

MAB2

ADC B Mux Address 2

GPIO466

ETPUC26

PCSD2

—

GPIO

I/O

467 ETPUC26_PCSD2_

GPIO467

eTPU C channel

V_DDEH7

—/WKPCFG

K26

L23

L24

L25

L26

J25

J26

K22

K23

K24

DSPI D peripheral chip select

—

GPIO467

ETPUC27

PCSD1

—

GPIO

I/O

468 ETPUC27_PCSD1_

GPIO468

eTPU C channel

DSPI D peripheral chip select

—

GPIO468

ETPUC28

PCSD0

—

GPIO

I/O

469 ETPUC28_PCSD0_

GPIO469

eTPU C channel

DSPI D peripheral chip select

—

GPIO469

ETPUC29

SCKD

GPIO

I/O

—

470 ETPUC29_SCKD_

GPIO470

eTPU C channel

DSPI D clock

—

GPIO470

ETPUC30

SOUTD

—

GPIO

I/O

471 ETPUC30_SOUTD_

GPIO471

eTPU C channel

DSPI D data output

—

GPIO471

GPIO

I/O

Table 39. Signal Properties and Muxing Summary (continued)

Package

Location

State

after

Stateduring

RESET⁷

Signal Name²

Function⁴

Function Summary

RESET⁸

472 ETPUC31_SIND_

ETPUC31

eTPU C channel

I/O

V_DDEH7

—/WKPCFG

M23

K25

GPIO472

SIND

—

DSPI D data input

—

I/O

GPIO472

GPIO

eMIOS

179 EMIOS0_ETPUA0_

GPIO179

EMIOS0

ETPUA0

—

eMIOS channel

eTPU A channel

—

I/O

V_DDEH4

—/WKPCFG

—/WKPCFG AE10 AC13

—/WKPCFG AF10 AB13

—/WKPCFG AD11 AD13

—/WKPCFG AE11 AE13

—/WKPCFG AF11 AF13

—

GPIO179

EMIOS1

ETPUA1

—

GPIO

I/O

180 EMIOS1_ETPUA1_

GPIO180

eMIOS channel

eTPU A channel

—

GPIO180

EMIOS2

ETPUA2

—

GPIO

I/O

181 EMIOS2_ETPUA2_

GPIO181

eMIOS channel

eTPU A channel

—

GPIO181

EMIOS3

ETPUA3

—

GPIO

I/O

182 EMIOS3_ETPUA3_

GPIO182

eMIOS channel

eTPU A channel

—

GPIO182

EMIOS4

ETPUA4

—

GPIO

I/O

183 EMIOS4_ETPUA4_

GPIO183

eMIOS channel

eTPU A channel

—

GPIO183

GPIO

I/O

Table 39. Signal Properties and Muxing Summary (continued)

Package

Location

State

after

Stateduring

RESET⁷

Signal Name²

Function⁴

Function Summary

RESET⁸

184 EMIOS5_ETPUA5_

GPIO184

EMIOS5

eMIOS channel

I/O

V_DDEH4

—/WKPCFG

—/WKPCFG AD12 AF14

—/WKPCFG AE12 AE14

—/WKPCFG AF12 AD14

—/WKPCFG AC13 AC14

—/WKPCFG AD13 AF15

—/WKPCFG AE13 AE15

ETPUA5

—

eTPU A channel

—

GPIO184

EMIOS6

ETPUA6

—

GPIO

I/O

185 EMIOS6_ETPUA6_

GPIO185

eMIOS channel

eTPU A channel

—

GPIO185

EMIOS7

ETPUA7

—

GPIO

I/O

186 EMIOS7_ETPUA7_

GPIO186

eMIOS channel

eTPU A channel

—

GPIO186

EMIOS8

ETPUA8

—

GPIO

I/O

187 EMIOS8_ETPUA8_

GPIO187

eMIOS channel

eTPU A channel

—

GPIO187

EMIOS9

ETPUA9

—

GPIO

I/O

188 EMIOS9_ETPUA9_

GPIO188

eMIOS channel

eTPU A channel

—

GPIO188

EMIOS10

SCKD

GPIO

I/O

189 EMIOS10_SCKD_

GPIO189

eMIOS channel

DSPI D clock

—

GPIO189

GPIO

I/O

Table 39. Signal Properties and Muxing Summary (continued)

Package

Location

State

after

Stateduring

RESET⁷

Signal Name²

Function⁴

Function Summary

RESET⁸

190 EMIOS11_SIND_

EMIOS11

eMIOS channel

I/O

V_DDEH4

—/WKPCFG

—/WKPCFG AF13 AB14

—/WKPCFG AF14 AD15

—/WKPCFG AE14 AC15

—/WKPCFG AC14 AF17

—/WKPCFG AD14 AE16

—/WKPCFG AF15 AD16

GPIO190

SIND

DSPI D data input

—

I/O

GPIO190

EMIOS12

SOUTC

—

GPIO

191 EMIOS12_SOUTC_

GPIO191

eMIOS channel

DSPI C data output

—

I/O

GPIO191

EMIOS13

SOUTD

—

GPIO

192 EMIOS13_SOUTD_

GPIO192

eMIOS channel

DSPI D data output

—

I/O

GPIO192

EMIOS14

IRQ0

GPIO

193 EMIOS14_IRQ0_

GPIO193

eMIOS channel

External interrupt request

FlexCAN D transmit

GPIO

CNTXD

GPIO193

EMIOS15

IRQ1

I/O

194 EMIOS15_IRQ1_

GPIO194

eMIOS channel

External interrupt request

FlexCAN D receive

GPIO

CNRXD

GPIO194

EMIOS16

ETPUB0

FR_DBG[3]

GPIO195

I/O

195 EMIOS16_ETPUB0_

GPIO195

eMIOS channel

eTPU B channel

FlexRay debug

GPIO

I/O

Table 39. Signal Properties and Muxing Summary (continued)

Package

Location

State

after

Stateduring

RESET⁷

Signal Name²

Function⁴

Function Summary

RESET⁸

196 EMIOS17_ETPUB1_

GPIO196

EMIOS17

eMIOS channel

I/O

V_DDEH4

—/WKPCFG

—/WKPCFG AE15 AB15

—/WKPCFG AC15 AD17

—/WKPCFG AD15 AB16

—/WKPCFG AF16 AF16

—/WKPCFG AE16 AE17

—/WKPCFG AC16 AC16

ETPUB1

FR_DBG[2]

GPIO196

EMIOS18

ETPUB2

FR_DBG[1]

GPIO197

EMIOS19

ETPUB3

FR_DBG[0]

GPIO198

EMIOS20

ETPUB4

—

eTPU B channel

FlexRay debug

GPIO

I/O

197 EMIOS18_ETPUB2_

GPIO197

eMIOS channel

eTPU B channel

FlexRay debug

GPIO

I/O

198 EMIOS19_ETPUB3_

GPIO198

eMIOS channel

eTPU B channel

FlexRay debug

GPIO

I/O

199 EMIOS20_ETPUB4_

GPIO199

eMIOS channel

eTPU B channel

—

I/O

GPIO199

EMIOS21

ETPUB5

—

GPIO

200 EMIOS21_ETPUB5_

GPIO200

eMIOS channel

eTPU B channel

—

I/O

GPIO200

EMIOS22

ETPUB6

—

GPIO

201 EMIOS22_ETPUB6_

GPIO201

eMIOS channel

eTPU B channel

—

I/O

GPIO201

GPIO

Table 39. Signal Properties and Muxing Summary (continued)

Package

Location

State

after

Stateduring

RESET⁷

Signal Name²

Function⁴

Function Summary

RESET⁸

202 EMIOS23_ETPUB7_

GPIO202

EMIOS23

eMIOS channel

I/O

V_DDEH4

—/WKPCFG

—/WKPCFG AD16 AA16

—/WKPCFG AF17 AC17

—/WKPCFG AE17 AF18

—/WKPCFG AD17 AE18

—/WKPCFG AC17 AD18

—/WKPCFG AF18 AC18

ETPUB7

—

eTPU B channel

—

GPIO202

EMIOS24

PCSB0

—

GPIO

I/O

—

203 EMIOS24_PCSB0_

GPIO203

eMIOS channel

DSPI B peripheral chip select

—

GPIO203

EMIOS25

PCSB1

—

GPIO

I/O

204 EMIOS25_PCSB1_

GPIO204

eMIOS channel

DSPI B peripheral chip select

—

GPIO204

EMIOS26

PCSB2

—

GPIO

I/O

432 EMIOS26_PCSB2_

GPIO432

eMIOS channel

DSPI B peripheral chip select

—

GPIO432

EMIOS27

PCSB3

—

GPIO

I/O

433 EMIOS27_PCSB3_

GPIO433

eMIOS channel

DSPI B peripheral chip select

—

GPIO433

EMIOS28

PCSC0

—

GPIO

I/O

—

434 EMIOS28_PCSC0_

GPIO434

eMIOS channel

DSPI C peripheral chip select

—

GPIO434

GPIO

I/O

Table 39. Signal Properties and Muxing Summary (continued)

Package

Location

State

after

Stateduring

RESET⁷

Signal Name²

Function⁴

Function Summary

RESET⁸

435 EMIOS29_PCSC1_

GPIO435

EMIOS29

eMIOS channel

I/O

V_DDEH4

—/WKPCFG

—/WKPCFG AE18 AB17

—/WKPCFG AD18 AF19

—/WKPCFG AC18 AA17

PCSC1

—

DSPI C peripheral chip select

—

GPIO435

EMIOS30

PCSC2

—

GPIO

I/O

436 EMIOS30_PCSC2_

GPIO436

eMIOS channel

DSPI C peripheral chip select

—

GPIO436

EMIOS31

PCSC5

—

GPIO

I/O

437 EMIOS31_PCSC5_

GPIO437

eMIOS channel

DSPI C peripheral chip select

—

GPIO437

GPIO

I/O

eQADC

ANA0⁹

ANA1⁹

ANA2⁹

ANA3⁹

ANA4⁹

ANA5⁹

ANA6⁹

ANA7⁹

eQADC A shared analog input

AE/up- V_{DDA_A1}

down

ANA0

ANA1

ANA2

ANA3

ANA4

ANA5

ANA6

ANA7

ANA0

ANA1

ANA2

ANA3

ANA4

ANA5

ANA6

ANA7

—

ANA0

ANA1

ANA2

ANA3

ANA4

ANA5

ANA6

ANA7

eQADC A shared analog input

AE/up- V_{DDA_A1}

down

AE/up- V_{DDA_A1}

down

AE/up- V_{DDA_A1}

down

AE/up- V_{DDA_A1}

down

AE/up- V_{DDA_A1}

down

AE/up- V_{DDA_A1}

down

AE/up- V_{DDA_A1}

down

Table 39. Signal Properties and Muxing Summary (continued)

Package

Location

State

after

Stateduring

RESET⁷

Signal Name²

Function⁴

Function Summary

RESET⁸

—

ANA8

ANA9

ANA8

eQADC A analog input

V_{DDA_A1}

V_{DDA_A0}

V_{DDA_B1}

V_{DDA_B0}

ANA8

ANA9

ANA10

ANA11

ANA12

ANA13

ANA14

ANA15

ANA16

ANA17

ANA18

ANA19

ANA20

ANA21

ANA22

ANA23

AN24

ANA8

ANA9

ANA10

ANA11

ANA12

ANA13

ANA14

ANA15

ANA16

ANA17

ANA18

ANA19

ANA20

ANA21

ANA22

ANA23

AN24

ANA9

ANA10

ANA11

ANA12

ANA13

ANA14

ANA15

ANA16

ANA17

ANA18

ANA19

ANA20

ANA21

ANA22

ANA23

AN24

eQADC A analog input

eQADC analog input

ANA10

ANA11

ANA12

ANA13

ANA14

ANA15

ANA16

ANA17

ANA18

ANA19

ANA20

ANA21

ANA22

ANA23

AN24

D10

C10

D11

C11

D12

C12

B12

D13

C13

B13

A13

B14

C14

D14

A14

B15

C15

D10

C10

D11

C11

C12

D12

B12

C13

D13

B13

A13

A14

B14

C14

B15

D14

C15

AN25

AN26

AN27

AN28

AN29

AN30

AN31

AN32

AN33

AN34

Table 39. Signal Properties and Muxing Summary (continued)

Package

Location

State

after

Stateduring

RESET⁷

Signal Name²

Function⁴

Function Summary

RESET⁸

—

AN35

AN36

AN37

AN38

AN39

ANB0

AN35

eQADC analog input

V_{DDA_B0}

V_{DDA_B1}

V_{DDA_B0}

AN35

AN36

AN37

AN38

AN39

ANB0

AN35

AN36

AN37

AN38

AN39

ANB0

D15

A15

C16

C17

D16

C18

D15

A15

C17

D16

C16

C18

AN36

AN37

AN38

AN39

ANB0

eQADC analog input

eQADC B shared analog input

AE/up- V_{DDA_B0}

down

—

ANB1

ANB2

ANB3

ANB4

ANB5

ANB6

ANB7

ANB1

ANB2

ANB3

ANB4

ANB5

ANB6

ANB7

eQADC B shared analog input

AE/up- V_{DDA_B0}

down

ANB1

ANB2

ANB3

ANB4

ANB5

ANB6

ANB7

ANB1

ANB2

ANB3

ANB4

ANB5

ANB6

ANB7

D17

D18

D19

C19

C20

B19

A20

D17

D18

D19

B19

A20

C20

C19

AE/up- V_{DDA_B0}

down

AE/up- V_{DDA_B0}

down

AE/up- V_{DDA_B0}

down

AE/up- V_{DDA_B0}

down

AE/up- V_{DDA_B0}

down

AE/up- V_{DDA_B0}

down

—

ANB8

ANB9

ANB8

eQADC B analog input

V_{DDA_B0}

ANB8

ANB9

ANB8

ANB9

B20

D20

B21

A21

C21

D21

A22

B22

C22

B20

A21

B21

C21

A22

B22

D20

C22

D21

ANB9

ANB10

ANB11

ANB12

ANB13

ANB14

ANB15

ANB16

ANB10

ANB11

ANB12

ANB13

ANB14

ANB15

ANB16

ANB10

ANB11

ANB12

ANB13

ANB14

ANB15

ANB16

ANB10

ANB11

ANB12

ANB13

ANB14

ANB15

ANB16

Table 39. Signal Properties and Muxing Summary (continued)

Package

Location

State

after

Stateduring

RESET⁷

Signal Name²

Function⁴

Function Summary

RESET⁸

—

ANB17

eQADC B analog input

V_{DDA_B0}

V_{RH_A}

ANB17

ANB18

ANB17

ANB18

A23

B23

C23

D22

A24

B24

A25

A12

A11

A19

A18

B18

B11

D22

A23

B23

C23

A24

B24

E20

A12

A11

A19

A18

B18

B11

ANB18

eQADC B analog input

ANB19

eQADC B analog input

ANB19

ANB20

eQADC B analog input

ANB20

ANB21

eQADC B analog input

ANB21

ANB22

eQADC B analog input

ANB22

ANB23

eQADC B analog input

ANB23

VRH_A

ADC A Voltage reference high

ADC A Voltage reference low

ADC B Voltage reference high

ADC B Voltage reference low

ADC B Reference bypass capacitor

ADC A Reference bypass capacitor

Internal logic supply input

ADC A Reference bypass capacitor

Ground

VDDINT

VSSINT

VDDINT

VSSINT

VRH_A

VRL_A

V_{RL_A}

VRL_A

VRH_B

V_{RH_B}

VRH_B

VRL_B

V_{RL_B}

VRL_B

REFBYPCB

REFBYPCA

VDDA_A0

VDDA_A1

REFBYPCA1

VSSA_A1

VDDA_B0

VDDA_B1

VSSA_B0

REFBYPCB1

REFBYPCB

REFBYPCA

VDDA_A

REFBYPCA1

VSSA_A

VDDA_B

VSSA_B

REFBYPCB1

V_{DDA_B0}

V_{DDA_A1}

REFBYPCB

REFBYPCA

VDDA_A0

VDDA_A1

REFBYPCB

REFBYPCA

VDDA_A0

VDDA_A1

VDDE V_{DDA_A0}

VDDE V_{DDA_A1}

V_{DDA_A1}REFBYPCA1 REFBYPCA1

A10

B10

A16

B16

B17

A17

A10

B10

A16

B16

B17

A17

VSSE

V_{SSA_A1}

VSSA_A1

VDDA_B0

VDDA_B1

VSSA_B0

VSSA_A1

VDDA_B0

VDDA_B1

VSSA_B0

Internal logic supply input

Ground

VDDE V_{DDA_B0}

VDDE V_{DDA_B1}

VSSE

V_{SSA_B0}

ADC B Reference bypass capacitor

V_{DDA_B0}REFBYPCB1 REFBYPCB1

FlexRay

248 FR_A_TX_

GPIO248

FR_A_TX

—

FlexRay A transfer

—

I/O

V_DDE2

—/Up

AD4

(–/– for Rev.1 (–/– for Rev.1

of the device) of the device)

—

GPIO248

GPIO

Table 39. Signal Properties and Muxing Summary (continued)

Package

Location

State

after

Stateduring

RESET⁷

Signal Name²

Function⁴

Function Summary

RESET⁸

249 FR_A_RX_

FR_A_RX

FlexRay A receive

V_DDE2

—/Up

AE3

AF3

AD5

AE4

AF4

AE3

AF3

AD5

AE4

AF4

GPIO249

(–/– for Rev.1 (–/– for Rev.1

of the device) of the device)

—

I/O

—

GPIO249

GPIO

250 FR_A_TX_EN_

GPIO250

FR_A_TX_EN

FlexRay A transfer enable

—/Up

(–/– for Rev.1 (–/– for Rev.1

of the device) of the device)

—

I/O

—

GPIO250

FR_B_TX

—

GPIO

251 FR_B_TX_

GPIO251

FlexRay B transfer

—/Up

(–/– for Rev.1 (–/– for Rev.1

of the device) of the device)

—

I/O

—

GPIO251

FR_B_RX

—

GPIO

252 FR_B_RX_

GPIO252

FlexRay B receive

—/Up

(–/– for Rev.1 (–/– for Rev.1

of the device) of the device)

—

I/O

—

GPIO252

FR_B_TX_EN

—

GPIO

253 FR_B_TX_EN_

GPIO253

FlexRay B transfer enable

—/Up

(–/– for Rev.1 (–/– for Rev.1

of the device) of the device)

—

I/O

—

GPIO253

GPIO

FlexCAN

83 CNTXA_TXDA_

GPIO83

CNTXA

TXDA

—

FlexCAN A transmit

V_DDEH4

—/Up

AF19 AE19

eSCI A transmit

—

I/O

GPIO83

GPIO

Table 39. Signal Properties and Muxing Summary (continued)

Package

Location

State

after

Stateduring

RESET⁷

Signal Name²

Function⁴

Function Summary

RESET⁸

84 CNRXA_RXDA_

CNRXA

FlexCAN A receive

V_DDEH4

—/Up

AE19 AD19

AD19 AC19

AC19 AA19

AF20 AF20

AE20 AE20

AD20 AD20

GPIO84

RXDA

—

eSCI A receive

—

I/O

GPIO84

CNTXB

PCSC3

—

GPIO

85 CNTXB_PCSC3_

GPIO85

FlexCAN B transmit

DSPI C peripheral chip select

—

I/O

GPIO85

CNRXB

PCSC4

—

GPIO

86 CNRXB_PCSC4_

GPIO86

FlexCAN B receive

DSPI C peripheral chip select

—

I/O

GPIO86

CNTXC

PCSD3

—

GPIO

87 CNTXC_PCSD3_

GPIO87

FlexCAN C transmit

DSPI D peripheral chip select

—

I/O

GPIO87

CNRXC

PCSD4

—

GPIO

88 CNRXC_PCSD4_

GPIO88

FlexCAN C receive

DSPI D peripheral chip select

—

I/O

GPIO88

CNTXD

—

GPIO

246 CNTXD_

GPIO246

FlexCAN D transmit

—

I/O

—

GPIO246

GPIO

Table 39. Signal Properties and Muxing Summary (continued)

Package

Location

State

after

Stateduring

RESET⁷

Signal Name²

Function⁴

Function Summary

RESET⁸

247 CNRXD_

CNRXD

FlexCAN D receive

V_DDEH4

—/Up

AC20 AC20

GPIO247

—

I/O

—

GPIO247

GPIO

eSCI

89 TXDA_

GPIO89

TXDA

—

eSCI A transmit

—

I/O

V_DDEH1

V_DDEH4

—/Up

—

GPIO89

RXDA

—

GPIO

90 RXDA _

GPIO90

eSCI A receive

—

GPIO90

TXDB

PCSD1

—

GPIO

91 TXDB_PCSD1_

GPIO91

eSCI B transmit

DSPI D peripheral chip select

—

I/O

GPIO91

RXDB

PCSD5

—

GPIO

92 RXDB_PCSD5_

GPIO92

eSCI B receive

DSPI D peripheral chip select

—

I/O

GPIO92

TXDC

ETRIG0

—

GPIO

244 TXDC_ETRIG0_

GPIO244

eSCI C transmit

AF23 AF23

eQADC trigger input

—

I/O

GPIO244

GPIO

Table 39. Signal Properties and Muxing Summary (continued)

Package

Location

State

after

Stateduring

RESET⁷

Signal Name²

Function⁴

Function Summary

RESET⁸

245 RXDC_

RXDC

eSCI C receive

V_DDEH5

—/Up

AD22 AD22

GPIO245

—

I/O

—

GPIO245

GPIO

DSPI

93 SCKA_PCSC1_

GPIO93

SCKA

PCSC1

—

DSPI A clock

I/O

V_DDEH3

—/Up

AD8

AF7

AD7

AE6

AC6

AB8

AE7

AC7

AD6

AC6

DSPI C peripheral chip select

—

I/O

GPIO93

SINA

GPIO

94 SINA_PCSC2_

GPIO94

DSPI A data input

PCSC2

—

DSPI C peripheral chip select

—

I/O

GPIO94

SOUTA

PCSC5

—

GPIO

95 SOUTA_PCSC5_

GPIO95

DSPI A data output

DSPI C peripheral chip select

—

I/O

GPIO95

PCSA0

PCSD2

—

GPIO

96 PCSA0_PCSD2_

GPIO96

DSPI A peripheral chip select

DSPI D peripheral chip select

—

I/O

GPIO96

PCSA1

GPIO

97 PCSA1_

DSPI A peripheral chip select

PCSE0_GPIO97

DSPI E peripheral chip select

—

GPIO97

GPIO

I/O

Table 39. Signal Properties and Muxing Summary (continued)

Package

Location

State

after

Stateduring

RESET⁷

Signal Name²

Function⁴

Function Summary

RESET⁸

98 PCSA2_

SOUTE_GPIO98

PCSA2

DSPI A peripheral chip select

V_DDEH3

—/Up

AC7

AE7

AE5

AD6

AE8

AE9

AF6

AD7

AE5

AA8

AC8

AB9

DSPI E data output

—

I/O

GPIO98

PCSA3

GPIO

99 PCSA3_

SINE_GPIO99

DSPI A peripheral chip select

DSPI E data input

—

I/O

GPIO99

PCSA4

GPIO

100 PCSA4_

SCKE_GPIO100

DSPI A peripheral chip select

DSPI E clock

—

I/O

GPIO100

PCSA5

ETRIG1

—

GPIO

101 PCSA5_ETRIG1_

GPIO101

DSPI A peripheral chip select

eQADC trigger input

—

I/O

—

I/O

GPIO101

SCKB

—

GPIO

102 SCKB_

GPIO102

DSPI B clock

—

GPIO102

SINB

—

GPIO

103 SINB_

GPIO103

DSPI B data input

—

I/O

—

GPIO103

GPIO

Table 39. Signal Properties and Muxing Summary (continued)

Package

Location

State

after

Stateduring

RESET⁷

Signal Name²

Function⁴

Function Summary

RESET⁸

104 SOUTB_

SOUTB

DSPI B data output

—

I/O

V_DDEH3

—/Up

AF9 AA10

GPIO104

—

GPIO104

PCSB0

PCSD2

—

GPIO

105 PCSB0_PCSD2_

GPIO105

DSPI B peripheral chip select

AD9

AC9

AF8

AE8

AD8

DSPI D peripheral chip select

—

I/O

GPIO105

PCSB1

PCSD0

—

GPIO

106 PCSB1_PCSD0_

GPIO106

DSPI B peripheral chip select

DSPI D peripheral chip select

I/O

—

I/O

—

GPIO106

PCSB2

SOUTC

—

GPIO

107 PCSB2_SOUTC_

GPIO107

DSPI B peripheral chip select

DSPI C data output

—

I/O

GPIO107

PCSB3

SINC

GPIO

108 PCSB3_SINC_

GPIO108

DSPI B peripheral chip select

AD10 AC9

DSPI C data input

—

I/O

GPIO108

PCSB4

SCKC

—

GPIO

109 PCSB4_SCKC_

GPIO109

DSPI B peripheral chip select

AC8

AF7

DSPI C clock

I/O

—

I/O

—

GPIO109

GPIO

Table 39. Signal Properties and Muxing Summary (continued)

Package

Location

State

after

Stateduring

RESET⁷

Signal Name²

Function⁴

Function Summary

RESET⁸

110 PCSB5_PCSC0_

PCSB5

DSPI B peripheral chip select

I/O

—

V_DDEH3

—/Up

AF6

AE6

GPIO110

PCSC0

—

DSPI C peripheral chip select

—

GPIO110

SCKC

GPIO

I/O

235 SCKC_SCK_C_LVDSP_

GPIO235

DSPI C clock

MH+

LVDS

V_DDEH4

—/Up

AD21 AD21

AE22 AE22

AF21 AF21

AE21 AE21

AC22 AC22

SCK_C_LVDSP

LVDS+ downstream signal positive

output clock

—

I/O

GPIO235

SINC

GPIO

236 SINC_SCK_C_LVDSM_

GPIO236

DSPI C data input

MH+

LVDS

V_DDEH4

—/Up

SCK_C_LVDSM

LVDS– downstream signal negative

output clock

—

I/O

GPIO236

SOUTC

GPIO

237 SOUTC_SOUT_C_LVDSP_

GPIO237

DSPI C data output

MH+

LVDS

SOUT_C_LVDSP

LVDS+ downstream signal positive

output data

—

I/O

GPIO237

PCSC0

GPIO

238 PCSC0_SOUT_C_LVDSM_

GPIO238

DSPI C peripheral chip select

MH+

LVDS

SOUT_C_LVDSM

LVDS– downstream signal negative

output data

—

I/O

GPIO238

PCSC1

—

GPIO

239 PCSC1_

GPIO239

DSPI C peripheral chip select

—

GPIO239

GPIO

I/O

Table 39. Signal Properties and Muxing Summary (continued)

Package

Location

State

after

Stateduring

RESET⁷

Signal Name²

Function⁴

Function Summary

RESET⁸

240 PCSC2_GPIO240

PCSC2

DSPI C peripheral chip select

—

I/O

V_DDEH5

—/Up

AE23 AE23

AD23 AD23

AF24 AF24

AE24 AE24

—

GPIO240

PCSC3

—

GPIO

241 PCSC3_GPIO241

242 PCSC4_GPIO242

243 PCSC5_GPIO243

DSPI C peripheral chip select

—

I/O

—

GPIO241

PCSC4

—

GPIO

DSPI C peripheral chip select

—

I/O

—

GPIO242

PCSC5

—

GPIO

DSPI C peripheral chip select

—

I/O

—

GPIO243

GPIO

EBI

256 D_CS0_

GPIO256

D_CS0

—

EBI chip select 0

—

V_DDE9

—/Up

—

AD9

—

GPIO256

D_CS2

D_ADD_DAT31

—

GPIO

I/O

257 D_CS2_D_ADD_DAT31_

GPIO257

EBI chip select 2

V_DDE8

Address and data in mux mode.

I/O

—

GPIO257

GPIO

I/O

Table 39. Signal Properties and Muxing Summary (continued)

Package

Location

State

after

Stateduring

RESET⁷

Signal Name²

Function⁴

Function Summary

RESET⁸

258 D_CS3_D_TEA_

D_CS3

EBI chip select 3

I/O

—

I/O

V_DDE8

—/Up

—

GPIO258

D_TEA

—

EBI transfer error acknowledge

—

GPIO258

D_ADD12

—

GPIO

259 D_ADD12_

GPIO259

EBI address bus

—

I/O

—

GPIO259

D_ADD13

—

GPIO

260 D_ADD13_

GPIO260

EBI address bus

—

I/O

—

GPIO260

D_ADD14

—

GPIO

261 D_ADD14_

GPIO261

EBI address bus

—

I/O

—

GPIO261

D_ADD15

—

GPIO

262 D_ADD15_

GPIO262

EBI address bus

—

I/O

—

GPIO262

D_ADD16

D_ADD_DAT16

—

GPIO

263 D_ADD16_D_ADD_DAT16_

GPIO263

EBI address bus

Address and data in mux mode.

I/O

—

I/O

—

GPIO263

GPIO

Table 39. Signal Properties and Muxing Summary (continued)

Package

Location

State

after

Stateduring

RESET⁷

Signal Name²

Function⁴

Function Summary

RESET⁸

264 D_ADD17_D_ADD_DAT17_

GPIO264

D_ADD17

EBI address bus

I/O

—

V_DDE8

V_DDE9

—/Up

—

D_ADD_DAT17

—

Address and data in mux mode.

—

GPIO264

D_ADD18

D_ADD_DAT18

—

GPIO

I/O

265 D_ADD18_D_ADD_DAT18_

GPIO265

EBI address bus

Address and data in mux mode.

I/O

—

GPIO265

D_ADD19

D_ADD_DAT19

—

GPIO

I/O

266 D_ADD19_D_ADD_DAT19_

GPIO266

EBI address bus

Address and data in mux mode.

I/O

—

GPIO266

D_ADD20

D_ADD_DAT20

—

GPIO

I/O

267 D_ADD20_D_ADD_DAT20_

GPIO267

EBI address bus

Address and data in mux mode.

I/O

—

GPIO267

D_ADD21

D_ADD_DAT21

—

GPIO

I/O

268 D_ADD21_D_ADD_DAT21_

GPIO268

EBI address bus

AB11

AD10

Address and data in mux mode.

I/O

—

GPIO268

D_ADD22

D_ADD_DAT22

—

GPIO

I/O

269 D_ADD22_D_ADD_DAT22_

GPIO269

EBI address bus

Address and data in mux mode.

I/O

—

GPIO269

GPIO

I/O

Table 39. Signal Properties and Muxing Summary (continued)

Package

Location

State

after

Stateduring

RESET⁷

Signal Name²

Function⁴

Function Summary

RESET⁸

270 D_ADD23_D_ADD_DAT23_

GPIO270

D_ADD23

EBI address bus

I/O

—

V_DDE9

—/Up

—

AE10

D_ADD_DAT23

—

Address and data in mux mode.

—

GPIO270

D_ADD24

D_ADD_DAT24

—

GPIO

I/O

271 D_ADD24_D_ADD_DAT24_

GPIO271

EBI address bus

AF10

AD11

AE11

AF11

AD12

Address and data in mux mode.

I/O

—

GPIO271

D_ADD25

D_ADD_DAT25

—

GPIO

I/O

272 D_ADD25_D_ADD_DAT25_

GPIO272

EBI address bus

Address and data in mux mode.

I/O

—

GPIO272

D_ADD26

D_ADD_DAT26

—

GPIO

I/O

273 D_ADD26_D_ADD_DAT26_

GPIO273

EBI address bus

Address and data in mux mode.

I/O

—

GPIO273

D_ADD27

D_ADD_DAT27

—

GPIO

I/O

274 D_ADD27_D_ADD_DAT27_

GPIO274

EBI address bus

Address and data in mux mode.

I/O

—

GPIO274

D_ADD28

D_ADD_DAT28

—

GPIO

I/O

275 D_ADD28_D_ADD_DAT28_

GPIO275

EBI address bus

Address and data in mux mode.

I/O

—

GPIO275

GPIO

I/O

Table 39. Signal Properties and Muxing Summary (continued)

Package

Location

State

after

Stateduring

RESET⁷

Signal Name²

Function⁴

Function Summary

RESET⁸

276 D_ADD29_D_ADD_DAT29_

GPIO276

D_ADD29

EBI address bus

V_DDE9

V_DDE10

—/Up

—

AB12

D_ADD_DAT29

—

Address and data in mux mode.

I/O

—

GPIO276

D_ADD30

D_ADD_DAT30

—

GPIO

I/O

277 D_ADD30_D_ADD_DAT30_

GPIO277

EBI address bus

AE12

P25

Address and data in mux mode.

I/O

—

GPIO277

D_ADD_DAT0

GPIO

I/O

278 D_ADD_DAT0_

GPIO278

EBI data only in non-mux mode.

Address and data in mux mode.

—

GPIO278

D_ADD_DAT1

GPIO

I/O

279 D_ADD_DAT1_

GPIO279

EBI data only in non-mux mode.

Address and data in mux mode.

V_DDE10

—/Up

—

P26

N24

N25

—

GPIO279

D_ADD_DAT2

GPIO

I/O

280 D_ADD_DAT2_

GPIO280

EBI data only in non-mux mode.

Address and data in mux mode.

—

GPIO280

D_ADD_DAT3

GPIO

I/O

281 D_ADD_DAT3_

GPIO281

EBI data only in non-mux mode.

Address and data in mux mode.

—

GPIO281

GPIO

I/O

Table 39. Signal Properties and Muxing Summary (continued)

Package

Location

State

after

Stateduring

RESET⁷

Signal Name²

Function⁴

Function Summary

RESET⁸

282 D_ADD_DAT4_

D_ADD_DAT4

EBI data only in non-mux mode.

Address and data in mux mode.

I/O

V_DDE10

—/Up

—

N26

M25

N22

M24

M23

GPIO282

—

GPIO282

D_ADD_DAT5

GPIO

I/O

283 D_ADD_DAT5_

GPIO283

EBI data only in non-mux mode.

Address and data in mux mode.

—

GPIO283

D_ADD_DAT6

GPIO

I/O

284 D_ADD_DAT6_

GPIO284

EBI data only in non-mux mode.

Address and data in mux mode.

—

GPIO284

D_ADD_DAT7

GPIO

I/O

285 D_ADD_DAT7_

GPIO285

EBI data only in non-mux mode.

Address and data in mux mode.

—

GPIO285

D_ADD_DAT8

GPIO

I/O

286 D_ADD_DAT8_

GPIO286

EBI data only in non-mux mode.

Address and data in mux mode.

—

GPIO286

GPIO

I/O

Table 39. Signal Properties and Muxing Summary (continued)

Package

Location

State

after

Stateduring

RESET⁷

Signal Name²

Function⁴

Function Summary

RESET⁸

287 D_ADD_DAT9_

D_ADD_DAT9

EBI data only in non-mux mode.

Address and data in mux mode.

I/O

V_DDE10

—/Up

—

M22

L26

L25

L24

L23

GPIO287

—

GPIO287

D_ADD_DAT10

GPIO

I/O

288 D_ADD_DAT10_

GPIO288

EBI data only in non-mux mode.

Address and data in mux mode.

—

GPIO288

D_ADD_DAT11

GPIO

I/O

289 D_ADD_DAT11_

GPIO289

EBI data only in non-mux mode.

Address and data in mux mode.

—

GPIO289

D_ADD_DAT12

GPIO

I/O

290 D_ADD_DAT12_

GPIO290

EBI data only in non-mux mode.

Address and data in mux mode.

—

GPIO290

D_ADD_DAT13

GPIO

I/O

291 D_ADD_DAT13

_GPIO291

EBI data only in non-mux mode.

Address and data in mux mode.

—

GPIO291

GPIO

I/O

Table 39. Signal Properties and Muxing Summary (continued)

Package

Location

State

after

Stateduring

RESET⁷

Signal Name²

Function⁴

Function Summary

RESET⁸

292 D_ADD_DAT14_GPIO292

D_ADD_DAT14

EBI data only in non-mux mode.

Address and data in mux mode.

I/O

V_DDE10

—/Up

—

L22

—

GPIO292

D_ADD_DAT15

GPIO

I/O

293 D_ADD_DAT15_GPIO293

EBI data only in non-mux mode.

Address and data in mux mode.

V_DDE10

—/Up

—

K26

—

I/O

—

GPIO293

D_RD_WR

—

GPIO

294 D_RD_WR_GPIO294

295 D_WE0_GPIO295

296 D_WE1_GPIO296

297 D_OE_GPIO297

EBI read/write

V_DDE10

V_DDE8

V_DDE10

—/Up

—

R26

—

I/O

—

GPIO294

D_WE0

—

GPIO

EBI write enable

—

I/O

—

GPIO295

D_WE1

—

GPIO

EBI write enable

—

I/O

—

GPIO296

D_OE

—

GPIO

EBI output enable

P23

—

I/O

—

GPIO297

GPIO

Table 39. Signal Properties and Muxing Summary (continued)

Package

Location

State

after

Stateduring

RESET⁷

Signal Name²

Function⁴

Function Summary

RESET⁸

298 D_TS_GPIO298

D_TS

EBI transfer start

—

I/O

V_DDE9

V_DDE10

V_DDE9

V_DDE8

—/Up

—

AE9

P24

AF9

AB10

—

GPIO298

D_ALE

—

GPIO

299 D_ALE_GPIO299

300 D_TA_GPIO300

301 D_CS1_GPIO301

302 D_BDIP_GPIO302

303 D_WE2_GPIO303

EBI Address Latch Enable

—

I/O

—

I/O

—

GPIO299

D_TA

—

GPIO

EBI transfer acknowledge

—

GPIO300

D_CS1

—

GPIO

EBI chip select

—

I/O

—

GPIO301

D_BDIP

—

GPIO

EBI burst data in progress

—

I/O

—

GPIO302

D_WE2

—

GPIO

EBI write enable

—

I/O

—

GPIO303

GPIO

Table 39. Signal Properties and Muxing Summary (continued)

Package

Location

State

after

Stateduring

RESET⁷

Signal Name²

Function⁴

Function Summary

RESET⁸

304 D_WE3_GPIO304

D_WE3

EBI write enable

—

I/O

V_DDE8

—/Up

—

GPIO304

D_ADD9

—

GPIO

305 D_ADD9_GPIO305

306 D_ADD10_GPIO306

307 D_ADD11_GPIO307

EBI address bus

—

I/O

—

GPIO305

D_ADD10

—

GPIO

EBI address bus

—

I/O

—

GPIO306

D_ADD11

—

GPIO

EBI address bus

—

I/O

—

GPIO307

GPIO

Reset and Clocks

—

RESET

External reset input

External reset output

V_DDEH1

RESET/Up

230 RSTOUT

RSTOUT

V_DDEH1RSTOUT/Low

RSTOUT/

High

211 BOOTCFG0_IRQ2_

GPIO211

BOOTCFG0

IRQ2

Boot configuration

V_DDEH1

BOOTCFG/

Down

—/Down

—

I/O

GPIO211

GPIO

Table 39. Signal Properties and Muxing Summary (continued)

Package

Location

State

after

Stateduring

RESET⁷

Signal Name²

Function⁴

Function Summary

RESET⁸

212 BOOTCFG1_IRQ3_

GPIO212

BOOTCFG1

Boot configuration

V_DDEH1

BOOTCFG/

Down

—/Down

IRQ3

External interrupt request

—

I/O

GPIO212

WKPCFG

GPIO

213 WKPCFG_NMI_

GPIO213¹⁰

Weak pull configuration input

WKPCFG/Up

PLLCFG/Up

—/Up

—

GPIO213

PLLCFG0

IRQ4

GPIO

208 PLLCFG0_IRQ4_

GPIO208

FMPLL mode configuration input

External interrupt request

—

—/Up

—

I/O

GPIO208

PLLCFG1

IRQ5

GPIO

209 PLLCFG1_IRQ5_GPIO209

FMPLL mode configuration input

External interrupt request

DSPI D data output

GPIO

—/Up

SOUTD

GPIO209

PLLCFG2

I/O

—

PLLCFG2

FMPLL mode configuration input

PLLCFG/

Down

—

Down

—

XTAL

Crystal oscillator output

Crystal oscillator input

EBI system clock output

V_DD33

V_DDE9

XTAL

AC26 AC26

AB26 AB26

EXTAL

229 D_CLKOUT

D_CLKOUT

CLKOUT/

Enabled

CLKOUT/

Enabled

—

AF12

214 ENGCLK

ENGCLK

EBI engineering clock output

V_DDE2

ENGCLK/

Enabled

ENGCLK/

Enabled

AD1

Note: EXTCLK (External clock input)

selected through SIU register)

JTAG and Nexus

(see footnote¹¹about resets)

–

—

EVTI

Nexus event in

V_DDE2

—/Up

EVTI/Up

Table 39. Signal Properties and Muxing Summary (continued)

Package

Location

State

after

Stateduring

RESET⁷

Signal Name²

Function⁴

Function Summary

RESET⁸

–

227 EVTO

EVTO

Nexus event out

V_DDE2

ABS/Up

EVTO/HI

(the BAM uses this pin to

select if auto baud rate is on

or off)

–

219 MCKO

MCKO

MDO0¹⁴

—

Nexus message clock out

V_DDE2

O/Low

Disabled¹³

See Note¹⁵

220 MDO0_GPIO220

221 MDO1_GPIO221

222 MDO2_GPIO222

223 MDO3_GPIO223

75 MDO4_GPIO75

Nexus message data out

See Note¹⁵

–

—

I/O

—

GPIO220

MDO1¹⁴

—

GPIO

–

Nexus message data out

V_DDE2

O/Low

—/Down

—

I/O

—

GPIO221

MDO2¹⁴

—

GPIO

–

Nexus message data out

—

I/O

—

GPIO222

MDO3¹⁴

—

GPIO

–

Nexus message data out

—

I/O

—

GPIO223

MDO4¹⁴

—

GPIO

–

Nexus message data out

—

I/O

—

GPIO75

GPIO

Table 39. Signal Properties and Muxing Summary (continued)

Package

Location

State

after

Stateduring

RESET⁷

Signal Name²

Function⁴

Function Summary

RESET⁸

–

76 MDO5_GPIO76

MDO5¹⁴

Nexus message data out

—

I/O

V_DDE2

O/Low

—/Down

—

GPIO76

MDO6¹⁴

—

GPIO

–

77 MDO6_GPIO77

78 MDO7_GPIO78

79 MDO8_GPIO79

80 MDO9_GPIO80

81 MDO10_GPIO81

Nexus message data out

—

I/O

—

GPIO77

MDO7¹⁴

—

GPIO

–

Nexus message data out

—

I/O

—

GPIO78

MDO8¹⁴

—

GPIO

–

Nexus message data out

—

I/O

—

GPIO79

MDO9¹⁴

—

GPIO

–

Nexus message data out

—

I/O

—

GPIO80

MDO10¹⁴

—

GPIO

–

Nexus message data out

—

I/O

—

GPIO81

GPIO

Table 39. Signal Properties and Muxing Summary (continued)

Package

Location

State

after

Stateduring

RESET⁷

Signal Name²

Function⁴

Function Summary

RESET⁸

–

82 MDO11_GPIO82

MDO11¹⁴

Nexus message data out

—

I/O

V_DDE2

O/Low

—/Down

AA1

AA2

AA3

—

GPIO82

MDO12¹⁴

—

GPIO

–

231 MDO12_GPIO231

232 MDO13_GPIO232

233 MDO14_GPIO233

234 MDO15_GPIO234

Nexus message data out

—

I/O

—

GPIO231

MDO13¹⁴

—

GPIO

–

Nexus message data out

AA1

AA2

AA3

—

I/O

—

GPIO232

MDO14¹⁴

—

GPIO

–

Nexus message data out

—

I/O

—

GPIO233

MDO15¹⁴

—

GPIO

–

Nexus message data out

—

I/O

—

GPIO234

MSEO0¹⁴

MSEO1¹⁴

RDY

GPIO

–

224 MSEO0

225 MSEO1

226 RDY

Nexus message start/end out

Nexus ready output

JTAG test clock input

JTAG test data input

JTAG test data output

JTAG test mode select input

V_DDE2

O/Low

MSEO/HI

RDY/HI

O/Low

—

TCK

TDI

TCK

TCK/Down

TDI/Up

TCK/Down

TDI/Up

AB2

AC2

AB1

AB3

AB2

AC2

AB1

AB3

TDI

228 TDO

TMS

TDO

TDO/Up

TMS/Up

TDO/Up

TMS/Up

—

TMS

Table 39. Signal Properties and Muxing Summary (continued)

Package

Location

State

after

Stateduring

RESET⁷

Signal Name²

Function⁴

Function Summary

RESET⁸

–

—

JCOMP

JTAG TAP controller enable

V_DDE2

JCOMP/Down JCOMP/Down

—

TEST

Test mode select (not for customer

use)

V_DDEH1

TEST/Down

—

VDDSYN

VSSSYN

VSTBY

VDDSYN

VSSSYN

VSTBY

Clock synthesizer power input

Clock synthesizer ground input

SRAM standby power input

I/O VDDE

V_DDSYN

V_DDEH1

V_DDREG

VDDSYN

VSSSYN

VSTBY

VDDSYN

VSSSYN

VSTBY

AD26 AD26

AA26 AA26

VSSE

VHV

REGSEL

Selects regulator mode

(Linear/Switch mode)

REGSEL

W23 W23

—

REGCTL

Regulator controller output to

base/gate of power transistor

V_DDREG

REGCTL

Y26

—

VSSFL

Tie to V_SS

VSS

V_DDREG

VSSFL

AB25 AB25

AA25 AA25

VDDREG

Source voltage for on-chip regulators

and Low voltage detect circuits

VDDINT V_DDREG

VDDREG

The GPIO number is the same as the corresponding pad configuration register (SIU_PCRn) number in pins that have GPIO functionality. For pins that do not

have GPIO functionality, this number is the PCR number.

The primary signal name is used as the pin label on the BGA map for identification purposes. However, the primary signal function is not available on all devices

and is indicated by a dash in the following table columns: Signal Functions, P/F/G, and I/O Type.

P/A/G stands for Primary/Alternate/GPIO . This column indicates which function on a pin is Primary, Alternate 1, Alternate 2, (Alternate n) and GPIO.

Each line in the Function column corresponds to a separate signal function on the pin. For all device I/O pins, the primary, alternate, or GPIO signal functions

are designated in the PA field of the SIU_PCRn registers except where explicitly noted.

MH = High voltage, medium speed

F = Fast speed

FS = Fast speed with slew

AE = Analog with ESD protection circuitry (up/down = pull up and pull down circuits included in the pad)

VHV = Very high voltage

VDDE (fast I/O) and VDDEH (slow I/O) power supply inputs are grouped into segments. Each segment of VDDEH pins can connect to a separate 3.3–5.0 V

(+5%/–10%) power supply input. Each segment of VDDE pins can connect to a separate 1.8–3.3 V (±10%) power supply.

All pins are sampled after the internal POR is negated. The terminology used in this column is: O – output, I – input, Up – weak pull up enabled, Down – weak

pulldown enabled, Low – output driven low, High – output driven high, ABS — Auto Baud Select (during Reset or until JCOMP assertion). A dash on the left side

of the slash denotes that both the input and output buffers for the pin are off. A dash on the right side of the slash denotes that there is no weak pull up/down

enabled on the pin. The signal name to the left or right of the slash indicates the pin is enabled.

The Function After Reset of a GPI function is general purpose input. A dash on the left side of the slash denotes that both the input and output buffers for the pin

are off. A dash on the right side of the slash denotes that there is no weak pull up/down enabled on the pin.

During and just after POR negates, internal pull resistors can be enabled, resulting in as much as 4 mA of current draw. The pull resistors are disabled when the

system clock propagates through the device.

¹⁰NMI function is selected using the SIU_IREER/SIU_IFEER registers and has priority over any other function on this pin.

¹¹Nexus reset is different than system reset; MDO0-11 are enabled in RPM or FPM trace modes, while MDO12-15 are enabled in FPM trace mode only. MSEO

and MCKO are also dependent on trace (RPM or FPM) being enabled.

¹²The Nexus pins don’t have a “primary” function as they are not configured by the SIU. The pins are selected by asserting JCOMP and configuring the NPC. SIU

values have no effect on the function of these pins once enabled.

¹³MCKO is disabled from reset; it can be enabled from the tool (controlled by Nexus NPC_PCR register).

¹⁴Do not connect pin directly to a power supply or ground.

¹⁵While JCOMP is negated, the MDO0 pad is pulled up because of the default values in its SIU PCR. When JCOMP is asserted, the MDO0 pad is enabled as an

output and goes low when the system clock is present.

Revision History

Appendix B Revision History

Table 40 describes the changes made to this document between revisions.

Table 40. Revision History

Revision

Date

Description

Rev 1

Rev 2

5 Aug 2011

Initial customer release

21 Dec 2011

Added information about specs 1a through 1d in the PMC Electrical Specifications table.

Updated the footnote reference (changed from ¹³to ¹⁴) of spec 18 of the PMC Electrical

Specifications table.

Updated the Operating Current 5.0 V Supplies @ fsys = 180MHz VDDA Max value

(changed from 30 to 50).

Updated footnote ¹of the VDD33 Pad Average DC Current table (changed IDDE to

IDD33).

Updated the pF value of 11 SRC/DSC Fast with Slew Rate (changed from 2.6 to 200) in

the Pad AC Specifications (VDDEH = 5.0 V, VDDE = 3.3 V) table.

Added a footnote for ANA0-ANA7 (⁹) functions in the “Signal Properties and Muxing

Summary” table.

Added a footnote for MDO0-MDO15 (¹⁴) and MSEO0 functions in the “Signal Properties

and Muxing Summary” table.

Updated figure numbers 25, 27, 29, and 31: Added specs 1-4.

Changed the title of the “PFCPR1 Settings” table to “BIUCR1/BIUCR3”.

Added a new row “Load” under “Termination” in the “DSPI LVDS Pad Specification” table.

Updated the “Max” and “Typical” values of “Delay, Z to Normal”, “Rise/Fall Time”, and “Data

Frequency” in the “DSPI LVDS Pad Specification” table.

Changed “V_DDE” to “V_DDEH” in footnote ¹⁰of the “DC Electrical Specifications” table.

Made the following changes in the “DSPI Timing” table:

• Update the minimum peripheral bus frequencies for “Data Setup Time for Inputs” and

“Data Hold Time for Outputs”.

• Updated the maximum peripheral bus frequencies for “Data Valid (after SCK edge)”.

• Added “Master (LVDS)” information for “Data Valid (after SCK edge)” and “Data Hold

Time for Outputs”.

Changed the minimum voltage value of the “I/O Supply Voltage (fast I/O pads)” from

“1.62 V” to “3.0 V” in the “DC Electrical Specifications” table.

Changed “V_DDE” values from “1.62 V to 1.98 V” to “3.0 V to 3.6 V” in footnote ¹of the “Pad

AC Specifications (V_DDEH= 5.0 V, V_DDE= 3.3 V)” table.

Removed voltage ranges “1.62 V–1.98 V” and “2.25 V–2.75 V” from “Fast I/O Weak Pull

Up/Down Current” in the “DC Electrical Specifications” table.

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

109

Revision History

Table 40. Revision History (continued)

Description

Revision

Date

Rev 3

10 August 2012 Added minimum and maximum “Nominal bandgap reference voltage” values in the “PMC

Electrical Specifications” table.

Updated the maximum “Medium I/O Output Low Voltage” value (changed from 0.2 x V_DDEH

to 0.2 x V_DDEHand 0.15 x _VDDEH) in the “DC Electrical Specifications” table, moved

reference to the footnote ¹⁰(I_{OH_S}= {11.6} mA and I_{OL_S}= {17.7} mA for {medium} I/O

with V_DDEH= 4.5 V; I_{OH_S}= {5.4} mA and I_{OL_S}= {8.1} mA for {medium} I/O with VDDEH

= 3.0 V) to “0.2 x V_DDEH”, and added a new footnote ¹¹(IOL_S=2 mA) to “0.15 x V_DDEH”.

Updated footnote⁹(I_{OH_F}= {12,20,30,40} mA and I_{OL_F}= {24,40,50,65} mA for

{00,01,10,11} drive mode with V_DDE= 3.0 V): Removed “I_{OH_F}= {7,13,18,25} mA and

I_{OL_F}= {18,30,35,50} mA for {00,01,10,11} drive mode with V_DDE= 2.25 V;

I_{OH_F}= {3,7,10,16}mA and I_{OL_F}= {12,20,27,35} mA for {00,01,10,11} drive mode with

V_DDE= 1.62 V”.

Added minimum and maximum values to all rows of the “Power Management Control

(PMC) Specification” table.

Updated the “Accuracy” temperature values in the “Temperature Sensor Electrical

Specifications” table: Changed “–40 C to 100 C to 40 C to 150 C, removed the

correspnding “Typ” value, removed “100 C to 150 C, and added minimum (10) and

maximum (+10) values.

Added a new section “ADC Internal Resource Measurements” and moved “Power

Management Control (PMC) Specification”, “Standby RAM Regulator Electrical

Specifications”, “ADC Band Gap Reference / LVI Electrical Specifications”, and

“Temperature Sensor Electrical Specifications” tables to the section.

Changed “Minimum Data Retention at 25 °C ambient temperature” to “Minimum Data

Retention at 85 °C ambient temperature” in the “Flash EEPROM Module Life” table.

Added the following note after “Flash Program and Erase Specifications (Pending Si

characterization)” table in the “C90 Flash Memory Electrical Characteristics” section:

“The low, mid, and high address blocks of the flash arrays are erased (all bits set to 1)

before leaving the factory.

Updated the “DSPI LVDS Pad Specification” table: Changed maximum “Load” value from

“25” to “32”; minimum values for “Differential Output Voltage SRC=0b00 or 0b11,

SRC=0b01, SRC=0b10” from “150, 90, 160” to “215, 170, 260”; “Transmission lines

(Differential) to “Termination Resistance”; “Zc” to “RLoad”; and added the following

footnote: “The termination resistance spec is not meant to specify the receiver

termination requirements. They are there to establish the measurement criteria for the

specs in this table. As per the TIA/EIA-644A standard, the LVDS receiver termination

resistance can vary from 90 to 132  .

Rev 4

21 January 2016 Added a table “Flash Memory AC Timing Specifications”.

Updated the min and max values from -10 and +10 to -20 and +20 for “Accuracy” in the

“Temperature Sensor Electrical Specifications” table.

MPC5676R Microcontroller Data Sheet, Rev. 4

110

Freescale Semiconductor

Information in this document is provided solely to enable system and software

implementers to use Freescale products. There are no express or implied copyright

licenses granted hereunder to design or fabricate any integrated circuits based on the

information in this document.

How to Reach Us:

Home Page:

freescale.com

Web Support:

freescale.com/support

Freescale reserves the right to make changes without further notice to any products

herein. Freescale makes no warranty, representation, or guarantee regarding the

suitability of its products for any particular purpose, nor does Freescale assume any

liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation consequential or incidental

damages. “Typical” parameters that may be provided in Freescale data sheets and/or

specifications can and do vary in different applications, and actual performance may

vary over time. All operating parameters, including “typicals,” must be validated for each

customer application by customer’s technical experts. Freescale does not convey any

license under its patent rights nor the rights of others. Freescale sells products pursuant

to standard terms and conditions of sale, which can be found at the following

address:freescale.com/SalesTermsandConditions.

Freescale and the Freescale logo are trademarks of Freescale Semiconductor, inc. Reg.

U.S. Pat. & Tm. Off. the power Architecture and Power.org word marks and the Power

and Power.org logos and related marks are trademarks and service marks licensed by

Power.org. All other product or service names are the property of their respective

owners.

Document Number: MPC5676R

Rev. 4

16 Feb 2016

SPC5676RDK2MVU1 [NXP]

相关型号：

SPC5676RDK2MVU1R

SPC5676RDK2MVY1

SPC5676RDK2MVY1R

SPC56AP54L5

SPC56AP54x

SPC56AP60L3

SPC56AP60L5

SPC56AP60X

SPC56EC64L7

SPC56EC70L7

SPC56EC74L7

SPC56EC74L8