SPC56EC74L8 [STMICROELECTRONICS]
用于汽车车身和网关应用的32位Power Architecture MCU;
| 型号： | SPC56EC74L8 |
| 厂家： | 
ST |
| 描述： | 用于汽车车身和网关应用的32位Power Architecture MCU |
| 文件： | 总118页 (文件大小：1209K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SPC564Bxx
SPC56ECxx
32-bit MCU family built on the Power Architecture® for automotive
body electronics applications
Target specification
■ Communication interfaces
Features
– Up to 6 FlexCAN with 64 buffers each
®
■ e200z4d, 32-bit Power Architecture
– Up to 10 LINFlex/UART channels
– up to 120 MHz and 200 MIPs operation
– Up to 8 buffered DSPI channels
2
■ e200z0h, 32-bit Power Architecture
– I C interface
– up to 80 MHz and 75 MIPs operation
– One FleyRay (dual-ch.) with 128 buffers
■ Memory
– Up to 3 MByte on-chip Flash with ECC
– Fast Ethernet Controller
■ Cryptographic Services Engine (CSE)
– AES-128 en/decryption, CMAC auth.
– Secured device boot mode
– Up to 256 KByte on-chip SRAM with ECC
– 64KByte on-chip Data Flash with ECC
– 16-entry memory protection unit (MPU)
– User selectable Memory BIST
■ 32-ch. eDMA with multiple request sources
■ Clock generation
■ Interrupts
– 4 to 40 MHz main oscillator
– 16 MHz internal RC oscillator
– Software-controlled FMPLL
– 128 kHz internal RC oscillator
– 32 kHz auxiliary oscillator
– Clock Monitoring Unit (CMU)
– 255 interrupt sources with 16 priority levels
– Up to 54 ext. IRQ including 30 wake-up
■ GPIOs: from 147 (QFP176) to 199 (BGA256)
■ System timer units
– 8-ch. 32-bit periodic interrupt timer (PIT)
– 4-channel 32-bit system timer (STM)
– Safety System Watchdog Timer (SWT)
– Real-time clock timer (RTC/API)
■ Low power capabilities
– Ultra low power STANDBY
– CAN Sampler to store CAN ID in STBY
– Fast wake-up and exectute from RAM
■ eMIOS, 16-bit counter timed I/O units
– Up to 64 channels with PWM/MC/IC/OC
■ Exhaustive debugging capability
– Nexus 3+ interface on LBGA256 only
– Nexus 1 on all devices
■ Two ADC (10-bit and 12-bit)
– Up to 62 channels extendable to 90 ch.
– Multiple Analog Watchdog
■ Voltage supply
■ Dedicated diagnostic features for lighting
– Advanced shiffted PWM generation
– ADC conversion synchronized on PWM
– Single 5 V or 3.3 V supply
– On-chip Vreg with external ballast transitor
■ Operating temperature range -40 to 125 °C
Table 1.
Device summary
Part number
Package
1.5 MByte
2 MByte
3 MByte
SPC564B64L7
SPC56EC64L7
SPC564B64L8
SPC56EC64L8
SPC56EC64B3
SPC564B70L7
SPC56EC70L7
SPC564B70L8
SPC56EC70L8
SPC56EC70B3
SPC564B74L7
SPC56EC74L7
SPC564B74L8
SPC56EC74L8
SPC56EC74B3
LQFP176
LQFP208
BGA256
December 2011
Doc ID 17478 Rev 4
1/118
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.
www.st.com
1
Contents
SPC564Bxx - SPC56ECxx
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1
1.2
Document Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2
3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 15
3.1
3.2
3.3
Pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Functional ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.1
4.2
Parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.2.1
4.2.2
NVUSRO [PAD3V5V(0)] field description . . . . . . . . . . . . . . . . . . . . . . . 49
NVUSRO [PAD3V5V(1)] field description . . . . . . . . . . . . . . . . . . . . . . . 49
4.3
4.4
4.5
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.5.1
4.5.2
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.6
I/O pad electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.6.1
4.6.2
4.6.3
4.6.4
4.6.5
I/O pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
I/O input DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
I/O output DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
I/O pad current specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.7
4.8
RESET electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Power management electrical characteristics . . . . . . . . . . . . . . . . . . . . . 64
4.8.1
4.8.2
4.8.3
Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 64
VDD_BV options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Voltage monitor electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 66
4.9
Low voltage domain power consumption . . . . . . . . . . . . . . . . . . . . . . . . . 67
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Contents
4.10 Flash memory electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 69
4.10.1 Program/Erase characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
4.10.2 Flash memory power supply DC characteristics . . . . . . . . . . . . . . . . . . 71
4.10.3 Flash memory start-up/switch-off timings . . . . . . . . . . . . . . . . . . . . . . . 72
4.11 Electromagnetic compatibility (EMC) characteristics . . . . . . . . . . . . . . . . 72
4.11.1 Designing hardened software to avoid noise problems . . . . . . . . . . . . . 72
4.11.2 Electromagnetic interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4.11.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 73
4.12 Fast external crystal oscillator (4–40 MHz) electrical characteristics . . . . 74
4.13 Slow external crystal oscillator (32 kHz) electrical characteristics . . . . . . 76
4.14 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.15 Fast internal RC oscillator (16 MHz) electrical characteristics . . . . . . . . . 79
4.16 Slow internal RC oscillator (128 kHz) electrical characteristics . . . . . . . . 80
4.17 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.18 Fast Ethernet Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.18.1 MII Receive Signal Timing (RXD[3:0], RX_DV, RX_ER, and RX_CLK) . 92
4.18.2 MII Transmit Signal Timing (TXD[3:0], TX_EN, TX_ER, TX_CLK) . . . . 92
4.18.3 MII Async Inputs Signal Timing (CRS and COL) . . . . . . . . . . . . . . . . . . 93
4.18.4 MII Serial Management Channel Timing (MDIO and MDC) . . . . . . . . . 94
4.19 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
4.19.1 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
4.19.2 DSPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.19.3 Nexus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.19.4 JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
5
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
5.1
5.2
ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5.2.1
5.2.2
5.2.3
LQFP176 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . 107
LQFP208 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . 109
LBGA256 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . 111
6
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Appendix A Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
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Contents
SPC564Bxx - SPC56ECxx
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SPC564Bxx and SPC56ECxx family comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SPC564Bxx and SPC56ECxx series block summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
System pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Functional port pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Parameter classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
PAD3V5V(0) field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
PAD3V5V(1) field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Recommended operating conditions (3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Recommended operating conditions (5.0 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
LQFP thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
LBGA256 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
I/O input DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
I/O pull-up/pull-down DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
SLOW configuration output buffer electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 57
MEDIUM configuration output buffer electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 58
FAST configuration output buffer electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 58
Output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
I/O supplies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
I/O consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Reset electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Low voltage monitor electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Low voltage power domain electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Code flash memory—Program and erase specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Data flash memory—Program and erase specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Flash memory module life. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Flash memory read access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Flash memory power supply DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 71
Start-up time/Switch-off time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
EMI radiated emission measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Latch-up results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Crystal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Fast external crystal oscillator (4 to 40 MHz) electrical characteristics. . . . . . . . . . . . . . . . 75
Crystal motional characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Slow external crystal oscillator (32 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . 78
FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Fast internal RC oscillator (16 MHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 80
Slow internal RC oscillator (128 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . 81
ADC input leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
ADC conversion characteristics (10-bit ADC_0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Conversion characteristics (12-bit ADC_1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
MII Receive Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
MII transmit signal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
MII Async Inputs Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
MII serial management channel timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
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List of tables
SPC564Bxx - SPC56ECxx
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
On-chip peripherals current consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
DSPI timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Nexus debug port timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
JTAG characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
LQFP176 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
LQFP208 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
LBGA256 mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
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SPC564Bxx - SPC56ECxx
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
SPC564Bxx and SPC56ECxx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
176-pin LQFP configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
208-pin LQFP configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
256-pin BGA configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
I/O input DC electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Start-up reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Noise filtering on reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Voltage regulator capacitance connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Low voltage monitor vs. Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 10. Crystal oscillator and resonator connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 11. Fast external crystal oscillator (4 to 40 MHz) electrical characteristics. . . . . . . . . . . . . . . . 75
Figure 12. Crystal oscillator and resonator connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 13. lEquivalent circuit of a quartz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 14. Slow external crystal oscillator (32 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . 78
Figure 15. ADC_0 characteristic and error definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 16. Input equivalent circuit (precise channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 17. Input equivalent circuit (extended channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 18. Transient behavior during sampling phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 19. Spectral representation of input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 20. ADC_1 characteristic and error definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 21. MII receive signal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 22. MII transmit signal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 23. MII async inputs timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 24. MII serial management channel timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 25. DSPI classic SPI timing–master, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 26. DSPI classic SPI timing–master, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 27. DSPI classic SPI timing–slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 28. DSPI classic SPI timing–slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 29. DSPI modified transfer format timing–master, CPHA = 0. . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 30. DSPI modified transfer format timing–master, CPHA = 1. . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 31. DSPI modified transfer format timing–slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 32. DSPI modified transfer format timing–slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 33. DSPI PCS strobe (PCSS) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 34. Nexus output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 35. Nexus TDI, TMS, TDO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 36. Timing diagram - JTAG boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 37. LQFP176 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 38. LQFP208 mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 39. LBGA256 mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 40. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
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Introduction
SPC564Bxx - SPC56ECxx
1
Introduction
1.1
1.2
Document Overview
This document describes the features of the family and options available within the family
members, and highlights important electrical and physical characteristics of the SPC564Bxx
and SPC56ECxx device. To ensure a complete understanding of the device functionality,
refer also to the SPC564Bxx and SPC56ECxx Reference Manual.
Description
The SPC564Bxx and SPC56ECxx is a new family of next generation microcontrollers built
on the Power Architecture embedded category. This document describes the features of the
family and options available within the family members, and highlights important electrical
and physical characteristics of the device.
The SPC564Bxx and SPC56ECxx family expands the range of the CSPC560B
microcontroller family. It provides the scalability needed to implement platform approaches
and delivers the performance required by increasingly sophisticated software architectures.
The advanced and cost-efficient host processor core of the SPC564Bxx and SPC56ECxx
automotive controller family complies with the Power Architecture embedded category,
which is 100 percent user-mode compatible with the original Power Architecture user
instruction set architecture (UISA). It operates at speeds of up to 120 MHz and offers high
performance processing optimized for low power consumption. It also capitalizes on the
available development infrastructure of current Power Architecture devices and is supported
with software drivers, operating systems and configuration code to assist with users
implementations.
8/118
Doc ID 17478 Rev 4
(1)
Table 2.
Feature
SPC564Bxx and SPC56ECxx family comparison
SPC564B64 SPC56EC64
LQFP LQFP LQFP LQFP
176 208 176 208
e200z4d
SPC564B70
SPC56EC70
SPC564B74
SPC56EC74
LQFP LQFP LQFP BGA LQFP LQFP LQFP LQFP
BGA LQFP1
BGA
256
Package
256
76
208
176
208
256
176
208
176
208
CPU
e200z4d + e200z0h
e200z4d
e200z4d + e200z0h
e200z4d
e200z4d + e200z0h
Up to 120 MHz
Up to 120 MHz
Up to 120 MHz
(e200z4d)
(e200z4d)
(e200z4d)
Up to 120 MHz
(e200z4d)
Up to 120 MHz
(e200z4d)
Up to 120 MHz
(e200z4d)
Execution speed(2)
Up to 80 MHz
(e200z0h)(3)
Up to 80 MHz
(e200z0h)(3)
Up to 80 MHz
(e200z0h)(3)
Code flash memory
Data flash memory
SRAM
1.5 MB
2 MB
3 MB
4 x16 KB
128 KB
192 KB
160 KB
256 KB
192 KB
256 KB
MPU
16-entry
32 ch
eDMA(4)
10-bit ADC
dedicated(5),
(6)
27 ch 33 ch 27 ch
33 ch
27 ch 33 ch 27 ch
33 ch
27 ch 33 ch 27 ch
33 ch
shared with
12-bit ADC(7)
19 ch
10 ch
12-bit ADC
dedicated(8)
shared with
10-bit ADC(7)
19 ch
64 ch
CTU
Total timer I/O(9) eMIOS
64 ch, 16-bit
SCI (LINFlexD)
10
8
SPI (DSPI)
CAN (FlexCAN)(10)
6
(1)
Table 2.
Feature
SPC564Bxx and SPC56ECxx family comparison (continued)
SPC564B64 SPC56EC64 SPC564B70
LQFP LQFP LQFP LQFP LQFP LQFP LQFP BGA LQFP LQFP LQFP LQFP
SPC56EC70
SPC564B74
SPC56EC74
BGA LQFP1
BGA
256
Package
256
76
176
208
176
208
Yes
177
208
176
Yes
Yes
208
Yes
177
256
176
208
176
208
Yes
177
FlexRay
STCU(11)
Ethernet
No
No
No
I2C
1
32 kHz oscillator (SXOSC)
GPIO(12)
Yes
147
147
177
147
199
147
177
199
147
177
147
199
Nexus3
+
Nexus
3+
Nexus
3+
Debug
JTAG
JTAG
Optional
JTAG
Cryptographic Services
Engine (CSE)
1. Feature set dependent on selected peripheral multiplexing; table shows example.
2. Based on 125 °C ambient operating temperature and subject to full device characterisation.
3. The e200z0h can run at speeds up to 80 MHz. However, if system frequency is >80 MHz (e.g., e200z4d running at 120 MHz) the e200z0h needs to run at 1/2 system
frequency. There is a configurable e200z0 system clock divider for this purpose.
4. DMAMUX also included that allows for software selection of 32 out of a possible 57 sources.
5. Not shared with 12-bit ADC, but possibly shared with other alternate functions.
6. There are 23 dedicated ANS plus 4 dedicated ANX channels on LQPF176. For higher pin count packages, there are 29 dedicated ANS plus 4 dedicated ANX channels.
7. 16x precision channels (ANP) and 3x standard (ANS).
8. Not shared with 10-bit ADC, but possibly shared with other alternate functions.
9. As a minimum, all timer channels can function as PWM or Input Capture and Output Control. Refer to the eMIOS section of the device reference manual for information on
the channel configuration and functions.
10. CAN Sampler also included that allows ID of CAN message to be captured when in low power mode.
11. STCU controls MBIST activation and reporting.
12. Estimated I/O count for proposed packages based on multiplexing with peripherals.
SPC564Bxx - SPC56ECxx
Block diagram
2
Block diagram
Figure 1 shows the detailed block diagram of the SPC564Bxx and
SPC56ECxx.
Doc ID 17478 Rev 4
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Block diagram
SPC564Bxx - SPC56ECxx
Figure 1.
SPC564Bxx and SPC56ECxx block diagram
FEC
JTAGC
CSE
SRAM
Code Flash Data Flash
1.5 MB 64 KB
JTAG Port
Nexus Port
2
2
×
128 KB
2 ×
FlexRay
Instructions
Nexus 3+
e200z0h
Nexus
(Master)
×
SRAM
NMI0
NMI1
Flash memory
controller
Data
(Master)
controller
Instructions
(Master)
Data
Voltage
regulator
e200z4d
(Master)
(Slave)
Nexus 3+
NMI0
NMI1
Clocks
(Slave)
(Slave)
Interrupt requests
from peripheral
blocks
DMAMUX
MPU
registers
INTC
eDMA
CMU
CAN
Sampler
STCU
( Master)
FMPLL
8
×
16 x
Semaphores
MC_RGM MC_CGM MC_ME MC_PCU
Peripheral Bridge
WKPU
PIT RTI
ECSM
SSCM
RTC/API 4
× STM
BAM
SWT
(2)
(1)
10
LINFlexD
×
SIUL
Reset Control
27 ch or 33 ch
10-bit
ADC
10 ch
12-bit
ADC
8
×
6 ×
FlexCAN
2
32 ch
×
2
CTU
I C
1
×
1
×
DSPI
eMIOS
Interrupt
Request
External
Interrupt
Request
IMUX
GPIO &
Pad Control
(3)
(3)
I/O
ADC
BAM
CSE
CAN
CMU
CTU
Analog-to-Digital Converter
Boot Assist Module
Cryptographic Services Engine
Controller Area Network (FlexCAN)
Clock Monitor Unit
Legend:
JTAGC
JTAG controller
LINFlexD Local Interconnect Network Flexible with DMA support
MC_ME Mode Entry Module
MC_CGM Clock Generation Module
MC_PCU Power Control Unit
MC_RGM Reset Generation Module
MPU
Nexus
NMI
Cross Triggering Unit
DMAMUX DMA Channel Multiplexer
DSPI
eDMA
FlexCAN Controller Area Network controller modules
FEC
Memory Protection Unit
Nexus Development Interface
Non-Maskable Interrupt
Deserial Serial Peripheral Interface
enhanced Direct Memory Access
PIT_RTI Periodic Interrupt Timer with Real-Time Interrupt
RTC/API Real-Time Clock/ Autonomous Periodic Interrupt
Fast Ethenet Controller
eMIOS
ECSM
FMPLL
FlexRay
I2C
Enhanced Modular Input Output System
Error Correction Status Module
Frequency-Modulated Phase-Locked Loop
FlexRay Communication Controller
Inter-integrated Circuit Bus
SIUL
System Integration Unit Lite
Static Random-Access Memory
System Status Configuration Module
System Timer Module
Software Watchdog Timer
Self Test Control Unit
SRAM
SSCM
STM
SWT
STCU
WKPU
IMUX
INTC
Internal Multiplexer
Interrupt Controller
Wakeup Unit
1) 10 dedicated channels plus up to 19 shared channels
2) Package dependent. 27 or 33 dedicated channels plus up to 19 shared channels. See the device-comparison table.
. See the device-comparison table.
Notes:
3)
16 x precision channels (ANP) are mapped on input only I/O cells.
Table 3 summarizes the functions of the blocks present on the SPC564Bxx and
SPC56ECxx.
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SPC564Bxx - SPC56ECxx
Block diagram
Table 3.
SPC564Bxx and SPC56ECxx series block summary
Block Function
Analog-to-digital converter (ADC) Converts analog voltages to digital values
A block of read-only memory containing VLE code which is executed according
to the boot mode of the device
Boot assist module (BAM)
Clock monitor unit (CMU)
Cross triggering unit (CTU)
Monitors clock source (internal and external) integrity
Enables synchronization of ADC conversions with a timer event from the eMIOS
or from the PIT
Cryptographic Security Engine
(CSE)
Supports the encoding and decoding of any kind of data
Supports simultaneous connections between two master ports and three slave
ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus
width
Crossbar (XBAR) switch
DMA Channel Multiplexer
(DMAMUX)
Allows to route DMA sources (called slots) to DMA channels
Deserial serial peripheral
interface (DSPI)
Provides a synchronous serial interface for communication with external
devices
Provides a myriad of miscellaneous control functions for the device including
program-visible information about configuration and revision levels, a reset
status register, wakeup control for exiting sleep modes, and optional features
such as information on memory errors reported by error-correcting codes
Error Correction Status Module
(ECSM)
Enhanced Direct Memory Access Performs complex data transfers with minimal intervention from a host
(eDMA)
processor via “n” programmable channels.
Enhanced modular input output
system (eMIOS)
Provides the functionality to generate or measure events
Provides non-volatile storage for program code, constants and variables
Supports the standard CAN communications protocol
Flash memory
FlexCAN (controller area
network)
FMPLL (frequency-modulated
phase-locked loop)
Generates high-speed system clocks and supports programmable frequency
modulation
FlexRay (FlexRay communication
controller)
Provides high-speed distributed control for advanced automotive applications
Ethernet Media Access Controller (MAC) designed to support both 10 and 100
Mbps Ethernet/IEEE 802.3 networks
Fast Ethernet Controller (FEC)
Internal multiplexer (IMUX) SIUL
subblock
Allows flexible mapping of peripheral interface on the different pins of the device
A two wire bidirectional serial bus that provides a simple and efficient method of
data exchange between devices
Inter-integrated circuit (I2C™) bus
Interrupt controller (INTC)
JTAG controller
Provides priority-based preemptive scheduling of interrupt requests for both
e200z0h and e200z4d cores
Provides the means to test chip functionality and connectivity while remaining
transparent to system logic when not in test mode
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Block diagram
SPC564Bxx - SPC56ECxx
Table 3.
SPC564Bxx and SPC56ECxx series block summary (continued)
Block Function
LinFlexD (Local Interconnect
Network Flexible with DMA
support)
Manages a high number of LIN (Local Interconnect Network protocol)
messages efficiently with a minimum of CPU load
Provides hardware access control for all memory references generated in a
device
Memory protection unit (MPU)
Clock generation module
(MC_CGM)
Provides logic and control required for the generation of system and peripheral
clocks
Reduces the overall power consumption by disconnecting parts of the device
from the power supply via a power switching device; device components are
grouped into sections called “power domains” which are controlled by the PCU
Power control unit (MC_PCU)
Reset generation module
(MC_RGM)
Centralizes reset sources and manages the device reset sequence of the
device
Provides a mechanism for controlling the device operational mode and
modetransition sequences in all functional states; also manages the power
control unit, reset generation module and clock generation module, and holds
the configuration, control and status registers accessible for applications
Mode entry module (MC_ME)
Handles external events that must produce an immediate response, such as
power down detection
Non-Maskable Interrupt (NMI)
Nexus Development Interface
(NDI)
Provides real-time development capabilities for e200z0h and e200z4d core
processor
Periodic interrupt timer/ Real
Time Interrupt Timer (PIT_RTI)
Produces periodic interrupts and triggers
A free running counter used for time keeping applications, the RTC can be
configured to generate an interrupt at a predefined interval independent of the
mode of operation (run mode or low-power mode). Supports autonomous
periodic interrupt (API) function to generate a periodic wakeup request to exit a
low power mode or an interrupt request
Real-time counter (RTC/API)
Static random-access memory
(SRAM)
Provides storage for program code, constants, and variables
Provides control over all the electrical pad controls and up 32 ports with 16 bits
System integration unit lite (SIUL) of bidirectional, general-purpose input and output signals and supports up to 32
external interrupts with trigger event configuration
Provides system configuration and status data (such as memory size and
System status and configuration
status, device mode and security status), device identification data, debug
module (SSCM)
status port enable and selection, and bus and peripheral abort enable/disable
Provides a set of output compare events to support AutoSAR and operating
System timer module (STM)
system tasks
Provides the hardware support needed in multi-core systems for sharing
resources and provides a simple mechanism to achieve lock/unlock operations
Semaphores
via a single write access.
Supports external sources that can generate interrupts or wakeup events, of
which can cause non-maskable interrupt requests or wakeup events.
Wake Unit (WKPU)
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Doc ID 17478 Rev 4
SPC564Bxx - SPC56ECxx
Package pinouts and signal descriptions
3
Package pinouts and signal descriptions
The available LQFP pinouts and the LBGA ballmaps are provided in the following figures.
For functional port pin description, see Table 6.
Figure 2.
176-pin LQFP configuration
PB[3]
PC[9]
PC[14]
PC[15]
PJ[4]
PA[11]
1
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
PA[10]
2
PA[9]
3
PA[8]
4
PA[7]
5
PE[13]
PF[14]
VDD_HV_A
VSS_HV
PH[15]
PH[13]
PH[14]
PI[6]
6
7
PF[15]
8
VDD_HV_B
VSS_HV
PG[0]
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
PG[1]
PI[7]
PH[3]
PG[5]
PH[2]
PG[4]
PH[1]
PG[3]
PH[0]
PG[2]
PG[12]
PG[13]
PA[3]
PA[2]
PE[0]
PA[1]
PI[13]
PE[1]
PI[12]
PE[8]
LQFP176
Top view
PI[11]
PE[9]
VDD_LV
VSS_LV
PI[8]
PEp[10]
A[0]
PE[11]
VSS_HV
VDD_HV_A
VSS_HV
RESET
VSS_LV
VDD_LV
VRC_CTRL
PG[9]
PB[15]
PD[15]
PB[14]
PD[14]
PB[13]
PD[13]
PB[12]
PD[12]
VDD_HV_ADC1
VSS_HV_ADC1
PB[11]
PG[8]
PC[11]
PC[10]
PG[7]
98
97
PD[11]
PD[10]
PD[9]
96
PG[6]
95
PB[0]
94
PB[7]
PB[1]
93
PB[6]
PF[9]
92
PB[5]
PF[8]
91
VDD_HV_ADC0
VSS_HV_ADC0
PF[12]
PC[6]
90
89
NOTE
1) VDD_HV_B supplies the IO voltage domain for the
pins PE[12], PA[11], PA[10], PA[9], PA[8], PA[7],
PE[13], PF[14], PF[15], PG[0], PG[1], PH[3], PH[2],
PH[1], PH[0], PG[12], PG[13], and PA[3].
2)Availability of port pin alternate functions depends
on product selection.
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Package pinouts and signal descriptions
SPC564Bxx - SPC56ECxx
Figure 3.
208-pin LQFP configuration
PB[3]
PC[9]
1
2
3
4
5
6
7
8
9
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
PA[11]
PA[10]
PA[9]
PC[14]
PC[15]
PJ[4]
PA[8]
PA[7]
VDD_HV_A
VSS_HV
PH[15]
PE[13]
PF[14]
PF[15]
VDD_HV_B
VSS_HV
PG[0]
PH[13]
PH[14] 10
P[I6] 11
P[I7] 12
PG[1]
PG[5] 13
PG[4] 14
PG[3] 15
PG[2] 16
PA[2] 17
PH[3]
PH[2]
PH[1]
PH[0]
PG[12]
PE[0] 18
PA[1] 19
PE[1] 20
PE[8] 21
PE[9] 22
PE[10] 23
PA[0] 24
PG[13]
PA[3]
PI[13]
PI[12]
PI[11]
LQFP208
Top view
PI[10]
VDD_LV
VSS_LV
PI[9]
PE[11] 25
VSS_HV 26
VDD_HV_A 27
VSS_HV 28
RESET 29
VSS_LV 30
VDD_LV 31
VRC_CTRL 32
PG[9] 33
PG[8] 34
PC[11] 35
PC[10] 36
PG[7] 37
PG[6] 38
PB[0] 39
PB[1] 40
PK[1] 41
PK[2] 42
PK[3] 43
PK[4] 44
PK[5] 45
PK[6] 46
PK[7] 47
PK[8] 48
PF[9] 49
PI[8]
PB[15]
PD[15]
PB[14]
PD[14]
PB[13]
PD[13]
PB[12]
VDD_HV_A
VSS_HV
PD[12]
VDD_HV_ADC1
VSS_HV_ADC1
PB[11]
PD[11]
PD[10]
PD[9]
PJ[5]
PJ[6]
PJ[7]
PJ[8]
PB[7]
PB[6]
PF[8] 50
PF[12] 51
PC[6] 52
PB[5]
VDD_HV_ADC0
VSS_HV_ADC0
NOTE
1) VDD_HV_B supplies the IO voltage domain for the pins PE[12], PA[11], PA[10], PA[9], PA[8], PA[7], PE[13], PF[14],
PF[15], PG[0], PG[1], PH[3], PH[2], PH[1], PH[0], PG[12], PG[13], and PA[3].
2) Availability of port pin alternate functions depends on product selection.
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SPC564Bxx - SPC56ECxx
Package pinouts and signal descriptions
Figure 4.
256-pin BGA configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PC[15]
PB[2]
PC[13]
PI[1]
PE[7]
PH[8]
PE[2]
PE[4]
PC[4]
PE[3]
PH[9]
PI[4]
PH[11]
PE[14]
PA[10]
PG[11]
A
B
C
D
E
F
A
B
C
D
E
F
PH[13]
PH[14]
PG[5]
PG[3]
PA[2]
PC[14]
PC[8]
PC[9]
PJ[4]
PC[12]
PL[0]
PI[3]
PI[0]
PE[6]
PH[7]
PH[5]
PH[6]
PH[4]
PK[10]
PL[1]
PE[5]
PC[5]
PC[0]
PA[5]
PC[2]
PC[3]
PA[6]
PH[12]
PE[15]
PI[5]
PG[10]
PG[14]
PG[15]
PG[0]
PA[11]
PE[12]
PF[14]
PG[1]
PH[3]
PA[9]
PA[7]
PA[8]
PE[13]
PH[2]
VDD_HV
_A
VSS_LV VDD_HV
_A
PI[6]
PI[7]
PB[3]
PG[2]
PE[1]
PA[0]
PK[15]
VDD_LV
PL[2]
PI[2]
VDD_LV
PK[9]
PC[1]
PM[1]
PM[5]
PH[10]
PM[0]
PL[13]
PF[15]
PH[0]
PH[15]
PA[1]
VSS_LV
PM[6]
PL[15]
PL[12]
PL[14]
PM[2]
PK[12]
PK[13]
PK[14]
PM[3]
PM[4]
PL[11]
PJ[5]
VDD_HV
_A
PG[4]
PE[0]
PK[11]
PH[1]
PG[12]
PI[12]
VSS_LV
PI[9]
PG[13]
PA[3]
PE[8]
PE[9]
PE[10]
PE[11]
PL[3]
VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV
VDD_HV
_B
PI[13]
G
H
J
G
H
J
VDD_HV
_A
PK[1]
PG[9]
PC[11]
PK[2]
PF[9]
PC[7]
PA[14]
PJ[15]
PJ[14]
PL[4]
VSS_LV
VSS_LV
VSS_LV
VSS_LV
PK[6]
VSS_LV
VSS_LV
VSS_LV
VSS_LV
PK[7]
VSS_HV VSS_HV VSS_HV VSS_HV
VDD_HV VDD_LV
_A
PI[11]
PI[10]
PB[15]
VSS_HV VRC_CT VDD_LV
RL
PL[5]
VSS_LV
VSS_LV
VSS_LV
PK[8]
VSS_HV VSS_HV VSS_HV
PD[15]
PD[14]
PD[12]
PB[11]
PB[5]
PI[8]
PD[13]
PB[12]
PD[10]
PB[6]
RESET
PC[10]
PG[6]
VSS_LV
PG[7]
PB[1]
PG[8]
PB[0]
PK[4]
PC[6]
PF[13]
PJ[11]
PK[0]
PL[6]
VSS_LV
VSS_LV
PL[8]
VDD_LV
VDD_LV
PL[9]
VDD_LV
VDD_LV
PL[10]
PD[2]
PB[14]
PB[13]
PD[11]
PJ[6]
K
L
K
L
PL[7]
VDD_HV
_ADC1
PK[5]
PJ[13]
PJ[9]
VSS_HV_
ADC1
M
N
P
R
T
M
N
P
R
T
PK[3]
PF[8]
VDD_HV
_A
PB[10]
PF[0]
PF[6]
VDD_HV
_A
PJ[1]
PD[9]
PJ[7]
PB[7]
PB[4]
PF[12]
PF[11]
PJ[12]
PF[10]
PA[15]
PA[4]
PA[12]
PF[2]
PF[1]
PF[5]
PF[7]
PJ[3]
PI[15]
PD[4]
PD[0]
PI[14]
PD[7]
PD[8]
PD[6]
PD[5]
PJ[8]
PA[13]
PJ[10]
PF[3]
PF[4]
VDD_LV
VSS_LV
PJ[2]
PJ[0]
PD[3]
VDD_HV
_ADC0
XTAL
EXTAL
PB[9]
PB[8]
PD[1]
VSS_HV_
ADC0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Notes:
1) VDD_HV_B supplies the IO voltage domain for the pins PE[12], PA[11], PA[10], PA[9], PA[8], PA[7], PE[13], PF[14],
PF[15], PG[0], PG[1], PH[3], PH[2], PH[1], PH[0], PG[12], PG[13], and PA[3].
2)Availability of port pin alternate functions depends on product selection.
3.1
Pad types
In the device the following types of pads are available for system pins and functional port
pins:
(a)
S = Slow
(a), (b)
M = Medium
(a), (b)
F = Fast
(a)
I = Input only with analog feature
A = Analog
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Package pinouts and signal descriptions
SPC564Bxx - SPC56ECxx
3.2
System pins
The system pins are listed in Table 4.
Table 4.
Port pin
System pin descriptions
Function
Pin number
I/O
Pad
RESET
config.
direction type
Input, weak
pull-up only
after
Bidirectional reset with Schmitt-Trigger
characteristics and noise filter.
RESET
I/O
I
M
29
58
29
74
K1
T8
PHASE2
Analog input of the oscillator amplifier
EXTAL circuit. Needs to be grounded if oscillator
bypass mode is used.
A(1)
—
—
Analog output of the oscillator amplifier
circuit, when the oscillator is not in bypass
mode.
XTAL
I/O
A(1)
56
72
T7
Analog input for the clock generator when
the oscillator is in bypass mode.
1. For analog pads, it is not recommended to enable IBE if APC is enabled to avoid extra current in middle range voltage.
3.3
Functional ports
The functional port pins are listed in Table 5.
a. See the I/O pad electrical characteristics in the device datasheet for details.
b. All medium and fast pads are in slow configuration by default at reset and can be configured as fast or medium.
For example, Fast/Medium pad will be Medium by default at reset. Similarly, Slow/Medium pad will be Slow by
default. Only exception is PC[1] which is in medium configuration by default (refer to PCR.SRC in the reference
manual, Pad Configuration Registers (PCR0—PCR198)).
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Package pinouts and signal descriptions
Pin number
Table 5.
Functional port pin descriptions
Port
pin
PCR
Function
AF0
AF1
AF2
AF3
—
GPIO[0]
E0UC[0]
SIUL
I/O
I/O
O
eMIOS_0
MC_CGM
eMIOS_0
WKPU
CLKOUT
E0UC[13]
WKPU[19]
CAN1RX
PA[0]
PA[1]
PA[2]
PA[3]
PCR[0]
M/S Tristate
24
19
24
19
G4
I/O
I
I
—
FlexCAN_1
AF0
AF1
AF2
AF3
—
GPIO[1]
E0UC[1]
—
SIUL
eMIOS_0
—
I/O
I/O
—
—
I
PCR[1]
PCR[2]
PCR[3]
—
—
S
S
Tristate
Tristate
F3
WKPU[2]
CAN3RX
NMI[0](3)
WKPU
FlexCAN_3
WKPU
—
I
—
I
AF0
AF1
AF2
AF3
—
GPIO[2]
E0UC[2]
—
SIUL
eMIOS_0
—
I/O
I/O
—
O
I
17
17
F1
MA[2]
ADC_0
WKPU
WKPU
WKPU[3]
NMI[1](3)
—
I
AF0
AF1
AF2
AF3
—
GPIO[3]
E0UC[3]
SIUL
eMIOS_0
LINFlexD_5
DSPI_1
FEC
I/O
I/O
O
O
I
LIN5TX
CS4_1
M/S Tristate
114
138
G16
RX_ER_CLK
EIRQ[0]
—
SIUL
I
—
ADC1_S[0]
ADC_1
I
AF0
AF1
AF2
AF3
—
GPIO[4]
E0UC[4]
—
SIUL
eMIOS_0
—
I/O
I/O
—
I/O
I
PA[4]
PA[5]
PCR[4]
PCR[5]
S
Tristate
51
61
T2
CS0_1
LIN5RX
WKPU[9]
DSPI_1
LINFlexD_5
WKPU
—
I
AF0
AF1
AF2
GPIO[5]
E0UC[5]
LIN4TX
SIUL
I/O
eMIOS_0
LINFlexD_4
I/O M/S Tristate
O
146
170
C10
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Package pinouts and signal descriptions
SPC564Bxx - SPC56ECxx
Pin number
Table 5.
Functional port pin descriptions (continued)
Port
pin
PCR
Function
AF0
AF1
AF2
AF3
—
GPIO[6]
E0UC[6]
—
SIUL
eMIOS_0
—
I/O
I/O
—
O
I
PA[6]
PA[7]
PCR[6]
S
Tristate
147
128
171
152
D11
C15
CS1_1
LIN4RX
EIRQ[1]
DSPI_1
LINFlexD_4
SIUL
—
I
AF0
AF1
AF2
AF3
—
GPIO[7]
E0UC[7]
LIN3TX
—
SIUL
eMIOS_0
LINFlexD_3
—
I/O
I/O
O
—
I
PCR[7]
M/S Tristate
RXD[2]
EIRQ[2]
ADC1_S[1]
FEC
—
SIUL
I
—
ADC_1
I
AF0
AF1
AF2
AF3
—
GPIO[8]
E0UC[8]
E0UC[14]
—
SIUL
eMIOS_0
eMIOS_0
—
I/O
I/O
I/O
Input,
weak
pull-up
—
PA[8]
PCR[8]
M/S
129
153
B16
RXD[1]
EIRQ[3]
ABS[0]
LIN3RX
FEC
I
I
I
I
—
SIUL
—
MC_RGM
LINFlexD_3
—
AF0
AF1
AF2
AF3
—
GPIO[9]
E0UC[9]
—
SIUL
eMIOS_0
—
I/O
I/O
—
O
I
Pull-
down
PA[9]
PCR[9]
M/S
130
131
154
155
B15
A15
CS2_1
RXD[0]
FAB
DSPI1
FEC
—
MC_RGM
I
AF0
AF1
AF2
AF3
—
GPIO[10]
E0UC[10]
SDA
SIUL
eMIOS_0
I2C
I/O
I/O
I/O
O
I
PA[10]
PCR[10]
LIN2TX
COL
LINFlexD_2
FEC
M/S Tristate
—
ADC1_S[2]
SIN_1
ADC_1
DSPI_1
I
—
I
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SPC564Bxx - SPC56ECxx
Package pinouts and signal descriptions
Pin number
Table 5.
Functional port pin descriptions (continued)
Port
pin
PCR
Function
AF0
AF1
AF2
AF3
—
GPIO[11]
E0UC[11]
SCL
SIUL
eMIOS_0
I2C
I/O
I/O
I/O
—
—
—
PA[11]
PA[12]
PCR[11]
M/S Tristate
132
156
B14
RX_ER
EIRQ[16]
LIN2RX
ADC1_S[3]
FEC
I
I
I
I
—
SIUL
—
LINFlexD_2
ADC_1
—
AF0
AF1
AF2
AF3
—
GPIO[12]
—
SIUL
—
I/O
—
I/O
O
I
E0UC[28]
CS3_1
EIRQ[17]
SIN_0
eMIOS_0
DSPI1
SIUL
PCR[12]
S
Tristate
53
69
P6
—
DSPI_0
I
AF0
AF1
AF2
AF3
GPIO[13]
SOUT_0
E0UC[29]
—
SIUL
DSPI_0
eMIOS_0
—
I/O
O
PA[13]
PA[14]
PCR[13]
PCR[14]
M/S Tristate
52
50
66
58
R5
P4
I/O
—
AF0
AF1
AF2
AF3
—
GPIO[14]
SCK_0
SIUL
DSPI_0
DSPI_0
eMIOS_0
SIUL
I/O
I/O
CS0_0
I/O M/S Tristate
E0UC[0]
EIRQ[4]
I/O
I
AF0
AF1
AF2
AF3
—
GPIO[15]
CS0_0
SIUL
DSPI_0
DSPI_0
eMIOS_0
WKPU
I/O
I/O
PA[15]
PB[0]
PCR[15]
PCR[16]
SCK_0
I/O M/S Tristate
48
39
56
39
R2
L3
E0UC[1]
WKPU[10]
I/O
I
AF0
AF1
AF2
AF3
GPIO[16]
CAN0TX
E0UC[30]
LIN0TX
SIUL
I/O
FlexCAN_0
eMIOS_0
LINFlexD_0
O
M/S Tristate
I/O
I
AF0
AF1
AF2
—
GPIO[17]
—
SIUL
—
I/O
—
E0UC[31]
LIN0RX
WKPU[4]
CAN0RX
eMIOS_0
LINFlexD_0
WKPU
I/O
PB[1]
PCR[17]
S
Tristate
40
40
M2
I
I
I
—
—
FlexCAN_0
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Package pinouts and signal descriptions
SPC564Bxx - SPC56ECxx
Pin number
Table 5.
Functional port pin descriptions (continued)
Port
pin
PCR
Function
AF0
AF1
AF2
AF3
GPIO[18]
LIN0TX
SDA
SIUL
LINFlexD_0
I2C
I/O
O
PB[2]
PB[3]
PCR[18]
M/S Tristate
176
208
A2
D4
I/O
I/O
E0UC[30]
eMIOS_0
AF0
AF1
AF2
AF3
—
GPIO[19]
E0UC[31]
SCL
SIUL
eMIOS_0
I2C
I/O
I/O
I/O
—
I
PCR[19]
PCR[20]
PCR[21]
PCR[22]
PCR[23]
S
Tristate
Tristate
Tristate
Tristate
Tristate
1
1
—
—
WKPU[11]
LIN0RX
WKPU
LINFlexD_0
—
I
AF0
AF1
AF2
AF3
—
GPI[20]
SIUL
—
I
—
—
—
I
—
—
—
PB[4]
PB[5]
PB[6]
PB[7]
I
88
91
92
93
104
107
108
109
T16
N13
N14
R16
—
—
ADC0_P[0]
ADC1_P[0]
ADC_0
ADC_1
—
I
AF0
AF1
AF2
AF3
—
GPI[21]
SIUL
—
I
—
—
—
I
—
—
—
I
—
—
ADC0_P[1]
ADC1_P[1]
ADC_0
ADC_1
—
I
AF0
AF1
AF2
AF3
—
GPI[22]
SIUL
—
I
—
—
—
I
—
—
—
I
—
—
ADC0_P[2]
ADC1_P[2]
ADC_0
ADC_1
—
I
AF0
AF1
AF2
AF3
—
GPI[23]
SIUL
—
I
—
—
—
I
—
—
—
I
—
—
ADC0_P[3]
ADC1_P[3]
ADC_0
ADC_1
—
I
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Package pinouts and signal descriptions
Pin number
Table 5.
Functional port pin descriptions (continued)
Port
pin
PCR
Function
AF0
AF1
AF2
AF3
—
GPI[24]
—
SIUL
—
I
—
—
—
—
—
—
—
PB[8]
PCR[24]
I
—
61
77
T11
ADC0_S[0]
ADC1_S[4]
WKPU[25]
OSC32k_XTAL(4)
ADC_0
ADC_1
WKPU
SXOSC
I
I
I
I
—
—
—
AF0
AF1
AF2
AF3
—
GPI[25]
—
SIUL
—
I
—
—
—
I
—
—
—
—
PB[9](5) PCR[25]
I
—
60
76
T10
ADC0_S[1]
ADC1_S[5]
WKPU[26]
OSC32k_EXTAL4
ADC_0
ADC_1
WKPU
SXOSC
—
I
—
I
—
I
AF0
AF1
AF2
AF3
—
GPIO[26]
SOUT_1
CAN3TX
—
SIUL
DSPI_1
FlexCAN_3
—
I/O
O
—
—
I
PB[10] PCR[26]
S
Tristate
62
78
N7
ADC0_S[2]
ADC1_S[6]
WKPU[8]
ADC_0
ADC_1
WKPU
—
I
—
I
AF0
AF1
AF2
AF3
—
GPIO[27]
E0UC[3]
—
SIUL
eMIOS_0
—
I/O
I/O
—
I/O
I
PB[11] PCR[27]
PB[12] PCR[28]
PB[13] PCR[29]
S
S
S
Tristate
Tristate
Tristate
97
117
123
125
M13
L14
L15
CS0_0
DSPI_0
ADC_0
ADC0_S[3]
AF0
AF1
AF2
AF3
—
GPIO[28]
E0UC[4]
—
SIUL
eMIOS_0
—
I/O
I/O
—
O
101
103
CS1_0
DSPI_0
ADC_0
ADC0_X[0]
I
AF0
AF1
AF2
AF3
—
GPIO[29]
E0UC[5]
—
SIUL
eMIOS_0
—
I/O
I/O
—
O
CS2_0
DSPI_0
ADC_0
ADC0_X[1]
I
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Package pinouts and signal descriptions
SPC564Bxx - SPC56ECxx
Pin number
Table 5.
Functional port pin descriptions (continued)
Port
pin
PCR
Function
AF0
AF1
AF2
AF3
—
GPIO[30]
E0UC[6]
—
SIUL
eMIOS_0
—
I/O
I/O
—
O
PB[14] PCR[30]
PB[15] PCR[31]
S
Tristate
Tristate
105
107
127
129
K15
K16
CS3_0
DSPI_0
ADC_0
ADC0_X[2]
I
AF0
AF1
AF2
AF3
—
GPIO[31]
E0UC[7]
—
SIUL
eMIOS_0
—
I/O
I/O
—
O
S
CS4_0
DSPI_0
ADC_0
ADC0_X[3]
I
AF0
AF1
AF2
AF3
GPIO[32]
SIUL
—
I/O
—
I
Input,
weak
pull-up
—
TDI
—
PC[0](6) PCR[32]
PC[1](6) PCR[33]
M/S
154
149
178
173
B10
D9
JTAGC
—
—
AF0
AF1
AF2
AF3
GPIO[33]
—
SIUL
—
I/O
—
O
F/M Tristate
M/S Tristate
TDO
—
JTAGC
—
—
AF0
AF1
AF2
AF3
—
GPIO[34]
SCK_1
CAN4TX
—
SIUL
DSPI_1
FlexCAN_4
—
I/O
I/O
O
PC[2]
PC[3]
PCR[34]
PCR[35]
145
144
169
168
B11
C11
—
I
EIRQ[5]
SIUL
AF0
AF1
AF2
AF3
—
GPIO[35]
CS0_1
MA[0]
SIUL
DSPI_1
ADC_0
—
I/O
I/O
O
—
S
Tristate
CAN1RX
CAN4RX
EIRQ[6]
FlexCAN_1
FlexCAN_4
SIUL
I
I
I
—
—
AF0
AF1
AF2
AF3
ALT4
—
GPIO[36]
E1UC[31]
—
SIUL
eMIOS_1
—
I/O
I/O
—
PC[4]
PCR[36]
M/S Tristate
159
183
A9
FR_B_TX_EN
SIN_1
Flexray
DSPI_1
FlexCAN_3
SIUL
O
I
—
CAN3RX
EIRQ[18]
I
—
I
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Package pinouts and signal descriptions
Pin number
Table 5.
Functional port pin descriptions (continued)
Port
pin
PCR
Function
AF0
AF1
AF2
AF3
ALT4
—
GPIO[37]
SOUT_1
CAN3TX
—
SIUL
DSPI_1
FlexCAN_3
—
I/O
O
O
PC[5]
PC[6]
PC[7]
PC[8]
PC[9]
PCR[37]
PCR[38]
PCR[39]
PCR[40]
PCR[41]
M/S Tristate
158
44
45
175
2
182
52
53
207
2
B9
N3
N4
B3
C3
L1
—
O
I
FR_A_TX
EIRQ[7]
Flexray
SIUL
AF0
AF1
AF2
AF3
GPIO[38]
LIN1TX
E1UC[28]
—
SIUL
LINFlexD_1
eMIOS_1
—
I/O
O
S
S
S
S
Tristate
Tristate
Tristate
Tristate
I/O
—
AF0
AF1
AF2
AF3
—
GPIO[39]
—
SIUL
—
I/O
—
I/O
—
I
E1UC[29]
—
eMIOS_1
—
LIN1RX
WKPU[12]
LINFlexD_1
WKPU
—
I
AF0
AF1
AF2
AF3
GPIO[40]
LIN2TX
E0UC[3]
—
SIUL
LINFlexD_2
eMIOS_0
—
I/O
O
I/O
—
AF0
AF1
AF2
AF3
—
GPIO[41]
—
SIUL
—
I/O
—
I/O
—
I
E0UC[7]
—
eMIOS_0
—
LIN2RX
WKPU[13]
LINFlexD_2
WKPU
—
I
AF0
AF1
AF2
AF3
GPIO[42]
CAN1TX
CAN4TX
MA[1]
SIUL
I/O
O
FlexCAN_1
FlexCAN_4
ADC_0
PC[10] PCR[42]
PC[11] PCR[43]
M/S Tristate
36
36
35
O
O
AF0
AF1
AF2
AF3
—
GPIO[43]
—
SIUL
—
I/O
—
—
O
I
—
—
MA[2]
ADC_0
FlexCAN_1
FlexCAN_4
WKPU
S
Tristate
35
K4
CAN1RX
CAN4RX
WKPU[5]
—
I
—
I
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25/118
Package pinouts and signal descriptions
SPC564Bxx - SPC56ECxx
Pin number
Table 5.
Functional port pin descriptions (continued)
Port
pin
PCR
Function
AF0
AF1
AF2
AF3
ALT4
—
GPIO[44]
E0UC[12]
—
SIUL
eMIOS_0
—
I/O
I/O
—
—
O
205
PC[12] PCR[44]
—
—
M/S Tristate
173
B4
FR_DBG[0]
SIN_2
Flexray
DSPI_2
SIUL
I
—
EIRQ[19]
I
AF0
AF1
AF2
AF3
ALT4
GPIO[45]
E0UC[13]
SOUT_2
—
SIUL
eMIOS_0
DSPI_2
—
I/O
I/O
O
206
PC[13] PCR[45]
PC[14] PCR[46]
M/S Tristate
M/S Tristate
174
A3
B2
—
O
FR_DBG[1]
Flexray
AF0
AF1
AF2
AF3
ALT4
—
GPIO[46]
E0UC[14]
SCK_2
SIUL
eMIOS_0
DSPI_2
—
I/O
I/O
I/O
—
O
3
3
—
FR_DBG[2]
EIRQ[8]
Flexray
SIUL
I
GPIO[47]
E0UC[15]
CS0_2
SIUL
eMIOS_0
DSPI_2
—
I/O
I/O
I/O
—
O
AF0
AF1
AF2
AF3
ALT4
4
PC[15] PCR[47]
M/S Tristate
4
A1
—
FR_DBG[3]
EIRQ[20]
Flexray
SIUL
I
AF0
AF1
AF2
AF3
—
GPI[48]
—
SIUL
—
I
—
—
—
I
—
—
PD[0]
PCR[48]
—
—
I
Tristate
Tristate
77
93
R12
ADC0_P[4]
ADC1_P[4]
WKPU[27]
ADC_0
ADC_1
WKPU
—
I
—
I
AF0
AF1
AF2
AF3
—
GPI[49]
—
SIUL
—
I
—
—
—
I
—
—
PD[1]
PCR[49]
—
—
I
78
94
T13
ADC0_P[5]
ADC1_P[5]
WKPU[28]
ADC_0
ADC_1
WKPU
—
I
—
I
26/118
Doc ID 17478 Rev 4
SPC564Bxx - SPC56ECxx
Package pinouts and signal descriptions
Pin number
Table 5.
Functional port pin descriptions (continued)
Port
pin
PCR
Function
AF0
AF1
AF2
AF3
—
GPI[50]
SIUL
—
I
—
—
—
—
—
PD[2]
PD[3]
PD[4]
PD[5]
PD[6]
PD[7]
PCR[50]
I
I
I
I
I
I
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
79
80
81
82
83
84
95
96
N11
R13
P12
T14
R14
P13
—
—
—
ADC0_P[6]
ADC1_P[6]
ADC_0
ADC_1
I
I
—
AF0
AF1
AF2
AF3
—
GPI[51]
SIUL
—
I
—
—
—
I
—
—
—
PCR[51]
PCR[52]
PCR[53]
PCR[54]
PCR[55]
—
—
ADC0_P[7]
ADC1_P[7]
ADC_0
ADC_1
—
I
AF0
AF1
AF2
AF3
—
GPI[52]
SIUL
—
I
—
—
—
I
—
—
—
97
—
—
ADC0_P[8]
ADC1_P[8]
ADC_0
ADC_1
—
I
AF0
AF1
AF2
AF3
—
GPI[53]
SIUL
—
I
—
—
—
I
—
—
—
98
—
—
ADC0_P[9]
ADC1_P[9]
ADC_0
ADC_1
—
I
AF0
AF1
AF2
AF3
—
GPI[54]
SIUL
—
I
—
—
—
I
—
—
—
99
—
—
ADC0_P[10]
ADC1_P[10]
ADC_0
ADC_1
—
I
AF0
AF1
AF2
AF3
—
GPI[55]
SIUL
—
I
—
—
—
I
—
—
—
100
—
—
ADC0_P[11]
ADC1_P[11]
ADC_0
ADC_1
—
I
Doc ID 17478 Rev 4
27/118
Package pinouts and signal descriptions
SPC564Bxx - SPC56ECxx
Pin number
Table 5.
Functional port pin descriptions (continued)
Port
pin
PCR
Function
AF0
AF1
AF2
AF3
—
GPI[56]
SIUL
—
I
—
—
—
I
—
—
—
PD[8]
PD[9]
PCR[56]
I
I
I
I
Tristate
Tristate
Tristate
Tristate
87
94
95
96
103
P14
N16
M14
M15
—
—
ADC0_P[12]
ADC1_P[12]
ADC_0
ADC_1
—
I
AF0
AF1
AF2
AF3
—
GPI[57]
SIUL
—
I
—
—
—
I
—
—
—
PCR[57]
114
115
—
—
ADC0_P[13]
ADC1_P[13]
ADC_0
ADC_1
—
I
AF0
AF1
AF2
AF3
—
GPI[58]
SIUL
—
I
—
—
—
I
—
—
—
PD[10] PCR[58]
—
—
ADC0_P[14]
ADC1_P[14]
ADC_0
ADC_1
—
I
AF0
AF1
AF2
AF3
—
GPI[59]
SIUL
—
I
—
—
—
I
—
—
—
116
PD[11] PCR[59]
—
—
ADC0_P[15]
ADC1_P[15]
ADC_0
ADC_1
—
I
AF0
AF1
AF2
AF3
—
GPIO[60]
CS5_0
SIUL
DSPI_0
eMIOS_0
—
I/O
O
PD[12] PCR[60]
PD[13] PCR[61]
E0UC[24]
—
I/O
—
I
S
S
Tristate
Tristate
100
102
120
124
L13
K14
ADC0_S[4]
ADC_0
AF0
AF1
AF2
AF3
—
GPIO[61]
CS0_1
SIUL
DSPI_1
eMIOS_0
—
I/O
I/O
I/O
—
I
E0UC[25]
—
ADC0_S[5]
ADC_0
AF0
AF1
AF2
AF3
ALT4
—
GPIO[62]
CS1_1
SIUL
DSPI_1
eMIOS_0
—
I/O
O
E0UC[26]
—
I/O
—
O
PD[14] PCR[62]
S
Tristate
104
126
K13
FR_DBG[0]
ADC0_S[6]
Flexray
ADC_0
I
28/118
Doc ID 17478 Rev 4
SPC564Bxx - SPC56ECxx
Package pinouts and signal descriptions
Pin number
Table 5.
Functional port pin descriptions (continued)
Port
pin
PCR
Function
AF0
AF1
AF2
AF3
ALT4
—
GPIO[63]
CS2_1
SIUL
DSPI_1
eMIOS_0
—
I/O
O
E0UC[27]
—
I/O
PD[15] PCR[63]
S
S
Tristate
Tristate
106
128
18
J13
—
O
I
FR_DBG[1]
ADC0_S[7]
Flexray
ADC_0
AF0
AF1
AF2
AF3
—
GPIO[64]
E0UC[16]
—
SIUL
eMIOS_0
—
I/O
I/O
—
—
I
PE[0]
PE[1]
PCR[64]
PCR[65]
18
20
G2
F4
—
—
CAN5RX
WKPU[6]
FlexCAN_5
WKPU
—
I
AF0
AF1
AF2
AF3
GPIO[65]
E0UC[17]
CAN5TX
—
SIUL
eMIOS_0
FlexCAN_5
—
I/O
I/O
O
M/S Tristate
M/S Tristate
20
—
AF0
AF1
AF2
AF3
ALT4
—
GPIO[66]
E0UC[18]
—
SIUL
eMIOS_0
—
I/O
I/O
—
—
O
180
PE[2]
PCR[66]
—
—
156
A7
FR_A_TX_EN
SIN_1
Flexray
DSPI_1
SIUL
I
—
EIRQ[21]
I
AF0
AF1
AF2
AF3
—
GPIO[67]
E0UC[19]
SOUT_1
—
SIUL
eMIOS_0
DSPI_1
—
I/O
I/O
O
—
I
181
184
PE[3]
PE[4]
PCR[67]
PCR[68]
M/S Tristate
157
160
A10
FR_A_RX
WKPU[29]
Flexray
WKPU
—
I
AF0
AF1
AF2
AF3
ALT4
—
GPIO[68]
E0UC[20]
SCK_1
—
SIUL
eMIOS_0
DSPI_1
—
I/O
I/O
I/O
—
O
M/S Tristate
A8
FR_B_TX
EIRQ[9]
Flexray
SIUL
I
Doc ID 17478 Rev 4
29/118
Package pinouts and signal descriptions
SPC564Bxx - SPC56ECxx
Pin number
Table 5.
Functional port pin descriptions (continued)
Port
pin
PCR
Function
AF0
AF1
AF2
AF3
—
GPIO[69]
E0UC[21]
CS0_1
SIUL
eMIOS_0
DSPI_1
ADC_0
Flexray
WKPU
I/O
I/O
I/O
O
185
PE[5]
PE[6]
PCR[69]
PCR[70]
M/S Tristate
M/S Tristate
161
167
B8
B6
MA[2]
FR_B_RX
WKPU[30]
I
—
I
AF0
AF1
AF2
AF3
—
GPIO[70]
E0UC[22]
CS3_0
SIUL
eMIOS_0
DSPI_0
ADC_0
SIUL
I/O
I/O
O
191
MA[1]
O
EIRQ[22]
I
AF0
AF1
AF2
AF3
—
GPIO[71]
E0UC[23]
CS2_0
SIUL
eMIOS_0
DSPI_0
ADC_0
SIUL
I/O
I/O
O
192
21
PE[7]
PE[8]
PCR[71]
PCR[72]
M/S Tristate
M/S Tristate
168
21
A5
G1
MA[0]
O
EIRQ[23]
I
AF0
AF1
AF2
AF3
GPIO[72]
CAN2TX
E0UC[22]
CAN3TX
SIUL
I/O
O
FlexCAN_2
eMIOS_0
FlexCAN_3
I/O
O
AF0
AF1
AF2
AF3
—
GPIO[73]
—
SIUL
—
I/O
—
I/O
—
I
E0UC[23]
—
eMIOS_0
—
22
PE[9]
PCR[73]
S
Tristate
22
H1
WKPU[7]
CAN2RX
CAN3RX
WKPU
FlexCAN_2
FlexCAN_3
—
I
—
I
AF0
AF1
AF2
AF3
—
GPIO[74]
LIN3TX
SIUL
LINFlexD_3
DSPI_1
eMIOS_1
SIUL
I/O
O
23
25
PE[10] PCR[74]
CS3_1
O
S
S
Tristate
Tristate
23
25
G3
H3
E1UC[30]
EIRQ[10]
I/O
I
AF0
AF1
AF2
AF3
—
GPIO[75]
E0UC[24]
CS4_1
SIUL
eMIOS_0
DSPI_1
—
I/O
I/O
O
—
I
PE[11] PCR[75]
—
LIN3RX
WKPU[14]
LINFlexD_3
WKPU
—
I
30/118
Doc ID 17478 Rev 4
SPC564Bxx - SPC56ECxx
Package pinouts and signal descriptions
Pin number
Table 5.
Functional port pin descriptions (continued)
Port
pin
PCR
Function
AF0
AF1
AF2
AF3
—
GPIO[76]
—
SIUL
—
I/O
—
E1UC[19]
—
eMIOS_1
—
I/O
—
157
151
PE[12] PCR[76]
M/S Tristate
133
127
C14
C16
CRS
FEC
I
I
I
I
—
SIN_2
DSPI_2
SIUL
—
EIRQ[11]
ADC1_S[7]
—
ADC_1
AF0
AF1
AF2
AF3
—
GPIO[77]
SOUT_2
E1UC[20]
—
SIUL
DSPI_2
eMIOS_1
—
I/O
O
PE[13] PCR[77]
I/O M/S Tristate
—
I
RXD[3]
FEC
AF0
AF1
AF2
AF3
—
GPIO[78]
SCK_2
E1UC[21]
—
SIUL
DSPI_2
eMIOS_1
—
I/O
I/O
160
161
79
PE[14] PCR[78]
PE[15] PCR[79]
I/O M/S Tristate
136
137
63
A14
C12
P7
—
I
EIRQ[12]
SIUL
AF0
AF1
AF2
AF3
GPIO[79]
CS0_2
SIUL
I/O
DSPI_2
eMIOS_1
DSPI_6
I/O
M/S Tristate
I/O
E1UC[22]
SCK_6
I/O
AF0
AF1
AF2
AF3
—
GPIO[80]
E0UC[10]
CS3_1
SIUL
eMIOS_0
DSPI_1
—
I/O
I/O
PF[0]
PF[1]
PF[2]
PCR[80]
PCR[81]
PCR[82]
O
—
I
S
S
S
Tristate
Tristate
Tristate
—
ADC0_S[8]
ADC_0
AF0
AF1
AF2
AF3
—
GPIO[81]
E0UC[11]
CS4_1
SIUL
eMIOS_0
DSPI_1
—
I/O
I/O
O
80
81
64
65
T6
R6
—
—
I
ADC0_S[9]
ADC_0
AF0
AF1
AF2
AF3
—
GPIO[82]
E0UC[12]
CS0_2
SIUL
eMIOS_0
DSPI_2
—
I/O
I/O
I/O
—
I
—
ADC0_S[10]
ADC_0
Doc ID 17478 Rev 4
31/118
Package pinouts and signal descriptions
SPC564Bxx - SPC56ECxx
Pin number
Table 5.
Functional port pin descriptions (continued)
Port
pin
PCR
Function
AF0
AF1
AF2
AF3
—
GPIO[83]
E0UC[13]
CS1_2
SIUL
eMIOS_0
DSPI_2
—
I/O
I/O
O
82
PF[3]
PF[4]
PF[5]
PF[6]
PCR[83]
PCR[84]
PCR[85]
PCR[86]
S
S
S
S
S
Tristate
Tristate
Tristate
Tristate
Tristate
66
67
68
69
R7
R8
P8
N8
—
—
I
ADC0_S[11]
ADC_0
AF0
AF1
AF2
AF3
—
GPIO[84]
E0UC[14]
CS2_2
SIUL
eMIOS_0
DSPI_2
—
I/O
I/O
O
83
84
—
—
I
ADC0_S[12]
ADC_0
AF0
AF1
AF2
AF3
—
GPIO[85]
E0UC[22]
CS3_2
SIUL
eMIOS_0
DSPI_2
—
I/O
I/O
O
—
—
I
ADC0_S[13]
ADC_0
AF0
AF1
AF2
AF3
—
GPIO[86]
E0UC[23]
CS1_1
SIUL
eMIOS_0
DSPI_1
—
I/O
I/O
O
85
86
50
49
—
—
I
ADC0_S[14]
ADC_0
AF0
AF1
AF2
AF3
—
GPIO[87]
—
SIUL
—
I/O
—
O
PF[7]
PF[8]
PCR[87]
PCR[88]
CS2_1
—
DSPI_1
—
70
42
P9
N2
—
I
ADC0_S[15]
ADC_0
AF0
AF1
AF2
AF3
GPIO[88]
CAN3TX
CS4_0
SIUL
I/O
O
FlexCAN_3
DSPI_0
M/S Tristate
O
CAN2TX
FlexCAN_2
O
AF0
AF1
AF2
AF3
—
GPIO[89]
E1UC[1]
CS5_0
SIUL
eMIOS_1
DSPI_0
—
I/O
I/O
O
—
I
PF[9]
PCR[89]
—
S
Tristate
41
46
M4
P2
CAN2RX
CAN3RX
WKPU[22]
FlexCAN_2
FlexCAN_3
WKPU
—
I
—
I
AF0
AF1
AF2
AF3
GPIO[90]
CS1_0
SIUL
I/O
O
DSPI_0
54
PF[10] PCR[90]
M/S Tristate
LIN4TX
E1UC[2]
LINFlexD_4
eMIOS_1
O
I/O
32/118
Doc ID 17478 Rev 4
SPC564Bxx - SPC56ECxx
Package pinouts and signal descriptions
Pin number
Table 5.
Functional port pin descriptions (continued)
Port
pin
PCR
Function
AF0
AF1
AF2
AF3
—
GPIO[91]
CS2_0
SIUL
DSPI_0
eMIOS_1
—
I/O
O
E1UC[3]
—
I/O
—
I
55
51
PF[11] PCR[91]
PF[12] PCR[92]
PF[13] PCR[93]
S
Tristate
47
43
49
R1
P1
P3
LIN4RX
WKPU[15]
LINFlexD_4
WKPU
—
I
AF0
AF1
AF2
AF3
GPIO[92]
E1UC[25]
LIN5TX
—
SIUL
eMIOS_1
LINFlexD_5
—
I/O
I/O
O
M/S Tristate
—
AF0
AF1
AF2
AF3
—
GPIO[93]
E1UC[26]
—
SIUL
eMIOS_1
—
I/O
I/O
—
—
I
57
S
Tristate
—
—
LIN5RX
WKPU[16]
LINFlexD_5
WKPU
—
I
AF0
AF1
AF2
AF3
ALT4
GPIO[94]
CAN4TX
E1UC[27]
CAN1TX
MDIO
SIUL
FlexCAN_4
eMIOS_1
FlexCAN_1
FEC
I/O
O
150
PF[14] PCR[94]
I/O M/S Tristate
126
125
122
D14
D15
E13
O
I/O
AF0
AF1
AF2
AF3
—
GPIO[95]
E1UC[4]
—
SIUL
eMIOS_1
—
I/O
I/O
—
—
—
—
149
146
PF[15] PCR[95]
M/S Tristate
I
RX_DV
CAN1RX
CAN4RX
EIRQ[13]
FEC
—
FlexCAN_1
FlexCAN_4
SIUL
I
I
I
—
—
AF0
AF1
AF2
AF3
ALT4
GPIO[96]
CAN5TX
E1UC[23]
—
SIUL
FlexCAN_5
eMIOS_1
—
I/O
O
PG[0]
PCR[96]
I/O
—
O
F
Tristate
MDC
FEC
Doc ID 17478 Rev 4
33/118
Package pinouts and signal descriptions
SPC564Bxx - SPC56ECxx
Pin number
Table 5.
Functional port pin descriptions (continued)
Port
pin
PCR
Function
AF0
AF1
AF2
AF3
—
GPIO[97]
—
SIUL
—
I/O
—
I/O
—
I
E1UC[24]
—
eMIOS_1
—
PG[1]
PCR[97]
M
Tristate
121
145
E14
TX_CLK
CAN5RX
EIRQ[14]
FEC
—
FlexCAN_5
SIUL
I
—
I
AF0
AF1
AF2
AF3
GPIO[98]
E1UC[11]
SOUT_3
—
SIUL
eMIOS_1
DSPI_3
—
I/O
I/O
O
PG[2]
PG[3]
PCR[98]
PCR[99]
M/S Tristate
16
15
14
16
15
14
E4
E1
F2
—
AF0
AF1
AF2
AF3
—
GPIO[99]
E1UC[12]
CS0_3
SIUL
eMIOS_1
DSPI_3
—
I/O
I/O
I/O
—
I
S
Tristate
—
WKPU[17]
WKPU
AF0
AF1
AF2
AF3
GPIO[100]
E1UC[13]
SCK_3
—
SIUL
eMIOS_1
DSPI_3
—
I/O
I/O
I/O
—
PG[4] PCR[100]
PG[5] PCR[101]
PG[6] PCR[102]
PG[7] PCR[103]
M/S Tristate
AF0
AF1
AF2
AF3
—
GPIO[101]
E1UC[14]
—
SIUL
eMIOS_1
—
I/O
I/O
—
—
I
S
Tristate
13
38
37
13
38
37
D1
M1
L2
—
—
WKPU[18]
SIN_3
WKPU
DSPI_3
—
I
AF0
AF1
AF2
AF3
GPIO[102]
E1UC[15]
LIN6TX
—
SIUL
eMIOS_1
LINFlexD_6
—
I/O
I/O
O
M/S Tristate
—
AF0
AF1
AF2
AF3
—
GPIO[103]
E1UC[16]
E1UC[30]
—
SIUL
eMIOS_1
eMIOS_1
—
I/O
I/O
I/O
—
I
S
Tristate
LIN6RX
WKPU[20]
LINFlexD_6
WKPU
—
I
34/118
Doc ID 17478 Rev 4
SPC564Bxx - SPC56ECxx
Package pinouts and signal descriptions
Pin number
Table 5.
Functional port pin descriptions (continued)
Port
pin
PCR
Function
AF0
AF1
AF2
AF3
—
GPIO[104]
E1UC[17]
LIN7TX
SIUL
eMIOS_1
LINFlexD_7
DSPI_2
SIUL
I/O
I/O
PG[8] PCR[104]
PG[9] PCR[105]
O
I/O
I
S
S
S
Tristate
Tristate
Tristate
34
33
34
33
K3
J4
CS0_2
EIRQ[15]
AF0
AF1
AF2
AF3
—
GPIO[105]
E1UC[18]
—
SIUL
eMIOS_1
—
I/O
I/O
—
I/O
I
SCK_2
DSPI_2
LINFlexD_7
WKPU
LIN7RX
WKPU[21]
—
I
AF0
AF1
AF2
AF3
—
GPIO[106]
E0UC[24]
E1UC[31]
—
SIUL
eMIOS_0
eMIOS_1
—
I/O
I/O
I/O
—
I
PG[10] PCR[106]
PG[11] PCR[107]
PG[12] PCR[108]
138
139
116
162
163
140
B13
A16
F15
SIN_4
DSPI_4
AF0
AF1
AF2
AF3
GPIO[107]
E0UC[25]
CS0_4
SIUL
I/O
I/O
I/O
I/O
eMIOS_0
DSPI_4
DSPI_6
M/S Tristate
M/S Tristate
CS0_6
AF0
AF1
AF2
AF3
ALT4
GPIO[108]
E0UC[26]
SOUT_4
—
SIUL
eMIOS_0
DSPI_4
—
I/O
I/O
O
—
O
TXD[2]
FEC
AF0
AF1
AF2
AF3
ALT4
GPIO[109]
E0UC[27]
SCK_4
—
SIUL
eMIOS_0
DSPI_4
—
I/O
I/O
PG[13] PCR[109]
PG[14] PCR[110]
PG[15] PCR[111]
I/O M/S Tristate
115
134
135
139
158
159
F16
C13
—
O
TXD[3]
FEC
AF0
AF1
AF2
AF3
—
GPIO[110]
E1UC[0]
LIN8TX
—
SIUL
eMIOS_1
LINFlexD_8
—
I/O
I/O
O
—
I
S
Tristate
SIN_6
DSPI_6
AF0
AF1
AF2
AF3
—
GPIO[111]
E1UC[1]
SOUT_6
—
SIUL
eMIOS_1
DSPI_6
—
I/O
I/O
O
M/S Tristate
D13
—
I
LIN8RX
LINFlexD_8
Doc ID 17478 Rev 4
35/118
Package pinouts and signal descriptions
SPC564Bxx - SPC56ECxx
Pin number
Table 5.
Functional port pin descriptions (continued)
Port
pin
PCR
Function
AF0
AF1
AF2
AF3
ALT4
—
GPIO[112]
E1UC[2]
—
SIUL
eMIOS_1
—
I/O
I/O
—
—
O
PH[0] PCR[112]
M/S Tristate
M/S Tristate
117
141
E15
—
—
TXD[1]
SIN_1
FEC
DSPI_1
I
AF0
AF1
AF2
AF3
ALT4
GPIO[113]
E1UC[3]
SOUT_1
—
SIUL
eMIOS_1
DSPI_1
—
I/O
I/O
O
PH[1] PCR[113]
PH[2] PCR[114]
118
119
142
143
F13
D16
—
O
TXD[0]
FEC
AF0
AF1
AF2
AF3
ALT4
GPIO[114]
E1UC[4]
SCK_1
—
SIUL
eMIOS_1
DSPI_1
—
I/O
I/O
I/O M/S Tristate
—
O
TX_EN
FEC
AF0
AF1
AF2
AF3
ALT4
GPIO[115]
E1UC[5]
CS0_1
—
SIUL
eMIOS_1
DSPI_1
—
I/O
I/O
PH[3] PCR[115]
PH[4] PCR[116]
PH[5] PCR[117]
PH[6] PCR[118]
PH[7] PCR[119]
I/O M/S Tristate
120
162
163
164
165
144
186
187
188
189
F14
D7
B7
—
O
TX_ER
FEC
AF0
AF1
AF2
AF3
GPIO[116]
E1UC[6]
SOUT_7
—
SIUL
eMIOS_1
DSPI_7
—
I/O
I/O
M/S Tristate
O
—
AF0
AF1
AF2
AF3
—
GPIO[117]
E1UC[7]
—
SIUL
eMIOS_1
—
I/O
I/O
—
—
I
S
Tristate
—
—
SIN_7
DSPI_7
AF0
AF1
AF2
AF3
GPIO[118]
E1UC[8]
SCK_7
SIUL
eMIOS_1
DSPI_7
ADC_0
I/O
I/O
I/O
O
M/S Tristate
M/S Tristate
C7
C6
MA[2]
AF0
AF1
AF2
AF3
ALT4
GPIO[119]
E1UC[9]
CS3_2
SIUL
eMIOS_1
DSPI_2
ADC_0
DSPI_7
I/O
I/O
O
MA[1]
O
CS0_7
I/O
36/118
Doc ID 17478 Rev 4
SPC564Bxx - SPC56ECxx
Package pinouts and signal descriptions
Pin number
Table 5.
Functional port pin descriptions (continued)
Port
pin
PCR
Function
AF0
AF1
AF2
AF3
GPIO[120]
E1UC[10]
CS2_2
SIUL
eMIOS_1
DSPI_2
ADC_0
I/O
I/O
PH[8] PCR[120]
PH[9](6) PCR[121]
PH[10](6
M/S Tristate
Input,
166
155
190
179
A6
O
O
MA[0]
AF0
AF1
AF2
AF3
—
GPIO[121]
SIUL
—
I/O
—
—
—
I
—
—
—
S
weak
A11
pull-up
—
—
TCK
JTAGC
AF0
AF1
AF2
AF3
—
GPIO[122]
SIUL
—
I/O
—
—
—
I
—
—
Input,
weak
PCR[122]
—
M/S
148
172
D10
)
pull-up
—
—
TMS
JTAGC
AF0
AF1
AF2
AF3
GPIO[123]
SOUT_3
CS0_4
SIUL
I/O
O
DSPI_3
DSPI_4
eMIOS_1
PH[11] PCR[123]
PH[12] PCR[124]
PH[13] PCR[125]
PH[14] PCR[126]
PH[15] PCR[127]
M/S Tristate
M/S Tristate
M/S Tristate
M/S Tristate
M/S Tristate
140
141
9
164
165
9
A13
B12
B1
I/O
I/O
E1UC[5]
AF0
AF1
AF2
AF3
GPIO[124]
SCK_3
SIUL
I/O
I/O
O
DSPI_3
DSPI_4
eMIOS_1
CS1_4
E1UC[25]
I/O
AF0
AF1
AF2
AF3
GPIO[125]
SOUT_4
CS0_3
SIUL
I/O
O
DSPI_4
DSPI_3
eMIOS_1
I/O
I/O
E1UC[26]
AF0
AF1
AF2
AF3
GPIO[126]
SCK_4
SIUL
I/O
I/O
O
DSPI_4
DSPI_3
eMIOS_1
10
8
10
8
C1
CS1_3
E1UC[27]
I/O
AF0
AF1
AF2
AF3
GPIO[127]
SOUT_5
—
SIUL
DSPI_5
—
I/O
O
E3
—
E1UC[17]
eMIOS_1
I/O
AF0
AF1
AF2
AF3
GPIO[128]
E0UC[28]
LIN8TX
—
SIUL
eMIOS_0
LINFlexD_8
—
I/O
I/O
O
PI[0]
PCR[128]
S
Tristate
172
196
C5
—
Doc ID 17478 Rev 4
37/118
Package pinouts and signal descriptions
SPC564Bxx - SPC56ECxx
Pin number
Table 5.
Functional port pin descriptions (continued)
Port
pin
PCR
Function
AF0
AF1
AF2
AF3
—
GPIO[129]
E0UC[29]
—
SIUL
eMIOS_0
—
I/O
I/O
—
—
I
PI[1]
PI[2]
PI[3]
PCR[129]
PCR[130]
PCR[131]
S
S
S
Tristate
Tristate
Tristate
171
170
169
195
194
193
A4
D6
B5
—
—
WKPU[24]
LIN8RX
WKPU
LINFlexD_8
—
I
AF0
AF1
AF2
AF3
GPIO[130]
E0UC[30]
LIN9TX
—
SIUL
eMIOS_0
LINFlexD_9
—
I/O
I/O
O
—
AF0
AF1
AF2
AF3
—
GPIO[131]
E0UC[31]
—
SIUL
eMIOS_0
—
I/O
I/O
—
—
I
—
—
WKPU[23]
LIN9RX
WKPU
LINFlexD_9
—
I
AF0
AF1
AF2
AF3
GPIO[132]
E1UC[28]
SOUT_4
—
SIUL
eMIOS_1
DSPI_4
—
I/O
I/O
O
PI[4]
PI[5]
PCR[132]
PCR[133]
M/S Tristate
143
142
167
166
A12
D12
—
AF0
AF1
AF2
AF3
ALT4
GPIO[133]
E1UC[29]
SCK_4
SIUL
I/O
I/O
eMIOS_1
DSPI_4
DSPI_5
DSPI_6
I/O M/S Tristate
CS2_5
O
O
CS2_6
AF0
AF1
AF2
AF3
ALT4
GPIO[134]
E1UC[30]
CS0_4
SIUL
I/O
I/O
eMIOS_1
DSPI_4
DSPI_5
DSPI_6
PI[6]
PI[7]
PCR[134]
PCR[135]
PCR[136]
I/O
I/O
I/O
S
S
S
Tristate
Tristate
Tristate
11
12
11
12
D2
E2
CS0_5
CS0_6
AF0
AF1
AF2
AF3
ALT4
GPIO[135]
E1UC[31]
CS1_4
SIUL
I/O
I/O
O
eMIOS_1
DSPI_4
DSPI_5
DSPI_6
CS1_5
O
CS1_6
O
AF0
AF1
AF2
AF3
—
GPIO[136]
SIUL
—
I/O
—
—
—
I
—
PI[8]
—
—
—
108
130
J14
—
ADC0_S[16]
ADC_0
38/118
Doc ID 17478 Rev 4
SPC564Bxx - SPC56ECxx
Package pinouts and signal descriptions
Pin number
Table 5.
Functional port pin descriptions (continued)
Port
pin
PCR
Function
AF0
AF1
AF2
AF3
—
GPIO[137]
SIUL
—
I/O
—
—
PI[9]
PCR[137]
—
—
—
—
—
I
S
S
Tristate
Tristate
—
—
131
134
J15
J16
—
ADC0_S[17]
ADC_0
AF0
AF1
AF2
AF3
—
GPIO[138]
SIUL
—
I/O
—
—
—
I
—
PI[10] PCR[138]
PI[11] PCR[139]
—
—
—
—
ADC0_S[18]
ADC_0
AF0
AF1
AF2
AF3
—
GPIO[139]
SIUL
—
I/O
—
—
—
I
—
—
—
S
Tristate
111
135
H16
—
—
ADC0_S[19]
SIN_3
ADC_0
DSPI_3
—
I
AF0
AF1
AF2
AF3
—
GPIO[140]
CS0_3
SIUL
DSPI_3
DSPI_2
—
I/O
I/O
I/O
—
I
PI[12] PCR[140]
PI[13] PCR[141]
CS0_2
S
S
Tristate
Tristate
112
113
136
137
G15
G14
—
ADC0_S[20]
ADC_0
AF0
AF1
AF2
AF3
—
GPIO[141]
CS1_3
SIUL
DSPI_3
DSPI_2
—
I/O
O
O
—
I
CS1_2
—
ADC0_S[21]
ADC_0
AF0
AF1
AF2
AF3
—
GPIO[142]
SIUL
—
I/O
—
—
—
I
—
—
—
PI[14] PCR[142]
PI[15] PCR[143]
S
S
Tristate
Tristate
76
75
92
91
T12
P11
—
—
ADC0_S[22]
SIN_4
ADC_0
DSPI_4
—
I
AF0
AF1
AF2
AF3
—
GPIO[143]
CS0_4
SIUL
DSPI_4
DSPI_2
—
I/O
I/O
O
CS2_2
—
—
I
ADC0_S[23]
ADC_0
Doc ID 17478 Rev 4
39/118
Package pinouts and signal descriptions
SPC564Bxx - SPC56ECxx
Pin number
Table 5.
Functional port pin descriptions (continued)
Port
pin
PCR
Function
AF0
AF1
AF2
AF3
—
GPIO[144]
CS1_4
SIUL
DSPI_4
DSPI_2
—
I/O
O
O
—
I
PJ[0]
PJ[1]
PJ[2]
PCR[144]
CS3_2
S
S
Tristate
Tristate
74
73
72
90
89
88
R11
N10
R10
—
ADC0_S[24]
ADC_0
AF0
AF1
AF2
AF3
—
GPIO[145]
SIUL
—
I/O
—
—
—
I
—
—
—
PCR[145]
PCR[146]
—
——
ADC0_S[25]
SIN_5
ADC_0
DSPI_5
—
I
AF0
AF1
AF2
AF3
—
GPIO[146]
CS0_5
SIUL
I/O
I/O
I/O
I/O
I
DSPI_5
DSPI_6
DSPI_7
ADC_0
CS0_6
S
S
Tristate
Tristate
CS0_7
ADC0_S[26]
AF0
AF1
AF2
AF3
—
GPIO[147]
CS1_5
SIUL
I/O
O
O
O
I
DSPI_5
DSPI_6
DSPI_7
ADC_0
PJ[3]
PJ[4]
PJ[5]
PCR[147]
PCR[148]
PCR[149]
CS1_6
71
5
87
5
P10
D3
CS1_7
ADC0_S[27]
AF0
AF1
AF2
AF3
GPIO[148]
SCK_5
E1UC[18]
—
SIUL
DSPI_5
eMIOS_1
—
I/O
I/O
I/O
—
M/S Tristate
AF0
AF1
AF2
AF3
—
GPIO[149]
SIUL
—
I/O
—
—
—
I
—
—
—
—
S
S
S
Tristate
Tristate
Tristate
—
113
N12
—
ADC0_S[28]
ADC_0
AF0
AF1
AF2
AF3
—
GPIO[150]
SIUL
—
I/O
—
—
—
I
—
PJ[6]
PCR[150]
PCR[151]
—
—
—
—
—
112
111
N15
P16
—
ADC0_S[29]
ADC_0
AF0
AF1
AF2
AF3
—
GPIO[151]
SIUL
—
I/O
—
—
—
I
—
PJ[7]
—
—
—
—
ADC0_S[30]
ADC_0
40/118
Doc ID 17478 Rev 4
SPC564Bxx - SPC56ECxx
Package pinouts and signal descriptions
Pin number
Table 5.
Functional port pin descriptions (continued)
Port
pin
PCR
Function
AF0
AF1
AF2
AF3
—
GPIO[152]
SIUL
—
I/O
—
—
PJ[8]
PJ[9]
PCR[152]
PCR[153]
—
—
—
—
—
I
S
S
S
S
S
Tristate
Tristate
Tristate
Tristate
Tristate
—
—
—
—
—
110
68
67
60
59
P15
P5
T5
—
ADC0_S[31]
ADC_0
AF0
AF1
AF2
AF3
—
GPIO[153]
SIUL
—
I/O
—
—
—
I
—
—
—
—
—
ADC1_S[8]
ADC_1
AF0
AF1
AF2
AF3
—
GPIO[154]
SIUL
—
I/O
—
—
—
I
—
PJ[10] PCR[154]
PJ[11] PCR[155]
PJ[12] PCR[156]
—
—
—
—
ADC1_S[9]
ADC_1
AF0
AF1
AF2
AF3
—
GPIO[155]
SIUL
—
I/O
—
—
—
I
—
—
—
—
R3
T1
—
ADC1_S[10]
ADC_1
AF0
AF1
AF2
AF3
—
GPIO[156]
SIUL
—
I/O
—
—
—
I
—
—
—
—
—
ADC1_S[11]
ADC_1
AF0
AF1
AF2
AF3
—
GPIO[157]
—
SIUL
—
I/O
—
O
—
I
CS1_7
DSPI_7
—
—
PJ[13] PCR[157]
S
Tristate
—
—
65
64
N5
T4
CAN4RX
ADC1_S[12]
CAN1RX
WKPU[31]
FlexCAN_4
ADC_1
FlexCAN_1
WKPU
—
I
—
I
—
I
AF0
AF1
AF2
AF3
GPIO[158]
CAN1TX
CAN4TX
CS2_7
SIUL
I/O
O
FlexCAN_1
FlexCAN_4
DSPI_7
PJ[14] PCR[158]
M/S Tristate
O
O
Doc ID 17478 Rev 4
41/118
Package pinouts and signal descriptions
SPC564Bxx - SPC56ECxx
Pin number
Table 5.
Functional port pin descriptions (continued)
Port
pin
PCR
Function
AF0
AF1
AF2
AF3
—
GPIO[159]
—
SIUL
—
I/O
—
O
PJ[15] PCR[159]
PK[0] PCR[160]
PK[1] PCR[161]
PK[2] PCR[162]
CS1_6
—
DSPI_6
—
M/S Tristate
M/S Tristate
M/S Tristate
M/S Tristate
—
—
—
—
63
62
41
42
R4
T3
H4
L4
—
I
CAN1RX
FlexCAN_1
AF0
AF1
AF2
AF3
GPIO[160]
CAN1TX
CS2_6
—
SIUL
FlexCAN_1
DSPI_6
—
I/O
O
O
—
AF0
AF1
AF2
AF3
—
GPIO[161]
CS3_6
—
SIUL
DSPI_6
—
I/O
O
—
—
I
—
—
CAN4RX
FlexCAN_4
AF0
AF1
AF2
AF3
GPIO[162]
CAN4TX
—
SIUL
I/O
O
FlexCAN_4
—
—
—
—
—
AF0
AF1
AF2
AF3
—
GPIO[163]
E1UC[0]
—
SIUL
eMIOS_1
—
I/O
I/O
—
—
I
PK[3] PCR[163]
PK[4] PCR[164]
PK[5] PCR[165]
PK[6] PCR[166]
M/S Tristate
M/S Tristate
M/S Tristate
M/S Tristate
—
—
—
—
43
44
45
46
N1
M3
M5
M6
—
—
CAN5RX
LIN8RX
FlexCAN_5
LINFlexD_8
—
I
AF0
AF1
AF2
AF3
GPIO[164]
LIN8TX
SIUL
I/O
O
LINFlexD_8
FlexCAN_5
eMIOS_1
CAN5TX
E1UC[1]
O
I/O
AF0
AF1
AF2
AF3
—
GPIO[165]
—
SIUL
I/O
—
—
—
I
—
—
—
—
—
CAN2RX
LIN2RX
FlexCAN_2
LINFlexD_2
—
I
AF0
AF1
AF2
AF3
GPIO[166]
CAN2TX
LIN2TX
—
SIUL
FlexCAN_2
LINFlexD_2
—
I/O
O
O
—
42/118
Doc ID 17478 Rev 4
SPC564Bxx - SPC56ECxx
Package pinouts and signal descriptions
Pin number
Table 5.
Functional port pin descriptions (continued)
Port
pin
PCR
Function
AF0
AF1
AF2
AF3
—
GPIO[167]
—
SIUL
I/O
—
—
—
—
—
PK[7] PCR[167]
M/S Tristate
—
47
M7
—
—
—
CAN3RX
LIN3RX
FlexCAN_3
LINFlexD_3
I
I
—
AF0
AF1
AF2
AF3
GPIO[168]
CAN3TX
LIN3TX
—
SIUL
FlexCAN_3
LINFlexD_3
—
I/O
O
PK[8] PCR[168]
PK[9] PCR[169]
M/S Tristate
M/S Tristate
—
—
48
M8
E8
O
—
AF0
AF1
AF2
AF3
—
GPIO[169]
SIUL
—
I/O
—
—
—
I
—
—
—
197
—
—
SIN_4
DSPI_4
AF0
AF1
AF2
AF3
GPIO[170]
SOUT_4
—
SIUL
DSPI_4
—
I/O
O
PK[10] PCR[170]
PK[11] PCR[171]
PK[12] PCR[172]
M/S Tristate
M/S Tristate
M/S Tristate
—
—
—
198
199
200
E7
F8
—
—
—
—
AF0
AF1
AF2
AF3
GPIO[171]
SCK_4
—
SIUL
DSPI_4
—
I/O
I/O
—
—
—
—
AF0
AF1
AF2
AF3
GPIO[172]
CS0_4
—
SIUL
DSPI_4
—
I/O
I/O
—
G12
—
—
—
AF0
AF1
AF2
AF3
—
GPIO[173]
CS3_6
SIUL
DSPI_6
I/O
O
PK[13] PCR[173]
PK[14] PCR[174]
CS2_7
DSPI_7
O
M/S Tristate
M/S Tristate
—
—
201
202
H12
J12
SCK_1
DSPI_1
I/O
I
CAN3RX
FlexCAN_3
AF0
AF1
AF2
AF3
GPIO[174]
CAN3TX
CS3_7
SIUL
FlexCAN_3
DSPI_7
I/O
O
O
CS0_1
DSPI_1
I/O
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Package pinouts and signal descriptions
SPC564Bxx - SPC56ECxx
Pin number
Table 5.
Functional port pin descriptions (continued)
Port
pin
PCR
Function
AF0
AF1
AF2
AF3
—
GPIO[175]
—
SIUL
—
I/O
—
—
—
I
—
—
PK[15] PCR[175]
M/S Tristate
—
203
D5
—
—
SIN_1
SIN_7
DSPI_1
DSPI_7
—
I
AF0
AF1
AF2
AF3
GPIO[176]
SOUT_1
SOUT_7
—
SIUL
DSPI_1
DSPI_7
—
I/O
O
PL[0]
PL[1]
PL[2]
PL[3]
PL[4]
PL[5]
PL[6]
PL[7]
PCR[176]
PCR[177]
M/S Tristate
M/S Tristate
M/S Tristate
M/S Tristate
M/S Tristate
M/S Tristate
M/S Tristate
M/S Tristate
—
—
—
—
—
—
—
—
204
—
—
—
—
—
—
—
C4
F7
F5
G5
H5
J5
O
—
AF0
AF1
AF2
AF3
GPIO[177]
SIUL
—
I/O
—
—
—
—
—
—
—
—
AF0
AF1
AF2
AF3
GPIO[178]
—
MDO0(8)
SIUL
—
I/O
—
O
PCR[178]
(7)
Nexus
—
—
—
AF0
AF1
AF2
AF3
GPIO[179]
—
SIUL
—
I/O
—
O
PCR[179]
PCR[180]
PCR[181]
PCR[182]
PCR[183]
MDO1
—
Nexus
—
—
AF0
AF1
AF2
AF3
GPIO[180]
—
SIUL
—
I/O
—
O
MDO2
—
Nexus
—
—
AF0
AF1
AF2
AF3
GPIO[181]
—
SIUL
—
I/O
—
O
MDO3
—
Nexus
—
—
AF0
AF1
AF2
AF3
GPIO[182]
—
SIUL
—
I/O
—
O
K5
L5
MDO4
—
Nexus
—
—
AF0
AF1
AF2
AF3
GPIO[183]
—
SIUL
—
I/O
—
O
MDO5
—
Nexus
—
—
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Package pinouts and signal descriptions
Pin number
Table 5.
Functional port pin descriptions (continued)
Port
pin
PCR
Function
AF0
AF1
AF2
AF3
—
GPIO[184]
SIUL
—
I/O
—
—
—
PL[8]
PL[9]
PCR[184]
PCR[185]
—
—
—
I
S
Pull-up
—
—
M9
—
—
EVTI
Nexus
AF0
AF1
AF2
AF3
GPIO[185]
—
SIUL
—
I/O
—
O
M/S Tristate
F/S Tristate
M/S Tristate
M/S Tristate
M/S Tristate
M/S Tristate
M/S Tristate
M/S Tristate
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
M10
M11
M12
F11
F10
E12
E11
E10
MSEO0
—
Nexus
—
—
AF0
AF1
AF2
AF3
GPIO[186]
—
SIUL
—
I/O
—
O
PL[10] PCR[186]
PL[11] PCR[187]
PL[12] PCR[188]
PL[13] PCR[189]
PL[14] PCR[190]
PL[15] PCR[191]
PM[0] PCR[192]
MCKO
—
Nexus
—
—
AF0
AF1
AF2
AF3
GPIO[187]
—
SIUL
—
I/O
—
O
MSEO1
—
Nexus
—
—
AF0
AF1
AF2
AF3
GPIO[188]
SIUL
—
I/O
—
O
—
EVTO
—
Nexus
—
—
AF0
AF1
AF2
AF3
GPIO[189]
—
SIUL
—
I/O
—
O
MDO6
—
Nexus
—
—
AF0
AF1
AF2
AF3
GPIO[190]
—
SIUL
—
I/O
—
O
MDO7
—
Nexus
—
—
AF0
AF1
AF2
AF3
GPIO[191]
—
SIUL
—
I/O
—
O
MDO8
—
Nexus
—
—
AF0
AF1
AF2
AF3
GPIO[192]
—
SIUL
—
I/O
—
O
MDO9
—
Nexus
—
—
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Package pinouts and signal descriptions
SPC564Bxx - SPC56ECxx
Pin number
Table 5.
Functional port pin descriptions (continued)
Port
pin
PCR
Function
AF0
AF1
AF2
AF3
GPIO[193]
—
SIUL
—
I/O
—
O
PM[1] PCR[193]
PM[2] PCR[194]
PM[3] PCR[195]
PM[4] PCR[196]
PM[5] PCR[197]
PM[6] PCR[198]
M/S Tristate
M/S Tristate
M/S Tristate
M/S Tristate
M/S Tristate
M/S Tristate
—
—
—
—
—
—
—
—
—
—
—
—
E9
F12
K12
L12
F9
MDO10
—
Nexus
—
—
AF0
AF1
AF2
AF3
GPIO[194]
—
SIUL
—
I/O
—
O
MDO11
—
Nexus
—
—
AF0
AF1
AF2
AF3
GPIO[195]
SIUL
—
I/O
—
—
—
—
—
—
—
—
AF0
AF1
AF2
AF3
GPIO[196]
SIUL
—
I/O
—
—
—
—
—
—
—
—
AF0
AF1
AF2
AF3
GPIO[197]
SIUL
—
I/O
—
—
—
—
—
—
—
—
AF0
AF1
AF2
AF3
GPIO[198]
SIUL
—
I/O
—
—
—
—
—
—
F6
—
—
1. Alternate functions are chosen by setting the values of the PCR.PA bitfields inside the SIUL module. PCR.PA =
000 → AF0; PCR.PA = 001 → AF1; PCR.PA = 010 → AF2; PCR.PA = 011 → AF3; PCR.PA = 100 → ALT4. This is
intended to select the output functions; to use one of the input functions, the PCR.IBE bit must be written to ‘1’, regardless
of the values selected in the PCR.PA bitfields. For this reason, the value corresponding to an input only function is reported
as “—”.
2. Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by setting the
values of the PSMIO.PADSELx bitfields inside the SIUL module.
3. NMI[0] and NMI[1] have a higher priority than alternate functions. When NMI is selected, the PCR.PA field is ignored.
4. SXOSC’s OSC32k_XTAL and OSC32k_EXTAL pins are shared with GPIO functionality. When used as crystal pins, other
functionality of the pin cannot be used and it should be ensured that application never programs OBE and PUE bit of the
corresponding PCR to "1".
5. If you want to use OSC32K functionality through PB[8] and PB[9], you must ensure that PB[10] is static in nature as PB[10]
can induce coupling on PB[9] and disturb oscillator frequency.
6. Out of reset all the functional pins except PC[0:1] and PH[9:10] are available to the user as GPIO.
PC[0:1] are available as JTAG pins (TDI and TDO respectively).
PH[9:10] are available as JTAG pins (TCK and TMS respectively).
It is up to the user to configure these pins as GPIO when needed.
7. When MBIST is enabled to run ( STCU Enable = 1), the application must not drive or tie PAD[178) (MDO[0]) to 0 V before
the device exits reset (external reset is removed) as the pad is internally driven to 1 to indicate MBIST operation. When
MBIST is not enabled (STCU Enable = 0), there are no restriction as the device does not internally drive the pad.
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Package pinouts and signal descriptions
8. These pins can be configured as Nexus pins during reset by the debugger writing to the Nexus Development Interface
"Port Control Register" rather than the SIUL. Specifically, the debugger can enable the MDO[7:0], MSEO[1:0], and MCKO
ports by programming NDI (PCR[MCKO_EN] or PCR[PSTAT_EN]). MDO[8:11] ports can be enabled by programming NDI
((PCR[MCKO_EN] and PCR[FPM]) or PCR[PSTAT_EN]).
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Electrical Characteristics
SPC564Bxx - SPC56ECxx
4
Electrical Characteristics
This section contains electrical characteristics of the device as well as temperature and
power considerations.
This product contains devices to protect the inputs against damage due to high static
voltages. However, it is advisable to take precautions to avoid application of any voltage
higher than the specified maximum rated voltages.
To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (V
DD
or V
). This could be done by the internal pull-up and pull-down, which is provided by
SS_HV
the product for most general purpose pins.
The parameters listed in the following tables represent the characteristics of the device and
its demands on the system.
In the tables where the device logic provides signals with their respective timing
characteristics, the symbol “CC” for Controller Characteristics is included in the Symbol
column.
In the tables where the external system must provide signals with their respective timing
characteristics to the device, the symbol “SR” for System Requirement is included in the
Symbol column.
4.1
Parameter classification
The electrical parameters shown in this supplement are guaranteed by various methods. To
give the customer a better understanding, the classifications listed in Table 6 are used and
the parameters are tagged accordingly in the tables where appropriate.
Table 6.
Parameter classifications
Classification tag
Tag description
P
Those parameters are guaranteed during production testing on each individual device.
Those parameters are achieved by the design characterization by measuring a statistically
relevant sample size across process variations.
C
Those parameters are achieved by design characterization on a small sample size from typical
devices under typical conditions unless otherwise noted. All values shown in the typical
column are within this category.
T
D
Those parameters are derived mainly from simulations.
Note:
The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
4.2
NVUSRO register
Portions of the device configuration, such as high voltage supply is controlled via bit values
in the Non-Volatile User Options Register (NVUSRO). For a detailed description of the
NVUSRO register, see SPC564Bxx and SPC56ECxx Reference Manual.
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Electrical Characteristics
4.2.1
NVUSRO [PAD3V5V(0)] field description
Table 7 shows how NVUSRO [PAD3V5V(0)] controls the device configuration for V
DD_HV_A
domain.
Table 7.
PAD3V5V(0) field description
Value(1)
Description
0
1
High voltage supply is 5.0 V
High voltage supply is 3.3 V
1. '1' is delivery value. It is part of shadow flash memory, thus programmable by customer.
The DC electrical characteristics are dependent on the PAD3V5V(0,1) bit value.
NVUSRO [PAD3V5V(1)] field description
4.2.2
Table 8 shows how NVUSRO [PAD3V5V(1)] controls the device configuration the device
configuration for V domain.
DD_HV_B
Table 8.
PAD3V5V(1) field description
Value(1)
Description
0
1
High voltage supply is 5.0 V
High voltage supply is 3.3 V
1. '1' is delivery value. It is part of shadow flash memory, thus programmable by customer.
The DC electrical characteristics are dependent on the PAD3V5V(0,1) bit value.
4.3
Absolute maximum ratings
Table 9.
Absolute maximum ratings
Value
Symbol
Parameter
Conditions
Unit
Min
Max
Digital ground on VSS_HV
pins
VSS_HV
SR
—
—
0
0
V
V
Voltage on VDD_HV_A pins
VDD_HV_A
SR with respect to ground
(VSS_HV
–0.3
–0.3
6.0
6.0
)
Voltage on VDD_HV_B pins
SR with respect to common
(1)
VDD_HV_B
—
—
V
V
ground (VSS_HV
)
Voltage on VSS_LV (low
voltage digital supply) pins
with respect to ground
VSS_LV
SR
VSS_HV − 0.1
VSS_HV + 0.1
(VSS_HV
)
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Electrical Characteristics
SPC564Bxx - SPC56ECxx
Table 9.
Symbol
Absolute maximum ratings (continued)
Value
Unit
Parameter
Conditions
Min
Max
Base control voltage for
external BCP68 NPN device
(2)
VRC_CTRL
Relative to VDD_LV
0
VDD_LV + 1
V
V
Voltage on VSS_HV_ADC0,
VSS_HV_ADC1 (ADC
reference) pin with respect to
VSS_ADC
SR
—
—
VSS_HV − 0.1
VSS_HV + 0.1
ground (VSS_HV
)
Voltage on VDD_HV_ADC0
–0.3
6.0
VDD_HV_ADC0 SR with respect to ground
(VSS_HV
V
(3)
Relative to VDD_HV_A
VDD_HV_A − 0.3 VDD_HV_A+0.3
)
Voltage on VDD_HV_ADC1
SR with respect to ground
—
–0.3
6.0
VDD_HV_ADC1
V
V
(4)
(2)
Relative to VDD_HV_A
VDD_HV_A−0.3
VDD_HV_A+0.3
(VSS_HV
)
Voltage on any GPIO pin with Relative to
VDD_HV_A/HV_B VDD_HV_A/HV_B
VIN
SR
SR
respect to ground (VSS_HV
)
VDD_HV_A/HV_B
−0.3
+0.3
Injected input current on any
pin during overload condition
IINJPAD
—
–10
10
mA
Absolute sum of all injected
IINJSUM
SR input currents during overload
condition
—
–50
50
70
VDD = 5.0 V 10ꢀ,
PAD3V5V = 0
Sum of all the static I/O
current within a supply
segment
(5)
IAVGSEG
SR
mA
°C
VDD = 3.3 V 10ꢀ,
PAD3V5V = 1
64
(VDD_HV_A or VDD_HV_B
)
TSTORAGE
SR Storage temperature
—
–55(6)
150
1. VDD_HV_B can be independently controlled from VDD_HV_A. These can ramp up or ramp down in any order. Design is robust
against any supply order.
2. This voltage is internally generated by the device and no external voltage should be supplied.
3. Both the relative and the fixed conditions must be met. For instance: If VDD_HV_A is 5.9 V, VDD_HV_ADC0 maximum value is
6.0 V then, despite the relative condition, the max value is VDD_HV_A + 0.3 = 6.2 V.
4. PA3, PA7, PA10, PA11 and PE12 ADC_1 channels are coming from VDD_HV_B domain hence VDD_HV_ADC1 should be
within 300 mV of VDD_HV_B when these channels are used for ADC_1.
5. Any temperature beyond 125 °C should limit the current to 50 mA (max).
6. This is the storage temperature for the flash memory.
Note:
Stresses exceeding the recommended absolute maximum ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification are not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability. During overload conditions (V > V
or
IN
DD_HV_A/HV_B
V
< V
), the voltage on pins with respect to ground (V
) must not exceed the
IN
SS_HV
SS_HV
recommended values.
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Electrical Characteristics
4.4
Recommended operating conditions
Table 10. Recommended operating conditions (3.3 V)
Value
Symbol
Parameter
Conditions
Unit
Min
Max
VSS_HV
SR Digital ground on VSS_HV pins
—
—
0
0
V
V
Voltage on VDD_HV_A pins with
SR
(1)
(1)
VDD_HV_A
3.0
3.0
3.6
respect to ground (VSS_HV
)
Voltage on VDD_HV_B pins with
VDD_HV_B
SR
—
—
3.6
V
V
V
respect to ground (VSS_HV
)
Voltage on VSS_LV (low
SR voltage digital supply) pins with
(2)
VSS_LV
VSS_HV − 0.1
VSS_HV + 0.1
respect to ground (VSS_HV
)
Base control voltage for
external BCP68 NPN device
(3)
VRC_CTRL
Relative to VDD_LV
0
VDD_LV + 1
Voltage on VSS_HV_ADC0,
VSS_HV_ADC1 (ADC
reference) pin with respect to
VSS_ADC
SR
—
VSS_HV − 0.1
VSS_HV + 0.1
V
ground (VSS_HV
)
—
3.0(5)
VDD_HV_A − 0.1
3.0
3.6
VDD_HV_A + 0.1
3.6
Voltage on VDD_HV_ADC0
SR with respect to ground
(VSS_HV
VDD_HV_ADC0
V
V
V
(4)
Relative to
VDD_HV_A
(6)
)
—
Voltage on VDD_HV_ADC1
SR with respect to ground
VDD_HV_ADC1
(7)
Relative to
VDD_HV_A
VDD_HV_A − 0.1
VSS_HV − 0.1
—
VDD_HV_A + 0.1
(6)
(VSS_HV
)
—
—
VDD_HV_A/HV_B
Voltage on any GPIO pin with
VIN
SR
SR
Relative to
VDD_HV_A/HV_B
respect to ground (VSS_HV
)
+ 0.1
Injected input current on any
pin during overload condition
IINJPAD
—
—
−5
5
mA
Absolute sum of all injected
SR input currents during overload
condition
IINJSUM
−50
50
—
—
—
0.5
—
V/µs
V
DD_HV_A slope to ensure
TVDD
SR
correct power up(8)
0.5
V/min
Ambient temperature under
bias
fCPU up to
120 MHz + 2ꢀ
TA
TJ
SR
SR
–40
125
150
°C
Junction temperature under
bias
—
−40
1. 100 nF EMI capacitance and 10 µF bulk capacitance need to be provided between each VDD/VSS_HV pair.
2. 100 nF EMI capacitance and 10 µF bulk capacitance need to be provided between each of the four VDD_LV/VSS_LV supply
pairs. For details refer to the Power Management chapter of the SPC564Bxx and SPC56ECxx Reference Manual.
3. This voltage is internally generated by the device and no external voltage should be supplied.
4. 100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair.
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Electrical Characteristics
SPC564Bxx - SPC56ECxx
5. Full electrical specification cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical
characteristics and I/Os DC electrical specification may not be guaranteed. When voltage drops below VLVDHVL, device is
reset.
6. Both the relative and the fixed conditions must be met. For instance: If VDD_HV_A is 5.9 V, VDD_HV_ADC0 maximum value is
6.0 V then, despite the relative condition, the max value is VDD_HV_A + 0.3 = 6.2 V.
7. PA3, PA7, PA10, PA11 and PE12 ADC_1 channels are coming from VDD_HV_B domain hence VDD_HV_ADC1 should be
within 100 mV of VDD_HV_B when these channels are used for ADC_1.
8. Guaranteed by the device validation.
Table 11.
Recommended operating conditions (5.0 V)
Value
Symbol
Parameter
Conditions
Unit
Min
Max
VSS_HV
SR Digital ground on VSS_HV pins
—
0
0
V
V
V
—
Voltage drop(2)
—
4.5
3.0
3.0
5.5
5.5
5.5
Voltage on VDD_HV_A pins with
SR
(1)
VDD_HV_A
respect to ground (VSS_HV
)
Generic GPIO functionality
Ethernet/3.3 V functionality
(See the notes in all figures in
Section 3: Package pinouts and
signal descriptions” for the list of
channels operating in VDD_HV_B
domain)
VDD_HV_B
SR
—
3.0
3.6
V
Voltage on VSS_LV (Low voltage
(3)
VSS_LV
SR digital supply) pins with respect to
ground (VSS_HV
—
VSS_HV – 0.1
VSS_HV + 0.1
V
V
)
Base control voltage for external
BCP68 NPN device
Relative to
VDD_LV
(4)
VRC_CTRL
0
VDD_LV + 1
Voltage on VSS_HV_ADC0,
VSS_HV_ADC1 (ADC reference)
pin with respect to ground
VSS_ADC
SR
SR
—
VSS_HV – 0.1
VSS_HV + 0.1
V
V
(VSS_HV
)
—
4.5
3.0
5.5
5.5
VDD_HV_ADC0
Voltage on VDD_HV_ADC0 with Voltage drop(2)
respect to ground (VSS_HV
(5)
)
Relative to
VDD_HV_A
VDD_HV_A – 0.1 VDD_HV_A + 0.1
(6)
—
4.5
3.0
5.5
5.5
Voltage on VDD_HV_ADC1 with
respect to ground (VSS_HV
VDD_HV_ADC1
Voltage drop(2)
Relative to
)
SR
SR
V
V
(7)
VDD_HV_A − 0.1 VDD_HV_A + 0.1
(6)
VDD_HV_A
—
V
SS_HV –0.1
—
Voltage on any GPIO pin with
respect to ground (VSS_HV
VIN
Relative to
VDD_HV_A/HV_B
VDD_HV_A/HV_B
+ 0.1
)
—
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Electrical Characteristics
Table 11.
Recommended operating conditions (5.0 V) (continued)
Value
Symbol
Parameter
Conditions
Unit
Min
Max
Injected input current on any pin
during overload condition
IINJPAD
IINJSUM
SR
SR
—
—
–5
5
mA
Absolute sum of all injected input
currents during overload condition
–50
50
—
—
—
—
—
—
—
—
—
0.5
—
V/µs
V
DD_HV_A slope to ensure correct
TVDD
SR
power up(8)
0.5
V/min
TA C-Grade Part SR Ambient temperature under bias
TJ C-Grade Part SR Junction temperature under bias
TA V-Grade Part SR Ambient temperature under bias
TJ V-Grade Part SR Junction temperature under bias
TA M-Grade Part SR Ambient temperature under bias
TJ M-Grade Part SR Junction temperature under bias
−40
−40
−40
−40
−40
−40
85
110
105
130
125
150
°C
1. 100 nF EMI capacitance and 10 µF bulk capacitance needs to be provided between each VDD_HV_A/HV_B/VSS_HV pair.
2. Full device operation is guaranteed by design from 3.0 V–5.5 V. OSC electrical characteristics (startup time, IDD, negative
resistance, ESR and duty cycle) will not be guaranteed to stay within the stated limits when operating below 4.5 V and
above 3.6 V. However, OSC functionality is guaranteed within the entire range (3.0 V–5.5 V).
3. 100 nF EMI capacitance and 40 µF bulk capacitance needs to be provided between each VDD_LV/VSS_LV supply pair.
4. This voltage is internally generated by the device and no external voltage should be supplied.
5. 100 nF capacitance needs to be provided between VDD_HV_(ADC0/ADC1)/VSS_HV_(ADC0/ADC1) pair.
6. Both the relative and the fixed conditions must be met. For instance: If VDD_HV_A is 5.9 V, VDD_HV_ADC0 maximum value is
6.0 V then, despite the relative condition, the max value is VDD_HV_A + 0.3 = 6.2 V.
7. PA3, PA7, PA10, PA11 and PE12 ADC_1 channels are coming from VDD_HV_B domain hence VDD_HV_ADC1 should be
within 100 mV of VDD_HV_B when these channels are used for ADC_1.
8. Guaranteed by device validation.
Note:
SRAM retention guaranteed to LVD levels.
4.5
Thermal characteristics
4.5.1
Package thermal characteristics
(1)
Table 12. LQFP thermal characteristics
Value(3)
Pin
count
Symbol
C
Parameter
Conditions(2)
Unit
Min
—
Typ
—
Max
Thermal resistance,
junction-to-ambient
natural convection
176
208
176
208
44.4(4) °C/W
Single-layer
board—1s
RθJA
CC
CC
D
D
—
—
TBD
36.1
TBD
°C/W
°C/W
°C/W
Thermal resistance,
junction-to-ambient
natural convection
—
—
Four-layer
RθJA
board—2s2p(5)
—
—
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Electrical Characteristics
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1. Thermal characteristics are targets based on simulation that are subject to change per device characterization.
2. VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C.
3. All values need to be confirmed during device validation.
4. 1s board as per standard Jedec (JESD51-7) in natural convection
5. 2s2p board as per standard JEDEC (JESD51-7) in natural convection.
(1)
Table 13. LBGA256 thermal characteristics
Symbol
C
Parameter
Conditions
Value
Unit
Single-layer board—1s
Four-layer board—2s2p
TBD
TBD
Thermal resistance, junction-to-ambient
natural convection
RθJA CC
—
°C/W
1. Thermal characteristics are targets based on simulation that are subject to change per device characterization.
4.5.2
Power considerations
The average chip-junction temperature, T , in degrees Celsius, may be calculated using
J
Equation 1:
Equation 1 T = T + (P
×
R
)
θJA
J
A
D
Where:
T is the ambient temperature in °C.
A
R
is the package junction-to-ambient thermal resistance, in °C/W.
θJA
P is the sum of P
and P (P = P
+ P ).
INT I/O
D
INT
I/O
D
P
is the product of I and V , expressed in watts. This is the chip internal
DD DD
INT
power.
P
represents the power dissipation on input and output pins; user determined.
I/O
Most of the time for the applications, P < P
and may be neglected. On the other hand,
INT
I/O
P
may be significant, if the device is configured to continuously drive external modules
I/O
and/or memories.
An approximate relationship between P and T (if P is neglected) is given by:
D
J
I/O
Equation 2 P = K / (T + 273 °C)
D
J
Therefore, solving equations Equation 1 and Equation 2:
2
Equation 3 K = P
×
(T + 273 °C) + R
× P
D
A
θJA D
Where:
K is a constant for the particular part, which may be determined from Equation 3
by measuring P (at equilibrium) for a known T Using this value of K, the values
D
A.
of P and T may be obtained by solving equations Equation 1 and Equation 2
D
J
iteratively for any value of T .
A
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Electrical Characteristics
4.6
I/O pad electrical characteristics
4.6.1
I/O pad types
The device provides four main I/O pad types depending on the associated alternate
functions:
●
●
●
●
●
Slow pads—These pads are the most common pads, providing a good compromise
between transition time and low electromagnetic emission.
Medium pads—These pads provide transition fast enough for the serial communication
channels with controlled current to reduce electromagnetic emission.
Fast pads—These pads provide maximum speed. These are used for improved Nexus
debugging capability.
Input only pads—These pads are associated to ADC channels and 32 kHz low power
external crystal oscillator providing low input leakage.
Low power pads—These pads are active in standby mode for wakeup source.
Also, medium/slow and fast/medium pads are available in design which can be configured to
behave like a slow/medium and medium/fast pads depending upon the slew-rate control.
Medium and fast pads can use slow configuration to reduce electromagnetic emission, at
the cost of reducing AC performance.
4.6.2
I/O input DC characteristics
Table 14 provides input DC electrical characteristics as described in Figure 5.
Figure 5.
I/O input DC electrical characteristics definition
V
IN
V
DD
V
IH
V
HYS
V
IL
PDIx = ‘1
(GPDI register of SIUL)
PDIx = ‘0’
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Electrical Characteristics
SPC564Bxx - SPC56ECxx
Table 14. I/O input DC electrical characteristics
Value(2)
Symbol
C
Parameter
Conditions(1)
Unit
Min
Typ
Max
Input high level CMOS (Schmitt
Trigger)
VIH SR P
VIL SR P
—
—
—
0.65VDD
—
VDD + 0.4
Input low level CMOS (Schmitt
Trigger)
−0.3
—
—
0.35VDD
—
V
Input hysteresis CMOS (Schmitt
Trigger)
VHYS CC C
P
0.1VDD
TA = −40 °C
—
—
—
—
2
2
—
—
No injection
on adjacent
pin
P
ILKG CC
D
TA = 25 °C
TA = 105 °C
TA = 125 °C
Digital input leakage
nA
12
70
500
1000
P
Width of input pulse rejected by
analog filter(3)
WFI SR P
—
—
—
—
40(4)
ns
ns
Width of input pulse accepted by
analog filter(3)
WNFI SR P
—
1000(4)
—
1. VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified.
2. VDD as mentioned in the table is VDD_HV_A/VDD_HV_B. All values need to be confirmed during device validation.
3. Analog filters are available on all wakeup lines.
4. The width of input pulse in between 40 ns to 1000 ns is indeterminate. It may pass the noise or may not depending on
silicon sample to sample variation.
4.6.3
I/O output DC characteristics
The following tables provide DC characteristics for bidirectional pads:
●
●
●
●
Table 15 provides weak pull figures. Both pull-up and pull-down resistances are
supported.
Table 16 provides output driver characteristics for I/O pads when in SLOW
configuration.
Table 17 provides output driver characteristics for I/O pads when in MEDIUM
configuration.
Table 18 provides output driver characteristics for I/O pads when in FAST configuration.
Table 15. I/O pull-up/pull-down DC electrical characteristics
Value
Symbol
C
Parameter
Conditions(1),(2)
Unit
Min
Typ
Max
P
C
PAD3V5V = 0
10
—
150
VIN = VIL, VDD
5.0 V 10ꢀ
=
=
Weak pull-up
current absolute
value
PAD3V5V =
1(3)
10
10
—
—
250
150
|IWPU
|
CC
µA
VIN = VIL, VDD
3.3 V 10ꢀ
P
PAD3V5V = 1
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Electrical Characteristics
Table 15. I/O pull-up/pull-down DC electrical characteristics (continued)
Value
Typ
Symbol
C
Parameter
Conditions(1),(2)
Unit
Min
Max
P
C
PAD3V5V = 0
10
10
—
—
150
250
VIN = VIH, VDD
5.0 V 10ꢀ
=
=
Weak pull-down
current absolute
value
PAD3V5V = 1
PAD3V5V = 1
|IWPD
|
CC
µA
VIN = VIH, VDD
3.3 V 10ꢀ
P
10
—
150
1. VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified.
2. VDD as mentioned in the table is VDD_HV_A/VDD_HV_B
.
3. The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and
Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
Table 16. SLOW configuration output buffer electrical characteristics
Value
Symbol
C
Parameter
Conditions(1),(2)
Unit
Min
Typ
Max
IOH = −3 mA,
VDD = 5.0 V 10ꢀ, PAD3V5V = 0
P
0.8VDD
—
—
Output high level
IOH = −3 mA,
VOH CC C SLOW
configuration
Push Pull VDD = 5.0 V 10ꢀ, PAD3V5V =
0.8VDD
—
—
V
1(3)
IOH = −1.5 mA,
P
P
VDD − 0.8
—
—
—
VDD = 3.3 V 10ꢀ, PAD3V5V = 1
IOL = 3 mA,
VDD = 5.0 V 10ꢀ, PAD3V5V = 0
—
0.1VDD
Output low level
VOL CC C SLOW
configuration
IOL = 3 mA,
Push Pull VDD = 5.0 V 10ꢀ, PAD3V5V =
—
—
—
—
0.1VDD
0.5
V
1(3)
IOL = 1.5 mA,
P
VDD = 3.3 V 10ꢀ, PAD3V5V = 1
1. VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified.
2. VDD as mentioned in the table is VDD_HV_A/VDD_HV_B
.
3. The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and
Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
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Electrical Characteristics
SPC564Bxx - SPC56ECxx
Table 17. MEDIUM configuration output buffer electrical characteristics
Value
Typ
Symbol
C
Parameter
Conditions(1) (2)
,
Unit
Min
Max
IOH = −3 mA,
VDD = 5.0 V 10ꢀ,
PAD3V5V = 0
C
C
C
C
C
C
0.8VDD
—
—
—
—
—
—
—
Output high level
MEDIUM
configuration
IOH = −1.5 mA,
VOH CC
Push Pull VDD = 5.0 V 10ꢀ,
0.8VDD
—
—
PAD3V5V = 1(3)
V
I
OH = −2 mA,
VDD = 3.3 V 10ꢀ,
PAD3V5V = 1
VDD − 0.8
IOL = 3 mA,
VDD = 5.0 V 10ꢀ,
PAD3V5V = 0
—
—
—
0.2VDD
0.1VDD
0.5
Output low level
MEDIUM
configuration
IOL = 1.5 mA,
VOL CC
Push Pull VDD = 5.0 V 10ꢀ,
PAD3V5V = 1(3)
V
IOL = 2 mA,
VDD = 3.3 V 10ꢀ,
PAD3V5V = 1
1. VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified.
2. VDD as mentioned in the table is VDD_HV_A/VDD_HV_B
.
3. The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and
Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
Table 18. FAST configuration output buffer electrical characteristics
Value
Symbol
C
Parameter
Conditions(1),(2)
Unit
Min
Typ
Max
IOH = −14 mA,
P
C
C
VDD = 5.0 V 10ꢀ,
0.8VDD
—
—
PAD3V5V = 0
Output high
level
FAST
I
OH = −7 mA,
VOH
CC
Push Pull VDD = 5.0 V 10ꢀ,
0.8VDD
—
—
—
—
V
PAD3V5V = 1(3)
configuration
I
OH = −11 mA,
VDD = 3.3 V 10ꢀ, VDD − 0.8
PAD3V5V = 1
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Electrical Characteristics
Table 18. FAST configuration output buffer electrical characteristics (continued)
Value
Symbol
C
Parameter
Conditions(1),(2)
Unit
Min
Typ
Max
IOL = 14 mA,
P
C
C
VDD = 5.0 V 10ꢀ,
PAD3V5V = 0
—
—
0.1VDD
Output low level
FAST
configuration
IOL = 7 mA,
VOL
CC
Push Pull VDD = 5.0 V 10ꢀ,
—
—
—
—
0.1VDD
0.5
V
PAD3V5V = 1(3)
I
OL = 11 mA,
VDD = 3.3 V 10ꢀ,
PAD3V5V = 1
1. VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified.
2. VDD as mentioned in the table is VDD_HV_A/VDD_HV_B
.
3. The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and
Nexus outputs (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
4.6.4
Output pin transition times
Table 19. Output pin transition times
Value(3)
Typ
Symbol
C
Parameter
Conditions(1),(2)
Unit
Min
Max
D
T
CL = 25 pF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
50
100
125
40
50
75
10
20
40
12
25
40
4
VDD = 5.0 V 10ꢀ,
PAD3V5V = 0
CL = 50 pF
CL = 100 pF
CL = 25 pF
CL = 50 pF
CL = 100 pF
CL = 25 pF
CL = 50 pF
CL = 100 pF
CL = 25 pF
CL = 50 pF
CL = 100 pF
CL = 25 pF
CL = 50 pF
CL = 100 pF
CL = 25 pF
CL = 50 pF
CL = 100 pF
Output transition time
output pin(4)
SLOW configuration
D
D
T
Ttr CC
ns
VDD = 3.3 V 10ꢀ,
PAD3V5V = 1
D
D
T
VDD = 5.0 V 10ꢀ,
PAD3V5V = 0
Output transition time
output pin(4)
MEDIUM
SIUL.PCRx.SRC = 1
D
D
T
Ttr CC
ns
VDD = 3.3 V 10ꢀ,
configuration
PAD3V5V = 1
SIUL.PCRx.SRC = 1
D
VDD = 5.0 V 10ꢀ,
6
PAD3V5V = 0
Output transition time
output pin(4)
FAST configuration
12
4
Ttr CC
D
ns
VDD = 3.3 V 10ꢀ,
7
PAD3V5V = 1
12
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Electrical Characteristics
SPC564Bxx - SPC56ECxx
1. VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified.
2. VDD as mentioned in the table is VDD_HV_A/VDD_HV_B
.
3. All values need to be confirmed during device validation.
4. CL includes device and package capacitances (CPKG < 5 pF).
4.6.5
I/O pad current specification
The I/O pads are distributed across the I/O supply segment. Each I/O supply is associated
to a V /V supply pair as described in Table 20.
DD SS_HV
Table 21 provides I/O consumption figures.
In order to ensure device reliability, the average current of the I/O on a single segment
should remain below the I
maximum value.
AVGSEG
In order to ensure device functionality, the sum of the dynamic and static current of the I/O
on a single segment should remain below the I
maximum value.
DYNSEG
Table 20. I/O supplies
Package
I/O Supplies
LBGA256
pin6
Equivalent to 208-pin LQFP segment pad distribution + G6, G11, H11, J11
pin73
pin132
pin147
pin174
pin27
pin101
(VSS_HV
)
(VSS_HV
)
(VSS_HV
)
(VSS_HV)
(VDD_HV_A) (VDD_HV_A
)
(VDD_HV_A
pin102
)
LQFP208
—
—
pin7
pin28
pin75
pin133
pin148
pin175
(VSS_HV
)
(VSS_HV
)
(VSS_HV
)
(VDD_HV_A
)
(VDD_HV_A) (VDD_HV_B) (VDD_HV_A)
pin6
pin27
pin57
pin85
(VDD_HV_A) (VSS_HV
pin86 pin124
pin123
pin150
(VSS_HV
pin151
(VDD_HV_A) (VDD_HV_A
pin7
)
(VSS_HV
pin59
)
)
)
LQFP176
—
pin28
(VDD_HV_A) (VSS_HV
)
(VDD_HV_B) (VDD_HV_A)
(VSS_HV
)
(VSS_HV)
Table 21. I/O consumption
Value(3)
Min Typ Max
Symbol
C
Parameter
Conditions(1),(2)
Unit
V
DD = 5.0 V 10ꢀ,
—
—
—
—
—
—
—
—
—
—
—
—
19.9
15.5
28.8
16.3
113.5
52.1
PAD3V5V = 0
Peak I/O current for
SLOW configuration
(4)
ISWTSLW
CC D
CL = 25 pF
CL = 25 pF
CL = 25 pF
VDD = 3.3 V 10ꢀ,
mA
mA
mA
PAD3V5V = 1
VDD = 5.0 V 10ꢀ,
Peak I/O current for
CC D MEDIUM
configuration
PAD3V5V = 0
(4)
ISWTMED
VDD = 3.3 V 10ꢀ,
PAD3V5V = 1
VDD = 5.0 V 10ꢀ,
PAD3V5V = 0
Peak I/O current for
FAST configuration
(4)
ISWTFST
CC D
VDD = 3.3 V 10ꢀ,
PAD3V5V = 1
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Electrical Characteristics
Table 21. I/O consumption (continued)
Value(3)
Unit
Symbol
C
Parameter
Conditions(1),(2)
Min Typ Max
CL = 25 pF, 2 MHz
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2.22
3.13
6.54
1.51
2.14
4.33
6.5
VDD = 5.0 V 10ꢀ,
PAD3V5V = 0
CL = 25 pF, 4 MHz
CL = 100 pF, 2 MHz
CL = 25 pF, 2 MHz
CL = 25 pF, 4 MHz
CL = 100 pF, 2 MHz
CL = 25 pF, 13 MHz
CL = 25 pF, 40 MHz
CL = 100 pF, 13 MHz
CL = 25 pF, 13 MHz
CL = 25 pF, 40 MHz
CL = 100 pF, 13 MHz
CL = 25 pF, 40 MHz
CL = 25 pF, 64 MHz
CL = 100 pF, 40 MHz
CL = 25 pF, 40 MHz
CL = 25 pF, 64 MHz
CL = 100 pF, 40 MHz
Root mean square
CC D I/O current for SLOW
configuration
IRMSSLW
VDD = 3.3 V 10ꢀ,
PAD3V5V = 1
mA
mA
VDD = 5.0 V 10ꢀ,
PAD3V5V = 0
13.32
18.26
4.91
8.47
10.94
21.05
33
Root mean square
I/O current for
MEDIUM
IRMSMED CC D
configuration
VDD = 3.3 V 10ꢀ,
PAD3V5V = 1
VDD = 5.0 V 10ꢀ,
PAD3V5V = 0
Root mean square
CC D I/O current for FAST
configuration
55.77
14
IRMSFST
mA
mA
VDD = 3.3 V 10ꢀ,
PAD3V5V = 1
20
34.89
70
Sum of all the static VDD = 5.0 V 10ꢀ, PAD3V5V = 0
SR D I/O current within a
supply segment
IAVGSEG
VDD = 3.3 V 10ꢀ, PAD3V5V = 1
—
—
65(4)
1. VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified.
2. VDD as mentioned in the table is VDD_HV_A/VDD_HV_B
.
3. All values need to be confirmed during device validation.
4. Stated maximum values represent peak consumption that lasts only a few ns during I/O transition.
4.7
RESET electrical characteristics
The device implements a dedicated bidirectional RESET pin.
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Electrical Characteristics
SPC564Bxx - SPC56ECxx
Figure 6.
Start-up reset requirements
V
DD_HV_A
V
DDMIN
RESET
V
IH
V
IL
device reset forced by RESET
device start-up phase
Figure 7.
Noise filtering on reset signal
VRESET
hw_rst
‘1’
V
DD
V
IH
V
IL
‘0’
filtered by
lowpass filter
unknown reset
state
filtered by
hysteresis
filtered by
lowpass filter
device under hardware reset
W
W
FRST
FRST
W
NFRST
Table 22. Reset electrical characteristics
Value(2)
Typ
Symbol
C
Parameter
Conditions(1)
Unit
Min
Max
Input High Level CMOS
(Schmitt Trigger)
VIH
VIL
SR P
SR P
—
—
—
0.65VDD
—
—
—
VDD + 0.4
V
V
V
Input low Level CMOS
(Schmitt Trigger)
−0.3
0.35VDD
—
Input hysteresis CMOS
(Schmitt Trigger)
VHYS CC C
0.1VDD
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Electrical Characteristics
Table 22. Reset electrical characteristics (continued)
Value(2)
Symbol
C
Parameter
Conditions(1)
Unit
Min
Typ
Max
Push Pull, IOL = 2 mA,
VDD = 5.0 V 10ꢀ, PAD3V5V = 0
(recommended)
—
—
0.1VDD
Push Pull, IOL = 1 mA,
VOL CC P Output low level
—
—
—
—
0.1VDD
0.5
V
VDD = 5.0 V 10ꢀ, PAD3V5V = 1(3)
Push Pull, IOL = 1 mA,
VDD = 3.3 V 10ꢀ, PAD3V5V = 1
(recommended)
CL = 25 pF,
VDD = 5.0 V 10ꢀ, PAD3V5V = 0
—
—
—
—
—
—
—
—
—
—
10
20
40
12
25
CL = 50 pF,
VDD = 5.0 V 10ꢀ, PAD3V5V = 0
CL = 100 pF,
Output transition time
CC D output pin(4)
MEDIUM configuration
VDD = 5.0 V 10ꢀ, PAD3V5V = 0
Ttr
ns
CL = 25 pF,
VDD = 3.3 V 10ꢀ, PAD3V5V = 1
CL = 50 pF,
VDD = 3.3 V 10ꢀ, PAD3V5V = 1
CL = 100 pF,
VDD = 3.3 V 10ꢀ, PAD3V5V = 1
—
—
—
—
—
40
40
—
WFRST SR P Reset input filtered pulse
—
ns
ns
Reset input not filtered
WNFRST SR P
pulse
—
1000
VDD = 3.3 V 10ꢀ, PAD3V5V = 1
10
10
10
—
—
—
150
150
250
Weak pull-up current
absolute value
|IWPU
|
CC P
VDD = 5.0 V 10ꢀ, PAD3V5V = 0
µA
VDD = 5.0 V 10ꢀ, PAD3V5V = 1(5)
1. VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified.
2. VDD as mentioned in the table is VDD_HV_A/VDD_HV_B. All values need to be confirmed during device validation.
3. This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to the RGM module section of the
device Reference Manual).
4. CL includes device and package capacitance (CPKG < 5 pF).
5. The configuration PAD3V5 = 1 when VDD = 5 V is only transient configuration during power-up. All pads but RESET and
Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
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Electrical Characteristics
SPC564Bxx - SPC56ECxx
4.8
Power management electrical characteristics
4.8.1
Voltage regulator electrical characteristics
The device implements an internal voltage regulator to generate the low voltage core supply
V
from the high voltage supply V
. The following supplies are involved:
DD_LV
DD_HV_A
●
HV: High voltage external power supply for voltage regulator module. This must be
provided externally through V power pin.
DD_HV_A
●
LV: Low voltage internal power supply for core, FMPLL and Flash digital logic. This is
generated by the on-chip VREG with an external ballast (BCP68 NPN device). It is
further split into four main domains to ensure noise isolation between critical LV
modules within the device:
–
–
–
–
LV_COR: Low voltage supply for the core. It is also used to provide supply for
FMPLL through double bonding.
LV_CFLA0/CFLA1: Low voltage supply for the two code Flash modules. It is
shorted with LV_COR through double bonding.
LV_DFLA: Low voltage supply for data Flash module. It is shorted with LV_COR
through double bonding.
LV_PLL: Low voltage supply for FMPLL. It is shorted to LV_COR through double
bonding.
Figure 8.
Voltage regulator capacitance connection
100 nf
100 nf
100 nf
VSS_LV
VDD_LV
VDD_LV
VSS_LV
VSS_LV
VDD_LV
40
(4
μf
PD0 (always on domain)
×
10
μ
f)
PD1 Switchable Domain
(FMPLL, Flash)
8 KB
Split
32 KB
Split
56 KB
Split
(C
)
REGn
CTRL
CTRL
CTRL
VDD_LV
HPVDD
VSS_LV
Off chip
BCP68
NPN driver
sw1 (<0.1Ω)
VRC_CTRL
HPREG
LPVDD
10 μf
LPREG
Chip Boundary
(C
)
DEC2
VDD_BV
VSS_HV
VDD_HV_A
100 nf
HPVDD
LPVDD
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Electrical Characteristics
The internal voltage regulator requires external bulk capacitance (C
) to be connected
REGn
to the device to provide a stable low voltage digital supply to the device. Also required for
stability is the C capacitor at ballast collector. This is needed to minimize sharp
DEC2
injection current when ballast is turning ON. Apart from the bulk capacitance, user should
connect EMI/decoupling cap (C
) at each V
/V
pin pair.
REGP
DD_LV SS_LV
Recommendations
●
●
The external NPN driver must be BCP68 type.
should be implemented as a power plane from the emitter of the ballast
V
DD_LV
transistor.
●
10 μF capacitors should be connected to the 4 pins closest to the outside of the
package and should be evenly distributed around the package. For BGA packages, the
balls should be used are D8, H14, R9, J3–one cap on each side of package.
–
There should be a track direct from the capacitor to this pin (pin also connects to
plane). The tracks ESR should be less than 100 mΩ.
V
DD_LV
–
The remaining V
pins (exact number will vary with package) should be
DD_LV
decoupled with 0.1 μF caps, connected to the pin as per 10 μF.
(see Section 4.4: Recommended operating conditions).
4.8.2
V
options
DD_BV
●
Option 1: V
shared with V
DD_HV_A
DD_BV
V
must be star routed from V
from the common source. This is to
DD_HV_A
DD_BV
eliminate ballast noise injection on the MCU.
●
Option 2: V independent of the MCU supply
DD_BV
V
> 2.6 V for correct functionality. The device is not monitoring this supply hence
DD_BV
the external component must meet the 2.6 V criteria through external monitoring if
required.
Table 23. Voltage regulator electrical characteristics
Value(2)
Symbol
C
Parameter
Conditions(1)
Unit
Min
Typ
Max
CREGn
RREG
SR — External ballast stability capacitance
—
—
40
—
60
μF
Stability capacitor equivalent serial
SR —
—
—
0.2
W
resistance
VDD_HV_A/HV_B/VSS_HV
pair
100
100
—
—
nF
nF
Decoupling capacitance (Close to
the pin)
CREGP
SR —
VDD_LV/VSS_LV pair
Stability capacitance regulator
SR — supply (Close to the ballast
collector)
CDEC2
VDD_HV_A/VSS_HV
10
—
40
μF
Before trimming
After trimming
—
—
1.32
1.28
—
—
VMREG
CC P Main regulator output voltage
V
Main regulator current provided to
VDD_LV domain
IMREG
SR —
—
—
—
350
mA
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Electrical Characteristics
SPC564Bxx - SPC56ECxx
Table 23. Voltage regulator electrical characteristics (continued)
Value(2)
Symbol
C
Parameter
Conditions(1)
Unit
Min
Typ
Max
IMREG = 200 mA
IMREG = 0 mA
—
—
—
—
—
2
1
Main regulator module current
consumption
IMREGINT CC D
VLPREG
ILPREG
mA
CC P Low power regulator output voltage After trimming
Low power regulator current
1.23
—
V
SR —
—
—
—
—
—
—
20
50
600
—
mA
provided to VDD_LV domain
ILPREG = 15 mA;
TA = 55 °C
D
Low power regulator module current
consumption
ILPREGINT CC
μA
I
LPREG = 0 mA;
—
TA = 55 °C
Main LVDs and reference current
IVREGREF CC D consumption (low power and main TA = 55 °C
regulator switched off)
—
2
—
—
μA
μA
Main LVD current consumption
(switch-off during standby)
IVREDLVD12 CC D
TA = 55 °C
—
—
1
(3)
In-rush current on VDD_HV_A
during power-up
IDD_HV_A CC D
—
—
600(4) mA
1. VDD_HV_A = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified.
2. All values need to be confirmed during device validation.
3. Assumption is VDD_HV_A is now supplying the external ballast. This current is the ballast inrush current.
4. Inrush current is seen more like steps of 600 mA peak. The startup of the regulator happens in steps of 50 mV in ~25 steps
to reach ~1.2 V VDD_LV. Each step peak current is within 600 mA
4.8.3
Voltage monitor electrical characteristics
The device implements a Power-on Reset module to ensure correct power-up initialization,
as well as four low voltage detectors to monitor the V
device is supplied:
and the V
voltage while
DD_HV_A
DD_LV
●
POR monitors V
during the power-up phase to ensure device is maintained in
DD_HV_A
a safe reset state
●
●
●
●
LVDHV3 monitors V
LVDHV5 monitors V
to ensure device is reset below minimum functional supply
when application uses device in the 5.0 V 10ꢀ range
DD_HV_A
DD_HV_A
LVDLVCOR monitors power domain No. 1 (PD1)
LVDLVBKP monitors power domain No. 0 (PD0). VDD_LV is same as PD0 supply.
Note:
When enabled, PD2 (RAM retention) is monitored through LVD_DIGBKP.
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Electrical Characteristics
Figure 9.
Low voltage monitor vs. Reset
V
DDHV/LV
V
V
LVDHVxH/LVxH
LVDHVxL/LVxL
RESET
Table 24. Low voltage monitor electrical characteristics
Symbol Parameter
Value(2)
Unit
C
Conditions(1)
Min
Typ
Max
VPORUP
VPORH
SR P Supply for functional POR module
CC P Power-on reset threshold
—
—
—
—
—
—
1.0
1.5
2.7
2.6
4.3
4.2
—
—
5.5
2.6
VLVDHV3H CC T LVDHV3 low voltage detector high threshold
VLVDHV3L CC T LVDHV3 low voltage detector low threshold
VLVDHV5H CC T LVDHV5 low voltage detector high threshold
VLVDHV5L CC T LVDHV5 low voltage detector low threshold
—
2.85
2.74
4.5
—
—
—
4.4
V
VLVDLVCORL CC P LVDLVCOR low voltage detector low threshold TA = 25 °C,
1.14(3)
after trimming
VLVDLVBKPL CC P LVDLVBKP low voltage detector low threshold
1.14(3)
1. VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified.
2. All values need to be confirmed during device validation.
3. The min. and max variation across process voltage and temperature will be available after device characterization.
Expected to be within 10 mV.
4.9
Low voltage domain power consumption
Table 25 provides DC electrical characteristics for significant application modes. These
values are indicative values; actual consumption depends on the application.
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Electrical Characteristics
SPC564Bxx - SPC56ECxx
Table 25. Low voltage power domain electrical characteristics
Value
Unit
Symbol
C
Parameter
Conditions(1)
Min Typ(2) Max(3)
RUN mode maximum
average current
(4)
IDDMAX
CC D
—
—
—
210 300(5),(6) mA
175(8), 240(9),
T
at 120 MHz
at 80 MHz
TA = 25 °C
TA = 25 °C
mA
(9)
(10)
RUN mode typical average
current(7)
IDDRUN
CC
T
110(8) 150(10) mA
IDDHALT
CC P HALT mode current(11)
—
—
—
25
35
mA
µA
1200(9),
P
TA = 25 °C
400(9)
(13)
IDDSTOP CC
STOP mode current(12)
No clocks active
P
P
TA = 150 °C
TA = 25 °C
—
—
10(9)
60
30(9)
175
mA
µA
IDDSTDBY3
(96 KBRAM CC
retained)
STANDBY3 mode
current(14)
No clocks active
No clocks active
No clocks active
P
P
P
T
P
TA = 150 °C
TA = 25 °C
TA = 150 °C
TA = 25 °C
TA = 150 °C
—
—
—
—
—
1000
45
3000
135
µA
µA
µA
µA
µA
IDDSTDBY2
(64 KBRAM CC
retained)
STANDBY2 mode
current(15)
800
25
2000
75
IDDSTDBY1
(8 KB RAM CC
retained)
STANDBY1 mode
current(16)
500
1000
32 kHz OSC
4–40 MHz OSC
16 MHz IRC
128 kHz IRC
—
—
—
—
TA = 25 °C
TA = 25 °C
TA = 25 °C
TA = 25 °C
—
—
—
—
—
—
—
—
5
3
µA
mA
µA
µA
Adders in
LP mode
CC T
500
5
1. VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified All temperatures are based on an
ambient temperature.
2. Target typical current consumption for the following typical operating conditions and configuration. Process = typical,
Voltage = 1.2 V.
3. Target maximum current consumption for mode observed under typical operating conditions. Process = Fast, Voltage =
1.32 V.
4. Running consumption is given on voltage regulator supply (VDDREG). It does not include consumption linked to I/Os
toggling. This value is highly dependent on the application. The given value is thought to be a worst case value with all
cores and peripherals running, and code fetched from code flash while modify operation on-going on data flash. It is to be
noticed that this value can be significantly reduced by application: switch-off not used peripherals (default), reduce
peripheral frequency through internal prescaler, fetch from RAM most used functions, use low power mode when possible.
5. Higher current may sunk by device during power-up and standby exit. Please refer to in rush current in Table 23.
6. Maximum “allowed” current is package dependent.
7. Only for the “P” classification: Code fetched from RAM: Serial IPs CAN and LIN in loop back mode, DSPI as Master, PLL
as system Clock (4 x Multiplier) peripherals on (eMIOS/CTU/ADC) and running at max frequency, periodic SW/WDG timer
reset enabled. RUN current measured with typical application with accesses on both code flash and RAM.
8. Subject to change, Configuration: 1
125 kbit/s), 10 LINFlexD (20 kbit/s), 8
Input, 1 CTU (40 ch.), 1 FlexRay (2 ch., 10 Mbit/s), 1
×
e200z4d + 4 kbit/s Cache, 1
DSPI (4 2 Mbit/s, 3 4 Mbit/s, 1
RTC, 4 PIT, 1
×
eDMA (32 ch), 4
10 Mbit/s), 40
SWT, 1 STM. Ethernet and e200z0h
×
FlexCAN (2
× 500 kbit/s, 2 ×
×
×
×
×
×
×
PWM (200 Hz), 40
× ADC
×
×
×
×
×
×
disabled. Also reduced timed I/O channels for smaller packages. RUN current measured with typical application with
accesses on both code flash and RAM.
9. This value is obtained from limited sample set
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Electrical Characteristics
10. Subject to change, Configuration: 1
×
e200z4d + 4 kbit/s Cache, 1
125 kbit/s), 4 LINFlexD (20 kbit/s), 6
ADC Input, 1 FlexRay (2 ch., 10 Mbit/s), 1
×
e200z0h (1/2 system frequency), CSE, 1
DSPI (2 2 Mbit/s, 3 4 Mbit/s,
FEC (100 Mbit/s), 1 RTC, 4
×
e
DMA
(10 ch.), 6
×
FlexCAN (4
×
500 kbit/s, 2
×
×
×
×
×
1
1
×
10 Mbit/s), 16
SWT, 1
×
Timed I/O, 16
×
×
×
×
×
PIT,
×
×
STM. For lower pin count packages reduce the amount of timed I/O’s and ADC channels. RUN current
measured with typical application with accesses on both code flash and RAM.
11. Data Flash Power Down. Code Flash in Low Power. SIRC 128 kHz and FIRC 16 MHz ON. 16 MHz XTAL clock. FlexCAN:
instances: 0, 1, 2 ON (clocked but no reception or transmission), instances: 4, 5, 6 clocks gated. LINFlex: instances: 0, 1, 2
ON (clocked but no reception or transmission), instance: 3-9 clocks gated. eMIOS: instance: 0 ON (16 channels on PA[0]-
PA[11] and PC[12]-PC[15]) with PWM 20 kHz, instance: 1 clock gated. DSPI: instance: 0 (clocked but no communication,
instance: 1-7 clocks gated). RTC/API ON. PIT ON. STM ON. ADC ON but no conversion except 2 analog watchdogs.
12. Only for the “P” classification: No clock, FIRC 16 MHz OFF, SIRC128 kHz ON, PLL OFF, HPvreg OFF, LPVreg ON. All
possible peripherals off and clock gated. Flash in power down mode.
13. This current is the maximum value at room temperature for any sample. The condition is same as note 11.
14. Only for the “P” classification: LPreg ON, HPVreg OFF, 96 KB RAM ON, device configured for minimum consumption, all
possible modules switched-off.
15. Only for the “P” classification: LPreg ON, HPVreg OFF, 64 KB RAM ON, device configured for minimum consumption, all
possible modules switched-off.
16. LPreg ON, HPVreg OFF, 8 KB RAM ON, device configured for minimum consumption, all possible modules switched OFF.
4.10
Flash memory electrical characteristics
4.10.1
Program/Erase characteristics
Table 26 shows the code flash memory program and erase characteristics.
Table 26. Code flash memory—Program and erase specifications
Value
Symbol
C
Parameter
Unit
Initial
Min
Typ(1)
Max(3)
max(2)
Tdwprogram
T16Kpperase
T32Kpperase
T128Kpperase
Teslat
Double word (64 bits) program time(4)
16 KB block pre-program and erase time
32 KB block pre-program and erase time
128 KB block pre-program and erase time
—
—
—
—
—
20
—
—
18
200
300
600
—
50
500
600
1300
30
500
5000
5000
5000
30
µs
ms
ms
ms
µs
C
D Erase Suspend Latency
C Erase Suspend Request Rate
D Program Abort Latency
D Erase Abort Latency
tESRT
—
—
—
ms
µs
CC
tPABT
—
10
10
tEAPT
—
30
30
µs
1. Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to change
pending device characterization.
2. Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.
3. The maximum program and erase times occur after the specified number of program/erase cycles. These maximum values
are characterized but not guaranteed.
4. Actual hardware programming times. This does not include software overhead.
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Table 27 shows the data flash memory program and erase characteristics.
Table 27. Data flash memory—Program and erase specifications
Value
Symbol
C
Parameter
Unit
Initial
Max(3)
max(2)
Min
Typ(1)
Twprogram
T16Kpperase
Teslat
Word (32 bits) program time(4)
—
—
—
10
—
—
30
700
—
70
800
30
500
5000
30
µs
ms
µs
C
16 KB block pre-program and erase time
D Erase Suspend Latency
C Erase Suspend Request Rate
D Program Abort Latency
D Erase Abort Latency
tESRT
—
—
—
ms
µs
tPABT
—
12
12
CC
tEAPT
—
30
30
µs
1. Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to change
pending device characterization.
2. Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.
3. The maximum program and erase times occur after the specified number of program/erase cycles. These maximum values
are characterized but not guaranteed.
4. Actual hardware programming times. This does not include software overhead.
Table 28. Flash memory module life
Value
Symbol
C
Parameter
Conditions
Unit
Min
Typ
Number of program/erase cycles per
block for 16 Kbyte blocks over the
operating temperature range (TJ)
—
—
—
100000
100000 cycles
100000 cycles
100000 cycles
Number of program/erase cycles per
CC C block for 32 Kbyte blocks over the
operating temperature range (TJ)
P/E
10000
1000
Number of program/erase cycles per
block for 128 Kbyte blocks over the
operating temperature range (TJ)
Blocks with 0–1000 P/E
cycles
20
10
5
—
—
—
years
years
years
Minimum data retention at 85 °C
Blocks with 10000 P/E
cycles
Retention CC
C
average ambient temperature(1)
Blocks with 100000 P/E
cycles
1. Ambient temperature averaged over duration of application, not to exceed recommended product operating temperature
range.
ECC circuitry provides correction of single bit faults and is used to improve further
automotive reliability results. Some units will experience single bit corrections throughout
the life of the product with no impact to product reliability.
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Electrical Characteristics
Table 29. Flash memory read access timing
Conditions(1)
Symbol
C
Parameter
Max
Unit
Code flash
memory
Data flash
memory
P
C
D
C
5 wait states
3 wait state
3 wait states(2)
—
13 wait states
9 wait state
—
120 + 2ꢀ
80 + 2ꢀ
Maximum frequency for Flash
reading
fREAD
CC
MHz
64 + 2ꢀ
7 wait states
1. VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified.
2. Wait states are subject to change per device characterization.
4.10.2
Flash memory power supply DC characteristics
Table 30 shows the flash memory power supply DC characteristics on external supply.
Table 30. Flash memory power supply DC electrical characteristics
Value(2)
Symbol
Parameter
Conditions(1)
Unit
Min Typ Max
Code flash
memory
(3)
ICFREAD
33
13
52
13
Sum of the current consumption Flash memory module read
on VDD_HV_A on read access
CC
CC
mA
fCPU = 120 MHz + 2ꢀ(4)
Data flash
memory
(3)
IDFREAD
Code flash
memory
(3)
(3)
Program/Erase on-going
Sum of the current consumption while reading flash memory
ICFMOD
IDFMOD
mA
on VDD_HV_A (program/erase)
registers
Data flash
memory
fCPU = 120 MHz + 2ꢀ (4)
Sum of the current consumption
CC on VDD_HV_A during flash
memory low power mode
Code flash
memory
(3)
ICFLPW
1.1 mA
Code flash
memory
(3)
ICFPWD
150
µA
Sum of the current consumption
CC on VDD_HV_A during flash
memory power down mode
Data flash
memory
(3)
IDFPWD
150
1. VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = –40 to 125 °C, unless otherwise specified.
2. All values need to be confirmed during device validation.
3. Data based on characterization results, not tested in production.
4. fCPU 120 MHz + 2ꢀ can be achieved over full temperature 125 °C ambient, 150 °C junction temperature.
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Electrical Characteristics
SPC564Bxx - SPC56ECxx
4.10.3
Flash memory start-up/switch-off timings
Table 31. Start-up time/Switch-off time
Value
Min Typ Max
Conditions
Symbol
C
Parameter
Unit
(1)
Code flash
memory
—
—
—
—
—
—
—
—
—
—
—
—
Delay for flash memory module to exit
reset mode
TFLARSTEXIT CC D
—
—
—
—
125
0.5
30
Data flash
memory
Delay for flash memory module to exit Code flash
TFLALPEXIT
CC T
low-power mode
memory
Code flash
memory
Delay for flash memory module to exit
power-down mode
TFLAPDEXIT CC T
Data flash
memory
µs
Delay for flash memory module to enter Code flash
TFLALPENTRY CC T
0.5
low-power mode
memory
1. VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified.
4.11
Electromagnetic compatibility (EMC) characteristics
Susceptibility tests are performed on a sample basis during product characterization.
4.11.1
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user apply EMC software optimization and pre-
qualification tests in relation with the EMC level requested for the application.
●
Software recommendations − The software flowchart must include the management of
runaway conditions such as:
–
–
–
Corrupted program counter
Unexpected reset
Critical data corruption (control registers)
●
Pre-qualification trials − Most of the common failures (unexpected reset and program
counter corruption) can be reproduced by manually forcing a low state on the reset pin
or the oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device. When
unexpected behavior is detected, the software can be hardened to prevent
unrecoverable errors occurring (see application note Software Techniques For
Improving Microcontroller EMC Performance (AN1015)).
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Electrical Characteristics
4.11.2
Electromagnetic interference (EMI)
The product is monitored in terms of emission based on a typical application. This emission
test conforms to the IEC61967-1 standard, which specifies the general conditions for EMI
measurements.
(1)(2)
Table 32. EMI radiated emission measurement
Symbol Parameter
Value
C
Conditions
Unit
Min Typ Max
—
SR — Scan range
—
—
—
0.150
—
1000 MHz
fCPU SR — Operating frequency
VDD_LV SR — LV operating voltages
120
—
—
MHz
V
—
1.28
No PLL frequency
modulation
VDD = 5 V, TA = 25 °C,
LQFP176 package
Test conforming to IEC 61967-2,
fOSC = 40 MHz/fCPU = 120 MHz
—
—
—
—
18 dBµV
SEMI CC T Peak level
2ꢀ PLL frequency
modulation
14(3) dBµV
1. EMI testing and I/O port waveforms per IEC 61967-1, -2, -4.
2. For information on conducted emission and susceptibility measurement (norm IEC 61967-4), please contact your local
marketing representative.
3. All values need to be confirmed during device validation.
4.11.3
Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the
product is stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pin). This test
conforms to the AEC-Q100-002/-003/-011 standard. For more details, refer to the
application note Electrostatic Discharge Sensitivity Measurement (AN1181).
(1)(2)
Table 33. ESD absolute maximum ratings
Symbol
Ratings
Conditions
Class
Max value(3)
Unit
Electrostatic discharge voltage
(Human Body Model)
TA = 25 °C
conforming to AEC-Q100-002
VESD(HBM)
H1C
2000
Electrostatic discharge voltage
(Machine Model)
TA = 25 °C
conforming to AEC-Q100-003
VESD(MM)
M2
200
V
500
Electrostatic discharge voltage
(Charged Device Model)
TA = 25 °C
conforming to AEC-Q100-011
VESD(CDM)
C3A
750 (corners)
1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
2. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification
requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at
room temperature followed by hot temperature, unless specified otherwise in the device specification.
3. Data based on characterization results, not tested in production.
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Electrical Characteristics
SPC564Bxx - SPC56ECxx
Static latch-up (LU)
Two complementary static tests are required on six parts to assess the latch-up
performance:
●
A supply over-voltage is applied to each power supply pin.
●
A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with the EIA/JESD 78 IC latch-up standard.
Table 34. Latch-up results
Symbol
Parameter
Conditions
Class
TA = 125 °C
conforming to JESD 78
LU
Static latch-up class
II level A
4.12
Fast external crystal oscillator (4–40 MHz) electrical
characteristics
The device provides an oscillator/resonator driver. Figure 10 describes a simple model of
the internal oscillator driver and provides an example of a connection for an oscillator or a
resonator.
Table 35 provides the parameter description of 4 MHz to 40 MHz crystals used for the
design simulations.
Figure 10. Crystal oscillator and resonator connection scheme
EXTAL
C1
XTAL
XTAL
R
D
C2
DEVICE
V
DD
I
R
EXTAL
EXTAL
DEVICE
XTAL
DEVICE
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Electrical Characteristics
Note:
XTAL/EXTAL must not be directly used to drive external circuits.
Table 35. Crystal description
Shunt
Crystal
equivalent
series
resistance
ESR Ω
Crystal
motional
capacitance
(Cm) fF
Crystal
motional
inductance
(Lm) mH
Load on
xtalin/xtalout
C1 = C2
capacitance
between
xtalout
Nominal
frequency
(MHz)
NDK crystal
reference
(pF)(1)
and xtalin
C0(2) (pF)
4
NX8045GB
300
300
150
120
120
50
2.68
2.46
2.93
3.11
3.90
6.18
591.0
160.7
86.6
56.5
25.3
2.56
21
17
15
15
10
8
2.93
3.01
2.91
2.93
3.00
3.49
8
10
12
16
40
NX5032GA
NX5032GA
1. The values specified for C1 and C2 are the same as used in simulations. It should be ensured that the testing includes all
the parasitics (from the board, probe, crystal, etc.) as the AC / transient behavior depends upon them.
2. The value of C0 specified here includes 2 pF additional capacitance for parasitics (to be seen with bond-pads, package,
etc.).
Figure 11. Fast external crystal oscillator (4 to 40 MHz) electrical characteristics
S_MTRANS bit (ME_GS register)
1
0
V
XTAL
1/f
MXOSC
V
FXOSC
90ꢀ
10ꢀ
V
FXOSCOP
T
valid internal clock
MXOSCSU
Table 36. Fast external crystal oscillator (4 to 40 MHz) electrical characteristics
Value(2)
Symbol
C
Parameter
Conditions(1)
Unit
Min
Typ
Max
Fast external crystal
oscillator frequency
fFXOSC
SR —
—
4.0
—
40.0
MHz
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Electrical Characteristics
SPC564Bxx - SPC56ECxx
Table 36. Fast external crystal oscillator (4 to 40 MHz) electrical characteristics (continued)
Value(2)
Symbol
C
Parameter
Conditions(1)
Unit
Min
Typ
Max
Fast external crystal VDD = 3.3 V 10ꢀ
oscillator
transconductance
8.699
9.440
13.159
13.159
15.846
16.859
CC C
gmFXOSC
mA/V
VDD = 5.0 V 10ꢀ
fOSC = 40 MHz
Oscillation
amplitude at EXTAL
For both VDD = 3.3 V
10ꢀ, VDD = 5.0 V
10ꢀ
VFXOSC
CC T
—
0.95
—
V
V
Oscillation
operating point
VFXOSCOP CC P
—
—
—
—
—
—
1.8
2
VDD = 3.3 V 10ꢀ,
fOSC = 40 MHz
2.2
2.5
1.5
1.8
V
DD = 5.0 V 10ꢀ,
fOSC = 40 MHz
DD = 3.3 V 10ꢀ,
fOSC = 16 MHz
DD = 5.0 V 10ꢀ,
fOSC = 16 MHz
OSC = 40 MHz
2.3
1.3
1.6
Fast external crystal
consumption
(3)
IFXOSC
CC T oscillator
V
mA
ms
V
f
Fast external crystal
TFXOSCSU CC T oscillator start-up
time
For both VDD = 3.3 V
10ꢀ, VDD = 5.0 V
10ꢀ
—
—
5
Input high level
SR P CMOS
(Schmitt Trigger)
Oscillator bypass
mode
VIH
0.65VDD_HV_A
—
—
VDD_HV_A + 0.4
V
V
Input low level
SR P CMOS
(Schmitt Trigger)
Oscillator bypass
mode
VIL
−0.3
0.35VDD_HV_A
1. VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified.
2. All values need to be confirmed during device validation.
3. Stated values take into account only analog module consumption but not the digital contributor (clock tree and enabled
peripherals).
4.13
Slow external crystal oscillator (32 kHz) electrical
characteristics
The device provides a low power oscillator/resonator driver.
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Electrical Characteristics
Figure 12. Crystal oscillator and resonator connection scheme
OSC32K_EXTAL
OSC32K_EXTAL
C1
R
P
OSC32K_XTAL
OSC32K_XTAL
C2
DEVICE
DEVICE
Note:
OSC32K_XTAL/OSC32K_EXTAL must not be directly used to drive external circuits.
Figure 13. lEquivalent circuit of a quartz crystal
C0
Crystal
Rm
Lm
Cm
C1
C2
C1
C2
(1)
Table 37. Crystal motional characteristics
Value
Symbol
Parameter
Conditions
Unit
Min
Typ
Max
Lm
Motional inductance
—
—
—
—
11.796
2
—
—
KH
fF
Cm
Motional capacitance
Load capacitance at OSC32K_XTAL and
OSC32K_EXTAL with respect to ground(2)
C1/C2
—
18
—
28
pF
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Electrical Characteristics
SPC564Bxx - SPC56ECxx
(1)
Table 37. Crystal motional characteristics (continued)
Value
Unit
Symbol
Parameter
Conditions
Min
Typ
Max
AC coupled @ C0 = 2.85
pF(4)
—
—
65
AC coupled @ C0 = 4.9 pF(4)
AC coupled @ C0 = 7.0 pF(4)
AC coupled @ C0 = 9.0 pF(4)
—
—
—
—
—
—
50
35
30
(3)
Rm
Motional resistance
kW
1. The crystal used is Epson Toyocom MC306.
2. This is the recommended range of load capacitance at OSC32K_XTAL and OSC32K_EXTAL with respect to ground. It
includes all the parasitics due to board traces, crystal and package.
3. Maximum ESR (Rm) of the crystal is 50 kΩ.
4. C0 Includes a parasitic capacitance of 2.0 pF between OSC32K_XTAL and OSC32K_EXTAL pins.
Figure 14. Slow external crystal oscillator (32 kHz) electrical characteristics
OSCON bit (OSC_CTL register)
1
0
V
OSC32K_XTAL
1/f
LPXOSC32K
V
LPXOSC32K
90ꢀ
10ꢀ
T
valid internal clock
LPXOSC32KSU
Table 38. Slow external crystal oscillator (32 kHz) electrical characteristics
Value(2)
Symbol
C
Parameter
Conditions(1)
Unit
Min
Typ
Max
Slow external crystal oscillator
frequency
fSXOSC
SR —
—
32
32.768
40
kHz
VDD = 3.3 V 10ꢀ,
17.45
17.79
1.2
—
—
28.23
29.91
1.7
Slow external crystal oscillator
transconductance
gmSXOSC CC —
µA/V
VDD = 5.0 V 10ꢀ
VSXOSC
CC T Oscillation amplitude
—
—
1.4
—
V
ISXOSCBIAS CC T Oscillation bias current
1.2
4.4
µA
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Electrical Characteristics
Table 38. Slow external crystal oscillator (32 kHz) electrical characteristics (continued)
Value(2)
Symbol
C
Parameter
Conditions(1)
Unit
Min
Typ
Max
Slow external crystal oscillator
consumption
ISXOSC
CC T
—
—
—
—
7
µA
s
Slow external crystal oscillator
start-up time
TSXOSCSU CC T
—
—
2(3)
1. VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified.
2. All values need to be confirmed during device validation.
3. Start-up time has been measured with EPSON TOYOCOM MC306 crystal. Variation may be seen with other crystal.
4.14
FMPLL electrical characteristics
The device provides a frequency-modulated phase-locked loop (FMPLL) module to
generate a fast system clock from the main oscillator driver.
Table 39. FMPLL electrical characteristics
Symbol Parameter
Value(2)
C
Conditions(1)
Unit
Min
Typ
Max
fPLLIN SR — FMPLL reference clock(3)
—
—
4
—
64
MHz
ꢀ
FMPLL reference clock duty
ΔPLLIN SR —
40
16
—
—
60
cycle(3)
FMPLL output clock
fPLLOUT CC P
—
120
MHz
frequency
fCPU SR — System clock frequency
fFREE CC P Free-running frequency
—
—
—
—
—
120 + 2ꢀ(4) MHz
20
150
100
MHz
µs
Stable oscillator (fPLLIN = 16
MHz)
tLOCK CC P FMPLL lock time
40
f
PLLIN = 40 MHz (resonator),
6
ΔtLTJIT CC — FMPLL long term jitter
fPLLCLK @ 120 MHz, 4000
cycles
—
—
—
—
ns
(for < 1ppm)
IPLL
CC C FMPLL consumption
TA = 25 °C
3
mA
1. VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified.
2. All values need to be confirmed during device validation.
3. PLLIN clock retrieved directly from 4-40 MHz XOSC or 16 MIRC. Input characteristics are granted when oscillator is used
in functional mode. When bypass mode is used, oscillator input clock should verify fPLLIN and ΔPLLIN
.
4. fCPU 120 + 2ꢀ MHz can be achieved at 125 °C.
4.15
Fast internal RC oscillator (16 MHz) electrical characteristics
The device provides a 16 MHz main internal RC oscillator. This is used as the default clock
at the power-up of the device and can also be used as input to PLL.
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Electrical Characteristics
SPC564Bxx - SPC56ECxx
Table 40. Fast internal RC oscillator (16 MHz) electrical characteristics
Value(2)
Unit
Symbol
C
Parameter
Conditions(1)
Min
Typ
Max
CC P
SR —
TA = 25 °C, trimmed
—
—
16
—
Fast internal RC oscillator high
frequency
fFIRC
MHz
µA
12
20
Fast internal RC oscillator high
(3)
IFIRCRUN
CC T frequency current in running
mode
TA = 25 °C, trimmed
—
—
200
D
TA = 25 °C
TA = 55 °C
—
—
—
—
—
—
—
—
—
—
—
—
—
—
100
200
1
nA
nA
µA
Fast internal RC oscillator high
IFIRCPWD CC D frequency current in power
down mode
D
TA = 125 °C
—
sysclk = off
500
600
700
900
1250
—
—
—
—
—
—
2.0
5
sysclk = 2 MHz
TA = 25 °C sysclk = 4 MHz
sysclk = 8 MHz
sysclk = 16 MHz
Fast internal RC oscillator high
IFIRCSTOP CC T frequency and system clock
current in stop mode
µA
µs
C
V
V
V
DD = 5.0 V 10ꢀ
DD = 3.3 V 10ꢀ
DD = 5.0 V 10ꢀ
TA = 55 °C
—
—
Fast internal RC oscillator start-
up time
TFIRCSU CC
—
—
2.0
5
TA = 125 °C
—
VDD = 3.3 V 10ꢀ
—
Fast internal RC oscillator
ΔFIRCPRE CC C precision after software
trimming of fFIRC
TA = 25 °C
TA = 25 °C
−1
—
+1
+5
ꢀ
ꢀ
Fast internal RC oscillator
ΔFIRCTRIM CC C
—
1.6
trimming step
Fast internal RC oscillator
variation over temperature and
ΔFIRCVAR CC C supply with respect to fFIRC at
TA = 25 °C in high-frequency
—
−5
—
ꢀ
configuration
1. VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified.
2. All values need to be confirmed during device validation.
3. This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is ON.
4.16
Slow internal RC oscillator (128 kHz) electrical
characteristics
The device provides a 128 kHz low power internal RC oscillator. This can be used as the
reference clock for the RTC module.
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Electrical Characteristics
Table 41. Slow internal RC oscillator (128 kHz) electrical characteristics
Value(2)
Symbol
C
Parameter
Conditions(1)
Unit
Min Typ Max
CC P
SR —
TA = 25 °C, trimmed
—
—
128
—
—
Slow internal RC oscillator low
frequency
fSIRC
kHz
100
150
Slow internal RC oscillator low
frequency current
(3)
ISIRC
CC C
TA = 25 °C, trimmed
—
—
−2
—
—
8
5
µA
µs
Slow internal RC oscillator start-up
time
TSIRCSU CC P
ΔSIRCPRE CC C
ΔSIRCTRIM CC C
TA = 25 °C, VDD = 5.0 V 10ꢀ
12
+2
—
Slow internal RC oscillator precision
after software trimming of fSIRC
TA = 25 °C
—
—
2.7
ꢀ
ꢀ
Slow internal RC oscillator trimming
step
Slow internal RC oscillator variation
in temperature and supply with
respect to fSIRC at TA = 55 °C in high
frequency configuration
ΔSIRCVAR CC C
High frequency configuration −10
—
+10
1. VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified.
2. All values need to be confirmed during device validation.
3. This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is ON.
4.17
ADC electrical characteristics
4.17.1
Introduction
The device provides two Successive Approximation Register (SAR) analog-to-digital
converters (10-bit and 12-bit).
Note:
Due to ADC limitations, the two ADCs cannot sample a shared channel at the same time
i.e., their sampling windows cannot overlap if a shared channel is selected. If this is done,
neither of the ADCs can guarantee their conversion accuracies.
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Electrical Characteristics
SPC564Bxx - SPC56ECxx
Figure 15. ADC_0 characteristic and error definitions
Offset Error OSE
Gain Error GE
1023
1022
1021
1020
1019
1 LSB ideal = V
/ 1024
DD_ADC
1018
(2)
code out
7
(1)
6
(1) Example of an actual transfer curve
(2) The ideal transfer curve
5
(5)
(3) Differential non-linearity error (DNL)
(4) Integral non-linearity error (INL)
(5) Center of a step of the actual transfer curve
4
(4)
3
(3)
2
1
1 LSB (ideal)
0
1
2
3
4
5
6
7
1017 1018 1019 1020 1021 1022 1023
Vin(A) (LSBideal
)
Offset Error OSE
Input impedance and ADC accuracy
In the following analysis, the input circuit corresponding to the precise channels is
considered.
To preserve the accuracy of the A/D converter, it is necessary that analog input pins have
low AC impedance. Placing a capacitor with good high frequency characteristics at the input
pin of the device can be effective: the capacitor should be as large as possible, ideally
infinite. This capacitor contributes to attenuating the noise present on the input pin;
furthermore, it sources charge during the sampling phase, when the analog signal source is
a high-impedance source.
A real filter can typically be obtained by using a series resistance with a capacitor on the
input pin (simple RC filter). The RC filtering may be limited according to the value of source
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Electrical Characteristics
impedance of the transducer or circuit supplying the analog signal to be measured. The filter
at the input pins must be designed taking into account the dynamic characteristics of the
input signal (bandwidth) and the equivalent input impedance of the ADC itself.
In fact a current sink contributor is represented by the charge sharing effects with the
sampling capacitance: C being substantially a switched capacitance, with a frequency
S
equal to the conversion rate of the ADC, it can be seen as a resistive path to ground. For
instance, assuming a conversion rate of 1 MHz, with C equal to 3 pF, a resistance of 330
S
kΩ is obtained (R = 1 / (fc
× C ), where fc represents the conversion rate at the
considered channel). To minimize the error induced by the voltage partitioning between this
EQ
S
resistance (sampled voltage on C ) and the sum of R + R + R + R
+ R , the external
S
S
F
L
SW
AD
circuit must be designed to respect the Equation 4:
Equation 4
R + R + R + R
+ R
S
F
L
SW
AD
1
--------------------------------------------------------------------------
V •
< -- LSB
2
A
R
EQ
Equation 4 generates a constraint for external network design, in particular on resistive path.
Internal switch resistances (R
resistances.
and R ) can be neglected with respect to external
SW
AD
Figure 16. Input equivalent circuit (precise channels)
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME
V
DD
Channel
Sampling
Selection
Source
Filter
Current Limiter
R
R
R
R
R
AD
S
F
L
SW1
V
C
C
C
C
S
A
F
P1
P2
R
Source Impedance
Filter Resistance
S
F
F
L
R
C
R
R
R
C
C
Filter Capacitance
Current Limiter Resistance
Channel Selection Switch Impedance
SW1
Sampling Switch Impedance
AD
Pin Capacitance (two contributions, C and C
P1
)
P
S
P2
Sampling Capacitance
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Electrical Characteristics
SPC564Bxx - SPC56ECxx
Figure 17. Input equivalent circuit (extended channels)
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME
V
DD
Channel
Selection
Extended
Switch
Sampling
Source
R
Filter
Current Limiter
R
R
R
R
L
R
AD
SW2
S
F
SW1
C
S
C
V
C
C
C
P2
A
F
P1
P3
R
R
C
R
R
R
C
C
Source Impedance
Filter Resistance
S
F
Filter Capacitance
F
Current Limiter Resistance
L
Channel Selection Switch Impedance (two contributions R
and R
)
SW2
SW
SW1
Sampling Switch Impedance
AD
Pin Capacitance (three contributions, C , C and C )
P3
P
S
P1
P2
Sampling Capacitance
A second aspect involving the capacitance network shall be considered. Assuming the three
capacitances C , C and C are initially charged at the source voltage V (refer to the
F
P1
P2
A
equivalent circuit reported in Figure 16): A charge sharing phenomenon is installed when
the sampling phase is started (A/D switch close).
Figure 18. Transient behavior during sampling phase
Voltage Transient on CS
V
CS
V
A
ΔV < 0.5 LSB
V
A2
1
2
τ1 < (RSW + RAD) CS << TS
V
A1
τ2 = RL (CS + CP1 + CP2)
T
t
S
In particular two different transient periods can be distinguished:
1. A first and quick charge transfer from the internal capacitance C and C to the
P1
P2
sampling capacitance C occurs (C is supposed initially completely discharged):
S
S
considering a worst case (since the time constant in reality would be faster) in which
C
is reported in parallel to C (call C = C + C ), the two capacitances C and
P2
P1 P P1 P2 P
C are in series, and the time constant is
S
Equation 5
C • C
P
S
---------------------
τ = (R
+ R
) •
1
SW
AD
C + C
P
S
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Electrical Characteristics
Equation 5 can again be simplified considering only C as an additional worst
S
condition. In reality, the transient is faster, but the A/D converter circuitry has been
designed to be robust also in the very worst case: the sampling time T is always much
S
longer than the internal time constant:
Equation 6
τ < (R
+ R
) • C « T
S S
1
SW
AD
The charge of C and C is redistributed also on C , determining a new value of the
P1
P2
S
voltage V on the capacitance according to Equation 7:
A1
Equation 7
V
• (C + C + C ) = V • (C + C )
P1 P2 P1 P2
A1
S
A
2. A second charge transfer involves also C (that is typically bigger than the on-chip
F
capacitance) through the resistance R : again considering the worst case in which C
L
P2
and C were in parallel to C (since the time constant in reality would be faster), the
S
P1
time constant is:
Equation 8
τ < R • (C + C + C )
P2
2
L
S
P1
In this case, the time constant depends on the external circuit: in particular imposing
that the transient is completed well before the end of sampling time T , a constraints on
S
R sizing is obtained:
L
Equation 9
10 • τ = 10 • R • (C + C + C ) < T
P1 P2 S
2
L
S
Of course, R shall be sized also according to the current limitation constraints, in
L
combination with R (source impedance) and R (filter resistance). Being C
S
F
F
definitively bigger than C , C and C , then the final voltage V (at the end of the
P1
P2
S
A2
charge transfer transient) will be much higher than V . Equation 10 must be respected
A1
(charge balance assuming now C already charged at V ):
S
A1
Equation 10
V
• (C + C + C + C ) = V • C + V • (C + C + C )
P1 P2 A1 P1 P2
A2
S
F
A
F
S
The two transients above are not influenced by the voltage source that, due to the presence
of the R C filter, is not able to provide the extra charge to compensate the voltage drop on
F
F
C with respect to the ideal source V ; the time constant R C of the filter is very high with
S
A
F F
respect to the sampling time (T ). The filter is typically designed to act as anti-aliasing.
S
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Electrical Characteristics
SPC564Bxx - SPC56ECxx
Figure 19. Spectral representation of input signal
Analog source bandwidth (VA)
TC < 2 RFCF (Conversion rate vs. filter pole)
Noise
fF = f0 (Anti-aliasing filtering condition)
2 f0 < fC (Nyquist)
f0
f
Anti-aliasing filter (fF = RC filter pole)
Sampled signal spectrum (fC = Conversion rate)
fF
f0
fC
f
f
Calling f the bandwidth of the source signal (and as a consequence the cut-off frequency of
0
the anti-aliasing filter, f ), according to the Nyquist theorem the conversion rate f must be at
F
C
least 2f ; it means that the constant time of the filter is greater than or at least equal to twice
0
the conversion period (T ). Again the conversion period T is longer than the sampling time
C
C
T , which is just a portion of it, even when fixed channel continuous conversion mode is
S
selected (fastest conversion rate at a specific channel): in conclusion it is evident that the
time constant of the filter R C is definitively much higher than the sampling time T , so the
F
F
S
charge level on C cannot be modified by the analog signal source during the time in which
S
the sampling switch is closed.
The considerations above lead to impose new constraints on the external circuit, to reduce
the accuracy error due to the voltage drop on C ; from the two charge balance equations
S
above, it is simple to derive Equation 11 between the ideal and real sampled voltage on C :
S
Equation 11
V
C
+ C + C + C
P2
----------- = -------------------------------------------------------
A
P1
C
F
S
V
+ C + C
P2 F
A2
P1
From this formula, in the worst case (when V is maximum, that is for instance 5 V),
A
assuming to accept a maximum error of half a count, a constraint is evident on C value:
F
Equation 12 ADC_0 (10-bit)
C
C
> 2048 • C
> 8192 • C
F
F
S
S
Equation 13 ADC_1 (12-bit)
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Electrical Characteristics
ADC electrical characteristics
Table 42. ADC input leakage current
Value
Unit
Symbol C
Parameter
Conditions
Min
Typ
Max
C
TA = −40 °C
TA = 25 °C
TA = 105 °C
TA = 125 °C
—
—
—
—
1
1
—
—
C
ILKG CC
C
Input leakage current
No current injection on adjacent pin
nA
8
200
400
P
45
Table 43. ADC conversion characteristics (10-bit ADC_0)
Value
Typ
Symbol
C
Parameter
Conditions(1)
Unit
Min
Max
Voltage on
VSS_HV_ADC0
VSS_ADC0 SR — (ADC_0 reference)
—
−0.1
—
—
0.1
V
pin with respect to
(2)
ground (VSS_HV
)
Voltage on
VDD_HV_ADC0 pin
VDD_ADC0 SR — (ADC_0 reference)
with respect to
—
VDD_HV_A − 0.1
VDD_HV_A + 0.1
V
ground (VSS_HV
)
Analog input
voltage(3)
VAINx
SR —
—
—
—
VSS_ADC0 − 0.1
—
—
—
VDD_ADC0 + 0.1
32 + 2ꢀ
1.5
V
ADC_0 analog
frequency
fADC0 SR —
6
MHz
ADC_0 power up
delay
tADC0_PU SR —
—
µs
ns
tADC0_S CC
tADC0_C CC
T
P
Sample time(4)
Conversion time(5),(6)
ADC_0 input
fADC = 32 MHz
fADC = 32 MHz
fADC = 30 MHz
500
—
—
—
0.625
0.700
µs
pF
CS
CC D sampling
capacitance
—
—
—
3
ADC_0 input pin
capacitance 1
CP1
CP2
CP3
CC
CC
CC
D
D
D
—
—
—
—
—
—
—
—
—
3
1
1
pF
pF
pF
ADC_0 input pin
capacitance 2
ADC_0 input pin
capacitance 3
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Table 43. ADC conversion characteristics (10-bit ADC_0) (continued)
Value
Symbol
C
Parameter
Conditions(1)
Unit
Min
Typ
Max
Internal resistance of
analog source
RSW1 CC
RSW2 CC
D
D
D
—
—
—
—
—
3
kΩ
kΩ
kΩ
Internal resistance of
analog source
—
—
−5
—
—
—
2
2
5
Internal resistance of
analog source
RAD
CC
Current
VDD =
3.3 V 10ꢀ
injection on
one ADC_0
input, different
from the
IINJ
SR — Input current Injection
Absolute value for
mA
VDD
=
−5
—
5
5.0 V 10ꢀ
converted one
| INL | CC
T
No overload
No overload
—
—
0.5
0.5
1.5
1.0
LSB
LSB
integral non-linearity
Absolute differential
non-linearity
| DNL | CC
T
| OFS | CC
| GNE | CC
T
T
P
Absolute offset error
Absolute gain error
—
—
—
−2
0.5
0.6
0.6
—
—
2
LSB
LSB
—
Total unadjusted
error(7) for precise
channels, input only
pins
Without current injection
TUEP CC
TUEX CC
LSB
LSB
T
With current injection
−3
3
T
T
Total unadjusted
error(7) for extended
channel
Without current injection
With current injection
−3
−4
1
3
4
1. VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified.
2. Analog and digital VSS_HV must be common (to be tied together externally).
3. VAINx may exceed VSS_ADC0 and VDD_ADC0 limits, remaining on absolute maximum ratings, but the results of the
conversion will be clamped respectively to 0x000 or 0x3FF.
4. During the sample time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tADC0_S. After the end of
the sample time tADC0_S, changes of the analog input voltage have no effect on the conversion result. Values for the
sample clock tADC0_S depend on programming.
5. Conversion time = Bit evaluation time + Sampling time + 1 Clock cycle delay.
6. Refer to ADC conversion table for detailed calculations.
7. Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a
combination of Offset, Gain and Integral Linearity errors.
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Electrical Characteristics
Figure 20. ADC_1 characteristic and error definitions
Offset Error OSE
Gain Error GE
4095
4094
4093
4092
4091
1 LSB ideal = AVDD / 4096
4090
(2)
code out
7
(1)
6
(1) Example of an actual transfer curve
(2) The ideal transfer curve
5
(5)
(3) Differential non-linearity error (DNL)
(4) Integral non-linearity error (INL)
(5) Center of a step of the actual transfer curve
4
(4)
3
(3)
2
1
1 LSB (ideal)
0
1
2
3
4
5
6
7
4090 4091 4092 4093 4094 4095
Vin(A) (LSBideal
)
Offset Error OSE
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Table 44. Conversion characteristics (12-bit ADC_1)
Value
Symbol
Parameter
Conditions(1)
Unit
Min
Typ
Max
Voltage on
VSS_HV_ADC1
VSS_ADC1 SR (ADC_1 reference) —
−0.1
0.1
V
pin with respect to
(2)
ground (VSS_HV
)
Voltage on
VDD_HV_ADC1
pin (ADC_1
reference) with
respect to ground
3
VDD_ADC1
SR
—
VDD_HV_A − 0.1
VDD_HV_A + 0.1
V
(VSS_HV
)
Analog input
voltage(5)
(3),(4)
VAINx
fADC1
tADC1_PU
SR
SR
SR
—
—
—
—
VSS_ADC1 − 0.1
VDD_ADC1 + 0.1
32 + 2ꢀ
V
MHz
µs
ADC_1 analog
frequency
8 + 2ꢀ
ADC_1 power up
delay
1.5
Sample time(6)
VDD=5.0 V
440
530
tADC1_S
CC
ns
Sample time(6)
VDD=3.3 V
—
Conversion time(7),
(8)
fADC1 = 32 MHz
2
2.1
3
VDD=5.0 V
Conversion time(7),
(6)
fADC 1= 30 MHz
fADC 1= 20 MHz
fADC1 = 15 MHz
VDD =5.0 V
tADC1_C
CC
Conversion time(7),
(6)
µs
VDD=3.3 V
Conversion time(7),
(6)
3.01
VDD =3.3 V
ADC_1 input
CS
CC sampling
capacitance
—
—
5
pF
ADC_1 input pin
capacitance 1
CP1
CP2
CP3
CC
CC
CC
3
1
pF
pF
pF
ADC_1 input pin
capacitance 2
—
—
ADC_1 input pin
capacitance 3
1.5
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Electrical Characteristics
Table 44. Conversion characteristics (12-bit ADC_1) (continued)
Value
Symbol
Parameter
Conditions(1)
Unit
Min
Typ
Max
Internal resistance
of analog source
RSW1
RSW2
RAD
CC
CC
CC
—
—
—
1
kΩ
kΩ
kΩ
Internal resistance
of analog source
2
0.3
5
Internal resistance
of analog source
Current
VDD = 3.3
V 10ꢀ
−5
−5
—
—
injection
on one
ADC_1
input,
Input current
Injection
IINJ
SR
mA
VDD = 5.0
V
different
from the
converted
one
5
10ꢀ
Absolute Integral
INLP
INLS
DNL
CC non-linearity-
Precise channels
No overload
No overload
No overload
1
3
5
1
LSB
LSB
LSB
Absolute Integral
CC non-linearity-
Standard channels
1.5
0.5
Absolute
CC Differential non-
linearity
Absolute Offset
error
OFS
GNE
CC
—
—
2
2
LSB
LSB
Absolute Gain
error
CC
Total Unadjusted
Error for precise
channels, input
only pins
Without current
injection
TUEP(9)
TUES(9)
CC
−6
−8
6
8
With current injection
Total Unadjusted
CC Error for standard
channel
Without current
injection
−10
−12
10
12
LSB
LSB
With current injection
1. VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified.
2. Analog and digital VSS_HV must be common (to be tied together externally).
3. PA3, PA7, PA10, PA11 and PE12 ADC_1 channels are coming from VDD_HV_B domain hence VDD_HV_ADC1 should be
within 100 mV of VDD_HV_B when these channels are used for ADC_1.
4. VDD_HV_ADC1 can operate at 5V condition while VDD_HV_B can operate at 3.3V provided that ADC_1 channels coming
from VDD_HV_B domain are limited in max swing as VDD_HV_B
.
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5. VAINx may exceed VSS_ADC1 and VDD_ADC1 limits, remaining on absolute maximum ratings, but the results of the
conversion will be clamped respectively to 0x000 or 0xFFF.
6. During the sample time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tADC1_S. After the end of
the sample time tADC1_S, changes of the analog input voltage have no effect on the conversion result. Values for the
sample clock tADC1_S depend on programming.
7. Conversion time = Bit evaluation time + Sampling time + 1 Clock cycle delay.
8. Refer to ADC conversion table for detailed calculations.
9. Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a
combination of Offset, Gain and Integral Linearity errors.
4.18
Fast Ethernet Controller
MII signals use CMOS signal levels compatible with devices operating at 3.3 V. Signals are
not TTL compatible. They follow the CMOS electrical characteristics.
4.18.1
MII Receive Signal Timing (RXD[3:0], RX_DV, RX_ER, and RX_CLK)
The receiver functions correctly up to a RX_CLK maximum frequency of 25 MHz +1ꢀ.
There is no minimum frequency requirement. In addition, the system clock frequency must
exceed four times the RX_CLK frequency in 2:1 mode and two times the RX_CLK frequency
in 1:1 mode.
Table 45. MII Receive Signal Timing
Spec
Characteristic
Min
Max
Unit
RXD[3:0], RX_DV, RX_ER to
RX_CLK setup
M1
5
—
ns
RX_CLK to RXD[3:0], RX_DV,
RX_ER hold
M2
5
—
ns
M3
M4
RX_CLK pulse width high
RX_CLK pulse width low
35ꢀ
35ꢀ
65ꢀ
65ꢀ
RX_CLK period
RX_CLK period
Figure 21. MII receive signal timing diagram
M3
RX_CLK (input)
M4
RXD[3:0] (inputs)
RX_DV
RX_ER
M1
M2
4.18.2
MII Transmit Signal Timing (TXD[3:0], TX_EN, TX_ER, TX_CLK)
The transmitter functions correctly up to a TX_CLK maximum frequency of 25 MHz +1ꢀ.
There is no minimum frequency requirement. In addition, the system clock frequency must
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Electrical Characteristics
exceed four times the TX_CLK frequency in 2:1 mode and two times the TX_CLK frequency
in 1:1 mode.
The transmit outputs (TXD[3:0], TX_EN, TX_ER) can be programmed to transition from
either the rising or falling edge of TX_CLK, and the timing is the same in either case. This
options allows the use of non-compliant MII PHYs.
Refer to the Fast Ethernet Controller (FEC) chapter of the SPC564B74 and SPC56EC74
Reference Manual for details of this option and how to enable it.
(1)
Table 46. MII transmit signal timing
Spec
Characteristic
Min
Max
Unit
TX_CLK to TXD[3:0],
TX_EN, TX_ER invalid
M5
5
—
ns
TX_CLK to TXD[3:0],
TX_EN, TX_ER valid
M6
—
25
ns
M7
M8
TX_CLK pulse width high
TX_CLK pulse width low
35ꢀ
35ꢀ
65ꢀ
65ꢀ
TX_CLK period
TX_CLK period
1. Output pads configured with SRE = 0b11.
Figure 22. MII transmit signal timing diagram
M7
TX_CLK (input)
M5
M8
TXD[3:0] (outputs)
TX_EN
TX_ER
M6
4.18.3
MII Async Inputs Signal Timing (CRS and COL)
(1)
Table 47. MII Async Inputs Signal Timing
Spec
Characteristic
Min
Max
Unit
M9
CRS, COL minimum pulse width
1.5
—
TX_CLK period
1. Output pads configured with SRE = 0b11.
Figure 23. MII async inputs timing diagram
CRS, COL
M9
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Electrical Characteristics
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4.18.4
MII Serial Management Channel Timing (MDIO and MDC)
The FEC functions correctly with a maximum MDC frequency of 2.5 MHz.
(1)
Table 48. MII serial management channel timing
Spec
Characteristic
Min
Max
Unit
MDC falling edge to
MDIO output invalid
(minimum
M10
0
—
ns
propagation delay)
MDC falling edge to
MDIO output valid
(max prop delay)
M11
—
25
ns
MDIO (input) to MDC
rising edge setup
M12
M13
28
0
—
—
ns
ns
MDIO (input) to MDC
rising edge hold
MDC pulse width
high
M14
M15
40ꢀ
40ꢀ
60ꢀ
60ꢀ
MDC period
MDC period
MDC pulse width low
1. Output pads configured with SRE = 0b11.
Figure 24. MII serial management channel timing diagram
M14
M15
MDC (output)
MDIO (output)
M10
M11
MDIO (input)
M12
M13
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Electrical Characteristics
4.19
On-chip peripherals
4.19.1
Current consumption
(1)
Table 49. On-chip peripherals current consumption
Value(2)
Typ
fperiph + 84.73
Symbol
C
Parameter
Conditions
Unit
Min
7.652
Max
500
Kbps
Total (static +
dynamic)
×
consumption:
CAN
(FlexCAN)
IDD_HV_A(CAN) CC D supply
current on
FlexCAN in loop-
back mode
XTAL@8 MHz used
as CAN engine clock
source
125
Kbps
8.0743
×
fperiph + 26.757
VDD_HV_A
Message sending
period is 580 µs
Static consumption:
eMIOS channel OFF
Global prescaler enabled
28.7 × fperiph
eMIOS
supply
current on
VDD_HV_A
IDD_HV_A(eMIOS) CC
D
D
Dynamic consumption:
µA
3
It does not change varying
the frequency (0.003 mA)
Total (static + dynamic)
consumption:
SCI(LINFlex)
supply
current on
VDD_HV_A
IDD_HV_A(SCI) CC
4.7804 × fperiph + 30.946
LIN mode
Baudrate: 20 Kbps
Ballast static consumption
(only clocked)
1
SPI (DSPI)
supply
current on
VDD_HV_A
Ballast dynamic consumption
(continuous communication):
IDD_HV_A(SPI) CC
D
Baudrate: 2 Mbit
Trasmission every 8 µs
Frame: 16 bits
16.3
× fperiph
Ballast static
consumption (no
conversion)
VDD
5.5 V
=
0.0409
0.0049
× fperiph
ADC supply
IDD_HV_A(ADC) CC D current on
VDD_HV_A
mA
Ballast dynamic
consumption
(continuous
VDD
5.5 V
=
×
fperiph
conversion)
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Electrical Characteristics
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(1)
Table 49. On-chip peripherals current consumption (continued)
Value(2)
Symbol
C
Parameter
Conditions
Unit
Min
Typ
Max
Analog static
consumption (no
conversion)
—
200
—
µA
mA
µA
ADC_0
supply
current on
VDD_HV_ADC0
VDD
5.5 V
=
IDD_HV_ADC0 CC
D
Analog dynamic
consumption
—
4
—
(continuous
conversion)
Analog static
consumption (no
conversion)
VDD
5.5 V
=
300
× fperiph
ADC_1
supply
current on
VDD_HV_ADC1
IDD_HV_ADC1 CC
D
Analog dynamic
consumption
(continuous
VDD
5.5 V
=
6
mA
conversion)
CFlash +
DFlash
IDD_HV(FLASH) CC D supply
current on
VDD
5.5 V
=
=
—
—
13.25
mA
VDD_HV_ADC
PLL supply
CC D current on
VDD_HV
VDD
5.5 V
IDD_HV(PLL)
0.0031 × fperiph
1. Operating conditions: TA = 25 °C, fperiph = 8 MHz to 120 MHz.
2. fperiph is in absolute value.
4.19.2
DSPI characteristics
Table 50. DSPI timing
Spec
Characteristic
Symbol
Unit
Min
Max
Refer
1
DSPI Cycle Time
tSCK
—
115
—
ns
ns
ns
note(1)
Internal delay between pad associated to SCK and pad
associated to CSn in master mode for CSn1->0
—
—
ΔtCSC
ΔtASC
—
Internal delay between pad associated to SCK and pad
associated to CSn in master mode for CSn1->1
15
2
3
4
CS to SCK Delay(2)
After SCK Delay(3)
SCK Duty Cycle
tCSC
tASC
tSDC
7
15
—
—
ns
ns
ns
0.4 × tSCK
0.6 × tSCK
Slave Setup Time
—
tSUSS
5
—
ns
(SS active to SCK setup time)
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Electrical Characteristics
Table 50. DSPI timing (continued)
Spec
Characteristic
Symbol
Unit
Min
Max
Slave Hold Time
—
5
tHSS
10
—
ns
ns
ns
(SS active to SCK hold time)
Slave Access Time
(SS active to SOUT valid)(4)
tA
—
—
42
25
Slave SOUT Disable Time
6
tDIS
(SS inactive to SOUT High-Z or invalid)
7
8
CSx to PCSS time
PCSS to PCSx time
tPCSC
tPASC
0
0
—
—
ns
ns
Data Setup Time for Inputs
Master (MTFE = 0)
36
5
—
—
—
—
ns
ns
ns
ns
9
Slave
tSUI
Master (MTFE = 1, CPHA = 0)(5)
36
36
Master (MTFE = 1, CPHA = 1)
Data Hold Time for Inputs
Master (MTFE = 0)
0
4
0
0
—
—
—
—
ns
ns
ns
ns
10
11
12
Slave
tHI
Master (MTFE = 1, CPHA = 0)(5)
Master (MTFE = 1, CPHA = 1)
Data Valid (after SCK edge)
Master (MTFE = 0)
—
—
—
—
12
37
12
12
ns
ns
ns
ns
Slave
tSUO
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
Data Hold Time for Outputs
Master (MTFE = 0)
0(6)
9.5
0(7)
0(8)
—
—
—
—
ns
ns
ns
ns
Slave
tHO
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
1. This value of this parameter is dependent upon the external device delays and the other parameters mentioned in this
table.
2. The maximum value is programmable in DSPI_CTARn [PSSCK] and DSPI_CTARn [CSSCK]. For SPC564B74 and
SPC56EC74, the spec value of tCSC will be attained only if TDSPI x PSSCK x CSSCK > ΔtCSC
.
3. The maximum value is programmable in DSPI_CTARn [PASC] and DSPI_CTARn [ASC]. For SPC564B74 and
SPC56EC74, the spec value of tASC will be attained only if TDSPI x PASC x ASC > ΔtASC.
4. The parameter value is obtained from tSUSS and tSUO for slave.
5. This number is calculated assuming the SMPL_PT bitfield in DSPI_MCR is set to 0b00.
6. For DSPI1, the Data Hold Time for Outputs in Master (MTFE = 0) is −2 ns.
7. For DSPI1, the Data Hold Time for Outputs in Master (MTFE = 1, CPHA = 0) is −2 n.
8. For DSPI1, the Data Hold Time for Outputs in Master (MTFE = 1, CPHA = 1) is −2 ns.
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Figure 25. DSPI classic SPI timing–master, CPHA = 0
2
3
CSx
1
4
SCK Output
(CPOL = 0)
4
SCK Output
(CPOL = 1)
10
9
Last Data
SIN
First Data
First Data
Data
Data
12
11
Last Data
SOUT
Note: Numbers shown reference Table 50.
Figure 26. DSPI classic SPI timing–master, CPHA = 1
CSx
SCK Output
(CPOL = 0)
10
SCK Output
(CPOL = 1)
9
Data
Data
First Data
Last Data
SIN
12
11
SOUT
Last Data
First Data
Note: Numbers shown reference Table 50.
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Electrical Characteristics
Figure 27. DSPI classic SPI timing–slave, CPHA = 0
3
2
SS
1
4
SCK Input
(CPOL = 0)
4
SCK Input
(CPOL = 1)
5
11
12
6
First Data
Data
Last Data
SOUT
SIN
9
10
Data
Last Data
First Data
Note: Numbers shown reference Table 50.
Figure 28. DSPI classic SPI timing–slave, CPHA = 1
SS
SCK Input
(CPOL = 0)
SCK Input
(CPOL = 1)
11
5
6
12
Last Data
Data
Data
SOUT
SIN
First Data
10
9
Last Data
First Data
Note: Numbers shown reference Table 50.
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Figure 29. DSPI modified transfer format timing–master, CPHA = 0
3
CSx
4
1
2
SCK Output
(CPOL = 0)
4
SCK Output
(CPOL = 1)
9
10
SIN
First Data
Last Data
Last Data
Data
12
11
SOUT
First Data
Data
Note: Numbers shown reference Table 50.
Figure 30. DSPI modified transfer format timing–master, CPHA = 1
CSx
SCK Output
(CPOL = 0)
SCK Output
(CPOL = 1)
10
9
SIN
Last Data
First Data
Data
12
Data
11
First Data
Last Data
SOUT
Note: Numbers shown reference Table 50.
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Electrical Characteristics
Figure 31. DSPI modified transfer format timing–slave, CPHA = 0
3
2
SS
1
SCK Input
(CPOL = 0)
4
4
SCK Input
(CPOL = 1)
12
11
6
5
First Data
9
Data
Data
Last Data
10
SOUT
SIN
Last Data
First Data
Note: Numbers shown reference Table 50.
Figure 32. DSPI modified transfer format timing–slave, CPHA = 1
SS
SCK Input
(CPOL = 0)
SCK Input
(CPOL = 1)
11
5
6
12
Last Data
First Data
10
Data
Data
SOUT
SIN
9
First Data
Last Data
Note: Numbers shown reference Table 50.
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Electrical Characteristics
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Figure 33. DSPI PCS strobe (PCSS) timing
8
7
PCSS
CSx
Note: Numbers shown reference Table 50.
4.19.3
Nexus characteristics
(1)
Table 51. Nexus debug port timing
Spec
Characteristic
Symbol
tMCYC
tMDC
Min
Max
Unit
MCKO Cycle
Time(2)
1
16.3
—
ns
MCKO Duty
Cycle
2
3
40
60
ꢀ
MCKO Low to
MDO, MSEO,
EVTO Data
Valid(3)
tMDOV
–0.1
0.25
—
tMCYC
4
5
EVTI Pulse Width
tEVTIPW
4.0
1
tTCYC
tMCYC
EVTO Pulse
Width
tEVTOPW
TCK Cycle
Time(4)
6
7
8
tTCYC
tTDC
tNTDIS, NTMSS
tNTDIH, NTMSH
tJOV
40
40
8
—
60
—
ns
ꢀ
TCK Duty Cycle
TDI, TMS Data
Setup Time
t
ns
TDI, TMS Data
Hold Time
9
t
5
0
—
ns
ns
TCK Low to TDO
Data Valid
10
25
1. JTAG specifications in this table apply when used for debug functionality. All Nexus timing relative to MCKO is measured
from 50ꢀ of MCKO and 50ꢀ of the respective signal. Nexus timing specified at VDDE = 4.0 – 5.5 V, TA = TL to TH, and
CL = 30 pF with SRC = 0b11.
2. MCKO can run up to 1/2 of full system frequency. It can also run at system frequency when it is <60 MHz.
3. MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.
4. The system clock frequency needs to be three times faster than the TCK frequency.
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Electrical Characteristics
Figure 34. Nexus output timing
1
2
MCKO
3
MDO
MSEO
EVTO
Output Data Valid
5
4
EVTI
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Electrical Characteristics
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Figure 35. Nexus TDI, TMS, TDO timing
6
7
TCK
8
9
TMS, TDI
10
TDO
4.19.4
JTAG characteristics
Table 52. JTAG characteristics
Value
Typ
No.
Symbol
C
Parameter
Unit
Min
Max
1
2
3
4
5
6
tJCYC
tTDIS
tTDIH
CC
CC
CC
CC
CC
CC
D
D
D
D
D
D
TCK cycle time
64
10
5
—
—
—
—
—
—
—
—
—
—
—
33
ns
ns
ns
ns
ns
ns
TDI setup time
TDI hold time
tTMSS
tTMSH
tTDOV
TMS setup time
TMS hold time
10
5
TCK low to TDO valid
—
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Electrical Characteristics
Table 52. JTAG characteristics (continued)
Value
No.
Symbol
C
Parameter
Unit
Min
Typ
Max
7
tTDOI
tTDC
CC
CC
D
D
D
TCK low to TDO invalid
TCK Duty Cycle
6
—
—
—
—
60
3
ns
ꢀ
—
—
40
—
tTCKRISE CC
TCK Rise and Fall Times
ns
Figure 36. Timing diagram - JTAG boundary scan
TCK
2/4
3/5
INPUT DATA VALID
DATA INPUTS
6
DATA OUTPUTS
OUTPUT DATA VALID
7
DATA OUTPUTS
Note: Numbers shown reference Table 52.
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Package characteristics
SPC564Bxx - SPC56ECxx
5
Package characteristics
5.1
ECOPACK®
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
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Package characteristics
5.2
Package mechanical data
5.2.1
LQFP176 package mechanical drawing
Figure 37. LQFP176 package mechanical drawing
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Package characteristics
SPC564Bxx - SPC56ECxx
inches(2)
(1)
Table 53. LQFP176 mechanical data
mm
Symbol
Min
Typ
Max
Min
Typ
Max
A
1.400
0.050
1.350
0.170
0.090
23.900
23.900
1.600
0.150
1.450
0.270
0.200
24.100
24.100
0.063
A1
0.002
0.053
0.007
0.004
0.941
0.941
A2
0.057
0.011
0.008
0.949
0.949
b
C
D
E
e
0.500
0.020
HD
25.900
25.900
0.450
26.100
26.100
0.750
1.020
1.020
0.018
1.028
1.028
0.030
HE
L(3)
L1
1.000
1.250
1.250
0.039
0.049
0.049
ZD
ZE
q
0 °
7 °
0 °
7 °
Tolerance
ccc
mm
inches
0.0031
0.080
1. Controlling dimension: millimeter
2. Values in inches are converted from mm and rounded to 4 decimal digits.
3. L dimension is measured at gauge plane at 0.25 mm above the seating plane
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Package characteristics
5.2.2
LQFP208 package mechanical drawing
Figure 38. LQFP208 mechanical drawing
Note: Exact shape of each corner is optional.
Table 54. LQFP208 mechanical data
mm
Typ
Ref
Min
Max
A
1.6
A1
0.05
0.15
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Package characteristics
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Table 54. LQFP208 mechanical data (continued)
mm
Typ
Ref
Min
Max
A2
b
1.35
0.17
0.09
29.8
27.8
1.40
0.22
1.45
0.27
0.2
c
D
30
28
30.2
28.2
D1
D3
e
25.5
0.5
30
E
29.8
27.8
30.2
28.2
E1
E3
L
28
25.5
0.6
1
0.45
0
0.75
L1
K
3.5
7.0
ccc
0.08
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Package characteristics
5.2.3
LBGA256 package mechanical drawing
Figure 39. LBGA256 mechanical drawing
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Package characteristics
SPC564Bxx - SPC56ECxx
Table 55. LBGA256 mechanical data
mm
Typ
Ref
Min
Max
A
A1
A2
A4
b
1.210
0.300
1.700
0.300
0.800
0.600
0.400
0.500
17.000
15.000
17.000
15.000
1.000
D
16.800
17.200
D1
E
16.800
17.200
E1
e
0.900
0.750
1.100
1.250
0.200
Z
1.000
ddd
Note:
The package is designed according to the Jedec standard No 95-1 Section 14 dedicated to
Ball Grid Array Package Design Guide.
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Ordering information
6
Ordering information
Figure 40. Ordering information scheme
Example code:
L7
Family Memory Package
SPC56
4
C
74
C
8
E
0
Y
Product identifier Core
Conditioning
Temperature CPU Frequency EEPROM Options
Y = Tray
X = Tape and Reel
0 = No option
E = Ethernet
C = CSE + Ethernet
0 = NO EEPROM
E = EEPROM
8 = 80 MHz
9 = 120 MHz
B = –40 to 105 °C
C = –40 to 125 °C
L7 = LQFP176
L8 = LQFP208
B3 = LBGA256
74 = 3 MB
70 = 2 MB
64 = 1.5 MB
B = Body
C = Gateway
4 = e200z4d
E = e200z4d + e200
z0h
SPC56 = Power
Architecture in
90 nm
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Abbreviations
SPC564Bxx - SPC56ECxx
Appendix A
Abbreviations
Table 56 lists abbreviations used but not defined elsewhere in this document.
Table 56. Abbreviations
Abbreviation
Meaning
CS
EVTO
MCKO
MDO
MSEO
MTFE
SCK
Chip select
Event out
Message clock out
Message data out
Message start/end out
Modified timing format enable
Serial communications clock
Serial data out
SOUT
TBD
To be defined
TCK
Test clock input
TDI
Test data input
TDO
Test data output
TMS
Test mode select
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Revision history
Revision history
Table summarizes revisions to this document
.
Revision history
Date
Revision
Changes
01-Jun-2010
1
Initial Release
– Editing and formatting updates throughout the document.
– Updated Voltage regulator capacitance connection figure.
– Added a new sub-section “VDD_BV Options”
– Program and erase specifications:
Updated Tdwprogram TYP to 22 us
Updated T128Kpperase Max to 5000 ms
Added tESUS parameter
– Added recommendation in the Voltage regulator electrical characteristics section.
– Added Crystal description table in Fast external crystal oscillator (4 to 140 MHz)
electrical characteristics section and corrected the cross-reference to the same.
– Added new sections - Pad types, System pins and functional ports
– Updated TYP numbers in the Flash program and erase specifications table
– Added a new table: Program and erase specifications (Data Flash)
– Flash read access timing table: Added Data flash memory numbers
– Flash power supply DC electrical characteristics table: Updated IDFREAD and
IDFMOD values for Data flash, Removed IDFLPW parameter
– Updated feature list.
– SPC564Bxx and SPC56ECxx family comparison table: Updated ADC channels
and added ADC footnotes.
17-Dec-2010
2
– SPC564Bxx and SPC56ECxx block diagram: Updated ADC channels and added
legends.
– SPC564Bxx and SPC56ECxx series block summary: Added new blocks.
– Functional Port Pin Descriptions table: Added OSC32k_XTAL and
OSC32k_EXTAL function at PB8 and PB9 port pins.
– Electrical Characteristics: Replaced VSS with VSS_HV throughout the section.
– Absolute maximum ratings, Recommended operating conditions (3.3 V) and
Recommended operating conditions (5.0 V) tables: VRC_CTRL min is updated to
"0".
– Recommended operating conditions (3.3 V) and Recommended operating
conditions (5.0 V) tables: Clarified VIN parameter, clarified footnote 2 in both
tables.
– LQFP thermal characteristics section: Added numbers for LQFP packages.
– Low voltage power domain electrical characteristics table: Clarified footnotes
based upon review comments.
– Code flash memory—Program and erase specifications: Updated tESRT to
20 ms.
– ADC electrical characteristics section: Replace ADC0 with ADC_0 and ADC1 with
ADC_1 throughout the document.
DSPI characteristics section: Replaced PCSx with CSx in all figures and tables.
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Revision history
SPC564Bxx - SPC56ECxx
Revision history (continued)
Date
Revision
Changes
– Replaced VIL min from –0.4 V to –0.3 V in the following tables:
- I/O input DC electrical characteristics
- Reset electrical characteristics
- Fast external crystal oscillator (4 to 40 MHz) electrical characteristics
– Updated Crystal oscillator and resonator connection scheme figure
– Specified NPN transistor as the recommended BCP68 transistor throughout the
document
– Code and Data flash memory—Program and erase specifications tables:
Renamed the parameter tESUS to Teslat
– Revised the footnotes in the “Functional port pin descriptions” table.
– In the “System pin descriptions” table, added a footnote to the A pads regarding
not using IBE.
For ports PB[12–15], changed ANX to ADC0_X.
– Revised the presentation of the ADC functions on the following ports:
PB[4–7]
PD[0–11]
– ADC conversion characteristics (10-bit ADC_0) table and Conversion
characteristics (12-bit ADC_1) table- Updated footnote 5 and 7 respectively for the
definition of the conversion time.
– Data flash memory—Program and erase specifications: Updated Twprogram to 500
µs and T16Kpperase to 500 µs. Corrected Teslat classsification from “C” to “D”.
– Code flash memory—Program and erase specifications: Corrected Teslat
classification from “C” to “D”.
– Flash Start-up time/Switch-off time: Changed TFLARSTEXIT classification from “C”
to “D”.
28-Apr-2011
3
– Functional port pin description: Added a footnote at the PB [9] port pin.
– Absolute maximum ratings table: Added footnote 1.
– Low voltage power domain electrical characteristics table: Updated IDDHALT,
IDDSTOP, IDDSTBY3, IDDSTDBY2, IDDSTDBY1.
– Updated commercial product code structure.
– Slow external crystal oscillator (32 kHz) electrical characteristics table: Updated
gmSXOSC, VSXOSC, ISXOSCBIAS and ISXOSC.
– FMPLL electrical characteristics table: Updated ΔtLTJIT.
– Fast internal RC oscillator (16 MHz) electrical characteristics table: Updated
TFIRCSU and IFIRCPWD.
– MII serial management channel timing table: Updated M12
– JTAG characteristics table: Updated tTDOV.
– Low voltage monitor electrical characteristics table: Updated VLVDHV3H,
VLVDHV3L, VLVDHV5H, VLVDHV5L.
– DSPI electricals table: Updated spec 1, 5, 6. Updated footnote 2 and 3. Added
ΔtCSC, ΔtASC, tSUSS, tHSS.
– IO consumption table: Updated all parameter values.
– DSPI electricals: Updated ΔtCSC max to 115 ns.
– Low voltage power domain electrical characteristics table: Added footnote 9.
– ADC electrical characteristics: Added 2 notes above 10-bit and 12-bit conversion
tables.
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Revision history
Revision history (continued)
Date
Revision
Changes
– Interchanged the denominator with numerator in Equation 11 of Input impedance
and ADC accuracy section
– Removed the note (All ADC conversion characteristics described in the table
below are applicable only for the precision channels. The data for semi-precision
and extended channels is awaited and same will be subsequently updated in later
revs.) in the ADC electrical characteristics section.
01-Dec-2011
4
– Table 49 (On-chip peripherals current consumption). Replaced IDD_HV_ADC
with IDD_HV_ADC0 and IDD_HV_ADC1 values as per ADC specs
– In Table 43, the minimum sample time of ADC0 changed to 500 at 32 MHz
– In Table 43, removed the entry for sample time at 30 MHz
– In Table 44, changed TUEX to TUES and INLX to INLS (Extended channels are
not supported by the device. So, changed to standard channel.)
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SPC564Bxx - SPC56ECxx
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32-bit Power Architecture® microcontroller for automotive SIL3/ASILD chassis and safety applications
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