SSL4120T/1,518_技术文档

SSL4120

Resonant power supply controller IC with PFC for LED

lighting

Rev. 2 — 1 November 2012

Product data sheet

1. General description

The SSL4120 integrates a Power Factor Corrector (PFC) controller and a controller for a

Half-Bridge resonant Converter (HBC) in a multi-chip IC. It provides the drive function for

the discrete MOSFET in an up-converter and for the two discrete power MOSFETs in a

resonant half-bridge configuration.

Efficient PFC operation is achieved by implementing functions for Quasi-Resonant (QR)

operation at high-power levels and QR with valley skipping at lower power levels.

OverCurrent Protection (OCP), OverVoltage Protection (OVP) and demagnetization

sensing ensure safe operation under all conditions

The HBC module is a high-voltage controller for a zero-voltage switching LLC resonant

converter. It contains a high-voltage level shift circuit and several protection circuits

including OCP, open-loop protection, capacitive mode protection and a general purpose

latched protection input.

The high-voltage chip is fabricated using a proprietary high-voltage Bipolar-CMOS-DMOS

power logic process enabling efficient direct start-up from the rectified universal mains

voltage. The low-voltage Silicon-On-Insulator (SOI) chip is used for accurate, high-speed

protection functions and control.

The SSL4120 controlled PFC circuit and resonant converter topology is very flexible. It

can be used for a broad range of applications over a wide mains voltage range.

Combining PFC and HBC controllers in a single IC makes the SSL4120 ideal for

controlling compact power supplies in lighting applications, such as LED drivers.

Using the SSL4120, highly efficient and reliable power supplies providing over 100 W can

be designed easily which use the minimum of external components.

Remark: Unless otherwise stated, all values are typical.

SSL4120

NXP Semiconductors

Resonant power supply controller IC with PFC for LED lighting

2. Features and benefits

2.1 General features

 Integrated PFC and HBC controllers

 Universal mains supply operation from 85 V to 305 V (AC)

 High level of integration resulting in a low external component count and a cost

effective design

 Enable input to enable only the PFC or both the PFC and HBC controllers

 On-chip high-voltage start-up source

 Stand-alone operation or IC supplied from external DC source

2.2 PFC controller features

 Boundary mode operation with on-time control

 Valley/zero-voltage switching for minimum switching losses

 Frequency limiting to reduce switching losses

 Accurate boost voltage regulation

 Burst mode switching with soft-start and soft-stop

2.3 HBC controller features

 Integrated high-voltage level shifter

 Adjustable minimum and maximum frequency

 Maximum 500 kHz half-bridge switching frequency

 Adaptive non-overlap time

 Burst mode switching

2.4 Protection features

 Safe restart mode for system fault conditions

 General latched protection input for output overvoltage protection or external

temperature protection

 Protection timer for time-out and restart

 Overtemperature protection

 Soft (re)start for both controllers

 Undervoltage protection for mains (brownout), boost, IC supply and output voltage

 Overcurrent regulation and protection for both controllers

 Accurate overvoltage protection for the boost voltage

 Capacitive mode protection for the HBC controller

3. Applications

The IC is used in all LED lighting applications that require very efficient, low Total

Harmonic Distortion (THD), high Power Factor (PF) and a universal mains input voltage.

The SSL4120 provides a cost-effective power supply solution between 25 W and 400 W.

SSL4120

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 1 November 2012

2 of 48

SSL4120

NXP Semiconductors

Resonant power supply controller IC with PFC for LED lighting

4. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

plastic small outline package; 24 leads; body width 7.5 mm

Version

SSL4120T

SO24

SOT137-1

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Fig 1. SSL4120 block diagram

SSL4120

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 1 November 2012

3 of 48

SSL4120

NXP Semiconductors

Resonant power supply controller IC with PFC for LED lighting

6. Pinning information

6.1 Pinning

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Fig 2. SSL4120T pin configuration

6.2 Pin description

Table 2.

Symbol

Pin description

Pin Description

COMPPFC

SNSMAINS

SNSAUXPFC

SNSCURPFC

SNSOUT

1

PFC controller frequency compensation.

Externally connected to filter

2

3

4

5

mains voltage sense input.

Externally connected to resistive divided mains voltage

PFC demagnetization timing sense input.

Externally connected to the PFC auxiliary winding

PFC controller sense input for momentary current and soft-start.

Externally connected to current sense resistor and soft-start filter

• HBC output voltage sense input

• HBC controller or PFC and HBC controllers sense input for burst

mode

Externally connected to the HBC transformer auxiliary winding

SUPIC

6

SUPIC input low-voltage supply and output of internal HV start-up source.

Externally connected to HBC transformer auxiliary winding or to the

external DC supply

GATEPFC

PGND

7

8

9

PFC MOSFET gate driver output

power ground. HBC low-side and PFC driver reference (ground)

regulated SUPREG IC supply; internal regulator output; input drivers.

Externally connected to SUPREG buffer capacitor

HBC low-side MOSFET gate driver output

SUPREG

GATELS

n.c.

10

11

not connected; high-voltage spacer.

SSL4120

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 1 November 2012

4 of 48

SSL4120

NXP Semiconductors

Resonant power supply controller IC with PFC for LED lighting

Table 2.

Pin description …continued

Symbol

Description

SUPHV

12

internal HV start-up source high-voltage supply input.

Externally connected to the boost voltage

HBC high-side MOSFET gate driver output

high-side driver supply input.

GATEHS

SUPHS

13

14

Externally connected to the bootstrap capacitor

reference for high-side driver and input for half-bridge slope detection.

HB

15

Externally connected to half-bridge node HB between HBC MOSFETs (see

Figure 19)

n.c.

16

not connected; high-voltage spacer

SNSCURHBC 17

momentary HBC current sense input.

Externally connected to the resonant current sense resistor

signal ground and IC reference (ground).

HBC minimum frequency setting.

SGND

CFMIN

18

19

Externally connected to the capacitor

RFMAX

20

21

22

HBC maximum frequency setting.

Externally connected to the resistor

SNSFB

output voltage regulation feedback sense input.

Externally connected to opto-coupler

SSHBC/EN

• HBC soft-start timing input

• IC enable input. Enables PFC only or both PFC and HBC controllers.

Externally connected to soft-start capacitor and enable pull-down signal

protection timer setting for time-out and restart.

Externally connected to resistor and capacitor

sense input for boost voltage regulation.

Externally connected to resistive divided V_boost

RCPROT

23

24

SNSBOOST

SSL4120

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 1 November 2012

5 of 48

SSL4120

NXP Semiconductors

Resonant power supply controller IC with PFC for LED lighting

7. Functional description

7.1 Overview of IC modules

The functionality of the SSL4120 is grouped as follows:

• Supply module:

Supply management for the IC. Includes the restart and (latched) shut-down states

• Protection and restart timer:

An externally adjustable timer used for delayed protection and restart timing

• Enable input:

Control input for enabling and disabling the controllers. When disabled has very low

current consumption

• PFC controller:

Controls and protects the power factor converter. Generates a 400 V (DC) boost

voltage V_boostfrom the rectified AC mains input with a high PF

• HBC controller:

Controls and protects the resonant converter. generates a regulated, mains isolated

output voltage from the 400 V (DC) boost voltage V_boost

Figure 1 shows the block diagram of the SSL4120. A typical application is shown in

Figure 19.

SSL4120

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 1 November 2012

6 of 48

SSL4120

NXP Semiconductors

Resonant power supply controller IC with PFC for LED lighting

7.2 Power supply

The SSL4120 contains several supply-related pins SUPIC, SUPREG, SUPHS and

SUPHV. These pins are described in Section 7.2.1 to Section 7.2.4

7.2.1 Low-voltage supply input (SUPIC pin)

The SUPIC pin is the main low-voltage supply input to the IC. All internal circuits are

supplied from this pin directly or indirectly using the SUPREG pin. The high-voltage circuit

however, is not supplied from the SUPIC pin. The SUPIC pin is connected externally to a

buffer capacitor C_SUPIC. This buffer capacitor can be charged in several ways:

• from the internal high voltage start-up source

• from the HBC transformer auxiliary winding

• from the switching half-bridge node capacitive supply

• from an external DC supply, for example, a standby supply

The IC starts operating when voltage on the SUPIC pin reaches the start level, provided

the voltage on the SUPREG pin has also reached the start level. The start level depends

on the condition of the SUPHV pin:

• High voltage present on the SUPHV pin (V_SUPHV> V_det(SUPHV)).

In a stand-alone application this is the case because C_SUPICis initially charged from

the HV start-up source. The start level is V_{start(hvd)(SUPIC)}= 22 V. The wide difference

between the start and stop (V_uvp(SUPIC)) levels allows sufficient energy to be drawn

from the SUPIC buffer capacitor until the output voltage stabilizes.

• Not connected or voltage not present on the SUPHV pin (V_SUPHV< V_det(SUPHV)).

When the SSL4120 is supplied from an external DC source, this is the case. The start

level is V_{start(nohvd)(SUPIC)}= 17 V. The IC is supplied from the DC supply during

start-up. To minimize power dissipation, the DC supply to the SUPIC pin must be

higher than but close to V_uvp(SUPIC)= 15 V.

The IC stops operating when V_SUPIC< V_uvp(SUPIC). This voltage is the SUPIC pin

UnderVoltage Protection (UVP) voltage (UVP-SUPIC; see Section 7.9). The PFC

controller stops switching immediately but the HBC controller continues operating until the

low-side MOSFET is active.

The current consumption depends on the state of the IC. The SSL4120 operating states

are described in Section 7.3.

• Disabled IC state

When the IC is disabled using the SSHBC/EN pin, the current consumption is very

low (I_dism(SUPIC)).

• SUPIC charge, SUPREG charge, Thermal hold, Restart and Protection shut-down

states

Only a small section of the IC is active while C_SUPICand C_SUPREGare charging during

a restart sequence before start-up or during shut-down after a protection function has

been activated. The PFC and HBC controllers are disabled. Current consumption is

limited to I_protm(SUPIC)

.

SSL4120

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 1 November 2012

7 of 48

SSL4120

NXP Semiconductors

Resonant power supply controller IC with PFC for LED lighting

• Boost charge state

The PFC controller is switching; the HBC controller is off. The current from the

high-voltage start-up source is large enough to supply the SUPIC pin (current

consumption < I_{ch(nom)(SUPIC)}).

• Operational supply state

Both the PFC and HBC controllers are switching. Current consumption is I_oper(SUPIC)

When the HBC controller is enabled, the switching frequency is initially high and the

.

HBC MOSFET drivers current consumption is dominant. The stored energy in C_SUPIC

supplies the initial SUPIC current before the SUPIC supply source takes over.

The SUPIC pin has a low short-circuit detection voltage (V_scp(SUPIC)= 0.65 V). The current

dissipated in the HV start-up source is limited while V_SUPIC< V_scp(SUPIC)(see

Section 7.2.4).

7.2.2 Regulated supply (SUPREG pin)

The voltage range on the SUPIC pin exceeds that of the external MOSFETs gate

voltages. The SSL4120 contains an integrated series stabilizer for this reason. The series

stabilizer creates an accurate regulated voltage (V_reg(SUPREG)= 10.9 V) at the buffer

capacitor C_SUPREG. This stabilized voltage is used to:

• supply the internal PFC driver

Remark: The internal SUPIC pin supply provides most of the external MOSFET charge

current.

• supply the internal low-side HBC driver

• supply the internal high-side driver using external components

• as a reference voltage for optional external circuits

The SUPREG series stabilizer is enabled after C_SUPIChas been fully charged. Enabling

the stabilizer after charging C_SUPICensures any optional external circuitry connected to

SUPREG does not dissipate any of the start-up current.

To ensure that the external MOSFETs receive sufficient gate drive current, the voltage on

the SUPREG pin must reach V_{start(SUPREG)}. In addition, the voltage on the SUPIC pin must

reach the start level. The IC starts operating when both voltages reach their start levels.

SUPREG is provided with undervoltage protection (UVP-SUPREG; see Section 7.9).

When V_SUPREG< V_uvp(SUPREG)= 10.3 V, two events are triggered:

• The IC stops operating to prevent unreliable switching because the gate driver voltage

is too low. The PFC controller stops switching immediately but the HBC controller

continues until the low-side stroke is active.

• The maximum current from the internal SUPREG series stabilizer is reduced to

I_{ch(red)(SUPREG)}= 5.4 mA. This feature reduces the dissipation in the series stabilizer

when an overload occurs at the SUPREG pin while the SUPIC pin is supplied from an

external DC supply.

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7.2.3 High-side driver floating supply (SUPHS pin)

The high-side driver is supplied by an external bootstrap buffer capacitor, C_SUPHS. The

bootstrap capacitor is connected between the high-side reference the HB pin and the

high-side driver supply input the SUPHS pin. C_SUPHSis charged from the SUPREG pin

using an external diode D_SUPHS

.

Careful selection of the appropriate diode minimizes the voltage drop between SUPREG

and SUPHS, especially when large MOSFETs and high switching frequencies are used.

7.2.4 High-voltage supply input (SUPHV pin)

In a stand-alone power supply application, the SUPHV pin is connected to V_boost. C_SUPIC

and C_SUPREGare charged using the HV start-up source (which delivers a constant current

from SUPHV to SUPIC) using this pin.

Short-circuit protection on the SUPIC pin (SCP-SUPIC; see Section 7.9) limits dissipation

in the HV start-up source when SUPIC is shorted to ground. SCP-SUPIC limits the current

on SUPHV to I_red(SUPHV)when the voltage on SUPIC is less than V_scp(SUPIC)

.

Under normal operating conditions, the SUPIC pin voltage exceeds V_scp(SUPIC)very

quickly after start-up and the HV start-up source switches to I_nom(SUPHV)

.

During start-up and restart, the HV start-up source charges C_SUPICand regulates the

voltage on SUPIC using hysteretic control. The start level has a small amount of

hysteresis V_{start(hys)(SUPIC)}. The HV start-up source switches-off when V_SUPICexceeds the

start level V_{start(hvd)(SUPIC)}. Current consumption through the SUPHV pin is low

(I_tko(SUPHV)).

Once start-up is complete and the HBC controller is operating, SUPIC is supplied from the

HBC transformer auxiliary winding. In operational state, the HV start-up source is

disabled.

7.3 Flow diagram

The operation of the SSL4120 can be divided into a number of states (see Figure 3). The

abbreviations used in Figure 3 are explained in Table 8.

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Resonant power supply controller IC with PFC for LED lighting

START

UVP supplies = yes

enable PFC = no

NO SUPPLY

-All off

UVP supplies = no

DISABLED lC

-Only "Enable lC" detection active

Enable PFC = yes

Explanation flow diagram symbols

STATE NAME

THERMAL HOLD

-Minimum functionality active

OTP = no

-action 1

-action 2

-...

Disabled items are not mentioned

exit condition 1 exit condition 2

SUPIC CHARGE

reached

-HV start-up source on

UVP SUPIC = no

OTP = yes

exit condition

next state can be entered

from any state when exit

condition is true

SUPREG CHARGE

-HV start-up source on

-Series stabilizer on

UVP SUPREG = no

UVP SUPIC= yes

OTP = yes

BOOST CHARGE

-HV start-up source on

-Series stabilizer on

-PFC on

1

*

Protection timer is activated by:

-UVP output

-OLP HBC

-OCR HBC

-HFP

UVP boost = no &

Enable lC = yes

SCP boost = yes

UVP SUPREG = yes

UVP SUPIC = yes

OTP = yes

OPERATIONAL SUPPLY

-Series stabilizer on

-PFC on

-HBC on

Protection timer

passed *

UVP boost = yes

or Enable IC = no

SCP boost = yes

OVP output =yes

UVP SUPREG = yes

UVP SUPIC = yes

OTP = yes

1

RESTART

PROTECTION SHUTDOWN

-HV start-up source on

-Restart timer on

Mains reset = yes

Restart time passed

014aaa851

Fig 3. SSL4120 flow diagram

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Table 3.

Operating states

State

Description

No supply

Supply voltages on the SUPIC and SUPHV pins are too low to provide

any functionality. Undervoltage protection (UVP supplies; see

Section 7.9) is active when V_SUPHV< V_rst(SUPHV)and

V_SUPIC< V_rst(SUPIC). The IC is reset.

Disabled IC

The IC is disabled because the SSHBC/EN pin is LOW.

Thermal hold

Activated when OTP is active. The IC is not operating. The PFC and

HBC controllers are disabled and C_SUPICand C_SUPREGare not

charged.

SUPIC charge

The HV start-up source charges the IC supply capacitor (C_SUPIC).

C_SUPREGis not charged.

SUPREG charge

The series regulator charges the stabilized supply capacitor

(C_SUPREG).

Boost charge

The operational PFC builds up V_boost.

Operational supply

The output voltage is generated. Both the PFC and HBC controllers

are fully operational.

Restart

Activated when a protection function is triggered. The restart timer is

activated. During this time, both the PFC/HBC controllers are disabled

and C_SUPREGis not charged. C_SUPICis charged.

Protection shut-down

Activated when a protection function is triggered. The IC is not

operational. The PFC and HBC controllers are disabled and

C_SUPIC/C_SUPREGare not charged.

7.4 Enable input (SSHBC/EN pin)

The power supply application is disabled by pulling the SSHBC/EN pin LOW.

Figure 4 shows the internal functionality. When a voltage is present on the SUPHV pin or

on the SUPIC pin, a current I_pu(EN)= 42 A flows from the SSHBC/EN pin. If the pin is not

pulled down, the current increases the voltage up to V_pu(EN)= 3 V. Since the voltage is

above both V_en(PFC)(EN)= 1.2 V and V_en(IC)(EN)= 2.2 V, the IC is enabled.

The IC is disabled when the SSHBC/EN pin voltage is pulled down under V_en(PFC)(EN)and

V_en(IC)(EN)via an optocoupler driven from the HBC transformer secondary side (see

Figure 4). The PFC controller stops switching immediately but the HBC controller

continues switching until the low-side stroke is active. It is also possible to control the

voltage on the SSHBC/EN pin from another circuit on the secondary side via a diode. The

external pull-down current must be larger than the internal soft-start charge current

I_{ss(hf)(SSHBC)}

.

If the voltage on SSHBC/EN is pulled under V_en(IC)(EN), but not under V_en(PFC)(EN), only the

HBC is disabled. This feature is useful when another power converter is connected to the

PFC V_boost

.

The low-side power switch of the HBC is on when the HBC is disabled using the

SSHBC/EN pin.

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SSL4120

NXP Semiconductors

Resonant power supply controller IC with PFC for LED lighting

ꢋ95>ꢓꢆꢇꢅꢆAꢆ:Aꢁꢔ9

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Fig 4. Circuit configuration around the SSHBC/EN pin

7.5 IC protection

7.5.1 IC restart and shut-down

In addition to the protection functions influencing the PFC and HBC controller operation,

several protection functions are provided to disable both controllers. See the protection

overview in Section 7.9 for details on which protection functions trigger a restart or

protection shut-down.

• Restart

When the SSL4120 enters the Restart state, the PFC and HBC controllers are

switched off. After a period defined by the restart timer, the IC automatically restarts

following the normal start-up cycle.

• Protection shut-down

When the SSL4120 enters the Protection shut-down state, the PFC and HBC

controllers are switched off. The Protection shut-down state is latched, the IC does

not automatically start up again. It can be restarted by resetting the Protection

shut-down state in one of the following ways:

– lower V_SUPICand V_SUPHVbelow their respective reset levels, V_rst(SUPIC)and

V_rst(SUPHV)

– using a fast shut-down reset (see Section 7.5.3).

– using the enable pin (see Section 7.4)

• Thermal hold

In the Thermal hold state, the PFC and HBC controllers are switched off. The Thermal

hold state remains active until the IC junction temperature drops to approximately

10 C below T_otp(see Section 7.5.6).

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7.5.2 Protection and restart timer

The SSL4120 contains a programmable timer which can be used for timing several

protection functions. The timer can be used in two ways: as a protection timer and as a

restart timer. The timing of the timers is set independently using the external resistor R_prot

and capacitor C_protconnected to the RCPROT pin.

7.5.2.1 Protection timer

Certain error conditions are allowed to persist for a time period before protective action

must be taken. The protection timer defines the protection period (how long the error can

persist before the protection function is triggered). The protection functions that use the

protection timer are found in the protection overview in Section 7.9.

short

error

long

error

repetative

error

present

Error

none

I

ch(slow)(RCPROT)

I

RCPROT

0

V

u(RCPROT)

V

RCPROT

0

passed

Protection time

t

014aaa853

Fig 5. Operation of the protection timer

Figure 5 shows the operation of the protection timer. When an error condition occurs, a

fixed current I_{ch(slow)(RCPROT)}= 100 A flows from the RCPROT pin and charges C_prot

_protcauses the voltage to increase exponentially. The protection time elapses when the

.

R

RCPROT voltage reaches the upper switching level. When the protection time has

elapsed, the appropriate protective action is taken and C_protis discharged.

If the error condition is removed before the voltage on the RCPROT pin reaches

V_u(RCPROT), C_protis discharged using R_protand no action is taken.

The RCPROT voltage can be forced > V_u(RCPROT)by an external circuit to trigger a restart.

7.5.2.2 Restart timer

The IC must be disabled for a time period on certain error conditions. Particularly when

the error condition can cause components to overheat. In such cases, the IC is disabled to

allow the power supply to cool down. It automatically restarts. The restart timer

determines the restart time. The restart timer is active in the Restart state. The protection

functions which trigger a restart are found in the protection functions overview in

Section 7.9.

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Resonant power supply controller IC with PFC for LED lighting

yes

Restart request

no

V

u(RCPROT)

V

RCPROT

V

l(RCPROT)

0

passed

Restart time

t

014aaa854

Fig 6. Operation of the restart timer

Figure 6 shows the operation of the restart timer. Normally C_protis discharged to 0 V.

When a restart is requested, C_protis quickly charged to the upper switching level

V

R

V

_u(RCPROT). Then the RCPROT pin becomes high ohmic and C_protdischarges through

_prot. The restart time has elapsed when V_RCPROTreaches the lower switching level

_l(RCPROT)= 0.5 V. The IC restarts and C_protis discharged.

7.5.3 Fast shut-down reset (SNSMAINS pin)

The latched Protection shut-down state is reset when V_SUPICand V_SUPHVdrop below their

respective reset levels, V_rst(SUPIC)and V_rst(SUPHV). Typically, the PFC boost capacitor

C

_boost, must discharge before V_SUPICand V_SUPHVdrop below their reset levels.

Discharging C_boostcan take a long time.

Fast shut-down reset causes a faster reset. When the mains supply is interrupted, the

voltage on the SNSMAINS pin falls. When V_SNSMAINSfalls below V_{rst(SNSMAINS)}and then

increases again by a hysteresis value, the IC leaves the Protection shut-down state. The

boost capacitor C_boostdoes not require discharging to trigger a new start-up.

The Protection shutdown state is also exited by pulling down the enable input (the

SSHBC/EN pin).

7.5.4 Output overvoltage protection (SNSOUT pin)

The SSL4120 outputs are provided with overvoltage protection (OVP output; see

Section 7.9). The output voltage is measured using the resonant transformer auxiliary

winding. The voltage is sensed on the SNSOUT pin using an external rectifier and

resistive divider. An overvoltage is detected when the SNSOUT voltage exceeds

V

_ovp(SNSOUT). When an overvoltage is detected, the SSL4120 enters the Protection

shut-down state.

Additional external protection circuits, such as an external OTP circuit, can be connected

to this pin. Connect them to the SNSOUT pin using a diode to ensure that an error

condition triggers an OVP event.

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7.5.5 Output undervoltage protection (SNSOUT pin)

If an error condition causes an output voltage drop when the SSL4120 is supplied from

the HBC transformer auxiliary winding, a SUPIC UVP event is automatically triggered.

If an error condition causes a decrease in the output voltage when the IC is supplied from

a separate DC source (for example, a standby supply), the IC does not automatically stop

switching. To counter this, the IC outputs are provided with undervoltage protection (UVP

output; see Section 7.9).

If V_SNSOUT< V_uvp(SNSOUT)= 2.3 V, a UVP output event restarts the IC.

During start-up, the output voltage is less than V_uvp(SNSOUT)for a time. This voltage drop is

not considered as an error condition if it does not last longer than expected. The

protection timer is started when V_SNSOUT< V_uvp(SNSOUT)for this reason. The Restart state

is activated if the UVP output event is still active when the protection time has expired.

7.5.6 OverTemperature Protection (OTP)

Accurate internal overtemperature protection is provided in the SSL4120. When the

junction temperature exceeds the overtemperature protection activation temperature,

T_otp= 150 C), the IC enters the Thermal hold state. The SSL4120 exits the Thermal hold

state when the temperature falls again to approximately T_otp 10 C.

7.6 Burst mode operation (SNSOUT pin)

The HBC and PFC controllers can be operated in burst mode. In burst mode, the

controllers are on for a period, then off for a period. Burst mode operation increases

efficiency under low-load conditions.

A low-load condition can be detected using a simple external circuit that uses the

information from the feedback loop or from the average primary current. The detection

circuit can pull down the SNSOUT pin to pause the SSL4120 operation for a burst-off

time. Only the HBC controller or both controllers can be paused during the burst-off time:

• Burst-off level for HBC, V_burst(HBC)= 1 V

When V_SNSOUT< V_burst(HBC), the HBC controller is suspended. Both the high-side and

the low-side power switches are off. The PFC continues to operate normally. When

V

_SNSOUT> V_burst(HBC)again, the HBC controller resumes normal operation, without

executing a soft-start sequence.

• Burst-off level for PFC, V_burst(PFC)= 0.4 V

When V_SNSOUT< V_burst(PFC), operation of the PFC controller is also suspended (the

HBC is already paused). When V_SNSOUT> V_burst(PFC)again, the PFC controller

resumes normal operation using a PFC soft-start (see Section 7.7.6).

To ensure that burst mode is not activated before the output voltage becomes valid,

current from the SNSOUT pin (100 A) holds V_SNSOUTat V_pu(SNSOUT). This level is above

both burst levels. The resistance between the SNSOUT pin and ground must be > 20 k.

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Resonant power supply controller IC with PFC for LED lighting

7.7 PFC controller

The PFC controller converts the rectified universal mains voltage into an accurately

regulated V_boostof 400 V (DC) or 450 V (DC). It operates in Quasi-Resonant (QR) or

Discontinuous Conduction Mode (DCM) and is controlled using an on-time control

system. The resulting mains harmonic current emissions of a typical application can meet

the Class-C MHR requirements for lighting applications.

The PFC controller uses valley switching to minimize losses. A primary stroke is only

started once the previous secondary stroke ends and the voltage across the PFC

MOSFET reaches a minimum value.

7.7.1 PFC gate driver (GATEPFC pin)

The circuit driving the gate of the power MOSFET has a high current sourcing capability

I_{source(GATEPFC)}of 500 mA. It also has a high current sink capability I_{sink(GATEPFC)}of 1.2 A.

The source and sink capabilities enable fast power MOSFET switch-on and switch-off to

ensure efficient operation. The driver is supplied from the regulated SUPREG supply.

7.7.2 PFC on-time control

The PFC operates under on-time control. The following determine the PFC MOSFET

on-time:

• the error amplifier and the loop compensation using the COMPPFC pin voltage

– At V_{ton(COMPPFC)zero}= 3.5 V, the on-time is reduced to zero.

– At V_{ton(COMPPFC)max}= 1.25 V, the on-time is at a maximum

• Mains compensation using the SNSMAINS pin voltage

The on-time must be modulated with the mains voltage to reach the Class-C MHR

requirements. In the application, this is achieved when a modulation current is injected

into the COMPPFC network using a capacitor which connects to the mains voltage, see

Figure 19.

7.7.2.1 PFC error amplifier (COMPPFC and SNSBOOST pins)

V_boostis divided using a high-ohmic resistive divider. It is supplied to the SNSBOOST pin.

The transconductance error amplifier, which compares the SNSBOOST voltage with an

accurate trimmed reference voltage V_{reg(SNSBOOST)}, is connected to this pin. The external

loop compensation network on the COMPPFC pin filters the output current. In a typical

application, a resistor and two capacitors set the regulation loop bandwidth.

The COMPPFC voltage is clamped at a maximum of V_{clamp(COMPPFC)}. This clamp avoids a

long recovery time if V_boostrises above the regulation level for a period.

7.7.2.2 PFC mains compensation (SNSMAINS pin)

The mathematical equation for the transfer function of a power factor corrector contains

the square of the mains input voltage. In a typical application, this results in a low

bandwidth for low mains input voltages. At high mains input voltages, the MHR

requirements are hard to meet.

The SSL4120 contains a correction circuit to compensate for this effect. The average

mains voltage is measured using the SNSMAINS pin and this information is supplied to an

internal compensation circuit.

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Figure 7 illustrates the relationship between V_SNSMAINS, V_COMPPFCand the on-time. The

compensation makes it is possible to keep the regulation loop bandwidth constant over

the full mains input range. This feature provides a fast transient response on load steps,

while still meeting the Class-C MHR requirements.

t

on(max)(lowmains)

on-time

V

= 0.97 V

SNSMAINS

V

= 3.3 V

SNSMAINS

t

on(max)(highmains)

0

V

COMPPFC

014aaa855

ton(COMPPFC)max

ton(COMPPFC)zero

Fig 7. Relationship between on-time, SNSMAINS voltage and COMPPFC voltage

7.7.3 PFC demagnetization sensing (SNSAUXPFC pin)

The voltage on the SNSAUXPFC pin is used to detect transformer demagnetization.

During the secondary stroke, the transformer is magnetized and current flows in the boost

output. During this time, V_SNSAUXPFC< V_{demag(SNSAUXPFC)}= 100 mV and the PFC

MOSFET remains switched off.

When the transformer becomes demagnetized, the current stops flowing to the boost

output V_SNSAUXPFC> V_{demag(SNSAUXPFC)}and valley detection is started. The MOSFET

remains switched off.

To ensure that switching continues under all circumstances, the MOSFET is forced to

switch on if the magnetizing of the transformer (V_SNSAUXPFC< V_{demag(SNSAUXPFC)}) is not

detected within t_to(mag)= 50 s after the GATEPFC pin goes LOW.

Connect a 5 k series resistor to this pin to protect the internal circuitry, against lightning

for example. Place the resistor close to the IC on the PCB to prevent incorrect switching

due to external disturbances.

7.7.4 PFC valley sensing (SNSAUXPFC pin)

If the voltage at the MOSFET drain is at its minimum (valley switching), the PFC MOSFET

is switched on for the next stroke. This action reduces switching losses and EMI

(see Figure 8).

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Resonant power supply controller IC with PFC for LED lighting

on

GATEPFC

off

V

boost

V

Rect

Dr(PFC)

0

V

/N

0

Rect

Aux(PFC)

V

demag(SNSAUXPFC)

(V

boost

- V

Rect

)/N

l

Tr(PFC)

0

demagnetized

Demagnetization

magnetized

Valley

(= top for detection)

t

014aaa856

Fig 8. Demagnetization and valley detection

The valley sensing block connected to the SNSAUXPFC pin detects the valleys. This

block measures the PFC transformer auxiliary winding voltage which is a reduced and

inverted copy of the MOSFET drain voltage. When a valley of the drain voltage (= top at

SNSAUXPFC voltage) is detected, the MOSFET is switched on.

If a top is not detected on the SNSAUXPFC pin (a valley at the drain) within t_to(vrec)= 4 s

after demagnetization is detected, the MOSFET is forced to switch on.

7.7.5 PFC frequency and off-time limiting

The switching frequency is limited to f_max(PFC)for transformer optimization and to minimize

switching losses. If the frequency for quasi-resonant operation > f_max(PFC), the system

switches to DCM. The PFC MOSFET is switched on when the drain-source voltage is at a

minimum (valley switching).

The minimum off-time is limited at t_off(PFC)minto ensure correct control of the PFC

MOSFET under all circumstances.

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7.7.6 PFC soft-start and soft-stop (SNSCURPFC pin)

The PFC controller features a soft-start function. The function slowly increases the

primary peak current during start-up. The soft-stop function slowly decreases the

transformer peak current before operations are stopped. These functions prevent

transformer rattle during start-up and burst mode operation.

Connecting a resistor R_ss(PFC)and capacitor C_ss(PFC)between the SNSCURPFC pin and

the current sense resistor R_cur(PFC)achieves this. During start-up, an internal current

source I_ch(ss)(PFC)charges the capacitor to V_SNSCURPFC= I_ch(ss)(PFC) R_ss(PFC)

.

The voltage is limited to the maximum PFC soft-start clamp voltage, V_clamp(ss)PFC. The

additional voltage across the charged capacitor reduces the peak current. After start-up,

the internal current source is switched-off, capacitor C_ss(PFC)discharges across R_ss(PFC)

and the peak current increases.

The start level and the time constant of the rising primary current can be adjusted

externally by changing the values of R_ss(PFC)and C_ss(PFC)

.

V

– I

 R



ssPFC

ocrPFC

chssPFC

I

=

---------------------------------------------------------------------------------------------

CurPFCpk

R

curPFC

 = R

 C

ssPFC

Switching on the internal current source I_ch(ss)(PFC)starts a soft-stop. I_ch(ss)(PFC)charges

_ss(PFC). The increasing capacitor voltage decreases the peak current. The charge current

C

flows when the voltage on the SNSCURPFC pin is less than the maximum PFC soft-start

voltage = 0.5 V. If V_SNSCURPFCexceeds the maximum PFC soft-start voltage, the soft-start

current source starts limiting the charge current. To determine accurately if the capacitor is

charged, the voltage is only measured during the PFC power switch off-time. The PFC is

stopped when V_SNSCURPFC> V_{stop(ss)(PFC)}

.

7.7.7 PFC overcurrent regulation, OCR-PFC (SNSCURPFC pin)

The maximum peak current is limited cycle-by-cycle by sensing the voltage across an

external sense resistor (R_cur(PFC)) connected to the source of the external MOSFET. The

voltage is measured via the SNSCURPFC pin and is limited to V_ocr(PFC)

.

A voltage peak appears on V_SNSCURPFCwhen the PFC MOSFET is switched on due to the

discharging of the drain capacitance. The leading-edge blanking time t_leb(PFC)ensures that

the overcurrent sensing block does not react to this transitory peak.

7.7.8 PFC mains undervoltage protection/brownout protection, UVP mains

(SNSMAINS pin)

The voltage on the SNSMAINS pin is continuously sensed to prevent the PFC trying to

operate at very low mains input voltages. PFC switching stops when

V

_SNSMAINS< V_{uvp(SNSMAINS)}. Mains undervoltage protection is also called brownout

protection.

V_SNSMAINSis clamped to a minimum value of V_pu(SNSMAINS)for fast restart as soon as the

mains input voltage recovers after a mains dropout. The PFC starts or restarts once

V

_SNSMAINSexceeds the V_{start(SNSMAINS)}start level.

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Product data sheet

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7.7.9 PFC boost overvoltage protection, OVP boost (SNSBOOST pin)

An overvoltage protection circuit has been built in to prevent boost overvoltage during load

steps and mains transients. Switching of the power factor correction circuit is inhibited

when the voltage on the SNSBOOST pin > V_{ovp(SNSBOOST)}

.

PFC switching resumes when V_SNSBOOST< V_{ovp(SNSBOOST)}again.

Overvoltage protection is also triggered when an open circuit occurs at the resistor

connected between the SNSBOOST pin and ground.

7.7.10 PFC short circuit/open-loop protection, SCP/OLP-PFC (SNSBOOST pin)

The PFC circuit does not start switching until the voltage on the SNSBOOST

pin > V_{scp(SNSBOOST)}. This acts as short-circuit protection for the V_boost(SCP boost).

The SNSBOOST pin draws a small input current I_{prot(SNSBOOST)}. If this pin gets

disconnected, the residual current pulls down V_SNSBOOSTwhich triggers the short-circuit

protection (SCP boost). This combination creates an open-loop protection (OLP-PFC).

7.8 HBC controller

The HBC controller converts the V_boost400 V from the PFC into one or more regulated DC

output voltages and drives two external MOSFETs in a half-bridge configuration

connected to a transformer. The transformer forms the resonant circuit in combination with

the resonant capacitor and the load at the output. The transformer has a leakage

inductance and a magnetizing inductance. The regulation is realized using frequency

control.

7.8.1 HBC high-side and low-side driver (GATEHS and GATELS pins)

Both drivers have an identical driving capability. The output of each driver is connected to

the equivalent gate of an external high-voltage power MOSFET.

The low-side driver is referenced to the PGND pin and is supplied from the SUPREG pin.

The high-side driver is floating. The reference for the high-side driver is the HB pin,

connected to the midpoint of the external half-bridge. The high-side driver is supplied from

the SUPHS pin which is connected to the external bootstrap capacitor C_SUPHS. When the

low-side MOSFET is on, the bootstrap capacitor is charged from the SUPREG pin using

the external diode D_SUPHS

.

7.8.2 HBC boost undervoltage protection, UVP boost (SNSBOOST pin)

The SNSBOOST pin voltage is sensed continuously to prevent the HBC controller trying

to operate at very low boost input voltages. When V_SNSBOOST< V_{uvp(SNSBOOST)}HBC

switching stops the next time the GATELS pin goes HIGH. HBC switching resumes when

V

_SNSBOOST> V_{start(SNSBOOST).}

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7.8.3 HBC switch control

HBC switch control determines when the MOSFETs switch on and off. It uses the output

from several other blocks.

• A divider is used to alternate switching of the high and low-side MOSFETs for each

oscillator cycle. The oscillator frequency is twice the half-bridge frequency.

• The controlled oscillator determines the switch-off point.

• Adaptive non-overlap time sensing determines the switch-on point. This function is

the adaptive non-overlap time.

• Several protection circuits and the state of the SSHBC/EN input pin specify if the

resonant converter is allowed to start switching.

Figure 9 provides an overview of typical switching behavior.

GATEHS

GATELS

V

boost

HB

0

I

Tr(HBC) 0

CFMIN

t

014aaa857

Fig 9. Switching behavior of the HBC

7.8.4 HBC Adaptive Non-Overlap (ANO) time function (HB pin)

7.8.4.1 Inductive mode (normal operation)

The high efficiency characteristic of a resonant converter is the result of Zero-Voltage

Switching (ZVS) of the power MOSFETs. ZVS is also called soft switching. To allow soft

switching, a small non-overlap time is required between the high-side on-times and

low-side MOSFETs. During this non-overlap time, the primary resonant current charges or

discharges the half-bridge capacitance between ground and V_boost

.

After the charge or discharge cycles, the MOSFET body diode starts conducting and

because the voltage across the MOSFET is zero, when the MOSFET is switched on there

are no switching losses. This operating mode is called inductive mode. In inductive mode,

the switching frequency is above the resonance frequency and the resonant tank has an

inductive impedance.

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The HB transition time depends on the resonant current amplitude when switching starts.

There is a complex relationship between this amplitude, the frequency, V_boostand the

output voltage. Ideally, the IC switches on the MOSFET when the HB transition is

complete. If it waits any longer, V_HBcan swing back, especially at high output loads. The

advanced adaptive non-overlap time function controls the timing. The adaptive

non-overlap time function makes it unnecessary to choose a fixed dead time (which is

always a compromise). This saves on external components.

Adaptive non-overlap time sensing measures the HB slope after one MOSFET has been

switched off. Normally, the HB slope starts immediately (the voltage starts rising or falling).

Once the transition at the HB node is complete, the slope ends (the voltage stops

rising/falling). This slope end is detected by the ANO time sensor and the other MOSFET

is switched on. In this way, the non-overlap time is automatically optimized even when the

HB transition cannot be completed which minimizes switching losses.

Figure 10 illustrates the adaptive non-overlap time function operation of the inductive

mode.

GATEHS

GATELS

V

boost

HB

t

0

fast HB slope

slow HB slope

incomplete HB slope

014aaa858

Fig 10. Adaptive non-overlap time function (normal inductive operation)

The non-overlap time depends on the HB slope but it has upper and lower limits.

An integrated minimum non-overlap time, t_no(min)prevents cross conduction occurring

under any circumstances.

The maximum non-overlap time is limited to the oscillator charge time. If the HB slope is

longer than the oscillator charge time (¹⁄₄of HB switching period), the MOSFET is forced

to switch on. In this case, the MOSFET is not soft switching. This limitation ensures the

MOSFET on-time is at least ¹⁄₄of the HB switching period at very high switching

frequencies.

7.8.4.2 Capacitive mode

Section 7.8.4.1 is true for normal operation with a switching frequency higher than the

resonance frequency. When an error condition occurs (for example; output short, load

pulse too high) the switching frequency is lower than the resonance frequency. The

resonant tank then has a capacitive impedance. In capacitive mode, the HB slope does

not start after the MOSFET switches off. Switching on the other MOSFET is not

recommended in this situation. The absence of soft switching increases dissipation in the

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MOSFETs. In capacitive mode, the body diode in the switched off MOSFET can start

conducting. Switching on the other MOSFET at this instant can result in the immediate

destruction of the MOSFETs.

The advanced adaptive non-overlap time of the SSL4120 always waits until the slope at

the half-bridge node starts. It guarantees safe switching of the MOSFETs in all

circumstances. Figure 11 shows the adaptive non-overlap time function operation in

capacitive mode.

In capacitive mode, half the resonance period can elapse before the resonant current

changes back to the correct polarity and starts charging the half-bridge node. The

oscillator is slowed down until the half-bridge slope starts to allow this relatively long

waiting time. See Section 7.8.5 for more details on the oscillator.

V

pu(SNSFB)

V

fmax(ss)(RFMAX)

fmax(fb)(RFMAX)

V

SNSFB

V

olp(SNSFB)

V

= 8.4 V

SSHBC

V

fmin(SNSFB)

V

SNSFB

V

RFMAX

V

fmax(SNSFB)

RFMAX

V

clamp(SNSFB)

0

I

clamp(SNSFB)

olp(SNSFB) fmin(SNSFB)

fmax(SNSFB)

0

I

SNSFB

014aaa862

Fig 11. Adaptive non-overlap time function (capacitive operation)

The MOSFET is forced to switch on when the half-bridge slope fails to start and the

oscillator voltage reaches V_u(CFMIN)

.

The switching frequency is increased to eliminate the problems associated with capacitive

mode operation (see Section 7.8.11).

7.8.5 HBC slope controlled oscillator (CFMIN and RFMAX pins)

The slope-controlled oscillator determines the half-bridge switching frequency. The

oscillator generates a triangular waveform between V_u(CFMIN)and V_l(CFMIN)at the external

capacitor C_fmin

.

Figure 12 shows how the frequency is determined.

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FEEDBACK CURRENT

VOLTAGE PIN SSHBC

PIN SNSFB

POLARITY INVERSION

(max 2.5 V)

CONVERSION TO

VOLTAGE (max 1.5 V)

VOLTAGE PIN RFMAX

CONVERSION TO CURRENT

via R

FIXED f

CURRENT

min

fmax

(DIS-)CHARGE CURRENT

PIN CFMIN

CONVERSION TO

FRQUENCY via C

fmin

014aaa860

Fig 12. Determination of frequency

Two external components determine the frequency range:

• Capacitor C_fminconnected between the CFMIN pin and ground sets the minimum

frequency in combination with an internally trimmed current source I_osc(min)

.

• Resistor R_fmaxconnected between the RFMAX pin and ground sets the frequency

range and thus the maximum frequency.

The oscillator frequency depends on the charge and discharge currents of C_fmin. The

charge and discharge current contains a fixed component, I_osc(min), which determines the

minimum frequency. In addition, a variable component that is 4.9 times greater than the

current in the RFMAX pin. The value of R_fmaxand the RFMAX voltage pin determine

I_RFMAX

:

• The voltage on the RFMAX pin is V_fmin(RFMAX)= 0 V at the minimum frequency.

• The voltage on the RFMAX pin is V_{fmax(fb)(RFMAX)}= 1.5 V at the maximum feedback

frequency.

• The voltage on the RFMAX pin is V_{fmax(ss)(RFMAX)}= 2.5 V at the maximum soft-start

frequency.

The maximum frequency of the oscillator is internally limited. The HB frequency is limited

to f_limit(HB)(minimum. 500 kHz). Figure 13 shows the relationship between V_RFMAX, R_fmax

_fminand f_HB

,

C

.

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f

C

B

limit(HB)

f

max(B)

f

HB

f

max(A)

A

f

min(B and C)

f

min(A)

V

RFMAX

fmax(fb)(RFMAX) fmax(ss)(RFMAX)

014aaa861

V

0

A: C_fmin= high, R_fmax= high.

B: C_fmin= low, R_fmax= low.

C: C_fmin= low, R_fmax= too low.

Fig 13. Function of R_fmaxand C_fmin

The half-bridge slope controls the oscillator. The oscillator charge current is initially set to

a low value I_osc(red)= 30 A. When the start of the half-bridge slope is detected, the

charge current is increased to its normal value. This feature is used in combination with

the adaptive non-overlap time function as described in Section 7.8.4.2 and Figure 11.

The length of time the oscillator current is low is negligible under normal operating

conditions because the half-bridge slope normally starts directly after the MOSFET is

switched off.

7.8.6 HBC feedback input (SNSFB pin)

In a typical power supply application, the output voltage is compared and amplified on the

secondary side. The error amplifier output is transferred to the primary side using an

optocoupler. This optocoupler can be connected directly to the SNSFB pin.

The SNSFB pin supplies the optocoupler from an internal voltage source

V_pu(SNSFB)= 8.4 V with the R_O(SNSFB)series resistance. The series resistance allows spike

filtering using an external capacitor. To ensure sufficient optocoupler bias current, the

feedback input has a threshold current I_fmin(SNSFB)= 0.66 mA at which the frequency is at

a minimum.

The maximum frequency is reached at I_fmax(SNSFB)= 2.2 mA. The maximum frequency

that can be reached using the SNSFB pin is lower (60 %) than the maximum frequency

that can be reached using the SSHBC/EN pin. Figure 14 shows the relationship between

I_SNSFB, V_SNSFBand V_RFMAX.

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V

pu(SNSFB)

V

fmax(ss)(RFMAX)

fmax(fb)(RFMAX)

V

SNSFB

V

olp(SNSFB)

V

= 8.4 V

SSHBC

V

fmin(SNSFB)

V

SNSFB

V

RFMAX

V

fmax(SNSFB)

RFMAX

V

clamp(SNSFB)

0

I

clamp(SNSFB)

olp(SNSFB) fmin(SNSFB)

fmax(SNSFB)

0

I

SNSFB

014aaa862

Fig 14. Transfer function of feedback input

Below the minimum frequency level, V_SNSFBis clamped at V_clamp(SNSFB)= 3.2 V. This

clamp enables a fast recovery of the output voltage regulation loop after an overshoot of

the output voltage. The maximum current the clamp can deliver is I_clamp(SNSFB)= 7.3 mA.

7.8.7 HBC open-loop protection, OLP-HBC (SNSFB pin)

Under normal operating conditions, the optocoupler current is between I_fmin(SNSFB)and

I_fmax(SNSFB)and pulls down the voltage at the SNSFB pin. Due to an error in the feedback

loop, the current could be less than I_fmin(SNSFB)with the HBC controller delivering

maximum output power.

The HBC controller features open-loop protection (OLP-HBC) which monitors the SNSFB

pin voltage. When V_SNSFB> V_olp(SNSFB), the protection timer is started. The Restart state

is activated if the OLP condition is still present after the protection time has elapsed.

7.8.8 HBC soft start (SSHBC/EN pin)

The relationship between switching frequency and output current is not constant. It

depends strongly on the output voltage V_Oand V_boost. This relationship can be complex.

The SSL4120 contains a soft-start function to ensure that the resonant converter starts or

restarts with safe currents. This soft-start function forces a start at such a high frequency

that the currents are acceptable under all conditions. The soft-start then slowly decreases

the frequency. Normally, output voltage regulation takes over frequency control before

soft-start reaches its minimum frequency. Limiting the output current during start-up also

limits the rate at which the output voltage rises and prevents an overshoot.

Soft-start utilizes the SSHBC/EN pin voltage. The external capacitor C_ss(HBC)sets the

timing of the soft-start. The SSHBC/EN pin is also used as an enable input. Soft-start

voltage levels are above the enable voltage thresholds.

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7.8.8.1 Soft-start voltage levels

The relationship between the soft-start voltage at the SSHBC/EN pin and the RFMAX pin

voltage is shown in Figure 15. The relationship is directly related to the frequency.

V

RFMAX

f

max

f

HB

V

fmax,ss(RFMAX)

f

HB

V

fmax,fb(RFMAX)

V

RFMAX

f

min

0

V

fmax(SSHBC)

clamp(SSHBC)

fmin(SSHBC)

V

pu(EN)

V

SSHBC

< I

fmin(SNSFB)

I

SNSFB

< I

fmax(SNSFB)

fmin(SNSFB)

SNSFB

014aaa863

Fig 15. Relation between SSHBC/EN voltage and frequency

V_RFMAXand V_SSHBC/ENare of opposite polarity. V_SSHBC/EN< V_fmax(SSHBC)= 3.2 V at initial

start-up which corresponds to the maximum frequency. During start-up, C_ss(HBC)is

charged, V_SSHBC/ENincreases and the frequency decreases. The contribution of the

soft-start function is zero when V_SSHBC/EN= V_fmin(SSHBC)= 7.9 V.

V_SSHBC/ENis clamped at a maximum of V_clamp(SSHBC)= 8.4 V (frequency is at a minimum)

and at a minimum ( 3 V). Under V_fmax(SSHBC)(maximum frequency), the discharge

current is reduced to a maximum frequency soft-start current of 5 A The voltage is

clamped at a minimum of V_pu(EN)= 3 V. Both clamp levels are just outside the operating

area of V_fmax(SSHBC)to V_fmin(SSHBC). The margins avoid frequency disturbance during

normal output voltage regulation but ensure that overcurrent regulation can respond

quickly.

7.8.8.2 Soft-start charge and discharge

At initial start-up, the soft-start capacitor C_ss(HBC)is charged to obtain a decreasing

frequency sweep from the maximum to the operating frequency. As well as being used to

soft-start the resonant converter, the soft-start functionality is also used for regulation

(such as overcurrent regulation). C_ss(HBC)can therefore be charged or discharged. A

continuous alternation between charging and discharging occurs during overcurrent

regulation. In this way V_SSHBC/ENcan be regulated, overruling the signal from the

feedback input.

The charge and discharge current can have a high value, I_{ss(hf)(SSHBC)}= 160 A. This

current results in fast charging and discharging. In addition, it can have a low value

I_{ss(lf)(SSHBC)}= 40 A, resulting in a slow charge and discharge. This two-speed soft-start

sweep allows a combination of a short start-up time for the resonant converter and stable

regulation loops (such as overcurrent regulation).

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The fast charge and discharge is used for the upper frequency range where

_SSHBC/EN< V_{ss(hf-lf)(SSHBC)}= 5.6 V. In the upper frequency range, the currents in the

V

converter do not react strongly to frequency variations.

The slow charge and discharge speed is used for the lower frequency range where

V_SSHBC/EN> V_{ss(hf-lf)(SSHBC)}= 5.6 V. In the lower frequency range, the currents in the

converter react strongly to frequency variations.

Section 7.8.10.2 describes how the two-speed soft-start function is used for overcurrent

regulation.

The soft-start capacitor is not charged or discharged during non-operation time in burst

mode. The soft-start voltage does not change during this time.

7.8.8.3 Soft-start reset

Some protection functions, such as overcurrent protection, require fast correction of the

operating frequency set point, but do not require switching to stop. See the protection

overview in Section 7.9 for details on which protection functions use this step to the

maximum frequency. The SSL4120 has a special fast soft-start reset feature for the HBC

controller that forces V_{fmax(ss)(RFMAX)}on the RFMAX pin. Soft-start reset is also used when

the HBC controller is enabled using the SSHBC/EN pin or after a restart to ensure a

safe-start at maximum frequency. Soft-start reset is not used when the operation was

stopped in burst mode.

When a protection function is activated, the oscillator control input is disconnected from

the soft-start capacitor C_ss(HBC)which is connected between the SSHBC/EN pin and

ground. The switching frequency is immediately set to a maximum. Setting the switching

frequency to a maximum restores safe switching operation in most cases. At the same

time, the capacitor is discharged to the maximum frequency level V_fmax(SSHBC). Once

V

_SSHBC/ENhas reached this level, the oscillator control input is connected to the pin again

and the normal soft-start sweep follows. Figure 16 shows the soft-start reset and the

two-speed frequency sweep downwards.

on

Protection

off

V

fmin(SSHBC)

V

ss(hf-lf)(SSHBC)

V

SSHBC/EN

V

fmax(SSHBC)

0

f

max

f

HB

f

min

0

t

f

max

regulation

fast

sweep

slow sweep

regulation

forced

014aaa864

Fig 16. Soft-start reset and two-speed soft-start

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7.8.9 HBC high-frequency protection, HFP-HBC (RFMAX pin)

Normally the converter does not operate continuously at maximum frequency because it

sweeps down to much lower values. Certain error conditions, such as a disconnected

transformer, could cause the converter to operate continuously at maximum frequency. If

zero-voltage switching conditions are no longer present, the MOSFETs can overheat. The

SSL4120 features High-Frequency Protection (HFP) for the HBC controller to protect it

from being damaged in such circumstances.

HFP senses the RFMAX pin voltage. This voltage indicates the current frequency. When

the frequency is higher than 75 % of the soft-start frequency range, the protection timer is

started. The 75 % level corresponds to an RFMAX voltage of V_hfp(RFMAX)= 1.83 V.

7.8.10 HBC overcurrent regulation and protection, OCR and OCP

(SNSCURHBC pin)

The HBC controller is protected against overcurrent in two ways:

• Overcurrent regulation (OCR-HBC) which increases the frequency slowly. The

protection timer is also started.

• Overcurrent protection (OCP-HBC) which steps to maximum frequency.

A V_boostcompensation function is used to reduce the variation in the output current

protection level.

7.8.10.1 Boost voltage compensation

The primary current, also known as the resonant current, is sensed using the

SNSCURHBC pin. It senses the momentary voltage across an external current sense

resistor R_cur(HBC). The use of the momentary current signal allows fast overcurrent

protection and simplifies the stabilizing of overcurrent regulation. The OCR and OCP

comparators compare V_SNSCURHBCwith the maximum positive and negative values.

The primary current is higher when V_boostis low for the same output power. Boost

compensation is included to reduce the dependency of the protected output current level

on V_boost. The boost compensation sources and sinks a current from the SNSCURHBC

pin. This current creates a voltage drop across the series resistor R_curcmp

.

The amplitude of the current is linearly dependent on V_boost. At V_boost(nom), the current is

zero and the voltage V_Cur(HBC)across the current sense resistor is also present on the

SNSCURHBC pin.

At the UVP boost start level V_{uvp(SNSBOOST)}, the current is at a maximum. The current sink

or source direction depends on the active gate signal. The voltage drop created across

R

_curcmpreduces the amplitude at the pin. This reduction in amplitude results in a higher

effective current protection level. The R_curcmpvalue sets the amount of compensation.

Figure 17 shows how the boost compensation works for an artificial current signal. The

sinking compensation current only flows when V_SNSCURHBCis positive because of the

circuit implementation.

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V

reg

V

boost

V

uvp

t

GATEHS

GATELS

t

sink

0

sink current only with positive V

SNSCURHBC

I

SNSCURHBC

t

source

V

= R_cur(HBC)× I

Cur(HBC)

I

ocp(high)

I

ocr(high)

ocp(nom)

ocr(nom)

I

Cur(HBC)

t

0

ocr(nom)

ocp(nom)

-I

ocr(high)

ocp(high)

-I

V

SNSCURHBC

V

ocp(HBC)

ocr(HBC)

V

SNSCURHBC

0

ocr(HBC)

ocp(HBC)

t

-V

nominal V

low V

boost

strong compensation

high OCP

boost

no compensation

nominal OCR

no compensation

nominal OCP

strong compensation

high OCR

014aaa865

Fig 17. Boost voltage compensation

7.8.10.2 Overcurrent regulation, OCR-HBC

The lowest comparator levels at the SNSCURHBC pin (V_ocr(HBC)= 0.5 V and +0.5 V),

relate to the overcurrent regulation voltage. There are comparators for both the positive

and negative polarities. The positive comparator is active during the high-side on-time and

the following high-side to low-side non-overlap time. The negative comparator is active

during the remaining time. If either level is exceeded, the frequency is slowly increased.

Discharging the soft-start capacitor achieves this decrease.

Each time the OCR level is exceeded, the event is latched until the next stroke and the

soft-start discharge current is enabled. When both the positive and negative OCR levels

are exceeded, the soft-start discharge current flows continuously.

Overcurrent regulation is very effective at limiting the output current during start-up. A

smaller soft-start capacitor is used to achieve a faster start-up. Using a smaller capacitor

can result in an output current that is too high at times. However, the OCR function slows

down the frequency sweep when required to keep the output current within the specified

limits. Figure 18 shows the operation of the OCR during output voltage start-up.

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I

ocr

I

Cur(HBC)

0

t

-I

ocr

I

ss(hf)(SSHBC)

I

-I

ss(If)(SSHBC)

I

SSHBC/EN

ss(If)(SSHBC)

-I

ss(hf)(SSHBC)

V

fmin(SSHBC)

V

SSHBC/EN

V

ss(hf-lf)(SSHBC)

V

fmax(SSHBC)

t

0

V

reg

V

O

t

0

Fast soft start sweep (charge and discharge)

Slow soft start sweep (charge and discharge)

014aaa866

Fig 18. Overcurrent regulation during start-up

The protection timer is also started. The Restart state is activated when the OCR-HBC

condition is still present after the protection time has elapsed.

7.8.10.3 Overcurrent protection, OCP-HBC

Under normal operating conditions, OCR is able to ensure the current remains below the

specified maximum values. However, in the event of certain error conditions, it is not fast

enough to limit the current. OCP is implemented to protect against those error conditions.

The OCP level (V_ocp(HBC)= 1 V and +1 V), is higher than the OCR level V_ocr(HBC)

.

When the OCP level is reached, the frequency immediately jumps to the maximum value

using the soft-start reset, then a normal sweep down.

7.8.11 HBC capacitive mode regulation, CMR (HB pin)

The MOSFETs in the half-bridge drive the resonant circuit. Depending on the output load,

the output voltage and the switching frequency this resonant circuit can have an inductive

or a capacitive impedance. Inductive impedance is preferred because it facilitates efficient

zero-voltage switching.

Harmful switching in capacitive mode is avoided using the adaptive non-overlap time

function (see Section 7.8.4.2). An extra action is performed which results in Capacitive

Mode Regulation (CMR). CMR causes the half-bridge circuit to return to Inductive mode

from Capacitive mode.

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Capacitive mode is detected when the HB slope does not start within t_to(cmr)after the

MOSFETs have switched off. Detection of Capacitive mode increases the switching

frequency. This increase is caused by discharging the soft-start capacitor with a relatively

high current I_{cmr(hf)(SSHBC)}immediately after t_to(cmr)expires until the half-bridge slope

starts. The frequency increase regulates the HBC to the border between capacitive and

inductive mode.

7.9 Protection functions overview

Table 4.

Overview protections

Protected Symbol

part

Protection

Affected Action

Description

IC

UVP-SUPIC

Undervoltage protection SUPIC

IC

disable

Section 7.2.1

Section 7.2.2

Section 7.3

IC

UVP-SUPREG Undervoltage protection SUPREG IC

disable

IC

UVP-supplies

SCP-SUPIC

OVP output

UVP output

OTP

Undervoltage protection supplies

Short circuit protection SUPIC

Overvoltage protection output

Undervoltage protection output

Overtemperature protection

Overcurrent regulation PFC

Undervoltage protection mains

Overvoltage protection boost

Short circuit protection boost

Open-loop protection PFC

IC

disable and reset

low HV start-up current

shutdown

IC

Section 7.2.4

Section 7.5.4

IC

restart after protection time Section 7.5.5

IC

disable

Section 7.5.6

Section 7.7.7

Section 7.7.8

Section 7.7.9

Section 7.7.10

Section 7.8.2

PFC

HBC

OCR-PFC

UVP mains

OVP boost

SCP boost

OLP-PFC

UVP boost

OLP-HBC

HFP-HBC

OCR-HBC

PFC

IC

switch off cycle-by-cycle

suspend switching

restart

IC

restart

Undervoltage protection boost

Open-loop protection HBC

HBC

IC

disable

restart after protection time Section 7.8.7

restart after protection time Section 7.8.9

High-frequency protection HBC

Overcurrent regulation HBC

IC

HBC

IC

increase frequency

restart after protection time

Section 7.8.10.2

HBC

OCP-HBC

Overcurrent protection HBC

HBC

step to maximum

frequency

Section 7.8.10.3

HBC

CMR

ANO

Capacitive mode regulation

Adaptive non-overlap

HBC

increase frequency

Section 7.8.11

Section 7.8.4

prevent hazardous

switching

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Product data sheet

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32 of 48

SSL4120

NXP Semiconductors

Resonant power supply controller IC with PFC for LED lighting

8. Limiting values

Table 5.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are measured with respect to pin SGND;

Currents are positive when flowing into the IC; The voltage ratings are valid provided other ratings are not violated; Current

ratings are valid provided the maximum power rating is not violated.

Symbol

Voltages

V_SUPHV

V_SUPHS

Parameter

Conditions

Min

Max

Unit

voltage on pin SUPHV

voltage on pin SUPHS

continuous

0.4

25

+630

V

DC

+570

t < 0.5 s

+630

referenced to the HB pin

+14

V_SUPIC

voltage on pin SUPIC

+38

V_SNSAUXPFC

V_SUPREG

V_SNSOUT

V_RCPROT

V_SNSFB

voltage on pin SNSAUXPFC

voltage on pin SUPREG

voltage on pin SNSOUT

voltage on pin RCPROT

voltage on pin SNSFB

+25

0.4

5

+12

V_SSHBC/EN

V_GATEHS

V_GATELS

V_GATEPFC

V_SNSCURHBC

V_SNSBOOST

V_SNSMAINS

V_SNSCURPFC

V_COMPPFC

V_CFMIN

voltage on pin SSHBC/EN

voltage on pin GATEHS

voltage on pin GATELS

voltage on pin GATEPFC

voltage on pin SNSCURHBC

voltage on pin SNSBOOST

voltage on pin SNSMAINS

voltage on pin SNSCURPFC

voltage on pin COMPPFC

voltage on pin CFMIN

+12

t < 10 µs for I > 10 mA

V_SUPHS+ 0.4

V_SUPREG+ 0.4

+5

+1

0.4

1

current limited

V_PGND

voltage on pin PGND

Currents

I_GATEPFC

I_SNSCURPFC

General

P_tot

current into pin GATEPFC

duty cycle < 10 %

0.8

1

+2

A

current into pin SNSCURPFC

+10

mA

total power dissipation

storage temperature

junction temperature

T_amb< 75 C

-

0.8

W

T_stg

55

40

+150

C

T_j

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Product data sheet

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SSL4120

NXP Semiconductors

Resonant power supply controller IC with PFC for LED lighting

Table 5.

Limiting values …continued

In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are measured with respect to pin SGND;

Currents are positive when flowing into the IC; The voltage ratings are valid provided other ratings are not violated; Current

ratings are valid provided the maximum power rating is not violated.

Symbol

ESD

Parameter

Conditions

Min

Max

Unit

V_ESD

Electrostatic discharge voltage

Human body model

pin 12 (SUPHV)

pin 13,14,15 (HS driver)

other pins

[1]

-

1.5

1

kV

2

Machine model

all pins

[2]

-

200

500

V

Charged device model

all pins

[1] Equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.

[2] Equivalent to discharging a 200 pF capacitor through a 0.75 H coil and a 10  resistor.

9. Thermal characteristics

Table 6.

Symbol

R_th(j-a)

Thermal characteristics

Parameter

Conditions

in free air; JEDEC single layer test board

Typ

Unit

thermal resistance from junction to ambient

90

K/W

10. Characteristics

Table 7.

Characteristics

T_amb= 25 C; V_SUPIC= 20 V; V_SUPHV> 40 V; all voltages are measured with respect to SGND; currents are positive when

flowing into the IC; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max Unit

High-voltage start-up source (SUPHV pin)

I_dism(SUPHV)

disable mode current on pin

SUPHV

disabled IC state

-

150

-

A

I_red(SUPHV)

I_nom(SUPHV)

I_tko(SUPHV)

V_det(SUPHV)

V_rst(SUPHV)

reduced current on pin SUPHV

nominal current on pin SUPHV

takeover current on pin SUPHV

detection voltage on pin SUPHV

reset voltage on pin SUPHV

V_SUPIC< V_scp(SUPIC)

-

1.1

5.1

7

-

mA

A

V

V_SUPIC< V_{start(hvd)(SUPIC)}

V_SUPIC> V_{start(hvd)(SUPIC)}

-

25

-

V_SUPIC< V_rst(SUPIC)

7

V

Low-voltage IC supply (SUPIC pin)

V_{start(hvd)(SUPIC)}

V_{start(nohvd)(SUPIC)}

V_{start(hys)(SUPIC)}

V_uvp(SUPIC)

start voltage with high voltage

detected

V_SUPHV> V_det(SUPHV)

21

22

23

V

start voltage with no high voltage

detected

V_SUPHV< V_det(SUPHV)or open

16.1 17

0.3

14.2 15

17.9

-

hysteresis of start voltage on pin

SUPIC

-

undervoltage protection voltage on

pin SUPIC

15.8

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Product data sheet

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34 of 48

SSL4120

NXP Semiconductors

Resonant power supply controller IC with PFC for LED lighting

Table 7.

Characteristics …continued

T_amb= 25 C; V_SUPIC= 20 V; V_SUPHV> 40 V; all voltages are measured with respect to SGND; currents are positive when

flowing into the IC; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max Unit

V_rst(SUPIC)

V_scp(SUPIC)

reset voltage on pin SUPIC

V_SUPHV< V_rst(SUPHV)

-

7

-

V

short-circuit protection voltage on

pin SUPIC

0.55 0.65

0.75

I_{ch(red)(SUPIC)}

I_{ch(nom)(SUPIC)}

I_dism(SUPIC)

reduced charge current on pin

SUPIC

V_SUPIC< V_scp(SUPIC)

-

0.95

4.8

0.25

0.4

-

mA

nominal charge current on pin

SUPIC

current on pin SUPIC in disabled

mode

disabled IC state

I_protm(SUPIC)

current on pin SUPIC in protection SUPIC charge, SUPREG

mode

charge; Restart or

Shut-down state

I_oper(SUPIC)

current on pin SUPIC in operating

mode

Operational supply state;

Driver pins open.

-

3

-

mA

Regulated supply (SUPREG pin)

[1]

V_reg(SUPREG)

V_{start(SUPREG)}

V_uvp(SUPREG)

regulation voltage on pin SUPREG I_SUPREG= 40 mA

10.6 10.9

11.2

V

start voltage on pin SUPREG

-

10.7

10.3

-

undervoltage protection voltage on

pin SUPREG

I_{ch(SUPREG)max}

I_{ch(red)(SUPREG)}

maximum charge current on pin

SUPREG

V_SUPREG> V_uvp(SUPREG)

40

-

100

5.5

-

mA

reduced charge current on pin

SUPREG

V_SUPREG< V_uvp(SUPREG);

T = 25 C.

T = 140 C

2.5

Enable input (SSHBC/EN pin)

[2]

V_en(PFC)(EN)

V_en(IC)(EN)

I_pu(EN)

PFC enable voltage on pin EN

PFC only

0.8

1.8

-

1.2

2.2

42

3

1.4

2.4

-

V

IC enable voltage on pin EN

pull-up current on pin EN

pull-up voltage on pin EN

PFC + HBC

V

V_SSHBC/EN= 2.5 V

A

V

V_pu(EN)

-

Fast shut-down reset (SNSMAINS pin)

[2]

V_{rst(SNSMAINS)}

reset level on pin SNSMAINS

-

0.8

-

V

Protection and restart timer (RCPROT pin)

V_u(RCPROT)

upper voltage on pin RCPROT

3.8

0.4

-

4

4.2

0.6

-

V

V_l(RCPROT)

lower voltage on pin RCPROT

0.5

2.2

V

I_{ch(fast)(RCPROT)}

I_{ch(slow)(RCPROT)}

fast-charge current on pin RCPROT

mA

A

slow-charge current on pin

RCPROT

120 100 80

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Product data sheet

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35 of 48

SSL4120

NXP Semiconductors

Resonant power supply controller IC with PFC for LED lighting

Table 7.

Characteristics …continued

T_amb= 25 C; V_SUPIC= 20 V; V_SUPHV> 40 V; all voltages are measured with respect to SGND; currents are positive when

flowing into the IC; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max Unit

Output voltage protection sensing, UVP/OVP output (SNSOUT pin)

[2]

V_ovp(SNSOUT)

V_uvp(SNSOUT)

overvoltage protection voltage on

pin SNSOUT

3.4

2.2

3.5

3.6

2.5

V

under-voltage protection voltage on

pin SNSOUT

2.35

Overtemperature protection

T_otpovertemperature protection trip

temperature

Burst mode activation (SNSOUT pin)

[2]

130

150

160

C

[2]

V_burst(HBC)

V_burst(PFC)

I_pu(SNSOUT)

V_pu(SNSOUT)

HBC burst mode voltage

0.9

0.3

-

1.1

0.4

1.2

0.5

V

PFC burst mode voltage

V

pull-up current on pin SNSOUT

pull-up voltage on pin SNSOUT

100 80

A

V

R_SNSOUT= 25 k to SGND

-

1.5

-

PFC driver (GATEPFC pin)

I_{source(GATEPFC)}source current on pin GATEPFC

I_{sink(GATEPFC)}sink current on pin GATEPFC

V_GATEPFC= 2 V

V_GATEPFC= 10 V

-

0.5

0.7

A

-

1.2

PFC on-timer (COMPPFC pin)

V_{ton(COMPPFC)zero}zero on-time voltage on pin

-

3.5

-

V

COMPPFC

V_{ton(COMPPFC)max}

maximum on-time voltage on pin

COMPPFC

1.25

f_max(PFC)

PFC maximum frequency

minimum PFC off-time

300

-

380

1.1

460

-

kHz

t_off(PFC)min

s

PFC error amplifier (SNSBOOST and COMPPFC pins)

V_{reg(SNSBOOST)}

regulation voltage on pin

SNSBOOST pin

I_COMPPFC= 0 A

2.475 2.5

2.525 V

g_m

transconductance

V_SNSBOOSTto I_COMPPFC

V_SNSBOOST= 2 V

-

80

-

A/V

I_{sink(COMPPFC)}

I_{source(COMPPFC)}

V_{clamp(COMPPFC)}

sink current on pin COMPPFC

source current on pin COMPPFC

clamp voltage on pin COMPPFC

39

A

V

V_SNSBOOST= 3.3 V

39

3.9

[3]

PFC mains compensation (SNSMAINS pin)

t_on(max)

maximum on-time

high mains;

V_SNSMAINS= 3.3 V

3.5

29

4

4.7

44

-

5.9

59

-

s

V

low mains;

V_SNSMAINS= 0.97 V

V_{mvc(SNSMAINS)max}

maximum mains voltage

compensation voltage on pin

SNSMAINS

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Product data sheet

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36 of 48

SSL4120

NXP Semiconductors

Resonant power supply controller IC with PFC for LED lighting

Table 7.

Characteristics …continued

T_amb= 25 C; V_SUPIC= 20 V; V_SUPHV> 40 V; all voltages are measured with respect to SGND; currents are positive when

flowing into the IC; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max Unit

PFC demagnetization sensing (SNSAUXPFC pin)

V_{demag(SNSAUXPFC)}

demagnetization voltage on pin

SNSAUXPFC

150 100 50

mV

t_to(mag)

magnetization time-out time

40

50

60

-

s

I_{prot(SNSAUXPFC)}

protection current on pin

SNSAUXPFC

V_SNSAUXPFC= 50 mV

75

33

nA

PFC valley sensing (SNSAUXPFC pin)

(dV/dt)_vrec(min)minimum valley recognition rate of

-

1.7

V/s

voltage change

[4]

[5]

t_{slope(vrec)min}

minimum valley recognition slope

time

V_SNSAUXPFC= 1 V_pp

-

300

50

-

ns

demagnetization to V/t = 0

-

t_{d(val-dem)max}

t_to(vrec)

maximum valley-to-demag delay

time

200

valley recognition time-out time

3

4

6

s

PFC soft start (SNSCURPFC pin)

I_ch(ss)(PFC)

PFC soft-start charge current

-

60

-

A

V

[1]

V_{clamp(ss)(PFC)}

V_{stop(ss)(PFC)}

R_ss(PFC)

PFC soft-start clamp voltage

PFC soft-start stop voltage

PFC soft-start resistor

0.46 0.5

0.54

-

0.45

-

V

12

-

k

PFC overcurrent sensing (SNSCURPFC pin)

V_ocr(PFC)

PFC overcurrent regulation voltage dV/dt = 50 mV/s

0.49 0.52

0.51 0.54

0.55

0.57

370

-

V

dV/dt = 200 mV/s

V

t_leb(PFC)

leading edge blanking time

250

310

ns

nA

I_{prot(SNSCURPFC)}

protection current on pin

SNSCURPFC

50

33

PFC mains voltage sensing and clamp (SNSMAINS pin)

[1]

V_{start(SNSMAINS)}

V_{uvp(SNSMAINS)}

start voltage on pin SNSMAINS

1.11 1.15

0.84 0.89

1.19

0.94

V

undervoltage protection voltage on

pin SNSMAINS

[1]

V_pu(SNSMAINS)

I_pu(SNSMAINS)

I_{prot(SNSMAINS)}

pull-up voltage on pin SNSMAINS

maximum clamp current

UVP mains active

-

1.05

42

33

-

V

UVP mains active

35

100

A

nA

Protection current on pin

SNSMAINS

V_SNSMAINS> V_{uvp(SNSMAINS)}

PFC boost voltage protection sensing, SCP/UVP/OVP boost (SNSBOOST pin)

V_{scp(SNSBOOST)}

short-circuit protection voltage on

pin SNSBOOST

0.35 0.4

0.45

V

V_{start(SNSBOOST)}

V_{uvp(SNSBOOST)}

start voltage on pin SNSBOOST

-

2.3

1.6

2.4

-

V

undervoltage protection voltage on

pin SNSBOOST

1.5

V_{ovp(SNSBOOST)}

overvoltage protection voltage on

pin SNSBOOST

2.59 2.63

2.67

V

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Product data sheet

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SSL4120

NXP Semiconductors

Resonant power supply controller IC with PFC for LED lighting

Table 7.

Characteristics …continued

T_amb= 25 C; V_SUPIC= 20 V; V_SUPHV> 40 V; all voltages are measured with respect to SGND; currents are positive when

flowing into the IC; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max Unit

I_{prot(SNSBOOST)}

protection current on pin

SNSBOOST

V_SNSBOOST= 2.5 V

-

45

100

nA

HBC high-side and low-side driver (GATEHS and GATELS pins)

I_{source(GATEHS)}

I_{source(GATELS)}

I_sink(GATEHS)

source current on pin GATEHS

source current on pin GATELS

sink current on pin GATEHS

V_GATEHS V_HB= 4 V

V_GATELS V_PGND= 4 V

V_GATEHS V_HB= 2 V;

V_GATEHS V_HB= 11 V

V_GATELS V_PGND= 2 V

V_GATELS V_PGND= 11 V

-

310

560

1.9

-

mA

A

I_sink(GATELS)

sink current on pin GATELS

560

1.9

mA

A

V_rst(SUPHS)

I_q(SUPHS)

reset voltage on pin SUPHS

4.5

V

quiescent current on pin SUPHS

V_SUPHS V_HB= 11 V

37

A

HBC adaptive non-overlap time (HB pin)

(dV/dt)_ano(min)minimum adaptive non-overlap time

-

120

160

V/s

rate of voltage change

t_no(min)

minimum non-overlap time

ns

HBC current controlled oscillator (CFMIN and RFMAX pin)

f_min(HB)

minimum frequency on pin HB

C_fmin= 390 pF;

40

44

48

kHz

V_SSHBC/EN> V_fmin(SSHBC)

V_SNSFB> V_fmin(SNSFB)

I_osc(min)

I_osc(max)

minimum oscillator current

maximum oscillator current

V_RFMAX= 0 V; charge and

discharge

-

150

970

-

A

R_fmax= 15 k;

V_RFMAX=2.5 V;

V_SSHBC/EN< V_fmax(SSHBC)

I_osc(red)

reduced oscillator current

slowed-down oscillator

C_fmin= 20 pF

-

30

-

A

I_CFMIN/I_RFMAX

current on pin CFMIN to current on

pin RFMAX ratio

4.9

f_limit(HB)

limit frequency on pin HB

upper voltage on pin CFMIN

lower voltage on pin CFMIN

500

2.85

0.9

-

670

3

-

kHz

V

V_u(CFMIN)

V_l(CFMIN)

V_fmin(RFMAX)

3.15

1.1

-

1

V

minimum frequency voltage on pin

RFMAX

0

V

V_{fmax(ss)(RFMAX)}

V_{fmax(fb)(RFMAX)}

maximum soft start frequency

voltage on pin RFMAX

V_SSHBC/EN< V_fmax(SSHBC)

V_SNSFB< V_fmax(SNSFB)

2.4

2.5

2.6

V

maximum feedback frequency

voltage on pin RFMAX

1.45 1.55

1.65

HBC feedback input (SNSFB pin)

V_pu(SNSFB)

R_O(SNSFB)

V_olp(SNSFB)

pull-up voltage on pin SNSFB

-

8.4

1.5

7.7

-

V

output resistance on pin SNSFB

-

k

V

[2]

open-loop protection voltage on pin

SNSFB

7

7.9

I_olp(SNSFB)

open-loop protection current on pin

SNSFB

0.35 0.26 0.1 mA

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Product data sheet

Rev. 2 — 1 November 2012

38 of 48

SSL4120

NXP Semiconductors

Resonant power supply controller IC with PFC for LED lighting

Table 7.

Characteristics …continued

T_amb= 25 C; V_SUPIC= 20 V; V_SUPHV> 40 V; all voltages are measured with respect to SGND; currents are positive when

flowing into the IC; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max Unit

6.9

V_fmin(SNSFB)

minimum frequency voltage on pin

SNSFB

6.1

6.4

V

I_fmin(SNSFB)

minimum frequency current on pin V_SSHBC/EN> V_fmin(SSHBC)

SNSFB

0.86 0.66 0.46 mA

V_fmax(SNSFB)

I_fmax(SNSFB)

V_clamp(SNSFB)

I_clamp(SNSFB)

maximum frequency voltage on pin V_SSHBC/EN> V_fmin(SSHBC)

SNSFB

3.9

4.1

4.3

V

maximum frequency current on pin V_SSHBC/EN> V_fmin(SSHBC)

SNSFB

-

2.2

3.2

-

mA

V

clamp voltage on pin SNSFB

maximum frequency;

I_SNSFB= 4 mA

clamp current on pin SNSFB

maximum frequency;

V_SNSFB= 0 V

7.3

mA

HBC soft-start (SSHBC/EN pin)

V_fmax(SSHBC)maximum frequency voltage on pin

SSHBC

-

3.2

7.9

-

V

V_fmin(SSHBC)

minimum frequency voltage on pin V_SNSFB> V_fmin(SNSFB)

SSHBC

7.5

8.3

V_clamp(SSHBC)

V_{ss(hf-lf)(SSHBC)}

clamp voltage on pin SSHBC

-

8.4

5.6

-

V

[2]

high-low frequency soft-start

voltage on pin SSHBC

I_{ss(hf)(SSHBC)}

high frequency soft-start current on V_SSHBC< V_{ss(lf-hf)(SSHBC)}

pin SSHBC

charge current

-

160

-

A

discharge current

160

I_{ss(lf)(SSHBC)}

low frequency soft-start current on V_SSHBC> V_{ss(lf-hf)(SSHBC)}

pin SSHBC

charge current

-

40

40

-

A

discharge current

I_{cmr(hf)(SSHBC)}

high frequency CMR current on pin V_SSHBC< V_{ss(lf-hf)(SSHBC)}

1800

SSHBC

low frequency CMR current on pin V_SSHBC> V_{ss(lf-hf)(SSHBC)}

SSHBC discharge only

HBC high frequency sensing, HFP - HBC (RFMAX pin)

discharge only

I_{cmr(lf)(SSHBC)}

-

440

-

A

[2]

V_hfp(RFMAX)

High-frequency protection voltage

on pin RFMAX

1.7

1.83

2

V

HBC overcurrent sensing, OCR/OCP - HBC (SNSCURHBC pin)

V_ocr(HBC)

HBC overcurrent regulation voltage

positive level;

0.45 0.5

0.55

V

HS on + HS-LS non-overlap

time

negative level;

LS on + LS-HS non-overlap

time

0.55 0.5

0.45 V

SSL4120

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Product data sheet

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SSL4120

NXP Semiconductors

Resonant power supply controller IC with PFC for LED lighting

Table 7.

Characteristics …continued

T_amb= 25 C; V_SUPIC= 20 V; V_SUPHV> 40 V; all voltages are measured with respect to SGND; currents are positive when

flowing into the IC; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max Unit

V_ocp(HBC)

HBC overcurrent protection voltage

positive level;

HS on + HS-LS non-overlap

time

0.9

1

1.1

V

negative level;

LS on + LS-HS non-overlap

time

1.1 1

0.9

I_{bstc(SNSCURHBC)max}

maximum boost compensation

current on pin SNSCURHBC

V_SNSBOOST= 1.8 V

source current;

-

170

-

A

V_SNSCURHBC= 0.5 V

sink current;

170

V_SNSCURHBC= 0.5 V

HBC Capacitive Mode Protection (CMP) (HB pin)

t_to(cmr)time-out capacitive mode regulation

-

690

-

ns

[1] The marked levels on this pin are correlated. The voltage difference between the levels has much less spread than the absolute value of

the levels themselves.

[2] Switching level has some hysteresis. The hysteresis falls within the limits.

[3] For a typical application with a compensation network on the COMPPFC pin, as the example in Figure 19.

[4] Minimum required voltage change time for valley recognition on the SNSAUXPFC pin.

[5] Minimum time required between demagnetization detection and V/t = 0 on the SNSAUXPFC pin.

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Product data sheet

Rev. 2 — 1 November 2012

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SSL4120

NXP Semiconductors

Resonant power supply controller IC with PFC for LED lighting

12. Package outline

SO24: plastic small outline package; 24 leads; body width 7.5 mm

SOT137-1

D

E

A

X

c

H

v

M

A

E

y

Z

24

13

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

12

w

detail X

e

M

b

p

0

5

10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

max.

(1)

UNIT

mm

A

b

c

D

E

e

H

L

Q

v

w

y

θ

1

2

3

p

E

p

Z

0.3

0.1

2.45

2.25

0.49

0.36

0.32

0.23

15.6

15.2

7.6

7.4

10.65

10.00

1.1

0.4

1.1

1.0

0.9

0.4

2.65

0.1

0.25

0.01

1.27

0.05

1.4

0.25 0.25

0.01

0.1

8^o

0^o

0.012 0.096

0.004 0.089

0.019 0.013 0.61

0.014 0.009 0.60

0.30

0.29

0.419

0.394

0.043 0.043

0.016 0.039

0.035

0.016

inches

0.055

0.01 0.004

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT137-1

075E05

MS-013

Fig 20. Package outline SOT137 (SO24)

SSL4120

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Product data sheet

Rev. 2 — 1 November 2012

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SSL4120

NXP Semiconductors

Resonant power supply controller IC with PFC for LED lighting

13. Abbreviations

Table 8.

Abbreviations

Acronym Description

ANO

CMOS

CMP

CMR

DMOS

EMI

Adaptive Non-Overlap

Complementary Metal-Oxide-Semiconductor'

Capacitive Mode Protection

Capacitive Mode Regulation

Double-diffused Metal-Oxide-Semiconductor

ElectroMagnetic Interference

HBC

Half-Bridge Converter or Controller. Resonant converter which generates the

regulated output voltage.

HFP

HV

High-Frequency Protection

High-voltage

OCP

OCR

OLP

OTP

OVP

PFC

OverCurrent Protection

OverCurrent Regulation

Open-Loop Protection

OverTemperature Protection

OverVoltage Protection

Power Factor Converter or Controller. Converter which performs the power factor

correction.

UVP

SCP

UnderVoltage Protection

Short-Circuit Protection

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Product data sheet

Rev. 2 — 1 November 2012

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SSL4120

NXP Semiconductors

Resonant power supply controller IC with PFC for LED lighting

14. Revision history

Table 9.

Revision history

Document ID

SSL4120 v.2

SSL4120T v.1

Release date

20121101

Data sheet status

Product data sheet

Objective data sheet

Change notice

Supersedes

-

SSL4120T v.1

-

20120621

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15. Legal information

15.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use — NXP Semiconductors products are not designed,

15.2 Definitions

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

15.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

SSL4120

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Product data sheet

Rev. 2 — 1 November 2012

45 of 48

SSL4120

NXP Semiconductors

Resonant power supply controller IC with PFC for LED lighting

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

SSL4120

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Product data sheet

Rev. 2 — 1 November 2012

46 of 48

SSL4120

NXP Semiconductors

Resonant power supply controller IC with PFC for LED lighting

17. Contents

1

General description. . . . . . . . . . . . . . . . . . . . . . 1

7.7.9

PFC boost overvoltage protection, OVP

boost (SNSBOOST pin). . . . . . . . . . . . . . . . . 20

PFC short circuit/open-loop protection,

SCP/OLP-PFC (SNSBOOST pin) . . . . . . . . . 20

HBC controller . . . . . . . . . . . . . . . . . . . . . . . . 20

HBC high-side and low-side driver

(GATEHS and GATELS pins). . . . . . . . . . . . . 20

HBC boost undervoltage protection, UVP

boost (SNSBOOST pin). . . . . . . . . . . . . . . . . 20

HBC switch control. . . . . . . . . . . . . . . . . . . . . 21

HBC Adaptive Non-Overlap (ANO) time

function (HB pin) . . . . . . . . . . . . . . . . . . . . . . 21

Inductive mode (normal operation) . . . . . . . . 21

Capacitive mode . . . . . . . . . . . . . . . . . . . . . . 22

HBC slope controlled oscillator (CFMIN and

RFMAX pins) . . . . . . . . . . . . . . . . . . . . . . . . . 23

HBC feedback input (SNSFB pin) . . . . . . . . . 25

HBC open-loop protection, OLP-HBC

(SNSFB pin). . . . . . . . . . . . . . . . . . . . . . . . . . 26

HBC soft start (SSHBC/EN pin) . . . . . . . . . . . 26

Soft-start voltage levels . . . . . . . . . . . . . . . . . 27

Soft-start charge and discharge. . . . . . . . . . . 27

Soft-start reset . . . . . . . . . . . . . . . . . . . . . . . . 28

HBC high-frequency protection, HFP-HBC

(RFMAX pin) . . . . . . . . . . . . . . . . . . . . . . . . . 29

HBC overcurrent regulation and protection,

OCR and OCP (SNSCURHBC pin) . . . . . . . . 29

2

Features and benefits . . . . . . . . . . . . . . . . . . . . 2

General features. . . . . . . . . . . . . . . . . . . . . . . . 2

PFC controller features. . . . . . . . . . . . . . . . . . . 2

HBC controller features . . . . . . . . . . . . . . . . . . 2

Protection features . . . . . . . . . . . . . . . . . . . . . . 2

7.7.10

2.1

2.2

2.3

2.4

7.8

7.8.1

3

4

5

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

7.8.2

7.8.3

7.8.4

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

7.8.4.1

7.8.4.2

7.8.5

7

7.1

7.2

7.2.1

7.2.2

7.2.3

7.2.4

7.3

Functional description . . . . . . . . . . . . . . . . . . . 6

Overview of IC modules . . . . . . . . . . . . . . . . . . 6

Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Low-voltage supply input (SUPIC pin) . . . . . . . 7

Regulated supply (SUPREG pin) . . . . . . . . . . . 8

High-side driver floating supply (SUPHS pin). . 9

High-voltage supply input (SUPHV pin) . . . . . . 9

Flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Enable input (SSHBC/EN pin) . . . . . . . . . . . . 11

IC protection . . . . . . . . . . . . . . . . . . . . . . . . . . 12

IC restart and shut-down . . . . . . . . . . . . . . . . 12

Protection and restart timer . . . . . . . . . . . . . . 13

Protection timer . . . . . . . . . . . . . . . . . . . . . . . 13

Restart timer . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Fast shut-down reset (SNSMAINS pin) . . . . . 14

Output overvoltage protection (SNSOUT pin) 14

Output undervoltage protection (SNSOUT pin) 15

OverTemperature Protection (OTP) . . . . . . . . 15

Burst mode operation (SNSOUT pin) . . . . . . . 15

PFC controller. . . . . . . . . . . . . . . . . . . . . . . . . 16

PFC gate driver (GATEPFC pin). . . . . . . . . . . 16

PFC on-time control . . . . . . . . . . . . . . . . . . . . 16

PFC error amplifier (COMPPFC and

SNSBOOST pins). . . . . . . . . . . . . . . . . . . . . . 16

PFC mains compensation (SNSMAINS pin). . 16

PFC demagnetization sensing

(SNSAUXPFC pin) . . . . . . . . . . . . . . . . . . . . . 17

PFC valley sensing (SNSAUXPFC pin) . . . . . 17

PFC frequency and off-time limiting . . . . . . . . 18

PFC soft-start and soft-stop

(SNSCURPFC pin). . . . . . . . . . . . . . . . . . . . . 19

PFC overcurrent regulation, OCR-PFC

(SNSCURPFC pin). . . . . . . . . . . . . . . . . . . . . 19

PFC mains undervoltage protection/brownout

protection, UVP mains (SNSMAINS pin) . . . . 19

7.8.6

7.8.7

7.8.8

7.8.8.1

7.8.8.2

7.8.8.3

7.8.9

7.4

7.5

7.5.1

7.5.2

7.5.2.1

7.5.2.2

7.5.3

7.5.4

7.5.5

7.5.6

7.6

7.8.10

7.8.10.1 Boost voltage compensation . . . . . . . . . . . . . 29

7.8.10.2 Overcurrent regulation, OCR-HBC . . . . . . . . 30

7.8.10.3 Overcurrent protection, OCP-HBC. . . . . . . . . 31

7.8.11

HBC capacitive mode regulation, CMR

(HB pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Protection functions overview . . . . . . . . . . . . 32

7.9

8

7.7

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 33

Thermal characteristics . . . . . . . . . . . . . . . . . 34

Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 34

Application information . . . . . . . . . . . . . . . . . 41

Package outline. . . . . . . . . . . . . . . . . . . . . . . . 42

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 43

Revision history . . . . . . . . . . . . . . . . . . . . . . . 44

7.7.1

7.7.2

7.7.2.1

9

10

11

12

13

14

7.7.2.2

7.7.3

7.7.4

7.7.5

7.7.6

15

Legal information . . . . . . . . . . . . . . . . . . . . . . 45

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 45

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 46

15.1

15.2

15.3

15.4

7.7.7

7.7.8

16

Contact information . . . . . . . . . . . . . . . . . . . . 46

continued >>

SSL4120

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Product data sheet

Rev. 2 — 1 November 2012

47 of 48

SSL4120

NXP Semiconductors

Resonant power supply controller IC with PFC for LED lighting

17

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 1 November 2012

Document identifier: SSL4120


型号：	SSL4120T/1,518
厂家：	NXP
描述：	Resonant power supply controller IC with PFC for LED lighting SOP 24-Pin 功率因数校正
文件：	总48页 (文件大小：650K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SSL4120T/1,518 [NXP]

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