SSTU32864EC/G,518 [NXP]
SSTU32864 - 1.8 V configurable registered buffer for DDR2 RDIMM applications BGA 96-Pin;型号: | SSTU32864EC/G,518 |
厂家: | NXP |
描述: | SSTU32864 - 1.8 V configurable registered buffer for DDR2 RDIMM applications BGA 96-Pin 双倍数据速率 逻辑集成电路 触发器 |
文件: | 总21页 (文件大小:117K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SSTU32864
1.8 V configurable registered buffer for DDR2 RDIMM
applications
Rev. 02 — 22 October 2004
Product data sheet
1. General description
The SSTU32864 is a 25-bit 1:1 or 14-bit 1:2 configurable registered buffer designed for
1.7 V to 1.9 V VDD operation.
All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The
control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized
to drive the DDR2 DIMM load.
The SSTU32864 operates from a differential clock (CK and CK). Data are registered at
the crossing of CK going HIGH, and CK going LOW.
The C0 input controls the pinout configuration of the 1:2 pinout from A configuration (when
LOW) to B configuration (when HIGH). The C1 input controls the pinout configuration from
25-bit 1:1 (when LOW) to 14-bit 1:2 (when HIGH).
The device supports low-power standby operation. When the reset input (RESET) is LOW,
the differential input receivers are disabled, and undriven (floating) data, clock and
reference voltage (VREF) inputs are allowed. In addition, when RESET is LOW all registers
are reset, and all outputs are forced LOW. The LVCMOS RESET and Cn inputs must
always be held at a valid logic HIGH or LOW level.
To ensure defined outputs from the register before a stable clock has been supplied,
RESET must be held in the LOW state during power-up.
In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with
respect to CK and CK. Therefore, no timing relationship can be guaranteed between the
two. When entering reset, the register will be cleared and the data outputs will be driven
LOW quickly, relative to the time to disable the differential input receivers. However, when
coming out of reset, the register will become active quickly, relative to the time to enable
the differential input receivers. As long as the data inputs are LOW, and the clock is stable
during the time from the LOW-to-HIGH transition of RESET until the input receivers are
fully enabled, the design of the SSTU32864 must ensure that the outputs will remain
LOW, thus ensuring no glitches on the output.
The device monitors both DCS and CSR inputs and will gate the Qn outputs from
changing states when both DCS and CSR inputs are HIGH. If either DCS or CSR input is
LOW, the Qn outputs will function normally. The RESET input has priority over the DCS
and CSR control and will force the outputs LOW. If the DCS-control functionality is not
desired, then the CSR input can be hardwired to ground, in which case the setup time
requirement for DCS would be the same as for the other Dn data inputs.
The SSTU32864 is available in a 96-ball, low profile fine-pitch ball grid array (LFBGA96)
package.
SSTU32864
Philips Semiconductors
1.8 V configurable registered buffer for DDR2 RDIMM applications
2. Features
■ Configurable register supporting DDR2 Registered DIMM applications
■ Configurable to 25-bit 1:1 mode or 14-bit 1:2 mode
■ Controlled output impedance drivers enable optimal signal integrity and speed
■ Exceeds JESD82-7 speed performance (1.8 ns max. single-bit switching propagation
delay; 2.0 ns max. mass-switching)
■ Supports up to 450 MHz clock frequency of operation
■ Optimized pinout for high-density DDR2 module design
■ Chip-selects minimize power consumption by gating data outputs from changing state
■ Supports SSTL_18 data inputs
■ Differential clock (CK and CK) inputs
■ Supports LVCMOS switching levels on the control and RESET inputs
■ Single 1.8 V supply operation
■ Available in 96-ball, 13.5 × 5.5 mm, 0.8 mm ball pitch LFBGA package
3. Ordering information
Table 1:
Ordering information
Tamb = 0 °C to +70 °C.
Type number
Solder process
Package
Name
Description
Version
SSTU32864EC/G Pb-free (SnAgCu
solder ball compound)
LFBGA96
plastic low profile fine-pitch ball grid array package; SOT536-1
96 balls; body 13.5 × 5.5 × 1.05 mm
SSTU32864EC
SnPb solder ball
compound
LFBGA96
plastic low profile fine-pitch ball grid array package; SOT536-1
96 balls; body 13.5 × 5.5 × 1.05 mm
9397 750 14092
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 02 — 22 October 2004
2 of 21
SSTU32864
Philips Semiconductors
1.8 V configurable registered buffer for DDR2 RDIMM applications
4. Functional diagram
RESET
CK
CK
SSTU32864
V
REF
DCKE
DODT
DCS
CSR
D1
1D
C1
QCKEA
QCKEB
(1)
(1)
R
1D
QODTA
QODTB
C1
R
1D
QCSA
C1
(1)
QCSB
R
0
1
1D
Q1A
C1
(1)
Q1B
R
002aaa954
to other channels
(1) Disabled in 1:1 configuration.
Fig 1. Functional diagram of SSTU32864; 1:2 mode (positive logic)
9397 750 14092
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 02 — 22 October 2004
3 of 21
SSTU32864
Philips Semiconductors
1.8 V configurable registered buffer for DDR2 RDIMM applications
5. Pinning information
5.1 Pinning
SSTU32864EC/G
ball A1
SSTU32864EC
index area
1 2 3 4 5 6
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
002aab107
Transparent top view
Fig 2. Pin configuration for LFBGA96
1
DCKE
D2
2
n.c.
3
4
5
QCKE
Q2
6
A
B
C
D
E
F
V
V
d.n.u.
Q15
Q16
d.n.u.
Q17
Q18
C0
REF
DD
D15
D16
n.c.
GND
GND
D3
V
V
Q3
DD
DD
DODT
D5
GND
GND
QODT
Q5
D17
D18
RESET
DCS
CSR
D19
D20
D21
D22
D23
D24
D25
V
V
DD
DD
D6
GND
GND
Q6
G
H
J
n.c.
CK
V
V
C1
DD
DD
GND
GND
QCS
ZOH
Q8
d.n.u.
ZOL
Q19
Q20
Q21
Q22
Q23
Q24
CK
V
V
DD
DD
K
L
D8
GND
GND
D9
V
V
Q9
DD
DD
M
N
P
R
T
D10
D11
D12
D13
D14
GND
GND
Q10
Q11
Q12
Q13
Q14
V
V
DD
DD
GND
GND
V
V
V
DD
DD
DD
V
Q25
REF
002aaa955
Fig 3. Ball mapping; 1:1 register (C0 = 0, C1 = 0); top view
Rev. 02 — 22 October 2004
9397 750 14092
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
4 of 21
SSTU32864
Philips Semiconductors
1.8 V configurable registered buffer for DDR2 RDIMM applications
1
DCKE
D2
2
3
4
5
6
A
B
C
D
E
F
n.c.
V
V
QCKEA QCKEB
REF
DD
d.n.u.
d.n.u.
n.c.
GND
GND
Q2A
Q3A
Q2B
Q3B
D3
V
V
DD
DD
DODT
D5
GND
GND
QODTA QODTB
d.n.u.
d.n.u.
RESET
DCS
V
V
Q5A
Q6A
Q5B
Q6B
DD
DD
D6
GND
GND
G
H
J
n.c.
CK
V
V
C1
C0
DD
DD
GND
GND
QCSA
ZOH
Q8A
QCSB
ZOL
CK
CSR
V
V
DD
DD
K
L
D8
d.n.u.
d.n.u.
d.n.u.
d.n.u.
d.n.u.
d.n.u.
d.n.u.
GND
GND
Q8B
D9
V
V
Q9A
Q9B
DD
DD
M
N
P
R
T
D10
D11
D12
D13
D14
GND
GND
Q10A
Q11A
Q12A
Q13A
Q14A
Q10B
Q11B
Q12B
Q13B
V
V
DD
DD
GND
GND
V
V
V
DD
DD
DD
V
Q14B
REF
002aaa956
Fig 4. Ball mapping; 1:2 register A (C0 = 0, C1 = 1); top view
1
D1
2
3
4
5
6
A
B
C
D
E
F
n.c.
V
V
Q1A
Q2A
Q3A
Q4A
Q5A
Q6A
C1
Q1B
Q2B
Q3B
Q4B
Q5B
Q6B
C0
REF
DD
D2
d.n.u.
d.n.u.
n.c.
GND
GND
D3
V
V
DD
DD
D4
GND
GND
D5
d.n.u.
d.n.u.
RESET
DCS
V
V
DD
DD
D6
GND
GND
G
H
J
n.c.
CK
V
V
DD
DD
GND
GND
QCSA
ZOH
Q8A
Q9A
Q10A
QCSB
ZOL
Q8B
Q9B
Q10B
CK
CSR
V
V
DD
DD
K
L
D8
d.n.u.
d.n.u.
d.n.u.
d.n.u.
d.n.u.
d.n.u.
d.n.u.
GND
GND
D9
V
V
DD
DD
M
N
P
R
T
D10
DODT
D12
D13
DCKE
GND
GND
V
V
QODTA QODTB
DD
DD
GND
GND
Q12A
Q13A
Q12B
Q13B
V
V
V
DD
DD
DD
V
QCKEA QCKEB
002aaa957
REF
Fig 5. Ball mapping; 1:2 register B (C0 = 1, C1 = 1); top view
9397 750 14092
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 02 — 22 October 2004
5 of 21
SSTU32864
Philips Semiconductors
1.8 V configurable registered buffer for DDR2 RDIMM applications
5.2 Pin description
Table 2:
Symbol
GND
Pin description
Pin
Type
Description
B3, B4, D3, D4,
F3, F4, H3, H4, K3,
K4, M3, M4, P3,
P4
ground input
ground
VDD
A4, C3, C4, E3,
E4, G3, G4, J3, J4,
L3, L4, N3, N4, R3,
R4, T4
1.8 V nominal
power supply voltage
VREF
ZOH
ZOL
A3, T3
J5
0.9 V nominal
input
input reference voltage
reserved for future use
reserved for future use
positive master clock input
negative master clock input
configuration control inputs
J6
input
CK
H1
differential input
differential input
LVCMOS inputs
LVCMOS input
CK
J1
C0, C1
RESET
G6, G5
G2
Asynchronous reset input. Resets registers and disables VREF
data and clock differential-input receivers.
CSR, DCS
D1 to D25
DODT
J2, H2
SSTL_18 input
SSTL_18 input
SSTL_18 input
SSTL_18 input
1.8 V CMOS
Chip select inputs. Disables data outputs switching when both
inputs are HIGH. [2]
[1]
Data inputs. Clocked in on the crossing of the rising edge of
CK and the falling edge of CK.
[1]
[1]
[1]
The outputs of this register will not be suspended by DCS and
CSR control.
DCKE
The outputs of this register will not be suspended by DCS and
CSR control.
The outputs that are suspended by DCS and CSR control. [3]
Q1 to Q25,
Q1A to Q14A,
Q1B to Q14B
[1]
[1]
[1]
QCS, QCSA,
QCSB
1.8 V CMOS
Data outputs that will not be suspended by DCS and CSR
control.
QODT, QODTA,
QODTB
1.8 V CMOS
Data outputs that will not be suspended by DCS and CSR
control.
QCKE, QCKEA,
QCKEB
1.8 V CMOS
Data outputs that will not be suspended by DCS and CSR
control.
n.c.
A2, D2, G1
-
-
Not connected. Ball present but no internal connection to the
die.
[1]
d.n.u.
Do-not-use. Ball internally connected to the die which should
be left open-circuit.
[1] Depends on configuration. Refer to Figure 3, Figure 4, and Figure 5 for ball number.
[2] Configurations:
Data inputs = D2, D3, D5, D6, D8 to D25 when C0 = 0 and C1 = 0.
Data inputs = D2, D3, D5, D6, D8 to D14 when C0 = 0 and C1 = 1.
Data inputs = D1 to D6, D8 to D10, D12, D13 when C0 = 1 and C1 = 1.
[3] Configurations:
Data outputs = Q2, Q3, Q5, Q6, Q8 to Q25 when C0 = 0 and C1 = 0.
Data outputs = Q2, Q3, Q5, Q6, Q8 to Q14 when C0 = 0 and C1 = 1.
9397 750 14092
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 02 — 22 October 2004
6 of 21
SSTU32864
Philips Semiconductors
1.8 V configurable registered buffer for DDR2 RDIMM applications
Data outputs = Q1 to Q6, Q8 to Q10, Q12, Q13 when C0 = 1 and C1 = 1.
6. Functional description
6.1 Function table
Table 3:
Function table (each flip-flop)
Inputs
Outputs [1]
QCS
RESET
DCS
CSR
CK
CK
Dn,
DODT,
DCKE
Qn
QODT,
QCKE
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
↑
↓
L
H
X
L
L
H
L
L
L
H
↑
↓
L
L
L or H
L or H
Q0
L
Q0
L
Q0
L
L
H
H
H
L
↑
↓
L
↑
↓
H
X
L
H
L
H
L
L or H
L or H
Q0
L
Q0
H
Q0
L
H
H
H
H
H
H
↑
↓
L
↑
L or H
↑
↓
L or H
↓
H
X
L
H
H
H
L
Q0
Q0
Q0
Q0
L
Q0
H
Q0
L
H
H
H
↑
↓
H
X
H
H
L or H
L or H
Q0
L
Q0
L
X or
X or
X or
X or
X or
floating
floating
floating
floating
floating
[1] Q0 is the previous state of the associated output.
H — HIGH voltage level
L — LOW voltage level
↓ — HIGH-to-LOW transition
↑ — LOW-to-HIGH transition
X — Don’t care
9397 750 14092
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 02 — 22 October 2004
7 of 21
SSTU32864
Philips Semiconductors
1.8 V configurable registered buffer for DDR2 RDIMM applications
7. Limiting values
Table 4:
In accordance with the Absolute Maximum Rating System (IEC 60134).
Limiting values[1]
Symbol
VDD
VI
Parameter
Conditions
Min
Max
Unit
V
supply voltage
−0.5
−0.5[2]
−0.5[2]
+2.5
receiver input voltage
driver output voltage
input clamp current
output clamp current
continuous output current
continuous current through each
+2.5[3]
VDD + 0.5[3]
±50
V
VO
V
IIK
VI < 0 V or VI > VDD
VO < 0 V or VO > VDD
0 V < VO < VDD
-
-
-
-
mA
mA
mA
mA
IOK
±50
IO
±50
ICCC
±100
VDD or GND pin
Tstg
storage temperature
−65
+150
°C
[1] Stresses beyond those listed under ‘absolute maximum ratings’ may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under ‘recommended operating
conditions’ is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
[2] The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
[3] This value is limited to 2.5 V maximum.
9397 750 14092
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 02 — 22 October 2004
8 of 21
SSTU32864
Philips Semiconductors
1.8 V configurable registered buffer for DDR2 RDIMM applications
8. Recommended operating conditions
Table 5:
Symbol
VDD
Operating conditions
Parameter
Conditions
Min
Typ
Max
Unit
V
supply voltage
1.7
-
1.9
VREF
VTT
reference voltage
termination voltage
input voltage
0.49 × VDD
0.50 × VDD 0.51 × VDD
V
VREF − 40 mV
VREF
VREF + 40 mV
V
VI
0
-
-
VDD
-
V
VIH(AC)
AC HIGH-level input voltage data inputs (Dn),
CSR
VREF + 250 mV
V
VIL(AC)
VIH(DC)
VIL(DC)
AC LOW-level input voltage data inputs (Dn),
CSR
-
-
-
-
V
-
REF − 250 mV
V
V
V
DC HIGH-level input voltage data inputs (Dn),
CSR
VREF + 125 mV
-
DC LOW-level input voltage data inputs (Dn),
CSR
V
REF − 125 mV
[1]
[1]
[2]
VIH
VIL
HIGH-level input voltage
LOW-level input voltage
RESET, Cn
RESET, Cn
0.65 × VDD
-
-
-
VDD
V
V
V
-
0.35 × VDD
1.125
VICR
common mode input voltage CK, CK
range
0.675
[2]
VID
IOH
IOL
differential input voltage
HIGH-level output current
LOW-level output current
CK, CK
600
-
-
-
-
-
mV
mA
mA
°C
-
−8
8
-
Tamb
operating ambient
0
+70
temperature in free air
[1] The RESET and Cn inputs of the device must be held at valid logic levels (not floating) to ensure proper device operation.
[2] The differential inputs must not be floating, unless RESET is LOW.
9397 750 14092
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 02 — 22 October 2004
9 of 21
SSTU32864
Philips Semiconductors
1.8 V configurable registered buffer for DDR2 RDIMM applications
9. Characteristics
Table 6:
Recommended operating conditions, unless otherwise specified. Voltages are referenced to GND (ground = 0 V).
amb = 0 °C to +70 °C.
Characteristics
T
Symbol Parameter
Conditions
Min
1.2
-
Typ
Max
-
Unit
V
VOH
VOL
II
HIGH-level output voltage
IOH = −6 mA; VDD = 1.7 V
IOL = 6 mA; VDD = 1.7 V
all inputs; VI = VDD or GND;
-
-
-
LOW-level output voltage
input current
0.5
+5
V
−5
µA
V
DD = 1.9 V
RESET = GND; IO = 0 mA;
DD = 1.9 V
RESET = VDD; IO = 0 mA;
DD = 1.9 V;
VI = VIH(AC) or VIL(AC)
RESET = VDD
IDD
static standby current
static operating current
-
-
-
-
100
40
µA
V
mA
V
IDDD
dynamic operating current per
MHz, clock only
;
-
-
16
11
-
-
µA
µA
VI = VIH(AC) or VIL(AC); CK and
CK switching at 50 % duty cycle.
IO = 0 mA; VDD = 1.9 V
dynamic operating current per
MHz, per each data input,
1:1 mode
RESET = VDD;
VI = VIH(AC) or VIL(AC); CK and
CK switching at 50 % duty cycle.
One data input switching at half
clock frequency, 50 % duty
cycle. IO = 0 mA; VDD = 1.9 V
dynamic operating current per
MHz, per each data input,
1:2 mode
RESET = VDD
;
-
19
-
µA
VI = VIH(AC) or VIL(AC); CK and
CK switching at 50 % duty cycle.
One data input switching at half
clock frequency, 50 % duty
cycle. IO = 0 mA; VDD = 1.9 V
Ci
input capacitance, data inputs,
CSR
VI = VREF ± 250 mV;
2.5
2
-
-
-
3.5
3
pF
pF
pF
V
DD = 1.8 V
VICR = 0.9 V; VID = 600 mV;
DD = 1.8 V
input capacitance, CK and CK
V
input capacitance, RESET
VI = VDD or GND; VDD = 1.8 V
2
4
9397 750 14092
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 02 — 22 October 2004
10 of 21
SSTU32864
Philips Semiconductors
1.8 V configurable registered buffer for DDR2 RDIMM applications
Table 7:
Timing requirements
Recommended operating conditions; VDD = 1.8 V ± 0.1 V; Tamb = 0 °C to +70 °C; unless otherwise specified.
See Figure 6 through Figure 11.
Symbol
fclock
Parameter
Conditions
Min
Typ
Max
450
-
Unit
MHz
ns
clock frequency
-
-
-
tW
pulse duration, CK, CK HIGH or
LOW
1
[1] [2]
[1] [3]
tACT
tINACT
tsu
differential inputs active time
differential inputs inactive time
set-up time
-
-
-
-
10
15
-
ns
ns
ns
-
DCS before CK ↑, CK ↓,
0.7
CSR HIGH
DCS before CK ↑, CK ↓,
CSR LOW
0.5
0.5
0.5
-
-
-
-
-
-
ns
ns
ns
CSR, ODT, CKE, and data
before CK ↑, CK ↓
th
hold time
DCS, CSR, ODT, CKE,
and data after CK ↑, CK ↓
[1] This parameter is not necessarily production tested.
[2] Data inputs must be active below a minimum time of tACT(max) after RESET is taken HIGH.
[3] Data and clock inputs must be held at valid levels (not floating) a minimum time of tINACT(max) after RESET is taken LOW.
Table 8:
Switching characteristics
Recommended operating conditions; VDD = 1.8 V ± 0.1 V; Tamb = 0 °C to +70 °C;
Class I, VREF = VTT = VDD × 0.5 and CL = 10 pF; unless otherwise specified. See Figure 6 through Figure 11.
Symbol
fMAX
Parameter
Conditions
Min
450
1.41
-
Typ
Max
-
Unit
MHz
ns
maximum input clock frequency
propagation delay
-
-
-
[1]
tPDM
CK and CK to output
CK and CK to output
1.8
2.0
[1] [2]
tPDMSS
propagation delay, simultaneous
switching
ns
tPHL
propagation delay
RESET to output
-
-
3
ns
[1] Includes 350 ps of test-load transmission line delay.
[2] This parameter is not necessarily production tested.
Table 9:
Output edge rates
Recommended operating conditions, unless otherwise specified. VDD = 1.8 V ± 0.1 V
Symbol
dV/dt_r
dV/dt_f
dV/dt_∆
Parameter
Conditions
Min
Typ
Max
Unit
V/ns
V/ns
V/ns
rising edge slew rate
falling edge slew rate
1
1
-
-
-
-
4
4
1
absolute difference between dV/dt_r
and dV/dt_f
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Product data sheet
Rev. 02 — 22 October 2004
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10. Test information
10.1 Test circuit
All input pulses are supplied by generators having the following characteristics:
PRR ≤ 10 MHz; Z0 = 50 Ω; input slew rate = 1 V/ns ± 20 %, unless otherwise specified.
The outputs are measured one at a time with one transition per measurement.
V
DD
DUT
R
= 1000 Ω
= 1000 Ω
L
T
= 50 Ω
T
= 350 ps, 50 Ω
L
L
CK
CK
CK inputs
OUT
(1)
= 30 pF
C
L
R
L
test point
R
L
= 100 Ω
002aaa371
test point
(1) CL includes probe and jig capacitance.
Fig 6. Load circuit
LVCMOS
V
DD
RESET
V
/2
DD
V
/2
DD
0 V
t
t
ACT
INACT
90 %
(1)
DD
I
10 %
002aaa372
(1) IDD tested with clock and data inputs held at VDD or GND, and IO = 0 mA.
Fig 7. Voltage and current waveforms; inputs active and inactive times
t
W
V
V
IH
IL
V
input
V
V
ICR
ID
ICR
002aaa373
VID = 600 mV
VIH = VREF + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs.
VIL = VREF − 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
Fig 8. Voltage waveforms; pulse duration
9397 750 14092
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Product data sheet
Rev. 02 — 22 October 2004
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Philips Semiconductors
1.8 V configurable registered buffer for DDR2 RDIMM applications
CK
V
V
ICR
ID
CK
t
t
h
su
V
V
IH
IL
input
V
REF
V
REF
002aaa374
VID = 600 mV
VREF = VDD/2
VIH = VREF + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs.
VIL = VREF − 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
Fig 9. Voltage waveforms; set-up and hold times
CK
V
V
V
ICR
ICR
i(p-p)
CK
t
t
PHL
PLH
V
V
OH
OL
V
output
TT
002aaa375
tPLH and tPHL are the same as tPD
.
Fig 10. Voltage waveforms; propagation delay times (clock to output)
LVCMOS
V
V
V
V
IH
RESET
V
/2
DD
IL
t
PHL
OH
OL
output
V
TT
002aaa376
tPLH and tPHL are the same as tPD
.
VIH = VREF + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs.
VIL = VREF − 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
Fig 11. Voltage waveforms; propagation delay times (reset to output)
9397 750 14092
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Product data sheet
Rev. 02 — 22 October 2004
13 of 21
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Philips Semiconductors
1.8 V configurable registered buffer for DDR2 RDIMM applications
10.2 Output slew rate measurement
VDD = 1.8 V ± 0.1 V.
All input pulses are supplied by generators having the following characteristics:
PRR ≤ 10 MHz; Z0 = 50 Ω; input slew rate = 1 V/ns ± 20 %, unless otherwise specified.
V
DD
R
DUT
= 50 Ω
L
OUT
test point
002aaa377
(1)
= 10 pF
C
L
(1) CL includes probe and jig capacitance.
Fig 12. Load circuit, HIGH-to-LOW slew measurement
output
V
OH
80 %
dv_f
20 %
V
OL
dt_f
002aaa378
Fig 13. Voltage waveforms, HIGH-to-LOW slew rate measurement
DUT
OUT
test point
(1)
= 10 pF
C
L
R
L
= 50 Ω
002aaa379
(1) CL includes probe and jig capacitance.
Fig 14. Load circuit, LOW-to-HIGH slew measurement
dt_r
V
V
OH
80 %
dv_r
20 %
output
OL
002aaa380
Fig 15. Voltage waveforms, LOW-to-HIGH slew rate measurement
9397 750 14092
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 02 — 22 October 2004
14 of 21
SSTU32864
Philips Semiconductors
1.8 V configurable registered buffer for DDR2 RDIMM applications
11. Package outline
LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm SOT536-1
B
A
D
ball A1
index area
A
2
A
E
A
1
detail X
e
1
C
1/2 e
y
y
v M
w M
C
C
A B
C
1
e
b
T
R
P
N
e
M
L
K
J
H
G
F
e
2
1/2 e
E
D
C
B
A
ball A1
index area
1
2
3
4
5
6
X
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
A
b
e
e
e
v
w
y
y
1
D
E
1
2
1
2
max.
0.41
0.31
1.2
0.9
0.51
0.41
5.6
5.4
13.6
13.4
mm
1.5
4
12
0.1
0.2
0.8
0.15
0.1
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
00-03-04
03-02-05
SOT536-1
Fig 16. Package outline SOT536-1 (LFBGA96)
9397 750 14092
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 02 — 22 October 2004
15 of 21
SSTU32864
Philips Semiconductors
1.8 V configurable registered buffer for DDR2 RDIMM applications
12. Soldering
12.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account of
soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages
(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface mount IC packages. Wave
soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is recommended.
12.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and
binding agent) to be applied to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement. Driven by legislation and
environmental forces the worldwide use of lead-free solder pastes is increasing.
Several methods exist for reflowing; for example, convection or convection/infrared
heating in a conveyor type oven. Throughput times (preheating, soldering and cooling)
vary between 100 seconds and 200 seconds depending on heating method.
Typical reflow peak temperatures range from 215 °C to 270 °C depending on solder paste
material. The top-surface temperature of the packages should preferably be kept:
• below 225 °C (SnPb process) or below 245 °C (Pb-free process)
– for all BGA, HTSSON..T and SSOP..T packages
– for packages with a thickness ≥ 2.5 mm
– for packages with a thickness < 2.5 mm and a volume ≥ 350 mm3 so called
thick/large packages.
• below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with a
thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages.
Moisture sensitivity precautions, as indicated on packing, must be respected at all times.
12.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices
(SMDs) or printed-circuit boards with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering method was specifically
developed.
If wave soldering is used the following conditions must be observed for optimal results:
• Use a double-wave soldering method comprising a turbulent wave with high upward
pressure followed by a smooth laminar wave.
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be
parallel to the transport direction of the printed-circuit board;
9397 750 14092
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Product data sheet
Rev. 02 — 22 October 2004
16 of 21
SSTU32864
Philips Semiconductors
1.8 V configurable registered buffer for DDR2 RDIMM applications
– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the
transport direction of the printed-circuit board.
The footprint must incorporate solder thieves at the downstream end.
• For packages with leads on four sides, the footprint must be placed at a 45° angle to
the transport direction of the printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement and before soldering, the package must be fixed with a droplet of
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the adhesive is cured.
Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C
or 265 °C, depending on solder material applied, SnPb or Pb-free respectively.
A mildly-activated flux will eliminate the need for removal of corrosive residues in most
applications.
12.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage
(24 V or less) soldering iron applied to the flat part of the lead. Contact time must be
limited to 10 seconds at up to 300 °C.
When using a dedicated tool, all other leads can be soldered in one operation within
2 seconds to 5 seconds between 270 °C and 320 °C.
12.5 Package related soldering information
Table 10: Suitability of surface mount IC packages for wave and reflow soldering methods
Package [1]
Soldering method
Wave
Reflow[2]
BGA, HTSSON..T[3], LBGA, LFBGA, SQFP,
SSOP..T[3], TFBGA, VFBGA, XSON
not suitable
suitable
DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP,
HSQFP, HSSON, HTQFP, HTSSOP, HVQFN,
HVSON, SMS
not suitable[4]
suitable
PLCC[5], SO, SOJ
suitable
suitable
LQFP, QFP, TQFP
not recommended[5] [6]
not recommended[7]
not suitable
suitable
SSOP, TSSOP, VSO, VSSOP
CWQCCN..L[8], PMFP[9], WQCCN..L[8]
suitable
not suitable
[1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026);
order a copy from your Philips Semiconductors sales office.
[2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the
maximum temperature (with respect to time) and body size of the package, there is a risk that internal or
external package cracks may occur due to vaporization of the moisture in them (the so called popcorn
effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit
Packages; Section: Packing Methods.
[3] These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no
account be processed through more than one soldering cycle or subjected to infrared reflow soldering with
peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package
body peak temperature must be kept as low as possible.
9397 750 14092
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 02 — 22 October 2004
17 of 21
SSTU32864
Philips Semiconductors
1.8 V configurable registered buffer for DDR2 RDIMM applications
[4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the
solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink
on the top side, the solder might be deposited on the heatsink surface.
[5] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave
direction. The package footprint must incorporate solder thieves downstream and at the side corners.
[6] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
[7] Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger
than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
[8] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered
pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by
using a hot bar soldering process. The appropriate soldering profile can be provided on request.
[9] Hot bar soldering or manual soldering is suitable for PMFP packages.
13. Abbreviations
Table 11: Abbreviations
Acronym
CMOS
DDR
Description
Complementary Metal Oxide Silicon
Double Data Rate
DIMM
Dual In-line Memory Module
JEDEC
LFBGA
LVCMOS
PRR
Joint Electron Device Engineering Council
Low profile Fine-pitch Ball Grid Array
Low Voltage Complementary Metal Oxide Silicon
Pulse Repetition Rate
RDIMM
SSTL
Registered Dual In-line Memory Module
Stub Series Terminated Logic
9397 750 14092
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 02 — 22 October 2004
18 of 21
SSTU32864
Philips Semiconductors
1.8 V configurable registered buffer for DDR2 RDIMM applications
14. Revision history
Table 12: Revision history
Document ID
SSTU32864_2
Modifications:
Release date Data sheet status
20041022 Product data sheet
Change notice Doc. number
Supersedes
-
9397 750 14092 SSTU32864-01
• The format of this data sheet has been redesigned to comply with the new presentation and
information standard of Philips Semiconductors.
• Data sheet status changed to ‘Product data sheet’.
• Table 2 “Pin description”
–
–
–
(new) Table note [1] added
pin (ball) numbers added
changed pin name ‘DNU’ to ‘d.n.u.’
• Table 3 “Function table (each flip-flop)”
–
–
–
moved to Section 6.1 on page 7
added Table note 1 and its reference at ‘Outputs’
corrected column sub-headings under ‘Outputs’
• Table 4 “Limiting values[1]”: Symbol Vi changed to VI; Symbol Vo changed to VO
• Table 5 “Operating conditions”:
–
–
–
changed VIH (for data inputs) to VIH(AC) and VIH(DC); condition changed to ‘data inputs (Dn)’
changed VIL (for data inputs) to VIL(AC) and VIL(DC); condition changed to ‘data inputs (Dn)’
Table note split into 2 notes; references added.
• Table 6 “Characteristics”
–
changed IDDD Parameter from “dynamic operating current ...” to “dynamic operating current
per MHz ...”; change Unit from “µA/MHz” to “µA”.
• Table 7 “Timing requirements”:
–
–
–
changed symbol fCLOCK to fclock
changed symbol tSU to tsu
changed symbol tH to th
• Table 8 “Switching characteristics”:
–
changed tPDM and tPDMSS Conditions from ‘clock to output’ to ‘CK and CK to output’
–
changed tPHL Condition from ‘reset to output’ to ‘RESET to output’
• Table 9 “Output edge rates”: deleted Table note [1]
• Section 10.1 “Test circuit”: titles for Figure 10 and Figure 11 modified.
• Added Section 13 “Abbreviations”
SSTU32864-01
20040712
Objective data
-
9397 750 13339
-
9397 750 14092
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 02 — 22 October 2004
19 of 21
SSTU32864
Philips Semiconductors
1.8 V configurable registered buffer for DDR2 RDIMM applications
15. Data sheet status
Level Data sheet status[1] Product status[2] [3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
[2]
Please consult the most recently issued data sheet before initiating or completing a design.
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
16. Definitions
17. Disclaimers
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
18. Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
9397 750 14092
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 02 — 22 October 2004
20 of 21
SSTU32864
Philips Semiconductors
1.8 V configurable registered buffer for DDR2 RDIMM applications
19. Contents
1
2
3
4
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
6
6.1
7
Functional description . . . . . . . . . . . . . . . . . . . 7
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8
Recommended operating conditions. . . . . . . . 9
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 10
8
9
10
10.1
10.2
Test information. . . . . . . . . . . . . . . . . . . . . . . . 12
Test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Output slew rate measurement. . . . . . . . . . . . 14
11
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15
12
12.1
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Introduction to soldering surface mount
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 16
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 16
Manual soldering . . . . . . . . . . . . . . . . . . . . . . 17
Package related soldering information . . . . . . 17
12.2
12.3
12.4
12.5
13
14
15
16
17
18
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 19
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 20
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Contact information . . . . . . . . . . . . . . . . . . . . 20
© Koninklijke Philips Electronics N.V. 2004
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.
Date of release: 22 October 2004
Document number: 9397 750 14092
Published in The Netherlands
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