SSTU32866EC/G,518 [NXP]
SSTU32866 - 1.8 V 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity for DDR2 RDIMM applications BGA 96-Pin;型号: | SSTU32866EC/G,518 |
厂家: | NXP |
描述: | SSTU32866 - 1.8 V 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity for DDR2 RDIMM applications BGA 96-Pin 双倍数据速率 逻辑集成电路 触发器 |
文件: | 总29页 (文件大小:155K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SSTU32866
1.8 V 25-bit 1:1 or 14-bit 1:2 configurable registered buffer
with parity for DDR2 RDIMM applications
Rev. 02 — 11 November 2004
Product data sheet
1. General description
The SSTU32866 is a 1.8 V configurable register specifically designed for use on DDR2
memory modules requiring a parity checking function. It is defined in accordance with the
JEDEC JESD82-7 standard for the SSTU32864 registered buffer, while adding the parity
checking function in a compatible pinout. The JEDEC standard for SSTU32866 is pending
publication. The register is configurable (using configuration pins C0 and C1) to two
topologies: 25-bit 1:1 or 14-bit 1:2, and in the latter configuration can be designated as
Register A or Register B on the DIMM.
The SSTU32866 accepts a parity bit from the memory controller on its parity bit (PAR_IN)
input, compares it with the data received on the DIMM-independent D-inputs and
indicates whether a parity error has occurred on its open-drain QERR pin (active-LOW).
The convention is even parity, that is, valid parity is defined as an even number of ones
across the DIMM-independent data inputs combined with the parity input bit.
The SSTU32866 is packaged in a 96-ball, 6 × 16 grid, 0.8 mm ball pitch LFBGA package
(13.5 mm by 5.5 mm).
2. Features
■ Configurable register supporting DDR2 Registered DIMM applications
■ Configurable to 25-bit 1:1 mode or 14-bit 1:2 mode
■ Controlled output impedance drivers enable optimal signal integrity and speed
■ Exceeds JESD82-7 speed performance (1.8 ns max. single-bit switching propagation
delay; 2.0 ns max. mass-switching)
■ Supports up to 450 MHz clock frequency of operation
■ Optimized pinout for high-density DDR2 module design
■ Chip-selects minimize power consumption by gating data outputs from changing state
■ Supports SSTL_18 data inputs
■ Checks parity on the DIMM-independent data inputs
■ Partial parity output and input allows cascading of two SSTU32866s for correct parity
error processing
■ Differential clock (CK and CK) inputs
■ Supports LVCMOS switching levels on the control and RESET inputs
■ Single 1.8 V supply operation
■ Available in 96-ball, 13.5 × 5.5 mm, 0.8 mm ball pitch LFBGA package
SSTU32866
Philips Semiconductors
1.8 V DDR2 configurable registered buffer with parity
3. Applications
■ DDR2 registered DIMMs desiring parity checking functionality
4. Ordering information
Table 1:
Ordering information
Tamb = 0 °C to +70 °C.
Type number Solder process
Package
Name
Description
Version
SSTU32866EC/G Pb-free (SnAgCu solder LFBGA96 plastic low profile fine-pitch ball grid array package; SOT536-1
ball compound)
96 balls; body 13.5 × 5.5 × 1.05 mm
SSTU32866EC
SnPb solder ball
compound
LFBGA96 plastic low profile fine-pitch ball grid array package; SOT536-1
96 balls; body 13.5 × 5.5 × 1.05 mm
9397 750 14181
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 02 — 11 November 2004
2 of 29
SSTU32866
Philips Semiconductors
1.8 V DDR2 configurable registered buffer with parity
5. Functional diagram
RESET
CK
CK
SSTU32866
V
REF
DCKE
DODT
DCS
CSR
D2
1D
C1
QCKEA
QCKEB
(1)
(1)
R
1D
QODTA
QODTB
C1
R
1D
QCSA
C1
(1)
QCSB
R
0
1
1D
Q2A
C1
(1)
Q2B
R
002aaa649
to 10 other channels
(D3, D5, D6, D8 to D14)
(1) Disabled in 1:1 configuration.
Fig 1. Functional diagram of SSTU32866; 1:2 Register A configuration with C0 = 0 and
C1 = 1 (positive logic)
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© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 02 — 11 November 2004
3 of 29
SSTU32866
Philips Semiconductors
1.8 V DDR2 configurable registered buffer with parity
RESET
CK
CK
LPS0
(internal node)
Q2A, Q3A,
Q5A, Q6A,
Q8A to Q14A
D2, D3, D5, D6,
11
CE
D
D8 to D14
11
D2, D3, D5, D6,
D8 to D14
V
REF
11
CLK
R
11
Q2B, Q3B,
Q5B, Q6B,
Q8B to Q14B
D2, D3, D5, D6,
D8 to D14
11
PARITY
CHECK
C1
1
0
0
1
PPO
D
D
D
CLK
R
CLK
R
CLK
R
CE
PAR_IN
QERR
C0
CLK
2-BIT
COUNTER
R
0
1
LPS1
(internal node)
D
CLK
R
002aaa650
Fig 2. Parity logic diagram for 1:2 Register A configuration (positive logic); C0 = 0, C1 = 1
9397 750 14181
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 02 — 11 November 2004
4 of 29
SSTU32866
Philips Semiconductors
1.8 V DDR2 configurable registered buffer with parity
6. Pinning information
6.1 Pinning
SSTU32866EC/G
ball A1
SSTU32866EC
index area
1 2 3 4 5 6
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
002aab135
Transparent top view
Fig 3. Pin configuration for LFBGA96
1
DCKE
D2
2
3
4
5
QCKE
Q2
6
A
B
C
D
E
F
PPO
D15
D16
QERR
D17
D18
V
V
d.n.u.
Q15
Q16
d.n.u.
Q17
Q18
C0
REF
DD
GND
GND
D3
V
V
Q3
DD
DD
DODT
D5
GND
GND
QODT
Q5
V
V
DD
DD
D6
GND
GND
Q6
G
H
J
PAR_IN RESET
V
V
C1
DD
DD
CK
CK
DCS
CSR
D19
D20
D21
D22
D23
D24
D25
GND
GND
QCS
n.c.
Q8
d.n.u.
n.c.
V
V
DD
DD
K
L
D8
GND
GND
Q19
Q20
Q21
Q22
Q23
Q24
D9
V
V
Q9
DD
DD
M
N
P
R
T
D10
D11
D12
D13
D14
GND
GND
Q10
Q11
Q12
Q13
Q14
V
V
DD
DD
GND
GND
V
V
V
DD
DD
DD
V
Q25
REF
002aab108
Fig 4. Ball mapping, 1:1 register (C0 = 0, C1 = 0)
Rev. 02 — 11 November 2004
9397 750 14181
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
5 of 29
SSTU32866
Philips Semiconductors
1.8 V DDR2 configurable registered buffer with parity
1
DCKE
D2
2
3
4
5
6
A
B
C
D
E
F
PPO
d.n.u.
d.n.u.
QERR
n.c.
V
V
QCKEA QCKEB
REF
DD
GND
GND
Q2A
Q3A
Q2B
Q3B
D3
V
V
DD
DD
DODT
D5
GND
GND
QODTA QODTB
V
V
Q5A
Q6A
Q5B
Q6B
DD
DD
D6
n.c.
GND
GND
G
H
J
PAR_IN RESET
V
V
C1
C0
DD
DD
CK
CK
DCS
CSR
GND
GND
QCSA
n.c.
QCSB
n.c.
V
V
DD
DD
K
L
D8
d.n.u.
d.n.u.
d.n.u.
d.n.u.
d.n.u.
d.n.u.
d.n.u.
GND
GND
Q8A
Q8B
D9
V
V
Q9A
Q9B
DD
DD
M
N
P
R
T
D10
D11
D12
D13
D14
GND
GND
Q10A
Q11A
Q12A
Q13A
Q14A
Q10B
Q11B
Q12B
Q13B
V
V
DD
DD
GND
GND
V
V
V
DD
DD
DD
V
Q14B
REF
002aab109
Fig 5. Ball mapping, 1:2 Register A (C0 = 0, C1 = 1)
1
2
3
4
5
6
A
B
C
D
E
F
D1
D2
D3
D4
D5
D6
PPO
V
V
Q1A
Q2A
Q3A
Q4A
Q5A
Q6A
C1
Q1B
Q2B
Q3B
Q4B
Q5B
Q6B
C0
REF
DD
d.n.u.
d.n.u.
QERR
d.n.u.
d.n.u.
GND
GND
V
V
DD
DD
GND
GND
V
V
DD
DD
GND
GND
G
H
J
PAR_IN RESET
V
V
DD
DD
CK
CK
DCS
CSR
GND
GND
QCSA
n.c.
QCSB
n.c.
V
V
DD
DD
K
L
D8
d.n.u.
d.n.u.
d.n.u.
d.n.u.
d.n.u.
d.n.u.
d.n.u.
GND
GND
Q8A
Q9A
Q10A
Q8B
Q9B
Q10B
D9
V
V
DD
DD
M
N
P
R
T
D10
DODT
D12
D13
DCKE
GND
GND
V
V
QODTA QODTB
DD
DD
GND
GND
Q12A
Q13A
Q12B
Q13B
V
V
V
DD
DD
DD
V
QCKEA QCKEB
002aab110
REF
Fig 6. Ball mapping, 1:2 Register B (C0 = 1, C1 = 1)
Rev. 02 — 11 November 2004
9397 750 14181
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
6 of 29
SSTU32866
Philips Semiconductors
1.8 V DDR2 configurable registered buffer with parity
6.2 Pin description
Table 2:
Symbol
GND
Pin description
Pin
Type
Description
B3, B4, D3, D4, ground input
F3, F4, H3, H4,
ground
K3, K4, M3, M4,
P3, P4
VDD
A4, C3, C4, E3, 1.8 V nominal
E4, G3, G4, J3,
J4, L3, L4, N3,
power supply voltage
input reference voltage
N4, R3, R4, T4
VREF
CK
CK
C0
A3, T3
H1
0.9 V nominal
Differential input positive master clock input
Differential input negative master clock input
J1
G6
LVCMOS inputs Configuration control inputs; Register A
or Register B and 1:1 mode or 1:2 mode
select.
C1
G5
RESET
G2
LVCMOS input
SSTL_18 input
SSTL_18 input
Asynchronous reset input. Resets
registers and disables VREF data and
clock.
Chip select inputs. Disables D1 to D25[2]
outputs switching when both inputs are
HIGH.
CSR
DCS
J2
H2
[1]
D1 to D25
Data input. Clocked in on the crossing of
the rising edge od CK and the falling
edge of CK.
[1]
[1]
DODT
DCKE
PAR_IN
SSTL_18 input
SSTL_18 input
SSTL_18 input
The outputs of this register bit will not be
suspended by the DCS and CSR control.
The outputs of this register bit will not be
suspended by the DCS and CSR control.
G1
Parity input. Arrives one clock cycle after
the corresponding data input.
[1]
Q1 to Q25,
Q2A to Q14A,
Q1B to Q14B
1.8 V CMOS
outputs
Data outputs that are suspended by the
DCS and CSR control. [3]
PPO
A2
1.8 V CMOS
output
Partial parity out. Indicates odd parity of
inputs D1 to D25[2]
.
[1]
QCS, QCSA,
QCSB
1.8 V CMOS
output
Data output that will not be suspended by
the DCS and CSR control.
[1]
[1]
QODT, QODTA,
QODTB
1.8 V CMOS
output
Data output that will not be suspended by
the DCS and CSR control.
QCKE, QCKEA,
QCKEB
1.8 V CMOS
output
Data output that will not be suspended by
the DCS and CSR control.
9397 750 14181
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 02 — 11 November 2004
7 of 29
SSTU32866
Philips Semiconductors
1.8 V DDR2 configurable registered buffer with parity
Table 2:
Symbol
QERR
Pin description …continued
Pin
Type
Description
D2
open-drain
output
Output error bit. Generated one clock
cycle after the corresponding data output
[1]
[1]
n.c.
-
Not connected. Ball present but no
internal connection to the die.
d.n.u.
-
Do not use. Inputs are in
standby-equivalent mode and outputs
are driven LOW.
[1] Depends on configuration. Refer to Figure 4, Figure 5, and Figure 6 for ball number.
[2] Data inputs = D2, D3, D5, D6, D8 to D25 when C0 = 0 and C1 = 0.
Data inputs = D2, D3, D5, D6, D8 to D14 when C0 = 0 and C1 = 1.
Data inputs = D1 to D6, D8 to D10, D12, D13 when C0 = 1 and C1 = 1.
[3] Data outputs = Q2, Q3, Q5, Q6, Q8 to Q25 when C0 = 0 and C1 = 0.
Data outputs = Q2, Q3, Q5, Q6, Q8 to Q14 when C0 = 0 and C1 = 1.
Data outputs = Q1 to Q6, Q8 to Q10, Q12, Q13 when C0 = 1 and C1 = 1.
7. Functional description
The SSTU32866 is a 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity,
designed for 1.7 V to 1.9 V VDD operation.
All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The
control and reset (RESET) inputs are LVCMOS. All data outputs are 1.8 V CMOS drivers
that have been optimized to drive the DDR2 DIMM load, and meet SSTL_18
specifications. The error (QERR) output is 1.8 V open-drain driver.
The SSTU32866 operates from a differential clock (CK and CK). Data are registered at
the crossing of CK going HIGH, and CK going LOW.
The C0 input controls the pinout configuration for the 1:2 pinout from A configuration
(when LOW) to B configuration (when HIGH). The C1 input controls the pinout
configuration from 25-bit 1:1 (when LOW) to 14-bit 1:2 (when HIGH).
The SSTU32866 accepts a parity bit from the memory controller on its parity bit (PAR_IN)
input, compares it with the data received on the DIMM-independent D-inputs and
indicates whether a parity error has occurred on its open-drain QERR pin (active-LOW).
The convention is even parity, i.e., valid parity is defined as an even number of ones
across the DIMM-independent data inputs combined with the parity input bit.
When used as a single device, the C0 and C1 inputs are tied LOW. In this configuration,
parity is checked on the PAR_IN input which arrives one cycle after the input data to which
it applies. The partial-parity-out (PPO) and QERR signals are produced three cycles after
the corresponding data inputs.
When used in pairs, the C0 input of the first register is tied LOW and the C0 input of the
second register is tied HIGH. The C1 input of both registers are tied HIGH. Parity, which
arrives one cycle after the data input to which it applies, is checked on the PAR_IN input of
the first device. The PPO and QERR signals are produced on the second device three
clock cycles after the corresponding data inputs. The PPO output of the first register is
9397 750 14181
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Product data sheet
Rev. 02 — 11 November 2004
8 of 29
SSTU32866
Philips Semiconductors
1.8 V DDR2 configurable registered buffer with parity
cascaded to the PAR_IN of the second register. The QERR output of the first register is
left floating and the valid error information is latched on the QERR output of the second
register.
If an error occurs and the QERR output is driven LOW, it stays latched LOW for two clock
cycles or until RESET is driven LOW. The DIMM-dependent signals (DCKE, DCS, DODT,
and CSR) are not included in the parity check computation.
The device supports low-power standby operation. When RESET is LOW, the differential
input receivers are disabled, and undriven (floating) data, clock and reference voltage
(VREF) inputs are allowed. In addition, when RESET is LOW all registers are reset, and all
outputs are forced LOW. The LVCMOS RESET input must always be held at a valid logic
HIGH or LOW level.
The device also supports low-power active operation by monitoring both system chip
select (DCS and CSR) inputs and will gate the Qn and PPO outputs from changing states
when both DCS and CSR inputs are HIGH. If either DCS or CSR input is LOW, the Qn
and PPO outputs will function normally. The RESET input has priority over the DCS and
CSR control and when driven LOW will force the Qn and PPO outputs LOW, and the
QERR output HIGH. If the DCS control functionality is not desired, then the CSR input can
be hard-wired to ground, in which case, the set-up time requirement for DCS would be the
same as for the other Dn data inputs. To control the low-power mode with DCS only, then
the CSR input should be pulled up to VDD through a pull-up resistor.
To ensure defined outputs from the register before a stable clock has been supplied,
RESET must be held in the LOW state during power-up.
In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with
respect to CK and CK. Therefore, no timing relationship can be guaranteed between the
two. When entering reset, the register will be cleared and the Qn outputs will be driven
LOW quickly, relative to the time to disable the differential input receivers. However, when
coming out of reset, the register will become active quickly, relative to the time to enable
the differential input receivers. As long as the data inputs are LOW, and the clock is stable
during the time from the LOW-to-HIGH transition of RESET until the input receivers are
fully enabled, the design of the SSTU32866 must ensure that the outputs will remain
LOW, thus ensuring no glitches on the output.
9397 750 14181
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 02 — 11 November 2004
9 of 29
SSTU32866
Philips Semiconductors
1.8 V DDR2 configurable registered buffer with parity
7.1 Function table
Table 3:
Function table (each flip-flop)
L = LOW voltage level; H = HIGH voltage level; X = don’t care; ↑ = LOW-to-HIGH transition; ↓ = HIGH-to-LOW transition
Inputs
Outputs[1]
QCS
RESET
DCS
CSR
CK
CK
Dn, DODTn,
DCKEn
Qn
QODT,
QCKE
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
↑
↑
↓
L
H
X
L
L
H
L
L
L
H
↓
L
L
L or H
L or H
Q0
L
Q0
L
Q0
L
L
H
H
H
L
↑
↓
L
↑
↓
H
X
L
H
L
H
L
L or H
L or H
Q0
L
Q0
H
Q0
L
H
H
H
H
H
H
↑
↓
L
↑
L or H
↑
↓
L or H
↓
H
X
L
H
H
H
L
Q0
Q0
Q0
Q0
L
Q0
H
Q0
L
H
H
H
↑
↓
H
X
H
H
L or H
L or H
Q0
L
Q0
L
X or floating X or floating X or floating X or floating X or floating
[1] Q0 is the previous state of the associated output.
Table 4:
Parity and standby function table
L = LOW voltage level; H = HIGH voltage level; X = don’t care; ↑ = LOW-to-HIGH transition; ↓ = HIGH-to-LOW transition
Inputs
Outputs[1]
CK
RESET
DCS
CSR
CK
∑ of inputs = H PAR_IN[2]
PPO [3]
QERR
(D1 to D25)
H
H
H
H
H
H
H
H
H
H
L
L
L
X
X
X
X
L
↑
↓
even
odd
L
L
H
↑
↓
L
H
L
L
↑
↓
even
odd
H
H
L
L
↑
↓
H
L
H
H
H
H
H
H
X
↑
↓
even
odd
L
L
H
H
L
↑
↓
L
L
L
↑
↓
even
odd
H
H
L
H
L
↑
↑
↓
↓
H
L
H
X
X
X
X
PPO0
PPO0
L
QERR0
QERR0
H
L or H
L or H
X
X or floating X or floating X or floating X or floating
X or floating
X or floating
[1] PPO0 is the previous state of output PPO; QERR0 is the previous state of output QERR.
[2] Data inputs = D2, D3, D5, D6, D8 to D25 when C0 = 0 and C1 = 0.
Data inputs = D2, D3, D5, D6, D8 to D14 when C0 = 0 and C1 = 1.
Data inputs = D1 to D6, D8 to D10, D12, D13 when C0 = 1 and C1 = 1.
[3] PAR_IN arrives one clock cycle (C0 = 0), or two clock cycles (C0 = 1), after the data to which it applies.
[4] This condition assumes QERR is HIGH at the crossing of CK going HIGH and CK going LOW. If QERR is LOW, it stays latched LOW for
two clock cycles or until RESET is driven LOW.
9397 750 14181
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 02 — 11 November 2004
10 of 29
SSTU32866
Philips Semiconductors
1.8 V DDR2 configurable registered buffer with parity
8. Limiting values
Table 5:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). [1]
Symbol
VDD
VI
Parameter
Conditions
Min
Max
Unit
V
supply voltage
−0.5
−0.5[2]
−0.5[2]
+2.5
receiver input voltage
driver output voltage
input clamp current
output clamp current
continuous output current
+2.5[3]
VDD + 0.5 [3]
−50
V
VO
V
IIK
VI < 0 V or VI > VDD
VO < 0 V or VO > VDD
0 V < VO < VDD
-
-
-
-
mA
mA
mA
mA
IOK
±50
IO
±50
ICCC
continuous current through
each VDD or GND pin
±100
Tstg
storage temperature
−65
+150
-
°C
Vesd
electrostatic discharge
voltage
Human Body Model (HBM); 1.5 kΩ;
100 pF
2
kV
Machine Model (MM); 0 Ω; 200 pF
200
-
V
[1] Stresses beyond those listed under ‘absolute maximum ratings’ may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under ‘recommended operating
conditions’ is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
[2] The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
[3] This value is limited to 2.5 V maximum.
9. Recommended operating conditions
Table 6:
Symbol
VDD
Recommended operating conditions
Parameter
Conditions
Min
Typ
Max
Unit
V
supply voltage
1.7
-
1.9
VREF
VTT
reference voltage
termination voltage
input voltage
0.49 × VDD
0.50 × VDD
0.51 × VDD
V
VREF − 40 mV
VREF
VREF + 40 mV
V
VI
0
-
-
VDD
-
V
VIH(AC)
AC HIGH-level input voltage
data (Dn),
VREF + 250 mV
V
CSR, and
PAR_IN inputs
VIL(AC)
VIH(DC)
VIL(DC)
AC LOW-level input voltage
DC HIGH-level input voltage
DC LOW-level input voltage
data (Dn),
CSR, and
PAR_IN inputs
-
-
-
-
V
REF − 250 mV
V
V
V
data (Dn),
CSR, and
PAR_IN inputs
VREF + 125 mV
-
data (Dn),
-
VREF − 125 mV
CSR, and
PAR_IN inputs
[1]
[1]
[2]
VIH
VIL
HIGH-level input voltage
LOW-level input voltage
RESET, Cn
RESET, Cn
CK, CK
0.65 × VDD
-
-
-
-
V
V
V
-
0.35 × VDD
VICR
common mode input voltage
range
0.675
1.125
9397 750 14181
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Product data sheet
Rev. 02 — 11 November 2004
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SSTU32866
Philips Semiconductors
1.8 V DDR2 configurable registered buffer with parity
Table 6:
Symbol
VID
Recommended operating conditions …continued
Parameter
Conditions
Min
Typ
Max
-
Unit
mV
mA
mA
°C
[2]
differential input voltage
HIGH-level output current
LOW-level output current
CK, CK
600
-
-
-
-
IOH
-
−8
8
IOL
-
Tamb
operating ambient temperature
in free air
0
+70
[1] The RESET and Cn inputs of the device must be held at valid levels (not floating) to ensure proper device operation.
[2] The differential inputs must not be floating, unless RESET is LOW.
10. Characteristics
Table 7:
Characteristics
At recommended operating conditions (see Table 6), unless otherwise specified.
Symbol
VOH
VOL
Parameter
Conditions
Min
Typ
Max
-
Unit
V
HIGH-level output voltage
LOW-level output voltage
input current
IOH = −6 mA; VDD = 1.7 V
IOL = 6 mA; VDD = 1.7 V
all inputs; VI = VDD or GND;
1.2
-
-
-
-
-
0.5
±5
V
II
µA
V
DD = 1.9 V
RESET = GND; IO = 0 mA;
DD = 1.9 V
RESET = VDD; IO = 0 mA;
DD = 1.9 V; VI = VIH(AC) or VIL(AC)
dynamic operating current per MHz, RESET = VDD
IDD
static standby current
static operating current
-
-
-
-
100
40
-
µA
mA
µA
V
-
V
IDDD
;
16
clock only
VI = VIH(AC) or VIL(AC); CK and CK
switching at 50 % duty cycle.
IO = 0 mA; VDD = 1.8 V
dynamic operating current per MHz, RESET = VDD
;
-
-
11
19
-
-
µA
µA
per each data input, 1:1 mode
VI = VIH(AC) or VIL(AC); CK and CK
switching at 50 % duty cycle. One
data input switching at half clock
frequency, 50 % duty cycle.
IO = 0 mA; VDD = 1.8 V
dynamic operating current per MHz, RESET = VDD
;
per each data input, 1:2 mode
VI = VIH(AC) or VIL(AC); CK and CK
switching at 50 % duty cycle. One
data input switching at half clock
frequency, 50 % duty cycle.
IO = 0 mA; VDD = 1.8 V
Ci
input capacitance, data and CSR
inputs
VI = VREF ± 250 mV; VDD = 1.8 V
2.5
2
-
-
-
3.5
3
pF
pF
pF
input capacitance,
CK and CK inputs
VICR = 0.9 V; Vi(p-p) = 600 mV;
VDD = 1.8 V
input capacitance, RESET input
VI = VDD or GND; VDD = 1.8 V
3
4
9397 750 14181
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Product data sheet
Rev. 02 — 11 November 2004
12 of 29
SSTU32866
Philips Semiconductors
1.8 V DDR2 configurable registered buffer with parity
Table 8:
Timing requirements
At recommended operating conditions (see Table 6), unless otherwise specified. See Figure 2.
Symbol Parameter
fclock clock frequency
tW
Conditions
Min
Typ
Max
450
-
Unit
MHz
ns
-
-
-
pulse duration, CK, CK HIGH
or LOW
1
[1] [2]
[1] [3]
tACT
tINACT
tsu
differential inputs active time
differential inputs inactive time
set-up time
-
-
-
-
10
15
-
ns
ns
ns
-
DCS before CK↑, CK↓, CSR HIGH; CSR
before CK↑, CK↓, DCS HIGH
0.7
DCS before CK↑, CK↓, CSR LOW
0.5
0.5
-
-
-
-
ns
ns
DODT, DCKE and data (Dn) before CK↑,
CK↓
PAR_IN before CK↑, CK↓
0.5
0.5
-
-
-
-
ns
ns
th
hold time
DCS, DODT, DCKE and data (Dn) after
CK↑, CK↓
PAR_IN after CK↑, CK↓
0.5
-
-
ns
[1] This parameter is not necessarily production tested.
[2] VREF must be held at a valid input voltage level and data inputs must be held LOW for a minimum time of tACT(max) after RESET is taken
HIGH.
[3] VREF, data and clock inputs must be held at valid levels (not floating) a minimum time of tINACT(max) after RESET is taken LOW.
Table 9:
Switching characteristics
At recommended operating conditions (see Table 6), unless otherwise specified. See Section 11.1.
Symbol Parameter
Conditions
Min
450
1.41
0.5
1.2
1
Typ
Max
-
Unit
MHz
ns
fMAX
tPDM
tPD
maximum input clock frequency
-
-
-
-
-
-
[1]
propagation delay, single bit switching from CK↑ and CK↓ to Qn
1.8
1.8
3
propagation delay
from CK↑ and CK↓ to PPO
from CK↑ and CK↓ to QERR
from CK↑ and CK↓ to QERR
from CK↑ and CK↓ to Qn
ns
tLH
LOW-to-HIGH propagation delay
HIGH-to-LOW propagation delay
ns
tHL
2.4
2.0
ns
[1] [2]
tPDMSS
propagation delay,
-
ns
simultaneous switching
tPHL
HIGH-to-LOW propagation delay
LOW-to-HIGH propagation delay
from RESET↓ to Qn↓
from RESET↓ to PPO↓
from RESET↓ to QERR↑
-
-
-
-
-
-
3
3
3
ns
ns
ns
tPLH
[1] Includes 350 ps of test-load transmission line delay.
[2] This parameter is not necessarily production tested.
Table 10: Data output edge rates
At recommended operating conditions (see Table 6), unless otherwise specified. See Section 11.2.
Symbol
dV/dt_r
dV/dt_f
dV/dt_∆
Parameter
Conditions
Min
Typ
Max
Unit
rising edge slew rate
falling edge slew rate
from 20 % to 80 %
from 80 % to 20 %
1
1
-
-
-
-
4
4
1
V/ns
V/ns
V/ns
absolute difference between dV/dt_r from 20 % or 80 %
and dV/dt_f
to 80 % or 20 %
9397 750 14181
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Product data sheet
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SSTU32866
Philips Semiconductors
1.8 V DDR2 configurable registered buffer with parity
10.1 Timing diagrams
RESET
DCS
CSR
CK
m
m + 1
m + 2
m + 3
m + 4
CK
t
t
h
su
D1
to
D25
t
PD
CK to Q
Q1
to
Q25
t
t
h
su
PAR_IN
PPO
t
PD
CK to PPO
t
t
PD
PD
CK to QERR
CK to QERR
QERR
002aaa655
Fig 7. Timing diagram for SSTU32866 used as a single device; C0 = 0, C1 = 0
9397 750 14181
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Product data sheet
Rev. 02 — 11 November 2004
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SSTU32866
Philips Semiconductors
1.8 V DDR2 configurable registered buffer with parity
RESET
DCS
CSR
CK
m
m + 1
m + 2
m + 3
m + 4
CK
t
t
h
su
D1
to
D14
t
PD
CK to Q
Q1
to
Q14
t
t
h
su
PAR_IN
PPO
t
PD
CK to PPO
t
t
PD
PD
CK to QERR
CK to QERR
QERR
(not used)
002aaa656
Fig 8. Timing diagram for the first SSTU32866 (1:2 Register A configuration) device used in pair; C0 = 0, C1 = 1
9397 750 14181
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Product data sheet
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15 of 29
SSTU32866
Philips Semiconductors
1.8 V DDR2 configurable registered buffer with parity
RESET
DCS
CSR
CK
m
m + 1
m + 2
m + 3
m + 4
CK
t
t
h
su
D1
to
D14
t
PD
CK to Q
Q1
to
Q14
t
t
h
su
(1)
PAR_IN
t
PD
CK to PPO
PPO
(not used)
t
t
PD
PD
CK to QERR
CK to QERR
QERR
002aaa657
(1) PAR_IN is driven from PPO of the first SSTU32866 device.
Fig 9. Timing diagram for the second SSTU32866 (1:2 Register B configuration) device used in pair;
C0 = 1, C1 = 1
9397 750 14181
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Product data sheet
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SSTU32866
Philips Semiconductors
1.8 V DDR2 configurable registered buffer with parity
11. Test information
11.1 Parameter measurement information for data output load circuit
VDD = 1.8 V ± 0.1 V.
All input pulses are supplied by generators having the following characteristics:
PRR ≤ 10 MHz; Z0 = 50 Ω; input slew rate = 1 V/ns ± 20 %, unless otherwise specified.
The outputs are measured one at a time with one transition per measurement.
V
DD
DUT
R
= 1000 Ω
= 1000 Ω
L
T
= 50 Ω
T
= 350 ps, 50 Ω
L
L
CK
CK
CK inputs
OUT
(1)
= 30 pF
C
L
R
L
test point
R
L
= 100 Ω
002aaa371
test point
(1) CL includes probe and jig capacitance.
Fig 10. Load circuit, data output measurements
LVCMOS
V
DD
RESET
V
/2
DD
V
/2
DD
0 V
t
t
ACT
INACT
90 %
(1)
DD
I
10 %
002aaa372
(1) IDD tested with clock and data inputs held at VDD or GND, and IO = 0 mA.
Fig 11. Voltage and current waveforms; inputs active and inactive times
t
W
V
V
IH
IL
V
input
V
V
ICR
ID
ICR
002aaa373
VID = 600 mV
VIH = VREF + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs.
VIL = VREF − 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
Fig 12. Voltage waveforms; pulse duration
9397 750 14181
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Product data sheet
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SSTU32866
Philips Semiconductors
1.8 V DDR2 configurable registered buffer with parity
CK
CK
V
V
ICR
ID
t
t
h
su
V
V
IH
IL
input
V
REF
V
REF
002aaa374
VID = 600 mV
VREF = VDD/2
VIH = VREF + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs.
VIL = VREF − 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
Fig 13. Voltage waveforms; set-up and hold times
CK
V
V
V
ICR
ICR
i(p-p)
CK
t
t
PHL
PLH
V
V
OH
OL
V
output
TT
002aaa375
tPLH and tPHL are the same as tPD
.
Fig 14. Voltage waveforms; propagation delay times (clock to output)
LVCMOS
V
V
V
V
IH
RESET
V
/2
DD
IL
t
PHL
OH
OL
output
V
TT
002aaa376
tPLH and tPHL are the same as tPD
.
VIH = VREF + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs.
VIL = VREF − 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
Fig 15. Voltage waveforms; propagation delay times (reset to output)
9397 750 14181
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Product data sheet
Rev. 02 — 11 November 2004
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SSTU32866
Philips Semiconductors
1.8 V DDR2 configurable registered buffer with parity
11.2 Data output slew rate measurement information
VDD = 1.8 V ± 0.1 V.
All input pulses are supplied by generators having the following characteristics:
PRR ≤ 10 MHz; Z0 = 50 Ω; input slew rate = 1 V/ns ± 20 %, unless otherwise specified.
V
DD
R
DUT
= 50 Ω
L
OUT
test point
002aaa377
(1)
= 10 pF
C
L
(1) CL includes probe and jig capacitance.
Fig 16. Load circuit, HIGH-to-LOW slew measurement
output
V
OH
80 %
dv_f
20 %
V
OL
dt_f
002aaa378
Fig 17. Voltage waveforms, HIGH-to-LOW slew rate measurement
DUT
OUT
test point
(1)
= 10 pF
C
L
R
L
= 50 Ω
002aaa379
(1) CL includes probe and jig capacitance.
Fig 18. Load circuit, LOW-to-HIGH slew measurement
dt_r
V
V
OH
80 %
dv_r
20 %
output
OL
002aaa380
Fig 19. Voltage waveforms, LOW-to-HIGH slew rate measurement
9397 750 14181
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Product data sheet
Rev. 02 — 11 November 2004
19 of 29
SSTU32866
Philips Semiconductors
1.8 V DDR2 configurable registered buffer with parity
11.3 Error output load circuit and voltage measurement information
VDD = 1.8 V ± 0.1 V.
All input pulses are supplied by generators having the following characteristics:
PRR ≤ 10 MHz; Z0 = 50 Ω; input slew rate = 1 V/ns ± 20 %, unless otherwise specified.
V
DD
R
DUT
= 1 kΩ
L
OUT
test point
002aaa500
(1)
= 10 pF
C
L
(1) CL includes probe and jig capacitance.
Fig 20. Load circuit, error output measurements
LVCMOS
V
CC
RESET
V
/2
CC
0 V
t
PLH
V
OH
0.15 V
output
waveform 2
0 V
002aaa501
Fig 21. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to
RESET input.
timing
inputs
V
i(p-p)
V
V
ICR
ICR
t
HL
V
V
CC
OL
output
waveform 1
V
/2
CC
002aaa502
Fig 22. Voltage waveforms, open-drain output HIGH-to-LOW transition time with respect
to clock inputs
9397 750 14181
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Product data sheet
Rev. 02 — 11 November 2004
20 of 29
SSTU32866
Philips Semiconductors
1.8 V DDR2 configurable registered buffer with parity
timing
inputs
V
V
i(p-p)
V
ICR
ICR
t
LH
V
OH
output
waveform 2
0.15 V
0 V
002aaa503
Fig 23. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to
clock inputs
11.4 Partial Parity Out load circuit and voltage measurement information
VDD = 1.8 V ± 0.1 V.
All input pulses are supplied by generators having the following characteristics:
PRR ≤ 10 MHz; Z0 = 50 Ω; input slew rate = 1 V/ns ± 20 %, unless otherwise specified.
DUT
OUT
test point
(1)
= 5 pF
C
L
R
L
= 1 kΩ
002aaa654
(1) CL includes probe and jig capacitance.
Fig 24. Partial Parity Out load circuit
CK
V
V
V
ICR
ICR
i(p-p)
CK
t
t
PHL
PLH
V
V
OH
OL
V
output
TT
002aaa375
VTT = VDD/2
tPLH and tPHL are the same as tPD
.
Vi(p-p) = 600 mV
Fig 25. Partial Parity Out voltage waveforms; propagation delay times with respect to
clock inputs
9397 750 14181
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 02 — 11 November 2004
21 of 29
SSTU32866
Philips Semiconductors
1.8 V DDR2 configurable registered buffer with parity
LVCMOS
V
V
V
V
IH
RESET
output
V
/2
DD
IL
t
PHL
OH
OL
V
TT
002aaa376
VTT = VDD/2
tPLH and tPHL are the same as tPD
.
VIH = VREF + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs.
VIL = VREF − 250 mV (AC voltage levels) for differential inputs. VIL = VDD for LVCMOS inputs.
Fig 26. Partial Parity Out voltage waveforms; propagation delay times with respect to
RESET input
9397 750 14181
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Product data sheet
Rev. 02 — 11 November 2004
22 of 29
SSTU32866
Philips Semiconductors
1.8 V DDR2 configurable registered buffer with parity
12. Package outline
LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm SOT536-1
B
A
D
ball A1
index area
A
2
A
E
A
1
detail X
e
1
C
1/2 e
y
y
v M
w M
C
C
A B
C
1
e
b
T
R
P
N
e
M
L
K
J
H
G
F
e
2
1/2 e
E
D
C
B
A
ball A1
index area
1
2
3
4
5
6
X
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
A
b
e
e
e
v
w
y
y
1
D
E
1
2
1
2
max.
0.41
0.31
1.2
0.9
0.51
0.41
5.6
5.4
13.6
13.4
mm
1.5
4
12
0.1
0.2
0.8
0.15
0.1
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
00-03-04
03-02-05
SOT536-1
Fig 27. Package outline SOT536-1 (LFBGA96)
9397 750 14181
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Product data sheet
Rev. 02 — 11 November 2004
23 of 29
SSTU32866
Philips Semiconductors
1.8 V DDR2 configurable registered buffer with parity
13. Soldering
13.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account of
soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages
(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface mount IC packages. Wave
soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is recommended.
13.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and
binding agent) to be applied to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement. Driven by legislation and
environmental forces the worldwide use of lead-free solder pastes is increasing.
Several methods exist for reflowing; for example, convection or convection/infrared
heating in a conveyor type oven. Throughput times (preheating, soldering and cooling)
vary between 100 seconds and 200 seconds depending on heating method.
Typical reflow peak temperatures range from 215 °C to 270 °C depending on solder paste
material. The top-surface temperature of the packages should preferably be kept:
• below 225 °C (SnPb process) or below 245 °C (Pb-free process)
– for all BGA, HTSSON..T and SSOP..T packages
– for packages with a thickness ≥ 2.5 mm
– for packages with a thickness < 2.5 mm and a volume ≥ 350 mm3 so called
thick/large packages.
• below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with a
thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages.
Moisture sensitivity precautions, as indicated on packing, must be respected at all times.
13.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices
(SMDs) or printed-circuit boards with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering method was specifically
developed.
If wave soldering is used the following conditions must be observed for optimal results:
• Use a double-wave soldering method comprising a turbulent wave with high upward
pressure followed by a smooth laminar wave.
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be
parallel to the transport direction of the printed-circuit board;
9397 750 14181
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Product data sheet
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24 of 29
SSTU32866
Philips Semiconductors
1.8 V DDR2 configurable registered buffer with parity
– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the
transport direction of the printed-circuit board.
The footprint must incorporate solder thieves at the downstream end.
• For packages with leads on four sides, the footprint must be placed at a 45° angle to
the transport direction of the printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement and before soldering, the package must be fixed with a droplet of
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the adhesive is cured.
Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C
or 265 °C, depending on solder material applied, SnPb or Pb-free respectively.
A mildly-activated flux will eliminate the need for removal of corrosive residues in most
applications.
13.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage
(24 V or less) soldering iron applied to the flat part of the lead. Contact time must be
limited to 10 seconds at up to 300 °C.
When using a dedicated tool, all other leads can be soldered in one operation within
2 seconds to 5 seconds between 270 °C and 320 °C.
13.5 Package related soldering information
Table 11: Suitability of surface mount IC packages for wave and reflow soldering methods
Package [1]
Soldering method
Wave
Reflow[2]
BGA, HTSSON..T[3], LBGA, LFBGA, SQFP,
SSOP..T[3], TFBGA, VFBGA, XSON
not suitable
suitable
DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP,
HSQFP, HSSON, HTQFP, HTSSOP, HVQFN,
HVSON, SMS
not suitable[4]
suitable
PLCC[5], SO, SOJ
suitable
suitable
LQFP, QFP, TQFP
not recommended[5] [6]
not recommended[7]
not suitable
suitable
SSOP, TSSOP, VSO, VSSOP
CWQCCN..L[8], PMFP[9], WQCCN..L[8]
suitable
not suitable
[1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026);
order a copy from your Philips Semiconductors sales office.
[2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the
maximum temperature (with respect to time) and body size of the package, there is a risk that internal or
external package cracks may occur due to vaporization of the moisture in them (the so called popcorn
effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit
Packages; Section: Packing Methods.
[3] These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no
account be processed through more than one soldering cycle or subjected to infrared reflow soldering with
peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package
body peak temperature must be kept as low as possible.
9397 750 14181
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 02 — 11 November 2004
25 of 29
SSTU32866
Philips Semiconductors
1.8 V DDR2 configurable registered buffer with parity
[4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the
solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink
on the top side, the solder might be deposited on the heatsink surface.
[5] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave
direction. The package footprint must incorporate solder thieves downstream and at the side corners.
[6] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
[7] Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger
than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
[8] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered
pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by
using a hot bar soldering process. The appropriate soldering profile can be provided on request.
[9] Hot bar soldering or manual soldering is suitable for PMFP packages.
14. Abbreviations
Table 12: Abbreviations
Acronym
CMOS
DDR
Description
Complementary Metal Oxide Silicon
Double Data Rate
DIMM
Dual In-line Memory Module
JEDEC
LFBGA
LVCMOS
PPO
Joint Electron Device Engineering Council
Low profile Fine-pitch Ball Grid Array
Low Voltage Complementary Metal Oxide Silicon
Partial Parity Out
PRR
Pulse Repetition Rate
RDIMM
SSTL
Registered Dual In-line Memory Module
Stub Series Terminated Logic
9397 750 14181
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 02 — 11 November 2004
26 of 29
SSTU32866
Philips Semiconductors
1.8 V DDR2 configurable registered buffer with parity
15. Revision history
Table 13: Revision history
Document ID
SSTU32866_2
Modifications:
Release date Data sheet status
20041111 Product data sheet
Change notice Doc. number
Supersedes
-
9397 750 14181 SSTU32866-01
• The format of this data sheet has been redesigned to comply with the new presentation and
information standard of Philips Semiconductors.
• Data sheet status upgraded to ‘Product data sheet’.
• (Old) Figure 1 and Figure 2 (logic diagrams) moved to Section 5 “Functional diagram”
• Section 6 “Pinning information”
–
–
–
–
changed ‘NC’ to ‘n.c.’ and ‘DNU’ to ‘d.n.u.’
added Figure 3 “Pin configuration for LFBGA96”
added Figure 4, Figure 5, and Figure 6 (replacing old Tables 2, 3 and 4 “Ball mapping”)
Table 2 “Pin description”: added (new) Table note [1] and its references at affected pins.;
added pin number column.
• Table 3 “Function table (each flip-flop)”: added Table note [1] and its reference at ‘Outputs’.
• Table 4 “Parity and standby function table”:
–
added (new) Table note [1] and its reference at ‘Outputs’.
–
Table note [4]: changed ‘This transition assumes ...’ to ‘This condition assumes ...’.
• Table 5 “Limiting values”:
–
symbol Vi changed to VI; Symbol Vo changed to VO.
–
symbols ESDHBM and ESDMM replaced with Vesd (added model types under “Conditions”)
• Table 6 “Recommended operating conditions”:
–
changed column heading from ‘Nom’ to ‘Typ’
–
changed VIH (for Data, CSR, and PAR_IN inputs) to VIH(AC) and VIH(DC); condition changed to
‘data inputs (Dn) ...’
–
–
changed VIL (for Data, CSR, and PAR_IN inputs) to VIL(AC) and VIL(DC); condition changed to
‘data inputs (Dn)
table note split into 2 notes; references added.
• merged sections “Static characteristics” and “Dynamic characteristics” into Section 10
“Characteristics”
• Table 7 “Characteristics”: changed IDDD Parameter from “dynamic operating current ...” to
“dynamic operating current per MHz ...”; change Unit from “µA/MHz” to “µA”.
• Table 8 “Timing requirements”:
–
–
–
changed symbol fCLOCK to fclock
changed symbol tSU to tsu
changed symbol tH to th
• Figure 7 modified.
• Section 11.1 “Parameter measurement information for data output load circuit”: titles for
Figure 14 and Figure 15 modified.
• added Section 14.
SSTU32866-01
20040709
Objective data
-
9397 750 12145
-
9397 750 14181
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 02 — 11 November 2004
27 of 29
SSTU32866
Philips Semiconductors
1.8 V DDR2 configurable registered buffer with parity
16. Data sheet status
Level Data sheet status[1] Product status[2] [3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
[2]
Please consult the most recently issued data sheet before initiating or completing a design.
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
17. Definitions
18. Disclaimers
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
19. Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
9397 750 14181
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 02 — 11 November 2004
28 of 29
SSTU32866
Philips Semiconductors
1.8 V DDR2 configurable registered buffer with parity
20. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7
7
7.1
8
Functional description . . . . . . . . . . . . . . . . . . . 8
Function table . . . . . . . . . . . . . . . . . . . . . . . . . 10
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 11
Recommended operating conditions. . . . . . . 11
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 12
Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . 14
9
10
10.1
11
11.1
Test information. . . . . . . . . . . . . . . . . . . . . . . . 17
Parameter measurement information for
data output load circuit . . . . . . . . . . . . . . . . . . 17
Data output slew rate measurement
information . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Error output load circuit and voltage
measurement information. . . . . . . . . . . . . . . . 20
Partial Parity Out load circuit and voltage
measurement information. . . . . . . . . . . . . . . . 21
11.2
11.3
11.4
12
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 23
13
13.1
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Introduction to soldering surface mount
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 24
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 24
Manual soldering . . . . . . . . . . . . . . . . . . . . . . 25
Package related soldering information . . . . . . 25
13.2
13.3
13.4
13.5
14
15
16
17
18
19
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 26
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 27
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 28
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Contact information . . . . . . . . . . . . . . . . . . . . 28
© Koninklijke Philips Electronics N.V. 2004
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.
Date of release: 11 November 2004
Document number: 9397 750 14181
Published in The Netherlands
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