SSTUA32866EC/G,557 [NXP]
SSTUA32866EC;
| 型号： | SSTUA32866EC/G,557 |
| 厂家： | 
NXP |
| 描述： | SSTUA32866EC 逻辑集成电路 触发器 |
| 文件： | 总28页 (文件大小：155K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SSTUA32866
1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer
with parity for DDR2-667 RDIMM applications
Rev. 02 — 26 March 2007
Product data sheet
1. General description
The SSTUA32866 is a 1.8 V configurable register specifically designed for use on DDR2
memory modules requiring a parity checking function. It is defined in accordance with the
JEDEC standard for the SSTUA32866 registered buffer. The register is configurable
(using configuration pins C0 and C1) to two topologies: 25-bit 1 : 1 or 14-bit 1 : 2, and in
the latter configuration can be designated as Register A or Register B on the DIMM.
The SSTUA32866 accepts a parity bit from the memory controller on its parity bit
(PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs
and indicates whether a parity error has occurred on its open-drain QERR pin
(active LOW). The convention is even parity, that is, valid parity is defined as an even
number of ones across the DIMM-independent data inputs combined with the parity input
bit.
The SSTUA32866 is packaged in a 96-ball, 6 × 16 grid, 0.8 mm ball pitch LFBGA package
(13.5 mm × 5.5 mm).
2. Features
I Configurable register supporting DDR2 up to 667 MT/s Registered DIMM applications
I Configurable to 25-bit 1 : 1 mode or 14-bit 1 : 2 mode
I Controlled output impedance drivers enable optimal signal integrity and speed
I Exceeds JESD82-7 speed performance (1.8 ns max. single-bit switching propagation
delay; 2.0 ns max. mass-switching)
I Supports up to 450 MHz clock frequency of operation
I Optimized pinout for high-density DDR2 module design
I Chip-selects minimize power consumption by gating data outputs from changing state
I Supports SSTL_18 data inputs
I Checks parity on the DIMM-independent data inputs
I Partial parity output and input allows cascading of two SSTUA32866s for correct parity
error processing
I Differential clock (CK and CK) inputs
I Supports LVCMOS switching levels on the control and RESET inputs
I Single 1.8 V supply operation (1.7 V to 2.0 V)
I Available in 96-ball, 13.5 mm × 5.5 mm, 0.8 mm ball pitch LFBGA package
3. Applications
I 400 MT/s to 667 MT/s DDR2 registered DIMMs desiring parity checking functionality
SSTUA32866
NXP Semiconductors
1.8 V DDR2-667 configurable registered buffer with parity
4. Ordering information
Table 1.
Ordering information
Tamb = 0 °C to +70 °C.
Type number
Solder process
Package
Name
SSTUA32866EC/G Pb-free (SnAgCu solder LFBGA96 plastic low profile fine-pitch ball grid array package; SOT536-1
Description
Version
ball compound)
96 balls; body 13.5 × 5.5 × 1.05 mm
SSTUA32866EC
SnPb solder ball
compound
LFBGA96 plastic low profile fine-pitch ball grid array package; SOT536-1
96 balls; body 13.5 × 5.5 × 1.05 mm
5. Functional diagram
RESET
CK
CK
SSTUA32866
VREF
DCKE
1D
C1
QCKEA
QCKEB
(1)
(1)
R
DODT
DCS
CSR
D2
1D
QODTA
QODTB
C1
R
1D
QCSA
C1
(1)
QCSB
R
0
1
1D
Q2A
C1
(1)
Q2B
R
002aab388
to 10 other channels
(D3, D5, D6, D8 to D14)
(1) Disabled in 1 : 1 configuration.
Fig 1. Functional diagram of SSTUA32866; 1 : 2 Register A configuration with C0 = 0 and
C1 = 1 (positive logic)
SSTUA32866_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 26 March 2007
2 of 28
SSTUA32866
NXP Semiconductors
1.8 V DDR2-667 configurable registered buffer with parity
RESET
CK
CK
LPS0
(internal node)
Q2A, Q3A,
Q5A, Q6A,
Q8A to Q14A
D2, D3, D5, D6,
11
CE
D
D8 to D14
VREF
11
D2, D3, D5, D6,
D8 to D14
11
CLK
R
11
Q2B, Q3B,
Q5B, Q6B,
Q8B to Q14B
D2, D3, D5, D6,
D8 to D14
11
PARITY
CHECK
C1
1
0
0
1
PPO
D
D
D
CLK
R
CLK
R
CLK
R
CE
PAR_IN
QERR
C0
CLK
2-BIT
COUNTER
R
0
1
LPS1
(internal node)
D
CLK
R
002aaa650
Fig 2. Parity logic diagram for 1 : 2 Register A configuration (positive logic); C0 = 0, C1 = 1
SSTUA32866_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 26 March 2007
3 of 28
SSTUA32866
NXP Semiconductors
1.8 V DDR2-667 configurable registered buffer with parity
6. Pinning information
6.1 Pinning
SSTUA32866EC/G
ball A1
SSTUA32866EC
index area
1 2 3 4 5 6
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
002aab389
Transparent top view
Fig 3. Pin configuration for LFBGA96
1
DCKE
D2
2
3
4
5
QCKE
Q2
6
A
B
C
D
E
F
PPO
D15
D16
QERR
D17
D18
VREF
GND
V
DNU
Q15
Q16
DNU
Q17
Q18
C0
DD
GND
D3
V
V
Q3
DD
DD
DODT
D5
GND
GND
QODT
Q5
V
V
DD
DD
D6
GND
GND
Q6
G
H
J
PAR_IN RESET
V
V
C1
DD
DD
CK
CK
DCS
CSR
D19
D20
D21
D22
D23
D24
D25
GND
GND
QCS
n.c.
Q8
DNU
n.c.
V
V
DD
DD
K
L
D8
GND
GND
Q19
Q20
Q21
Q22
Q23
Q24
D9
V
V
Q9
DD
DD
M
N
P
R
T
D10
D11
D12
D13
D14
GND
GND
Q10
Q11
Q12
Q13
Q14
V
V
DD
DD
GND
GND
V
V
V
DD
DD
DD
VREF
Q25
002aab108
Fig 4. Ball mapping, 1 : 1 register (C0 = 0, C1 = 0)
Rev. 02 — 26 March 2007
SSTUA32866_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
4 of 28
SSTUA32866
NXP Semiconductors
1.8 V DDR2-667 configurable registered buffer with parity
1
DCKE
D2
2
3
4
5
6
A
B
C
D
E
F
PPO
DNU
DNU
QERR
n.c.
VREF
GND
V
QCKEA QCKEB
DD
GND
Q2A
Q3A
Q2B
Q3B
D3
V
V
DD
DD
DODT
D5
GND
GND
QODTA QODTB
V
V
Q5A
Q6A
Q5B
Q6B
DD
DD
D6
n.c.
GND
GND
G
H
J
PAR_IN RESET
V
V
C1
C0
DD
DD
CK
CK
DCS
CSR
DNU
DNU
DNU
DNU
DNU
DNU
DNU
GND
GND
QCSA
n.c.
QCSB
n.c.
V
V
DD
DD
K
L
D8
GND
GND
Q8A
Q8B
D9
V
V
Q9A
Q9B
DD
DD
M
N
P
R
T
D10
D11
D12
D13
D14
GND
GND
Q10A
Q11A
Q12A
Q13A
Q14A
Q10B
Q11B
Q12B
Q13B
V
V
DD
DD
GND
GND
V
V
V
DD
DD
DD
VREF
Q14B
002aab109
Fig 5. Ball mapping, 1 : 2 Register A (C0 = 0, C1 = 1)
1
2
3
4
5
6
A
B
C
D
E
F
D1
D2
D3
D4
D5
D6
PPO
DNU
DNU
QERR
DNU
DNU
VREF
GND
V
Q1A
Q2A
Q3A
Q4A
Q5A
Q6A
C1
Q1B
Q2B
Q3B
Q4B
Q5B
Q6B
C0
DD
GND
V
V
DD
DD
GND
GND
V
V
DD
DD
GND
GND
G
H
J
PAR_IN RESET
V
V
DD
DD
CK
CK
DCS
CSR
DNU
DNU
DNU
DNU
DNU
DNU
DNU
GND
GND
QCSA
n.c.
QCSB
n.c.
V
V
DD
DD
K
L
D8
GND
GND
Q8A
Q9A
Q10A
Q8B
Q9B
Q10B
D9
V
V
DD
DD
M
N
P
R
T
D10
DODT
D12
D13
DCKE
GND
GND
V
V
QODTA QODTB
DD
DD
GND
GND
Q12A
Q13A
Q12B
Q13B
V
V
V
DD
DD
DD
VREF
QCKEA QCKEB
002aab110
Fig 6. Ball mapping, 1 : 2 Register B (C0 = 1, C1 = 1)
Rev. 02 — 26 March 2007
SSTUA32866_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
5 of 28
SSTUA32866
NXP Semiconductors
1.8 V DDR2-667 configurable registered buffer with parity
6.2 Pin description
Table 2.
Symbol
GND
Pin description
Pin
Type
Description
B3, B4, D3, D4, ground input
F3, F4, H3, H4,
ground
K3, K4, M3, M4,
P3, P4
VDD
A4, C3, C4, E3, 1.8 V nominal
E4, G3, G4, J3,
J4, L3, L4, N3,
power supply voltage
input reference voltage
N4, R3, R4, T4
VREF
CK
A3, T3
H1
0.9 V nominal
Differential input positive master clock input
Differential input negative master clock input
CK
J1
C0
G6
LVCMOS inputs Configuration control inputs; Register A
or Register B and 1 : 1 mode or
C1
G5
1 : 2 mode select.
RESET
G2
LVCMOS input
SSTL_18 input
SSTL_18 input
Asynchronous reset input (active LOW).
Resets registers and disables VREF data
and clock.
CSR
DCS
J2
Chip select inputs (active LOW). Disables
D1 to D25[2] outputs switching when both
inputs are HIGH.
H2
[1]
D1 to D25
Data input. Clocked in on the crossing of
the rising edge of CK and the falling edge
of CK.
[1]
[1]
DODT
DCKE
PAR_IN
SSTL_18 input
SSTL_18 input
SSTL_18 input
The outputs of this register bit will not be
suspended by the DCS and CSR control.
The outputs of this register bit will not be
suspended by the DCS and CSR control.
G1
Parity input. Arrives one clock cycle after
the corresponding data input.
[1]
Q1 to Q25,
Q2A to Q14A,
Q1B to Q14B
1.8 V CMOS
outputs
Data outputs that are suspended by the
DCS and CSR control[3].
PPO
A2
1.8 V CMOS
output
Partial parity out. Indicates odd parity of
inputs D1 to D25[2].
[1]
QCS, QCSA,
QCSB
1.8 V CMOS
output
Data output that will not be suspended by
the DCS and CSR control.
[1]
[1]
QODT, QODTA,
QODTB
1.8 V CMOS
output
Data output that will not be suspended by
the DCS and CSR control.
QCKE, QCKEA,
QCKEB
1.8 V CMOS
output
Data output that will not be suspended by
the DCS and CSR control.
SSTUA32866_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 26 March 2007
6 of 28
SSTUA32866
NXP Semiconductors
1.8 V DDR2-667 configurable registered buffer with parity
Table 2.
Pin description …continued
Symbol
Pin
Type
Description
QERR
D2
open-drain
output
Output error bit (active LOW). Generated
one clock cycle after the corresponding
data output
[1]
[1]
n.c.
-
-
Not connected. Ball present but no
internal connection to the die.
DNU
Do not use. Inputs are in
standby-equivalent mode and outputs
are driven LOW.
[1] Depends on configuration. See Figure 4, Figure 5, and Figure 6 for ball number.
[2] Data inputs = D2, D3, D5, D6, D8 to D25 when C0 = 0 and C1 = 0.
Data inputs = D2, D3, D5, D6, D8 to D14 when C0 = 0 and C1 = 1.
Data inputs = D1 to D6, D8 to D10, D12, D13 when C0 = 1 and C1 = 1.
[3] Data outputs = Q2, Q3, Q5, Q6, Q8 to Q25 when C0 = 0 and C1 = 0.
Data outputs = Q2, Q3, Q5, Q6, Q8 to Q14 when C0 = 0 and C1 = 1.
Data outputs = Q1 to Q6, Q8 to Q10, Q12, Q13 when C0 = 1 and C1 = 1.
7. Functional description
The SSTUA32866 is a 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity,
designed for 1.7 V to 2.0 V VDD operation.
All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The
control and reset (RESET) inputs are LVCMOS. All data outputs are 1.8 V CMOS drivers
that have been optimized to drive the DDR2 DIMM load, and meet SSTL_18
specifications. The error (QERR) output is 1.8 V open-drain driver.
The SSTUA32866 operates from a differential clock (CK and CK). Data are registered at
the crossing of CK going HIGH, and CK going LOW.
The C0 input controls the pinout configuration for the 1 : 2 pinout from A configuration
(when LOW) to B configuration (when HIGH). The C1 input controls the pinout
configuration from 25-bit 1 : 1 (when LOW) to 14-bit 1 : 2 (when HIGH).
The SSTUA32866 accepts a parity bit from the memory controller on its parity bit
(PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs
and indicates whether a parity error has occurred on its open-drain QERR pin
(active LOW). The convention is even parity, that is, valid parity is defined as an even
number of ones across the DIMM-independent data inputs combined with the parity input
bit.
When used as a single device, the C0 and C1 inputs are tied LOW. In this configuration,
parity is checked on the PAR_IN input which arrives one cycle after the input data to which
it applies. The Partial-Parity-Out (PPO) and QERR signals are produced three cycles after
the corresponding data inputs.
When used in pairs, the C0 input of the first register is tied LOW and the C0 input of the
second register is tied HIGH. The C1 input of both registers are tied HIGH. Parity, which
arrives one cycle after the data input to which it applies, is checked on the PAR_IN input of
the first device. The PPO and QERR signals are produced on the second device three
clock cycles after the corresponding data inputs. The PPO output of the first register is
SSTUA32866_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 26 March 2007
7 of 28
SSTUA32866
NXP Semiconductors
1.8 V DDR2-667 configurable registered buffer with parity
cascaded to the PAR_IN of the second register. The QERR output of the first register is
left floating and the valid error information is latched on the QERR output of the second
register.
If an error occurs and the QERR output is driven LOW, it stays latched LOW for two clock
cycles or until RESET is driven LOW. The DIMM-dependent signals (DCKE, DCS, DODT,
and CSR) are not included in the parity check computation.
The device supports low-power standby operation. When RESET is LOW, the differential
input receivers are disabled, and undriven (floating) data, clock and reference voltage
(VREF) inputs are allowed. In addition, when RESET is LOW all registers are reset, and
all outputs are forced LOW. The LVCMOS RESET input must always be held at a valid
logic HIGH or LOW level.
The device also supports low-power active operation by monitoring both system chip
select (DCS and CSR) inputs and will gate the Qn and PPO outputs from changing states
when both DCS and CSR inputs are HIGH. If either DCS or CSR input is LOW, the Qn
and PPO outputs will function normally. The RESET input has priority over the DCS and
CSR control and when driven LOW will force the Qn and PPO outputs LOW, and the
QERR output HIGH. If the DCS control functionality is not desired, then the CSR input can
be hard-wired to ground, in which case, the setup time requirement for DCS would be the
same as for the other Dn data inputs. To control the low-power mode with DCS only, then
the CSR input should be pulled up to VDD through a pull-up resistor.
To ensure defined outputs from the register before a stable clock has been supplied,
RESET must be held in the LOW state during power-up.
In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with
respect to CK and CK. Therefore, no timing relationship can be guaranteed between the
two. When entering reset, the register will be cleared and the Qn outputs will be driven
LOW quickly, relative to the time to disable the differential input receivers. However, when
coming out of reset, the register will become active quickly, relative to the time to enable
the differential input receivers. As long as the data inputs are LOW, and the clock is stable
during the time from the LOW-to-HIGH transition of RESET until the input receivers are
fully enabled, the design of the SSTUA32866 must ensure that the outputs will remain
LOW, thus ensuring no glitches on the output.
SSTUA32866_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 26 March 2007
8 of 28
SSTUA32866
NXP Semiconductors
1.8 V DDR2-667 configurable registered buffer with parity
7.1 Function table
Table 3.
Function table (each flip-flop)
L = LOW voltage level; H = HIGH voltage level; X = don’t care; ↑ = LOW-to-HIGH transition; ↓ = HIGH-to-LOW transition
Inputs
Outputs[1]
QCS
RESET
DCS
CSR
CK
CK
Dn, DODTn,
DCKEn
Qn
QODT,
QCKE
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
↑
↑
↓
L
H
X
L
L
H
L
L
L
H
↓
L
L
L or H
L or H
Q0
L
Q0
L
Q0
L
L
H
H
H
L
↑
↓
L
↑
↓
H
X
L
H
L
H
L
L or H
L or H
Q0
L
Q0
H
Q0
L
H
H
H
H
H
H
↑
↓
L
↑
L or H
↑
↓
L or H
↓
H
X
L
H
H
H
L
Q0
Q0
Q0
Q0
L
Q0
H
Q0
L
H
H
H
↑
↓
H
X
H
H
L or H
L or H
Q0
L
Q0
L
X or floating X or floating X or floating X or floating X or floating
[1] Q0 is the previous state of the associated output.
Table 4.
Parity and standby function table
L = LOW voltage level; H = HIGH voltage level; X = don’t care; ↑ = LOW-to-HIGH transition; ↓ = HIGH-to-LOW transition
Inputs
Outputs[1]
CK
RESET
DCS
CSR
CK
∑ of inputs = H PAR_IN[2]
PPO[3]
QERR[4]
(D1 to D25)
H
H
H
H
H
H
H
H
H
H
L
L
L
X
X
X
X
L
↑
↓
even
odd
L
L
H
↑
↓
L
H
L
L
↑
↓
even
odd
H
H
L
L
↑
↓
H
L
H
H
H
H
H
H
X
↑
↓
even
odd
L
L
H
H
L
↑
↓
L
L
L
↑
↓
even
odd
H
H
L
H
L
↑
↑
↓
↓
H
L
H
X
X
X
X
PPO0
PPO0
L
QERR0
QERR0
H
L or H
L or H
X
X or floating X or floating X or floating X or floating
X or floating
X or floating
[1] PPO0 is the previous state of output PPO; QERR0 is the previous state of output QERR.
[2] Data inputs = D2, D3, D5, D6, D8 to D25 when C0 = 0 and C1 = 0.
Data inputs = D2, D3, D5, D6, D8 to D14 when C0 = 0 and C1 = 1.
Data inputs = D1 to D6, D8 to D10, D12, D13 when C0 = 1 and C1 = 1.
[3] PAR_IN arrives one clock cycle (C0 = 0), or two clock cycles (C0 = 1), after the data to which it applies.
[4] This condition assumes QERR is HIGH at the crossing of CK going HIGH and CK going LOW. If QERR is LOW, it stays latched LOW for
two clock cycles or until RESET is driven LOW.
SSTUA32866_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 26 March 2007
9 of 28
SSTUA32866
NXP Semiconductors
1.8 V DDR2-667 configurable registered buffer with parity
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDD
VI
Parameter
Conditions
Min
Max
Unit
V
supply voltage
−0.5
−0.5[1]
−0.5[1]
+2.5
input voltage
receiver
+2.5[2]
VDD + 0.5[2]
−50
V
VO
output voltage
driver
V
IIK
input clamping current
output clamping current
output current
VI < 0 V or VI > VDD
VO < 0 V or VO > VDD
continuous; 0 V < VO < VDD
-
-
-
-
mA
mA
mA
mA
IOK
±50
IO
±50
ICCC
continuous current through
each VDD or GND pin
±100
Tstg
storage temperature
−65
2
+150
°C
kV
V
Vesd
electrostatic discharge
voltage
Human Body Model (HBM); 1.5 kΩ; 100 pF
Machine Model (MM); 0 Ω; 200 pF
-
-
200
[1] The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
[2] This value is limited to 2.5 V maximum.
9. Recommended operating conditions
Table 6.
Recommended operating conditions
Symbol Parameter
Conditions
Min
Typ
Max
Unit
V
VDD
Vref
VT
supply voltage
1.7
-
2.0
reference voltage
termination voltage
input voltage
0.49 × VDD
0.50 × VDD 0.51 × VDD
V
Vref − 0.040 Vref
Vref + 0.040
V
VI
0
-
-
VDD
-
V
VIH(AC)
AC HIGH-level input voltage
data (Dn), CSR, and
PAR_IN inputs
Vref + 0.250
V
VIL(AC)
VIH(DC)
VIL(DC)
AC LOW-level input voltage
DC HIGH-level input voltage
DC LOW-level input voltage
data (Dn), CSR, and
PAR_IN inputs
-
-
-
-
V
-
ref − 0.250
V
V
V
data (Dn), CSR, and
PAR_IN inputs
Vref + 0.125
-
data (Dn), CSR, and
PAR_IN inputs
V
-
ref − 0.125
[1]
[1]
[2]
[2]
VIH
VIL
HIGH-level input voltage
LOW-level input voltage
RESET, Cn
RESET, Cn
0.65 × VDD
-
-
-
-
-
-
-
V
-
0.35 × VDD
V
VICR
VID
IOH
common mode input voltage range CK, CK
0.675
1.125
-
V
differential input voltage
HIGH-level output current
LOW-level output current
ambient temperature
CK, CK
600
mV
mA
mA
°C
-
−8
IOL
-
8
Tamb
operating in free air
0
+70
[1] The RESET and Cn inputs of the device must be held at valid levels (not floating) to ensure proper device operation.
[2] The differential inputs must not be floating, unless RESET is LOW.
SSTUA32866_2
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Product data sheet
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SSTUA32866
NXP Semiconductors
1.8 V DDR2-667 configurable registered buffer with parity
10. Characteristics
Table 7.
Characteristics
At recommended operating conditions (see Table 6); unless otherwise specified.
Symbol
VOH
VOL
II
Parameter
Conditions
Min
Typ
Max
-
Unit
V
HIGH-level output voltage
LOW-level output voltage
input current
IOH = −6 mA; VDD = 1.7 V
IOL = 6 mA; VDD = 1.7 V
all inputs; VI = VDD or GND; VDD = 2.0 V
1.2
-
-
-
-
-
-
-
0.5
±5
2
V
µA
mA
IDD
supply current
static standby; RESET = GND;
IO = 0 mA; VDD = 2.0 V
static operating; RESET = VDD
IO = 0 mA; VDD = 2.0 V;
VI = VIH(AC) or VIL(AC)
;
-
-
-
40
-
mA
IDDD
dynamic operating current
per MHz
clock only; RESET = VDD
VI = VIH(AC) or VIL(AC)
;
16
µA
;
CK and CK switching at 50 % duty cycle.
IO = 0 mA; VDD = 1.8 V
per each data input, 1 : 1 mode;
RESET = VDD; VI = VIH(AC) or VIL(AC)
CK and CK switching at 50 % duty cycle.
One data input switching at half clock
frequency, 50 % duty cycle. IO = 0 mA;
-
-
11
19
-
-
µA
µA
;
VDD = 1.8 V
per each data input, 1 : 2 mode;
RESET = VDD; VI = VIH(AC) or VIL(AC)
;
CK and CK switching at 50 % duty cycle.
One data input switching at half clock
frequency, 50 % duty cycle. IO = 0 mA;
V
DD = 1.8 V
data and CSR inputs; VI = Vref ± 250 mV;
DD = 1.8 V
CK and CK inputs; VICR = 0.9 V;
i(p-p) = 600 mV; VDD = 1.8 V
RESET input; VI = VDD or GND;
DD = 1.8 V
Ci
input capacitance
2.5
2
-
-
-
3.5
3
pF
pF
pF
V
V
3
4
V
SSTUA32866_2
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Product data sheet
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SSTUA32866
NXP Semiconductors
1.8 V DDR2-667 configurable registered buffer with parity
Table 8.
Timing requirements
At recommended operating conditions (see Table 6), unless otherwise specified. See Figure 2.
Symbol Parameter
fclock clock frequency
tW
Conditions
Min
Typ
Max
450
-
Unit
MHz
ns
-
-
-
-
-
-
pulse width
CK, CK HIGH or LOW
1
[1][2]
[1][3]
tACT
tINACT
tsu
differential inputs active time
differential inputs inactive time
set-up time
-
10
15
-
ns
-
ns
DCS before CK↑, CK↓, CSR HIGH; CSR
before CK↑, CK↓, DCS HIGH
0.7
ns
DCS before CK↑, CK↓, CSR LOW
0.5
0.5
-
-
-
-
ns
ns
DODT, DCKE and data (Dn) before CK↑,
CK↓
PAR_IN before CK↑, CK↓
0.5
0.5
-
-
-
-
ns
ns
th
hold time
DCS, DODT, DCKE and data (Dn) after
CK↑, CK↓
PAR_IN after CK↑, CK↓
0.5
-
-
ns
[1] This parameter is not necessarily production tested.
[2] VREF must be held at a valid input voltage level and data inputs must be held LOW for a minimum time of tACT(max) after RESET is taken
HIGH.
[3] VREF, data and clock inputs must be held at valid levels (not floating) a minimum time of tINACT(max) after RESET is taken LOW.
Table 9.
Switching characteristics
At recommended operating conditions (see Table 6), unless otherwise specified. See Section 11.1.
Symbol Parameter
Conditions
Min
450
1.2
Typ
Max
-
Unit
MHz
ns
fmax
maximum input clock frequency
-
-
[1]
tPDM
peak propagation delay
single bit switching; from CK↑
and CK↓ to Qn
1.8
tPD
propagation delay
LOW-to-HIGH delay
HIGH-to-LOW delay
from CK↑ and CK↓ to PPO
from CK↑ and CK↓ to QERR
from CK↑ and CK↓ to QERR
from CK↑ and CK↓ to Qn
0.5
1.2
1
-
-
-
-
1.8
3
ns
ns
ns
ns
tLH
tHL
2.4
2.0
[1][2]
tPDMSS
simultaneous switching peak
propagation delay
-
tPHL
HIGH-to-LOW propagation delay
from RESET↓ to Qn↓
from RESET↓ to PPO↓
from RESET↓ to QERR↑
-
-
-
-
-
-
3
3
3
ns
ns
ns
tPLH
LOW-to-HIGH propagation delay
[1] Includes 350 ps of test-load transmission line delay.
[2] This parameter is not necessarily production tested.
Table 10. Data output edge rates
At recommended operating conditions (see Table 6), unless otherwise specified. See Section 11.2.
Symbol
dV/dt_r
dV/dt_f
dV/dt_∆
Parameter
Conditions
Min
Typ
Max
Unit
rising edge slew rate
falling edge slew rate
from 20 % to 80 %
from 80 % to 20 %
1
1
-
-
-
-
4
4
1
V/ns
V/ns
V/ns
absolute difference between dV/dt_r from 20 % or 80 %
and dV/dt_f
to 80 % or 20 %
SSTUA32866_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 26 March 2007
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SSTUA32866
NXP Semiconductors
1.8 V DDR2-667 configurable registered buffer with parity
10.1 Timing diagrams
RESET
DCS
CSR
CK
m
m + 1
m + 2
m + 3
m + 4
CK
t
t
h
su
D1
to
D25
t
PD
CK to Q
Q1
to
Q25
t
t
h
su
PAR_IN
PPO
t
PD
CK to PPO
t
t
PD
PD
CK to QERR
CK to QERR
QERR
002aaa655
Fig 7. Timing diagram for SSTUA32866 used as a single device; C0 = 0, C1 = 0
SSTUA32866_2
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Product data sheet
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SSTUA32866
NXP Semiconductors
1.8 V DDR2-667 configurable registered buffer with parity
RESET
DCS
CSR
CK
m
m + 1
m + 2
m + 3
m + 4
CK
t
t
h
su
D1
to
D14
t
PD
CK to Q
Q1
to
Q14
t
t
h
su
PAR_IN
PPO
t
PD
CK to PPO
t
t
PD
PD
CK to QERR
CK to QERR
QERR
(not used)
002aaa656
Fig 8. Timing diagram for the first SSTUA32866 (1 : 2 Register A configuration) device used in pair; C0 = 0,
C1 = 1
SSTUA32866_2
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Product data sheet
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SSTUA32866
NXP Semiconductors
1.8 V DDR2-667 configurable registered buffer with parity
RESET
DCS
CSR
CK
m
m + 1
m + 2
m + 3
m + 4
CK
t
t
h
su
D1
to
D14
t
PD
CK to Q
Q1
to
Q14
t
t
h
su
(1)
PAR_IN
t
PD
CK to PPO
PPO
(not used)
t
t
PD
PD
CK to QERR
CK to QERR
QERR
002aaa657
(1) PAR_IN is driven from PPO of the first SSTUA32866 device.
Fig 9. Timing diagram for the second SSTUA32866 (1 : 2 Register B configuration) device used in pair;
C0 = 1, C1 = 1
SSTUA32866_2
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SSTUA32866
NXP Semiconductors
1.8 V DDR2-667 configurable registered buffer with parity
11. Test information
11.1 Parameter measurement information for data output load circuit
VDD = 1.8 V ± 0.1 V.
All input pulses are supplied by generators having the following characteristics:
PRR ≤ 10 MHz; Z0 = 50 Ω; input slew rate = 1 V/ns ± 20 %, unless otherwise specified.
The outputs are measured one at a time with one transition per measurement.
V
DD
DUT
delay = 350 ps
= 50 Ω
R
= 1000 Ω
= 1000 Ω
L
50 Ω
Z
o
CK
CK
CK inputs
OUT
(1)
= 30 pF
C
L
R
L
test point
R
L
= 100 Ω
test point
002aaa371
(1) CL includes probe and jig capacitance.
Fig 10. Load circuit, data output measurements
LVCMOS
V
DD
0.5V
0.5V
RESET
DD
DD
0 V
t
t
ACT
INACT
90 %
(1)
DD
I
10 %
002aaa372
(1) IDD tested with clock and data inputs held at VDD or GND, and IO = 0 mA.
Fig 11. Voltage and current waveforms; inputs active and inactive times
t
W
V
V
IH
IL
V
input
V
V
ICR
ID
ICR
002aaa373
VID = 600 mV
VIH = Vref + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs.
VIL = Vref − 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
Fig 12. Voltage waveforms; pulse duration
SSTUA32866_2
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Product data sheet
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SSTUA32866
NXP Semiconductors
1.8 V DDR2-667 configurable registered buffer with parity
CK
V
V
ICR
ID
CK
t
t
h
su
V
V
IH
IL
input
V
ref
V
ref
002aaa374
VID = 600 mV
Vref = 0.5VDD
VIH = Vref + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs.
VIL = Vref − 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
Fig 13. Voltage waveforms; setup and hold times
CK
V
V
V
i(p-p)
ICR
ICR
CK
t
t
PHL
PLH
V
V
OH
OL
V
output
T
002aaa375
tPLH and tPHL are the same as tPD
.
Fig 14. Voltage waveforms; propagation delay times (clock to output)
LVCMOS
V
V
V
V
IH
RESET
0.5V
DD
IL
t
PHL
OH
OL
output
V
T
002aaa376
tPLH and tPHL are the same as tPD
.
VIH = Vref + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs.
VIL = Vref − 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
Fig 15. Voltage waveforms; propagation delay times (reset to output)
SSTUA32866_2
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Product data sheet
Rev. 02 — 26 March 2007
17 of 28
SSTUA32866
NXP Semiconductors
1.8 V DDR2-667 configurable registered buffer with parity
11.2 Data output slew rate measurement information
VDD = 1.8 V ± 0.1 V.
All input pulses are supplied by generators having the following characteristics:
PRR ≤ 10 MHz; Z0 = 50 Ω; input slew rate = 1 V/ns ± 20 %, unless otherwise specified.
V
DD
R
DUT
= 50 Ω
L
OUT
test point
002aaa377
(1)
= 10 pF
C
L
(1) CL includes probe and jig capacitance.
Fig 16. Load circuit, HIGH-to-LOW slew measurement
output
V
OH
80 %
dv_f
20 %
V
OL
dt_f
002aaa378
Fig 17. Voltage waveforms, HIGH-to-LOW slew rate measurement
DUT
OUT
test point
(1)
= 10 pF
C
L
R
L
= 50 Ω
002aaa379
(1) CL includes probe and jig capacitance.
Fig 18. Load circuit, LOW-to-HIGH slew measurement
dt_r
V
V
OH
80 %
dv_r
20 %
output
OL
002aaa380
Fig 19. Voltage waveforms, LOW-to-HIGH slew rate measurement
SSTUA32866_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 26 March 2007
18 of 28
SSTUA32866
NXP Semiconductors
1.8 V DDR2-667 configurable registered buffer with parity
11.3 Error output load circuit and voltage measurement information
VDD = 1.8 V ± 0.1 V.
All input pulses are supplied by generators having the following characteristics:
PRR ≤ 10 MHz; Z0 = 50 Ω; input slew rate = 1 V/ns ± 20 %, unless otherwise specified.
V
DD
R
DUT
= 1 kΩ
L
OUT
test point
002aaa500
(1)
= 10 pF
C
L
(1) CL includes probe and jig capacitance.
Fig 20. Load circuit, error output measurements
LVCMOS
V
DD
RESET
0.5V
DD
0 V
t
PLH
V
OH
output
waveform 2
0.15 V
0 V
002aaa501
Fig 21. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to
RESET input.
timing
inputs
V
i(p-p)
V
V
ICR
ICR
t
HL
V
V
DD
OL
output
waveform 1
0.5V
DD
002aaa502
Fig 22. Voltage waveforms, open-drain output HIGH-to-LOW transition time with respect
to clock inputs
SSTUA32866_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 26 March 2007
19 of 28
SSTUA32866
NXP Semiconductors
1.8 V DDR2-667 configurable registered buffer with parity
timing
inputs
V
V
i(p-p)
V
ICR
ICR
t
LH
V
OH
output
waveform 2
0.15 V
0 V
002aaa503
Fig 23. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to
clock inputs
11.4 Partial parity out load circuit and voltage measurement information
VDD = 1.8 V ± 0.1 V.
All input pulses are supplied by generators having the following characteristics:
PRR ≤ 10 MHz; Z0 = 50 Ω; input slew rate = 1 V/ns ± 20 %, unless otherwise specified.
DUT
OUT
test point
(1)
= 5 pF
C
L
R
L
= 1 kΩ
002aaa654
(1) CL includes probe and jig capacitance.
Fig 24. Partial parity out load circuit
CK
V
V
V
i(p-p)
ICR
ICR
CK
t
t
PHL
PLH
V
V
OH
OL
V
output
T
002aaa375
VT = 0.5VDD
.
tPLH and tPHL are the same as tPD
.
Vi(p-p) = 600 mV.
Fig 25. Partial parity out voltage waveforms; propagation delay times with respect to clock
inputs
SSTUA32866_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 26 March 2007
20 of 28
SSTUA32866
NXP Semiconductors
1.8 V DDR2-667 configurable registered buffer with parity
LVCMOS
V
V
V
V
IH
RESET
output
0.5V
DD
IL
t
PHL
OH
OL
V
T
002aaa376
VT = 0.5VDD
.
tPLH and tPHL are the same as tPD
.
VIH = Vref + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs.
VIL = Vref − 250 mV (AC voltage levels) for differential inputs. VIL = VDD for LVCMOS inputs.
Fig 26. Partial parity out voltage waveforms; propagation delay times with respect to
RESET input
SSTUA32866_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 26 March 2007
21 of 28
SSTUA32866
NXP Semiconductors
1.8 V DDR2-667 configurable registered buffer with parity
12. Package outline
LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm SOT536-1
B
A
D
ball A1
index area
A
2
A
E
A
1
detail X
e
1
C
1/2 e
y
y
v M
w M
C
C
A B
C
1
e
b
T
R
P
N
e
M
L
K
J
H
G
F
e
2
1/2 e
E
D
C
B
A
ball A1
index area
1
2
3
4
5
6
X
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
A
b
e
e
e
v
w
y
y
1
D
E
1
2
1
2
max.
0.41
0.31
1.2
0.9
0.51
0.41
5.6
5.4
13.6
13.4
mm
1.5
4
12
0.1
0.2
0.8
0.15
0.1
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
00-03-04
03-02-05
SOT536-1
Fig 27. Package outline SOT536-1 (LFBGA96)
SSTUA32866_2
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Product data sheet
Rev. 02 — 26 March 2007
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SSTUA32866
NXP Semiconductors
1.8 V DDR2-667 configurable registered buffer with parity
13. Soldering
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus PbSn soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
SSTUA32866_2
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Product data sheet
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SSTUA32866
NXP Semiconductors
1.8 V DDR2-667 configurable registered buffer with parity
13.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 28) than a PbSn process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 11 and 12
Table 11. SnPb eutectic process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
235
≥ 350
220
< 2.5
≥ 2.5
220
220
Table 12. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 28.
SSTUA32866_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 26 March 2007
24 of 28
SSTUA32866
NXP Semiconductors
1.8 V DDR2-667 configurable registered buffer with parity
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 28. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
14. Abbreviations
Table 13. Abbreviations
Acronym
CMOS
DDR
Description
Complementary Metal Oxide Silicon
Double Data Rate
DIMM
LVCMOS
PPO
Dual In-line Memory Module
Low Voltage Complementary Metal Oxide Silicon
Partial Parity Out
PRR
Pulse Repetition Rate
RDIMM
SSTL
Registered Dual In-line Memory Module
Stub Series Terminated Logic
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Product data sheet
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1.8 V DDR2-667 configurable registered buffer with parity
15. Revision history
Table 14. Revision history
Document ID
SSTUA32866_2
Modifications:
Release date
Data sheet status
Change notice
Supersedes
20070326
Product data sheet
-
SSTUA32866_1
• The format of this data sheet has been redesigned to comply with the new identity guidelines of
NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• 3rd paragraph, 2nd sentence of Section 7 “Functional description”: changed “... and CK going
LOW.” to “... and CK going LOW.”
• Table 5 “Limiting values”:
–
–
–
changed Parameter for VI to “input voltage”; moved “receiver” to Conditions
changed Parameter for VO to “output voltage”; moved “driver” to Conditions
changed Parameter for IO to “output current”; moved “continuous” to Conditions
• Table 6 “Recommended operating conditions”: changed symbol “VTT” to “VT”
• Table 7 “Characteristics”:
–
Symbol IDD: changed Parameter to “supply current”; moved “static standby” and “static
operating” to Conditions
–
–
IDD, supply current, static standby: changed Max value from “100 µA” to “2 mA”
Symbol IDDD: changed Parameter to “dynamic operating current per MHz”; moved “clock only”,
and “per each data input, 1 : 1 mode”, and “per each data input, 1 : 2 mode” to Conditions
–
Symbol Ci: changed Parameter to “input capacitance”; moved “data and CSR inputs”,
“CK and CK inputs”, and “RESET input” to Conditions
• Table 8 “Timing requirements”, Symbol tW: changed Parameter to “pulse width”; moved “CK, CK
HIGH or LOW” to Conditions
• Table 9 “Switching characteristics”:
–
changed Symbol “fMAX” to “fmax”
–
changed Parameter for tPDM to “peak propagation delay”; moved “single bit switching” to
Conditions
–
changed Parameter for tPDMSS to “simultaneous switching peak propagation delay”
• (throughout data sheet): changed “VDD/2” to “0.5VDD
20050715 Product data sheet
”
SSTUA32866_1
(9397 750 14759)
-
-
SSTUA32866_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 26 March 2007
26 of 28
SSTUA32866
NXP Semiconductors
1.8 V DDR2-667 configurable registered buffer with parity
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of a NXP Semiconductors product can reasonably be expected to
16.2 Definitions
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
17. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
SSTUA32866_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 26 March 2007
27 of 28
SSTUA32866
NXP Semiconductors
1.8 V DDR2-667 configurable registered buffer with parity
18. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
7
7.1
8
Functional description . . . . . . . . . . . . . . . . . . . 7
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 10
Recommended operating conditions. . . . . . . 10
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 11
Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . 13
9
10
10.1
11
11.1
Test information. . . . . . . . . . . . . . . . . . . . . . . . 16
Parameter measurement information for
data output load circuit . . . . . . . . . . . . . . . . . . 16
Data output slew rate measurement
information . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Error output load circuit and voltage
measurement information. . . . . . . . . . . . . . . . 19
Partial parity out load circuit and voltage
11.2
11.3
11.4
measurement information. . . . . . . . . . . . . . . . 20
12
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 22
13
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Introduction to soldering . . . . . . . . . . . . . . . . . 23
Wave and reflow soldering . . . . . . . . . . . . . . . 23
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 23
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 24
13.1
13.2
13.3
13.4
14
15
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 25
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 26
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 27
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 27
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 27
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 27
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 26 March 2007
Document identifier: SSTUA32866_2
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