SSTUM32868ET/S_技术文档

SSTUM32868

1.8 V 28-bit 1 : 2 conﬁgurable registered buffer with parity for

DDR2-800 RDIMM applications

Rev. 02 — 2 March 2007

Product data sheet

1. General description

The SSTUM32868 is a 1.8 V 28-bit 1 : 2 register speciﬁcally designed for use on two rank

by four (2R × 4) and similar high-density Double Data Rate 2 (DDR2) memory modules. It

is similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the

functionality of the normally required two registers in a single package, thereby freeing up

board real-estate and facilitating routing to accommodate high-density Dual In-line

Memory Module (DIMM) designs.

The SSTUM32868 also integrates a parity function, which accepts a parity bit from the

memory controller, compares it with the data received on the D-inputs and indicates

whether a parity error has occurred on its open-drain PTYERR pin (active LOW).

It further offers added features over the JEDEC standard register in that it is permanently

conﬁgured for high output drive strength. This allows use in high density designs with

heavier than normal net loading conditions. Furthermore, the SSTUM32868 features two

additional chip select inputs, which allow more versatile enabling and disabling in densely

populated memory modules. Both added features (drive strength and chip selects) are

fully backward compatible to the JEDEC standard register. Finally, the SSTUM32868 is

optimized for the fastest propagation delay in the SSTU family of registers.

The SSTUM32868 is packaged in a 176-ball, 8 × 22 grid, 0.65 mm ball pitch, thin proﬁle

ﬁne-pitch ball grid array (TFBGA) package, which (while requiring a minimum

6 mm × 15 mm of board space) allows for adequate signal routing and escape using

conventional card technology.

2. Features

I 28-bit data register supporting DDR2

I Fully compliant to JEDEC standard for SSTUB32868

I Supports 2 rank by 4 DIMM density by integrating equivalent functionality of two

JEDEC-standard DDR2 registers (that is, 2 × SSTUA32864 or 2 × SSTUA32866)

I Parity checking function across 22 input data bits

I Parity out signal

I Controlled multi-impedance output impedance drivers enable optimal signal integrity

and speed

I Meets or exceeds SSTUB32868 JEDEC standard speed performance

I Supports up to 450 MHz clock frequency of operation

I Permanently conﬁgured for high output drive

I Optimized pinout for high-density DDR2 module design

I Chip-selects minimize power consumption by gating data outputs from changing state

SSTUM32868

NXP Semiconductors

1.8 V DDR2-800 conﬁgurable registered buffer with parity

I Two additional chip select inputs allow optional ﬂexible enabling and disabling

I Supports Stub Series Terminated Logic SSTL_18 data inputs

I Differential clock (CK and CK) inputs

I Supports Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS)

switching levels on the control and RESET inputs

I Single 1.8 V supply operation (1.7 V to 2.0 V)

I Available in 176-ball 6 mm × 15 mm, 0.65 mm ball pitch TFBGA package

3. Applications

I 400 MT/s to 800 MT/s high-density (for example, 2 rank by 4) DDR2 registered DIMMs

I DDR2 Registered DIMMs (RDIMM) desiring parity checking functionality

4. Ordering information

Table 1.

Ordering information

Solder process

Type number

Package

Name

Description

Version

SSTUM32868ET/G Pb-free (SnAgCu solder ball TFBGA176 plastic thin ﬁne-pitch ball grid array package; SOT932-1

compound) 176 balls; body 6 × 15 × 0.7 mm

SSTUM32868ET/S Pb-free (SnAgCu solder ball TFBGA176 plastic thin ﬁne-pitch ball grid array package; SOT932-1

compound)

176 balls; body 6 × 15 × 0.7 mm

4.1 Ordering options

Table 2.

Ordering options

Type number

SSTUM32868ET/G

SSTUM32868ET/S

Temperature range

T_amb= 0 °C to +70 °C

T_amb= 0 °C to +85 °C

SSTUM32868_2

Product data sheet

Rev. 02 — 2 March 2007

2 of 30

SSTUM32868

NXP Semiconductors

1.8 V DDR2-800 conﬁgurable registered buffer with parity

5. Functional diagram

RESET

SSTUM32868

CK

VREF

2

DCKE0,

DCKE1

2

QCKE0A,

QCKE1A

D

2

CLK

Q

QCKE0B,

QCKE1B

R

DODT0,

DODT1

2

QODT0A,

QODT1A

D

CLK

QODT0B,

QODT1B

R

DCS0

QCS0A

QCS0B

D

CLK

R

CSGEN

DCS1

QCS1A

QCS1B

D

CLK

R

Q

DCS2

DCS3

one of 22 channels

D1

CE

Q1A

Q1B

D

CLK

Q

R

(1)

to 21 other channels

002aac512

(1) Register A conﬁguration (C = 0): D2 to D5, D7, D9 to D12, D17 to D28

Register B conﬁguration (C = 1): D2 to D12, D17 to D20, D22, D24 to D28

Fig 1. Logic diagram of SSTUM32868 (positive logic)

SSTUM32868_2

Product data sheet

Rev. 02 — 2 March 2007

3 of 30

SSTUM32868

NXP Semiconductors

1.8 V DDR2-800 conﬁgurable registered buffer with parity

RESET

CK

22

(1)

22

Dn

(2)

(3)

D

QnA

QnB

VREF

22

CLK

Q

R

CE

22

PAR_IN

D

PARITY GENERATOR

AND

QERR

CLK

ERROR CHECK

R

CE

DCS0

D

QCS0A

QCS0B

CLK

R

Q

CSGEN

DCS1

D

QCS1A

QCS1B

CLK

R

Q

DCS2

DCS3

002aac497

(1) Register A conﬁguration (C = 0): D1 to D5, D7, D9 to D12, D17 to D28

Register B conﬁguration (C = 1): D1 to D12, D17 to D20, D22, D24 to D28

(2) Register A conﬁguration (C = 0): Q1A to Q5A, Q7A, Q9A to Q12A, Q17A to Q28A

Register B conﬁguration (C = 1): Q1A to Q12A, Q17A to Q20A, Q22A, Q24A to Q28A

(3) Register A conﬁguration (C = 0): Q1B to Q5B, Q7B, Q9B to Q12B, Q17B to Q28B

Register B conﬁguration (C = 1): Q1B to Q12B, Q17B to Q20B, Q22B, Q24B to Q28B

Fig 2. Parity logic diagram (positive logic)

SSTUM32868_2

Product data sheet

Rev. 02 — 2 March 2007

4 of 30

SSTUM32868

NXP Semiconductors

1.8 V DDR2-800 conﬁgurable registered buffer with parity

6. Pinning information

6.1 Pinning

SSTUM32868ET/G

SSTUM32868ET/S

ball A1

index area

2

4

6

8

1

3

5

7

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AA

AB

002aac513

Transparent top view

Fig 3. Pin conﬁguration for TFBGA176

SSTUM32868_2

Product data sheet

Rev. 02 — 2 March 2007

5 of 30

SSTUM32868

NXP Semiconductors

1.8 V DDR2-800 conﬁgurable registered buffer with parity

1

2

3

4

5

6

7

8

A

B

D2

D1

C

GND

VREF

GND

Q1A

Q1B

D4

D3

D5

D7

V

DD

Q2A

Q3A

Q2B

Q3B

Q4B

Q5B

DD

D6

(DCKE1)

GND

C

D

E

D8

(DCKE0)

V

Q4A

DD

Q6A

(QCKE1A)

D9

GND

Q5A

Q8A

(QCKE0A)

Q6B

(QCKE1B)

D10

D11

D12

V

Q7A

F

DD

Q10A

Q12A

GND

Q9A

Q7B

G

H

J

Q8B

(QCKE0B)

V

Q11A

Q10B

Q12B

DD

DCS1

(D13)

QCS1A

(Q13A)

GND

DCS2

PAR_IN

QERR

GND

Q9B

DCS0

(D14)

QCS0A

(Q14A)

V

Q11B

K

DD

Q14B

(QCS0B)

Q13B

(QCS1B)

CK

CSGEN

RESET

GND

L

Q15B

Q16B

V

M

N

P

DD

(QODT0B) (QODT1B)

D15

(DODT0)

Q15A

(QODT0A)

GND

Q17B

Q19B

Q18A

Q20A

Q22A

Q24A

Q25A

Q26A

Q27A

Q28A

Q18B

Q20B

Q21B

Q22B

Q23B

Q24B

Q25B

Q26B

Q27B

D16

(DODT1)

Q16A

(QODT1A)

DCS3

GND

V

DD

D17

D18

D19

D20

D21

D23

D25

D27

Q17A

Q19A

Q21A

Q23A

D22

GND

R

T

V

DD

U

V

GND

V

DD

W

Y

GND

D24

V

DD

AA

AB

D26

GND

n.c.

GND

D28

V

VREF

V

Q28B

DD

002aac554

176-ball, 8 × 22 grid; top view.

Fig 4. Ball mapping (1 : 2 Register A; C = 0)

SSTUM32868_2

Product data sheet

Rev. 02 — 2 March 2007

6 of 30

SSTUM32868

NXP Semiconductors

1.8 V DDR2-800 conﬁgurable registered buffer with parity

1

2

3

4

5

6

7

8

A

B

D2

D1

C

GND

VREF

GND

Q1A

Q1B

D4

D6

D3

D5

V

DD

Q2A

Q3A

Q4A

Q5A

Q7A

Q9A

Q11A

Q10B

Q2B

Q3B

Q4B

Q5B

Q6B

Q7B

Q8B

Q9B

DD

GND

C

D

E

D8

D7

V

DD

D9

Q6A

Q8A

Q10A

Q12A

GND

D10

D11

D12

V

DD

F

DD

GND

G

H

J

V

DD

D13

(DODT1)

Q13A

(QODT1A)

GND

DCS2

PAR_IN

QERR

GND

D14

(DODT0)

Q14A

(QODT0A)

V

Q12B

Q14B

Q11B

Q13B

K

DD

CK

CSGEN

RESET

GND

L

(QODT0B) (QODT1B)

Q15B

(QCS0B)

Q16B

(QCS1B)

V

M

N

P

DD

D15

(DCS0)

Q15A

(QCS0A)

GND

Q17B

Q19B

Q18A

Q20A

Q22A

Q24A

Q25A

Q26A

Q27A

Q28A

Q18B

Q20B

D16

(DCS1)

Q16A

(QCS1A)

DCS3

GND

V

DD

Q21B

(QCKE0B)

D17

D18

D19

D20

Q17A

Q19A

GND

R

T

V

DD

V

DD

Q22B

DD

Q21A

(QCKE0A)

Q23B

(QCKE1B)

U

V

GND

Q23A

(QCKE1A)

V

DD

Q24B

Q25B

Q26B

Q27B

DD

D21

(DCKE0)

W

Y

D22

D24

D26

D28

GND

D23

(DCKE1)

V

DD

V

DD

AA

AB

D25

D27

GND

n.c.

GND

V

VREF

V

Q28B

DD

002aac555

176-ball, 8 × 22 grid; top view.

Fig 5. Ball mapping (1 : 2 Register B; C = 1)

SSTUM32868_2

Product data sheet

Rev. 02 — 2 March 2007

7 of 30

SSTUM32868

NXP Semiconductors

1.8 V DDR2-800 conﬁgurable registered buffer with parity

6.2 Pin description

Table 3.

Symbol Pin

1 : 2 Register A (C = 0)

Ungated inputs

Pin description

Type

Description

1 : 2 Register B (C = 1)

DCKE0

DCKE1

D1

C1

W1

Y1

SSTL_18

The outputs of this register will not be

suspended by the DCS0 and DCS1

control.

DODT0

DODT1

N1

P1

K1

J1

The outputs of this register will not be

suspended by the DCS0 and DCS1

control.

Chip Select gated inputs

D1 to

D28

A2, A1, B2, B1, C2, C1,

D2, D1, E1, F1, G1, H1, J1,

K1, N1, P1, R1, T1, U1,

V1, W1, W2, Y1, Y2, AA1,

AA2, AB1, AB2

SSTL_18

Data inputs, clocked in on the crossing of

the rising edge of CD and the falling

edge of CK.

D2, D1, E1, F1, G1, H1,

N1, P1, R1, T1, U1, V1,

W1, W2, Y1, Y2, AA1,

AA2, AB1, AB2

Chip Select inputs

DCS0

DCS1

DCS2

DCS3

K1

J1

N1

P1

K3

P3

Chip select inputs. These pins initiate

DRAM address/command decodes, and

as such at least one will be LOW when a

valid address/command is present. The

register can be programmed to re-drive

all D-inputs (CSGEN = HIGH) only when

at least one chip select input is LOW. If

CSGEN, DCS0 and DCS1 inputs are

HIGH, D1 to D28^[1]inputs will be

disabled.

K3

P3

Conﬁguration control inputs

A3

C

A3

LVCMOS

input

Conﬁguration control inputs; Register A

or Register B

Re-driven outputs

Q1A to

Q28A

A7, B7, C7, D7, E7, E2, F7, A7, B7, C7, D7, E7, E2, F7, 1.8 V

Data outputs^[2]that are suspended by

the DCS0 and DCS1 control.

F2, G7, G2, H7, H2, N2,

P2, R2, R7, T2, T7, U2,

F2, G7, G2, H7, H2, J2,

K2, N2, P2, R2, R7, T2, T7, outputs

CMOS

U7, V2, V7, W7, Y7, AA7, U2, U7, V2, V7, W7, Y7,

AB7

AA7, AB7

Q1B to

Q28B

A8, B8, C8, D8, E8, F8,

G8, H8, J8, J7, K8, K7, L8, G8, H8, J8, J7, K8, K7, L8,

A8, B8, C8, D8, E8, F8,

L7, M7, M8, N7, N8, P7,

P8, R8, T8, V8, U8, W8,

Y8, AA8, AB8

L7, M7, M8, N7, N8, P7,

P8, R8, T8, U8, V8, W8,

Y8, AA8, AB8

QCS0A

QCS0B

QCS1A

QCS1B

K2

L7

J2

L8

N2

M7

P2

M8

1.8 V

CMOS

outputs

Data outputs that will not be suspended

by the DCS0 and DCS1 control.

SSTUM32868_2

Product data sheet

Rev. 02 — 2 March 2007

8 of 30

SSTUM32868

NXP Semiconductors

1.8 V DDR2-800 conﬁgurable registered buffer with parity

Table 3.

Pin description …continued

Symbol Pin

Type

Description

1 : 2 Register A (C = 0)

1 : 2 Register B (C = 1)

QCKE0A F2

QCKE0B H8

QCKE1A E2

QCKE1B F8

QODT0A N2

QODT0B M7

QODT1A P2

QODT1B M8

Output error

U2

R8

V2

U8

K2

L7

J2

1.8 V

CMOS

outputs

Data outputs that will not be suspended

by the DCS0 and DCS1 control.

1.8 V

CMOS

outputs

Data outputs that will not be suspended

by the DCS0 and DCS1 control.

L8

QERR

M3

open-drain Output error bit; generated on clock

output

cycle after the corresponding data

output.

Parity input

PAR_IN

L3

L2

SSTL_18

Parity input. Arrives one clock cycle after

the corresponding data input.

Program inputs

CSGEN L2

LVCMOS

input

Chip select gate enable. When HIGH,

the D1 to D28^[1]inputs will be latched

only when at least one chip select input

is LOW during the rising edge of the

clock. When LOW, the D1 to D28^[1]

inputs will be latched and re-driven on

every rising edge of the clock.

Clock inputs

CK

L1

differential Positive master clock input.

input

CK

M1

differential Negative master clock input.

input

Miscellaneous inputs

RESET

M2

LVCMOS

input

Asynchronous reset input. Resets

registers and disables VREF data and

clock differential-input receivers.

SSTUM32868_2

Product data sheet

Rev. 02 — 2 March 2007

9 of 30

SSTUM32868

NXP Semiconductors

1.8 V DDR2-800 conﬁgurable registered buffer with parity

Table 3.

Pin description …continued

Symbol Pin

Type

Description

1 : 2 Register A (C = 0)

1 : 2 Register B (C = 1)

VREF

V_DD

A5, AB5

0.9 V

nominal

Input reference voltage.

Power supply voltage.

B3, B4, B5, B6, D3, D4,

1.8 V

D5, D6, F3, F4, F5, F6, H3, D5, D6, F3, F4, F5, F6, H3, nominal

H4, H5, H6, K4, K5, K6,

M4, M5, M6, P4, P5, P6,

H4, H5, H6, K4, K5, K6,

M4, M5, M6, P4, P5, P6,

T3, T4, T5, T6, V3, V4, V5, T3, T4, T5, T6, V3, V4, V5,

V6, Y3, Y4, Y5, Y6, AB4,

AB6

V6, Y3, Y4, Y5, Y6, AB4,

AB6

GND

A4, A6, C3, C4, C5, C6,

E3, E4, E5, E6, G3, G4,

A4, A6, C3, C4, C5, C6,

E3, E4, E5, E6, G3, G4,

ground

input

Ground.

G5, G6, J3, J4, J5, J6, L4, G5, G6, J3, J4, J5, J6, L4,

L5, L6, N3, N4, N5, N6, R3, L5, L6, N3, N4, N5, N6, R3,

R4, R5, R6, U3, U4, U5,

U6, W3, W4, W5, W6, AA3, U6, W3, W4, W5, W6, AA3,

AA4, AA5, AA6 AA4, AA5, AA6

R4, R5, R6, U3, U4, U5,

[1] Data inputs = D1 to D5, D7, D9 to D12, D17 to D28 when C = 0.

Data inputs = D1 to D12, D17 to D20, D22, D24 to D28 when C = 1.

[2] Data outputs = Q1x to Q5x, Q7x, Q9x to Q12x, Q17x to Q28x when C = 0.

Data outputs = Q1x to Q12x, Q17x to Q20x, Q22x, Q24x to Q28x when C = 1.

7. Functional description

7.1 Function table

Table 4.

RESET

Function table (each ﬂip-ﬂop)

Inputs

CSGEN

Outputs^[1]

DCS0^[2]DCS1^[2]

CK

Dn, DODTn,

DCKEn

Qn QCS0x QCS1x QODTn,

QCKEn

H

L

X

L

↑

↓

L

H

X

L

H

L

H

↑

↓

L

L or H

Q₀

L

Q₀

L

Q₀

H

Q₀

L

H

L

↑

↓

L

↑

↓

H

X

L

H

L

H

L

L or H

Q₀

L

Q₀

H

Q₀

L

Q₀

L

H

↑

↓

L

↑

↓

H

X

L

H

L

H

L

L or H

Q₀

L

Q₀

H

Q₀

H

Q₀

L

H

↑

↓

L

↑

L or H

↑

↓

L or H

↓

H

X

L

H

L

Q₀

H

Q₀

H

Q₀

L

H

SSTUM32868_2

Product data sheet

Rev. 02 — 2 March 2007

10 of 30

SSTUM32868

NXP Semiconductors

1.8 V DDR2-800 conﬁgurable registered buffer with parity

Table 4.

RESET

Function table (each ﬂip-ﬂop) …continued

Inputs

Outputs^[1]

DCS0^[2]DCS1^[2]

CSGEN

CK

Dn, DODTn,

DCKEn

Qn QCS0x QCS1x QODTn,

QCKEn

H

L

H

↑

↓

H

X

Q₀

L

H

Q₀

L

H

Q₀

L

H

Q₀

L

L or H

X or

X or ﬂoating

X or

X or ﬂoating

ﬂoating

[1] Q₀is the previous state of the associated output.

[2] DCS2 and DCS3 operate identically to DCS0 and DCS1, except they do not have corresponding re-driven (QCS) outputs.

Table 5.

RESET

Parity and standby function table

Inputs

CK

Output

QERR^[3][4]

DCS0^[1]

DCS1^[1]

CK

∑ of inputs = H

PAR_IN^[2]

(D1 to D28)

H

L

X

L

↑

↓

even

odd

even

odd

even

odd

even

odd

X

L

H

L

↑

↓

L

↑

↓

H

L

↑

↓

H

L

X

H

X

↑

↓

L

↑

↓

L

↑

↓

H

L

↑

↓

H

[5]

H

X

QERR₀

L or H

X

QERR₀

H

X or ﬂoating X or ﬂoating X or ﬂoating X or ﬂoating

X

X or ﬂoating

[1] DCS2 and DCS3 operate identically to DCS0 and DCS1 with regard to the parity function.

[2] PAR_IN arrives one clock cycle after the data to which it applies.

[3] This transition assumes QERR is HIGH at the crossing of CK going HIGH and CK going LOW. If QERR is LOW, it stays latched LOW for

two clock cycles or until RESET is driven LOW.

[4] QERR₀is the previous state of output QERR.

[5] If DCS0, DCS1, DCS2, DCS3 and CSGEN are driven HIGH, the device is placed in Low-Power Mode (LPM). If a parity error occurs on

the clock cycle before the device enters the LPM and the QERR output is driven LOW, it stays latched LOW for the LPM duration plus

two clock cycles or until RESET is driven LOW.

7.2 Functional information

The SSTUM32868 is a 28-bit 1 : 2 conﬁgurable registered buffer designed for 1.7 V to

1.9 V V_DDoperation.

All inputs are compatible with the JEDEC standard for SSTL_18, except the chip-select

gate-enable (CSGEN), control (C), and reset (RESET) inputs, which are LVCMOS. All

outputs are edge-controlled circuits optimized for unterminated DIMM loads, and meet

SSTL_18 speciﬁcations, except the open-drain error (QERR) output.

SSTUM32868_2

Product data sheet

Rev. 02 — 2 March 2007

11 of 30

SSTUM32868

NXP Semiconductors

1.8 V DDR2-800 conﬁgurable registered buffer with parity

The device supports low-power standby operation. When RESET is LOW, the differential

input receivers are disabled, and undriven (ﬂoating) data, clock, and reference voltage

(VREF) inputs are allowed. In addition, when RESET is LOW, all registers are reset and

all outputs are forced LOW except QERR. The LVCMOS RESET and C inputs always

must be held at a valid logic HIGH or LOW level.

To ensure deﬁned outputs from the register before a stable clock has been supplied,

RESET must be held in the LOW state during power-up.

In the DDR2 RDIMM application, RESET is speciﬁed to be completely asynchronous with

respect to CK and CK. Therefore, no timing relationship can be ensured between the two.

When entering reset, the register will be cleared and the data outputs will be driven LOW

quickly, relative to the time to disable the differential input receivers. However, when

coming out of reset, the register will become active quickly, relative to the time to enable

the differential input receivers. As long as the data inputs are LOW, and the clock is stable

during the time from the LOW-to-HIGH transition of RESET until the input receivers are

fully enabled, the design of the SSTUM32868 must ensure that the outputs will remain

LOW, thus ensuring no glitches on the output.

The SSTUM32868 includes a parity checking function. Parity, which arrives one cycle

after the data input to which it applies, is checked on the PAR_IN input of the device. The

corresponding QERR output signal for the data inputs is generated two clock cycles after

the data, to which the QERR signal applies, is registered.

The SSTUM32868 accepts a parity bit from the memory controller on the parity bit

(PAR_IN) input, compares it with the data received on the DIMM-independent D inputs

(D1 to D5, D7, D9 to D12, D17 to D28 when C = 0; or D1 to D12, D17 to D20, D22, D24 to

D28 when C = 1) and indicates whether a parity error has occurred on the open-drain

QERR pin (active LOW). The convention is even parity, that is, valid parity is deﬁned as an

even number of ones across the DIMM-independent data inputs combined with the parity

input bit. To calculate parity, all DIMM-independent D inputs must be tied to a known logic

state.

If an error occurs and the QERR output is driven LOW, it stays latched LOW for a

minimum of two clock cycles or until RESET is driven LOW. If two or more consecutive

parity errors occur, the QERR output is driven LOW and latched LOW for a clock duration

equal to the parity error duration or until RESET is driven LOW. If a parity error occurs on

the clock cycle before the device enters the Low-Power Mode (LPM) and the QERR

output is driven LOW, then it stays latched LOW for the LPM duration plus two clock cycles

or until RESET is driven LOW. The DIMM-dependent signals (DCKE0, DCKE1, DODT0,

DODT1, DCS0, DCS1, DCS2 and DCS3) are not included in the parity check

computation.

The C input controls the pinout conﬁguration from Register A conﬁguration (when LOW) to

Register B conﬁguration (when HIGH). The C input should not be switched during normal

operation. It should be hard-wired to a valid LOW or HIGH level to conﬁgure the register in

the desired mode.

The device also supports low-power active operation by monitoring both system chip

select (DCS0, DCS1, DCS2 and DCS3) and CSGEN inputs and will gate the Qn outputs

from changing states when CSGEN, DCS0 and DCS1 inputs are HIGH. If CSGEN or the

DCSn inputs are LOW, the Qn outputs will function normally. Also, if all DCSn inputs are

HIGH, the device will gate the QERR output from changing states. If any of the DCSn are

SSTUM32868_2

Product data sheet

Rev. 02 — 2 March 2007

12 of 30

SSTUM32868

NXP Semiconductors

1.8 V DDR2-800 conﬁgurable registered buffer with parity

LOW, the QERR output will function normally. The RESET input has priority over the

DCSn control, and when driven LOW will force the Qn outputs LOW and the QERR output

HIGH. If the chip-select control functionality is not desired, then the CSGEN input can be

hard-wired to ground (GND), in which case the set-up time requirement for DCSn would

be the same as for the other D data inputs. To control the Low-power mode with DCSn

only, the CSGEN input should be pulled up to V_DDthrough a pull-up resistor.

The two VREF pins (A5 and AB5) are connected together internally by approximately

150 Ω. However, it is necessary to connect only one of the two VREF pins to the external

V_refpower supply. An unused VREF pin should be terminated with a V_refcoupling

capacitor.

The SSTUM32868 is available in a TFGBA176 package.

SSTUM32868_2

Product data sheet

Rev. 02 — 2 March 2007

13 of 30

SSTUM32868

NXP Semiconductors

1.8 V DDR2-800 conﬁgurable registered buffer with parity

7.3 Register timing

RESET

CSGEN

DCSn

CK

m

m + 1

m + 2

m + 3

m + 4

CK

t

ACT

t

h

su

Dn, DODTn,

(1)

DCKEn

t

, t

PDM PDMSS

CK to Q

Qn, QODTn,

QCKEn

t

h

su

(1)

PAR_IN

t

, t

PHL PLH

PHL

CK to QERR

(2)

QERR

data to QERR latency

HIGH, LOW, or Don't care

HIGH or LOW

002aab899

(1) After RESET is switched from LOW to HIGH, all data and PAR_IN input signals must be set and held LOW for a minimum

time of t_ACT(max)to avoid false error.

(2) If the data is clocked on the m clock pulse, and PAR_IN is clocked in at m + 1, the QERR output signal will be produced on

the m + 2 clock pulse and it will be valid on the m + 3 clock pulse.

Fig 6. Timing diagram during start-up (RESET switches from LOW to HIGH)

SSTUM32868_2

Product data sheet

Rev. 02 — 2 March 2007

14 of 30

SSTUM32868

NXP Semiconductors

1.8 V DDR2-800 conﬁgurable registered buffer with parity

RESET

CSGEN

DCSn

CK

m

m + 1

m + 2

m + 3

m + 4

CK

t

h

su

Dn, DODTn,

DCKEn

t

, t

PDM PDMSS

CK to Q

Qn, QODTn,

QCKEn

t

su

t

h

PAR_IN

t

, t

PHL PLH

CK to QERR

(1)

QERR

data to QERR latency

output signal is dependent

on the prior unknown event

unknown input event

HIGH or LOW

002aab900

(1) If the data is clocked in on the m clock pulse, and PAR_IN is clocked in at m + 1, the QERR output signal will be generated

on the m + 2 clock pulse and it will be valid on the m + 3 clock pulse. If an error occurs and the QERR output is driven LOW,

it stays LOW for a minimum of two clock cycles or until RESET is driven LOW.

Fig 7. Timing diagram during normal operation (RESET = HIGH)

SSTUM32868_2

Product data sheet

Rev. 02 — 2 March 2007

15 of 30

SSTUM32868

NXP Semiconductors

1.8 V DDR2-800 conﬁgurable registered buffer with parity

RESET

t

INACT

(1)

CSGEN

(1)

DCSn

(1)

CK

(1)

CK

Dn, DODTn,

(1)

DCKEn

t

PHL

RESET to Q

Qn, QODTn,

QCKEn

(1)

PAR_IN

t

PLH

RESET to QERR

QERR

HIGH, LOW, or Don't care

HIGH or LOW

002aac511

(1) After RESET is switched from HIGH to LOW, all data and clock input signals must be held at valid logic levels (not ﬂoating)

for a minimum time of t_INACT(max)

.

Fig 8. Timing diagram during shutdown (RESET switches from HIGH to LOW)

SSTUM32868_2

Product data sheet

Rev. 02 — 2 March 2007

16 of 30

SSTUM32868

NXP Semiconductors

1.8 V DDR2-800 conﬁgurable registered buffer with parity

8. Limiting values

Table 6.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter

Conditions

Min

Max

Unit

V

V_DD

V_I

supply voltage

−0.5

+2.5

[1][2]

input voltage (receiver)

output voltage (driver)

input clamping current

output clamping current

output current (continuous)

−0.5

+2.5

V

V_O

I_IK

−0.5

V_DD+ 0.5

±50

V

V_I< 0 V or V_I> V_DD

V_O< 0 V or V_O> V_DD

0 V < V_O< V_DD

-

mA

I_OK

I_O

±50

I_CCC

continuous current through

each V_DDor GND pin

±100

T_stg

storage temperature

−65

2

+150

°C

kV

V

V_esd

electrostatic discharge

voltage

Human Body Model (HBM); 1.5 kΩ; 100 pF

Machine Model (MM); 0 Ω; 200 pF

-

200

[1] The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.

[2] This value is limited to 2.5 V maximum.

9. Recommended operating conditions

Table 7.

Recommended operating conditions

Conditions

Symbol Parameter

Min

Typ

Max

Unit

V

V_DD

supply voltage

1.7

-

2.0

V_ref

reference voltage

termination voltage

input voltage

0.49 × V_DD0.50 × V_DD0.51 × V_DD

V

V_T

V_ref− 0.040 V_ref

V_ref+ 0.040 V

V_I

0

-

V_DD

-

V

[1]

[2]

V_IH(AC)

V_IL(AC)

V_IH(DC)

V_IL(DC)

V_IH

AC HIGH-level input voltage Dn, CSR and PAR_IN inputs

AC LOW-level input voltage Dn, CSR and PAR_IN inputs

DC HIGH-level input voltage Dn, CSR and PAR_IN inputs

DC LOW-level input voltage Dn, CSR and PAR_IN inputs

V_ref+ 0.250

-

V_ref− 0.250

V_ref+ 0.125

-

V_ref− 0.125

HIGH-level input voltage

LOW-level input voltage

RESET, CSGEN

0.65 × V_DD

-

V_IL

-

0.35 × V_DD

V_ICR

common mode input voltage CK, CK

range

0.675

1.125

V_ID

I_OH

I_OL

differential input voltage

HIGH-level output current

LOW-level output current

ambient temperature

CK, CK

600

-

mV

mA

-

−8

8

T_amb

operating in free air

SSTUM32868ET/G

SSTUM32868ET/S

0

-

+70

+85

°C

[1] The differential inputs must not be ﬂoating, unless RESET is LOW.

[2] The RESET input of the device must be held at valid logic levels (not ﬂoating) to ensure proper device operation.

SSTUM32868_2

Product data sheet

Rev. 02 — 2 March 2007

17 of 30

SSTUM32868

NXP Semiconductors

1.8 V DDR2-800 conﬁgurable registered buffer with parity

10. Characteristics

Table 8.

Characteristics

Over recommended operating conditions, unless otherwise noted.

Symbol

V_OH

V_OL

I_I

Parameter

Conditions

Min

Typ

Max

-

Unit

V

HIGH-level output voltage

LOW-level output voltage

input current

I_OH= −6 mA; V_DD= 1.7 V

I_OL= 6 mA; V_DD= 1.7 V

all inputs; V_I= V_DDor GND; V_DD= 1.9 V

1.2

-

0.5

±5

2

V

µA

mA

I_DD

supply current

static standby; RESET = GND; V_DD= 1.9 V;

I_O= 0 mA

static operating; RESET = V_DD

_DD= 1.9 V; I_O= 0 mA;

V_I= V_IH(AC)or V_IL(AC)

;

-

80

-

mA

µA

V

I_DDD

dynamic operating current

per MHz

clock only; RESET = V_DD

;

16

19

V_I= V_IH(AC)or V_IL(AC); CK and CK switching

at 50 % duty cycle. I_O= 0 mA; V_DD= 1.8 V

per each data input (1 : 1 mode);

-

RESET = V_DD; V_I= V_IH(AC)or V_IL(AC)

;

CK and CK switching at 50 % duty cycle.

One data input switching at half clock

frequency, 50 % duty cycle. I_O= 0 mA;

V_DD= 1.8 V

per each data input (1 : 2 mode);

-

19

-

µA

RESET = V_DD; V_I= V_IH(AC)or V_IL(AC)

;

CK and CK switching at 50 % duty cycle.

One data input switching at half clock

frequency, 50 % duty cycle. I_O= 0 mA;

V_DD= 1.8 V

C_i

input capacitance

Dn, CSGEN, PAR_IN inputs;

V_I= V_ref± 250 mV; V_DD= 1.8 V

2.5

2

-

4

3

pF

DCSn; V_ICR= 0.9 V; V_ID= 600 mV;

V

_DD= 1.8 V

CK and CK; V_ICR= 0.9 V; V_ID= 600 mV;

_DD= 1.8 V

V

RESET; V_I= V_DDor GND; V_DD= 1.8 V

instantaneous

3

-

5

-

pF

Ω

[1]

Z_o

output impedance

7

steady-state

-

53

-

Ω

[1] Instantaneous is deﬁned as within < 2 ns following the output data transition edge.

SSTUM32868_2

Product data sheet

Rev. 02 — 2 March 2007

18 of 30

SSTUM32868

NXP Semiconductors

1.8 V DDR2-800 conﬁgurable registered buffer with parity

Table 9.

Timing requirements

Over recommended operating conditions, unless otherwise noted.

Symbol Parameter

Conditions

Min

Typ

Max

450

-

Unit

MHz

ns

f_clk

clock frequency

-

t_W

pulse duration

CK, CK HIGH or LOW

1

-

[1][2]

[1][3]

t_ACT

t_INACT

differential inputs active time

10

ns

differential inputs inactive

time

-

15

ns

t_su

set-up time

DCSn before CK↑, CK↓, CSR HIGH;

CSR before CK↑, CK↓, DCSn HIGH

0.6

-

ns

DCSn before CK↑, CK↓, CSR LOW

DODTn, DCKEn ad Dn before CK↑, CK↓

PAR_IN before CK↑, CK↓

0.5

0.4

-

ns

t_h

hold time

DCSn, DODTn, DCKEn and Dn after

CK↑, CK↓

PAR_IN after CK↑, CK↓

0.4

-

ns

[1] This parameter is not necessarily production tested.

[2] VREF must be held at a valid input voltage level, and data inputs must be held LOW for a minimum time of t_ACT(max)after RESET is

taken HIGH.

[3] VREF, data and clock inputs must be held at valid voltage levels (not ﬂoating) a minimum time of t_INACT(max)after RESET is taken LOW.

Table 10. Switching characteristics

Over recommended operating conditions, unless otherwise noted.

Symbol Parameter

f_clk(max)maximum clock frequency

t_PDM

Conditions

Min

450

1.1

Typ

Max

-

Unit

MHz

ns

input

-

[1]

peak propagation delay

single bit switching;

1.5

from CK↑ and CK↓ to Qn

t_PLH

LOW-to-HIGH propagation delay

from CK↑ and CK↓ to QERR

from RESET↑ to QERR↓

from CK↑ and CK↓ to QERR

from RESET↑ to Qn↓

1.2

-

3

ns

-

3

t_PHL

HIGH-to-LOW propagation delay

1

-

2.4

3

[1]

t_PDMSS

simultaneous switching

peak propagation delay

from CK↑ and CK↓ to Qn

-

1.6

[1] Includes 350 ps of test-load transmission line delay.

Table 11. Output edge rates

Over recommended operating conditions, unless otherwise noted.

Symbol

dV/dt_r

dV/dt_f

dV/dt_∆

Parameter

Conditions

Min

Typ

Max

Unit

V/ns

rising edge slew rate

falling edge slew rate

from 20 % to 80 %

from 80 % to 20 %

1

-

4

1

absolute difference between dV/dt_r (from 20 % to 80 %) or

and dV/dt_f

(from 80 % to 20 %)

SSTUM32868_2

Product data sheet

Rev. 02 — 2 March 2007

19 of 30

SSTUM32868

NXP Semiconductors

1.8 V DDR2-800 conﬁgurable registered buffer with parity

11. Test information

11.1 Parameter measurement information for data output load circuit

V_DD= 1.8 V ± 0.1 V.

All input pulses are supplied by generators having the following characteristics:

Pulse Repetition Rate (PRR) ≤ 10 MHz; Z₀= 50 Ω; input slew rate = 1 V/ns ± 20 %,

unless otherwise speciﬁed.

The outputs are measured one at a time with one transition per measurement.

V

DD

DUT

R

= 1000 Ω

delay = 350 ps

= 50 Ω

L

50 Ω

Z

o

CK

CK inputs

OUT

(1)

= 30 pF

C

L

R

L

test point

R

L

= 100 Ω

test point

002aab902

(1) C_Lincludes probe and jig capacitance.

Fig 9. Load circuit, data output measurements

LVCMOS

V

DD

0.5V

RESET

DD

0 V

t

ACT

INACT

90 %

(1)

DD

I

10 %

002aaa372

(1) I_DDtested with clock and data inputs held at V_DDor GND, and I_O= 0 mA.

Fig 10. Voltage and current waveforms; inputs active and inactive times

t

W

V

IH

IL

V

input

V

ICR

ID

ICR

002aaa373

V_ID= 600 mV.

V_IH= V_ref+ 250 mV (AC voltage levels) for differential inputs. V_IH= V_DDfor LVCMOS inputs.

V_IL= V_ref− 250 mV (AC voltage levels) for differential inputs. V_IL= GND for LVCMOS inputs.

Fig 11. Voltage waveforms; pulse duration

SSTUM32868_2

Product data sheet

Rev. 02 — 2 March 2007

20 of 30

SSTUM32868

NXP Semiconductors

1.8 V DDR2-800 conﬁgurable registered buffer with parity

CK

V

ICR

ID

CK

t

h

su

V

IH

IL

input

V

ref

V

ref

002aaa374

V_ID= 600 mV.

V_ref= 0.5V_DD

.

V_IH= V_ref+ 250 mV (AC voltage levels) for differential inputs. V_IH= V_DDfor LVCMOS inputs.

V_IL= V_ref− 250 mV (AC voltage levels) for differential inputs. V_IL= GND for LVCMOS inputs.

Fig 12. Voltage waveforms; set-up and hold times

CK

V

i(p-p)

ICR

CK

t

PHL

PLH

V

OH

OL

V

output

T

002aaa375

t_PLHand t_PHLare the same as t_PD

.

Fig 13. Voltage waveforms; propagation delay times (clock to output)

LVCMOS

V

IH

RESET

0.5V

DD

IL

t

PHL

OH

OL

output

V

T

002aaa376

t_PLHand t_PHLare the same as t_PD

.

V_IH= V_ref+ 250 mV (AC voltage levels) for differential inputs. V_IH= V_DDfor LVCMOS inputs.

V_IL= V_ref− 250 mV (AC voltage levels) for differential inputs. V_IL= GND for LVCMOS inputs.

Fig 14. Voltage waveforms; propagation delay times (reset to output)

SSTUM32868_2

Product data sheet

Rev. 02 — 2 March 2007

21 of 30

SSTUM32868

NXP Semiconductors

1.8 V DDR2-800 conﬁgurable registered buffer with parity

11.2 Data output slew rate measurement

V_DD= 1.8 V ± 0.1 V.

All input pulses are supplied by generators having the following characteristics:

PRR ≤ 10 MHz; Z₀= 50 Ω; input slew rate = 1 V/ns ± 20 %, unless otherwise speciﬁed.

V

DD

R

DUT

= 50 Ω

L

OUT

test point

002aaa377

(1)

= 10 pF

C

L

(1) C_Lincludes probe and jig capacitance.

Fig 15. Load circuit, HIGH-to-LOW slew measurement

output

V

OH

80 %

dv_f

20 %

V

OL

dt_f

002aaa378

Fig 16. Voltage waveforms, HIGH-to-LOW slew rate measurement

DUT

OUT

test point

(1)

= 10 pF

C

L

R

L

= 50 Ω

002aaa379

(1) C_Lincludes probe and jig capacitance.

Fig 17. Load circuit, LOW-to-HIGH slew measurement

dt_r

V

OH

80 %

dv_r

20 %

output

OL

002aaa380

Fig 18. Voltage waveforms, LOW-to-HIGH slew rate measurement

SSTUM32868_2

Product data sheet

Rev. 02 — 2 March 2007

22 of 30

SSTUM32868

NXP Semiconductors

1.8 V DDR2-800 conﬁgurable registered buffer with parity

11.3 Error output load circuit and voltage measurement

V_DD= 1.8 V ± 0.1 V.

All input pulses are supplied by generators having the following characteristics:

PRR ≤ 10 MHz; Z₀= 50 Ω; input slew rate = 1 V/ns ± 20 %, unless otherwise speciﬁed.

V

DD

R

DUT

= 1 kΩ

L

OUT

test point

002aaa500

(1)

= 10 pF

C

L

(1) C_Lincludes probe and jig capacitance.

Fig 19. Load circuit, error output measurements

LVCMOS

V

DD

RESET

0.5V

DD

0 V

t

PLH

V

OH

output

waveform 2

0.15 V

0 V

002aab903

Fig 20. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to

RESET input

timing

inputs

V

i(p-p)

V

ICR

t

PHL

V

DD

OL

output

waveform 1

0.5V

DD

002aab904

Fig 21. Voltage waveforms, open-drain output HIGH-to-LOW transition time with respect

to clock inputs

SSTUM32868_2

Product data sheet

Rev. 02 — 2 March 2007

23 of 30

SSTUM32868

NXP Semiconductors

1.8 V DDR2-800 conﬁgurable registered buffer with parity

timing

inputs

V

i(p-p)

V

ICR

t

PLH

V

OH

output

waveform 2

0.15 V

0 V

002aab907

Fig 22. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to

clock inputs

SSTUM32868_2

Product data sheet

Rev. 02 — 2 March 2007

24 of 30

SSTUM32868

NXP Semiconductors

1.8 V DDR2-800 conﬁgurable registered buffer with parity

12. Package outline

TFBGA176: plastic thin fine-pitch ball grid array package; 176 balls; body 6 x 15 x 0.7 mm

SOT932-1

D

B

A

ball A1

index area

A

2

E

A

1

detail X

e

1

1/2 e

C

e

y

C

1

y

M

v

C

A

B

b

w

AB

AA

Y

W

V

T

P

U

R

N

e

M

K

H

e

2

L

J

1/2 e

G

F

E

D

B

C

A

ball A1

index area

1

3

5

7

2

4

6

8

X

0

5

10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

UNIT

A

1

A

2

b

D

E

e

1

e

2

v

w

y

1

max

0.35 0.80 0.45

0.25 0.65 0.35

6.1

5.9

15.1

14.9

mm

1.15

0.65 4.55 13.65 0.15 0.08

0.1

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

06-01-11

06-01-16

SOT932-1

- - -

MO-246

- - -

Fig 23. Package outline SOT932-1 (TFBGA176)

SSTUM32868_2

Product data sheet

Rev. 02 — 2 March 2007

25 of 30

SSTUM32868

NXP Semiconductors

1.8 V DDR2-800 conﬁgurable registered buffer with parity

13. Soldering

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reﬂow

soldering description”.

13.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

13.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

• Board speciﬁcations, including the board ﬁnish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus PbSn soldering

13.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath speciﬁcations, including temperature and impurities

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1.8 V DDR2-800 conﬁgurable registered buffer with parity

13.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 24) than a PbSn process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 12 and 13

Table 12. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

235

≥ 350

220

< 2.5

≥ 2.5

220

Table 13. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 24.

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Product data sheet

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1.8 V DDR2-800 conﬁgurable registered buffer with parity

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 24. Temperature proﬁles for large and small components

For further information on temperature proﬁles, refer to Application Note AN10365

“Surface mount reﬂow soldering description”.

14. Abbreviations

Table 14. Abbreviations

Acronym

CMOS

DDR2

Description

Complementary Metal Oxide Semiconductor

Double Data Rate 2

DIMM

Dual In-line Memory Module

DRAM

LVCMOS

PRR

Dynamic Random Access Memory

Low Voltage Complementary Metal Oxide Semiconductor

Pulse Repetition Rate

RDIMM

SSTL

Registered Dual In-line Memory Module

Stub Series Terminated Logic

15. Revision history

Table 15. Revision history

Document ID

SSTUM32868_2

Modiﬁcations:

Release date

20070302

Data sheet status

Change notice

Supersedes

Product data sheet

SSTUM32868_1

• The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• Table 8 “Characteristics”, symbol I_DD: changed static standby condition’s maximum value

from “100 µA” to “2 mA”

SSTUM32868_1

20060912

Product data sheet

-

SSTUM32868_2

Product data sheet

Rev. 02 — 2 March 2007

28 of 30

SSTUM32868

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1.8 V DDR2-800 conﬁgurable registered buffer with parity

16. Legal information

16.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

malfunction of a NXP Semiconductors product can reasonably be expected to

16.2 Deﬁnitions

result in personal injury, death or severe property or environmental damage.

NXP Semiconductors accepts no liability for inclusion and/or use of NXP

Semiconductors products in such equipment or applications and therefore

such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

16.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

16.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

17. Contact information

For additional information, please visit: http://www.nxp.com

For sales ofﬁce addresses, send an email to: salesaddresses@nxp.com

SSTUM32868_2

Product data sheet

Rev. 02 — 2 March 2007

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18. Contents

1

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2

3

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3

4

4.1

5

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8

7

Functional description . . . . . . . . . . . . . . . . . . 10

Function table . . . . . . . . . . . . . . . . . . . . . . . . . 10

Functional information . . . . . . . . . . . . . . . . . . 11

Register timing . . . . . . . . . . . . . . . . . . . . . . . . 14

7.1

7.2

7.3

8

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 17

Recommended operating conditions. . . . . . . 17

Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 18

9

10

11

11.1

Test information. . . . . . . . . . . . . . . . . . . . . . . . 20

Parameter measurement information for

data output load circuit . . . . . . . . . . . . . . . . . . 20

Data output slew rate measurement. . . . . . . . 22

Error output load circuit and voltage

11.2

11.3

measurement . . . . . . . . . . . . . . . . . . . . . . . . . 23

12

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 25

13

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Introduction to soldering . . . . . . . . . . . . . . . . . 26

Wave and reﬂow soldering . . . . . . . . . . . . . . . 26

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 26

Reﬂow soldering . . . . . . . . . . . . . . . . . . . . . . . 27

13.1

13.2

13.3

13.4

14

15

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 28

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 28

16

Legal information. . . . . . . . . . . . . . . . . . . . . . . 29

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 29

Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 29

16.1

16.2

16.3

16.4

17

18

Contact information. . . . . . . . . . . . . . . . . . . . . 29

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 2 March 2007

Document identifier: SSTUM32868_2


型号：	SSTUM32868ET/S
厂家：	NXP
描述：	1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications 1.8 V 28位1 ： 2配置的注册校验缓冲DDR2-800 RDIMM应用触发器锁存器逻辑集成电路双倍数据速率
文件：	总30页 (文件大小：169K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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