TDA1566TH/N2S,118 [NXP]
TDA1566 - I2C-bus controlled dual channel 46 W/2 Ohm, single channel 92 W/1 Ohm amplifier with load diagnostic features SOIC 24-Pin;
| 型号： | TDA1566TH/N2S,118 |
| 厂家： | 
NXP |
| 描述： | TDA1566 - I2C-bus controlled dual channel 46 W/2 Ohm, single channel 92 W/1 Ohm amplifier with load diagnostic features SOIC 24-Pin 放大器 光电二极管 商用集成电路 |
| 文件： | 总46页 (文件大小：290K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TDA1566
I2C-bus controlled dual channel 46 W/2 Ω, single channel
92 W/1 Ω amplifier with load diagnostic features
Rev. 02 — 20 August 2007
Product data sheet
1. General description
The TDA1566 is a car audio power amplifier with a complementary output stage realized
in BCDMOS. The TDA1566 has two Bridge Tied Load (BTL) output stages and comes in a
HSOP24 or DBS27P package.
The TDA1566 can be controlled with or without I2C-bus. With I2C-bus control gain settings
per channel and diagnostic trigger levels can be selected. Failure conditions as well as
load identification can be read with I2C-bus. The load identification detects whether the
outputs of a BTL channel are connected with a DC or AC load and discriminates between
a speaker load, a line driver load and an open (unconnected) load.
The TDA1566 can be configured in a single BTL mode and drive a 1 Ω load. For the single
BTL mode it is necessary to connect on the Printed-Circuit Board (PCB) the outputs of
both BTL channels in parallel.
2. Features
I Operates in I2C-bus mode and non-I2C-bus mode
I TH version: four I2C-bus addresses controlled by two pins; J version: two I2C-bus
addresses controlled by one pin
I Two 4 Ω or 2 Ω capable BTL channels or one 1 Ω capable BTL channel
I Low offset
I Pop free off/standby/mute/operating mode transitions
I Speaker fault detection
I Selectable gain (26 dB and 16 dB)
I In I2C-bus mode:
N DC load detection: open, short and speaker or line driver present
N AC load (tweeter) detection
N Programmable trigger levels for DC and AC load detection
N Per channel programmable gain (26 dB and 16 dB, selectable per channel)
N Selectable diagnostic levels for clip detection and thermal pre-warning
N Selectable information on the DIAG pin for clip information of each channel
separately and independent enabling of thermal-, offset- or load fault
I Independent short-circuit protection per channel
I Loss of ground and open VP safe
I All outputs short-circuit proof to VP, GND and across the load
I All pins short-circuit proof to ground
I Temperature controlled gain reduction at high junction temperatures
TDA1566
NXP Semiconductors
I2C-bus controlled dual channel/single channel amplifier
I Fault condition diagnosis per channel: short to ground, short to supply, shorted lead
and speaker fault (wrongly connected)
I Low battery voltage detection
I TH version: pin compatible with the TDA8566TH1
3. Ordering information
Table 1.
Ordering information
Type number Package
Name
Description
Version
TDA1566TH
HSOP24
plastic, heatsink small outline package; 24 leads; low
stand-off height
SOT566-3
TDA1566J
DBS27P
plastic DIL-bent-SIL (special bent) power package;
27 leads (lead length 6.8 mm)
SOT827-1
4. Block diagram
V
V
P2
ADS2
8
ADS1
9
SDA
6
SCL
5
P1
14
23
22
13
PROG
CLIP
7
MODE
SELECT
SELECT DIAGNOSTIC
/CLIP DETECT
2
EN
I C-BUS
1
DIAG
16
18
10
11
2
OUT1+
OUT1−
IN1+
IN1−
IN2+
IN2−
MUTE
26 dB/
16 dB
PROTECTION
/DIAGNOSTIC
MUTE
MUTE
MUTE
19
21
OUT2+
OUT2−
26 dB/
16 dB
PROTECTION
/DIAGNOSTIC
V
P
3
15
24
1OHM
TAB
TDA1566TH
4
12
17
20
SVR
SGND
PGND1
PGND2
001aac999
Fig 1. Block diagram (TDA1566TH)
TDA1566_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 20 August 2007
2 of 46
TDA1566
NXP Semiconductors
I2C-bus controlled dual channel/single channel amplifier
V
V
P2
ADS1
2
SDA
26
SCL
25
P1
7
21
20
6
PROG
DIAG
1
MODE
SELECT
SELECT DIAGNOSTIC
/CLIP DETECT
2
EN
I C-BUS
10
13
3
OUT1+
OUT1−
IN1+
IN1−
IN2+
IN2−
MUTE
MUTE
MUTE
MUTE
26 dB/
16 dB
PROTECTION
/DIAGNOSTIC
4
15
18
22
23
OUT2+
OUT2−
26 dB/
16 dB
PROTECTION
/DIAGNOSTIC
V
P
9, 11, 14,
17, 19
n.c.
8
1OHM
TDA1566J
27
TAB
24
5
12
16
PGND2
SVR
SGND
PGND1
001aad002
Fig 2. Block diagram (TDA1566J)
TDA1566_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 20 August 2007
3 of 46
TDA1566
NXP Semiconductors
I2C-bus controlled dual channel/single channel amplifier
5. Pinning information
5.1 Pinning
24
23
22
21
20
19
18
17
16
15
14
13
1
2
TAB
DIAG
IN2+
IN2−
SVR
SCL
V
P2
3
PROG
OUT2−
PGND2
OUT2+
OUT1−
PGND1
OUT1+
1OHM
4
5
6
SDA
EN
TDA1566TH
7
8
ADS2
ADS1
IN1+
IN1−
SGND
9
10
11
12
V
P1
CLIP
001aad006
Fig 3. Pin configuration for TDA1566TH (top view)
TDA1566_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 20 August 2007
4 of 46
TDA1566
NXP Semiconductors
I2C-bus controlled dual channel/single channel amplifier
1
EN
ADS1
IN1+
2
3
4
IN1−
5
SGND
DIAG
6
7
V
P1
8
1OHM
n.c.
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
OUT1+
n.c.
PGND1
OUT1−
n.c.
TDA1566J
OUT2+
PGND2
n.c.
OUT2−
n.c.
PROG
V
P2
IN2+
IN2−
SVR
SCL
SDA
TAB
001aad007
Fig 4. Pin configuration for non mounting base TDA1566J (front)
5.2 Pin description
Table 2.
Pin description TDA1566TH
Symbol
DIAG
IN2+
IN2−
SVR
Pin
1
Description
diagnostic output
2
positive input channel 2
negative input channel 2
supply voltage ripple decoupling
I2C-bus clock input
3
4
SCL
5
SDA
6
I2C-bus data input/output
EN
7
enable input
ADS2
ADS1
IN1+
IN1−
SGND
8
I2C-bus address select bit 2
I2C-bus address select bit 1
positive input channel 1
negative input channel 1
signal ground
9
10
11
12
TDA1566_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 20 August 2007
5 of 46
TDA1566
NXP Semiconductors
I2C-bus controlled dual channel/single channel amplifier
Table 2.
Pin description TDA1566TH …continued
Symbol
CLIP
Pin
13
14
15
16
17
18
19
20
21
22
23
24
Description
clip detect and temperature pre-warning output
supply voltage channel 1
1 Ω select pin
VP1
1OHM
OUT1+
PGND1
OUT1−
OUT2+
PGND2
OUT2−
PROG
VP2
positive output channel 1
power ground channel 1
negative output channel 1
positive output channel 2
power ground channel 2
negative output channel 2
program input/output
supply voltage channel 2
connect to PGND
TAB
Table 3.
Symbol
EN
Pin description TDA1566J
Pin
1
Description
enable input
ADS1
IN1+
2
I2C-bus address select bit 1
positive input channel 1
negative input channel 1
signal ground
3
IN1−
4
SGND
DIAG
VP1
5
6
diagnostic output
7
supply voltage channel 1
1 Ω select pin
1OHM
n.c.
8
9
not connected
OUT1+
n.c.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
positive output channel 1
not connected
PGND1
OUT1−
n.c.
power ground channel 1
negative output channel 1
not connected
OUT2+
PGND2
n.c.
positive output channel 2
power ground channel 2
not connected
OUT2−
n.c.
negative output channel 2
not connected
PROG
VP2
program input/output
supply voltage channel 2
positive input channel 2
negative input channel 2
supply voltage ripple decoupling
IN2+
IN2−
SVR
TDA1566_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 20 August 2007
6 of 46
TDA1566
NXP Semiconductors
I2C-bus controlled dual channel/single channel amplifier
Table 3.
Pin description TDA1566J …continued
Symbol
SCL
Pin
25
26
27
Description
I2C-bus clock input
I2C-bus data input/output
connect to PGND
SDA
TAB
6. Functional description
6.1 General
Naming conventions used in this document:
• Reference to bits in instruction bytes: IBx[Dy] refers to bit Dy of instruction byte x
• Reference to bits in data bytes: DBx[Dy] refers to bit Dy of data byte x
6.1.1 Mode selection
The ADS1 pin selects the I2C-bus or non-I2C-bus mode operation as listed in Table 4. See
Section 6.1.6 and Section 6.4.3 for the ADS1 pin functionality.
Table 4.
Pin
Mode selection with the ADS1 pin
Non-I2C-bus mode
GND
I2C-bus mode
ADS1
open or via 33 kΩ to GND
Table 5 lists the control for the I2C-bus mode operation. In I2C-bus mode the EN pin
operates at CMOS compatible LOW and HIGH logic levels. With the EN pin LOW the
TDA1566 is switched off and the quiescent current is at its lowest value. With the enable
pin HIGH the operation mode of the TDA1566 is selected with IB1[D0] and IB1[D1]. The
I2C-bus instruction and data bytes are described in Section 6.4.2 and Section 6.4.3.
Table 5.
EN pin
I2C-bus mode operation
IB1[D0]
IB2[D0]
Operation mode
operating
mute
HIGH (> 2.6 V)
1
0
1
1
0
don’t care
don’t care
standby
off
LOW (< 1.0 V)
don’t care
In non-I2C-bus mode the TDA1566 has 3 operation modes: off/mute/operation. The
operation mode is selected with the EN pin. Figure 5 displays the required voltage levels
at the EN pin in I2C-bus and non-I2C-bus mode. For the voltage levels see Section 9
“Characteristics”.
TDA1566_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 20 August 2007
7 of 46
TDA1566
NXP Semiconductors
I2C-bus controlled dual channel/single channel amplifier
2
I C-bus mode
off
operation mode defined by IB1[D0] and IB2[D0]
0 V
1.0 V
2.6 V
V
P
2
non-I C-bus mode
off
mute
operating
0 V
1.0 V
2.6 V
4.5 V
6.5 V
V
P
001aad008
Fig 5. Enable pin mode switching in I2C-bus and non-I2C-bus mode
6.1.2 Gain selection
The TDA1566 features a 16 dB and a 26 dB gain setting. The 16 dB setting is referred to
as line driver mode, the 26 dB setting is referred to as amplifier mode. Table 6 shows how
the gain is selected.
Table 6.
Gain select in I2C-bus and non-I2C-bus mode
Gain select
I2C-bus
16 dB
26 dB
IB3[D6] = 1
IB3[D5] = 1
IB3[D6] = 0[1]
IB3[D5] = 0[2]
PROG open[3]
Non-I2C-bus
PROG connected with 1.5 kΩ
to GND
[1] Channel 1.
[2] Channel 2.
[3] Both channels.
6.1.2.1 I2C-bus mode
The gain is selected with IB3[D6] for channel 1 and IB3[D5] for channel 2. If the gain
select is performed when the amplifier is muted, the gain select will be pop free. See
Section 6.4.2 for the definition of the instruction bytes.
If DC load detection is used, IB1[D1] = 1, auto gain select is activated. Detection of an
open load (see Section 6.2.1) will result in a line driver mode setting. If the load detection
data is invalid, IB3[D5] and IB3[D6] will define the gain setting.
6.1.2.2 Non-I2C-bus mode
The gain for channel 1 and channel 2 is selected with the PROG pin. Leaving the pin
unconnected selects 26 dB gain and connecting a resistor of 1500 Ω between the PROG
pin and GND selects 16 dB gain.
When the amplifier is used in line driver mode loads of 2 Ω and 4 Ω can be driven. With a
load larger than 25 Ω a Zobel network of 33 nF in series with 22 Ω should be connected
between the amplifier output terminals. The Zobel network should be placed close to the
output pins. To prevent instability in 1 Ω mode the amplifier must not be used in line driver
mode with a load larger than 25 Ω.
TDA1566_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 20 August 2007
8 of 46
TDA1566
NXP Semiconductors
I2C-bus controlled dual channel/single channel amplifier
6.1.3 Balanced and unbalanced input sources
The TDA1566 accepts balanced as well as unbalanced input signals. Table 7 and Table 8
show the required hard or software setting and Figure 6 shows the input source
connection. Note that the unbalanced input source should be connected to the positive
BTL channel input. Note that the J version accepts in non-I2C-bus mode only a balanced
input source.
Table 7.
Balanced and unbalanced input source setting TDA1566TH
Source
Balanced input source
IB3[D1] = 0
Unbalanced input source
I2C-bus mode
Non-I2C-bus mode
IB3[D1] = 1
ADS2 pin connected to GND
ADS2 pin unconnected
Table 8.
Balanced and unbalanced input source setting TDA1566J
Source
Balanced input source
IB3[D1] = 0
Unbalanced input source
I2C-bus mode
Non-I2C-bus mode
IB3[D1] = 1
default
not selectable
001aad009
Fig 6. Balanced (left) and unbalanced (right) input source
6.1.4 Single channel 1 Ω operation
The input and output pins for single channel 1 Ω operation are listed in Table 9. The 1 Ω
operation requires that on the PCB the output pins are shorted as indicated in Table 9. In
the 1 Ω operation the input signal is taken from channel 1.
To prevent instability in 1 Ω operation the amplifier must not be used in line driver mode
with a load larger than 25 Ω.
Table 9.
Symbol
Pinning for the single channel 1 Ω mode; TDA1566TH and TDA1566J
Pin
Pin
Description single channel
operation
Description dual channel
operation
(TDA1566TH)
(TDA1566J)
IN2+
2
3
22
23
disabled: connect IN2+ with 470 nF
to SGND
positive input channel 2
IN2−
disabled: connect IN2+ with 470 nF
to SGND
negative input channel 2
IN1+
10
11
15
16
18
19
21
3
positive input channel 1
positive input channel 1
IN1−
4
negative input channel 1
1 Ω select pin connected to VP
positive output channel 1
negative output channel 1
shorted on board to OUT1−
shorted on board to OUT1+
negative input channel 1
1 Ω select pin connected to GND
positive output channel 1
negative output channel 1
positive output channel 2
negative output channel 2
1OHM
OUT1+
OUT1−
OUT2+
OUT2−
8
10
13
15
18
TDA1566_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 20 August 2007
9 of 46
TDA1566
NXP Semiconductors
I2C-bus controlled dual channel/single channel amplifier
6.1.5 Mute speed setting
In I2C-bus mode the amplifier can be muted slow (20 ms) or fast (0.1 ms). The mute speed
is selected with IB2[D2].
See Section 6.4.2 for the definition of the instruction bytes. Table 10 lists the operation
mode transitions where slow and fast mute are applied. The operation modes are
described in Section 6.1.1, Table 5.
Table 10. Mute speed setting
Mode transition
Mute to operating
Operating to mute
I2C-bus mode
slow mute
Non-I2C-bus mode
slow mute
IB2[D2] = 0: slow mute
IB2[D2] = 1: fast mute
slow mute
slow mute
Operating to standby
Operating to off
n.a.
fast mute
fast mute
6.1.6 Pins with double functions
Table 11. Pins with double functions
Pin
I2C-bus mode
Non-I2C-bus mode
PROG
load detection reference
current programming, see
Section 6.2.1 and 6.2.2
gain select, see Section 6.1.2
ADS1
I2C-bus address select bit 1,
see Section 6.4.1
non-I2C-bus mode select, see
Section 6.1.1
ADS2[1]
I2C-bus address select bit 2,
see Section 6.4.1
balanced/unbalanced input,
see Section 3
EN
chip enable, see Section 6.1.1 mode select, see Section 6.1.1
[1] TH version only.
6.2 Load identification (I2C-bus mode only)
6.2.1 DC load detection
The default setting IB1[D1] = 0 disables DC load detection. When the DC load detection is
enabled with IB1[D1] = 1, an offset is slowly applied at the output of the amplifiers at the
beginning of the start-up cycle. The DC load is measured and compared with Rtrip1 and
Rtrip2 to distinguish between an amplifier load, line driver load or open load. Rtrip1 and
Rtrip2 are set with resistor RPROG (1 %) connected between the PROG pin and GND.
amplifier load
25 Ω
line driver load
100 Ω 500 Ω
open load
5 kΩ
0 Ω
∞
R
trip1
R
trip2
001aad010
Fig 7. DC load detection limits (RPROG = 1500 Ω/1 %)
The relation between RPROG, Rtrip1 and Rtrip2 is approximated by (valid for RPROG should
be between 1.2 kΩ and 4 kΩ):
TDA1566_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 20 August 2007
10 of 46
TDA1566
NXP Semiconductors
I2C-bus controlled dual channel/single channel amplifier
Rtrip1 = 0.1 × (RPROG − 720) Ω
Rtrip2 = 1.05 × (RPROG − 450) Ω
Rtrip1 and Rtrip2 levels presented refer to the advised value of 1500 Ω. Note that a shorted
load will be interpreted as an amplifier load.
The result of the DC load detection is stored in DB1[D4] and DB1[D5] for channel 1 and in
DB2[D4] and DB2[D5] for channel 2, see Table 12.
Table 12. Interpretation of DC load detection bits
Open load bits
Amplifier load bits
DC load valid bit
Description
DB1[D4] and DB2[D4] DB1[D5] and DB2[D5] DB3[D3]
0
0
1
1
1
0
amplifier load
line driver load
open load
0
1
1
don’t care
don’t care
Don’t care
invalid DC load
detection result
Note that the DC load bits are only valid if DB3[D3] = 1. The DC load detection valid bit is
reset, DB3[D3] = 0, when the DC load detection is started with a not completely
discharged SVR capacitor (VSVR > 0.3 V) or when the DC load detection is interrupted by
an engine start (VP < 7.5 V typical, see Section 9).
6.2.2 AC load detection
The AC load detection is used to detect if AC coupled speakers like tweeters are
connected correctly during assembly. The detection starts when IB1[D2] changes from
LOW to HIGH. A sine wave of a certain frequency (e.g. 19 kHz) needs to be applied to the
inputs of the amplifier. The output voltage over the load impedance will cause an output
current in the amplifier. Output currents larger than 1.15 × Iref will set the AC load
detection bit and no AC load is detected when the output current is less than 0.85 × Iref,
see Figure 8. The reference current Iref is set with an external resistor RPROG (1 %)
connected between the PROG pin and GND. The relation between RPROG and Iref is given
by:
Iref = 390 / RPROG [A] (valid for RPROG between 1.2 kΩ and 4 kΩ).
To set the AC load detection bit the peak output current must pass the 1.15 × Iref threshold
three times. The three ‘threshold cross’ counter is used to prevent false AC load detection
caused by switching the input signal on or off. To reset the slope counter, IB1[D2] needs to
be reset. With RPROG = 1500 Ω the current thresholds are set to 200 mA and 320 mA.
0.78 × I
1.22 × I
ref
ref
no AC load detected
AC load detected
200 mA
(peak)
320 mA
(peak)
001aad011
Fig 8. AC load detection limits
The levels presented refer to the advised value of 1500 Ω.
TDA1566_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 20 August 2007
11 of 46
TDA1566
NXP Semiconductors
I2C-bus controlled dual channel/single channel amplifier
For instance at an output voltage of 4 V peak the total impedance must be less than 10 Ω
to detect the AC coupled load or more than 13.4 Ω to guarantee no connected AC load is
detected. Values between 10 Ω and 13.4 Ω cannot be recognized. The result of the AC
load detection is shown in DB1[D7] for channel 1 and DB2[D7] for channel 2.
When IB1[D2] = 1 the AC load detection is enabled. The AC load detection can only be
performed after the amplifier has completed its start-up cycle and will not conflict with the
DC load detection. The default setting of IB1[D2] = 0 disables AC load detection.
Note: in the 1 Ω mode Iref is doubled, so Iref = 2 × 390 / RPROG [A].
6.3 Diagnostic
6.3.1 Diagnostic table
The available diagnostic information is shown in Table 13 and Table 14. Refer to Table 17
and Table 18 for the bitmap of the instruction and data bytes.
DIAG and CLIP have an open-drain output, are active LOW and must have an external
pull-up resistor to an external voltage.
DIAG shows fixed information and via the I2C-bus selectable information. This information
will be seen on DIAG and CLIP as a logical OR. The temperature pre-warning diagnostic
and clip information is available on the CLIP.
In case of a failure, DIAG will remain LOW and the microprocessor can read out the failure
information via the I2C-bus. The I2C-bus bits are set on a failure and will be reset with the
I2C-bus read command. Even when the failure is removed the microprocessor will know
what was wrong by reading the I2C-bus. The consequence of this procedure is that during
the I2C-bus read old information is read. Most actual information will be gathered with 2
read commands after each other.
DIAG will give actual diagnostic information (when selected). When a failure is removed,
DIAG will be released instantly, independently of the I2C-bus latches.
Table 13. Available diagnostic data TH version
Diagnostic
I2C-bus mode
Non-I2C-bus mode
DIAG
yes
CLIP
no
DIAG
no
CLIP
no
POR
Low VP or load
dump detection
yes
no
yes
no
Clip detection
selectable
selectable
yes
yes
no
no
yes
yes
Temperature
pre-warning
Short
selectable
selectable
no
no
yes
yes
no
no
Speaker
protection
Offset detection
selectable
yes
no
no
yes
yes
no
no
Maximum
temperature
protection
Load detection
no
no
no
no
TDA1566_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 20 August 2007
12 of 46
TDA1566
NXP Semiconductors
I2C-bus controlled dual channel/single channel amplifier
Note that in the J version no CLIP pin is available.
Table 14. Available diagnostic data J version
Diagnostic
I2C-bus mode
Non-I2C-bus mode
DIAG
DIAG
no
POR
yes
Low VP or load dump detection yes
yes
yes
yes
yes
yes
no
Clip detection
selectable
Temperature pre-warning
Short
selectable
selectable
selectable
selectable
yes
Speaker protection
Offset detection
Maximum temperature
protection
yes
Load detection
no
no
Following diagnostic information is only available via I2C-bus:
• DC and AC load detection results, see Section 6.2
• DB3[D4] is set when the DC settling of the amplifier has almost completed and the
SVR voltage has risen to a value of VP / 2 or above, see Section 6.5.1
6.3.2 Diagnostic level settings
Table 15. Clip and temperature pre-warning level setting
Setting
I2C-bus mode
Non-I2C-bus mode
Clip detection level
IB2[D7] = 0 selects 3 %
IB2[D7] = 1 selects 7 %
3 %
Temperature pre-warning level IB3[D4] = 0 selects 145 °C
IB3[D4] = 1 selects 122 °C
145 °C
6.3.3 Temperature pre-warning
If in I2C-bus mode the average junction temperature reaches a by I2C-bus selectable level,
the pre-warning will be activated resulting in a LOW CLIP pin.
In non-I2C mode the thermal pre-warning is set on 145 °C.
In the TH version the thermal pre-warning is available on the CLIP pin in I2C-bus mode
and non-I2C mode.
In the J version the thermal pre-warning is available on the DIAG pin in non-I2C-bus mode.
In I2C-bus mode the presence of the thermal pre-warning on the DIAG is selected with
IB1[D4], see Section 6.3.1 and Section 6.4.2.
If the temperature increases above the pre-warning level, the temperature controlled gain
reduction will be activated for both channels resulting in a lower output power. If this does
not reduce the average junction temperature, both channels will be switched off at the
absolute maximum temperature Toff, typical 175 °C.
TDA1566_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 20 August 2007
13 of 46
TDA1566
NXP Semiconductors
I2C-bus controlled dual channel/single channel amplifier
6.3.4 Speaker protection
To prevent damage of the speaker when one side of the speaker is connected to ground,
see Figure 9, a ‘missing current protection’ is implemented.
I
I
O2
O1
001aad012
Fig 9. Speaker protection condition
When in one BTL channel the absolute value of the current through the output terminals
differ, so |IO1| ≠ |IO2|, a fault condition is assumed, and the BTL channel will be switched off.
The ‘speaker protection active’ diagnosis options for I2C-bus and non-I2C-bus mode are
listed in Table 13.
6.3.5 Offset detection
The offset detection can be performed with no input signal (for instance when the DSP is
in mute after a start-up) or with input signal.
In I2C-bus mode the offset bits DB1[D2] and DB2[D2] are set by executing a read
command. The offset bits will be reset when the BTL output voltage
Vo = |VOUT1+ − VOUT1−| enters the offset threshold window of 1.5 V. The offset bits are read
with a 2nd read command.
In non-I2C-bus mode (or in I2C-bus mode with offset diagnostic selected on DIAG) DIAG
will be pulled LOW if the BTL output voltage is more than 1.5 V.
TDA1566_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 20 August 2007
14 of 46
TDA1566
NXP Semiconductors
I2C-bus controlled dual channel/single channel amplifier
V
= V
− V
V
= V
− V
OUT+ OUT−
o
OUT+
OUT−
o
offset
threshold
offset
threshold
time
time
DB1[D2] read
DIAG
DB1[D2] =
1
0
0 => 1
time
V
= V
− V
V
= V
− V
OUT+ OUT−
o
OUT+
OUT−
o
offset
threshold
offset
threshold
time
time
DB1[D2] read
DB1[D2] =
DIAG
1
1
1
time
001aad013
2
2
I C-bus mode only
TH version only: Non-I C-bus mode
2
TH/J version:
I C-bus mode with offset
fault selected on DIAG
Fig 10. Offset detection in I2C-bus mode and in non-I2C-bus mode
6.4 I2C-bus operation
6.4.1 I2C-bus address with hardware address select
Table 16. I2C-bus address table TH version
ADS1
ADS2
open
GND
A6
1
A5
1
A4
0
A3
1
A2
0
A1
0
A0
0
R/W[1]
1/0
open
1
1
0
1
0
0
1
1/0
33 kΩ to GND open
1
1
0
1
0
1
0
1/0
GND
1
1
0
1
0
1
1
1/0
[1] 0 = write to TDA1566TH; 1 = read from TDA1566TH.
Table 17. I2C-bus address table J version
ADS1
A6
1
A5
1
A4
0
A3
1
A2
0
A1
A0
R/W[1]
1/0
open
0
1
1
1
33 kΩ to GND
1
1
0
1
0
1/0
[1] 0 = write to TDA1566J; 1 = read from TDA1566J.
TDA1566_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 20 August 2007
15 of 46
TDA1566
NXP Semiconductors
I2C-bus controlled dual channel/single channel amplifier
6.4.2 Instruction bytes
If R/W bit = 0, the TDA1566 expects 3 instruction bytes; IB1, IB2 and IB3. After a
power-on reset, all instruction bits are set to zero. In 1 Ω mode the instruction bits of
channel 1 are used. The instruction bits labelled ‘reserved for test’ should be set to zero.
Table 18. Instruction bytes
Bit
Instruction byte IB1
Instruction byte IB2
Instruction byte IB3
D7
0
1
0
1
0
1
0
1
slow start enable
0
clip detect level on
3 %
reserved for test
slow start disable
1
clip detect level on
7 %
D6
D5
D4
channel 1 no clip
detect on DIAG
reserved for test
0
1
0
1
0
1
channel 1 26 dB gain
channel 1 clip detect
on DIAG
channel 1 16 dB gain
channel 2 26 dB gain
channel 2 16 dB gain
channel 2 no clip
detect on DIAG
reserved for test
channel 2 clip detect
on DIAG
no temperature pre-
warning on DIAG
0
1
speaker protection or
short on DIAG
temperature pre-
warning on 145 °C
temperature pre-
warning on DIAG
no speaker protection
or short on DIAG
temperature pre-
warning on 122 °C
D3
D2
reserved for test
reserved for test
0
1
0
channel 1 enabled
channel 1 disabled
channel 2 enabled
0
AC load detection
0
slow mute (20 ms)
disabled; detection
slope counter reset
1
0
1
0
1
AC load detection
enabled
1
0
1
0
1
fast mute (0.1 ms)
offset fault on DIAG
no set fault on DIAG
1
0
1
channel 2 disabled
balanced input
D1
D0
DC load detection
disabled
DC load detection
enabled
unbalanced input
TDA1566 in standby
channel 1 and
channel 2 operating
reserved for test
TDA1566 in mute or
operating (see
IB2[D0])
channel 1 and
channel 2 muted
6.4.3 Data bytes
If R/W = 1, the TDA1566 will send 3 data bytes to the microprocessor: DB1, DB2, and
DB3. All short diagnostic and offset detect bits are latched. All bits are reset after a read
operation except DB1[D7], DB2[D7], DB1[D4], DB2[D4], DB1[D5] and DB2[D5]. DB1[D2]
and DB2[D2] are set after a read operation, see Section 6.3.5. DB1[D7] and DB2[D7] are
reset when IB1[D2] is LOW. In 1 Ω mode the diagnostic information will be shown in DB1.
The content of the bits ‘reserved for test’ should be ignored.
TDA1566_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 20 August 2007
16 of 46
TDA1566
NXP Semiconductors
I2C-bus controlled dual channel/single channel amplifier
Table 19. Data bytes
Bit
Data byte DB1 channel 1
Data byte DB2 channel 2
Data byte DB3 both
channels
D7
0
1
no AC load detected
AC load detected
0
1
no AC load detected
AC load detected
0
TDA1566 in mute or
operating
(IB1[D0] = 1)
1
power-on reset has
occurred or TDA1566
in standby
(IB1[D0] = 0)
D6
D5
0
1
no speaker fault
speaker fault
0
1
no speaker fault
speaker fault
0
1
below maximum
temperature
maximum
temperature
protection activated
0
1
amplifier load (D4 = 0) 0
not valid (D4 = 1)
amplifier load (D4 = 0) 0
not valid (D4 = 1)
no temperature
warning
line driver load
(D4 = 0)
1
line driver load
(D4 = 0)
1
temperature
pre-warning active
open load (D4 = 1)
open load (D4 = 1)
D4
0
1
amplifier load (D5 = 0) 0
amplifier load (D5 = 0) 0
SVR below VP / 2
SVR above VP / 2
line driver load
(D5 = 1)
line driver load
(D5 = 1)
not valid (D5 = 0)
open load (D5 = 1)
no shorted load
shorted load
1
not valid (D5 = 0)
open load (D5 = 1)
no shorted load
shorted load
1
D3
D2
D1
D0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
invalid DC load data
valid DC load data
no output offset
output offset detected
no short to VP
no output offset
output offset detected
no short to VP
reserved for test
reserved for test
reserved for test
short to VP
short to VP
no short to ground
short to ground
no short to ground
short to ground
6.5 Timing waveforms
6.5.1 Start-up and shutdown
To prevent switch-on or switch-off pop noise, the capacitor on the SVR pin CSVR is used
for smooth start-up and shutdown. During start-up and shutdown the output voltage tracks
the SVR voltage. With IB1[D7] = 0 the time constant made with the SVR capacitor can be
increased to reduce turn on transients at the load. Consequently the start-up time
td(mute_off) increases with approximately 420 ms (VP = 14.4 V, CSVR = 22 µF, Tamb = 25 °C).
Note that in non-I2C-bus mode the IB1[D7] = 0 setting will be used.
Increasing CSVR results in a longer start-up and shutdown time. Note that a larger SVR
capacitor value will also result in a longer DC load detection cycle.
TDA1566_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 20 August 2007
17 of 46
TDA1566
NXP Semiconductors
I2C-bus controlled dual channel/single channel amplifier
For optimized pop performance it is recommended to keep the amplifier in mute until the
SVR voltage has reached its final level.
When the amplifier is switched off by pulling the EN pin LOW the amplifier is muted (fast
mute) and the capacitor on the SVR pin will be discharged. With an SVR capacitor of
22 µF the off current is reached 2 s after the EN pin is switched to zero.
Start-up and shutdown in I2C-bus mode is shown in Figure 11 and explained in Table 20.
V
P
DIAG
DB3[D7]
DB3[D4]
5
9
3
7
4
IB1[D0]
IB2[D0] = 0
2
6
1
8
EN
10
SVR
t
dcload
t
d(mute-fgain)
slow
mute
fast
mute
t
wake
t
d(mute_off)
OUTx
001aad014
Fig 11. Start-up and shutdown timing in I2C-bus mode
Table 20. Start-up and shutdown timing in I2C-bus mode
Step
Action
Result
1
TDA1566 is enabled with EN TDA1566 from off to standby
DB3[D7] is set and DIAG is pulled LOW to indicate
power-on reset
2
TDA1566 is switched from
standby to operating with
IB1[D0] = 1
DIAG is released
DB3[D7] is reset
SVR capacitor is charged, OUTx voltage tracks SVR
voltage
gradual increase of gain; when the SVR voltage increases
above a threshold of 2 V + 2VBE the amplifiers operate at
full gain
TDA1566_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 20 August 2007
18 of 46
TDA1566
NXP Semiconductors
I2C-bus controlled dual channel/single channel amplifier
Table 20. Start-up and shutdown timing in I2C-bus mode …continued
Step
Action
Result
3
SVR voltage has become larger than VP / 2 resulting in
setting DB3[D4]
4
TDA1566 is switched from
operating to standby with
IB1[D0] = 0
DIAG is pulled LOW
SVR is discharged, OUTx voltage tracks SVR voltage
amplifier is slow muted
5
6
SVR voltage has dropped below VP / 2 resulting in
resetting DB3[D4]
TDA1566 is switched from
standby to operating with
IB1[D0] = 1
see step 2
7
8
see step 3
TDA1566 is disabled with
EN
DIAG is pulled LOW
amplifier is fast muted
SVR is discharged, OUTx voltage tracks SVR voltage
see step 5
9
10
OUTx is at ground potential, DIAG is released, TDA1566 is
off
6.5.2 Engine start
The DC-output voltage of the amplifier follows the voltage on the SVR pin. On the SVR pin
a capacitor is connected which is used for start-up and shutdown timing as well as for DC
load detection. If the supply voltage drops during engine start below 8.6 V the SVR
capacitor will be discharged and the fast mute is activated to prevent audible transients at
the output.
If in I2C-bus mode the supply voltage drops below 5.5 V (see VP(POR)) the content of the
I2C-bus latches cannot be guaranteed and the power-on reset will be activated:
DB3[D7] = 1. All latches will be reset, the amplifier is switched off and the DIAG pin will be
pulled LOW to indicate that a power-on reset has occurred. The TDA1566 will not start-up
but wait for a command to start-up.
7. Limiting values
Table 21. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
18
Unit
V
VP
supply voltage
operating; RL = 4 Ω
-
-
operating; RL = 2 Ω or
1 Ω
16
V
non operating
−1
+50
50
V
V
load dump protection;
during 50 ms;
-
tr ≥ 2.5 ms
VP(r)
IOSM
reverse supply voltage
maximum 10 minutes
-
-
−2
V
A
non-repetitive peak output current
13
TDA1566_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 20 August 2007
19 of 46
TDA1566
NXP Semiconductors
I2C-bus controlled dual channel/single channel amplifier
Table 21. Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
IORM
Parameter
Conditions
Min
Max
8
Unit
A
repetitive peak output current
peak back gate current
-
-
IBGM
loss off GND or open
VP application failure;
supply decoupling
capacitor of maximum
3 × 2200 µF/16 V and
a series resistance of
70 mΩ
50
A
[1]
[1]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
V1OHM
VEN
voltage on pin 1OHM
voltage on pin EN
operating,
non operating
0
0
0
0
0
0
0
0
0
0
0
0
0
0
24
24
13
13
13
13
13
13
13
13
6.5
6.5
6.5
6.5
V
V
V
V
V
V
V
V
V
V
V
V
V
V
operating,
non operating
VIN1-
voltage on pin IN1−
voltage on pin IN1+
voltage on pin IN2−
voltage on pin IN2+
voltage on pin DIAG
voltage on pin CLIP
voltage on pin PROG
voltage on pin SVR
voltage on pin SCL
voltage on pin SDA
voltage on pin ADS1
voltage on pin ADS2
operating,
non operating
VIN1+
VIN2-
operating,
non operating
operating,
non operating
VIN2+
VDIAG
VCLIP
VPROG
VSVR
VSCL
VSDA
VADS1
VADS2
operating,
non operating
operating,
non operating
operating,
non operating
operating,
non operating
operating,
non operating
operating,
non operating
operating,
non operating
operating,
non operating
operating,
non operating
Tj
junction temperature
storage temperature
ambient temperature
protection voltage
-
150
+150
+85
VP
°C
°C
°C
V
Tstg
Tamb
V(prot)
−55
−40
-
AC and DC short-circuit
voltage of output pins
and across the load
Ptot
total power dissipation
Tcase = 70 °C
-
80
W
TDA1566_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 20 August 2007
20 of 46
TDA1566
NXP Semiconductors
I2C-bus controlled dual channel/single channel amplifier
Table 21. Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
Vesd
electrostatic discharge voltage
HBM
C = 100 pF;
-
2000
V
Rs = 1500 Ω
MM
C = 200 pF;
Rs = 10 Ω;
L = 0.75 µH
-
200
V
[1] The voltage on this pin is clamped by an ESD protection. If this pin is connected to VP a series resistance of 10 kΩ should be added.
[2] The voltage on this pin is clamped by an ESD protection.
8. Thermal characteristics
Table 22. Thermal characteristics
Symbol
Parameter
Conditions
Typ
Unit
Rth(j-c)
thermal resistance from junction
to case
TDA1566TH
TDA1566J
1.0
1.0
K/W
K/W
Rth(j-a)
thermal resistance from junction
to ambient
TDA1566TH
TDA1566J
in free air
in free air
35
35
K/W
K/W
9. Characteristics
Table 23. Characteristics
Refer to test circuit (see Figure 22); VP = 14.4 V; RL = 4 Ω; −40 °C < Tamb < +85 °C and −40 °C < Tj < +150 °C; unless
otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supply voltage behavior
VP(oper)
operating supply
voltage
RL = 4 Ω
VP(low)(mute) 14.4
VP(low)(mute) 14.4
18
V
[1]
RL = 2 Ω or 1 Ω
no load
I2C-bus mode only
16
V
Iq
quiescent current
standby current
off-state current
output voltage
-
180
10
220
15
mA
mA
µA
V
Istb
-
Ioff
VEN ≤ 0.4 V; Tj < 85 °C
-
2
10
VO
6.7
6.5
7.0
4.1
7.2
7.2
7.6
5.0
7.6
7.7
8.2
5.8
VP(low)(mute)
low supply voltage
mute
falling supply voltage
rising supply voltage
V
V
VP(POR)
power-on reset supply
voltage
V
TDA1566_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 20 August 2007
21 of 46
TDA1566
NXP Semiconductors
I2C-bus controlled dual channel/single channel amplifier
Table 23. Characteristics …continued
Refer to test circuit (see Figure 22); VP = 14.4 V; RL = 4 Ω; −40 °C < Tamb < +85 °C and −40 °C < Tj < +150 °C; unless
otherwise specified.
Symbol
Parameter
Conditions
Min
−50
−25
−25
Typ
0
Max
+50
+25
+25
Unit
mV
mV
mV
VO(offset)
output offset voltage
amplifier mode; on
line driver mode; on
0
amplifier and line driver mode;
mute
0
Mode select pin EN (see Figure 5)
VEN voltage on pin EN
off condition; I2C-bus and
non-I2C-bus mode
-
-
1.0
V
standby mode; I2C-bus mode
mute condition; non-I2C-bus
mode
2.6
2.6
-
-
VP
V
V
4.5
[2]
[3]
operating condition;
non-I2C-bus mode
6.5
-
-
VP
70
V
IEN
current on pin EN
VEN = 8.5 V
10
µA
Start-up, shutdown and mute timing (see Figure 11)
twake
wake-up time
time after wake-up via EN pin
before first I2C-bus
-
300
500
µs
transmission is recognized
td(mute_off)
mute off delay time
I2C-bus mode with slow start
enabled and non-I2C-bus
mode; DC load detection
disabled
[4]
[4]
C
SVR = 22 µF
-
-
380
170
-
-
ms
ms
CSVR = 10 µF
I2C-bus mode only; DC load
detection enabled; slow start
enabled
[4]
[4]
C
SVR = 22 µF
-
-
510
250
-
-
ms
ms
CSVR = 10 µF
I2C-bus mode only; DC load
detection disabled; slow start
disabled
[4]
[4]
C
SVR = 22 µF
-
-
230
110
-
-
ms
ms
CSVR = 10 µF
I2C-bus mode only; DC load
detection enabled; slow start
disabled
[4]
[4]
C
SVR = 22 µF
-
-
370
180
-
-
ms
ms
CSVR = 10 µF
tdet(DCload)
DC load detection
time
I2C-bus mode only; DC load
detection enabled
[4]
[4]
[5]
[5]
CSVR = 22 µF
CSVR = 10 µF
-
-
-
-
160
70
-
-
-
-
ms
ms
ms
ms
td(mute-fgain)
mute to full gain delay CSVR = 22 µF
90
time
CSVR = 10 µF
40
TDA1566_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 20 August 2007
22 of 46
TDA1566
NXP Semiconductors
I2C-bus controlled dual channel/single channel amplifier
Table 23. Characteristics …continued
Refer to test circuit (see Figure 22); VP = 14.4 V; RL = 4 Ω; −40 °C < Tamb < +85 °C and −40 °C < Tj < +150 °C; unless
otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
td(mute-on)
mute to on delay time I2C-bus mode:
IB2[D0] = 1 to 0
-
20
40
ms
non-I2C-bus mode: VEN from
3.3 V to 8 V
slow mute delay time I2C-bus mode:
-
-
20
20
40
40
ms
ms
td(slow_mute)
IB2[D0] = 0 to 1; IB2[D2] = 0
non-I2C-bus mode: VEN from
8 V to 3.3 V
on to mute in I2C-bus mode;
IB2[D2] = 1; IB2[D0] = 0 to 1
-
-
20
40
1
ms
ms
td(fast_mute)
fast mute delay time
0.1
on to standby in I2C-bus mode;
IB2[D0] = 0; IB1[D0] = 1 to 0
on to off in I2C-bus and
non-I2C-bus mode: VEN from
8 V to 0.5 V
-
-
20
40
1
ms
ms
0.1
t(on-SVR)
time from amplifier
switch-on to SVR
above VP / 2
via I2C-bus (IB1[D0]) to
DB3[D4] = 1 (SVR above
VP / 2); I2C-bus mode with slow
start enabled; DC load
detection disabled
C
SVR = 22 µF
-
-
1000
440
-
-
ms
ms
CSVR = 10 µF
I2C-bus mode only; DC load
detection enabled; slow start
enabled.
C
SVR = 22 µF
-
-
1100
530
-
-
ms
ms
CSVR = 10 µF
I2C-bus mode only; DC load
detection disabled; slow start
disabled
C
SVR = 22 µF
-
-
810
370
-
-
ms
ms
CSVR = 10 µF
I2C-bus mode only; DC load
detection enabled; slow start
disabled
C
SVR = 22 µF
-
-
940
450
-
-
ms
ms
CSVR = 10 µF
I2C-bus interface and 1 Ω selection[6]
VIL(SCL)
VIL(SDA)
VIH(SCL)
LOW-level input
voltage on pin SCL
-
-
-
-
1.5
1.5
5.5
V
V
V
LOW-level input
voltage on pin SDA
-
HIGH-level input
2.3
voltage on pin SCL
TDA1566_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 20 August 2007
23 of 46
TDA1566
NXP Semiconductors
I2C-bus controlled dual channel/single channel amplifier
Table 23. Characteristics …continued
Refer to test circuit (see Figure 22); VP = 14.4 V; RL = 4 Ω; −40 °C < Tamb < +85 °C and −40 °C < Tj < +150 °C; unless
otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIH(SDA)
HIGH-level input
2.3
-
5.5
V
voltage on pin SDA
VOL(SDA)
LOW-level output
Iload = 5 mA
-
-
0.4
V
voltage on pin SDA
fclk
clock frequency
-
400
-
kHz
V
[7]
V1OHM
voltage on pin 1OHM mono channel mode
dual channel mode
2.5
-
VP
1.5
200
5
0
-
-
-
-
-
-
-
-
-
V
I1OHM
current on pin 1OHM V1OHM = 1.5 V
V1OHM = 5.5 V
130
µA
µA
µA
µA
µA
µA
µA
µA
-
ISCL
current on pin SCL
current on pin SDA
current on pin ADS1
VSCL = 1.5 V
-
5
VSCL = 5.5 V
-
5
ISDA
VSDA = 1.5 V
-
5
VSDA = 5.5 V
-
5
IADS1
ADS1 pin connected to GND
300
70
400
100
ADS1 pin connected via 33 kΩ
to GND
IADS2
current on pin ADS2
ADS2 pin connected to GND
-
-
300
70
400
100
µA
µA
ADS2 pin connected via 33 kΩ
to GND
Diagnostic
VOL(DIAG)
LOW-level output
voltage on pin DIAG
fault condition; IDIAG = 1 mA
-
-
-
-
0.3
0.3
V
V
VOL(CLIP)
ILIH(CLIP)
ILIH(DIAG)
LOW-level output
voltage on pin CLIP
TH version only; clip or
temperature pre-warning
active; ICLIP = 1 mA
HIGH-level input
leakage current on pin pre-warning not activated
CLIP
diagnostic, clip or temperature
-
-
-
-
2
2
µA
µA
HIGH-level input
diagnostic, clip or temperature
leakage current on pin pre-warning not activated
DIAG
Vth(offset)
threshold voltage for
offset detection
1.0
1.5
7
2.0
V
[8]
[8]
THDCLIP7
THDCLIP3
Tj(AV)(warn1)
7 % clip detection
level (THD)
I2C-bus mode: IB2[D7] = 1
-
-
-
-
-
-
%
%
°C
3 % clip detection
level (THD)
I2C-bus mode: IB2[D7] = 0 and
non-I2C-bus mode
I2C-bus mode: IB3[D4] = 0 and
non-I2C-bus mode
3
average junction
temperature for
pre-warning 1
145
Tj(AV)(warn2)
average junction
temperature for
pre-warning 2
I2C-bus mode: IB3[D4] = 1
-
122
-
°C
TDA1566_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 20 August 2007
24 of 46
TDA1566
NXP Semiconductors
I2C-bus controlled dual channel/single channel amplifier
Table 23. Characteristics …continued
Refer to test circuit (see Figure 22); VP = 14.4 V; RL = 4 Ω; −40 °C < Tamb < +85 °C and −40 °C < Tj < +150 °C; unless
otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Tj(AV)(G(−0.5dB)) average junction
temperature for 0.5 dB
gain reduction
Vi = 0.05 V
-
155
-
°C
∆Tj(warn1-mute) difference in junction
temperature between
pre-warning 1 and
-
-
10
20
-
-
°C
°C
mute
∆Tj(G(−0.5-40dB)) difference in junction
temperature between
0.5 dB and 40 dB gain
reduction
Tj(AV)(off)
average junction
temperature for off
-
-
175
-
185
25
°C
Zth(load)
load detection
threshold impedance I2C-bus mode only:
amplifier DC load detection;
Ω
R
PROG = 1500 Ω/1 %
line driver DC load detection;
I2C-bus mode only:
120
5
-
-
-
-
500
Ω
R
PROG = 1500 Ω/1 %
[9]
open load DC load detection;
I2C-bus mode only:
-
kΩ
mA
mA
R
PROG = 1500 Ω/1 %
IoM
peak output current
AC load bit is set; I2C-bus
mode only:
320
-
-
R
PROG = 1500 Ω/1 %; Tj > 0 °C
AC load bit is not set; I2C-bus
mode only:
200
R
PROG = 1500 Ω/1 %; Tj > 0 °C
TDA1566_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 20 August 2007
25 of 46
TDA1566
NXP Semiconductors
I2C-bus controlled dual channel/single channel amplifier
Table 23. Characteristics …continued
Refer to test circuit (see Figure 22); VP = 14.4 V; RL = 4 Ω; −40 °C < Tamb < +85 °C and −40 °C < Tj < +150 °C; unless
otherwise specified.
Symbol
Amplifier
Po
Parameter
Conditions
Min
Typ
Max
Unit
output power
RL = 4 Ω; VP = 14.4 V;
THD = 0.5 %
-
23
24
29
45
-
-
-
-
W
W
W
W
RL = 4 Ω; VP = 14.4 V;
THD = 3 %
-
RL = 4 Ω; VP = 14.4 V;
THD = 10 %
24
40
RL = 4 Ω; VP = 14.4 V
maximum power; Vi = 2 V
(RMS) square wave
RL = 4 Ω; VP = 15.2 V
maximum power; Vi = 2 V
(RMS) square wave
45
50
-
W
RL = 2 Ω; VP = 14.4 V;
THD = 0.5 %
-
38
41
50
75
-
-
-
-
W
W
W
W
RL = 2 Ω; VP = 14.4 V;
THD = 3 %
-
RL = 2 Ω; VP = 14.4 V;
THD = 10 %
39
67
RL = 2 Ω; VP = 14.4 V
maximum power; Vi = 2 V
(RMS) square wave
RL = 1 Ω; VP = 14.4 V;
THD = 0.5 %
-
74
-
-
-
-
W
W
W
W
RL = 1 Ω; VP = 14.4 V;
THD = 3 %
-
81
RL = 1 Ω; VP = 14.4 V;
THD = 10 %
78
130
92
RL = 1 Ω; VP = 14.4 V
maximum power; Vi = 2 V
(RMS) square wave
150
THD
total harmonic
distortion
Po = 1 W to 12 W; f = 1 kHz;
RL = 4 Ω
-
-
-
-
0.005
0.01
0.02
0.1
0.1
0.2
%
%
%
%
Po = 1 W to 12 W; f = 1 kHz;
RL = 2 Ω
Po = 1 W to 12 W; f = 1 kHz;
RL = 1 Ω
Po = 1 W to 12 W; f = 10 kHz;
measured with 30 kHz filter;
RL = 4 Ω
0.3
0.6
0.1
Po = 1 W to 12 W; f = 10 kHz;
measured with 30 kHz filter;
RL = 2 Ω
-
-
0.2
%
%
line driver mode; Vo =1 V
(RMS) and 5 V (RMS);
f = 20 Hz to 20 kHz;
RL = 400 Ω
0.02
TDA1566_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 20 August 2007
26 of 46
TDA1566
NXP Semiconductors
I2C-bus controlled dual channel/single channel amplifier
Table 23. Characteristics …continued
Refer to test circuit (see Figure 22); VP = 14.4 V; RL = 4 Ω; −40 °C < Tamb < +85 °C and −40 °C < Tj < +150 °C; unless
otherwise specified.
Symbol
αcs
Parameter
Conditions
Min
42
Typ
55
Max
Unit
dB
channel separation
f = 1 kHz to 10 kHz; Rs = 2 kΩ
-
-
SVRR
supply voltage
rejection ratio
f = 100 Hz to 10 kHz;
Rs = 2 kΩ; Vripple = 2 V (p-p)
45
70
dB
CMRR
common-mode
rejection ratio
amplifier mode;
Vcm = 0.3 V (p-p); f = 1 kHz to
3 kHz; Rs = 2 kΩ
60
70
-
dB
Vcm(max)(rms)
maximum
common-mode
voltage (RMS value)
f = 1 kHz; Vi = 0.5 V (RMS);
amplifier mode
-
-
1
V
f = 1 kHz; Vi = 1.6 V (RMS);
line driver mode
-
-
0.6
50
70
50
27
17
-
V
Vn(o)(RMS)
RMS noise output
voltage
line driver mode; filter 20 Hz to
22 kHz; Rs = 2 kΩ
-
20
50
20
26
16
60
80
µV
µV
µV
dB
dB
kΩ
amplifier mode; filter 20 Hz to
22 kHz; Rs = 2 kΩ
-
mute mode; filter 20 Hz to
22 kHz; Rs = 2 kΩ
-
Gv(amp)
Gv(ld)
voltage gain amplifier (VOUT1+ − VOUT1−) /
mode (VIN1+ − VIN1−
25
15
44
)
voltage gain line driver (VOUT1+ − VOUT1−) /
mode
(VIN1+ − VIN1−)
[10]
[11]
Zi(sym)
symmetrical input
impedance
C = 470 nF
αmute
mute attenuation
power bandwidth
f = 1 kHz; Vi = 1 V (RMS)
-
-
-
-
dB
Hz
Bp
−1 dB; C = 2.2 µF
20 to
20000
[1] Operation above 16 V with a 2 Ω or 1 Ω mode with reactive load can trigger the amplifier protection. The amplifier switches off and will
restart after 8 ms resulting in an ‘audio hole’.
[2] If the EN pin is connected with VP a series resistance of 10 kΩ is necessary for load dump robustness.
[3] If the EN pin is left unconnected the amplifier will be switched off.
[4] The mute release is initiated when the SVR voltage increases above 3.5 V typical. Mute release is defined as the moment when the
output signal has reached 10 % of the expected amplitude.
[5] Mute release is defined as the moment when the output signal has reached 10 % of the expected amplitude (Gv × Vi). Full gain is
defined as the moment when the output signal has reached 90 % of the expected amplitude (Gv × Vi).
[6] Standard I2C-bus spec: maximum LOW level = 0.3 × VDD, minimum HIGH level = 0.7 × VDD. To comply with 5 V and 3.3 V logic the
maximum LOW level is defined with VDD = 5 V and the minimum HIGH level with VDD = 3.3 V.
[7] If the 1 Ω pin is connected with VP a series resistance of 10 kΩ is necessary for load dump robustness.
[8] Clip detect is not operational for VP < 10 V.
[9] If an open load is detected the amplifier is switched in line driver mode.
[10] Rs is the total differential source resistance. −3 dB cut-off frequency is given as
1
1
=
= 19 Hz assuming worst case low input resistance and 20 % spread in Ci.
-----------------------------
2π × Ri × Ci
------------------------------------------------------------------
2π × 22 kΩ × 470 nF × 0.8
[11] Power bandwidth can be limited by the −3 dB cut-off frequency, see Table note 10.
TDA1566_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 20 August 2007
27 of 46
TDA1566
NXP Semiconductors
I2C-bus controlled dual channel/single channel amplifier
9.1 Performance diagrams
All graphs Tamb = 25 °C.
001aad019
001aad020
2
10
10
THD
(%)
THD
(%)
10
1
1
−1
10
−1
10
(1)
−2
10
−2
10
10
(1)
(2)
(2)
(3)
−3
−3
10
−1
2
2
3
4
5
10
1
10
10
10
10
10
10
10
P
(W)
f (Hz)
o
RL = 4 Ω; 80 kHz measurement filter.
RL = 4 Ω; 80 kHz measurement filter.
(1) Po = 1 W.
(1) f = 10 kHz.
(2) f = 1 kHz.
(3) f = 100 Hz.
(2) Po = 10 W.
Fig 12. THD as a function of output power
Fig 13. THD as a function of frequency
001aad021
001aad022
10
THD
0
SVRR
(dB)
(%)
operating
1
−20
−40
−1
10
10
10
10
−2
−3
−4
−60
−80
−100
−1
2
2
3
4
5
10
1
10
10
10
10
10
10
10
V
(V)
f (Hz)
o(rms)
RL = 100 Ω; 80 kHz measurement filter; f = 1 kHz.
Rs = 1 kΩ; CSVR = 10 µF.
Fig 14. THD as a function of output voltage in line
driver mode
Fig 15. SVRR as a function of frequency (operating)
TDA1566_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 20 August 2007
28 of 46
TDA1566
NXP Semiconductors
I2C-bus controlled dual channel/single channel amplifier
001aad023
001aad024
0
−50
α
(dB)
cs
SVRR
(dB)
mute
(1), (2)
(3)
−20
−60
−40
−60
−70
−80
(3)
(1) (2)
−80
−90
−100
−100
2
3
4
5
2
3
4
5
10
10
10
10
10
10
10
10
10
10
f (Hz)
f (Hz)
Rs = 1 kΩ; CSVR = 10 µF.
(1) Rs = 0 Ω.
(2) Rs = 1 kΩ.
(3) Rs = 10 kΩ.
Fig 16. SVRR as a function of frequency (mute)
Fig 17. Channel separation as a function of frequency
TDA1566_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 20 August 2007
29 of 46
TDA1566
NXP Semiconductors
I2C-bus controlled dual channel/single channel amplifier
9.2 PCB layout
S G + S
C n 5 D
L d V A
2
external
I C supply
I C/gain in legacy
2
2
Vp
supply
16 dB/I C load
detection
top
GND
+Vp
external
supply
26 dB
1.5 kΩ
1 %
10 µF
inputs
gnd
in
TDA3664
+
+
−
1
1 µF
prog
monitor
IN2
+
+
diagnostic
LED
470 nF
470 nF
2200 µF
2−
2+
1−
−
R
Rs
Zobel
+
22
Sgnd
µF
470 nF
470 nF
SVR
Zobel
+
1+
33 kΩ
temperature/clip
LED
output
Vp
−
R
IN1
2
legacy/I C
ADS1 ADS2
3.6 V
10 kΩ 1.5 kΩ
GND
sense
enable
Jp
2
D0
D2
D4
I C
device
off
device
operating
device
mute
legacy input
unbalanced
legacy mode control
legacy input
balanced
D6
TDA1566TH stereo
NXP Semiconductors
SRK ver. 1e
mode
select
address
select
001aad688
Fig 18. PCB layout TDA1566TH, components top
TDA1566_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 20 August 2007
30 of 46
TDA1566
NXP Semiconductors
I2C-bus controlled dual channel/single channel amplifier
top
1
24
13
12
001aad696
Fig 19. PCB layout TDA1566TH, components bottom
TDA1566_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 20 August 2007
31 of 46
TDA1566
NXP Semiconductors
I2C-bus controlled dual channel/single channel amplifier
2
ADS1
R2
SDA SCL
GND +5VA GND EXT-I C
1
X2
S2
S7
OUT2+
J1
C9
C6
C10
+
+
OUT2−
1
OUT1+
VP
OUT1−
J8
J9
1
1
APPL-BOARD-TDA1566J-DB527
7322-448-07651
C11
IN1+
IN1+DC
1
C12
IN1−
IN1−DC
X1
SGND
C13
IN2+
IN2+DC
C14
IN2−
IN2−DC
C7
C15
VP
S4
S1
R9
R1
S6
S5
V1
J7
1
GND
EN
SVR DIAG/CLIP GND PROG
1E
001aad689
Fig 20. PCB layout TDA1566J, components top
TDA1566_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 20 August 2007
32 of 46
TDA1566
NXP Semiconductors
I2C-bus controlled dual channel/single channel amplifier
A1
R6
C8
C5
R8
R4
R7
001aad708
Fig 21. PCB layout TDA1566J, components bottom
TDA1566_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 20 August 2007
33 of 46
TDA1566
NXP Semiconductors
I2C-bus controlled dual channel/single channel amplifier
10. Test information
+5 V
(4)
2200
µF
220
nF
(1)
10 kΩ
V
V
P2
ADS2
8
ADS1
9
SDA
6
SCL
5
P1
14
23
V
22 PROG
(2)
P
10 kΩ
13 CLIP
(3)
EN
7
STAND-BY
/MUTE
SELECT DIAGNOSTIC
/CLIP DETECT
2
I C-BUS
1
DIAG
0.5R
470 nF
C
s
16
OUT1+
IN1+ 10
MUTE
MUTE
MUTE
MUTE
26 dB/
R
L
16 dB
0.5V
0.5V
18 OUT1−
in
PROTECTION
/DIAGNOSTIC
in
470 nF
C
IN1− 11
0.5R
s
0.5R
0.5V
470 nF
C
s
19
21
OUT2+
IN2+
2
3
26 dB/
16 dB
R
L
OUT2−
in
0.5V
PROTECTION
/DIAGNOSTIC
in
470 nF
C
V
P
IN2−
0.5R
s
V
cm
TDA1566TH
4
12
17
20
24
15
1OHM
SVR
22 µF
SGND
PGND1
PGND2
TAB
001aad015
(1) The 220 nF capacitor should be placed close to the VP and PGND pins of the IC.
(2) In non-I2C-bus mode the PROG pin should be left unconnected for 26 dB gain selection or connected via a resistor of
1500 Ω to GND for 16 dB gain selection.
(3) CLIP is not available in the DBS27P version.
(4) In non-I2C-bus mode (ADS1 pin connected to GND) and balanced input source (ADS2 pin connected to GND) selected.
ADS2 is not available in DBS27P version.
Fig 22. Non-I2C-bus mode (26 dB gain)
TDA1566_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 20 August 2007
34 of 46
TDA1566
NXP Semiconductors
I2C-bus controlled dual channel/single channel amplifier
2200
µF
220
nF
(1)
connected to
microcontroller
+5 V
(4)
V
P
V
V
P2
ADS2
8
ADS1
9
SDA
6
SCL
5
P1
10 kΩ
14
23
22 PROG
(2)
R
PROG
1500 Ω
(1 %)
13 CLIP
(3)
EN
7
STAND-BY
/MUTE
SELECT DIAGNOSTIC
/CLIP DETECT
connected to
microcontroller
2
I C-BUS
1
DIAG
0.5R
470 nF
C
s
16
OUT1+
IN1+ 10
MUTE
MUTE
MUTE
MUTE
26 dB/
R
L
16 dB
0.5V
0.5V
18 OUT1−
in
PROTECTION
/DIAGNOSTIC
in
470 nF
C
IN1− 11
0.5R
s
0.5R
0.5V
470 nF
C
s
19
21
OUT2+
IN2+
2
3
26 dB/
16 dB
R
L
OUT2−
in
0.5V
PROTECTION
/DIAGNOSTIC
in
470 nF
C
V
P
IN2−
0.5R
s
V
cm
TDA1566TH
4
12
17
20
24
15
1OHM
SVR
22 µF
SGND
PGND1
PGND2
TAB
001aad016
(1) The 220 nF capacitor should be placed close to the VP and PGND pins of the IC.
(2) RPROG defines the trip levels for the AC and DC load detection.
(3) CLIP is not available in DBS27P version.
(4) I2C-bus mode is selected with ADS1 open. ADS2 is not available in DBS27P version.
Fig 23. I2C-bus mode
TDA1566_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 20 August 2007
35 of 46
TDA1566
NXP Semiconductors
I2C-bus controlled dual channel/single channel amplifier
+5 V
(4)
2200
µF
220
nF
(1)
10 kΩ
V
V
P2
ADS2
8
ADS1
9
SDA
6
SCL
5
P1
14
23
V
22 PROG
(2)
P
10 kΩ
13 CLIP
(3)
EN
7
STAND-BY
/MUTE
SELECT DIAGNOSTIC
/CLIP DETECT
2
I C-BUS
1
DIAG
0.5R
470 nF
C
s
16
OUT1+
IN1+ 10
MUTE
MUTE
MUTE
MUTE
26 dB/
16 dB
0.5V
0.5V
18 OUT1−
in
R
L
PROTECTION
/DIAGNOSTIC
in
470 nF
C
1 Ω
IN1− 11
0.5R
s
470 nF
C
19
21
OUT2+
IN2+
2
3
26 dB/
16 dB
OUT2−
PROTECTION
/DIAGNOSTIC
470 nF
C
V
P
IN2−
V
cm
TDA1566TH
4
12
17
20
24
15
SVR
22 µF
SGND
PGND1
PGND2
TAB
1OHM
001aad017
10 kΩ
connected to V
P
(1) The 220 nF capacitor should be placed close to the VP and PGND pins of the IC.
(2) In non-I2C-bus mode the PROG pin should be left unconnected for 26 dB gain selection or connected via a resistor of
1500 Ω to GND for 16 dB gain selection.
(3) CLIP is not available in the DBS27P version.
(4) In non-I2C-bus mode (ADS1 pin connected to GND) and balanced input source (ADS2 pin connected to GND) selected.
ADS2 is not available in DBS27P version.
Fig 24. Non-I2C-bus mode (1 Ω mode and 26 dB gain)
TDA1566_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 20 August 2007
36 of 46
TDA1566
NXP Semiconductors
I2C-bus controlled dual channel/single channel amplifier
2200
µF
220
nF
(1)
connected to
microcontroller
+5 V
(4)
V
P
V
V
P2
ADS2
8
ADS1
9
SDA
6
SCL
5
P1
10 kΩ
14
23
22 PROG
(2)
R
PROG
1500 Ω
(1 %)
13 CLIP
(3)
EN
7
STAND-BY
/MUTE
SELECT DIAGNOSTIC
/CLIP DETECT
connected to
microcontroller
2
I C-BUS
1
DIAG
0.5R
470 nF
C
s
16
OUT1+
IN1+ 10
MUTE
MUTE
MUTE
MUTE
26 dB/
16 dB
0.5V
0.5V
18 OUT1−
in
R
L
PROTECTION
/DIAGNOSTIC
in
470 nF
C
1 Ω
IN1− 11
0.5R
s
470 nF
C
19
21
OUT2+
IN2+
2
3
26 dB/
16 dB
OUT2−
PROTECTION
/DIAGNOSTIC
470 nF
C
V
P
IN2−
V
cm
TDA1566TH
4
12
17
20
24
15
SVR
22 µF
SGND
PGND1
PGND2
TAB
1OHM
001aad018
10 kΩ
connected to V
P
(1) The 220 nF capacitor should be placed close to the VP and PGND pins of the IC.
(2) RPROG defines the trip levels for the AC and DC load detection.
(3) CLIP is not available in the DBS27P version.
(4) I2C-bus mode is selected with ADS1 open. ADS2 is not available in DBS27P version.
Fig 25. I2C-bus mode (1 Ω mode)
TDA1566_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 20 August 2007
37 of 46
TDA1566
NXP Semiconductors
I2C-bus controlled dual channel/single channel amplifier
11. Package outline
HSOP24: plastic, heatsink small outline package; 24 leads; low stand-off height
SOT566-3
E
A
D
x
X
c
y
E
H
2
v
M
A
E
D
1
D
2
12
1
pin 1 index
Q
A
A
2
(A )
3
E
1
A
4
θ
L
p
detail X
24
13
w
M
Z
b
p
e
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
max.
(1)
(2)
(2)
A
A
A
b
c
D
D
D
E
E
1
E
e
H
E
L
p
Q
v
w
x
y
Z
θ
UNIT
2
3
4
p
1
2
2
8°
0°
+0.08 0.53 0.32
−0.04 0.40 0.23
16.0 13.0 1.1 11.1 6.2
15.8 12.6 0.9 10.9 5.8
2.9
2.5
14.5 1.1
13.9 0.8
1.7
1.5
2.7
2.2
3.5
3.2
mm
1
3.5
0.35
0.25 0.25 0.03 0.07
Notes
1. Limits per individual lead.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
03-02-18
03-07-23
SOT566-3
Fig 26. Package outline SOT566-3 (HSOP24)
TDA1566_2
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Product data sheet
Rev. 02 — 20 August 2007
38 of 46
TDA1566
NXP Semiconductors
I2C-bus controlled dual channel/single channel amplifier
DBS27P: plastic DIL-bent-SIL (special bent) power package; 27 leads (lead length 6.8 mm)
SOT827-1
non-concave
D
h
x
D
E
h
view B: mounting base side
A
2
d
B
j
E
A
L
4
L
3
L
L
2
1
27
e
w
M
Z
1
c
v
M
Q
b
p
e
e
2
m
0
10
scale
20 mm
DIMENSIONS (mm are the original dimensions)
(1)
(1)
(1)
UNIT
A
A
b
c
D
d
D
E
e
e
e
E
j
L
L
L
L
4
m
Q
v
w
x
Z
2
p
h
1
2
h
2
3
4.65 0.60 0.5 29.2 25.8
4.35 0.45 0.3 28.8 25.4
15.9
15.5
3.4
3.1
3.9 1.15 22.9
3.1 0.85 22.1
1.8
1.2
2.1
1.8
8
6.8
mm
12
2
1
4
19
4
0.6 0.25 0.03
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
03-07-29
SOT827-1
- - -
- - -
- - -
Fig 27. Package outline SOT827-1 (DBS27P)
TDA1566_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 20 August 2007
39 of 46
TDA1566
NXP Semiconductors
I2C-bus controlled dual channel/single channel amplifier
12. Handling information
Inputs and outputs are protected against electrostatic discharge in normal handling.
However, to be completely safe you must take normal precautions appropriate to handling
integrated circuits.
13. Soldering
13.1 Introduction
There is no soldering method that is ideal for all surface mount IC packages. Wave
soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is recommended.
13.2 Through-hole mount packages
13.2.1 Soldering by dipping or by solder wave
Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C
or 265 °C, depending on solder material applied, SnPb or Pb-free respectively.
The total contact time of successive solder waves must not exceed 5 seconds.
The device may be mounted up to the seating plane, but the temperature of the plastic
body must not exceed the specified maximum storage temperature (Tstg(max)). If the
printed-circuit board has been pre-heated, forced cooling may be necessary immediately
after soldering to keep the temperature within the permissible limit.
13.2.2 Manual soldering
Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the
seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is
less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is
between 300 °C and 400 °C, contact may be up to 5 seconds.
13.3 Surface mount packages
13.3.1 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 28) than a PbSn process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
TDA1566_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 20 August 2007
40 of 46
TDA1566
NXP Semiconductors
I2C-bus controlled dual channel/single channel amplifier
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 24 and 25
Table 24. SnPb eutectic process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
≥ 350
220
< 2.5
235
220
≥ 2.5
220
Table 25. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 28.
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 28. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
TDA1566_2
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Product data sheet
Rev. 02 — 20 August 2007
41 of 46
TDA1566
NXP Semiconductors
I2C-bus controlled dual channel/single channel amplifier
13.3.2 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices
(SMDs) or printed-circuit boards with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering method was specifically
developed.
If wave soldering is used the following conditions must be observed for optimal results:
• Use a double-wave soldering method comprising a turbulent wave with high upward
pressure followed by a smooth laminar wave.
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be
parallel to the transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the
transport direction of the printed-circuit board.
The footprint must incorporate solder thieves at the downstream end.
• For packages with leads on four sides, the footprint must be placed at a 45° angle to
the transport direction of the printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement and before soldering, the package must be fixed with a droplet of
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the adhesive is cured.
Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C
or 265 °C, depending on solder material applied, SnPb or Pb-free respectively.
A mildly-activated flux will eliminate the need for removal of corrosive residues in most
applications.
13.3.3 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage
(24 V or less) soldering iron applied to the flat part of the lead. Contact time must be
limited to 10 seconds at up to 300 °C.
When using a dedicated tool, all other leads can be soldered in one operation within
2 seconds to 5 seconds between 270 °C and 320 °C.
13.4 Package related soldering information
Table 26. Suitability of IC packages for wave, reflow and dipping soldering methods
Mounting
Package[1]
Soldering method
Wave
Reflow[2]
Dipping
Through-hole mount
CPGA, HCPGA
suitable
−
−
DBS, DIP, HDIP, RDBS, SDIP, SIL suitable[3]
−
suitable
Through-hole-surface
mount
PMFP[4]
not suitable
not suitable
−
TDA1566_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 20 August 2007
42 of 46
TDA1566
NXP Semiconductors
I2C-bus controlled dual channel/single channel amplifier
Table 26. Suitability of IC packages for wave, reflow and dipping soldering methods …continued
Mounting
Package[1]
Soldering method
Wave
Reflow[2]
Dipping
Surface mount
BGA, HTSSON..T[5], LBGA,
LFBGA, SQFP, SSOP..T[5], TFBGA,
VFBGA, XSON
not suitable
suitable
−
DHVQFN, HBCC, HBGA, HLQFP, not suitable[6]
HSO, HSOP, HSQFP, HSSON,
HTQFP, HTSSOP, HVQFN,
suitable
−
HVSON, SMS
PLCC[7], SO, SOJ
suitable
suitable
−
−
−
−
LQFP, QFP, TQFP
not recommended[7][8]
not recommended[9]
not suitable
suitable
SSOP, TSSOP, VSO, VSSOP
CWQCCN..L[10], WQCCN..L[10]
suitable
not suitable
[1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your NXP
Semiconductors sales office.
[2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with
respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of
the moisture in them (the so called popcorn effect).
[3] For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.
[4] Hot bar soldering or manual soldering is suitable for PMFP packages.
[5] These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed
through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 °C ± 10 °C
measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible.
[6] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate
between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the
heatsink surface.
[7] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint
must incorporate solder thieves downstream and at the side corners.
[8] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for
packages with a pitch (e) equal to or smaller than 0.65 mm.
[9] Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely
not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
[10] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil.
However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate
soldering profile can be provided on request.
TDA1566_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 20 August 2007
43 of 46
TDA1566
NXP Semiconductors
I2C-bus controlled dual channel/single channel amplifier
14. Revision history
Table 27. Revision history
Document ID
TDA1566_2
Release date
20070820
Data sheet status
Change notice
Supersedes
Product data sheet
-
TDA1566_1
Modifications:
• The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Table 23 “Characteristics” changed values for CMRR, Po and THD
TDA1566_1
20060405
Product data sheet
-
-
(9397 750 15043)
TDA1566_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 20 August 2007
44 of 46
TDA1566
NXP Semiconductors
I2C-bus controlled dual channel/single channel amplifier
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
result in personal injury, death or severe property or environmental damage.
15.2 Definitions
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a NXP Semiconductors product can reasonably be expected to
I2C-bus — logo is a trademark of NXP B.V.
16. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
TDA1566_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 20 August 2007
45 of 46
TDA1566
NXP Semiconductors
I2C-bus controlled dual channel/single channel amplifier
17. Contents
1
2
3
4
General description . . . . . . . . . . . . . . . . . . . . . . 1
13.2.2
13.3
13.3.1
13.3.2
13.3.3
13.4
Manual soldering . . . . . . . . . . . . . . . . . . . . . . 40
Surface mount packages . . . . . . . . . . . . . . . . 40
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 40
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 42
Manual soldering . . . . . . . . . . . . . . . . . . . . . . 42
Package related soldering information. . . . . . 42
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
14
Revision history . . . . . . . . . . . . . . . . . . . . . . . 44
15
Legal information . . . . . . . . . . . . . . . . . . . . . . 45
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 45
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6
6.1
Functional description . . . . . . . . . . . . . . . . . . . 7
General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . 7
Gain selection. . . . . . . . . . . . . . . . . . . . . . . . . . 8
I2C-bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Non-I2C-bus mode . . . . . . . . . . . . . . . . . . . . . . 8
Balanced and unbalanced input sources . . . . . 9
Single channel 1 W operation. . . . . . . . . . . . . . 9
Mute speed setting . . . . . . . . . . . . . . . . . . . . . 10
Pins with double functions . . . . . . . . . . . . . . . 10
Load identification (I2C-bus mode only) . . . . . 10
DC load detection . . . . . . . . . . . . . . . . . . . . . . 10
AC load detection . . . . . . . . . . . . . . . . . . . . . . 11
Diagnostic. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Diagnostic table . . . . . . . . . . . . . . . . . . . . . . . 12
Diagnostic level settings . . . . . . . . . . . . . . . . . 13
Temperature pre-warning . . . . . . . . . . . . . . . . 13
Speaker protection . . . . . . . . . . . . . . . . . . . . . 14
Offset detection. . . . . . . . . . . . . . . . . . . . . . . . 14
I2C-bus operation . . . . . . . . . . . . . . . . . . . . . . 15
I2C-bus address with hardware address select 15
Instruction bytes . . . . . . . . . . . . . . . . . . . . . . . 16
Data bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Timing waveforms. . . . . . . . . . . . . . . . . . . . . . 17
Start-up and shutdown . . . . . . . . . . . . . . . . . . 17
Engine start . . . . . . . . . . . . . . . . . . . . . . . . . . 19
15.1
15.2
15.3
15.4
6.1.1
6.1.2
6.1.2.1
6.1.2.2
6.1.3
6.1.4
6.1.5
6.1.6
6.2
6.2.1
6.2.2
6.3
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.4
16
17
Contact information . . . . . . . . . . . . . . . . . . . . 45
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.4.1
6.4.2
6.4.3
6.5
6.5.1
6.5.2
7
8
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 19
Thermal characteristics. . . . . . . . . . . . . . . . . . 21
9
9.1
9.2
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 21
Performance diagrams . . . . . . . . . . . . . . . . . . 28
PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
10
11
12
Test information. . . . . . . . . . . . . . . . . . . . . . . . 34
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 38
Handling information. . . . . . . . . . . . . . . . . . . . 40
13
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Through-hole mount packages. . . . . . . . . . . . 40
Soldering by dipping or by solder wave . . . . . 40
13.1
13.2
13.2.1
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 20 August 2007
Document identifier: TDA1566_2
相关型号：
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