TDA19989AET/C101,5_技术文档

TDA19989AET

150 MHz pixel rate HDMI 1.4 transmitter with 3 × 8-bit video

inputs, HDCP and CEC support

Rev. 02 — 18 May 2010

Product data sheet

1. General description

TDA19989AET is a very low power and very small size High-Definition Multimedia

Interface (HDMI) v. 1.4 transmitter. It is backward compatible DVI 1.0 and can be

connected to any DVI 1.0 and HDMI sink.

This device is primarily intended for mobile applications like Digital Video Camera (DVC),

Digital Still Camera (DSC), Portable Multimedia Player (PMP), Mobile Phone and

Ultra-Mobile Personal Computer (UM PC) where size and very low power are mandatory

for battery autonomy.

It allows mixing 3 × 8-bit RGB or YCbCr video stream with a pixel rate up to 150 MHz

together with one S/PDIF or two I²S-bus audio streams with an audio sampling rate up to

192 kHz.

In order to be compatible with most applications, TDA19989AET integrates a full

programmable input formatter and color space conversion block. The video input formats

accepted are YCbCr 4 :4 : 4 (up to 3 × 8-bit), YCbCr 4 : 2 : 2 semi-planar (up to 2 × 12-bit)

and YCbCr 4 : 2 : 2 compliant with ITU656 (up to 1 × 12-bit). In case of ITU656-like

format, the input pixel clock can be made active on one (SDR mode) or both edges (DDR

mode).

TDA19989AET includes a HDCP 1.3 compliant cipher block. The HDCP keys are stored

internally in a non-volatile OTP memory for maximum security.

This device provides additional embedded feature like CEC (Consumer Electronic

Control). CEC is a single bidirectional wire that transmits CEC commands (like Standby

from remote control) over the home appliance network connected through this wire. This

eliminates the need of any additional device to handle this feature thus improving BOM

(Bill Of Materials) of the whole system and enabling the connected devices (CEC

enabled) to be controlled by only one remote control.

TDA19989AET supports xvYCC HDMI 1.4 feature.

It can be switched to very low power Standby or Sleep modes to save power when HDMI

is not used.

TDA19989AET includes I²C-bus master interface for DDC-bus communication for EDID

reading and HDCP purpose.

This device can be controlled or configured via I²C-bus interface.

TDA19989AET

NXP Semiconductors

HDMI 1.4 transmitter with HDCP and CEC support

PLL

SERIALIZER

PIXEL, REPETITION

2

I C-BUS

CEC

SLAVE

2

I S-bus

HDMI

ENCODER

SERIALIZER

HMDI

TMDS

link

HDCP

1.3 cipher

AUDIO

video

S/PDIF

RGB

COLOR

SPACE

CONVERTER

INPUT

FORMATTER

2

I C-BUS

YCbCr

MASTER DDC-BUS

001aal264

Fig 1. TDA19989AET high-level block diagram

2. Features and benefits

Compliance:

DVI 1.0

HDMI 1.4

EIA/CEA-861B

CEC (HDMI 1.4)

SimplayHD

HDCP 1.3

Video:

xvYCC HDMI 1.4 feature

Video formats with a pixel rate up to 150 MHz:

RGB 4 : 4 : 4

YCbCr 4 : 4 : 4

YCbCr 4 : 2 : 2 semi-planar

YCbCr 4 : 2 : 2 ITU656

Maximum resolution:

1080p for TV

1600 × 1200 at 60 Hz for PC (UXGA60)

720p/1080i in ITU656

Programmable color space converter:

RGB to YCbCr

YCbCr to RGB

Programmable input formatter and upsampler/interpolator allows input of any of the

4 : 4 : 4, 4 : 2 : 2 semi-planar, 4 : 2 : 2 ITU656-like formats

Horizontal synchronization, vertical synchronization and Data Enable (DE) inputs

or VREF, HREF and FREF could be used for input data synchronization

Pixel clock input can be made active on one or both edges (selectable by I²C-bus)

Repetition of video samples as required by HDMI specification

Audio:

2 × I²S-bus 2 channels or one S/PDIF; audio data rate up to 192 kHz

Deals with multiple levels of HDCP receivers and repeaters

Internal SHA-1 calculation

TDA19989AET_2

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Product data sheet

Rev. 02 — 18 May 2010

2 of 46

TDA19989AET

NXP Semiconductors

HDMI 1.4 transmitter with HDCP and CEC support

System operation:

Master DDC-bus interface for EDID read

Controllable via I²C-bus

Downstream availability through the use of hot plug detect (HPD) and receiver

detection (RxSense)

Package:

TFBGA64

Size 4.5 × 4.5 × 0.95 mm

Power management:

External voltage supplies 1.8 V

Low power

Flexible power modes

Miscellaneous:

POR (Power-On Reset)

Audio and video inputs LV-CMOS 1.8 V compatible and LV-CMOS 3.3 V tolerant

250 MHz to 1.5 GHz TMDS transmitter operation

3. Applications

Digital Video Camera (DVC)

Digital Still Camera (DSC)

Portable Multimedia Player (PMP)

Mobile Phone

Ultra-Mobile Personal Computer (UM PC)

4. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

TDA19989AET TFBGA64

plastic thin fine-pitch ball grid array package; 64 balls SOT962-3

TDA19989AET_2

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Product data sheet

Rev. 02 — 18 May 2010

3 of 46

TDA19989AET

NXP Semiconductors

HDMI 1.4 transmitter with HDCP and CEC support

6. Pinning information

6.1 Pinning

TDA19989

ball A1

index area

1

2

3

4

5

6

7

8

A

B

C

D

E

F

G

H

001aal266

Transparent top view

Fig 3. Pin configuration (TFBGA64)

6.2 Pin description

Table 2.

Symbol

Pin description

H5

G5

F5

Type^[1]Description

ACLK

AP0

I

audio clock input

audio port 0 input

audio port 1 input

audio port 2 input

AP1

AP2

G6

H6

OSC_IN/AP3

input connected to the external oscillator circuit or external

clock source/audio port 3 input

HPD

E6

E7

I

hot plug detect; 5 V tolerant

EXT_SWING

O

TMDS output swing adjustment; place resistor

(R_{EXT_SWING}= 10 kΩ ± 1 %) between this pin and analog

ground.

DSDA

DSCL

VCLK

F6

F7

D4

I/O

DDC-bus data input/output; 5 V tolerant

DDC-bus clock input; 5 V tolerant

I

input video pixel clock

HSYNC/HREF F4

VSYNC/VREF G4

I

input horizontal synchronization or reference input

input vertical synchronization or reference input

data enable or field reference input

I²C-bus clock input; 1.8 V to 3.3 V tolerant

I²C-bus data input/output; 1.8 V to 3.3 V tolerant

I

DE/FREF

CSCL

CSDA

INT

H4

B5

A5

B6

I

I/O

interrupt HDMI output (open-drain); this pin is used as Dual

function pin selectable through I²C-bus. In calibration mode

only this pin is used as input for 10 ms ± 1 % calibration pulse.

In operation mode this pin is used to warn the external

microprocessor that a special event has occurred for HDMI or

CEC

TDA19989AET_2

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Product data sheet

Rev. 02 — 18 May 2010

5 of 46

TDA19989AET

NXP Semiconductors

HDMI 1.4 transmitter with HDCP and CEC support

Table 2.

Pin description …continued

Type^[1]Description

Symbol

TX0−

E8

D8

C8

B8

A7

A6

G8

F8

H7

C1

B1

B2

A2

B3

A3

B4

A4

E3

E2

E1

D1

D2

D3

C2

C3

H3

H2

G3

G2

G1

F1

F2

F3

O

I/O

I

negative data channel 0 for TMDS output

positive data channel 0 for TMDS output

negative data channel 1 for TMDS output

positive data channel 1 for TMDS output

negative data channel 2 for TMDS output

positive data channel 2 for TMDS output

negative clock channel for TMDS output

positive clock channel for TMDS output

CEC connection (open-drain) to HDMI connector

video port A input bit 0 (LSB)

video port A input bit 1

TX0+

TX1−

TX1+

TX2−

TX2+

TXC−

TXC+

CEC

VPA[0]

VPA[1]

VPA[2]

VPA[3]

VPA[4]

VPA[5]

VPA[6]

VPA[7]

VPB[0]

VPB[1]

VPB[2]

VPB[3]

VPB[4]

VPB[5]

VPB[6]

VPB[7]

VPC[0]

VPC[1]

VPC[2]

VPC[3]

VPC[4]

VPC[5]

VPC[6]

VPC[7]

I

video port A input bit 2

I

video port A input bit 3

I

video port A input bit 4

I

video port A input bit 5

I

video port A input bit 6

I

video port A input bit 7 (MSB)

video port B input bit 0 (LSB)

video port B input bit 1

I

video port B input bit 2

I

video port B input bit 3

I

video port B input bit 4

I

video port B input bit 5

I

video port B input bit 6

I

video port B input bit 7 (MSB)

video port C input bit 0 (LSB)

video port C input bit 1

I

video port C input bit 2

I

video port C input bit 3

I

video port C input bit 4

I

video port C input bit 5

I

video port C input bit 6

I

video port C input bit 7 (MSB)

TMDS analog supply voltage (1.8 V)

I/O digital supply voltage (1.8 V)

V_{DDA(TMDS)(1V8)}A8, C7

P

V_DDD(IO)(1V8)

V_{DDA(PLL)(1V8)}

E4

C6

PLL analog supply voltage (1.8 V), this PLL provides the clock

for the serializer

V_DDA(1V8)

G7, H8

P

analog supply voltage (1.8 V), is used for parallel-to-serial

shift register and miscellaneous blocks

V_DDDC

E5

D5

P

core digital supply voltage (1.8 V)

TDA19989AET_2

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Product data sheet

Rev. 02 — 18 May 2010

6 of 46

TDA19989AET

NXP Semiconductors

HDMI 1.4 transmitter with HDCP and CEC support

Table 2.

Pin description …continued

Symbol

Type^[1]Description

V_SSD

B7,

G

digital ground supply voltage, is used for digital core; I/O

C4,

C5, H1

V_SSA

n.c.

D6, D7

A1

G

analog ground supply voltage, is used for PLL; serializer,

transmitter, and parallel-to-serial shift register

not connected

[1] P = power supply, G = ground, I = input, O = output.

7. Functional description

TDA19989AET is designed to convert digital data (video and audio) provided by Set-Top

Boxes (STB), Digital Video Camera (DVC), Digital Still Camera (DSC), Portable

Multimedia Player (PMP) or DVD into an HDMI output, which can be used by a TV with

either an HDMI or DVI input.

The video data input formats are:

• RGB 4 : 4 : 4

• YCbCr 4 : 4 : 4

• YCbCr 4 : 2 : 2 semi-planar

• YCbCr 4 : 2 : 2 ITU656-like

TDA19989AET is able to output HDMI with the formats:

• RGB 4 : 4 : 4

• YCbCr 4 : 4 : 4

• YCbCr 4 : 2 : 2

It can also handle audio formats:

• two I²S-bus channels

• one S/PDIF channel

TDA19989AET is also designed to support CEC protocol. For more details about CEC,

refer to HDMI 1.4 specification.

7.1 System clock

The system clock section has a PLL serializer.

It is a system clock generator which enables the stream produced by the encoder to be

transmitted on the HDMI data channel at ten times, or above, the sampling rate.

TDA19989AET_2

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Product data sheet

Rev. 02 — 18 May 2010

7 of 46

TDA19989AET

NXP Semiconductors

HDMI 1.4 transmitter with HDCP and CEC support

7.2 Video input formatter

7.2.1 Description

TDA19989AET has three video input ports VPA[0] to VPA[7], VPB[0] to VPB[7] and

VPC[0] to VPC[7].

TDA19989AET can accept any of the following video input modes (see Table 6):

• RGB, with 8-bit for each component

• YCbCr 4 : 4 : 4, with 8-bit for each component

• YCbCr 4 : 2 : 2 semi-planar, with up to 12-bit for each component (YCbCr)

• YCbCr 4 : 2 : 2 ITU656, with up to 12-bit data depth

TDA19989AET can be set to latch data at either rising or falling edge, or both.

7.2.2 Internal assignment

The aim of the video input processor is to internally map the incoming data to the

corresponding mode, which can be handled by the video processing. The internal signal

named VP[23:0] is assigned depending on the input mode as defined below.

VPA[0] to VPA[7]

VIDEO

VPB[0] to VPB[7]

VP[23:0]

INPUT

PROCESSOR

VPC[0] to VPC[7]

001aah028

Fig 4. Internal assignment of VP[23:0]

Table 3.

Internal assignment

Internal port

RGB

YCbCr 4 : 4 : 4

YCbCr 4 : 2 : 2

semi-planar

YCbCr 4 : 2 : 2

ITU656

VP[23]

VP[22]

VP[21]

VP[20]

VP[19]

VP[18]

VP[17]

VP[16]

VP[15]

VP[14]

VP[13]

VP[12]

G[7]

G[6]

G[5]

G[4]

G[3]

G[2]

G[1]

G[0]

B[7]

B[6]

B[5]

B[4]

Y[7]

Y[11]

Y[10]

Y[9]

Y[8]

Y[7]

Y[6]

Y[5]

Y[4]

Y[3]

Y[2]

Y[1]

Y[0]

YCbCr[11]

YCbCr[10]

YCbCr[9]

YCbCr[8]

YCbCr[7]

YCbCr[6]

YCbCr[5]

YCbCr[4]

YCbCr[3]

YCbCr[2]

YCbCr[1]

YCbCr[0]

Y[6]

Y[5]

Y[4]

Y[3]

Y[2]

Y[1]

Y[0]

Cb[7]

Cb[6]

Cb[5]

Cb[4]

TDA19989AET_2

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Product data sheet

Rev. 02 — 18 May 2010

8 of 46

TDA19989AET

NXP Semiconductors

HDMI 1.4 transmitter with HDCP and CEC support

Table 3.

Internal assignment …continued

Internal assignment

Internal port

RGB

YCbCr 4 : 4 : 4

YCbCr 4 : 2 : 2

semi-planar

YCbCr 4 : 2 : 2

ITU656

VP[11]

VP[10]

VP[9]

VP[8]

VP[7]

VP[6]

VP[5]

VP[4]

VP[3]

VP[2]

VP[1]

VP[0]

B[3]

B[2]

B[1]

B[0]

R[7]

R[6]

R[5]

R[4]

R[3]

R[2]

R[1]

R[0]

Cb[3]

Cb[2]

Cb[1]

Cb[0]

Cr[7]

Cr[6]

Cr[5]

Cr[4]

Cr[3]

Cr[2]

Cr[1]

Cr[0]

CbCr[11]

CbCr[10]

CbCr[9]

CbCr[8]

CbCr[7]

CbCr[6]

CbCr[5]

CbCr[4]

CbCr[3]

CbCr[2]

CbCr[1]

CbCr[0]

The device can swap and invert, in the event of a little endian stream, the incoming video

data using I²C-bus registers VIP_CNTRL_0, VIP_CNTRL_1 and VIP_CNTRL_2 (page

00h) to match the expectation of the video processing block. Table 4 shows the behavior

of SWAP_A[2:0] of VIP_CNTRL_0 register, whose function is to map the 4 MSBs

VP[23:20] to the incoming video port.

TDA19989AET_2

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Product data sheet

Rev. 02 — 18 May 2010

9 of 46

TDA19989AET

NXP Semiconductors

HDMI 1.4 transmitter with HDCP and CEC support

Table 4.

Video input swap to VP[23:20]

External

assignment

SWAP_A[2:0] Internal assignment

selector

value

Internal RGB

YCbCr YCbCr 4 : 2 : 2 YCbCr 4 : 2 : 2

number

name

port

4 : 4 : 4 semi-planar

ITU656

F3

F2

F1

G1

G2

G3

H2

H3

C3

C2

D3

D2

D1

E1

E2

E3

A4

B4

A3

B3

A2

B2

B1

C1

VPC[7] 000b

VPC[6]

VP[23]

VP[22]

VP[21]

VP[20]

VP[23]

VP[22]

VP[21]

VP[20]

VP[23]

VP[22]

VP[21]

VP[20]

VP[23]

VP[22]

VP[21]

VP[20]

VP[23]

VP[22]

VP[21]

VP[20]

VP[23]

VP[22]

VP[21]

VP[20]

G[7]

G[6]

G[5]

G[4]

G[7]

G[6]

G[5]

G[4]

G[7]

G[6]

G[5]

G[4]

G[7]

G[6]

G[5]

G[4]

G[7]

G[6]

G[5]

G[4]

G[7]

G[6]

G[5]

G[4]

Y[7]

Y[6]

Y[5]

Y[4]

Y[7]

Y[6]

Y[5]

Y[4]

Y[7]

Y[6]

Y[5]

Y[4]

Y[7]

Y[6]

Y[5]

Y[4]

Y[7]

Y[6]

Y[5]

Y[4]

Y[7]

Y[6]

Y[5]

Y[4]

Y₀[11] Y₁[11]

Y₀[10] Y₁[10]

Cb[11] Y₀[11] Cr[11] Y₁[11]

Cb[10] Y₀[10] Cr[10] Y₁[10]

VPC[5]

Y₀[9]

Y₀[8]

Y₁[9]

Y₁[8]

Cb[9]

Cb[8]

Y₀[9]

Y₀[8]

Cr[9]

Cr[8]

Y₁[9]

Y₁[8]

VPC[4]

VPC[3] 001b

VPC[2]

Y₀[11] Y₁[11]

Y₀[10] Y₁[10]

Cb[11] Y₀[11] Cr[11] Y₁[11]

Cb[10] Y₀[10] Cr[10] Y₁[10]

VPC[1]

Y₀[9]

Y₀[8]

Y₁[9]

Y₁[8]

Cb[9]

Cb[8]

Y₀[9]

Y₀[8]

Cr[9]

Cr[8]

Y₁[9]

Y₁[8]

VPC[0]

VPB[7] 010b

VPB[6]

Y₀[11] Y₁[11]

Y₀[10] Y₁[10]

Cb[11] Y₀[11] Cr[11] Y₁[11]

Cb[10] Y₀[10] Cr[10] Y₁[10]

VPB[5]

Y₀[9]

Y₀[8]

Y₁[9]

Y₁[8]

Cb[9]

Cb[8]

Y₀[9]

Y₀[8]

Cr[9]

Cr[8]

Y₁[9]

Y₁[8]

VPB[4]

VPB[3] 011b

VPB[2]

Y₀[11] Y₁[11]

Y₀[10] Y₁[10]

Cb[11] Y₀[11] Cr[11] Y₁[11]

Cb[10] Y₀[10] Cr[10] Y₁[10]

VPB[1]

Y₀[9]

Y₀[8]

Y₁[9]

Y₁[8]

Cb[9]

Cb[8]

Y₀[9]

Y₀[8]

Cr[9]

Cr[8]

Y₁[9]

Y₁[8]

VPB[0]

VPA[7] 100b

VPA[6]

Y₀[11] Y₁[11]

Y₀[10] Y₁[10]

Cb[11] Y₀[11] Cr[11] Y₁[11]

Cb[10] Y₀[10] Cr[10] Y₁[10]

VPA[5]

Y₀[9]

Y₀[8]

Y₁[9]

Y₁[8]

Cb[9]

Cb[8]

Y₀[9]

Y₀[8]

Cr[9]

Cr[8]

Y₁[9]

Y₁[8]

VPA[4]

VPA[3] 101b

VPA[2]

Y₀[11] Y₁[11]

Y₀[10] Y₁[10]

Cb[11] Y₀[11] Cr[11] Y₁[11]

Cb[10] Y₀[10] Cr[10] Y₁[10]

VPA[1]

Y₀[9]

Y₀[8]

Y₁[9]

Y₁[8]

Cb[9]

Cb[8]

Y₀[9]

Y₀[8]

Cr[9]

Cr[8]

Y₁[9]

Y₁[8]

VPA[0]

In the same way:

• SWAP_B[2:0] is used to map incoming video port to the internal port VP[19:16].

• SWAP_C[2:0] is used to map incoming video port to the internal port VP[15:12].

• SWAP_D[2:0] is used to map incoming video port to the internal port VP[11:8].

• SWAP_E[2:0] is used to map incoming video port to the internal port VP[7:4].

• SWAP_F[2:0] is used to map incoming video port to the internal port VP[3:0].

The device expects to receive big endian incoming data. However, in cases where the

input digital stream to the chip is little endian, the use of the mirror bit of the same register

can help to re-order the input bits as described in Table 5.

TDA19989AET_2

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Product data sheet

Rev. 02 — 18 May 2010

10 of 46

TDA19989AET

NXP Semiconductors

HDMI 1.4 transmitter with HDCP and CEC support

Table 5.

TDA19989AET input/output capability

Bit setting

Internal port

VP[23]

VP[22]

VP[21]

VP[20]

VP[19]

VP[18]

VP[17]

VP[16]

VP[15]

VP[14]

VP[13]

VP[12]

VP[11]

VP[10]

VP[9]

To be mapped to

VPC[0]

VPC[1]

VPC[2]

VPC[3]

VPC[4]

VPC[5]

VPC[6]

VPC[7]

VPB[0]

VPB[1]

VPB[2]

VPB[3]

VPB[4]

VPB[5]

VPB[6]

VPB[7]

VPA[4]

VPA[5]

VPA[6]

VPA[7]

VPA[0]

VPA[1]

VPA[2]

VPA[3]

MIRR_A = 1

SWAP_A[2:0] = 1

MIRR_B = 1

SWAP_B[2:0] = 0

MIRR_C = 1

SWAP_C[2:0] = 3

MIRR_D = 1

SWAP_D[2:0] = 2

VP[8]

MIRR_E = 1

SWAP_E[2:0] = 5

VP[7]

VP[6]

VP[5]

VP[4]

MIRR_F = 1

SWAP_F[2:0] = 4

VP[3]

VP[2]

VP[1]

VP[0]

When input ports are not used, it is possible to deactivate them via the I²C-bus with the

appropriate set of registers ENA_VP_0, ENA_VP_1 and ENA_VP_2 on page 00h.

TDA19989AET_2

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Product data sheet

Rev. 02 — 18 May 2010

11 of 46

TDA19989AET

NXP Semiconductors

HDMI 1.4 transmitter with HDCP and CEC support

7.2.3.1 RGB 4 : 4 : 4 external synchronization (rising edge)

RGB (3 × 8-bit) external synchronization input (rising edge) mapping

Table 7.

Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 45h; VIP_CNTRL_2 = 01h.

Video port A

Video port B

RGB 4 : 4 : 4 Pin

Video port C

RGB 4 : 4 : 4 Pin

Control

RGB 4 : 4 : 4 Pin

RGB 4 : 4 : 4

VPA[0]

VPA[1]

VPA[2]

VPA[3]

VPA[4]

VPA[5]

VPA[6]

VPA[7]

B[0]

B[1]

B[2]

B[3]

B[4]

B[5]

B[6]

B[7]

VPB[0]

VPB[1]

VPB[2]

VPB[3]

VPB[4]

VPB[5]

VPB[6]

VPB[7]

G[0]

G[1]

G[2]

G[3]

G[4]

G[5]

G[6]

G[7]

VPC[0]

VPC[1]

VPC[2]

VPC[3]

VPC[4]

VPC[5]

VPC[6]

VPC[7]

R[0]

R[1]

R[2]

R[3]

R[4]

R[5]

R[6]

R[7]

HSYNC/HREF used

VSYNC/VREF used

DE/FREF

used

VCLK

HSYNC/HREF

VSYNC/VREF

DE/FREF

CONTROL

INPUTS

VPA[0] to VPA[7]

VPB[0] to VPB[7]

VPC[0] to VPC[7]

B [7:0]

...

B

[7:0]

B

[7:0]

xxx

0

1

2

3

xxx

G [7:0]

0

G [7:0]

1

G [7:0]

2

G [7:0]

3

G

R

G

R

[7:0]

xxx

R [7:0]

0

R [7:0]

1

R [7:0]

2

R [7:0]

3

xxx

001aag380

DE could also be generated from HSYNC/HREF and VSYNC/VREF.

Fig 5. Pixel encoding RGB 4 : 4 : 4 external synchronization input (rising edge)

7.2.3.2 YCbCr 4 : 4 : 4 external synchronization (rising edge)

Table 8.

YCbCr 4 : 4 : 4 (3 × 8-bit) external synchronization input (rising edge) mapping

Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 45h; VIP_CNTRL_2 = 01h.

Video port A Video port B Video port C

Control

YCbCr 4 : 4 : 4

used

VPA[0] Cb[0]

VPA[1] Cb[1]

VPA[2] Cb[2]

VPA[3] Cb[3]

VPA[4] Cb[4]

VPA[5] Cb[5]

VPA[6] Cb[6]

VPA[7] Cb[7]

VPB[0] Y[0]

VPB[1] Y[1]

VPB[2] Y[2]

VPB[3] Y[3]

VPB[4] Y[4]

VPB[5] Y[5]

VPB[6] Y[6]

VPB[7] Y[7]

VPC[0] Cr[0]

VPC[1] Cr[1]

VPC[2] Cr[2]

VPC[3] Cr[3]

VPC[4] Cr[4]

VPC[5] Cr[5]

VPC[6] Cr[6]

VPC[7] Cr[7]

HSYNC/HREF

VSYNC/VREF

DE/FREF

used

TDA19989AET_2

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Product data sheet

Rev. 02 — 18 May 2010

13 of 46

TDA19989AET

NXP Semiconductors

HDMI 1.4 transmitter with HDCP and CEC support

VCLK

HSYNC/HREF

CONTROL

VSYNC/VREF

INPUTS

DE/FREF

VPA[0] to VPA[7]

VPB[0] to VPB[7]

VPC[0] to VPC[7]

Cb [7:0]

...

Cb [7:0]

xxx

0

1

2

3

xxx

Y [7:0]

0

Y [7:0]

1

Y [7:0]

2

Y [7:0]

3

Y

xxx

[7:0]

Y

[7:0]

xxx

Cr [7:0]

0

Cr [7:0]

1

Cr [7:0]

2

Cr [7:0]

3

Cr [7:0]

xxx

Cr [7:0]

xxx

001aai444

DE could also be generated from HSYNC/HREF and VSYNC/VREF.

Fig 6. Pixel encoding YCbCr 4 : 4 : 4 external synchronization input (rising edge)

7.2.3.3 YCbCr 4 : 2 : 2 ITU656-like external synchronization (rising edge)

YCbCr 4 : 2 : 2 ITU656-like external synchronization input (rising edge) mapping

Table 9.

Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h.

Video port A Video port B

Control

YCbCr 4 : 2 : 2 (ITU656-like)

YCbCr 4 : 2 : 2

VPA[0] Cb[0]

VPA[1] Cb[1]

VPA[2] Cb[2]

VPA[3] Cb[3]

Y₀[0]

Cr[0]

Y₁[0]

VPB[0] Cb[4]

VPB[1] Cb[5]

VPB[2] Cb[6]

VPB[3] Cb[7]

VPB[4] Cb[8]

VPB[5] Cb[9]

Y₀[4]

Y₀[5]

Y₀[6]

Y₀[7]

Y₀[8]

Y₀[9]

Cr[4]

Cr[5]

Cr[6]

Cr[7]

Cr[8]

Cr[9]

Y₁[4]

Y₁[5]

Y₁[6]

Y₁[7]

Y₁[8]

Y₁[9]

HSYNC/HREF used

VSYNC/VREF used

Y₀[1]

Cr[1]

Y₁[1]

Y₀[2]

Cr[2]

Y₁[2]

DE/FREF

used

Y₀[3]

Cr[3]

Y₁[3]

VPA[4]

VPA[5]

VPA[6]

VPA[7]

-

VPB[6] Cb[10] Y₀[10] Cr[10] Y₁[10]

VPB[7] Cb[11] Y₀[11] Cr[11] Y₁[11]

VCLK

HSYNC/HREF

VSYNC/VREF

DE/FREF

CONTROL

INPUTS

VPB[0] to VPB[7];

VPA[0] to VPA[3]

Cb [11:0]

0

Y [11:0]

0

Cr [11:0]

0

Y [11:0]

1

...

Cr [11:0]

xxx

Y

[1:0]

xxx

001aai445

Fig 7. Pixel encoding YCbCr 4 : 2 : 2 ITU656-like external synchronization input (rising edge)

TDA19989AET_2

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Product data sheet

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14 of 46

TDA19989AET

NXP Semiconductors

HDMI 1.4 transmitter with HDCP and CEC support

7.2.3.4 YCbCr 4 : 2 : 2 ITU656-like external synchronization (double edge)

Table 10. YCbCr 4 : 2 : 2 ITU656-like external synchronization input (double edge) mapping

Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h.

Video port A

Video port B

Control

YCbCr 4 : 2 : 2 (ITU656-like)

YCbCr 4 : 2 : 2

VPA[0] Cb[0]

VPA[1] Cb[1]

VPA[2] Cb[2]

VPA[3] Cb[3]

VPA[4] -

Y₀[0]

Cr[0]

Y₁[0]

VPB[0] Cb[4]

VPB[1] Cb[5]

VPB[2] Cb[6]

VPB[3] Cb[7]

VPB[4] Cb[8]

VPB[5] Cb[9]

Y₀[4]

Y₀[5]

Y₀[6]

Y₀[7]

Y₀[8]

Y₀[9]

Cr[4]

Cr[5]

Cr[6]

Cr[7]

Cr[8]

Cr[9]

Y₁[4]

Y₁[5]

Y₁[6]

Y₁[7]

Y₁[8]

Y₁[9]

HSYNC/HREF used

VSYNC/VREF used

Y₀[1]

Cr[1]

Y₁[1]

Y₀[2]

Cr[2]

Y₁[2]

DE/FREF

used

Y₀[3]

Cr[3]

Y₁[3]

-

VPA[5] -

VPA[6] -

VPB[6] Cb[10] Y₀[10] Cr[10] Y₁[10]

VPB[7] Cb[11] Y₀[11] Cr[11] Y₁[11]

VPA[7] -

VCLK

HSYNC/HREF

VSYNC/VREF

DE/FREF

CONTROL

INPUTS

VPB[0] to VPB[7];

VPA[0] to VPA[3]

Cb [11:0]

0

Y [11:0]

0

Cr [11:0]

0

Y [11:0]

1

...

Cr [11:0]

xxx

Y

[1:0]

xxx

001aai446

Fig 8. Pixel encoding YCbCr 4 : 2 : 2 ITU656-like external synchronization input (double edge)

7.2.3.5 YCbCr 4 : 2 : 2 ITU656-like embedded synchronization (rising edge)

Table 11. YCbCr 4 : 2 : 2 ITU656-like embedded synchronization input (rising edge) mappings

Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h.

Video port A

Video port B

Control

YCbCr 4 : 2 : 2 (ITU656-like)

YCbCr 4 : 2 : 2

VPA[0] Cb[0] Y₀[0]

VPA[1] Cb[1] Y₀[1]

VPA[2] Cb[2] Y₀[2]

VPA[3] Cb[3] Y₀[3]

Cr[0]

Y₁[0]

VPB[0] Cb[4] Y₀[4]

VPB[1] Cb[5] Y₀[5]

VPB[2] Cb[6] Y₀[6]

VPB[3] Cb[7] Y₀[7]

VPB[4] Cb[8] Y₀[8]

VPB[5] Cb[9] Y₀[9]

Cr[4]

Cr[5]

Cr[6]

Cr[7]

Cr[8]

Cr[9]

Y₁[4]

Y₁[5]

Y₁[6]

Y₁[7]

Y₁[8]

Y₁[9]

HSYNC/HREF not used

VSYNC/VREF not used

Cr[1]

Y₁[1]

Cr[2]

Y₁[2]

DE/FREF

not used

Cr[3]

Y₁[3]

VPA[4] -

VPA[5] -

VPA[6] -

VPA[7] -

-

VPB[6] Cb[10] Y₀[10] Cr[10] Y₁[10]

VPB[7] Cb[11] Y₀[11] Cr11] Y₁[11]

TDA19989AET_2

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Product data sheet

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TDA19989AET

NXP Semiconductors

HDMI 1.4 transmitter with HDCP and CEC support

VCLK

VPB[0] to VPB[7];

VPA[0] to VPA[3]

Cb [11:0]

0

Y [11:0]

0

Cr [11:0]

0

Y [11:0]

1

...

Cr [11:0]

xxx

Y

[1:0]

xxx

001aai447

Fig 9. Pixel encoding YCbCr 4 : 2 : 2 ITU656-like embedded synchronization input (rising edge)

7.2.3.6 YCbCr 4 : 2 : 2 ITU656-like embedded synchronization (double edge)

Table 12. YCbCr 4 : 2 : 2 ITU656-like embedded synchronization input (double edge) mapping

Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h.

Video port A

Video port B

Control

YCbCr 4 : 2 : 2 (ITU656-like)

YCbCr 4 : 2 : 2

VPA[0] Cb[0] Y₀[0]

VPA[1] Cb[1] Y₀[1]

VPA[2] Cb[2] Y₀[2]

VPA[3] Cb[3] Y₀[3]

Cr[0]

Y₁[0]

VPB[0] Cb[4] Y₀[4]

VPB[1] Cb[5] Y₀[5]

VPB[2] Cb[6] Y₀[6]

VPB[3] Cb[7] Y₀[7]

VPB[4] Cb[8] Y₀[8]

VPB[5] Cb[9] Y₀[9]

Cr[4]

Cr[5]

Cr[6]

Cr[7]

Cr[8]

Cr[9]

Y₁[4]

Y₁[5]

Y₁[6]

Y₁[7]

Y₁[8]

Y₁[9]

HSYNC/HREF not used

VSYNC/VREF not used

Cr[1]

Y₁[1]

Cr[2]

Y₁[2]

DE/FREF

not used

Cr[3]

Y₁[3]

VPA[4] -

VPA[5] -

VPA[6] -

VPA[7] -

-

VPB[6] Cb[10] Y₀[10] Cr[10] Y₁[10]

VPB[7] Cb[11] Y₀[11] Cr[11] Y₁[11]

VCLK

VPB[0] to VPB[7];

VPA[0] to VPA[3]

Cb [11:0]

0

Y [11:0]

0

Cr [11:0]

0

Y [11:0]

1

...

Cr [11:0]

xxx

Y

[1:0]

xxx

001aai448

Fig 10. Pixel encoding YCbCr 4 : 2 : 2 ITU656-like embedded synchronization input (double edge)

TDA19989AET_2

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Product data sheet

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16 of 46

TDA19989AET

NXP Semiconductors

HDMI 1.4 transmitter with HDCP and CEC support

7.2.3.7 YCbCr 4 : 2 : 2 semi-planar external synchronization (rising edge)

Table 13. YCbCr 4 : 2 : 2 semi-planar external synchronization input (rising edge) mapping

Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 14h.

Video port A

Pin YCbCr 4 : 2 : 2

semi-planar

Video port B

Pin YCbCr 4 : 2 : 2

semi-planar

Video port C

Pin YCbCr 4 : 2 : 2

semi-planar

Control

YCbCr 4 : 2 : 2

VPA[0] Y₀[0]

VPA[1] Y₀[1]

VPA[2] Y₀[2]

VPA[3] Y₀[3]

VPA[4] Cb[0]

VPA[5] Cb[1]

VPA[6] Cb[2]

VPA[7] Cb[3]

Y₁[0]

Y₁[1]

Y₁[2]

Y₁[3]

Cr[0]

Cr[1]

Cr[2]

Cr[3]

VPB[0] Y₀[4]

VPB[1] Y₀[5]

VPB[2] Y₀[6]

VPB[3] Y₀[7]

VPB[4] Y₀[8]

VPB[5] Y₀[9]

VPB[6] Y₀[10]

VPB[7] Y₀[11]

Y₁[4]

Y₁[5]

Y₁[6]

Y₁[7]

Y₁[8]

Y₁[9]

Y₁[10]

Y₁[11]

VPC[0] Cb[4]

VPC[1] Cb[5]

VPC[2] Cb[6]

VPC[3] Cb[7]

VPC[4] Cb[8]

VPC[5] Cb[9]

Cr[4]

Cr[5]

Cr[6]

Cr[7]

Cr[8]

Cr[9]

HSYNC/HREF used

VSYNC/VREF

DE/FREF

used

VPC[6] Cb[10] Cr[10]

VPC[7] Cb[11] Cr[11]

VCLK

HSYNC/HREF

VSYNC/VREF

DE/FREF

CONTROL

INPUTS

VPB[0] to VPB[7];

VPA[0] to VPA[3]

Y [11:0]

0

Y [11:0]

1

Y [11:0]

2

Y [11:0]

3

Y [11:0]

4

Y [11:0]

5

...

VPC[0] to VPC[7];

VPA[4] to VPA[7]

Cb [11:0]

0

Cr [11:0]

0

Cb [11:0]

2

Cr [11:O]

2

Cb [11:0]

4

Cr [11:0]

4

...

001aai449

Fig 11. Pixel encoding YCbCr 4 : 2 : 2 semi-planar external input synchronization (rising edge)

7.2.3.8 YCbCr 4 : 2 : 2 semi-planar embedded synchronization (rising edge)

Table 14. YCbCr 4 : 2 : 2 semi-planar embedded synchronization input (rising edge) mapping

Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 14h.

Video port A

Pin YCbCr 4 : 2 : 2

semi-planar

Video port B

Pin YCbCr 4 : 2 : 2

semi-planar

Video port C

Pin YCbCr 4 : 2 : 2

semi-planar

Control

YCbCr 4 : 2 : 2

VPA[0] Y₀[0]

VPA[1] Y₀[1]

VPA[2] Y₀[2]

VPA[3] Y₀[3]

VPA[4] Cb[0]

VPA[5] Cb[1]

VPA[6] Cb[2]

VPA[7] Cb[3]

Y₁[0]

Y₁[1]

Y₁[2]

Y₁[3]

Cr[0]

Cr[1]

Cr[2]

Cr[3]

VPB[0] Y₀[4]

VPB[1] Y₀[5]

VPB[2] Y₀[6]

VPB[3] Y₀[7]

VPB[4] Y₀[8]

VPB[5] Y₀[9]

VPB[6] Y₀[10]

VPB[7] Y₀[11]

Y₁[4]

Y₁[5]

Y₁[6]

Y₁[7]

Y₁[8]

Y₁[9]

Y₁[10]

Y₁[11]

VPC[0] Cb[4]

VPC[1] Cb[5]

VPC[2] Cb[6]

VPC[3] Cb[7]

VPC[4] Cb[8]

VPC[5] Cb[9]

Cr[4]

Cr[5]

Cr[6]

Cr[7]

Cr[8]

Cr[9]

HSYNC/HREF not used

VSYNC/VREF

DE/FREF

not used

VPC[6] Cb[10] Cr[10]

VPC[7] Cb[11] Cr[11]

TDA19989AET_2

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Product data sheet

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TDA19989AET

NXP Semiconductors

HDMI 1.4 transmitter with HDCP and CEC support

VCLK

VPB[0] to VPB[7];

VPA[0] to VPA[3]

Y [11:0]

...

0

1

2

3

4

5

VPC[0] to VPC[7];

VPA[4] to VPA[7]

Cb [11:0]

0

Cr [11:0]

0

Cb [11:0]

2

Cr [11:0]

2

Cb [11:0]

4

Cr [11:0]

4

001aai450

Fig 12. Pixel encoding YCbCr 4 : 2 : 2 semi-planar embedded synchronization input (rising edge)

7.2.4 Synchronization

TDA19989AET can be synchronized with extraction of the sync information from

embedded sync (SAV/EAV) codes inside the video stream or with external

HSYNC/VSYNC inputs.

7.2.4.1 Timing extraction generator

Synchronization signals can be extracted from Start Active Video (SAV) and End Active

Video (EAV) in case of embedded synchronization in the data stream.

Synchronization signals can be embedded in YCbCr 4 : 2 : 2 ITU656 (up to 1 × 12-bit) and

YCbCr 4 : 2 : 2 semi-planar (up to 2 × 12-bit).

7.2.4.2 Data enable generator

TDA19989AET contains a Data Enable (DE) generator; this can generate an internal DE

signal for a system which does not provide one.

7.3 Input and output video format

Due to the flexible video input formatter, TDA19989AET can accept a large range of input

formats. This flexibility allows TDA19989AET to be compatible with the maximum possible

number of MPEG decoders. Moreover, these input formats may be changed in many

ways (color space converter, upsampler, downsampler) before it is transmitted across the

HDMI link. Table 15 gives the possible inputs and outputs.

Table 15. Use of color space converter, upsampler and downsampler

Input

Output

Color space

RGB

Color space

RGB

Format

Channels

Format

4 : 4 : 4

4 : 2 : 2

4 : 4 : 4

4 : 2 : 2

4 : 4 : 4

4 : 2 : 2

Channels

3 × 8-bit

2 × 12-bit

3 × 8-bit

2 × 12-bit

3 × 8-bit

2 × 12-bit

4 : 4 : 4

3 × 8-bit

YCbCr

RGB

YCbCr

4 : 4 : 4

4 : 2 : 2

3 × 8-bit

YCbCr

up to 1 × 12-bit RGB

semi-planar

YCbCr

TDA19989AET_2

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Product data sheet

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TDA19989AET

NXP Semiconductors

HDMI 1.4 transmitter with HDCP and CEC support

Table 15. Use of color space converter, upsampler and downsampler …continued

Input

Output

Color space

YCbCr

Format

Channels

Color space

Format

4 : 4 : 4

4 : 2 : 2

Channels

3 × 8-bit

2 × 12-bit

4 : 2 : 2

up to 2 × 12-bit RGB

semi-planar

YCbCr

7.4 Upsampler

The incoming YCbCr 4 : 2 : 2 (2 × 12-bit) data stream format may be upsampled into

YCbCr 4 : 4 : 4 (3 × 8-bit) data stream by repeating or linearly interpolating the

chrominance pixels.

7.5 Color space converter

The color space converter is used to convert input video data from one type to another

color space (e.g. RGB to YCbCr and YCbCr to RGB). This block can be bypassed and

each coefficient is programmable via the I²C-bus register.

⎛

⎜

⎝

⎞

⎟

⎠

C₁₁C₁₂C₁₃

C₂₁C₂₂C₂₃

C₃₁C₃₂C₃₃

Oin_{G ⁄ Y}

Oin_{R ⁄ Cr}

Oin_{B ⁄ Cb}

Oout_Y\G

Oout_Cr\R

Oout_Cb\B

Y\G

Cr\R

Cb\B

Y

=

×

+

(1)

R ⁄ Cr

B ⁄ Cb

7.6 Gamut-related metadata

Gamut-related metadata is an enhanced colorimetry beyond the default standard with

higher definition colorimetries. Profile P0 is supported, which means that only one packet

per video field is sent. Color gamut boundary data are defined the standards:

• xvYCC601 (IEC 61966-2-4 – SD) (using YCbCr)

• xvYCC709 (IEC 61966-2-4 – HD) (using YCbCr)

• AdobeYCC601 (IEC 61966-2-5) (using YCbCr)

• AdobeRGB (IEC 61966-2-5) (using RGB)

Remark: Gamut-related metadata is an HDMI 1.4 feature.

7.7 Downsampler

This block works only with YCbCr input format; the filters downsample the Cb and Cr

signals by a factor of 2. A delay is added on the Y channel, which corresponds to the

pipeline delay of the filters, to put the Y channel in phase with the Cb-Cr channel.

7.8 Audio input format

TDA19989AET is compatible with the following audio features described in the HDMI 1.4

specification:

• S/PDIF

• I²S-bus up to four channels

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Product data sheet

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TDA19989AET

NXP Semiconductors

HDMI 1.4 transmitter with HDCP and CEC support

TDA19989AET can carry audio in I²S-bus format (one stereo to two stereo channels) or in

S/PDIF format through one audio pin named AP1 or AP2. S/PDIF or I²S-bus format can

be selected via the I²C-bus. Only one audio format can be used at a time: either S/PDIF or

I²S-bus. Table 16 shows the audio port allocation and Section 7.8.3 gives more details.

Table 16. Audio port configuration

Audio port

Input configuration

S/PDIF

I²S-bus

AP0

AP1

AP2

AP3

ACLK

-

WS (word select)

I²S-bus channel 0

I²S-bus channel 1

S/PDIF input

MCLK

-

SCK (I²S-bus clock)

All audio ports are LV-CMOS 1.8 V compatible and LV-CMOS 3.3 V tolerant. It is possible

to deactivate unused ports via I²C-bus with ENA_AP register on page 00h for both audio

and clock inputs.

7.8.1 S/PDIF

In this format TDA19989AET supports 2-channel uncompressed PCM data (IEC 60958)

layout 0, or compressed bit stream (Dolby Digital, DTS, AC3 etc.) layout 1.

Only one S/PDIF input can be used at the same time. The selection is done by register.

TDA19989AET is able to recover the original clock from the S/PDIF signal (no need of

external clock). In addition, it can also use an external clock to decode the S/PDIF signal.

7.8.2 I²S-bus

There are 2 × I²S-bus stereo input, which enables 4 PCM channels to be carried. The

I²S-bus input interface receives an I²S-bus signal including serial data, word select and

serial clock.

Typical waveforms for the I²S-bus signals at 64f_sare given by Figure 13.

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LEFT CHANNEL RIGHT CHANNEL LEFT CHANNEL RIGHT CHANNEL LEFT CHANNEL RIGHT CHANNEL

(n−1)

(n)

(n+1)

word select

f

s

MSB

24-bit audio sample word

LSB

0

audio clock

64f

s

001aah029

a. Philips format.

LEFT CHANNEL RIGHT CHANNEL LEFT CHANNEL RIGHT CHANNEL LEFT CHANNEL RIGHT CHANNEL

(n−1)

(n)

(n+1)

word select

f

s

MSB

24-bit audio sample word

LSB

0

audio clock

64f

s

001aah030

b. Left justified format.

LEFT CHANNEL RIGHT CHANNEL LEFT CHANNEL RIGHT CHANNEL LEFT CHANNEL RIGHT CHANNEL

(n−1)

(n)

(n+1)

word select

f

s

0

MSB

24-bit audio sample word

LSB

audio clock

64f

s

001aah031

c. Right justified format.

Fig 13. I²S-bus formats

The I²S-bus input interface can receive up to 24-bit wide audio samples via the serial data

input with a clock frequency of at least 32 times the input sample frequency f_s.

Audio samples with a precision better than 24-bit are truncated to 24-bit. If the input clock

has a frequency of 32f_s, only 16-bit audio-samples can be received. In this case, the 8

LSBs will be set to 0. If the input clock has a frequency of 64f_sand is left justified or

Philips, the audio word is truncated to 24-bit format and other bits padded with zeros. If

the input clock has a frequency of 64f_sand is right justified, audio sample size has to be

specified via software drivers.

The serial data signal carries the serial baseband audio data, sample by sample left/right

interleaved.

The word select signal indicates whether left or right channel information is transferred

over the serial data line.

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7.8.3 Audio port internal assignment

The aim of the internal audio input assignment is to internally map any of the incoming

data from the audio port AP1 or AP2 to I²S-bus channel 0 or S/PDIF internal ports by

setting the appropriate I²C-bus register.

TDA19989

AUDIO

INTERNAL PORTS

2

I C-BUS CHANNEL 0/1

AP1/AP2

S/PDIF

2

I C-bus select

001aal259

Fig 14. Audio input swap to I²S-bus channel 0 or S/PDIF

7.9 Power management

TDA19989AET HDMI and CEC cores can be independently powered down by the I²C-bus

register. In Standby mode all activities are reduced by switching off all PLLs, HDMI and

CEC cores and disconnecting the biasing structure of the output stage. TDA19989AET

has a very low power consumption, which is suitable for portable applications.

Table 17 gives the typical power consumption of the device in different configurations.

Table 17. TDA19989AET typical power consumption in different configurations

Typical power Configuration

Comment

400 μW

Standby mode:

• I²C-bus ON

default configuration: after power-up; PLLs

HDMI and CEC cores are OFF; can be

switched ON via I²C-bus register

1.5 mW

Sleep mode without CEC:

no sink connected; CEC is OFF

• HDMI interruption (HPD,

RxSense only)

1.8 mW

90 mW

Sleep mode with CEC:

no sink connected; CEC is ON

• HDMI interruption (HPD,

RxSense only)

• CEC interruption

Low power 1080i mode:

• Video format 1080i

• Video input RGB 4 : 4 : 4

• No CEC

sink connected; CEC is OFF; 30 % activity on

video input ports

140 mW

Full speed mode:

all blocks enabled and running; 30 % activity on

video input ports

• Video format 1080p

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7.10 Interrupt controller

Pin INT is used to alert the system microcontroller that a critical event concerning the

HDMI or CEC has occurred. The software provided with the device read a status register

(I²C-bus) to determine which block between HDMI and CEC has caused the interruption

before processing it. Some of theses interrupts are maskable. The interrupt types are

described in Table 18.

Table 18. Interruptions

Interrupt domain

Interrupt name

Definition

Maskable feature

HDCP

r0

r0 = R’0 check done

pj = P’j check fails

V = V’ check success

bstatus available

bcaps available

maskable

pj

sha-1

bstatus

bcaps

t0

HDCP goes to initial

state

security

HDCP encryption is off

or blue screen removed

not maskable

HPD

hpd

transition on HPD input maskable

transition on RxSense maskable

RxSense

Interrupt

rx_sense

sw_intsoftware

test purpose (output an maskable

interrupt signal)

EDID

CEC

edid_block_rd

cec_int

EDID block read finished maskable

CEC message received not maskable

7.10.1 Hot plug/unplug detect

The hot plug detect (HPD) pin is 5 V input tolerant. The HPD signal, when asserted, tells

the transmitter that the receiver is connected. When changing from LOW-to-HIGH,

TDA19989AET has to read the EDID of the receiver in order to select the video format

that the receiver can handle.

7.10.2 Receiver sensitivity

TDA19989AET has the capability to sense the receiver connectivity and working behavior.

This feature (RxSense) detects the presence of the 50 Ω pull-up resistor R_Ton the TMDS

clock channel of the downstream side.

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RECEIVER

V

CC

R

pu

HDMI cable

V

DD

1.8 V

pole τ =

80 ns

35 kΩ

Vinp_rxs

Vinn_rxs

power_down

35 kΩ

RXS_FIL

INTERNAL

BANDGAP

0.935 V 4%

I_transmit

TDA19989

001aal267

Fig 15. Receiver sensitivity detection

As long as the receiver is connected to the transmitter and powered-up, bit RXS_FIL is set

to logic 1.

As soon as the cable is unplugged or receiver side powered off (assuming in this case that

V

_CCis switched off), the RxSense generates an interrupt inside TDA19989AET, changing

the value of bit RXS_FIL to logic 0 (See Table 19). This allows the application to stop

sending unnecessary video content.

This feature is very useful when the receiver recovers from an off-state and does not

generate a HPD transition HIGH-to-LOW-to-HIGH. In this particular case, RxSense will

generate an interrupt so that the chip restarts sending video.

Table 19. Receiver detection according to averaged terminal voltage

Average voltage

(Vinp_rxs + Vinn_rxs) / 2

bit RXS_FIL: receiver

powered on

bit RXS_FIL: receiver

powered off

V ≥ 1.2 V

1

0

0.7 V < V < 1.2 V

V ≤ 0.7 V

undefined

0

Remark: According to the HDMI specification, only the HPD interrupt allows the

application to read the EDID. The RxSense interrupt is not mandatory to initialize the

EDID reading procedure.

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7.11 HDCP processing

7.11.1 High-bandwidth digital content protection

TDA19989 contains an HDCP function, which encrypts the transmitted stream content

(both video and audio). This function can be enabled and disabled via the I²C-bus.

The keys are stored internally in OTP non-volatile memory for maximum security.

7.11.1.1 Repeater function

TDA19989AET can be used in a repeater device according to the HDCP specification,

Rev 1.3. TDA19989AET is able to store the KSV list of a maximum of 127 devices in a

register memory.

7.11.1.2 SHA-1

To deal with repeater, a SHA-1 calculation is performed by the transmitter and by the

downstream repeater. For security purposes and in order to relieve the microcontroller,

the SHA-1 has been implemented within TDA19989AET.

This calculation is worked out after the transmitter has loaded the KSV list (see HDCP

specification, Rev 1.3). If SHA-1 calculated by transmitter equals the SHA-1 calculated by

repeater, then an interrupt is sent.

7.12 CEC

TDA19989AET with its embedded CEC block provides a complete solution to enable

Consumer Electronic Control (CEC) in product (DSC, DVC, PMP, UM PC). This eliminates

the need of any additional device to handle this feature thus improving BOM (Bill Of

Materials). CEC capability allows AV products (CEC enable) to communicate together

over the home appliance network which could be controlled using only one remote

control.

The CEC block manages low level transactions (compliant to CEC timing specification)

over the one bidirectional line. It translates CEC protocol in I²C-bus for the host processor

and vice versa. It manages CEC message reception and transmission compliant to CEC

protocol and provides the message to the system microcontroller (host processor).

For power consumption optimization purpose CEC could be enable or disable through

I²C-bus register. The following sections describe CEC:

• Features

• Clocking scheme

7.12.1 Features

• Receive and transmit CEC messages to host processor

• Supports multiple CEC logical addresses

• Supports CEC messages up to 16 bytes long

• Programmable retry count

• Comprehensive arbitration and collision handling

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7.12.2 Clock

HDMI 1.4 transmitter with HDCP and CEC support

CEC clock must be running in Sleep mode (with CEC) to wake up TDA19989AET using

CEC specific message as described in “HDMI specification 1.4”.

CEC module can be clocked using:

• External clock:

– 12 MHz crystal ± 1 %.

• Internal clock:

– FRO (Free Running Oscillator). FRO frequency varies and in the range from

12.64 MHz to 12.9 MHz. See Figure 16.

CEC operates normally (i.e. matches the timing requested CEC specification) if and only if

its clock frequency is set to 12 MHz.

TDA19989

CEC clock calibration module

FRO

DIVIDER

CEC CLK

12 MHz

CEC

MODULE

2

I C-bus

2

INT

I C-bus

HOST PROCESSOR

001aal265

Fig 16. Modules involved in CEC clock calibration process

Calibration procedure is completely handled by the software delivered together with the

device, it has the following steps:

• Host processor set TDA19989AET in calibration mode

• Host processor generates a negative pulse of 10 ms ± 1 % on INT pin

• Host processor deselects the calibration mode when it is completed, the chip is ready

to operate

CEC clock calibration must be performed at each power-up and each time TDA19989AET

moves from Standby or Sleep (without CEC) state to normal operating mode.

Non successful calibration will lead to CEC signal not matching timings specification; as a

consequence, CEC will not be functional.

7.12.3 CEC interrupt

Pin INT is used by TDA19989AET to warn the host processor that HDMI or CEC events

(CEC message is available to read) have occurred.

Software interrupt status register reads determine which block between HDMI or CEC has

raised the interruption before processing it.

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7.12.4 Power-On Reset (POR)

After power-up, TDA19989AET is activated by internal reset from POR module. This is

used to set TDA19989AET to a known state.

7.12.5 Repeater function

TDA19989AET can be used in a repeater device according to HDMI 1.4.

7.13 HDMI core

7.13.1 Output TMDS buffers

7.13.1.1 Digitally controlled signal amplitude

The TMDS signal output peak-to-peak voltage (Vswing) is programmable by the software

using I²C-bus register vswing_crtl[3:0]. Vswing varies from 370 mV to 640 mV with ± 5 %

accuracy in 18 mV steps according to the following formula:

Vswing = 370 mV + 18 mV × vswing_ctrl[3:0]

An external resistor (10 kΩ ± 1 %) must be connected between pin EXT_SWING and

analog ground.

7.13.2 Pixel repetition

To transmit video formats with pixel rates below 25 megasamples per second or to

increase the number of audio sample packets in each frame, TDA19989AET uses pixel

repetition to increase the transmitted pixel clock (see Table 20).

Table 20. Pixel repetition

PR[3]

PR[2]

PR[1]

PR[0]

Pixel repetition factor

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

no repetition: pixel sent once

0

2 times: pixel repeated once

3 times

0

4 times

0

5 times

0

6 times

0

7 times

0

8 times

1

9 times

1

10 times

others

reserved

7.13.3 DDC-bus channel

The DDC-bus pins DSDA and DSCL are 5 V tolerant and can work at standard mode

(100 kHz). The DDC-bus is used as a master interface when reading the EDID.

When the device is power-off, DSDA and DSCL ports:

• become in high-impedance

• can withstand 5 V from the sink

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7.14 E-EDID

7.14.1 E-EDID reading

As a master interface for the EDID process, the DDC-bus is compliant with the I²C-bus

specification and has the possibility of repeat/start condition to enable quick access to the

EDID content, as well as the possibility of reading a large EDID (with the use of segment

pointer).

TDA19989AET has a whole I²C-bus (page 09h) dedicated to the EDID where one block

(128 bytes) can be stored. The block can be read by the system microcontroller to

determine the supported video and audio format of the downstream site.

Remark: When the block is read by TDA19989AET, it generates an interrupt to warn the

main processor that the chip is ready to transmit the content. Once the content is read out

by the main processor, it can allow other blocks to be read if required.

7.14.2 HDMI and DVI receiver discrimination

This information is located in the E-EDID receiver part, in the ‘vendor-specific data block’

within the first CEA EDID timing extension.

If the 24-bit IEEE Registration Identifier contains the value 00 0C03h, then the receiver

will support HDMI, otherwise the device will be treated as a DVI device.

However, even through TDA19989AET have directly access to that information, it is the

task of the host processor to ask to switch from DVI to HDMI mode.

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8. I²C-bus interface and register definitions

8.1 I²C-bus protocol

The I²C-bus pins CSDA and CSCL are 1.8 V and 3.3 V tolerant. Both Fast mode

(400 kHz) and Standard mode (100 kHz) are supported.

The registers of TDA19989AET can be accessed via the I²C-bus. All registers are R/W

except for those which are confidential.

HDMI and CEC cores I²C-bus addresses are given in Table 21 and Table 22.

Table 21. HDMI core I²C-bus address

HDMI core address

A6

A5

A4

A3

A2

A1

A0

R/W

1

0

0/1

Table 22. CEC core I²C-bus address

CEC core address

A6

A5

A4

A3

A2

A1

A0

R/W

0

1

0

1

0

0/1

For read access, the master writes the address of TDA19989AET HDMI or CEC core, and

the subaddress to access the specific register and then the data.

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

CSCL

CSDA

SLAVE ADDRESS

SUBADDRESS

DATA

STOP

001aal419

Fig 17. I²C-bus access

8.2 Memory page management

The I²C-bus memory is split into several pages for HDMI core only, and the selection

between pages is made with common register CURPAGE_ADR. It is only necessary to

write in this register once to change the current page. So multiple read or write operations

in the same page need a write register CURPAGE_ADR once at the beginning.

The following memory pages are available for TDA19989AET:

• Page 00h: general control

• Page 02h: PLL settings

• Page 09h: EDID control page

• Page 10h: information frames and packets

• Page 11h: audio settings and content info packets

• Page 12h: HDCP and OTP

• Page 13h: gamut-related metadata packets

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The CEC core does not need memory page mechanism due to its reduced number of

registers.

8.3 ID version

The ID version readable via I²C-bus is defined by the concatenation of VERSION_MSB

and VERSION registers. The ID version value is 212h.

8.4 Clock stretching

Clock stretching pauses a transaction by holding the CSCL line LOW. The transaction

cannot continue until the line is released HIGH again.

For example: on the byte level, a device may be able to receive bytes of data at a fast

rate, but needs more time to store a received byte or prepare another byte to be

transmitted. Slaves can then hold the CSCL line LOW after reception and

acknowledgment of a byte to force the master into a wait state until the slave is ready for

the next byte transfer; see Table 31.

Clock stretching must be supported by I²C-bus master especially when CEC feature of

TDA19989AET is used. If CEC feature of TDA19989AET is not used, I²C-bus master

does not need to support clock stretching.

9. Input format

In Table 23 the port VPA has been mapped to C_b(YCbCr space)/B (RGB space), VPB has

been mapped to Y (YCbCr space)/G (RGB space) and VPC has been mapped to Cr

(YCbCr space)/R (RGB space).

Table 23. Input format

L: recommend tield to LOW voltage, e.g. ground

Input pins Signal

RGB

YCbCr

4 : 4 : 4

4 : 2 : 2 (semi-planar)

4 : 2 : 2 (ITU 656-like)

Video port A

VPA[0]

VPA[1]

VPA[2]

VPA[3]

VPA[4]

VPA[5]

VPA[6]

VPA[7]

Video port B

VPB[0]

VPB[1]

VPB[2]

VPB[3]

VPB[4]

VPB[5]

Cb[0]/B[0]

B[0]

B[1]

B[2]

B[3]

B[4]

B[5]

B[6]

B[7]

Cb[0]

Cb[1]

Cb[2]

Cb[3]

Cb[4]

Cb[5]

Cb[6]

Cb[7]

Y₀[0]

Y₀[1]

Y₀[2]

Y₀[3]

Cb[0]

Cb[1]

Cb[2]

Cb[3]

Y₁[0]

Y₁[1]

Y₁[2]

Y₁[3]

Cr[0]

Cr[1]

Cr[2]

Cr[3]

Cb[0]

Cb[1]

Cb[2]

Cb[3]

L

Y₀[0]

Y₀[1]

Y₀[2]

Y₀[3]

L

Cr[0]

Cr[1]

Cr[2]

Cr[3]

L

Y₁[0]

Y₁[1]

Y₁[2]

Y₁[3]

L

Cb[1]/B[1]

Cb[2]/B[2]

Cb[3]/B[3]

Cb[4]/B[4]

Cb[5]/B[5]

Cb[6]/B[6]

Cb[7]/B[7]

L

Y[0]/G[0]

Y[1]/G[1]

Y[2]/G[2]

Y[3]/G[3]

Y[4]/G[4]

Y[5]/G[5]

G[0]

G[1]

G[2]

G[3]

G[4]

G[5]

Y[0]

Y[1]

Y[2]

Y[3]

Y[4]

Y[5]

Y₀[4]

Y₀[5]

Y₀[6]

Y₀[7]

Y₀[8]

Y₀[9]

Y₁[4]

Y₁[5]

Y₁[6]

Y₁[7]

Y₁[8]

Y₁[9]

Cb[4]

Cb[5]

Cb[6]

Cb[7]

Cb[8]

Cb[9]

Y₀[4]

Y₀[5]

Y₀[6]

Y₀[7]

Y₀[8]

Y₀[9]

Cr[4]

Cr[5]

Cr[6]

Cr[7]

Cr[8]

Cr[9]

Y₁[4]

Y₁[5]

Y₁[6]

Y₁[7]

Y₁[8]

Y₁[9]

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Table 23. Input format …continued

L: recommend tield to LOW voltage, e.g. ground

Input pins Signal

RGB

4 : 4 : 4

G[6]

YCbCr

4 : 4 : 4

Y[6]

4 : 2 : 2 (semi-planar)

4 : 2 : 2 (ITU 656-like)

VPB[6]

VPB[7]

Video port C

VPC[0]

VPC[1]

VPC[2]

VPC[3]

VPC[4]

VPC[5]

VPC[6]

VPC[7]

Y[6]/G[6]

Y[7]/G[7]

Y₀[10]

Y₀[11]

Y₁[10]

Y₁[11]

Cb[10]

Cb[11]

Y₀[10]

Y₀[11]

Cr[10] Y₁[10]

Cr[11] Y₁[11]

G[7]

Y[7]

Cr[0]/R[0]

Cr[1]/R[1]

Cr[2]/R[2]

Cr[3]/R[3]

Cr[4]/R[4]

Cr[5]/R[5]

Cr[6]/R[6]

Cr[7]/R[7]

R[0]

R[1]

R[2]

R[3]

R[4]

R[5]

R[6]

R[7]

Cr[0]

Cr[1]

Cr[2]

Cr[3]

Cr[4]

Cr[5]

Cr[6]

Cr[7]

Cb[4]

Cb[5]

Cb[6]

Cb[7]

Cb[8]

Cb[9]

Cr[4]

Cr[5]

Cr[6]

Cr[7]

Cr[8]

Cr[9]

L

Cb[10] Cr[10]

Cb[11] Cr[11]

9.1 Timing parameters for video supported

TDA19989AET supports all EIA/CEA-861B standards and ATSC video input formats.

Table 24. Timing parameters for EIA/CEA-861B

EIA/CEA-861b

Video code

Format

V frequency H total

(Hz)

V total

H frequency Pixel

Pixel

repetition

(kHz)

frequency

(MHz)

59.94 Hz systems

1 (VGA)

640 × 480p

720 × 480p

1280 × 720p

1920 × 1080i

1440 × 480i

1440 × 240p

2880 × 480i

2880 × 240p

1440 × 480p

1920 × 1080p

59.9401

60.000

800

525

750

1125

525

262

263

525

262

263

525

1125

31.469

44.955

33.716

15.734

31.469

67.432

25.175

27.000

74.175

27.000

54.000

148.350

1

2, 3

858

1

4

1650

2200

1716

3452

1716

2200

1

5

1

6, 7 (NTSC)

2

8, 9

2

8, 9

2

10, 11

4^[1]

2

12, 13

14, 15

16

1

60 Hz systems

1 (VGA)

640 × 480p

720 × 480p

1280 × 720p

1920 × 1080i

1440 × 480i

1440 × 240p

60.000

800

525

750

1125

525

262

263

31.500

45.000

33.750

15.750

25.200

27.027

74.250

27.027

1

2

2, 3

858

4

1650

2200

1716

5

6, 7 (NTSC)

8, 9

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Table 24. Timing parameters for EIA/CEA-861B …continued

EIA/CEA-861b

Video code

Format

V frequency H total

(Hz)

V total

H frequency Pixel

Pixel

repetition

(kHz)

frequency

(MHz)

10, 11

2880 × 480i

2880 × 240p

1440 × 480p

1920 × 1080p

60.000

3452

1716

2200

525

262

263

525

1125

15.750

31.500

67.500

54.054

148.50

4^[1]

2

12, 13

14, 15

16

1

50 Hz systems

17, 18

720 × 576p

1280 × 720p

1920 × 1080i

1440 × 576i

1440 × 288p

2880 × 576i

2880 × 288p

720 × 288p

1440 × 576p

1920 × 1080p

50.000

864

625

750

1125

625

312

313

314

625

312

313

314

625

1125

31.250

37.500

28.125

15.625

31.250

56.250

27.000

74.250

27.000

54.000

148.50

1

19

1980

2640

1728

3456

1728

2640

1

20

1

21, 22 (PAL)

2

23, 24

2

23, 24

2

23, 24

2

25, 26

4^[1]

4

27, 28

29, 30

2

31

1

Various systems

32

33

34

1920 × 1080p

23.976

24

2750

2640

2200

1125

26.973

27

74.175824

74.25

1

25

28.125

33.716

33.75

74.25

29.97

30

74.175824

74.25

[1] Format can also be defined with a repetition factor of up to 10.

Table 25. Timing parameters for ATSC DTV standards, which are not defined in EIA/CEA-861B

Standard

Format

V frequency H total

(Hz)

V total

H frequency Pixel

Pixel

repetition

(kHz)

frequency

(MHz)

74.250

74.175

74.250

74.175

SMPTE-296M

1280 × 720p

30.000

29.970

25.000

23.976

3300

3960

4125

750

22.500

22.478

18.750

17.982

1

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HDMI 1.4 transmitter with HDCP and CEC support

9.2 Timing parameters for PC standards supported

TDA19989AET can support all major PC Standards up to 150 MHz.

Table 26. Timing parameters for PC standards below 150 MHz

Standard

Format

V frequency H total

(Hz)

V total

H frequency

(kHz)

Pixel frequency Pixel

(MHz)

repetition

640 × 350p

640 × 400p

720 × 400p

640 × 480p

800 × 600p

848 × 480p

1024 × 768p

1024 × 768i

85.080

85.039

59.940

72.809

75.000

85.008

56.250

60.317

72.188

75.000

85.061

119.972

60.000

60.004

70.069

75.029

84.997

86.957

119.989

75.000

59.995

119.798

59.870

74.893

84.837

59.910

119.909

59.810

74.934

84.880

60.000

85.002

832

445

446

525

520

500

509

625

628

666

625

631

636

517

806

800

808

817

813

900

790

813

798

805

809

823

847

831

838

843

1000

1011

1066

795

813

37.861

37.927

31.469

37.861

37.500

43.269

35.156

37.879

48.077

46.875

53.674

76.302

31.020

48.363

56.476

60.023

68.677

35.522

97.551

67.500

47.396

97.396

47.776

60.289

68.633

49.306

101.563

49.702

62.795

71.554

60.000

85.938

63.981

79.976

47.712

97.533

31.500

35.500

25.175

31.500

36.000

40.000

50.000

49.500

56.250

73.250

33.750

65.000

75.000

78.750

94.500

44.900

115.500

108.000

68.250

140.250

79.500

102.250

117.500

71.000

146.250

83.500

106.500

122.500

108.000

148.500

108.000

135.000

85.500

148.250

-

832

936

0.31M3 VGA

800

832

840

832

0.48M3 SVGA

1024

1056

1040

1056

1048

960

0.48M3-R

0.41M9

1088

1344

1328

1312

1376

1264

1184

1600

1440

1664

1696

1712

1440

1680

1696

1712

1800

1728

1688

1792

1520

0.79M3 XGA

0.79M3-R XGA 1024 × 768p

1.00M3

1152 × 864p

1280 × 768p

1280 × 800p

1280 × 960p

0.98M9-R

0.98M9

1.02MA-R

1.02MA

1.23M3

1.31M4 SXGA

1280 × 1024p 60.020

1280 × 1024p 75.025

1.04M9

1360 × 768p

60.015

1.04M9-R

119.967

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Table 26. Timing parameters for PC standards below 150 MHz …continued

Standard

Format

V frequency H total

(Hz)

V total

H frequency

(kHz)

Pixel frequency Pixel

(MHz)

repetition

1.47M3-R

1.47M3

1400 × 1050p 59.948

1400 × 1050p 59.978

1560

1864

1600

1904

1936

1840

2240

1080

1089

926

64.744

65.317

55.469

55.935

70.635

64.674

65.290

101.000

121.750

88.750

-

1.29MA-R

1.29MA

1440 × 900p

59.901

59.887

74.984

934

106.500

136.750

119.000

146.250

942

1.76MA-R

1.76MA

1680 × 1050p 59.883

1680 × 1050p 59.954

1080

1089

10. Limiting values

Table 27. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions

V_{DDA(TMDS)(1V8)}TMDS analog supply voltage (1.8 V)

Min

Max

+2.5

+2

Unit

V

−0.5

−2

V_{DDA(PLL)(1V8)}

V_DDA(1V8)

V_DDD(IO)(1V8)

V_DDDC

PLL analog supply voltage (1.8 V)

analog supply voltage (1.8 V)

I/O digital supply voltage (1.8V)

core digital supply voltage

V

ΔV_DD

supply voltage difference

V

[1]

[2]

V_ESD

electrostatic discharge voltage

EIA/JESD22-A114 (HBM)

−2500 +2500

V

EIA/JESD22-C101-C (FCDM)

1000

-

V

[1] On TMDS outputs.

[2] It withstands class III of JEDEC classification.

11. Thermal characteristics

Table 28. Thermal characteristics

Symbol

R_th(j-a)

R_th(j-c)

T_stg

Parameter

Conditions

Min Typ

Max

-

Unit

K/W

°C

thermal resistance from junction to ambient

thermal resistance from junction to case

storage temperature

in free air; JEDEC 4L board

-

56.9

-

15.1

-

+150

+85

+125

T_amb

T_j

ambient temperature

−20

°C

junction temperature

-

°C

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12. Static characteristics

Table 29. Supplies

T_amb= −20 °C to +85 °C; without HDCP; unless otherwise specified.

Symbol

V_DDDC

Parameter

Conditions

Min

1.7

15

Typ

1.8

19

Max

1.9

22

Unit

V

[1]

core digital supply voltage

V_{DDA(TMDS)(1V8)}TMDS analog supply voltage (1.8 V)

V

V_{DDA(PLL)(1V8)}

V_DDA(1V8)

V_DDD(IO)(1V8)

I_{DDA(sum)(1V8)}

PLL analog supply voltage (1.8 V)

analog supply voltage (1.8 V)

I/O digital supply voltage (1.8V)

sum analog supply current (1.8 V)

V

[2]

I_{DDA(sum)(1V8)}

=

mA

I_{DDA(TMDS)(1V8)}+ I_DDA(1V8)

[2]

I_{DDA(PLL)(1V8)}

I_DDD(IO)(1V8)

PLL analog supply current (1.8 V)

-

6

9

mA

input/output digital supply current

(1.8 V)

40

60

μA

[2]

[3]

[2]

[3]

I_DDDC(1V8)

core digital supply current (1.8 V)

-

52

72

mA

32

40

mA

P_cons

power consumption

140

90

230

115

4.5

4

mW

μW

Sleep mode with CEC

Sleep mode without CEC

Standby mode

1.8

1.5

400

252

202

650

300

260

[4]

[5]

P_tot

total power dissipation

mW

[1] see Table 6.

[2] Input format: 1080p, any color space; output format: 1080p any color space: 30 % activity on video input ports.

[3] Input format: 1080i YCbCr 4 : 2 : 2; output format: YCbCr 4 : 2 : 2; CEC feature disable: 30 % activity on video input ports.

[4] Same as Table note [2] with TMDS output current added.

[5] Same as Table note [3] with TMDS output current added.

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Table 30. Digital inputs and outputs

T_amb= −20 °C to +85 °C; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Not 5 V tolerant CMOS 1.8 V and CMOS 3.3 V tolerant digital input pins HSYNC, VSYNC, APn, ACLK, VPA[n],

VPB[n], VPC[n], VCLK, DE

V_IL

V_IH

I_IL

LOW-level input voltage

HIGH-level input voltage

LOW-level input current

HIGH-level input current

input capacitance

-

0

-

0.75

-

V

1.4

−2

-

V

-

+2

-

μA

pF

I_IH

C_i

-

4.5

5 V tolerant input pin HPD

V_IL

V_IH

C_i

LOW-level input voltage

-

0

2

-

0.8

V

HIGH-level input voltage

input capacitance

-

V

4.5

pF

CMOS 1.8 V and CMOS 3.3 V tolerant digital input/output pin INT

V_IL

LOW-level input voltage

HIGH-level input voltage

-

0

-

0.85

-

V

V_IH

1.4

0

V_OL

LOW-level output voltage C_L= 10 pF; I_OL= 2 mA

0.4

5 V tolerant master bus: DDC-bus pins DSDA, DSCL^[1]

V_OL

V_IL

LOW-level output voltage

LOW-level input voltage

HIGH-level input voltage

0

-

0.4

0.6

5.5

V

0

V_IH

1.4

1.8 V to 3.3 V tolerant slave bus: I²C-bus input/output pins CSCL, CSDA^[1]

V_OL

V_IL

LOW-level output voltage

LOW-level input voltage

HIGH-level input voltage

0

-

0.4

0.6

5.5

V

0

V_IH

1.4

CEC input/output^[2]pin

V_OL

V_OH

V_IL

LOW-level output voltage

0

-

0.4

3.6

0.60

3.6

-

V

HIGH-level output voltage

LOW-level input voltage

HIGH-level input voltage

input hysteresis voltage

2.5

0

-

V_IH

2.5

-

[2]

V_hys(i)

0.27

TMDS output pins: TX0−, TX0+, TX1−, TX1+, TX2−, TX2+, TXC− and TXC+

V_O(dif)differential output voltage R_{EXT_SWING}= 10 kΩ ± 1 %

400

505

600

mV

[1] See Section 7.1 and refer to the I²C-bus specification version 2.1 (document order number 9398 393 40011).

[2] For information, input hysteresis is normally supplied by the microprocessor input circuit: in this circumstance, external hysteresis

circuitry is not needed.

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13. Dynamic characteristics

Table 31. Timing characteristics

T_amb= −20 °C to +85 °C; unless otherwise specified.

Symbol Parameter

Clock input: pin VCLK

Conditions

Min

Typ

Max

Unit

f_clk(max)

t_su(D)

t_h(D)

maximum clock frequency

-

148.5

MHz

ns

data input set-up time

data input hold time

clock duty cycle

see Figure 18 and 19

1.6

1.2

30

-

ns

[1]

δ_clk

50

12

70

-

%

f_clk

clock frequency

CEC

MHz

DDC-bus: pins DSDA, DSCL (5 V tolerant) master bus^[2]

f_SCL

SCL frequency

Standard mode

-

100

-

kHz

pF

C_i

capacitance for each I/O pin

7

I²C-bus: pins CSCL, CSDA (5 V tolerant) slave bus^[2]

f_SCL

SCL frequency

Standard mode

Fast mode

CEC

-

100

400

-

kHz

μs

-

t_stretch

stretch time

80

CEC input/output^[3]

t_r

t_f

rise time

fall time

10 % to 90 %

-

50

2

μs

TMDS output pins: TXC− and TXC+

f_clk(max)maximum clock frequency

on the TMDS link

-

148.5

1.485

MHz

GHz

TMDS output pins: TX0−, TX0+, TX1−, TX1+, TX2− and TX2+

f_clk(max)maximum clock frequency

[1]

δ_clk= t_clk(H)/ (t_clk(H)+ t_clk(L)).

[2] See Section 7.1 and refer to the I²C-bus specification version 2.1 (document order number 9398 393 40011).

[3] For details about CEC electrical specification, see HDMI 1.4 specification.

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EDGE = 0

VCLK

VPA[0] to VPA[7]

VPB[0] to VPB[7]

VPC[0] to VPC[7]

DE, HSYNC, VSYNC

t

h(D)

su(D)

EDGE = 1

VCLK

VPA[0] to VPA[7]

VPB[0] to VPB[7]

VPC[0] to VPC[7]

DE, HSYNC, VSYNC

t

h(D)

su(D)

data is not allowed to change in this period

data can change to meet the minimum set-up and hold time requirement

001aah035

Fig 18. Set-up and hold time definition diagram for single-edge clock mode

VCLK

VPA[0] to VPA[7]

VPB[0] to VPB[7]

VPC[0] to VPC[7]

DE, HSYNC, VSYNC

t

h(D)

su(D)

h(D)

su(D)

data is not allowed to change in this period

data can change to meet the minimum set-up and hold time requirement

001aah036

Fig 19. Set-up and hold time definition diagram for double-edge clock mode

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14. Application information

14.1 Transmitter connection with external world

Figure 20 and Figure 21 refer to a simple receiver application. However, TDA19989AET

can be part of a repeater application as described in “HDMI specification 1.4”.

TRANSMITTER SIDE

DOWNSTREAM SIDE

2

I C-bus

TMDS channel 0

TMDS channel 1

TMDS channel 2

TMDS clock

video 24-bit

MASTER

MAIN

PROCESSOR

2

sync

I C-BUS

SLAVE

audio

HDMI

RECEIVER/

REPEATER

TDA19989

HPD

12 MHz

EXTERNAL

CLOCK

DDC-bus channel

DDC-BUS

MASTER

SLAVE

CEC

001aal261

Fig 20. Connecting TDA19989AET transmitter using external clock source

TRANSMITTER SIDE

DOWNSTREAM SIDE

2

I C-bus

TMDS channel 0

TMDS channel 1

TMDS channel 2

TMDS clock

video 24-bit

MASTER

MAIN

PROCESSOR

2

sync

I C-BUS

SLAVE

audio

HDMI

RECEIVER/

REPEATER

TDA19989

HPD

DDC-bus channel

DDC-BUS

MASTER

SLAVE

CEC

001aal262

Fig 21. Connecting TDA19989AET transmitter using internal FRO for CEC

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HDMI 1.4 transmitter with HDCP and CEC support

15. Package outline

TFBGA64: plastic thin fine-pitch ball grid array package; 64 balls

SOT962-3

D

B

A

ball A1

index area

A

2

E

A

1

detail X

e

1

1/2 e

C

M

∅ v

∅ w

C A

C

B

e

b

y

1

y

C

H

e

G

F

E

D

C

B

A

e

2

1/2 e

ball A1

index area

1

2

3

4

5

6

7

8

X

0

2.5

scale

5 mm

DIMENSIONS (mm are the original dimensions)

UNIT

A

1

A

2

b

D

E

e

1

e

2

v

w

y

1

max 1.10 0.30 0.80 0.35

nom 0.95 0.25 0.70 0.30

4.6

4.5

4.4

4.6

4.5

4.4

mm

0.5

3.5

0.15 0.05 0.08

0.1

min

0.85 0.20 0.65 0.25

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

08-05-26

08-06-18

SOT962-3

- - -

Fig 22. Package outline SOT962-3 (TFBGA64)

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16. Abbreviations

Table 32. Abbreviations

Acronym

AC3

Description

Active Coding-3

ACP

Audio Content Protection

Audio Clock Recovery

ACR

ATSC

AV

Advanced Television Systems Committee

Audio Video

BOM

CEA

Bill Of Materials

Consumer Electronics Association

Consumer Electronics Control

Clock Time Stamp integer divider

Display Data Channel

CEC

CTS/N

DDC

DDR

DE

Double Data Rate

Data Enable

DSC

Digital Still Camera

DTS

Digital Transmission System

Desk Top Video

DTV

DVC

Digital Video Camera

DVD

Digital Versatile Disc

DVI

Digital Visual Interface

EAV

End Active Video

EDID

E-EDID

EIA

Extended Display Identification Data

Enhanced Extended Display Identification Data

Electronic Industries Alliance

Field Charged Device Model

First In, First Out

FCDM

FIFO

FREF

FRO

Field REFerence

Free Running Oscillator

Human Body Model

HBM

HDCP

HDMI

HPD

High-bandwidth Digital Content Protection

High-Definition Multimedia Interface

Hot Plug Detection

HREF

HSYNC

LSB

Horizontal REFerence

Horizontal SYNChronization

Least Significant Bit

LV-CMOS

MPEG

MSB

OTP

Low Voltage Complementary Metal-Oxide Semiconductor

Moving Picture Experts Group

Most Significant Bit

One Time Programming

Personal Computer

PC

PCB

Printed Circuit Board

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HDMI 1.4 transmitter with HDCP and CEC support

Table 32. Abbreviations …continued

Acronym Description

PCM

Pulse Code Modulation

PLL

Phase-Locked Loop

PMP

Portable Multimedia Player

Power-On Reset

POR

RGB

R = red, G = green, B = blue

Start Active Video

SAV

SDR

Single Data Rate

SMPTE

S/PDIF

STB

Society of Motion Picture and Television Engineers

Sony/Philips Digital Interface

Set-Top Box

TMDS

UM PC

UXGA60

VHREF

VREF

VSYNC

YCbCr

WS

Transition Minimized Differential Signalling

Ultra-Mobile Personal Computer

Ultra Extended Graphics Array

Vertical Horizontal REFerence

Vertical REFerence

Vertical SYNChronization

Y = luminance, Cb = Chroma component blue, Cr = Chroma component red

Word Select

17. Revision history

Table 33. Revision history

Document ID

TDA19989AET_2

Modifications:

Release date

20100518

Data sheet status

Change notice

Supersedes

Product data sheet

-

TDA19989_1

• Renamed TDA19989 by TDA19989AET

• All document: replaced HDMI 1.3 by HDMI 1.4

• Section 7.6: updated

• Table 19: updated

• Table 29: updated

• Table 31: updated

TDA19989_1

20100215

Preliminary data sheet

-

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HDMI 1.4 transmitter with HDCP and CEC support

18. Legal information

18.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

malfunction of an NXP Semiconductors product can reasonably be expected

18.2 Definitions

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

18.3 Disclaimers

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

TDA19989AET_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 18 May 2010

43 of 46

TDA19989AET

NXP Semiconductors

HDMI 1.4 transmitter with HDCP and CEC support

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

18.4 Licenses

Purchase of NXP ICs with HDMI technology

Use of an NXP IC with HDMI technology in equipment that complies with

the HDMI standard requires a license from HDMI Licensing LLC, 1060 E.

Arques Avenue Suite 100, Sunnyvale CA 94085, USA, e-mail:

admin@hdmi.org.

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

18.5 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

I²C-bus — logo is a trademark of NXP B.V.

19. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

TDA19989AET_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 18 May 2010

44 of 46

TDA19989AET

NXP Semiconductors

HDMI 1.4 transmitter with HDCP and CEC support

20. Tables

Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .3

Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5

Table 3. Internal assignment . . . . . . . . . . . . . . . . . . . . . .8

Table 4. Video input swap to VP[23:20] . . . . . . . . . . . . .10

Table 5. TDA19989AET input/output capability . . . . . . .11

Table 6. Inputs of video input formatter . . . . . . . . . . . . .12

Table 7. RGB (3 ´ 8-bit) external synchronization input

(rising edge) mapping . . . . . . . . . . . . . . . . . . .13

Table 8. YCbCr 4 : 4 : 4 (3 ´ 8-bit) external

synchronization input (rising edge) mapping . .13

Table 9. YCbCr 4 : 2 : 2 ITU656-like external

synchronization input (rising edge) mapping . .14

Table 10. YCbCr 4 : 2 : 2 ITU656-like external

synchronization input (double edge) mapping .15

Table 11. YCbCr 4 : 2 : 2 ITU656-like embedded

synchronization input (rising edge) mappings .15

Table 12. YCbCr 4 : 2 : 2 ITU656-like embedded

synchronization input (double edge) mapping .16

Table 13. YCbCr 4 : 2 : 2 semi-planar external

synchronization input (rising edge) mapping . .17

Table 14. YCbCr 4 : 2 : 2 semi-planar embedded

synchronization input (rising edge) mapping . .17

Table 15. Use of color space converter, upsampler and

downsampler . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 16. Audio port configuration . . . . . . . . . . . . . . . . . 20

Table 17. TDA19989AET typical power consumption in

different configurations . . . . . . . . . . . . . . . . . . 22

Table 18. Interruptions . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 19. Receiver detection according to averaged

terminal voltage . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 20. Pixel repetition . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 21. HDMI core I²C-bus address . . . . . . . . . . . . . . 29

Table 22. CEC core I²C-bus address . . . . . . . . . . . . . . . 29

Table 23. Input format . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 24. Timing parameters for EIA/CEA-861B . . . . . . 31

Table 25. Timing parameters for ATSC DTV standards,

which are not defined in EIA/CEA-861B . . . . . 32

Table 26. Timing parameters for PC standards below

150 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 27. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 28. Thermal characteristics . . . . . . . . . . . . . . . . . . 34

Table 29. Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 30. Digital inputs and outputs . . . . . . . . . . . . . . . . 36

Table 31. Timing characteristics . . . . . . . . . . . . . . . . . . . 37

Table 32. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 33. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 42

21. Figures

Fig 1. TDA19989AET high-level block diagram. . . . . . . .2

Fig 2. TDA19989AET Block diagram. . . . . . . . . . . . . . . .4

Fig 3. Pin configuration (TFBGA64). . . . . . . . . . . . . . . . .5

Fig 4. Internal assignment of VP[23:0]. . . . . . . . . . . . . . .8

Fig 5. Pixel encoding RGB 4 : 4 : 4 external

Fig 19. Set-up and hold time definition diagram for

double-edge clock mode. . . . . . . . . . . . . . . . . . . 38

Fig 20. Connecting TDA19989AET transmitter using

external clock source . . . . . . . . . . . . . . . . . . . . . 39

Fig 21. Connecting TDA19989AET transmitter using

internal FRO for CEC . . . . . . . . . . . . . . . . . . . . . 39

Fig 22. Package outline SOT962-3 (TFBGA64) . . . . . . . 40

synchronization input (rising edge) . . . . . . . . . . .13

Fig 6. Pixel encoding YCbCr 4 : 4 : 4 external

synchronization input (rising edge) . . . . . . . . . . .14

Fig 7. Pixel encoding YCbCr 4 : 2 : 2 ITU656-like

external synchronization input (rising edge) . . . .14

Fig 8. Pixel encoding YCbCr 4 : 2 : 2 ITU656-like

external synchronization input (double edge) . . .15

Fig 9. Pixel encoding YCbCr 4 : 2 : 2 ITU656-like

embedded synchronization input (rising edge) . .16

Fig 10. Pixel encoding YCbCr 4 : 2 : 2 ITU656-like

embedded synchronization input (double edge) .16

Fig 11. Pixel encoding YCbCr 4 : 2 : 2 semi-planar

external input synchronization (rising edge) . . . .17

Fig 12. Pixel encoding YCbCr 4 : 2 : 2 semi-planar

embedded synchronization input (rising edge) . .18

Fig 13. I²S-bus formats . . . . . . . . . . . . . . . . . . . . . . . . . .21

Fig 14. Audio input swap to I²S-bus channel 0 or

S/PDIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Fig 15. Receiver sensitivity detection . . . . . . . . . . . . . . .24

Fig 16. Modules involved in CEC clock calibration

process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Fig 17. I²C-bus access. . . . . . . . . . . . . . . . . . . . . . . . . . .29

Fig 18. Set-up and hold time definition diagram for

single-edge clock mode. . . . . . . . . . . . . . . . . . . .38

TDA19989AET_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 18 May 2010

45 of 46

TDA19989AET

NXP Semiconductors

HDMI 1.4 transmitter with HDCP and CEC support

22. Contents

1

2

3

4

5

General description. . . . . . . . . . . . . . . . . . . . . . 1

7.11.1

High-bandwidth digital content protection . . . 25

7.11.1.1 Repeater function. . . . . . . . . . . . . . . . . . . . . . 25

7.11.1.2 SHA-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.12

7.12.1

7.12.2

7.12.3

7.12.4

7.12.5

7.13

Features and benefits . . . . . . . . . . . . . . . . . . . . 2

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Ordering information. . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

CEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

CEC interrupt . . . . . . . . . . . . . . . . . . . . . . . . . 26

Power-On Reset (POR) . . . . . . . . . . . . . . . . . 27

Repeater function. . . . . . . . . . . . . . . . . . . . . . 27

HDMI core . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Output TMDS buffers. . . . . . . . . . . . . . . . . . . 27

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

7

7.1

7.2

7.2.1

7.2.2

7.2.3

7.2.3.1

Functional description . . . . . . . . . . . . . . . . . . . 7

System clock . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Video input formatter . . . . . . . . . . . . . . . . . . . . 8

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Internal assignment . . . . . . . . . . . . . . . . . . . . . 8

Input format mappings . . . . . . . . . . . . . . . . . . 12

RGB 4 : 4 : 4 external synchronization

(rising edge) . . . . . . . . . . . . . . . . . . . . . . . . . . 13

YCbCr 4 : 4 : 4 external synchronization

(rising edge) . . . . . . . . . . . . . . . . . . . . . . . . . . 13

YCbCr 4 : 2 : 2 ITU656-like external

synchronization (rising edge) . . . . . . . . . . . . . 14

YCbCr 4 : 2 : 2 ITU656-like external

synchronization (double edge) . . . . . . . . . . . . 15

YCbCr 4 : 2 : 2 ITU656-like embedded

synchronization (rising edge) . . . . . . . . . . . . . 15

YCbCr 4 : 2 : 2 ITU656-like embedded

synchronization (double edge) . . . . . . . . . . . . 16

YCbCr 4 : 2 : 2 semi-planar external

7.13.1

7.13.1.1 Digitally controlled signal amplitude. . . . . . . . 27

7.13.2

7.13.3

7.14

7.14.1

7.14.2

Pixel repetition . . . . . . . . . . . . . . . . . . . . . . . . 27

DDC-bus channel. . . . . . . . . . . . . . . . . . . . . . 27

E-EDID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

E-EDID reading . . . . . . . . . . . . . . . . . . . . . . . 28

HDMI and DVI receiver discrimination. . . . . . 28

I²C-bus interface and register definitions. . . 29

I²C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 29

Memory page management. . . . . . . . . . . . . . 29

ID version. . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Clock stretching . . . . . . . . . . . . . . . . . . . . . . . 30

8

7.2.3.2

7.2.3.3

7.2.3.4

7.2.3.5

7.2.3.6

7.2.3.7

7.2.3.8

8.1

8.2

8.3

8.4

9

9.1

9.2

Input format . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Timing parameters for video supported . . . . . 31

Timing parameters for PC standards

supported. . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

10

11

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 34

Thermal characteristics . . . . . . . . . . . . . . . . . 34

Static characteristics . . . . . . . . . . . . . . . . . . . 35

Dynamic characteristics. . . . . . . . . . . . . . . . . 37

Application information . . . . . . . . . . . . . . . . . 39

Transmitter connection with external world . . 39

Package outline. . . . . . . . . . . . . . . . . . . . . . . . 40

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 41

Revision history . . . . . . . . . . . . . . . . . . . . . . . 42

synchronization (rising edge) . . . . . . . . . . . . . 17

YCbCr 4 : 2 : 2 semi-planar embedded

12

13

14

14.1

15

16

17

synchronization (rising edge) . . . . . . . . . . . . . 17

Synchronization . . . . . . . . . . . . . . . . . . . . . . . 18

Timing extraction generator . . . . . . . . . . . . . . 18

Data enable generator . . . . . . . . . . . . . . . . . . 18

Input and output video format. . . . . . . . . . . . . 18

Upsampler . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Color space converter. . . . . . . . . . . . . . . . . . . 19

Gamut-related metadata. . . . . . . . . . . . . . . . . 19

Downsampler . . . . . . . . . . . . . . . . . . . . . . . . . 19

Audio input format . . . . . . . . . . . . . . . . . . . . . 19

S/PDIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

I²S-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Audio port internal assignment. . . . . . . . . . . . 22

Power management . . . . . . . . . . . . . . . . . . . . 22

Interrupt controller . . . . . . . . . . . . . . . . . . . . . 23

Hot plug/unplug detect . . . . . . . . . . . . . . . . . . 23

Receiver sensitivity. . . . . . . . . . . . . . . . . . . . . 23

HDCP processing. . . . . . . . . . . . . . . . . . . . . . 25

7.2.4

7.2.4.1

7.2.4.2

7.3

7.4

7.5

7.6

7.7

7.8

7.8.1

7.8.2

7.8.3

7.9

7.10

7.10.1

7.10.2

7.11

18

Legal information . . . . . . . . . . . . . . . . . . . . . . 43

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 43

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 44

18.1

18.2

18.3

18.4

18.5

19

20

21

22

Contact information . . . . . . . . . . . . . . . . . . . . 44

Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 18 May 2010

Document identifier: TDA19989AET_2


型号：	TDA19989AET/C101,5
厂家：	NXP
描述：	IC IC,TV/VIDEO CIRCUIT,AUDIO/VIDEO DECODER FOR MPEG,BGA,64PIN,PLASTIC, Consumer IC:Other 商用集成电路电视
文件：	总46页 (文件大小：339K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TDA19989AET/C101,5 [NXP]

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