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TDA6502TS/C1 [NXP]

IC 2-BAND, VIDEO TUNER, PDSO28, PLASTIC, SOT-341, SSOP-28, Tuner IC;
TDA6502TS/C1
型号： TDA6502TS/C1
厂家： NXP    NXP
描述：

IC 2-BAND, VIDEO TUNER, PDSO28, PLASTIC, SOT-341, SSOP-28, Tuner IC

光电二极管
文件： 总48页 (文件大小：242K)
中文：  中文翻译
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INTEGRATED CIRCUITS  
DATA SHEET  
TDA6502; TDA6502A; TDA6503;  
TDA6503A  
5 V mixers/oscillators and  
synthesizers for cable TV and VCR  
2-band tuners  
Product specification  
2000 Aug 02  
Supersedes data of 2000 Mar 16  
File under Integrated Circuits, IC02  
Philips Semiconductors  
Product specification  
5 V mixers/oscillators and synthesizers for  
cable TV and VCR 2-band tuners  
TDA6502; TDA6502A;  
TDA6503; TDA6503A  
CONTENTS  
14  
INTERNAL PIN CONFIGURATION  
15  
PACKAGE OUTLINE  
SOLDERING  
1
2
3
FEATURES  
16  
APPLICATIONS  
16.1  
Introduction to soldering surface mount  
packages  
Reflow soldering  
Wave soldering  
Manual soldering  
GENERAL DESCRIPTION  
I2C-bus format  
3-wire bus format  
3.1  
3.2  
16.2  
16.3  
16.4  
16.5  
4
5
6
7
8
QUICK REFERENCE DATA  
ORDERING INFORMATION  
BLOCK DIAGRAM  
Suitability of surface mount IC packages for  
wave and reflow soldering methods  
17  
18  
19  
20  
DATA SHEET STATUS  
DEFINITIONS  
PINNING  
FUNCTIONAL DESCRIPTION  
DISCLAIMERS  
PURCHASE OF PHILIPS I2C COMPONENTS  
8.1  
8.2  
Control mode selection  
I2C-bus data format: pin SW to ground  
I2C-bus address selection  
Write mode  
Read mode  
Power-on reset  
8.2.1  
8.2.2  
8.2.3  
8.2.4  
8.3  
3-wire bus data format: pin SW to VCC or  
open-circuit  
8.3.1  
9
Power-on reset  
LIMITING VALUES  
10  
11  
12  
13  
THERMAL CHARACTERISTICS  
CHARACTERISTICS  
TIMING CHARACTERISTICS  
TEST AND APPLICATION INFORMATION  
13.1  
13.2  
13.3  
13.4  
13.5  
Test circuits  
Measurement circuit  
Tuning amplifier  
Crystal oscillator  
Examples of I2C-bus data format sequences for  
TDA6502 and TDA6503  
Write sequences to register C2  
Read sequences from register C3  
Examples of 3-wire bus data format sequences  
for TDA6502 and TDA6503  
18-bit sequence  
13.5.1  
13.5.2  
13.6  
13.6.1  
13.6.2  
13.6.3  
19-bit sequence  
27-bit sequence  
2000 Aug 02  
2
Philips Semiconductors  
Product specification  
5 V mixers/oscillators and synthesizers for  
cable TV and VCR 2-band tuners  
TDA6502; TDA6502A;  
TDA6503; TDA6503A  
1
FEATURES  
• Single-chip 5 V mixer/oscillator and synthesizer for  
cable TV and VCR tuners  
• Pin-to-pin compatible with TDA6402, TDA6402A,  
TDA6403 and TDA6403A  
• Universal bus protocol (I2C-bus or 3-wire bus):  
– Bus protocol for 18 or 19-bit transmission (3-wire  
bus)  
2
APPLICATIONS  
• Cable tuners for TV and VCR (switched concept for  
– Extra protocol for 27-bit transmission (test modes and  
features for 3-wire bus)  
VHF).  
– Address + 4 data bytes transmission (I2C-bus ‘write’  
mode)  
3
GENERAL DESCRIPTION  
The TDA6502, TDA6502A, TDA6503 and TDA6503A are  
programmable 2-band mixers/oscillators and synthesizers  
intended for VHF/UHF TV and VCR tuners (see Fig.1).  
– Address + 1 status byte (I2C-bus ‘read’ mode)  
– 4 independent I2C-bus addresses.  
• 1 PMOS buffer for UHF band selection (25 mA)  
Partitioning of the bands is up to the customer as long as  
VHF is below 500 MHz and UHF is below 900 MHz.  
• 3 PMOS buffers for general purpose, e.g. 2 VHF  
sub-bands, FM sound trap (25 mA)  
The devices include two double balanced mixers and two  
oscillators for the VHF and UHF band respectively, an  
IF amplifier and a PLL synthesizer. The VHF band can be  
split-up into two sub-bands using a proper oscillator  
application and a switchable inductor.  
• 33 V tuning voltage output  
• In-lock detector  
• 5-step analog-to-digital converter (3 bits in I2C-bus  
mode)  
• 15-bit programmable divider  
Two pins are available between the mixer output and the  
IF amplifier input to enable IF filtering for improved signal  
handling.  
• Programmable reference divider ratio (64, 80 or 128)  
• Programmable charge pump current (60 or 280 µA)  
• Varicap drive disable  
The port register provides four PMOS ports. Band  
selection is provided by port register UHF. When port  
register UHF is ‘on’, the UHF mixer-oscillator is active and  
the VHF band is switched off. When port register UHF is  
‘off’, the VHF mixer-oscillator is active and the UHF band  
is off. Port registers VHFL and VHFH are used to select  
the VHF sub-bands. Port register FMST is a general  
purpose port, that can be used to switch an FM sound trap.  
When the ports are used, the sum of the drain currents has  
to be limited to 30 mA.  
• Balanced mixer with a common emitter input for VHF  
(single input)  
• Balanced mixer with a common base input for UHF  
(balanced input)  
• 2-pin common emitter oscillator for VHF  
• 4-pin common emitter oscillator for UHF  
• IF preamplifier with asymmetrical 75 Ω output  
impedance able to drive loads from 75 Ω upwards  
The synthesizer consists of a 15-bit programmable divider,  
a crystal oscillator and its programmable reference divider  
and a phase comparator (phase/frequency detector)  
combined with a charge pump which drives the tuning  
amplifier, including the 33 V output at pin VT. Depending  
on the reference divider ratio (64, 80 or 128), the phase  
comparator operates at 62.5, 50 or 31.25 kHz with a  
4 MHz crystal.  
• Low power  
• Low radiation  
• Small size  
• The TDA6502A and TDA6503A differ from the TDA6502  
and TDA6503 by the UHF port protocol in the I2C-bus  
mode (see Tables 3 and 4).  
2000 Aug 02  
3
Philips Semiconductors  
Product specification  
5 V mixers/oscillators and synthesizers for  
cable TV and VCR 2-band tuners  
TDA6502; TDA6502A;  
TDA6503; TDA6503A  
Depending on the voltage applied to pin SW (see Table 2)  
the device is operating in the I2C-bus mode or 3-wire bus  
mode.  
3.2  
3-wire bus format  
Data is transmitted to the device during a HIGH level on  
pin CE/AS (enable line). The device is accessible with  
18-bit and 19-bit data formats (see Figs 4 and 5). The first  
four bits are used to program the PMOS ports and the  
remaining bits control the programmable divider. A 27-bit  
data format (see Fig.6) may also be used to set the charge  
pump current, the reference divider ratio and the test  
modes.  
In the 3-wire bus mode, pin LOCK/ADC is the ‘lock’ output  
of the PLL and is at LOW level when the PLL is locked.  
Lock detector bit FL of the status byte is set to logic 1 when  
the loop is locked and is read on the SDA line during a  
READ operation in I2C-bus mode only.  
In the I2C-bus mode only, pin LOCK/ADC is the ADC input  
for digital AFC control. The ADC code is read during a  
READ operation on the I2C-bus.  
It is not allowed to address the device with words whose  
length is different from 18, 19 or 27 bits.  
In the test mode, in both I2C-bus mode and 3-wire bus  
mode, pin LOCK/ADC is used as a test output for fREF and  
Table 1 Data word length for 3-wire bus format  
1⁄2fDIV  
.
REFERENCE  
DIVIDER(1)  
FREQUENCY  
STEP  
DATA WORD  
3.1  
I2C-bus format  
18-bit  
19-bit  
27-bit  
64  
128  
62.50 kHz  
31.25 kHz  
Five serial bytes (including the address byte) are required  
to address the device, select the VCO frequency, program  
the four ports, set the charge pump current and set the  
reference divider ratio. The device has four independent  
I2C-bus addresses which can be selected by applying a  
specific voltage to pin CE/AS.  
programmable  
programmable  
Note  
1. The selection of the reference divider is given by an  
automatic identification of the data word length. When  
the 27-bit format is used, the reference divider is  
controlled by bits RSA and RSB (see Table 8). More  
details are given in Section 8.3.  
2000 Aug 02  
4
Philips Semiconductors  
Product specification  
5 V mixers/oscillators and synthesizers for  
cable TV and VCR 2-band tuners  
TDA6502; TDA6502A;  
TDA6503; TDA6503A  
4
QUICK REFERENCE DATA  
Measured over full voltage and temperature ranges.  
SYMBOL PARAMETER  
VCC supply voltage  
CONDITIONS  
operating  
MIN.  
4.5  
TYP. MAX. UNIT  
5
5.5  
V
ICC  
supply current  
all PMOS ports are off;  
VCC = 5V  
−
71  
−
mA  
fXTAL  
Io(PMOS)  
Ptot  
crystal oscillator frequency  
PMOS port output current  
total power dissipation  
IC storage temperature  
ambient temperature  
RF frequency  
−
4.0  
−
−
MHz  
mA  
note 1  
note 2  
−
30  
520  
−
−
mW  
Tstg  
−40  
−20  
40  
200  
−
−
+150 °C  
Tamb  
fRF  
−
+85  
800  
900  
−
°C  
VHF band  
UHF band  
VHF band  
UHF band  
VHF band  
UHF band  
VHF band  
UHF band  
−
MHz  
MHz  
dB  
−
GV  
NF  
Vo  
voltage gain  
noise figure  
20  
32  
7.5  
7
−
−
dB  
−
−
dB  
−
−
dB  
output voltage (causing 1% cross  
modulation in channel)  
−
110  
110  
−
dBµV  
dBµV  
−
−
Notes  
1. One buffer ‘on’, Io = 25 mA; two buffers ‘on’, maximum sum of Io = 30 mA.  
2. The power dissipation is calculated as follows:  
(0.5 × 33V)2  
Ptot = VCC × (ICC – Io) + VP(sat) × I +  
--------------------------------  
o
22 kΩ  
where:  
VP(sat) = output saturation voltage on the buffer output  
Io = source current for one buffer output.  
5
ORDERING INFORMATION  
TYPE  
PACKAGE  
NUMBER  
NAME  
DESCRIPTION  
VERSION  
TDA6502  
SSOP28  
plastic shrink small outline package; 28 leads; body width 5.3 mm  
SOT341-1  
TDA6502A  
TDA6503  
TDA6503A  
2000 Aug 02  
5
Philips Semiconductors  
Product specification  
5 V mixers/oscillators and synthesizers for  
cable TV and VCR 2-band tuners  
TDA6502; TDA6502A;  
TDA6503; TDA6503A  
6
BLOCK DIAGRAM  
V
IFFIL1 IFFIL2  
5 (24) 6 (23)  
CC  
19 (10)  
(5) 24  
3 (26)  
VHFOSCOC  
VHFIN  
VHF  
OSCILLATOR  
RF INPUT  
VHF  
VHF  
MIXER  
(7) 22  
VHFOSCIB  
BS  
BS  
BS  
(6) 23  
OSCGND  
TDA6502  
TDA6502A  
(TDA6503)  
(TDA6503A)  
4 (25)  
(9) 20  
IF  
RFGND  
IFOUT  
PREAMPLIFIER  
(1) 28  
(2) 27  
(3) 26  
(4) 25  
UHFOSCIB2  
UHFOSCOC2  
1 (28)  
UHFIN1  
RF INPUT  
UHF  
UHF  
MIXER  
UHF  
OSCILLATOR  
2 (27)  
UHFIN2  
UHFOSCOC1  
UHFOSCIB1  
BS  
BS  
BS  
(13) 16  
(12) 17  
CP  
VT  
XTAL  
OSCILLATOR  
4 MHz  
REFERENCE  
DIVIDER  
64, 80, 128  
18 (11)  
XTAL  
f
REF  
PHASE  
COMPARATOR  
CHARGE  
PUMP  
RSA  
RSB  
OPAMP  
OS  
15-BIT  
f
DIV  
PROGRAMMABLE  
DIVIDER  
T0, T1, T2 CP  
IN-LOCK  
DETECTOR  
15-BIT  
FREQUENCY  
REGISTER  
POWER-DOWN  
DETECTOR  
FL  
CONTROL  
REGISTER  
FL  
14 (15)  
CL  
SCL  
2
SDA  
CP T2 T1 T0 RSA RSB OS  
13 (16)  
I C-BUS / 3-WIRE BUS  
TRANSCEIVER  
DA  
11 (18)  
SW  
f
SW  
REF  
1/2f  
CE/AS  
PORT  
REGISTER  
FL  
DIV  
12 (17)  
CE/AS  
UHF VHFH VHFL FMST  
GATE  
3-BIT ADC  
BS  
(8) 21  
GND  
T0, T1, T2  
15 (14)  
LOCK/ADC  
9 (20)  
PVHFH  
7 (22) 10 (19)  
FMST  
8 (21)  
FCE527  
PUHF  
PVHFL  
The pin numbers in parenthesis refer to the TDA6503 and TDA6503A.  
Fig.1 Block diagram.  
2000 Aug 02  
6
Philips Semiconductors  
Product specification  
5 V mixers/oscillators and synthesizers for  
cable TV and VCR 2-band tuners  
TDA6502; TDA6502A;  
TDA6503; TDA6503A  
7
PINNING  
SYMBOL  
PIN  
DESCRIPTION  
TDA6502;  
TDA6502A  
TDA6503;  
TDA6503A  
UHFIN1  
1
2
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
UHF RF input 1  
UHF RF input 2  
VHF RF input  
RF ground  
UHFIN2  
VHFIN  
RFGND  
IFFIL1  
IFFIL2  
PVHFL  
PVHFH  
PUHF  
FMST  
SW  
3
4
5
IF filter output 1  
IF filter output 2  
6
7
PMOS port output, general purpose (e.g. VHF low sub-band)  
PMOS port output, general purpose (e.g. VHF high sub-band)  
PMOS port output, UHF band  
8
9
10  
11  
12  
PMOS port output, general purpose (e.g. FM sound trap)  
bus format selection input: I2C-bus mode or 3-wire bus mode  
CE/AS  
chip enable input in 3-wire bus mode or address selection input in  
I2C-bus mode  
DA  
13  
14  
15  
16  
15  
14  
serial data input/output  
serial clock input  
lock detector output in 3-wire bus mode or ADC input in I2C-bus  
mode  
CL  
LOCK/ADC  
CP  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
13  
12  
11  
10  
9
charge pump output  
VT  
tuning voltage output  
crystal oscillator input  
supply voltage  
XTAL  
VCC  
IFOUT  
IF output  
GND  
8
digital ground  
VHFOSCIB  
OSCGND  
VHFOSCOC  
UHFOSCIB1  
UHFOSCOC1  
UHFOSCOC2  
UHFOSCIB2  
7
VHF oscillator input base  
oscillator ground  
6
5
VHF oscillator output collector  
UHF oscillator input 1 (base)  
UHF oscillator output 1 (collector)  
UHF oscillator output 2 (collector)  
UHF oscillator input 2 (base)  
4
3
2
1
2000 Aug 02  
7
Philips Semiconductors  
Product specification  
5 V mixers/oscillators and synthesizers for  
cable TV and VCR 2-band tuners  
TDA6502; TDA6502A;  
TDA6503; TDA6503A  
handbook, halfpage  
handbook, halfpage  
UHFOSCIB2  
UHFOSCOC2  
UHFOSCOC1  
UHFOSCIB1  
VHFOSCOC  
OSCGND  
1
2
UHFIN1  
UHFIN2  
VHFIN  
28  
27  
26  
25  
24  
UHFIN1  
UHFOSCIB2  
UHFOSCOC2  
UHFOSCOC1  
UHFOSCIB1  
VHFOSCOC  
1
2
28  
27  
26  
25  
24  
UHFIN2  
VHFIN  
RFGND  
IFFIL1  
IFFIL2  
PVHFL  
PVHFH  
PUHF  
FMST  
SW  
3
3
RFGND  
IFFIL1  
4
4
5
5
23 IFFIL2  
22 PVHFL  
21 PVHFH  
6
23 OSCGND  
VHFOSCIB  
6
VHFOSCIB  
GND  
7
22  
7
TDA6503  
TDA6503A  
TDA6502  
TDA6502A  
8
8
21 GND  
IFOUT  
PUHF  
FMST  
SW  
9
20  
19  
18  
17  
16  
IFOUT  
9
20  
19  
18  
17  
16  
V
V
10  
11  
10  
11  
CC  
CC  
XTAL  
XTAL  
VT  
VT 12  
CP  
CE/AS  
DA  
CE/AS 12  
DA  
13  
LOCK/ADC 14  
CP  
13  
CL 14  
15 CL  
15 LOCK/ADC  
FCE571  
FCE570  
Fig.2 Pin configuration for TDA6502 and  
TDA6502A.  
Fig.3 Pin configuration for TDA6503 and  
TDA6503A.  
8
FUNCTIONAL DESCRIPTION  
Control mode selection  
8.1  
The device is controlled via the I2C-bus or the 3-wire bus, depending on the voltage applied to pin SW (see Table 2).  
A LOW level on pin SW enables the I2C-bus: pins CE/AS, DA and CL are used as address selection (AS), serial data  
(SDA) and serial clock (SCL) input respectively.  
A HIGH level on pin SW enables the 3-wire bus: pins CE/AS, DA and CL are used as chip enable (CE), data and clock  
inputs respectively.  
Table 2 Bus format selection  
PIN  
I2C-BUS MODE  
3-WIRE BUS MODE  
TDA6502;  
TDA6502A TDA6503A  
TDA6503;  
SYMBOL  
SW  
11  
12  
13  
14  
15  
18  
17  
16  
15  
14  
LOW-level voltage or ground  
address selection input  
serial data input  
HIGH-level voltage or open-circuit  
enable input  
CE/AS  
DA  
data input  
CL  
serial clock input  
clock input  
LOCK/ADC  
ADC input or test output  
lock detector output or test output  
2000 Aug 02  
8
Philips Semiconductors  
Product specification  
5 V mixers/oscillators and synthesizers for  
cable TV and VCR 2-band tuners  
TDA6502; TDA6502A;  
TDA6503; TDA6503A  
The bus transceiver has an auto-increment facility which  
permits the programming of the device within one single  
transmission (address byte + 4 data bytes). The device  
can also be partially programmed providing that the first  
data byte following the address byte is divider byte DB1 or  
the control byte CB.  
8.2  
I2C-bus data format: pin SW to ground  
8.2.1  
I2C-BUS ADDRESS SELECTION  
The module address contains programmable address  
bits MA1 and MA0 (see Tables 3, 4 and 9) which offer the  
possibility of having several synthesizers (up to 4) in one  
system by applying a specific voltage on pin CE/AS.  
The relationship between bits MA1 and MA0 and the input  
voltage applied to pin CE/AS is given in Table 6.  
The first bit of the byte following the address byte indicates  
whether frequency data (first bit = 0) or control and  
band-switch data (first bit = 1) will follow. Until an I2C-bus  
STOP command is sent by the controller, additional data  
bytes can be entered without the need to re-address the  
device.  
8.2.2  
WRITE MODE  
The write mode is defined by the address byte ADB with  
bit R/W = 0 (see Tables 3 and 4).  
The frequency register is loaded after the 8th clock pulse  
of byte DB2, the control register is loaded after the 8th  
clock pulse of the byte CB and the band-switch register is  
loaded after the 8th clock pulse of byte BB.  
Data bytes can be sent to the device after the address  
transmission (first byte). Four data bytes are needed to  
fully program the device.  
Table 3 I2C-bus data format for write mode of TDA6502 and TDA6503  
BIT  
NAME  
BYTE  
MSB  
LSB  
Address byte  
Divider byte 1  
Divider byte 2  
Control byte  
ADB  
DB1  
DB2  
CB  
1
0
1
N14  
N6  
CP  
X
0
N13  
N5  
T2  
X
0
N12  
N4  
T1  
X
0
N11  
N3  
MA1  
N10  
MA0  
N9  
R/W = 0  
N8  
N7  
1
N2  
N1  
N0  
T0  
RSA  
PUHF  
RSB  
OS  
Band-switch byte  
BB  
X
FMST  
PVHFH PVHFL  
Table 4 I2C-bus data format for write mode of TDA6502A and TDA6503A  
BIT  
NAME  
BYTE  
MSB  
LSB  
Address byte  
Divider byte 1  
Divider byte 2  
Control byte  
ADB  
DB1  
DB2  
CB  
1
0
1
N14  
N6  
CP  
X
0
N13  
N5  
T2  
X
0
N12  
N4  
T1  
X
0
N11  
N3  
MA1  
N10  
MA0  
N9  
R/W = 0  
N8  
N7  
1
N2  
N1  
N0  
T0  
RSA  
FMST  
RSB  
OS  
Band-switch byte  
BB  
X
PUHF  
PVHFH PVHFL  
2000 Aug 02  
9
Philips Semiconductors  
Product specification  
5 V mixers/oscillators and synthesizers for  
cable TV and VCR 2-band tuners  
TDA6502; TDA6502A;  
TDA6503; TDA6503A  
Table 5 Description of the bits used in Tables 3 and 4  
BIT  
DESCRIPTION  
programmable address bits (see Table 6)  
logic 0 for write mode  
MA1 and MA0  
R/W  
N14 to N0  
CP  
programmable divider bits: N = N14 × 214 + N13 × 213 + ... + N1 × 21 + N0  
charge pump current control bit:  
logic 0: charge pump current is 60 µA  
logic 1: charge pump current is 280 µA (at power-on)  
test bits (see Table 7)  
T2, T1 and T0  
RSA and RSB  
OS  
reference divider ratio select bits (see Table 8)  
tuning amplifier control bit:  
logic 0: tuning voltage is ‘on’ (during normal operating)  
logic 1: tuning voltage is ‘off’; high-impedance output of pin VT (at power-on)  
PVHFL, PVHFH, PUHF and FMST PMOS ports control bits:  
logic 0: corresponding buffer is ‘off’ (at power-on)  
logic 1: corresponding buffer is ‘on’  
don’t care  
X
Table 6 Address selection bits (I2C-bus mode)  
MA1  
MA0  
VOLTAGE APPLIED TO PIN CE/AS  
0
0
1
1
0
1
0
1
0 V to 0.1VCC  
0.2VCC to 0.3VCC or open-circuit  
0.4VCC to 0.6VCC  
0.9VCC to 1.0VCC  
Table 7 Test mode bits  
T2  
T1  
T0  
TEST MODE  
0
0
0
1
1
1
1
0
0
1
1
1
0
0
0
1
X
0
1
0
1
normal mode  
normal mode (note 1)  
charge pump is off  
charge pump is sinking current  
charge pump is sourcing current  
fREF is available on pin LOCK/ADC (note 2)  
1⁄2fDIV is available on pin LOCK/ADC (note 2)  
Notes  
1. This is the default mode at Power-on reset.  
2. The ADC input cannot be used when these test modes are active; see Section 8.2.3 for more information.  
2000 Aug 02  
10  
Philips Semiconductors  
Product specification  
5 V mixers/oscillators and synthesizers for  
cable TV and VCR 2-band tuners  
TDA6502; TDA6502A;  
TDA6503; TDA6503A  
Table 8 Reference divider ratio select bits  
RSA  
RSB  
REFERENCE DIVIDER RATIO  
FREQUENCY STEP (kHz)  
X
0
1
0
1
1
80  
128  
64  
50  
31.25  
62.5  
8.2.3  
READ MODE  
The read mode is defined by the address byte ADB with bit R/W = 1 (see Table 9).  
After the slave address has been recognized, the device generates an acknowledge pulse and status byte SB is  
transferred on the SDA line (MSB first). Data is valid on the SDA line during a HIGH level of the SCL line. A second data  
byte can be read from the device if the microcontroller generates an acknowledge on the SDA line (master acknowledge).  
End of transmission will occur if no master acknowledge occurs. The device will then release the data line to allow the  
microcontroller to generate a STOP condition.  
Bit POR is set to logic 1 at power-on. The bit is reset when an end-of-data is detected by the device (end of a read  
sequence). Control of the loop is made possible with bit FL which indicates when the loop is locked (bit FL = 1)  
A built-in ADC input is available on pin LOCK/ADC (I2C-bus mode only). This converter can be used to apply AFC  
information to the microcontroller of the IF section of the television.  
Table 9 Read data format  
BIT  
NAME  
BYTE  
MSB(1)  
LSB  
Address byte  
Status byte  
ADB  
SB  
1
1
0
0
1
0
1
MA1  
A2  
MA0  
A1  
R/W = 1  
A0  
POR  
FL  
R
Note  
1. MSB is transmitted first.  
Table 10 Description of the bits used in Table 9  
BIT  
DESCRIPTION  
MA1 and MA0  
R/W  
programmable address bits (see Table 6)  
logic 1 for read mode  
POR  
Power-on reset flag:  
logic 0: after an end-of-data detected by the device  
logic 1: at power-on  
FL  
in-lock flag:  
logic 0: loop is not locked  
logic 1: loop is locked  
R
ready flag:  
logic 0: mode after Power-on reset (bit T2 = 0, bit T1 = 0 and bit T0 = 1) and the PLL is locked  
logic 1: in other conditions  
A2, A1 and A0  
digital output of the 5-level ADC (see Table 11)  
2000 Aug 02  
11  
Philips Semiconductors  
Product specification  
5 V mixers/oscillators and synthesizers for  
cable TV and VCR 2-band tuners  
TDA6502; TDA6502A;  
TDA6503; TDA6503A  
Table 11 Output of ADC (note 1)  
A2  
A1  
A0  
VOLTAGE APPLIED TO PIN LOCK/ADC  
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
0 to 0.15VCC  
0.15VCC to 0.30VCC  
0.30VCC to 0.45VCC  
0.45VCC to 0.60VCC  
0.60VCC to 1.00VCC  
Note  
1. Accuracy is ±0.03 × VCC  
.
8.2.4  
POWER-ON RESET  
The power-on detection threshold voltage VPOR is set to 3.2 V at room temperature. Below this threshold the device is  
reset to the power-on state.  
At power-on state the following actions take place:  
• The charge pump current is set to 280 µA  
• The tuning voltage output is disabled  
• The test bits T2, T1 and T0 are set to logic ‘001’  
• The divider bit RSB is set to logic 1  
• Port register UHF is ‘off’, which means that the UHF oscillator and the UHF mixer are switched off. Consequently, the  
VHF oscillator and the VHF mixer are switched on. Port registers VHFL and VHFH are ‘off’, which means that the VHF  
tank circuit is operating in the VHF low sub-band. The tuning amplifier is switched off thus the tank circuit is supplied  
with the maximum tuning voltage. The oscillator is therefore operating at the end of the VHF low sub-band.  
Table 12 Default setting of the bits at Power-on reset  
BIT  
NAME  
BYTE  
MSB  
LSB  
Address byte  
Divider byte 1  
Divider byte 2  
Control byte  
ADB  
DB1  
DB2  
CB  
1
0
1
X
X
1
0
X
X
0
0
X
X
0
0
X
X
1
0
MA1  
X
MA0  
X
X
X
X
1
X
1
X
X
X
1
Band switch byte  
BB  
X
X
X
X
0
0
0
2000 Aug 02  
12  
Philips Semiconductors  
Product specification  
5 V mixers/oscillators and synthesizers for  
cable TV and VCR 2-band tuners  
TDA6502; TDA6502A;  
TDA6503; TDA6503A  
8.3  
3-wire bus data format: pin SW to VCC or  
open-circuit  
8.3.1  
POWER-ON RESET  
The power-on detection threshold voltage VPOR is set to  
3.2 V at room temperature. Below this threshold the device  
is reset to the power-on state.  
During a HIGH level on pin CE/AS (enable line), the data  
is clocked into the data register at the HIGH-to-LOW  
transition of the clock (see Figs 4, 5 and 6).  
At power-on state the following actions take place:  
• The charge pump current is set to 280 µA  
• The test bits T2, T1 and T0 are set to logic ‘001’  
• The divider bit RSB is set to logic 1  
The first four bits control the PMOS ports and are loaded  
into the internal band-switch register on the 5th rising edge  
of the clock pulse.  
The frequency bits are loaded into the frequency register  
at the HIGH-to-LOW transition of the enable line when an  
18-bit or 19-bit data word is transmitted. When a 27-bit  
data word is transmitted, the frequency bits are loaded into  
the frequency register on the 20th rising edge of the clock  
pulse and the control bits at the HIGH-to-LOW transition of  
the enable line (see Fig.6).  
• The tuning voltage output is disabled  
• The tuning amplifier control bit OS is automatically reset  
to logic 0 in 18-bit and 19-bit modes when the first data  
word is received to allow normal operation  
• Port register UHF is ‘off’, which means that the UHF  
oscillator and the UHF mixer are switched off.  
Consequently, the VHF oscillator and the VHF mixer are  
switched on. Port registers VHFL and VHFH are ‘off’,  
which means that the VHF tank circuit is operating in the  
VHF low sub-band. The tuning amplifier is switched off  
until the first transmission. In that case, the tank circuit  
is supplied with the maximum tuning voltage.  
The oscillator is therefore operating at the end of the  
VHF low sub-band  
In this 27-bit data format mode the reference divider is  
given by bits RSA and RSB (see Table 8).  
The test bits T2, T1 and T0, the charge pump bit CP, the  
ratio select bit RSB and bit OS can only be selected or  
changed with a 27-bit transmission. They remain  
programmed if an 18-bit or 19-bit transmission occurs.  
Only bit RSA is controlled by the transmission length when  
the 18-bit or 19-bit format is used. When an 18-bit data  
word is transmitted, the most significant bit of the divider  
(bit N14) is internally set to logic 0 and bit RSA is set to  
logic 1. When a 19-bit data word is transmitted, bit RSA is  
set to logic 0.  
• The reference divider ratio is set to 64 or 128 if the first  
sequence to the device has 18 bits or 19 bits  
respectively; if the sequence has 27 bits, the reference  
divider ratio is set by bits RSA and RSB (see Table 8).  
It is not allowed to address the devices with words whose  
length is different from 18, 19 or 27 bits. A data word of  
less than 18 bits will not affect the frequency register of the  
device.  
The definition of the bits is unchanged compared to the  
I2C-bus mode.  
2000 Aug 02  
13  
Philips Semiconductors  
Product specification  
5 V mixers/oscillators and synthesizers for  
cable TV and VCR 2-band tuners  
TDA6502; TDA6502A;  
TDA6503; TDA6503A  
INVALID  
DATA  
BAND-SWITCH  
DATA  
FREQUENCY  
DATA  
INVALID  
DATA  
FMST PVHFL  
PUHF  
PVHFH  
N13 N12 N11 N10 N9  
N8 N7  
N6 N5 N4 N3 N2 N1  
N0  
18  
DA  
CL  
CE  
1
4
5
LOAD BAND-SWITCH  
REGISTER  
LOAD FREQUENCY  
REGISTER  
FCE572  
Fig.4 18-bit data format (bit RSA = 1).  
INVALID  
BAND-SWITCH  
FREQUENCY  
DATA  
INVALID  
DATA  
DATA  
DATA  
FMST PVHFL  
PUHF PVHFH  
N14 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0  
DA  
CL  
CE  
1
4
5
19  
LOAD BAND-SWITCH  
REGISTER  
LOAD FREQUENCY  
REGISTER  
FCE573  
Fig.5 19-bit data format (bit RSA = 0).  
2000 Aug 02  
14  
Philips Semiconductors  
Product specification  
5 V mixers/oscillators and synthesizers for  
cable TV and VCR 2-band tuners  
TDA6502; TDA6502A;  
TDA6503; TDA6503A  
INVALID  
DATA  
BAND SWITCH  
DATA  
FREQUENCY  
DATA  
TEST AND FEATURES  
DATA  
INVALID  
DATA  
FMST PVHFL  
PUHF PVHFH  
N14 N13 N12  
N2  
N1 N0  
X
CP T2 T1  
T0 RSA RSB OS  
DA  
CL  
CE  
1
4
5
19  
20  
27  
LOAD BAND SWITCH  
REGISTER  
LOAD FREQUENCY  
REGISTER  
LOAD CONTROL  
REGISTER  
FCE574  
Fig.6 27-bit data format; test and features mode.  
2000 Aug 02  
15  
Philips Semiconductors  
Product specification  
5 V mixers/oscillators and synthesizers for  
cable TV and VCR 2-band tuners  
TDA6502; TDA6502A;  
TDA6503; TDA6503A  
9
LIMITING VALUES  
In accordance with the Absolute Maximum Rating System (IEC 60134); note 1.  
PIN  
SYMBOL  
PARAMETER  
MIN.  
MAX.  
UNIT  
TDA6502; TDA6503;  
TDA6502A TDA6503A  
VCC  
19  
10  
DC supply voltage  
−0.3  
+6  
V
V
OVS pulse time is 1 s; maximum current  
is 1 A  
−
8
VPn  
7 to 10  
7 to 10  
16  
19 to 22 PMOS port output voltage  
19 to 22 PMOS port output current  
−0.3  
−1  
VCC +0.3  
+30  
V
IPn  
mA  
V
VCP  
13  
18  
12  
14  
15  
16  
16  
17  
charge pump output voltage  
bus format selection input voltage  
tuning voltage output  
−0.3  
−0.3  
−0.3  
−0.3  
−0.3  
−0.3  
−1  
VCC +0.3  
VCC+ 0.3  
+35  
VSW  
VVT  
11  
V
17  
V
VLOCK/ADC  
VCL  
15  
lock/ADC output/input voltage  
serial clock input voltage  
VCC +0.3  
+6  
V
14  
V
VDA  
13  
serial data input/output voltage  
data output current (I2C-bus mode)  
+6  
V
IDA  
13  
+10  
mA  
V
VCE/AS  
12  
chip enable/address selection input  
voltage  
−0.3  
+6  
VXTAL  
IO(n)  
18  
11  
crystal input voltage  
−0.3  
VCC +0.3  
V
1 to 6,  
19 to 28  
1 to 10,  
23 to 28  
output current of each pin to ground  
−
−10  
mA  
tsc(max)  
−
−
maximum short-circuit time (all pins to VCC  
and all pins to GND, OSCGND and  
RFGND)  
−
10  
s
Tstg  
Tamb  
Tj  
−
−
−
−
−
−
storage temperature  
ambient temperature  
junction temperature  
−40  
−20  
−
+150  
+85  
°C  
°C  
°C  
150  
Note  
1. Maximum ratings can not be exceeded, not even momentarily without causing irreversible IC damage. Maximum  
ratings can not be accumulated.  
10 THERMAL CHARACTERISTICS  
SYMBOL  
PARAMETER  
CONDITIONS  
in free air  
TYP.  
UNIT  
Rth(j-a)  
thermal resistance from junction to ambient  
110  
K/W  
2000 Aug 02  
16  
Philips Semiconductors  
Product specification  
5 V mixers/oscillators and synthesizers for  
cable TV and VCR 2-band tuners  
TDA6502; TDA6502A;  
TDA6503; TDA6503A  
11 CHARACTERISTICS  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
Supply; Tamb = 25 oC  
VCC  
ICC  
supply voltage  
supply current  
4.5  
5.0  
5.5  
V
at VCC = 5 V  
all PMOS ports ‘off’  
−
−
71  
78  
mA  
mA  
one PMOS port ‘on’ and  
sourcing 25 mA  
103  
113  
one PMOS port ‘on’ and sourcing  
25 mA; a second port ‘on’ and  
sourcing 5 mA  
−
111  
122  
mA  
PLL part; VCC = 4.5 to 5.5 V; Tamb = −20 to +85 °C; unless otherwise specified  
FUNCTIONAL RANGE  
VPOR  
power-on reset supply  
voltage  
below this supply voltage power-on  
reset becomes active  
−
3.2  
−
V
N
divider ratio  
15-bit frequency word  
14-bit frequency word  
RXTAL = 25 to 300 Ω  
fXTAL = 4 MHz  
64  
64  
−
−
32767  
−
16383  
fXTAL  
crystal oscillator frequency  
4.0  
1200  
−
−
MHz  
ZXTAL  
input impedance  
(absolute value)  
600  
Ω
PMOS PORTS: PINS PUHF, PVHFL, PVHFH AND FMST  
IPn(off)  
leakage current  
VCC = 5.5 V; VPn = 0 V  
−10  
−
−
µA  
VPn(sat)  
output saturation voltage  
one buffer output is ‘on’ and  
sourcing 10 mA  
−
0.25  
0.4  
V
one buffer output is ‘on’ and  
sourcing 25 mA  
−
0.25  
0.5  
V
LOCK OUTPUT: PIN LOCK/ADC (IN 3-WIRE BUS MODE)  
IUNLOCK  
VUNLOCK  
VLOCK  
output current when the PLL VCC = 5.5 V; VO = 5.5 V  
is out-of-lock  
−
−
−
−
200  
0.8  
µA  
V
output saturation voltage  
VUNLOCK = VCC − VO; IO = 200 µA  
0.4  
0.2  
when the PLL is out-of-lock  
output voltage  
the PLL is locked  
0.40  
V
ADC INPUT: PIN LOCK/ADC (IN I2C-BUS MODE)  
VADC  
ADC input voltage  
see Table 11  
VADC = VCC  
VADC = 0 V  
0
−
−
−
VCC  
10  
−
V
IADC(H)  
IADC(L)  
HIGH-level input current  
LOW-level input current  
−
µA  
µA  
−10  
BUS FORMAT SELECTION: PIN SW  
VSW(L)  
VSW(H)  
ISW(H)  
ISW(L)  
LOW-level input voltage  
HIGH-level input voltage  
HIGH-level input current  
LOW-level input current  
0
−
−
−
−
1.5  
VCC  
10  
−
V
3
V
VSW = VCC  
VSW = 0 V  
−
µA  
µA  
−100  
2000 Aug 02  
17  
Philips Semiconductors  
Product specification  
5 V mixers/oscillators and synthesizers for  
cable TV and VCR 2-band tuners  
TDA6502; TDA6502A;  
TDA6503; TDA6503A  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
CHIP ENABLE/ADDRESS SELECTION INPUT: PIN CE/AS  
VCE/AS(L)  
VCE/AS(H)  
ICE/AS(H)  
ICE/AS(L)  
LOW-level input voltage  
HIGH-level input voltage  
HIGH-level input current  
LOW-level input current  
0
3
−
−
−
−
−
1.5  
V
5.5  
10  
−
V
VCE/AS = 5.5 V  
µA  
µA  
VCE/AS = 0 V  
−10  
CLOCK AND DATA INPUTS: PINS CL AND DA  
VCL(L)  
VDA(L)  
,
LOW-level input voltage  
0
3
−
−
1.5  
5.5  
V
V
VCL(H)  
,
HIGH-level input voltage  
VDA(H)  
ICL(H), IDA(H) HIGH-level input current  
VBUS = 5.5 V; VCC = 0 V  
−
−
−
−
−
10  
10  
10  
−
µA  
µA  
µA  
µA  
VBUS = 5.5 V; VCC = 5.5 V  
VBUS = 1.5 V; VCC = 0 V  
−
ICL(L), IDA(L) LOW-level input current  
−
VBUS = 0 V; VCC = 5.5 V  
−10  
DATA OUTPUT: PIN DA (IN I2C-BUS MODE ONLY)  
IDA(H)  
HIGH-level output current  
LOW-level output voltage  
VDA = 5.5 V  
−
−
−
−
10  
µA  
VDA(L)  
IDA = 3 mA (sink current)  
0.4  
V
CLOCK FREQUENCY (I2C-BUS MODE ONLY)  
fclk  
clock frequency  
−
−
400  
kHz  
CHARGE PUMP OUTPUT: PIN CP  
ICP(H)  
HIGH-level input current  
(absolute value)  
CP = 1  
−
280  
60  
−
−
µA  
µA  
nA  
ICP(L)  
LOW-level input current  
(absolute value)  
CP = 0  
−
−
ICP(leak)  
off-state leakage current  
T2 = 0; T1 = 1  
−15  
+15  
TUNING VOLTAGE OUTPUT: PIN VT  
IVT(off)  
leakage current when  
switched-off  
OS = 1; tuning supply is 33 V  
−
−
−
10  
µA  
VVT  
output voltage when the loop OS = 0; T2 = 0; T1 = 0; T0 = 1;  
is closed RL = 27 kΩ; tuning supply is 33 V  
0.2  
32.7  
V
Mixer/oscillator part; VCC = 5 V; Tamb = 25 oC; measurements related to measurement circuit (see Fig.19)  
VHF MIXER (INCLUDING IF PREAMPLIFIER)  
fRF(o)  
fRF  
RF operational frequency  
RF frequency  
40  
−
800  
MHz  
note 1  
55.25  
17.5  
17.5  
−
−
361.25 MHz  
Gv  
voltage gain  
fRF = 57.5 MHz; see Fig.12  
fRF = 363.5 MHz; see Fig.12  
20  
20  
7.5  
7.5  
7.5  
22.5  
22.5  
10  
dB  
dB  
dB  
dB  
dB  
NF  
noise figure  
f
RF = 50 MHz; see Figs 13 and 14  
fRF = 150 MHz; see Figs 13 and 14  
RF = 300 MHz; see Fig.14  
−
10  
f
−
10  
2000 Aug 02  
18  
Philips Semiconductors  
Product specification  
5 V mixers/oscillators and synthesizers for  
cable TV and VCR 2-band tuners  
TDA6502; TDA6502A;  
TDA6503; TDA6503A  
SYMBOL  
Vo  
PARAMETER  
CONDITIONS  
MIN.  
107  
TYP.  
110  
MAX.  
UNIT  
output voltage (causing 1% fRF = 55.25 MHz; see Fig.15  
cross modulation in channel)  
−
dBµV  
dBµV  
dBµV  
f
RF = 361.25 MHz; see Fig.15  
107  
110  
83  
−
−
Vi  
input voltage (causing  
fRF = 361.25 MHz; note 2  
−
pulling-in channel at 750 Hz)  
gos  
optimum source  
conductance for noise figure  
fRF = 50 MHz  
−
−
−
−
−
−
0.7  
0.9  
1.5  
0.3  
0.4  
1.35  
−
−
−
−
−
−
mS  
mS  
mS  
mS  
mS  
pF  
fRF = 150 MHz  
fRF = 300 MHz  
gi  
input conductance  
input capacitance  
fRF = 55.25 MHz; see Fig.7  
fRF = 361.25 MHz; see Fig.7  
Ci  
fRF = 57.5 to 357.5 MHz; see Fig.7  
VHF OSCILLATOR  
fOSC(o)  
oscillator operational  
60  
−
600  
MHz  
frequency  
fOSC  
oscillator frequency  
note 3  
101  
−
−
407  
−
MHz  
kHz  
kHz  
kHz  
∆fOSC(V)  
oscillator frequency variation ∆VCC = 5%; note 4  
with supply voltage  
60  
∆VCC = 10%; note 4  
−
110  
1600  
−
∆fOSC(T)  
oscillator frequency variation ∆T = 25 °C; with compensation;  
−
−
with temperature  
note 5  
∆fOSC(t)  
oscillator frequency drift  
5 s to 15 min after switch-on; note 6 −  
400  
105  
−
−
kHz  
ΦOSC  
phase noise, carrier-to-noise ±100 kHz frequency offset; worst  
−
dBc/Hz  
sideband  
case in the frequency range  
RSC  
ripple susceptibility of VCC  
(peak-to-peak value)  
VCC = 5 V; worst case in the  
frequency range; ripple frequency  
500 kHz; note 7  
15  
30  
−
mV  
UHF MIXER (INCLUDING IF PREAMPLIFIER)  
fRF(o)  
fRF  
RF operational frequency  
RF frequency  
200  
367.25  
29  
−
900  
MHz  
note 1  
−
801.25 MHz  
Gv  
voltage gain  
fRF = 369.5 MHz; see Fig.16  
fRF = 803.5 MHz; see Fig.16  
32  
32  
7
35  
35  
9
dB  
29  
dB  
NF  
Vo  
noise figure (not corrected  
for image)  
f
RF = 369.5 MHz; see Fig.17  
RF = 803.5 MHz; see Fig.17  
−
dB  
f
−
7
9
dB  
output voltage (causing 1% fRF = 367.25 MHz; see Fig.18  
cross modulation in channel)  
107  
107  
−
110  
110  
85  
−
dBµV  
dBµV  
dBµV  
f
RF = 801.25 MHz; see Fig.18  
−
Vi  
Zi  
input voltage (causing  
pulling in channel at 750 Hz)  
fRF = 801.25 MHz; note 2  
−
input impedance (RS + jωLS) RS at fRF = 367.25 MHz; see Fig.8  
RS at fRF = 801.25 MHz; see Fig.8  
−
−
−
−
26  
28  
8.5  
8
−
−
−
−
Ω
Ω
LS at fRF = 367.25 MHz; see Fig.8  
nH  
nH  
LS at fRF = 801.25 MHz; see Fig.8  
2000 Aug 02  
19  
Philips Semiconductors  
Product specification  
5 V mixers/oscillators and synthesizers for  
cable TV and VCR 2-band tuners  
TDA6502; TDA6502A;  
TDA6503; TDA6503A  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
UHF OSCILLATOR  
fOSC(o)  
oscillator operational  
frequency  
300  
−
−
1000  
MHz  
fOSC  
oscillator frequency  
note 3  
413  
−
847  
−
MHz  
kHz  
kHz  
kHz  
∆fOSC(V)  
oscillator frequency variation ∆VCC = 5%; note 4  
with supply voltage  
35  
∆VCC = 10%; note 4  
−
100  
500  
−
∆fOSC(T)  
∆fOSC(t)  
ΦOSC  
oscillator frequency variation ∆T = 25 °C; with compensation;  
with temperature  
−
−
note 5  
oscillator frequency drift  
5 s to 15 min after switching on;  
note 6  
−
120  
105  
30  
−
−
−
kHz  
phase noise, carrier-to-noise ±100 kHz frequency offset; worst  
sideband  
−
dBc/Hz  
mV  
case in the frequency range  
RSC  
ripple susceptibility of VCC  
(peak-to-peak value)  
VCC = 5 V; worst case in the  
frequency range; ripple frequency  
500 kHz; note 7  
15  
IF PREAMPLIFIER  
IF  
IF operational frequency  
30  
−
−
60  
−
MHz  
dB  
S22  
output reflection coefficient  
magnitude; see Fig.9  
phase; see Fig.9  
−12.8  
0.2  
80  
−
−
degree  
Ω
Zo  
output impedance  
(RS + jωLS)  
RS at 43.5 MHz; see Fig.9  
LS at 43.5 MHz; see Fig.9  
−
−
−
0.5  
−
nH  
REJECTION AT THE IF OUTPUT  
INTdiv  
INTxtal  
INTref  
level of divider interferences worst case; note 8  
in the IF signal  
−
16  
−
20  
−
dBµV  
dBc  
crystal oscillator  
VIF = 100 dBµV; worst case in the  
60  
60  
interferences rejection  
frequency range; note 9  
reference frequency  
rejection  
VIF = 100 dBµV; worst case in the  
frequency range; fREF = 62.5 kHz;  
note 10  
−
−
dBc  
INTch6  
channel 6 beat  
VRF(pix) = VRF(snd) = 80 dBµV;  
note 11  
50  
56  
54  
60  
−
−
dBc  
dBc  
INTchA-5  
channel A-5 beat  
VRF(pix) = 80 dBµV; note 12  
Notes  
1. The RF frequency range is defined by the oscillator frequency range and the IF frequency.  
2. This is the level of the RF signal (100% amplitude modulated with 11.89 kHz) that causes a 750 Hz frequency  
deviation on the oscillator signal; it produces sidebands 30 dB below the level of the oscillator signal.  
3. Limits are related to the tank circuits used in Fig.19; frequency bands may be adjusted by the choice of external  
components.  
4. The frequency shift is defined as a change in oscillator frequency when the supply voltage varies from  
VCC = 5 to 4.75 V (4.5 V) or from VCC = 5 to 5.25 V (5.5 V). The oscillator is free running during this measurement.  
5. The frequency drift is defined as a change in oscillator frequency when the ambient temperature varies from  
Tamb = 25 to 50 °C or from Tamb = 25 to 0 °C. The oscillator is free running during this measurement.  
2000 Aug 02  
20  
Philips Semiconductors  
Product specification  
5 V mixers/oscillators and synthesizers for  
cable TV and VCR 2-band tuners  
TDA6502; TDA6502A;  
TDA6503; TDA6503A  
6. Switch-on drift is defined as the change in oscillator frequency between 5 s and 15 min after switch-on. The oscillator  
is free running during this measurement.  
7. The ripple susceptibility is measured for a 500 kHz ripple at the IF output using the measurement circuit of Fig.19;  
the level of the ripple signal is increased until a difference of 53.5 dB occurs between the IF carrier fixed at 100 dBµV  
and the sideband components.  
8. This is the level of divider interferences close to the IF frequency. For example channel C: fOSC = 179 MHz,  
1⁄4 fOSC = 44.75 MHz. The VHFIN input must be left open (i.e. not connected to any load or cable); The UHFIN1 and  
UHFIN2 inputs are connected to a hybrid.  
9. Crystal oscillator interference means the 4 MHz sidebands caused by the crystal oscillator. The rejection has to be  
greater than 60 dB for an IF output signal of 100 dBµV.  
10. The reference frequency rejection is the level of reference frequency sidebands related to the sound subcarrier.  
11. Channel 6 beat is the interfering product of fRF(pix) + fRF(snd) − fOSC of channel 6 at 42 MHz. This measurement is  
done using the TDA6502 (respectively TDA6503) Philips demoboard number 9058_1 (respectively 9059_1).  
12. Channel A-5 beat is the interfering product of fRF(pix), fIF and fOSC of channel A-5: fbeat = 45.5 MHz.  
The possible mechanisms are: fOSC − 2 × fIF or 2 × fRF(pix) − fOSC. For the measurement: VRF = 80 dBµV. This  
measurement is done using the TDA6502 (respectively TDA6503) Philips demoboard number 9058_1  
(respectively 9059_1).  
1
handbook, full pagewidth  
2
0.5  
0.2  
5
10  
− j  
+ j  
40 MHz  
10  
5
2
1
0.5  
0.2  
∞
0
10  
400 MHz  
5
0.2  
2
0.5  
FCE528  
1
Fig.7 Input admittance (S11) of the VHF mixer input (40 to 400 MHz); Y0 = 20 mS.  
2000 Aug 02  
21  
Philips Semiconductors  
Product specification  
5 V mixers/oscillators and synthesizers for  
cable TV and VCR 2-band tuners  
TDA6502; TDA6502A;  
TDA6503; TDA6503A  
1
0.5  
2
860 MHz  
0.2  
5
350 MHz  
10  
∞
+ j  
0.2  
0.5  
1
2
5
10  
0
− j  
10  
5
0.2  
2
0.5  
FCE529  
1
Fig.8 Input impedance (S11) of the UHF mixer input (350 to 860 MHz); Z0 = 50 Ω.  
1
0.5  
2
0.2  
5
10  
+ j  
− j  
20 MHz  
0.2  
0.5  
1
2
5
10  
∞
0
100 MHz  
10  
5
0.2  
2
0.5  
FCE530  
1
Fig.9 Output impedance (S22) of the IF amplifier (20 to 60 MHz); Z0 = 50 Ω.  
2000 Aug 02  
22  
Philips Semiconductors  
Product specification  
5 V mixers/oscillators and synthesizers for  
cable TV and VCR 2-band tuners  
TDA6502; TDA6502A;  
TDA6503; TDA6503A  
12 TIMING CHARACTERISTICS  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP. MAX. UNIT  
3-wire bus timing  
tHIGH  
clock HIGH time  
data set-up time  
see Fig.10  
2
−
−
−
−
−
−
−
−
−
−
−
−
−
−
µs  
µs  
µs  
µs  
µs  
µs  
µs  
tSU;DA  
tHD;DA  
tSU;ENCL  
tHD;ENDA  
tEN  
see Fig.10  
see Fig.10  
see Fig.10  
see Fig.10  
2
data hold time  
2
enable-to-clock set-up time  
enable-to-data hold time  
10  
2
enable time between two transmissions see Fig.11  
10  
6
tHD;ENCL  
enable-to-clock active edge hold time  
see Fig.11  
INVALID  
DATA  
INVALID  
DATA  
LSB  
DA  
CL  
MSB  
t
HIGH  
t
SU;DA  
t
HD;DA  
CE  
t
t
SU;ENCL  
HD;ENDA  
FCE575  
Fig.10 Timing diagram for 3-wire bus; DA, CL and CE.  
handbook, halfpage  
t
EN  
CE  
CL  
t
FCE576  
HD;ENCL  
Fig.11 Timing diagram for 3-wire bus; CE and CL.  
2000 Aug 02  
23  
Philips Semiconductors  
Product specification  
5 V mixers/oscillators and synthesizers for  
cable TV and VCR 2-band tuners  
TDA6502; TDA6502A;  
TDA6503; TDA6503A  
13 TEST AND APPLICATION INFORMATION  
13.1 Test circuits  
signal  
source  
50 Ω  
27 Ω  
VHFIN  
IFOUT  
spectrum  
analyzer  
D.U.T.  
e
V
V
50 Ω  
50 Ω  
meas  
V
V
V'  
i
o
meas  
RMS  
voltmeter  
FCE577  
Zi >> 50 Ω  
Vi = 2 × Vmeas = 80 dBµV  
Vi = Vmeas + 6 dB = 80 dBµV  
50 + 27  
Vo = V’meas ×  
-------------------  
50  
V o  
G = 20 log  
v
------  
V i  
Fig.12 Gain measurement in VHF band.  
I1  
I3  
PCB  
PCB  
plug  
C1  
C3  
BNC  
BNC  
plug  
I2  
L1  
C2  
RIM-RIM  
RIM-RIM  
C4  
(a)  
(b)  
FCE578  
(a) For fRF = 50 MHz:  
(b) For fRF = 150 MHz:  
mixer A frequency response measured = 57 MHz, loss = 0 dB  
image suppression = 16 dB  
mixer A frequency response measured = 150.3 MHz, loss = 1.3 dB  
image suppression = 13 dB  
C1 = 9 pF  
C3 = 5 pF  
C2 = 15 pF  
C4 = 25 pF  
L1 = 7 turns ( 5.5 mm, wire = 0.5 mm)  
l1 = 5 cm semi rigid RIM cable (33 dB/100 m, 50 Ω and 96 pF/m).  
l2 = 30 cm semi rigid RIM cable (33 dB/100 m, 50 Ω and 96 pF/m).  
l3 = 5 cm semi rigid RIM cable (33 dB/100 m, 50 Ω and 96 pF/m).  
Fig.13 Input circuit for optimum noise figure in VHF band.  
2000 Aug 02  
24  
Philips Semiconductors  
Product specification  
5 V mixers/oscillators and synthesizers for  
cable TV and VCR 2-band tuners  
TDA6502; TDA6502A;  
TDA6503; TDA6503A  
NOISE  
NOISE  
FIGURE  
METER  
27 Ω  
BNC  
RIM  
VHFIN  
IFOUT  
SOURCE  
INPUT  
CIRCUIT  
D.U.T.  
FCE579  
NF = NFmeas − loss (of input circuit) (dB).  
Fig.14 Noise figure (NF) measurement in VHF band.  
FILTER  
AM = 30%  
18 dB  
attenuator  
50 Ω  
27 Ω  
2 kHz  
A
C
VHFIN  
IFOUT  
modulation  
analyzer  
unwanted  
signal  
45.75 MHz  
e
u
source  
HYBRID  
D.U.T.  
50 Ω  
V
V
V
meas  
o
50 Ω  
B
D
wanted  
signal  
e
50  
Ω
w
RMS  
voltmeter  
source  
FCE580  
50 + 27  
Vo = Vmeas  
×
-------------------  
50  
Wanted output signal at fRF(w) = 55.25 (361.25) MHz; Vo(w) = 100 dBµV.  
Measuring the level of the unwanted output signal Vo(u) causing 0.3% AM modulation in the wanted output signal; fRF(u) = 59.75 (366.75) MHz.  
fOSC = 101 (407) MHz.  
Filter characteristics: fc = 45.75 MHz, f−3dB(BW) = 1.4 MHz, f−30dB(BW) = 3.1 MHz.  
Fig.15 Cross modulation measurement in VHF band.  
2000 Aug 02  
25  
Philips Semiconductors  
Product specification  
5 V mixers/oscillators and synthesizers for  
cable TV and VCR 2-band tuners  
TDA6502; TDA6502A;  
TDA6503; TDA6503A  
signal  
source  
27 Ω  
50 Ω  
A
UHFIN1 IFOUT  
D.U.T.  
C
spectrum  
analyzer  
V
HYBRID  
i
e
V
V
50 Ω  
50 Ω  
meas  
V
V'  
o
meas  
B
D
UHFIN2  
50 Ω  
RMS  
voltmeter  
FCE581  
Loss (in hybrid) = 1 dB.  
Vi = Vmeas − loss (in hybrid) = 70 dBµV.  
50 + 27  
Vo = V’meas ×  
-------------------  
50  
V o  
G = 20 log  
v
------  
V i  
Fig.16 Gain (Gv) measurement in UHF band.  
NOISE  
FIGURE  
METER  
27 Ω  
NOISE  
SOURCE  
A
C
UHFIN IFOUT  
D.U.T.  
HYBRID  
B
D
UHFIN  
FCE582  
50 Ω  
Loss (in hybrid) = 1 dB.  
NF = NFmeas − loss (in hybrid).  
Fig.17 Noise figure (NF) measurement in bands UHF.  
26  
2000 Aug 02  
Philips Semiconductors  
Product specification  
5 V mixers/oscillators and synthesizers for  
cable TV and VCR 2-band tuners  
TDA6502; TDA6502A;  
TDA6503; TDA6503A  
FILTER  
18 dB  
attenuator  
AM = 30%  
50 Ω  
27 Ω  
2 kHz  
A
A
C
C
UHFIN IFOUT  
D.U.T.  
modulation  
analyzer  
unwanted  
signal  
45.75 MHz  
e
u
source  
HYBRID  
HYBRID  
50 Ω  
V
V
V
meas  
o
50 Ω  
B
D
B
D
UHFIN  
wanted  
signal  
e
w
RMS  
voltmeter  
source  
50 Ω  
50 Ω  
FCE583  
50 + 27  
Vo = Vmeas  
×
-------------------  
50  
Wanted output signal at fRF(w) = 367.25 (801.25) MHz; Vo(w) = 100 dBµV.  
Measuring the level of the unwanted output signal Vo(u) causing 0.3% AM modulation in the wanted output signal; fRF(u) = 371.25 (805.75) MHz.  
fOSC = 413 (847) MHz.  
Filter characteristics: fc = 45.75 MHz, f−3dB(BW) = 1.4 MHz, f−30dB(BW) = 3.1 MHz.  
Fig.18 Cross modulation measurement in UHF band.  
2000 Aug 02  
27  
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C1  
C8 1.2 pF  
C9 1.2 pF  
C10 1.2 pF  
W1  
R3  
UHFOSCOC2  
UHFIN1  
1(28)  
28(1)  
22 kΩ  
D1  
BB179  
4.7 nF  
C2  
W2  
UHFOSCIB2  
UHFOSCOC1  
UHFIN2  
VHFIN  
RFGND  
IFFIL1  
R4  
2(27)  
3(26)  
4(25)  
5(24)  
6(23)  
27(2)  
26(3)  
L1  
R2 27 Ω  
4.7 nF  
C3  
W3  
22 kΩ  
C12  
27 pF  
4.7 nF  
C11 1.2 pF  
C13  
R5  
UHFOSCIB1  
VHFOSCOC  
25(4)  
C4  
BB178  
L2  
22 kΩ  
C15  
R6 5.6 Ω  
24(5)  
23(6)  
15 pF  
C5  
D2  
82 pF  
L3  
2 pF  
C17  
4.7 nF  
R7  
IFFIL2  
OSCGND  
L4  
10 kΩ  
C6  
22 nF  
C14  
2 pF  
VHFOSCIB  
15 pF  
PVHFL  
PVHFH  
PUHF  
D4  
LED  
D5  
LED  
D6  
LED  
D7  
LED  
22(7)  
BA792  
C16  
TDA6502/2A  
(TDA6503/3A)  
7(22)  
330 Ω  
R8  
R15  
R16  
GND  
4.7 nF  
VHF-HIGH  
21(8)  
20(9)  
D3  
8(21)  
9(20)  
680 Ω  
C18 4.7 nF  
330 Ω  
R17 330 Ω  
R18  
L5  
R9  
IFOUT  
V
VHF-LOW  
3.9 kΩ  
CC  
C19 4.7 nF  
V
CC  
FMST  
R10  
19(10)  
18(11)  
17(12)  
10(19)  
11(18)  
Y1  
CON4  
330 Ω  
C20  
3.9 kΩ  
XTAL  
SW  
CON3  
J1  
18 pF  
R14  
open for 3-wire  
VT  
CP  
CE/AS  
DA  
for test purpose only  
12(17)  
13(16)  
14(15)  
2.2 kΩ  
C23  
C21  
R12  
10 nF  
V
16(13)  
15(14)  
CC  
12 kΩ  
R13  
22 kΩ  
100 nF  
CL  
LOCK/ADC  
CON1  
R21  
330  
Ω
R20 R19  
C22  
330 pF  
R22  
330  
330  
Ω
Ω
330 Ω  
TR1  
R11  
27 Ω  
BC847B  
R26  
6.8 kΩ  
C26  
LOCK  
R25  
for test  
purpose only  
1 kΩ  
C27  
10 µF 10 µF  
(16 V) (16 V)  
R24  
TR2  
FCE481  
68 kΩ  
01 02 03 04 05 06  
J3  
02  
J2 04 03  
01  
BC847B  
RIPPLE  
for test purpose only  
The pin numbers in parenthesis refer to the TDA6503 and TDA6503A.  
ahdnbok,uflapegwidt  
Fig.19 Measurement circuit.  
Philips Semiconductors  
Product specification  
5 V mixers/oscillators and synthesizers for  
cable TV and VCR 2-band tuners  
TDA6502; TDA6502A;  
TDA6503; TDA6503A  
Table 13 Capacitors (all SMD and NP0)  
COMPONENT  
VALUE  
COMPONENT  
VALUE  
R15  
R16  
R17  
R18  
R19  
R20  
R21  
R22  
R24  
R25  
R26  
330 Ω  
330 Ω  
330 Ω  
330 Ω  
330 Ω  
330 Ω  
330 Ω  
330 Ω  
68 kΩ  
1 kΩ  
C1  
4.7 nF  
4.7 nF  
4.7 nF  
15 pF  
15 pF  
22 nF  
C2  
C3  
C4  
C5  
C6  
C8  
1.2 pF (N750)  
1.2 pF (N750)  
1.2 pF(N750)  
1.2 pF (N750)  
27 pF (N750)  
2 pF (N750)  
2 pF (N750)  
82 pF (N750)  
4.7 nF  
C9  
C10  
C11  
C12  
C13  
C14  
C15  
C16  
C17  
C18  
C19  
C20  
C21  
C22  
C23  
C26  
C27  
6.8 kΩ  
Table 15 Diodes and ICs  
COMPONENT  
VALUE  
D1  
D2  
D3  
IC  
BB179  
BB178  
BA792  
4.7 nF  
4.7 nF  
TDA6502; TDA6502A  
TDA6503; TDA6503A  
4.7 nF  
18 pF  
Table 16 Coils (note 1)  
100 nF  
COMPONENT  
VALUE  
330 pF  
L1  
L2  
L3  
L5  
1.5 turns; diameter 1.5 mm  
2.5 turns; diameter 2.5 mm  
7.5 turns; diameter 3.0 mm  
7.5 turns; diameter 2.5 mm  
10 nF  
10 µF (16 V, electrolytic)  
10 µF (16 V, electrolytic)  
Table 14 Resistors (all SMD)  
Note  
COMPONENT  
VALUE  
1. Wire size is 0.4 mm.  
R2  
27 Ω  
Table 17 Transformer (note 1)  
R3  
22 kΩ  
22 kΩ  
22 kΩ  
5.6 Ω  
10 kΩ  
680 Ω  
3.9 kΩ  
3.9 kΩ  
27 Ω  
R4  
COMPONENT  
VALUE  
R5  
L4  
2 x 5 turns  
R6  
Note  
R7  
1. Coil type: TOKO 7kN; material: 113 kN; screw core:  
03-0093; pot core: 04-0026.  
R8  
R9  
R10  
R11  
R12  
R13  
R14  
Table 18 Crystal  
COMPONENT  
VALUE  
12 kΩ  
22 kΩ  
2.2 kΩ  
Y1  
4 MHz  
2000 Aug 02  
29  
Philips Semiconductors  
Product specification  
5 V mixers/oscillators and synthesizers for  
cable TV and VCR 2-band tuners  
TDA6502; TDA6502A;  
TDA6503; TDA6503A  
13.5 Examples of I2C-bus data format sequences for  
TDA6502 and TDA6503  
Table 19 Transistors  
COMPONENT  
VALUE  
Tables 20 to 24 show the various write sequences where:  
TR1  
TR2  
BC847B  
BC847B  
S = START bit  
A = acknowledge bit  
P = STOP bit.  
13.3 Tuning amplifier  
The tuning amplifier is capable of driving the varicap  
voltage without an external transistor. The tuning voltage  
output must be connected to an external load of 22 kΩ  
which is connected to the tuning voltage supply rail.  
The loop filter design depends on the oscillator  
Conditions:  
fxtal = 4 MHz  
N = 1600  
fosc = 100 MHz  
characteristics and the selected reference frequency.  
fstep = 62.5 kHz  
Port register VHFL is ‘on’ to switch-on band VHF low  
Port register FMST is ‘on’ to switch-on an FM sound trap  
ICP = 280 µA.  
13.4 Crystal oscillator  
The crystal oscillator uses a 4 MHz crystal connected in  
series with an 18 pF capacitor thereby operating in the  
series resonance mode. Connecting the crystal to the  
ground is preferred, but it can also be connected to the  
supply voltage.  
13.5.1 WRITE SEQUENCES TO REGISTER C2  
Table 20 Complete sequence with first the divider bytes (first data bit = 0)  
BAND-  
ADDRESS  
BYTE  
DIVIDER  
BYTE 1  
DIVIDER  
BYTE 2  
CONTROL  
BYTE  
START  
ACK  
ACK  
ACK  
ACK SWITCH ACK STOP  
BYTE  
S
C2  
A
06  
A
40  
A
CE  
A
09  
A
P
Table 21 Complete sequence with first the control and band-switch bytes (first data bit = 1)  
BAND-  
ACK SWITCH ACK  
BYTE  
ADDRESS  
BYTE  
CONTROL  
BYTE  
DIVIDER  
BYTE 1  
DIVIDER  
BYTE 2  
START  
ACK  
ACK  
ACK STOP  
S
C2  
A
CE  
A
09  
A
06  
A
40  
A
P
Table 22 Sequence with divider bytes only (first data bit = 0)  
START  
ADDRESS BYTE  
ACK  
DIVIDER BYTE 1  
06  
ACK  
DIVIDER BYTE 2  
ACK STOP  
S
C2  
A
A
40  
A
P
Table 23 Sequence with control and band-switch bytes only (first data bit = 1)  
START  
ADDRESS BYTE  
ACK  
CONTROL BYTE  
ACK BAND-SWITCH BYTE ACK STOP  
09  
S
C2  
A
CE  
A
A
P
Table 24 Sequence with control byte only (first data bit = 1)  
START  
ADDRESS BYTE  
ACK  
CONTROL BYTE  
ACK STOP  
S
C2  
A
CE  
A
P
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Product specification  
5 V mixers/oscillators and synthesizers for  
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TDA6502; TDA6502A;  
TDA6503; TDA6503A  
13.5.2 READ SEQUENCES FROM REGISTER C3  
Tables 25 and 26 show the various read sequences where:  
S = START bit  
A = acknowledge bit  
XX = read status byte  
X = no acknowledge from the master means end of sequence  
P = STOP bit  
Table 25 One status byte acquisition  
START  
ADDRESS BYTE  
ACK  
STATUS BYTE  
XX  
ACK STOP  
S
C3  
A
X
P
Table 26 Two status bytes acquisition  
START  
ADDRESS BYTE  
ACK  
STATUS BYTE  
ACK  
STATUS BYTE  
XX  
ACK STOP  
S
C3  
A
XX  
A
X
P
13.6 Examples of 3-wire bus data format sequences for TDA6502 and TDA6503  
13.6.1 18-BIT SEQUENCE  
Conditions:  
fosc = 800 MHz  
Port register PUHF is ‘on’.  
Table 27 18-bit sequence  
PUHF FMST PVHFH PVHFL N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0  
1
0
0
0
1
1
1
0
0
1
0
0
0
0
0
0
0
0
The reference divider is automatically set to 64 assuming that bit RSB has been set to logic 1 at power-on. If bit RSB has  
been set to logic 0, in a previous 27-bit sequence, the reference divider will still be set at 80. In this event, the 18-bit  
sequence has to be adapted to the 80 divider ratio.  
13.6.2 19-BIT SEQUENCE  
Conditions:  
fosc = 650 MHz  
Port register PUHF is ‘on’.  
Table 28 19-bit sequence  
PUHF FMST PVHFH PVHFL N14 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0  
1
0
0
0
1
0
1
0
0
0
1
0
1
0
0
0
0
0
0
The reference divider is automatically set to 128 assuming that bit RSB has been set to logic 1 at power-on. If bit RSB  
has been set to logic 0 in a previous 27-bit sequence, the reference divider will still be set at 80. In this event, the 19-bit  
sequence has to be adapted to the 80 divider ratio.  
2000 Aug 02  
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Product specification  
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TDA6502; TDA6502A;  
TDA6503; TDA6503A  
13.6.3 27-BIT SEQUENCE  
Conditions:  
fosc = 750 MHz  
Port register PUHF is ‘on’  
Reference divider is set at 80  
ICP = 60 µA  
No test function.  
Table 29 27-bit sequence  
FREQUENCY DATA BITS  
PORT BITS  
CONTROL DATA BITS  
14 13 12 11 10  
9
8
7
6
5
4
3
2
1
0
X
CP T2 T1 T0 RSA RSB OS  
1
0
0
0
0
1
1
1
0
1
0
1
0
0
1
1
0
0
0
1
0
0
0
1
0
0
0
To change the oscillator frequency to 600 MHz in 50 kHz steps a 19-bit sequence or an 18-bit sequence can be used.  
The charge pump current remains at 60 µA.  
Table 30 Changing frequency with a 19-bit sequence  
FREQUENCY DATA BITS  
PORT BITS  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
1
0
0
0
0
1
0
1
1
1
0
1
1
1
0
0
0
0
0
Table 31 Changing frequency with an 18-bit sequence  
FREQUENCY DATA BITS  
PORT BITS  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
1
0
0
0
1
0
1
1
1
0
1
1
1
0
0
0
0
0
2000 Aug 02  
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Product specification  
5 V mixers/oscillators and synthesizers for  
cable TV and VCR 2-band tuners  
TDA6502; TDA6502A;  
TDA6503; TDA6503A  
14 INTERNAL PIN CONFIGURATION  
DC VOLTAGE  
PIN  
(AVERAGE VALUE)(1)  
SYMBOL  
EQUIVALENT CIRCUIT(2)  
TDA6502;  
TDA6502A TDA6503A  
TDA6503;  
VHF  
UHF  
UHFIN1  
UHFIN2  
1
2
28  
27  
−
−
1.0 V  
1.0 V  
1
2
(27)  
(28)  
FCE584  
VHFIN  
3
26  
1.8 V  
−
3
(26)  
FCE585  
RFGND  
4
25  
0.0 V  
0.0 V  
4
(25)  
FCE586  
IFFIL1  
IFFIL2  
5
6
24  
23  
3.6 V  
3.6 V  
3.6 V  
3.6 V  
(24)  
5
6 (23)  
FCE587  
PVHFL  
PVHFH  
PUHF  
7
8
22  
21  
20  
19  
n.a. or 4.8 V  
4.8 V or n.a.  
n.a.  
n.a.  
n.a.  
9
4.8 V  
8
7
FMST  
10  
n.a. or 4.8 V n.a. or 4.8 V  
(21)  
(22)  
9
10  
(19)  
(20)  
FCE588  
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Product specification  
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cable TV and VCR 2-band tuners  
TDA6502; TDA6502A;  
TDA6503; TDA6503A  
DC VOLTAGE  
PIN  
(AVERAGE VALUE)(1)  
SYMBOL  
EQUIVALENT CIRCUIT(2)  
TDA6502;  
TDA6502A TDA6503A  
TDA6503;  
VHF  
UHF  
SW  
11  
12  
13  
14  
15  
18  
17  
16  
15  
14  
5.0 V  
5.0 V  
11  
(18)  
FCE189  
CE/AS  
1.25 V  
1.25 V  
12  
(17)  
FCE191  
DA  
−
−
13  
(16)  
FCE190  
CL  
−
−
14  
(15)  
FCE192  
LOCK/ADC  
4.6 V  
4.6 V  
15  
(14)  
FCE193  
2000 Aug 02  
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Product specification  
5 V mixers/oscillators and synthesizers for  
cable TV and VCR 2-band tuners  
TDA6502; TDA6502A;  
TDA6503; TDA6503A  
DC VOLTAGE  
PIN  
(AVERAGE VALUE)(1)  
SYMBOL  
EQUIVALENT CIRCUIT(2)  
TDA6502;  
TDA6502A TDA6503A  
TDA6503;  
VHF  
UHF  
CP  
16 13  
1 V  
1 V  
16  
(13)  
FCE194  
VT  
17  
12  
VVT  
VVT  
17  
(12)  
FCE589  
XTAL  
18  
11  
2.6 V  
2.6 V  
18  
(11)  
FCE590  
VCC  
19  
20  
10  
9
5.0 V  
2.1 V  
5.0 V  
2.1 V  
supply voltage  
IFOUT  
20  
(9)  
FCE591  
GND  
21  
8
0.0 V  
0.0 V  
21  
(8)  
FCE592  
2000 Aug 02  
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Product specification  
5 V mixers/oscillators and synthesizers for  
cable TV and VCR 2-band tuners  
TDA6502; TDA6502A;  
TDA6503; TDA6503A  
DC VOLTAGE  
PIN  
(AVERAGE VALUE)(1)  
SYMBOL  
EQUIVALENT CIRCUIT(2)  
TDA6502;  
TDA6502A TDA6503A  
TDA6503;  
VHF  
UHF  
OSCGND  
23  
6
0.0 V  
0.0 V  
23  
(6)  
FCE593  
VHFOSCIB  
22  
24  
7
5
1.8 V  
3.0 V  
−
−
VHFOSCOC  
24  
(5)  
22  
(7)  
FCE594  
UHFOSCIB1  
UHFOSCOC1  
UHFOSCOC2  
UHFOSCIB2  
25  
26  
27  
28  
4
3
2
1
−
−
−
−
1.9 V  
2.9 V  
2.9 V  
1.9 V  
(2)  
27  
(3)  
26  
28  
(1)  
25  
(4)  
FCE595  
Notes  
1. Measured in circuit of Fig.19.  
2. The pin numbers in parenthesis represent the TDA6503 and TDA6503A.  
2000 Aug 02  
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Product specification  
5 V mixers/oscillators and synthesizers for  
cable TV and VCR 2-band tuners  
TDA6502; TDA6502A;  
TDA6503; TDA6503A  
15 PACKAGE OUTLINE  
SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm  
SOT341-1  
D
E
A
X
v
c
H
M
A
y
E
Z
28  
15  
Q
A
2
A
(A )  
3
A
1
pin 1 index  
θ
L
p
L
1
14  
detail X  
w
M
b
p
e
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(1)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.  
8o  
0o  
0.21  
0.05  
1.80  
1.65  
0.38  
0.25  
0.20  
0.09  
10.4  
10.0  
5.4  
5.2  
7.9  
7.6  
1.03  
0.63  
0.9  
0.7  
1.1  
0.7  
mm  
2.0  
0.25  
0.65  
1.25  
0.2  
0.13  
0.1  
Note  
1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
EIAJ  
95-02-04  
99-12-27  
SOT341-1  
MO-150  
2000 Aug 02  
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Product specification  
5 V mixers/oscillators and synthesizers for  
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TDA6502; TDA6502A;  
TDA6503; TDA6503A  
16 SOLDERING  
If wave soldering is used the following conditions must be  
observed for optimal results:  
16.1 Introduction to soldering surface mount  
packages  
• Use a double-wave soldering method comprising a  
turbulent wave with high upward pressure followed by a  
smooth laminar wave.  
This text gives a very brief insight to a complex technology.  
A more in-depth account of soldering ICs can be found in  
our “Data Handbook IC26; Integrated Circuit Packages”  
(document order number 9398 652 90011).  
• For packages with leads on two sides and a pitch (e):  
– larger than or equal to 1.27 mm, the footprint  
longitudinal axis is preferred to be parallel to the  
transport direction of the printed-circuit board;  
There is no soldering method that is ideal for all surface  
mount IC packages. Wave soldering is not always suitable  
for surface mount ICs, or for printed-circuit boards with  
high population densities. In these situations reflow  
soldering is often used.  
– smaller than 1.27 mm, the footprint longitudinal axis  
must be parallel to the transport direction of the  
printed-circuit board.  
The footprint must incorporate solder thieves at the  
downstream end.  
16.2 Reflow soldering  
• For packages with leads on four sides, the footprint must  
be placed at a 45° angle to the transport direction of the  
printed-circuit board. The footprint must incorporate  
solder thieves downstream and at the side corners.  
Reflow soldering requires solder paste (a suspension of  
fine solder particles, flux and binding agent) to be applied  
to the printed-circuit board by screen printing, stencilling or  
pressure-syringe dispensing before package placement.  
During placement and before soldering, the package must  
be fixed with a droplet of adhesive. The adhesive can be  
applied by screen printing, pin transfer or syringe  
dispensing. The package can be soldered after the  
adhesive is cured.  
Several methods exist for reflowing; for example,  
infrared/convection heating in a conveyor type oven.  
Throughput times (preheating, soldering and cooling) vary  
between 100 and 200 seconds depending on heating  
method.  
Typical dwell time is 4 seconds at 250 °C.  
A mildly-activated flux will eliminate the need for removal  
of corrosive residues in most applications.  
Typical reflow peak temperatures range from  
215 to 250 °C. The top-surface temperature of the  
packages should preferable be kept below 230 °C.  
16.4 Manual soldering  
16.3 Wave soldering  
Fix the component by first soldering two  
diagonally-opposite end leads. Use a low voltage (24 V or  
less) soldering iron applied to the flat part of the lead.  
Contact time must be limited to 10 seconds at up to  
300 °C.  
Conventional single wave soldering is not recommended  
for surface mount devices (SMDs) or printed-circuit boards  
with a high component density, as solder bridging and  
non-wetting can present major problems.  
To overcome these problems the double-wave soldering  
method was specifically developed.  
When using a dedicated tool, all other leads can be  
soldered in one operation within 2 to 5 seconds between  
270 and 320 °C.  
2000 Aug 02  
38  
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Product specification  
5 V mixers/oscillators and synthesizers for  
cable TV and VCR 2-band tuners  
TDA6502; TDA6502A;  
TDA6503; TDA6503A  
16.5 Suitability of surface mount IC packages for wave and reflow soldering methods  
SOLDERING METHOD  
WAVE  
REFLOW(1)  
not suitable suitable  
PACKAGE  
BGA, LFBGA, SQFP, TFBGA  
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS  
PLCC(3), SO, SOJ  
not suitable(2)  
suitable  
suitable  
suitable  
LQFP, QFP, TQFP  
not recommended(3)(4) suitable  
not recommended(5)  
suitable  
SSOP, TSSOP, VSO  
Notes  
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum  
temperature (with respect to time) and body size of the package, there is a risk that internal or external package  
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the  
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.  
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink  
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).  
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.  
The package footprint must incorporate solder thieves downstream and at the side corners.  
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;  
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.  
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is  
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.  
2000 Aug 02  
39  
Philips Semiconductors  
Product specification  
5 V mixers/oscillators and synthesizers for  
cable TV and VCR 2-band tuners  
TDA6502; TDA6502A;  
TDA6503; TDA6503A  
17 DATA SHEET STATUS  
PRODUCT  
DATA SHEET STATUS  
STATUS  
DEFINITIONS (1)  
Objective specification  
Development This data sheet contains the design target or goal specifications for  
product development. Specification may change in any manner without  
notice.  
Preliminary specification Qualification  
This data sheet contains preliminary data, and supplementary data will be  
published at a later date. Philips Semiconductors reserves the right to  
make changes at any time without notice in order to improve design and  
supply the best possible product.  
Product specification  
Production  
This data sheet contains final specifications. Philips Semiconductors  
reserves the right to make changes at any time without notice in order to  
improve design and supply the best possible product.  
Note  
1. Please consult the most recently issued data sheet before initiating or completing a design.  
18 DEFINITIONS  
19 DISCLAIMERS  
Short-form specification  
The data in a short-form  
Life support applications  
These products are not  
specification is extracted from a full data sheet with the  
same type number and title. For detailed information see  
the relevant data sheet or data handbook.  
designed for use in life support appliances, devices, or  
systems where malfunction of these products can  
reasonably be expected to result in personal injury. Philips  
Semiconductors customers using or selling these products  
for use in such applications do so at their own risk and  
agree to fully indemnify Philips Semiconductors for any  
damages resulting from such application.  
Limiting values definition Limiting values given are in  
accordance with the Absolute Maximum Rating System  
(IEC 60134). Stress above one or more of the limiting  
values may cause permanent damage to the device.  
These are stress ratings only and operation of the device  
at these or at any other conditions above those given in the  
Characteristics sections of the specification is not implied.  
Exposure to limiting values for extended periods may  
affect device reliability.  
Right to make changes  
Philips Semiconductors  
reserves the right to make changes, without notice, in the  
products, including circuits, standard cells, and/or  
software, described or contained herein in order to  
improve design and/or performance. Philips  
Semiconductors assumes no responsibility or liability for  
the use of any of these products, conveys no licence or title  
under any patent, copyright, or mask work right to these  
products, and makes no representations or warranties that  
these products are free from patent, copyright, or mask  
work right infringement, unless otherwise specified.  
Application information  
Applications that are  
described herein for any of these products are for  
illustrative purposes only. Philips Semiconductors make  
no representation or warranty that such applications will be  
suitable for the specified use without further testing or  
modification.  
20 PURCHASE OF PHILIPS I2C COMPONENTS  
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the  
components in the I2C system provided the system conforms to the I2C specification defined by  
Philips. This specification can be ordered using the code 9398 393 40011.  
2000 Aug 02  
40  
Philips Semiconductors  
Product specification  
5 V mixers/oscillators and synthesizers for  
cable TV and VCR 2-band tuners  
TDA6502; TDA6502A;  
TDA6503; TDA6503A  
NOTES  
2000 Aug 02  
41  
Philips Semiconductors  
Product specification  
5 V mixers/oscillators and synthesizers for  
cable TV and VCR 2-band tuners  
TDA6502; TDA6502A;  
TDA6503; TDA6503A  
NOTES  
2000 Aug 02  
42  
Philips Semiconductors  
Product specification  
5 V mixers/oscillators and synthesizers for  
cable TV and VCR 2-band tuners  
TDA6502; TDA6502A;  
TDA6503; TDA6503A  
NOTES  
2000 Aug 02  
43  
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TDA6502; TDA6502A; TDA6503; TDA6503A; 5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band  
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The TDA6502, TDA6502A, TDA6503 and TDA6503A are programmable 2-band mixers/oscillators and synthesizers  
intended for VHF/UHF TV and VCR tuners.  
PC/PC-peripherals  
Cross reference  
Partitioning of the bands is up to the customer as long as VHF is below 500 MHz and UHF is below 900 MHz.  
Models  
Packages  
The devices include two double balanced mixers and two oscillators for the VHF and UHF band respectively, an IF  
amplifier and a PLL synthesizer. The VHF band can be split-up into two sub-bands using a proper oscillator application and  
a switchable inductor.  
Application notes  
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End of Life information  
Datahandbook system  
Two pins are available between the mixer output and the IF amplifier input to enable IF filtering for improved signal  
handling.  
The port register provides four PMOS ports. Band selection is provided by port register UHF. When port register UHF is  
‘on’, the UHF mixer-oscillator is active and the VHF band is switched off. When port register UHF is ‘off’, the VHF mixer-  
oscillator is active and the UHF band is off. Port registers VHFL and VHFH are used to select the VHF sub-bands. Port  
register FMST is a general purpose port, that can be used to switch an FM sound trap. When the ports are used, the sum  
of the drain currents has to be limited to 30 mA.  
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TDA6502; TDA6502A;  
TDA6503; TDA6503A  
The synthesizer consists of a 15-bit programmable divider, a crystal oscillator and its programmable reference divider and  
a phase comparator (phase/frequency detector) combined with a charge pump which drives the tuning amplifier, including  
the 33 V output at pin VT. Depending on the reference divider ratio (64, 80 or 128), the phase comparator operates at 62.5,  
50 or 31.25 kHz with a 4 MHz crystal.  
2 of 4  
50 or 31.25 kHz with a 4 MHz crystal.  
TDA6502; TDA6502A;  
TDA6503; TDA6503A  
Depending on the voltage applied to pin SW the device is operating in the I²C-bus mode or 3-wire bus mode.  
In the 3-wire bus mode, pin LOCK/ADC is the ‘lock’ output of the PLL and is at LOW level when the PLL is locked. Lock  
detector bit FL of the status byte is set to logic 1 when the loop is locked and is read on the SDA line during a READ  
operation in I²C-bus mode only.  
In the I²C-bus mode only, pin LOCK/ADC is the ADC input for digital AFC control. The ADC code is read during a READ  
operation on the I²C-bus.  
In the test mode, in both I²C-bus mode and 3-wire bus mode, pin LOCK/ADC is used as a test output for fREF and 1/2 fDIV  
.
I²C-bus format  
Five serial bytes (including the address byte) are required to address the device, select the VCO frequency, program the  
four ports, set the charge pump current and set the reference divider ratio. The device has four independent I²C-bus  
addresses which can be selected by applying a specific voltage to pin CE/AS.  
3-wire bus format  
Data is transmitted to the device during a HIGH level on pin CE/AS (enable line). The device is accessible with 18-bit and  
19-bit data formats. The first four bits are used to program the PMOS ports and the remaining bits control the  
programmable divider. A 27-bit data format may also be used to set the charge pump current, the reference divider ratio  
and the test modes.  
It is not allowed to address the device with words whose length is different from 18, 19 or 27 bits.  
Features  
l Single-chip 5 V mixer/oscillator and synthesizer for cable TV and VCR tuners  
l Pin-to-pin compatible with TDA6402, TDA6402A, TDA6403 and TDA6403A  
l Universal bus protocol (I²C-bus or 3-wire bus):  
- Bus protocol for 18 or 19-bit transmission (3-wire bus)  
- Extra protocol for 27-bit transmission (test modes and features for 3-wire bus)  
- Address + 4 data bytes transmission (I²C-bus ‘write’ mode)  
- Address + 1 status byte (I²C-bus ‘read’ mode)  
- 4 independent I²C-bus addresses.  
l 1 PMOS buffer for UHF band selection (25 mA)  
l 3 PMOS buffers for general purpose, e.g. 2 VHF sub-bands, FM sound trap (25 mA)  
3 of 4  
l 33 V tuning voltage output  
l In-lock detector  
l 5-step analog-to-digital converter (3 bits in I²C-bus mode)  
l 15-bit programmable divider  
l Programmable reference divider ratio (64, 80 or 128)  
l Programmable charge pump current (60 or 280 µA)  
l Varicap drive disable  
l Balanced mixer with a common emitter input for VHF (single input)  
l Balanced mixer with a common base input for UHF (balanced input)  
l 2-pin common emitter oscillator for VHF  
l 4-pin common emitter oscillator for UHF  
l IF preamplifier with asymmetrical 75 Ohm output impedance able to drive loads from 75 Ohm upwards  
l Low power  
l Low radiation  
l Small size  
l The TDA6502A and TDA6503A differ from the TDA6502 and TDA6503 by the UHF port protocol in the I²C-bus  
mode .  
Applications  
l Cable tuners for TV and VCR (switched concept for VHF).  
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TDA6502; 5 V mixers/oscillators and  
TDA6502A; synthesizers for cable TV and VCR  
TDA6503; 2-band tuners  
02-Aug-00  
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-
Standard Marking * Reel  
Pack, SMD, 13"  
TDA6502ATS/C1  
TDA6502TS/C1  
TDA6503ATS/C1  
TDA6503TS/C1  
9352 639 35118  
Standard Marking * Reel  
Pack, SMD, 13"  
9352 639 36118  
9352 639 37118  
9352 639 38118  
-
-
-
Standard Marking * Reel  
Pack, SMD, 13"  
Standard Marking * Reel  
Pack, SMD, 13"  
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