TDA8035HN_技术文档

TDA8035HN

Smart card interface

Rev. 1.0 — 19 April 2011

Product data sheet

1. General description

The TDA8035 is the cost efficient successor of the well established integrated contact

smart card reader IC TDA8024. It offers a high level of security for the card performing

current limitation, short circuit detection, ESD protection as well as supply supervision.

Operating in 3 V supply domain, the current consumption during the standby mode of the

contact reader is very low and is therefore the ideal component for a power efficient

contact reader.

2. Features and benefits

2.1 Protection of the contact smart card

Thermal and short-circuit protections on all card contacts

Vcc regulation:

5 V, 3 V, 1.8 V ± 5 % on 2 × 220 nF multilayer ceramic capacitors with low ESR

current spikes of 40 nA/s (Vcc = 5 V and 3 V) or 15 nA/s (Vcc = 1.8 V) up to

20 MHz, with controlled rise and fall times, filtered overload detection

approximately 120 mA

Automatic activation and deactivation sequences initiated by software or by hardware

in the event of a short-circuit, card take-off, overheating, falling V_REGV_DD(INTF),V_DDP

Enhanced card-side ElectroStatic Discharge (ESD) protection of (> 8 kV)

Supply supervisor for killing spikes during power on and off:

threshold internally fixed

externally by a resistor bridge

2.2 Easy integration into your contact reader

SW compatible to TDA8024 and TDA8034

5 V, 3 V, 1.8 V smart card supply

DC/DC converter for Vcc generation separately powered from 2.7 V to 5.5 V supply

(VDDP and GNDP)

Very low power consumption in Deep Shutdown mode

Three protected half-duplex bidirectional buffered I/O lines (C4, C7 and C8 )

External clock input up to 26 MHz

Card clock generation up to 20 MHz using pins CLKDIV1 and CLKDIV2 with

synchronous frequency changes of f_XTAL,f_{XTAL/2, XTAL/4}or f_XTAL/8

f

Non-inverted control of pin RST using pin RSTIN

Built-in debouncing on card presence contact

Multiplexed status signal using pin OFFN

TDA8035HN

NXP Semiconductors

Smart card interface

Chip Select digital input for parallel operation of several TDA8035 ICs.

2.2.1 Other

HVQFN32 package

Compliant with ISO 7816, NDS and EMV 4.2 payment systems

3. Applications

Pay TV

Electronic payment

Identification

IC card readers for banking

4. Quick reference data

Table 1.

Quick reference data

V_DDP= 3.3 V; V_DD(INTF)= 3.3 V; f_Xtal= 10 MHz; GND = 0 V; T_amb= 25 °C; unless otherwise specified

Symbol

Supply

V_DDP

Parameter

Conditions

Min

Typ

Max

Unit

power supply voltage

interface supply voltage

power supply current

2.7

1.6

-

3.3

0.1

5.5

3.6

3

V

V_DD(INTF)

I_DDP

V

Deep Shutdown mode;

μA

f_XTAL= stopped;

Shutdown mode;

f_XTAL= stopped;

-

300

500

μA

active mode; V_CC= +5 V

CLK = f_XTAL/2; no load

-

5

mA

active mode; CLK =

f_XTAL/2 ; V_CC= +5 V; Icc =

65 mA

220

active mode; CLK =

-

160

120

1

mA

μA

f

_XTAL/2 ; V_CC= +3 V; I_CC=

65 mA

active mode; CLK =

f_XTAL/2 ; V_CC= +1.8 V; Icc =

35 mA

I_DD(INTF)

interface supply current

Deep Shutdown mode;

f

_XTAL= stopped;

present card

Shutdown mode;

f_XTAL= stopped;

-

1

μA

present card

Internal supply voltage

V_DD

supply voltage

1.62

1.8

1.98

V

Card supply voltage: pin V_CC

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Product data sheet

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Smart card interface

Table 1.

Quick reference data …continued

V_DDP= 3.3 V; V_DD(INTF)= 3.3 V; f_Xtal= 10 MHz; GND = 0 V; T_amb= 25 °C; unless otherwise specified

Symbol

Parameter

Conditions

Min

4.75

4.65

Typ

5.0

Max

5.25

Unit

V

V_CC

supply voltage

5 V card; DC I_CC< 65 mA

5 V card; AC current spikes

of 40 nAs

V

3 V card; DC I_CC< 65 mA

2.85

2.76

-

3.15

3.24

V

3 V card; AC current spikes

of 40 nAs

1.8 V card; DC I_CC< 35 mA

1.71

1.66

-

1.89

1.94

V

1.8 V card; AC current

spikes of 15 nAs

V_ripple(p-p)

I_CC

peak-to-peak ripple voltage

supply current

from 20 kHz to 200 MHz

V_CC= 5 V or 3 V

V_CC= 1.8 V

-

300

65

mV

mA

35

General

t_deact

deactivation time

total sequence

35

-

90

-

250

0.45

+85

μs

W

P_tot

total power dissipation

ambient temperature

T_amb= −40 °C to +85 °C

T_amb

-25

-

°C

5. Ordering information

Table 2.

Ordering information

Type number

Package

Name

Description

Version

TDA8035HN/C1

HVQFN32

plastic thermal enhanced very thin quad flat package; no leads;

SOT617-7

32 terminals; body 5 × 5 × 0.85

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6. Block diagram

V

DD(INTF)

VDDP

330 nF

100 nF

10 μF

100 nF

V

DD(INTF)

VDDP

PORADJ VREG

GND

GNDP

SAP SAM SBP SBM

CS

VUP

1 μF

INTERNAL

deep

shutdown

cmdvccn

EN_5V/3VN

EN_1.8VN

RSTIN

DCDC

REGULATOR

DEEP

CONVERTER

SHUTDOWN

VCC

LATCH

CLKDIV1

CLKDIV2

ISO7816

READER

INTERFACE

reset and

supalarm

2 ×

INPUT SENSE

GNDC

220 nF

SUPERVISOR

HOST

INTERFACE

DEEP SHUTDOWN

RST

CLK

AUX1

AUX2

IO

IOUC

AUX1UC

AUX2UC

BANDGAP

C5

C1

C2

C3

C4

H

Z

UC

TDA8035

C6

C7

C8

INTERNAL

OSCILLATOR

vddi

THERMAL

configurations

bus for smartcard

reader interface

PROTECTION

XTAL1

OFFN

H

Z

CRYSTAL

OSCILLATOR

DIGITAL

SEQUENCER

XTAL2

interuption

PRESN

001aan745

Fig 1. Block diagram

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7. Pinning information

7.1 Pinning

terminal 1

index area

I/OUC

PORADJ

1

2

3

4

5

6

7

8

24 CLK

23 RST

22 VCC

21 VUP

20 SAP

19 SBP

18 VDDP

17 SBM

CMDVCCN

VDD(INTF)

CLKDIV1

TDA8035

CLKDIV2

EN_5V/3VN

EN_1.8VN

001aan746

Transparent top view

Fig 2. Pin configuration HVQFN32

7.2 Pin description

Table 3.

Symbol

I/OUC

Pin description

1

Supply

Type

I/O

I

Description

host data I/O line (internal 10k pullup resistor to V_DD(INTF)

V_DD(INTF)

)

PORADJ

2

Input for V_DD(INTF)supervisor. PORADJ threshold can be changed

with an external R bridge

CMDVCCN

V_DD(INTF)

3

4

5

6

7

V_DD(INTF)

I

start activation sequence input from the host (active LOW)

interface supply voltage

supply

CLKDIV1

CLKDIV2

EN_5V/3VN

I

control with CLKDIV2 for choosing CLK frequency see Table 4

control with CLKDIV1 for choosing CLK frequency see Table 4

control signal for selecting Vcc = 5 V (HIGH) or Vcc = 3 V (LOW) if

EN_1.8 VN = High

EN_1.8 VN

RSTIN

8

V_DD(INTF)

I

control signal for selecting Vcc = 1.8V (low)

card reset input from the host (active HIGH)

9

I

OFFN

10

O

NMOS interrupt to the host (active LOW) with 10k internal pull up

resistor to V_DD(INTF)(See fault detection)

GND

11

12

13

14

15

-

supply

ground

XTAL1

XTAL2

VREG

SAM

V_DD(INTF)

V_DDP

I

crystal connection

Internal supply voltage

O

supply

I/O

V_DDP

DC/DC converter capacitor ; connected between SAM and SAP; C =

330nF with ESR < 100mΩ

GNDP

16

-

supply

DC/DC converter power supply ground

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Table 3.

Symbol

SBM

Pin description …continued

Supply

Type

Description

17

V_DDP

I/O

DC/DC converter capacitor ; connected between SBM and SBP; C =

330nF with ESR < 100mΩ

V_DDP

SBP

18

19

V_DDP

supply

I/O

Power supply voltage

DC/DC converter capacitor ; connected between SBM and SBP; C =

330nF with ESR < 100mΩ

SAP

VUP

Vcc

20

21

22

V_DDP

Vcc

I/O

O

DC/DC converter capacitor ; connected between SAM and SAP; C =

330nF with ESR < 100mΩ

DC/DC converter output decoupling capacitor connected between

VUP and GNDP; C = 1uF with ESR < 100mΩ

supply for the card (C1)( decouple to GND with 2 × 220nF capacitors

with ESR < 100mΩ).

RST

23

24

25

26

Vcc

-

O

card reset (C2)

CLK

O

clock to the card (C3)

card signal ground

GNDC

AUX1

supply

I/O

Vcc

auxiliary data line to/from the card (C4)(internal 10 k pull up resistor to

Vcc )

AUX2

27

Vcc

I/O

auxiliary data line to/from the card (C8)(internal 10 k pull up resistor to

Vcc )

I/O

28

29

30

Vcc

I/O

data line to/from the card (C7)(internal 10 k pull up resistor toVcc)

Chip Select input from the host ( active High )

CS

V_DD(INTF)

I

PRESN

card presence contact input (active LOW); if PRESN is true, then the

card is considered as present. A debouncing feature of 4.05 ms typ.

is built in.

AUX1UC

AUX2UC

31

32

V_DD(INTF)

I/O

auxiliary data line to/from the host (internal 10 k pull up resistor to

V_DD(INTF)

auxiliary data line to/from the host (internal 10 k pull up resistor to

V_DD(INTF)

)

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Product data sheet

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8. Functional description

Remark: Throughout this document the ISO 7816 terminology conventions have been

adhered to and it is assumed that the reader is familiar with these.

8.1 Power Supply

Power supply voltage V_DDPshould be in the range from 2.7 to 5.5 V

All interface signals with the system controller are referenced to V_DD(INTF). All card

contacts remain inactive during powering up or powering down.

Internal regulator VREG should be in the range of 1.8 V

After powering the device, OFFN remains Low until CMDVCCN is set High and PRESN is

Low .

During power off, OFFN falls Low when V_DDPis below the threshold voltage falling.

The frequency of the internal oscillator Foscint used for the activation sequences is put in

low frequency mode in order to save power consumption as long as CMDVCCN is kept at

high level (card not activated).

This device includes DC/DC converter to generate the 5 V, 3 V or 1.8 V card supply

voltage (Vcc). The DC/DC converter should be supplied separately by Vddp and Gndp.

The DC/DC converter operates as a voltage tripler, doubler or follower according to the

respective values of Vcc and Vddp.

The operating mode is as follows (see Figure 3):

• Vcc = 5 V & Vddp > 3.8 V ; voltage doubler

• Vcc = 5 V & Vddp < 3.6 V; voltage tripler

• Vcc = 3 V & Vddp > 3.8 V; voltage follower

• Vcc = 3 V & Vddp < 3.6 V; voltage doubler

• Vcc = 1.8 V & Vddp > 3.8 V; voltage doubler

• Vcc = 1.8 V & Vddp < 3.6 V; voltage tripler

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8.2 Voltage supervisor

Vreg

vbg

vreg

VDDP

Deep_shutdown

VDD(INTF)

vbg

Poradj

001aan747

Fig 3. Block voltage supervisor

The voltage supervisor is used as a power on reset, and also as supply drop detection

during a card session. The threshold of the voltage supervisor is set internally in the IC for

V

_DDPand V_REGwhereas it can be adjusted externally for V_DD(INTF)using the PORADJ pin.

As long as V_REGis less than Vth(V_REG) + Vhys(V_REG), the IC will remain inactive whatever

the levels on the command lines are. This also lasts for the duration of tw after V_REGhas

reached a level higher than Vth(V_REG) + Vhys(V_REG).The outputs of the V_DDP,V_REGand

V

_DD(INTF)supervisors are combined and sent to a digital controller in order to reset the

TDA8035. This defined reset pulse of approximately 5.7 ms (tw=2048 × 1/(fosc(int)_Low)

is used internally for maintaining the IC in a inactive mode during the supply voltage

power-on; (see following pictures). When V_REGfalls below Vth(V_REG) or when V

_DD(INTF)falls below Vthextf or when V_DDPfalls below Vth(VDDP) , a deactivation sequence

is performed.

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VDDP

VREG

Vth_vddp_Ih

Vt

Supervisor outputs

vsup

X

Tw

reset

X

2 Tw

supalarm

Supervisor inputs

Deep_shutdown

X

Oscint

180 kHz

1.2 V

Vbg

IC pins

OFFN

X

debouncing

001aan748

Fig 4. Voltage supervisor

Vddp

Vth_Vddp_Ih

2.65 V

2.5 V

Vth_vddp_hI

1

Vreg

1.8 V

1

Vsup

2

3

Supalarm

3

Tw

100 μs analog delay

Reset

Start debouncing if a card

has been inserted during

shutdown mode

001aan749

Fig 5. Voltage supervisor

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8.3 Clock circuitry

DIGITAL

Enclkin

clkxtal

MUX

XTAL

001aan750

Fig 6. Switch external clock

To generate the card clock CLK, the TDA8035 can either use an external clock provided

on XTAL1 pin or a crystal oscillator connected on both XTAL1 and XTAL2 pins. The

TDA8035 automatically detects if an external clock is provided on XTAL1. So, there is no

need of an extra pin to configure the clock source (external clock or crystal).

The automatic clock source detection is performed on each activation command

(CMDVCCN pin falling edge). During a time window defined by the internal oscillator, the

presence of an external clock on XTAL1 pin is checked. If a clock is detected, the crystal

oscillator is kept stopped, else, the crystal oscillator is started. It is mandatory when an

external clock is used, that the clock is applied on XTAL1 before CMDVCCN falling edge

signal.

The frequency may be chosen as f_XTAL, f_XTAL/2, f_XTAL/4or f_XTAL/8via the pins CLKDIV1 and

CLKDIV2. (Both selection inputs shall not be changed simultaneously: 10 ns minimum are

required between changes on CLKDIV1/CLKDIV2).

The frequency change is synchronous, which means that during transition, no pulse is

shorter than 45 % of the smallest period and that the first and last clock pulse around the

change has the correct width. When changing dynamically the frequency, the change is

effective only 10 periods of XTAL1 after the command.

The duty cycle on pin CLK shall be between 45 % and 55 % :

• When an external clock is used on XTAL1 pin , it should have a duty cycle of 48

% to 52 % when f_XTALis used and rise and fall times shall respect values mentioned

on table 7 t_r(i), t_f(i). It has to connect a 56 pF serial capacitor .

• CLK frequency is f_XTAL,f_XTAL/2,f_XTAL/4or f_XTAL/8

:

It is guaranteed between 45 % and 55 % of the period by the frequency dividers.

Table 4.

Clock configuration

CLKDIV1

CLKDIV2

CLK

0

1

0

1

0

f_XTAL/8

f_XTAL/4

f_XTAL/2

f_XTAL

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8.4 I/O circuitry

The three data lines I/O, AUX1 and AUX2 are identical.

The Idle state is realized by both lines (I/O and I/OUC) being pulled HIGH via a 10 k

resistor (I/O to V_CCand I/OUC to V_DD(INTF))

.

I/O is referenced to V_CC, and I/OUC to V_DD(INTF), thus allowing operation with

V_CC≠ V_DD(INTF)

.

The first side on which a falling edge occurs becomes the master. An anti-latch circuit

disables the detection of falling edges on the other line, which becomes a slave.

After a time delay t_d(edge), the logic 0 present on the master side is transmitted to the slave

side.

When the master side returns to logic 1, the slave side transmits the logic 1 during the

time delay tpu, and then both sides return to their Idle states.

This active pull-up feature ensures fast Low to High transitions; it is able to deliver more

than 1 mA up to an output voltage of 0.9 V_CCon a 80 pF load. At the end of the active

pull-up pulse, the output voltage only depends on the internal pull-up resistor, and on the

load current.

The current to/from the cards I/O lines is internally limited to 15 mA.

The maximum frequency on these lines is 1.5 MHz.

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8.5 CS control

The CS (Chip Select) input allows multiple devices to operate in parallel. When CS is

high, the system interface signals operate as described. When CS is low , the signals

CMDVCCN, RSTIN, CLKDIV1, CLKDIV2, EN5V/3VN and EN1V8N are latched. I/OUC,

AUX1UC and AUX2UC are set to high impedance pull up mode and won’t pass data to or

from the smart card. OFFN output is tri-stated.

8.6 Shutdown mode and Deep Shutdown mode

After power-on reset, the circuit enters the Shutdown mode if CMDVCCN input pin is to a

logic-High. A minimum number of circuits are active while waiting for the micro-controller

to start a session.

1. All card contacts are inactive (approximately 200 Ω to GND).

2. I/OUC, AUX1UC and AUX2UC are high impedance (10 k pull-up resistor connected

to V_DDI).

3. Voltage generators are stopped.

4. Voltage supervisor is active.

5. The internal oscillator runs at its low frequency.

A Deep Shutdown mode can be entered by forcing CMDVCCN input pin to a logic-High

state and EN5V/3VN, EN1V8N input pins to a logic-Low state. Deep Shutdown mode can

only be entered when the smart card reader is inactive. In Deep Shutdown mode, all

circuits are disabled. The OFFN pin follows the status of PRESN pin. To exit Deep

Shutdown mode, change the state of one or more of the three control pins. Figure 8

shows the control sequence for entering and exiting.

DEACTIVATION

SEQUENCE

CMDVCCN

EN1V8N

EN5V/3VN

Shutdown

debounce

Mode

(internal pin)

Activation

Deep Shutdown

Activation

OFFN

PRESN

VCC

001aan751

Fig 7. Shutdown mode and Deep Shutdown mode

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8.7 Activation sequence

The following sequence then occurs with crystal oscillator (see Figure 8):

T = 64 × Toscint(freq high)

1. CMDVCCN is pulled Low (t0)

2. Crystal oscillator start up time (t0).

3. The internal oscillator changes to its high frequency & DC/DC starts (t1 = t0 + 768 ×

Tosc_Low)

4. V_CCrises from 0 to selected Vcc value ( 5 V, 3 V, 1.8 V ) with a controlled slope

(t₂= t₁+ 3T/2)

5. I/O, AUX1 and AUX2 are enabled (t₃= t₁+ 10T) (They were pulled LOW until this

moment)

6. CLK is applied to the C3 contact (t₄= t₃+ x) with 200 ns < x < 10 x 1/fXtal

7. RST is enabled (t₅= t₁+ 13T).

Oscint

CMDVCCN

Xtal1

low frequency

high frequency

VUP

VCC

IO

CLK

RST

T / 2

≈ 3 ms

t0

t1

t2

t3 t4

t5

001aan752

Fig 8. Activation sequence at t3

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8.8 Deactivation sequence

When a session is completed, the micro-controller sets the CMDVCCN line to the HIGH

state. The circuit then executes an automatic deactivation sequence by counting the

sequencer back and ends in the inactive state (see Figure 9):

1. RST goes LOW (t₁₁= t₁₀+ 3T/64)

2. CLK is stopped LOW (t₁₂= t₁₁+T/2)

3. I/O, AUX1 and AUX2 are pulled LOW (t₁₃= t₁₁+ T)

4. V_CCfalls to zero (t₁₄= t₁₁+ 3T/2) (The deactivation sequence is completed when V_CC

reaches its inactive state)

5. VUP falls to zero (t₁₅= t₁₁+ 7T/2)

6. V_CC< 0.4 V (t_de= t₁₁+ 3T/2 + Vcc fall time)

7. All card contacts become low-impedance to GND (I/OUC, AUX1UC and AUX2UC

remain pulled up to V_DD(INTF)via a 10 kΩ resistor).

8. The internal oscillator goes back to its lower frequency.

CMDVCCN

RST

CLK

I/O

VCC

VUP

Xtal1

Oscint

high frequency

low frequency

T / 2

t10

t11

t12 t13 t14

t15

001aan753

Fig 9. Deactivation sequence

8.9 VCC regulator

V_CCbuffer is able to continuously deliver up to 65mA at Vcc = 5 V, 65 mA at Vcc = 3 V,

35 mA at Vcc =1.8 V .

It has an internal overload detection at approximately 125 mA.

This detection is internally filtered, allowing spurious current pulses of some ms up to

200 mA to be drawn by the card without causing a deactivation. (The average current

value must stay below maximum).

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8.10 Fault detection

The following fault conditions are monitored by the circuit:

1. Short-circuit or high current on V_CC

2. Card removal during transaction

3. V_DDPor V_DD(INTF)or Vreg dropping

4. Overheating.

There are two different cases (see Figure 10 on page 16):

1. CMDVCCN High: (outside a card session) then, OFFN is Low if the card is not in the

reader, and High if the card is in the reader. A supply voltage drop on V_DDPis detected

by the supply supervisor, generates an internal power-on reset pulse, but does not act

upon OFFN. The card is not powered-up, so no short-circuit or overheating is

detected.

2. CMDVCCN Low: (within a card session) then, OFFN falls Low in any of the

aforementioned cases. As soon as the fault is detected, an emergency deactivation is

automatically performed. When the system controller sets CMDVCCN back to High, it

may sense OFFN again after complete deactivation sequence in order to distinguish

between a hardware problem or a card extraction (OFFN will then go back High if the

card is still present).

Depending on the type of card presence switch within the connector (normally close or

normally open), and on the mechanical characteristics of the switch, a bouncing may

occur on PRESN signal at card insertion or withdrawal. Consequently, a debounce feature

of approximately 4.05 ms (t_deb= 1280 × 1/(fosc(int)_Low) is integrated in the device.

Figure 11 on page 16 When the card is inserted, OFFN goes High only at the end of the

debouncing time.

When the card is extracted, an automatic deactivation sequence of the card is performed

on the first True/False transition on PRESN, and OFFN goes Low .

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OFFN

PRESN

RST

CLK

I/O

VCC

VUP

Xtal1

Oscint

high frequency

low frequency

T / 2

t10 = t11 t12 t13 t14

t15

001aan754

Fig 10. Emergency deactivation sequence (Card extraction)

PRESN

OFFN

CMDVCCN

tdeb

VCC

Deactivation caused by

cards withdrawal

Deactivation caused by

short circuit

001aan757

Fig 11. Behavior of OFFN, CMDVCCN, PRESN and Vcc

TDA8035HN

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Product data sheet

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16 of 32

TDA8035HN

NXP Semiconductors

Smart card interface

9. Limiting values

All card contacts are protected against any short with any other card contact.

Stress beyond these levels may cause permanent damage to the device. This is a stress

rating only and functional operation of the device under this condition is not implied.

Table 5.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

−0.3

Max

6

Unit

V

V_DDP

power supply voltage

V_DD(INTF)interface supply voltage

4.1

V

V_IH

High-level input voltage CS, PRESN,

CMDVCCN, CLKDIV2,

V

CLKDIV1, EN_1.8VN,

EN_5V/3VN, RSTIN,

OFFN, PORADJ, XTAL1,

I/OUC, AUX1UC, AUX2UC,

V_DDP, V_DD(INTF)

I/O, RST, AUX1, AUX2 and

CLK

−0.3

5.75

V

T_amb

T_stg

T_j

ambient temperature

storage temperature

junction temperature

−25

−55

+85

°C

W

+150

+125

0.45

+10

P_tot

V_ESD

total power dissipation T_amb= −40 to +85 °C

electrostatic discharge Human Body Model (HBM)

−10

kV

voltage

on card pins I/O, RST, V_CC,

AUX1, CLK, AUX2, PRESN

within typical application

Human Body Model (HBM)

on all other pins

−2

+2

kV

V

−200

+200

Machine Model (MM) on

all pins

Field Charged Device

−500

+500

V

Model (FCDM) on all pins

10. Thermal characteristics

Table 6.

Symbol

R_th(j-a)

Thermal characteristics

Package name Parameter

Conditions

Typ

Unit

HVQFN32

thermal resistance from junction in free air with 4 thermal vias

55

K/W

to ambient

on pcb

in free air without thermal

vias on pcb

63

K/W

TDA8035HN

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Product data sheet

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17 of 32

TDA8035HN

NXP Semiconductors

Smart card interface

11. Characteristics

Table 7.

Characteristics of IC

V_DDP= 3.3 V; V_DD(INTF)= 3.3 V; f_Xtal= 10 MHz; GND = 0 V; T_amb=25 °C; unless otherwise specified

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Supply voltage

V_DDP

power supply voltage

interface supply voltage

power supply current

2.7

1.6

-

3.3

0.1

5.5

3.6

3

V

V_DD(INTF)

I_DDP

V

Deep Shutdown mode;

f_XTAL= stopped

μA

Shutdown mode;

-

300

500

μA

f

_XTAL= stopped

active mode; CLK = f_XTA/2;

_CC= +5 V; no load

-

5

mA

μA

V

active mode; CLK = f_XTAL/2 ;

V_CC= +5 V; I_CC= 65 mA

220

160

120

1

active mode; CLK = f_XTAL/2 ;

V_CC= +3 V; Icc = 65 mA

active mode; CLK=f_XTAL/2 ;

V_CC= +1.8 V; I_CC= 35 mA

I_DD(INTF)

interface supply current

Deep Shutdown mode

f_XTAL= stopped;

present card

Shutdown mode

-

1

μA

f_XTAL= stopped;

present card

V_th(

V_ththreshold voltage

Internal voltage regulator

falling

1.38

1.45

1.52

V

)

VREG

V_hys(

V_hyshysteresis voltage

V_ththreshold voltage

V_hyshysteresis voltage

pulse width

Internal voltage regulator

Pin V_DDPfalling

Pin V_DDP

90

100

2.25

100

6.5

110

2.35

110

8.9

mV

V

)

VREG

V_th(VDDP)

V_hys(VDDP)

t_W

2.15

90

mV

ms

V

3

V_{th(L)(PORADJ)}

LOW-level threshold

voltage on pin PORADJ

External resistors on

PORADJ

0.68

0.86

1.04

V_hys(PORADJ)

V_hyshysteresis voltage

leakage current

Pin PORADJ

30

60

-

90

1

mV

I_L

−1

μA

V_REG

V_O

t_r

output voltage

rise time

1.62

-

1.8

-

1.98

200

V

Exit of deep Shutdown mode

μs

VUP ( DC/DC converter)

V_OHoutput voltage

V_CC= 5 V, I_CC< 65 mA DC

V_CC= 3 V, I_CC< 65 mA DC

V_CC= 1.8 V, I_CC< 35 mA DC

5.10

3.50

5.10

5.60

3.95

5.60

6.10

4.40

6.10

V

Card supply voltage (V_CC) (2 ceramic multilayer capacitances with low ESR 220 nF/220nF should be used in order

to meet these specs)^[1]

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Product data sheet

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TDA8035HN

NXP Semiconductors

Smart card interface

Table 7.

Characteristics of IC …continued

V_DDP= 3.3 V; V_DD(INTF)= 3.3 V; f_Xtal= 10 MHz; GND = 0 V; T_amb=25 °C; unless otherwise specified

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

C_dec

decoupling capacitance

connected on V_CC(220 nF +

220 nF 10 % )

396

-

484

nF

V_o

I_o

output voltage

output current

supply voltage

inactive mode; no load

inactive mode; I_o= 1 mA

inactive mode &

−0.1

-

+0.1

+0.3

−1

V

mA

at grounded pin V_CC

V_CC

active mode; 5 V card;

I_CC< 65 mA DC

4.75

2.85

1.71

4.65

5.0

5.25

3.15

1.89

5.25

V

active mode; 3 V card;

3.05

1.83

5.0

I_CC< 65 mA DC

active mode; 1.8 V card;

I_CC< 35 mA DC

active mode; current pulses

of 40 nAs with I_CC< 200 mA,

t < 400 ns; 5 V card

active mode; current pulses

of 40 nAs with I_CC< 200 mA,

t < 400 ns; 3 V card

2.76

1.66

-

3.20

1.94

350

V

active mode; current pulses

of 15 nAs with I_CC< 200 mA,

t < 400 ns;1.8 V card

V

V_ripple(p-p)

I_CC

peak to peak ripple

voltage

from 20 kHz to 200 MHz

mV

supply current

V_CC= 0 V to 5 V, 3V

V_CC= 0 V to 1.8V

5 V card

-

65

mA

-

35

mA

SR

slew rate

0.055

0.040

0.025

0.18

0.8

V/μs

3 V card

1.8 V card

Crystal oscillator (XTAL1 and XTAL2)

C_ext

external capacitance

connected on pins

-

33

pF

XTAL1/XTAL2 (depending on

specification of crystal or

resonator used)

f_XTAL

crystal frequency

2

0

-

27

MHz

f_XTAL1

External frequency

applied on XTAL1

with 56 pF serial capacitor

V_IL

V_IH

LOW-level input voltage

−0.3

-

0.3

V_DD(INTF)

V

HIGH-level input voltage

0.7V_DD(IN

-

V_DD(INTF)

+ 0.3

TF)

TDA8035HN

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Product data sheet

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19 of 32

TDA8035HN

NXP Semiconductors

Smart card interface

Table 7.

Characteristics of IC …continued

V_DDP= 3.3 V; V_DD(INTF)= 3.3 V; f_Xtal= 10 MHz; GND = 0 V; T_amb=25 °C; unless otherwise specified

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

t_r(i), t_f(i)

input rise time, input fall

times

f_CLK= f_XTAL1= 20 MHz on

external clock

-

4

ns

f_CLK= f_XTAL1= 10 MHz on

external clock

-

8

ns

f_CLK= f_XTAL1= 5 MHz on

external clock

16

Data lines (pins I/O, I/OUC, AUX1, AUX2, AUXIUC, AUX2UC )

t_d

delay time

falling edge on pins I/O and

I/OUC or I/OUC and I/O

-

200

ns

t_w(pu)

f_max

C_i

pull-up pulse width

maximum frequency

input capacitance

200

400

1

ns

on data lines

-

MHz

pF

10

Data lines to the card (pins I/O, AUX1, AUX2); (Integrated 10k pull up resistor connected to V_CC

)

V_o

output voltage

inactive mode; no load

inactive mode; I_o= 1 mA

inactive mode &

0

-

0.1

0.3

−1

V

I_o

output current

mA

at grounded pin I/O

V_OL

LOW-level output voltage I_OL= 1 mA

I_OL≥ 15 mA

0

-

0.3

V

V_CC− 0.4 -

V_CC

V_OH

HIGH-level output voltage No DC load

0.9 V_CC

-

V_CC+ 0.1 V

I_OH< −40 μA 5 V or 3 V

0.75 V_CC

I_OH< −20 μA 1.8 V card

I_OH≥ −15 mA

0.75 V_CC

0

-

0.4

0.8

V

V_IL

V_IH

LOW-level input voltage

HIGH-level input voltage V_CC= +5 V

V_CC= +3 V or 1.8 V

on I/O

−0.3

-

0.6Vcc

-

V_CC+ 0.3 V

0.7Vcc

-

V_hys

I_IL

hysteresis voltage

30

-

75

-

120

600

10

mV

LOW-level input current

on I/O; V_IL= 0

μA

I_LH

HIGH-level leakage

current

on I/O; V_IH= V_CC

-

t_r(i), t_f(i)

t_r(o), t_f(o)

input rise time, input fall

time

from V_ILmax to V_IHmin

-

1.2

0.1

μs

output rise time, output

fall time

C_L<= 80 pF; 10 % to 90 %

from 0 to V_CC

R_pu

I_pu

pull-up resistance

pull-up current

connected to V_CC

8k

10k

12k

Ω

V_OH= 0.9 V_CC, C = 80 pF

−8

−6

−4

mA

Data lines to the system; pins I/OμC, AUX1μC, AUX2μC (Integrated 10k pull up resistor to V_DD(INTF)

)

V_OL

LOW level output voltage I_OL= 1 mA

0

-

0.3

V

TDA8035HN

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Product data sheet

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TDA8035HN

NXP Semiconductors

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Table 7.

Characteristics of IC …continued

V_DDP= 3.3 V; V_DD(INTF)= 3.3 V; f_Xtal= 10 MHz; GND = 0 V; T_amb=25 °C; unless otherwise specified

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_OH

HIGH level output voltage No DC load

0.9

V_DD(INTF)

-

V_DD(INTF)

+ 0.1

V

I_OH≤ 40 μA; V_DDI>2V

0.75

V_DD(INTF)

-

V_DD(INTF)

+ 0.1

V

I_OH≤ 20 μA; V_DDI<2V

0.75

V_DD(INTF)

+ 0.1

V

V_IL

LOW-level input voltage

HIGH-level input voltage

hysteresis voltage

−0.3

0.3

V

V_DD(INTF)

V_IH

V_hys

I_LH

0.7

V_DD(INTF)

+ 0.3

V

on I/Ouc

0.05

-

0.25

V

V_DD(INTF)

HIGH-level input leakage V_IH= V_DDI

current

10

μA

I_IL

LOW-level input current

pull-up resistance

V_IL= 0

600

12k

1.2

0.1

μA

Ω

R_pu

connected to V_DD(INTF)

from V_ILmax to V_IHmin

8k

-

10k

t_r(i), t_f(i)

t_r(o), t_f(o)

input rise & fall times

output rise & fall times

-

μs

C_L≤ 30 pF; 10 % to 90 %

-

from 0 to V_DD(INTF)

I_pu

pull up current

V_OH= 0.9 V_DD, C = 30 pF

−1

-

mA

Internal oscillator

f_osc(int)internal oscillator

frequency

Reset output to the card (RST)

inactive state : osc(int)_Low

active state : osc(int)_High

230

2.0

315

2.5

430

3.0

kHz

MHz

V_o

output voltage

inactive mode; no load

inactive mode; I_o= 1 mA

inactive mode &

0

-

0.1

0.3

−1

V

I_o

output current

mA

at grounded pin RST

t_d

between RSTIn and RST RST enabled

-

200

0.3

0.2

ns

V

V_OL

LOW level output voltage I_OL= 200 μA ,V_CC= +5 V

0

I_OL= 200 μA ,V_CC= +3 V or

V

1.8 V

I_OL= 20 mA (current limit)

HIGH level output voltage I_OH= −200 μA

I_OH= −20 mA (current limit)

V_CC− 0.4 -

V_CC

0.4

V

V_OH

0.9 V_CC

-

V

0

-

V

tr, tf

rise and fall time

C_L= 100 pF

0.1

us

V_CC= +5 V and +3 V

rise and fall time

C_L= 100 pF

V_CC= +18 V

-

0.2

us

Clock output to the card (CLK)

V_o

output voltage

inactive mode; no load

inactive mode; I_o= 1 mA

0

-

0.1

0.3

V

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TDA8035HN

NXP Semiconductors

Smart card interface

Table 7.

Characteristics of IC …continued

V_DDP= 3.3 V; V_DD(INTF)= 3.3 V; f_Xtal= 10 MHz; GND = 0 V; T_amb=25 °C; unless otherwise specified

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

I_o

output current

inactive mode &

at grounded pin CLK

-

−1

mA

V_OL

LOW level output voltage I_OL= 200 μA

I_OL= 70 mA (current limit)

HIGH level output voltage I_OH= −200 μA

I_OH= −70 mA (current limit)

C_L= 30 pF ^[2]

0

-

0.3

V_CC

0.4

16

V

V_CC− 0.4 -

V

V_OH

0.9 V_CC

-

V

0

V

t_r

rise time

-

ns

MHz

%

t_f

fall time

C_L= 30 pF ^[2]

-

16

f_CLK

frequency on pin CLK

duty cycle

operational

C_L= 30 pF ^[2]

0

20

45

0.2

55

SR

slew rate

rise and fall; C_L= 30 pF; V_CC

= +5 V

-

V/ns

rise and fall; C_L= 30 pF; V_CC

= +3 V

0.12

-

V/ns

rise and fall; C_L= 30 pF; V_CC

= +1.8 V

0.072

Control inputs (pins CS, CMDVCCN, CLKDIV1, CLKDIV2, RSTIN, EN_5V/ 3VN, EN_1.8VN)^[3]

V_IL

V_IH

V_hys

I_LL

LOW-level input voltage

HIGH-level input voltage

hysteresis voltage

−0.3

-

0.3

V_DD(INTF)

V

0.7

V_DD(INTF)

+ 0.3

V

on control input

0.05

V_DD(INTF)

0.25

V_DD(INTF)

V

LOW-level input leakage V_IL= 0

current

-

1

μA

I_LH

HIGH-level input leakage V_IH= V_DD(INTF)

current

Card presence input (PRESN); PRESN has an integrated pull down resistor^[3]

V_IL

V_IH

V_hys

I_LL

LOW-level input voltage

HIGH-level input voltage

hysteresis voltage

−0.3

-

0.3

V_DD(INTF)

V

0.7

V_DD(INTF)

+ 0.3

V

0.05

V_DD(INTF)

0.1

V_DD(INTF)

V

LOW-level input leakage V_IL= 0

current

-

1

5

μA

I_LH

HIGH-level input leakage V_IH= V_DD(INTF)

current

OFFN output (pin OFFN is an NMOS drain with a 10k pull up resistor to V_DD(INTF)

)

V_OL

V_OH

LOW level output voltage I_OL= 2 mA

0

-

0.3

12

V

HIGH level output voltage I_OH= −15 μA

0.75

V_DD(INTF)

R_pu

pull-up resistance

8

10

kΩ

Protections and limitations

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Product data sheet

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TDA8035HN

NXP Semiconductors

Smart card interface

Table 7.

Characteristics of IC …continued

V_DDP= 3.3 V; V_DD(INTF)= 3.3 V; f_Xtal= 10 MHz; GND = 0 V; T_amb=25 °C; unless otherwise specified

Symbol

T_sd

Parameter

Conditions

Min

-

Typ

150

-

Max

-

Unit

°C

shutdown temperature

output current limit

at die

I_Olim

on pin I/O

−15

−70

−20

90

+15

+70

+20

160

260

150

250

mA

on pin CLK

-

on pin RST

-

on pin V_CC= 5 V or 1.8 V

on pin V_CC= 3 V

on pin V_CC= 5 V or 1.8 V

on pin V_CC= 3 V

125

160

115

150

90

I_sd

shutdown current

80

Timings

t_act

activation time

deactivation time

activation time

see Figure 8 on page 13

see Figure 9 on page 14

1847

35

-

3390

250

μs

t_deact

t_act

90

2690

time of the window for sending CLK 1992

to the card with XTAL1

3653

t_act(start)= t3; see Figure 8 on

page 13

2055

2766

3749

μs

t_act(end)=t5; see Figure 8 on

page 13

t_deb

debouncing time

on pin PRESN

2.96

4.05

5.55

ms

[1] To meet these specifications, V_CCshould be decoupled to CGND using two ceramic multilayer capacitors of low ESR with values of

either 220 nF.

[2] The transition time and the duty factor definitions are shown in Figure 12 on page 23.; d=t1/(t1+ t2)

[3] PRESN and CMDVCCN are active LOW; RSTIN is active HIGH; for CLKDIV1 and CLKDIV2 see Table 4.

t

r

f

V

OH

90%

(V

+ V ) /2

OL

OH

10%

V

OL

t

2

1

fce666

Fig 12. Definition of output and input transition times

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TDA8035HN

NXP Semiconductors

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12. Application information

V

DD(INTF)

V

DD(INTF)

(4)

C9

220 nF

CARD

CONNECTOR

C8

(3)

220 nF

VDDI

C5

C1

C2

C3

C4

I/OUC

PORADJ

CLK

RST

VCC

VUP

SAP

SBP

C6

C7

C8

(5)

R1

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

R

CMDVCCN

VDD(INTF)

CLKDIV1

CLKDIV2

EN5V_3V

EN_1.8V

R2

VDDI

(1)

0 Ω

C1

C5

VDDI

(2)

1 μF

100 nF

TDA8035

VDDP

SBM

VDD

C4

(2)

100 nF

(2)

C6

C7

10 μF

330 nF

C3

C10

C2

100 nF

330 nF

(1)

56 pF

001aan759

(1) Place close to the protected pin with good (low resistive) and straight connection to the main ground.

(2) Place close to the supply pin with good (low resistive) and straight connection to GNDP.

(3) Place close to TDA8035´s VCC pin with good connection to GNDC.

(4) Place close to card connector´s C1 (VCC) pinwidth good connection to GNDC.

(5) Optional bridge. If not used, R1 must be O Ohm and R2 absent (direct connection to VDDI).

(6) GNDP and GNDC must be connected to the main ground with a straight and low resistive connection

Fig 13. Application diagram

TDA8035HN

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TDA8035HN

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13. Package outline

HVQFN32: plastic thermal enhanced very thin quad flat package; no leads;

32 terminals; body 5 x 5 x 0.85 mm

SOT617-7

D

B

A

terminal 1

index area

E

A

1

c

detail X

e

1

1/2 e

C

y

v

w

C A

B

C

e

b

y

C

1

9

16

L

8

17

e

E

h

e

2

1/2 e

1

24

X

terminal 1

index area

32

25

D

h

0

2.5

scale

5 mm

w

Dimensions

Unit

(1)

A

1

b

c

D

h

E

h

e

1

e

2

L

v

y

1

max 1.00 0.05 0.30

5.1 2.2 5.1 2.2

0.5

mm nom 0.85 0.02 0.21 0.2 5.0 2.1 5.0 2.1 0.5 3.5 3.5 0.4 0.1 0.05 0.05 0.1

min 0.80 0.00 0.18 4.9 2.0 4.9 2.0 0.3

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

sot617-7_po

References

Outline

version

European

projection

Issue date

IEC

JEDEC

- - -

JEITA

- - -

10-02-08

10-02-09

SOT617-7

Fig 14. Package outline SOT617-7

TDA8035HN

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25 of 32

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NXP Semiconductors

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14. Soldering

14.1 Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology. A more in-depth account of

soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface mount IC packages. Wave

soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch

SMDs. In these situations reflow soldering is recommended.

14.2 Reflow soldering

Reflow soldering requires solder paste (a suspension of fine solder particles, flux and

binding agent) to be applied to the printed-circuit board by screen printing, stencilling or

pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example, convection or convection/infrared

heating in a conveyor type oven. Throughput times (preheating, soldering and cooling)

vary between 100 and 200 seconds depending on heating method.

Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature

of the packages should preferable be kept below 220 °C for thick/large packages, and

below 235 °C small/thin packages.

14.3 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices

(SMDs) or printed-circuit boards with a high component density, as solder bridging and

non-wetting can present major problems.

To overcome these problems the double-wave soldering method was specifically

developed.

If wave soldering is used the following conditions must be observed for optimal results:

• Use a double-wave soldering method comprising a turbulent wave with high upward

pressure followed by a smooth laminar wave.

• For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be

parallel to the transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the

transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

• For packages with leads on four sides, the footprint must be placed at a 45° angle to

the transport direction of the printed-circuit board. The footprint must incorporate

solder thieves downstream and at the side corners.

During placement and before soldering, the package must be fixed with a droplet of

adhesive. The adhesive can be applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the adhesive is cured.

TDA8035HN

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Product data sheet

Rev. 1.0 — 19 April 2011

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TDA8035HN

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Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need

for removal of corrosive residues in most applications.

14.4 Manual soldering

Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage

(24 V or less) soldering iron applied to the flat part of the lead. Contact time must be

limited to 10 seconds at up to 300 °C.

When using a dedicated tool, all other leads can be soldered in one operation within

2 to 5 seconds between 270 and 320 °C.

14.5 Package related soldering information

Table 8.

Suitability of surface mount IC packages for wave and reflow soldering methods

Soldering method

Package

Wave

Reflow^[1]

suitable

BGA, HBGA, LFBGA, SQFP, TFBGA

not suitable

not suitable^[2]

HBCC, HLQFP, HSQFP, HSOP, HTQFP,

HTSSOP, HVQFN, SMS

PLCC^[3], SO, SOJ

LQFP, QFP, TQFP

SSOP, TSSOP, VSO

suitable

not recommended^[3][4]

not recommended^[5]

[1] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the

maximum temperature (with respect to time) and body size of the package, there is a risk that internal or

external package cracks may occur due to vaporization of the moisture in them (the so called popcorn

effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit

Packages; Section: Packing Methods.

[2] These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and

heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

[3] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave

direction. The package footprint must incorporate solder thieves downstream and at the side corners.

[4] Wave soldering is only suitable for LQFP, QFP and TQFP packages with a pitch (e) equal to or larger than

0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

[5] Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than

0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

15. Abbreviations

Table 9.

Abbreviations

Description

Acronym

ESD

ElectroStatic Discharge

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Product data sheet

Rev. 1.0 — 19 April 2011

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TDA8035HN

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16. Revision history

Table 10. Revision history

Document ID

Release date Data sheet status

20110419 Product data sheet

Change notice

Supersedes

TDA8035HN v. 1.0

-

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Product data sheet

Rev. 1.0 — 19 April 2011

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17. Legal information

17.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

malfunction of an NXP Semiconductors product can reasonably be expected

17.2 Definitions

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

17.3 Disclaimers

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

TDA8035HN

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Product data sheet

Rev. 1.0 — 19 April 2011

29 of 32

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NXP Semiconductors

Smart card interface

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

17.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

18. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

TDA8035HN

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Product data sheet

Rev. 1.0 — 19 April 2011

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19. Tables

Table 1. Quick reference data . . . . . . . . . . . . . . . . . . . . .2

Table 2. Ordering information . . . . . . . . . . . . . . . . . . . . .3

Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5

Table 4. Clock configuration. . . . . . . . . . . . . . . . . . . . . .10

Table 5. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .17

Table 6. Thermal characteristics . . . . . . . . . . . . . . . . . .17

Table 7. Characteristics of IC . . . . . . . . . . . . . . . . . . . . 18

Table 8. Suitability of surface mount IC packages

for wave and reflow soldering methods . . . . . . 27

Table 9. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 10. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 28

20. Figures

Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Fig 2. Pin configuration HVQFN32 . . . . . . . . . . . . . . . . .5

Fig 3. Block voltage supervisor . . . . . . . . . . . . . . . . . . . .8

Fig 4. Voltage supervisor . . . . . . . . . . . . . . . . . . . . . . . . .9

Fig 5. Voltage supervisor . . . . . . . . . . . . . . . . . . . . . . . . .9

Fig 6. Switch external clock . . . . . . . . . . . . . . . . . . . . . .10

Fig 7. Shutdown mode and Deep Shutdown mode . . . .12

Fig 8. Activation sequence at t3 . . . . . . . . . . . . . . . . . .13

Fig 9. Deactivation sequence . . . . . . . . . . . . . . . . . . . .14

Fig 10. Emergency deactivation sequence

(Card extraction) . . . . . . . . . . . . . . . . . . . . . . . . .16

Fig 11. Behavior of OFFN, CMDVCCN, PRESN

and Vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Fig 12. Definition of output and input transition times . . .23

Fig 13. Application diagram . . . . . . . . . . . . . . . . . . . . . . .24

Fig 14. Package outline SOT617-7 . . . . . . . . . . . . . . . . .25

TDA8035HN

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Product data sheet

Rev. 1.0 — 19 April 2011

31 of 32

TDA8035HN

NXP Semiconductors

Smart card interface

21. Contents

1

General description. . . . . . . . . . . . . . . . . . . . . . 1

20

21

Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Protection of the contact smart card . . . . . . . . 1

Easy integration into your contact reader . . . . . 1

Other. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2.1

2.2

2.2.1

3

4

5

6

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Quick reference data . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

7

7.1

7.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

8

Functional description . . . . . . . . . . . . . . . . . . . 7

Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Voltage supervisor . . . . . . . . . . . . . . . . . . . . . . 8

Clock circuitry . . . . . . . . . . . . . . . . . . . . . . . . . 10

I/O circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

CS control. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Shutdown mode and Deep Shutdown mode . 12

Activation sequence . . . . . . . . . . . . . . . . . . . . 13

Deactivation sequence . . . . . . . . . . . . . . . . . . 14

VCC regulator. . . . . . . . . . . . . . . . . . . . . . . . . 14

Fault detection . . . . . . . . . . . . . . . . . . . . . . . . 15

8.1

8.2

8.3

8.4

8.5

8.6

8.7

8.8

8.9

8.10

9

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 17

Thermal characteristics . . . . . . . . . . . . . . . . . 17

Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 18

Application information. . . . . . . . . . . . . . . . . . 24

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 25

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

10

11

12

13

14

14.1

Introduction to soldering surface mount

packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 26

Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 26

Manual soldering . . . . . . . . . . . . . . . . . . . . . . 27

Package related soldering information . . . . . . 27

14.2

14.3

14.4

14.5

15

16

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 27

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 28

17

Legal information. . . . . . . . . . . . . . . . . . . . . . . 29

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 29

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 30

17.1

17.2

17.3

17.4

18

19

Contact information. . . . . . . . . . . . . . . . . . . . . 30

Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 19 April 2011

Document identifier: TDA8035HN


型号：	TDA8035HN
厂家：	NXP
描述：	Smart card interface externally by a resistor bridge 通过一个电阻电桥的智能卡接口的外部
文件：	总32页 (文件大小：918K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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