TDA8295HN/C2 [NXP]
IC AM/FM, AUDIO/VIDEO DEMODULATOR, PQCC40, 6 X 6 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT618-1, HVQFN-40, Receiver IC;
| 型号： | TDA8295HN/C2 |
| 厂家： | 
NXP |
| 描述： | IC AM/FM, AUDIO/VIDEO DEMODULATOR, PQCC40, 6 X 6 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT618-1, HVQFN-40, Receiver IC 商用集成电路 |
| 文件： | 总83页 (文件大小：3440K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TDA8295
Digital global standard low IF demodulator for analog TV and
FM radio
Rev. 02 — 27 November 2009
Product data sheet
1. General description
The TDA8295 is an alignment-free digital multistandard vision and sound low IF signal
PLL demodulator for positive and negative video modulation including AM and FM mono
sound processing. It can be used in all countries worldwide for M/N, B/G/H, I, D/K,
L and L-accent standard. CVBS and SSIF/mono audio is provided via two DACs. FM
radio preprocessing is included for simple interfacing with demodulator/stereo decoder
backends.
The IC is especially suited for the application with the NXP Silicon Tuner TDA8275A or
TDA1827x.
All the processing is done in the digital domain.
The chip has an ‘easy programming’ mode to make the I2C-bus protocol very simple. In
principle, only one bit sets the proper standard with recommended content. However, if
this is not suitable, free programming is always possible.
Note: The recommended ADC programming deviates from default setting and needs to
be set explicitly by I2C-bus protocol after hardware reset (see Section 13.5.1).
2. Features
Digital IF demodulation for all analog TV standards worldwide (M/N, B/G/H, D/K, I,
L and L-accent standard)
Multistandard true synchronous demodulation with active carrier regeneration
Alignment-free
16 MHz typical reference frequency input (from low IF tuner) or operating as crystal
oscillator
Internal PLL synthesizer which allows the use of a low-cost crystal (typically 16 MHz)
Especially suited for the NXP Silicon Tuner TDA8275A or TDA1827x
No SAW filter needed
Low application effort and external component count in combination with the
TDA8275A or TDA1827x
Pin compatible with predecessor TDA8290
Simple upgrade of TDA8290 possible
12-bit IF ADC on chip running with 54 MHz or 27 MHz
Two 10-bit DACs on chip for CVBS and SSIF or audio
Easy programming for I2C-bus
High flexibility due to various I2C-bus programming registers
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
I2C-bus interface and I2C-bus feed-through for tuner programming
Four I2C-bus addresses selectable via two external pins
Gated IF AGC acting on black level by using H/V PLL or peak IF AGC (I2C-bus
selectable)
Internal digital logarithmic IF AGC amplifier with up to 48 dB gain and 68 dB control
range
Peak search tuner IF AGC for optimal adaptive drive of the IF ADC
Switchable IF PLL and IF AGC loop bandwidths
Precise AFC and lock detector
Accurate group delay equalization for all standards
Very robust IF demodulator coping with adverse field conditions
Wide PLL pull-in range up to ±1660 kHz (I2C-bus selectable)
CVBS and SSIF or audio output with simple postfilter (capacitor only)
CVBS gain levelling stage to provide nearly constant signal amplitude during
overmodulation
Video equalizer with eight settings
Nyquist filter in video baseband
Excellent video S/N (typically 62 dB weighted)
High selectivity video low-pass filter for all standards
Low video into sound crosstalk
Sound performance comparable to QSS single reference concepts
AM/FM mono sound demodulator
Switchable de-emphasis
Excellent FM sound
Good AM sound
High FM Deviation mode for China
Preprocessing of FM radio (mono and stereo) with highly selective digital band-pass
filter
No ceramic filter or external components needed for FM radio
FM radio available in mono
Automatic or forced mute for mono sound
Automatic or forced blank for video
Mostly digital FIR filter implementation (NSC notches and video low-pass filters)
Three GPIO pins
Power-On Reset (POR) block for reliable power-up behavior
Low total power dissipation (typically 465 mW)
Standby mode (typically 7 mW)
40-pin HVQFN package
CMOS technology (0.12 μm 1.2 V and 3.3 V)
3. Applications
PC TV applications
DVD recorders
TV applications
TDA8295_C2_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 27 November 2009
2 of 83
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
4. Quick reference data
Table 1.
Quick reference data
Power supplies 3.3 V, 1.2 V; Tamb = 25 °C; PC / SC1 for L and M = 10 dB, all others 13 dB; residual picture carrier for L = 3 %,
all others 10 %; FM/AM modulation = 54 %, 1 kHz modulation frequency; measured in application PCB (see Figure 15) with
16 MHz crystal frequency, loaded with 75 Ω (CVBS) and 1 kΩ (SSIF/audio). Values are meant for ‘easy programming’
settings (recommended) except internal mono audio and IF demodulation. The low IF spectrum is delivered by a professional
downconverter.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Power supply
VDD(1V2)
VDD(3V3)
IDD(tot)(1V2)
IDD(tot)(3V3)
Ptot
supply voltage (1.2 V)
digital and analog
digital and analog
1.08
1.2
3.3
28
1.32
3.63
33
V
supply voltage (3.3 V)
2.97
V
total supply current (1.2 V)
total supply current (3.3 V)
total power dissipation
-
-
-
mA
mA
mW
[1]
[1]
168
575
179
631
default settings; 75 Ω drive;
fs = 54 MHz at ADC; including DAC
loads; RRSET = 1 kΩ
[2]
Power-save mode; fs = 54 MHz at
ADC; including DAC loads;
RRSET = 2 kΩ; see Section 13.6
-
-
465
7
510
10
mW
mW
Standby mode
IF input
Vi(p-p)
Vi
peak-to-peak input voltage for full-scale ADC input (0 dBFS)
1.8
2.0
2.2
V
input voltage
operational input related to ADC full
scale; all standards; sum of all signals
−3
−3
−3
dBFS
fi
input frequency
PC / SC1
M/N standard
B standard
-
-
-
-
-
-
-
5.75 / 1.25 -
6.75 / 1.25 -
7.75 / 2.25 -
7.75 / 1.75 -
7.75 / 1.25 -
1.25 / 7.75 -
MHz
MHz
MHz
MHz
MHz
MHz
MHz
G/H standard
I standard
DK and L standard
L-accent standard
FM radio
1.25
-
Carrier recovery FPLL
B−3dB(cl)
closed-loop −3 dB
wide
60
60
60
kHz
bandwidth
[3]
Δfpullin
pull-in frequency range
see Figure 11
-
±830
-
-
kHz
%
mover(PC)
picture carrier
overmodulation index
black for L/L-accent standard; flat field
white else
115
117
IF demodulation (video equalizer in Flat mode)
αsup(stpb)
stop-band suppression
video low-pass filter (M/N, B/G/H, I,
D/K, L/L-accent standard)
-
-
−60
-
dB
ns
tripple(GDE)
group delay equalizer
ripple time
peak value for B/G/H half, D/K half,
I flat, M (FCC) full, L/L-accent full
standard
20
40
TDA8295_C2_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 27 November 2009
3 of 83
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Table 1.
Quick reference data …continued
Power supplies 3.3 V, 1.2 V; Tamb = 25 °C; PC / SC1 for L and M = 10 dB, all others 13 dB; residual picture carrier for L = 3 %,
all others 10 %; FM/AM modulation = 54 %, 1 kHz modulation frequency; measured in application PCB (see Figure 15) with
16 MHz crystal frequency, loaded with 75 Ω (CVBS) and 1 kΩ (SSIF/audio). Values are meant for ‘easy programming’
settings (recommended) except internal mono audio and IF demodulation. The low IF spectrum is delivered by a professional
downconverter.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
CVBS output
Vo(p-p)
peak-to-peak output
voltage
negative PC modulation (all standards
except L/L-accent); 75 Ω DC load;
sync-white modulation
90 % (nominal)
0.8
0.8
1.0
1.0
1.2
1.2
V
V
positive PC modulation (L/L-accent
standard); 75 Ω DC load; sync-white
modulation
97 % (nominal)
Bvideo(−3dB) −3 dB video bandwidth
overall video response; CVBS
equalizer flat
all standards except M/N
M/N standard
4.8
3.9
−5
4.85
4.05
-
-
MHz
MHz
dB
-
αresp(f)
frequency response
video equalizer; 8 equally spaced
settings; value at 3.9 MHz
+4.5
Gdif
differential gain
“ITU-T J.63 line 330”
“ITU-T J.63 line 330”
-
1.5
1.5
62
3
3
-
%
ϕdif
differential phase
-
deg
dB
(S/N)w
weighted signal-to-noise
ratio
all standards; unified weighting filter
(“ITU-T J.61”); PC at −6 dBFS
58
SSIF/mono sound output
Vo(SSIF)(RMS) RMS SSIF output voltage 1 kΩ DC or AC load; no modulation;
PC / SC1 = 13 dB; scaled linearly for
all other ratios
all standards except B/G/H
B/G/H standard
30
35
40
mV
mV
mV
27
32
37
FM radio (single carrier)
460
530
610
Vo(AF)(RMS) RMS AF output voltage
1 kΩ DC or AC load
M standard; 54 % modulation
degree (±13.5 kHz FM deviation
before pre-emphasis)
125
125
143
143
165
165
mV
mV
B, G/H, I, D, K standard; 54 %
modulation degree (±27 kHz
FM deviation before pre-emphasis)
αhr(AF)
AF headroom
before clipping; 1 kΩ DC or AC load
M standard; related to ±25 kHz peak
deviation before pre-emphasis
7
7
7
7
7
7
dB
dB
B, G/H, I, D, K standard; related to
±50 kHz peak deviation before
pre-emphasis
THD
total harmonic distortion
FM; for 50 kHz deviation before
pre-emphasis (25 kHz for M standard)
-
-
0.1
0.6
0.2
1
%
%
AM; m = 80 %
TDA8295_C2_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 27 November 2009
4 of 83
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Table 1.
Quick reference data …continued
Power supplies 3.3 V, 1.2 V; Tamb = 25 °C; PC / SC1 for L and M = 10 dB, all others 13 dB; residual picture carrier for L = 3 %,
all others 10 %; FM/AM modulation = 54 %, 1 kHz modulation frequency; measured in application PCB (see Figure 15) with
16 MHz crystal frequency, loaded with 75 Ω (CVBS) and 1 kΩ (SSIF/audio). Values are meant for ‘easy programming’
settings (recommended) except internal mono audio and IF demodulation. The low IF spectrum is delivered by a professional
downconverter.
Symbol
Parameter
Conditions
AM
Min
20
Typ
27
Max
Unit
kHz
kHz
BAF(−3dB)
−3 dB AF bandwidth
-
-
FM
40
50
(S/N)w(AF)
AF weighted
signal-to-noise ratio
via internal mono sound demodulator;
“ITU-R BS.468-4”; FM mode related to
27 kHz deviation before
pre-emphasis; 10 % residual PC; SC1
color bar picture
54
43
58
46
-
-
dB
dB
via internal mono sound demodulator;
“ITU-R BS.468-4”; AM; m = 54 %; 3 %
residual PC; SC1
color bar picture
[1] 100 % ADC current; 100 % video DAC current; 50 % sound DAC current.
[2] 100 % ADC current; 50 % video DAC current; 25 % sound DAC current.
[3] The pull-in range can be doubled to ±1660 kHz by I2C-bus register like described in Table 16. Then the AFC read-out has 256 steps.
5. Ordering information
Table 2.
Ordering information
Type number
Package
Name
Description
Version
TDA8295HN/C2
HVQFN40
plastic thermal enhanced very thin quad flat package; no leads;
SOT618-1
40 terminals; body 6 × 6 × 0.85 mm
TDA8295_C2_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 27 November 2009
5 of 83
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VIDEO
DAC
analog
CVBS
GATED AGC
DETECTOR
AND
H/V PLL
INTEGRATOR
UPSAMPLER
FILTERS
AND
AGC AMPLIFIER
VIDEO
LOW-PASS
FILTER
VIDEO/
GROUP DELAY
EQUALIZER
2
low IF
signal
IF
ADC
PLL
NYQUIST
SLOPE
DEMODULATOR
SSIF AND FM RADIO
BAND-PASS FILTERS
PEAK DETECTOR
AND
INTEGRATOR
analog SSIF
or
mono sound
SOUND
DAC
SWITCH
UPSAMPLER
CORDIC AM/FM
SOUND DEMODULATOR
SUPPLY, REFERENCE
AND
CLOCK
PROCESSOR
AND PLL
tuner
IF AGC
BIT STREAM
DAC
POWER-ON
RESET
2
I C-BUS
DECOUPLING
2
crystal or
frequency
reference
I C-bus
008aaa181
Fig 1. Functional diagram of TDA8295
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
7. Pinning information
7.1 Pinning
terminal 1
index area
1
2
30
29
28
27
26
25
24
23
22
21
IF_POS
IF_NEG
TRST_N
SDA
3
V
SCL
DDA(ADC)(3V3)
4
V
TCK
DDD1(1V2)
5
V
SSD1
V
V
SSD2
TDA8295HN
6
i.c.
DDD2(1V2)
7
V
TMS
TDI
DDA(PLL)(1V2)
XIN
8
9
XOUT
TDO
RST_N
10
V
SSA(PLL)
008aaa095
Transparent top view
Fig 2. Pin configuration for HVQFN40
Table 3.
Pin
1
Pin allocation table
Symbol
Pin
2
Symbol
IF_POS
VDDA(ADC)(3V3)
VSSD1
IF_NEG
VDDD1(1V2)
i.c.
3
4
5
6
7
VDDA(PLL)(1V2)
XOUT
8
XIN
9
10
12
14
16
18
20
22
24
26
28
30
VSSA(PLL)
VSSA(DAC)
V_IOUTP
S_IOUTN
11
13
15
17
19
21
23
25
27
29
RSET
V_IOUTN
VDDA(DAC1)(3V3)
S_IOUTP
SADDR0
RST_N
VDDA(DAC2)(3V3)
SADDR1
TDO
TDI
TMS
VDDD2(1V2)
TCK
VSSD2
SCL
SDA
TRST_N
TDA8295_C2_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 27 November 2009
7 of 83
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Table 3.
Pin allocation table …continued
Pin
31
33
35
37
39
Symbol
Pin
32
34
36
38
40
Symbol
GPIO1/SCL_O
VDDDR(3V3)
i.c.
GPIO2/SDA_O
GPIO0/VSYNC
VSSDR
IF_AGC
i.c.
VDDD(ADC)(3V3)
VSSA(ADC)
7.2 Pin description
Table 4.
Symbol
Reset
Pin description
Pin Type[1][2] Description
RST_N
21
I
The RST_N input is asynchronous and active LOW, and clears the TDA8295. When
RST_N goes LOW, the circuit immediately enters its Reset mode and normal operation
will resume four XIN signal falling edges later after RST_N returns HIGH. Internal
register contents are all initialized to their default values. The minimum width of RST_N
at LOW level is four XIN clock periods.
Reference
XIN
8
9
I
Crystal oscillator input pin. In Slave mode (typically), the XIN input simply receives a
16 MHz clock signal from an external device (typically from the TDA8275A or
TDA1827x). In Oscillator mode, a fundamental 16 MHz (typically) crystal is connected
between pin XIN and pin XOUT.
XOUT
O
Crystal oscillator output pin. In Slave mode, the XOUT output is not connected. In
Oscillator mode a fundamental 16 MHz (typically) crystal is connected between pin XIN
and pin XOUT.
I2C-bus
SDA
29
28
I/O, OD
I
I2C-bus bidirectional serial data. SDA is an open-drain output and therefore requires an
external pull-up resistor (typically 4.7 kΩ).
I2C-bus clock input. SCL is nominally a square wave with a maximum frequency of
400 kHz. It is generated by the system I2C-bus master.
SCL
SADDR0
SADDR1
19
20
I
I
These two bits allow to select four possible I2C-bus addresses, and therefore permits to
use several TDA8295 in the same application and/or to avoid conflict with other ICs.
The complete I2C-bus address is: 1, 0, 0, SADDR1, 0, 1, SADDR0 (see also
Section 9.1).
I2C-bus feed-through switch or GPIO
GPIO2/SDA_O 31
I/O, OD
SDA_O is equivalent to SDA but can be 3-stated by I2C-bus programming. It is the
output of a switch controlled by I2CSW_EN parameter. SDA_O is an open-drain output
and therefore requires an external pull-up resistor (see Section 9.3.20).
GPIO1/SCL_O 32
I/O, OD
SCL_O is equivalent to SCL input but can be 3-stated by I2C-bus programming. SCL_O
is an open-drain output and therefore requires an external pull-up resistor
(see Section 9.3.20). For proper functioning of the I2C-bus feed-through, a capacitor
C = 33 pF to GND must be added (see Section 13.6).
V-sync or GPIO
GPIO0/VSYNC 33
Tuner IF AGC
I/O, OD
vertical synchronization pulse needed for the NXP Silicon Tuner (see Section 9.3.20)
IF_AGC
37
I/O, OD, T tuner IF AGC output
TDA8295_C2_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 27 November 2009
8 of 83
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Table 4.
Pin description …continued
Pin Type[1][2] Description
Symbol
Boundary scan
TMS
24
30
I
I
Test mode select provides the logic levels needed to change the TAP controller from
state to state during the boundary scan test.
TRST_N
Test reset is used to reset the TAP controller (active LOW). Grounding is mandatory in
Functional mode.
TCK
TDI
27
23
22
I
Test clock is used to drive the TAP controller.
I
Test data input is the serial data input for the test data instruction.
TDO
O
Test data output is the serial test data output pin. The data is provided on the falling
edge of TCK.
ADC
IF_POS
IF_NEG
DAC
1
2
AI
AI
IF positive analog input for internal ADC
IF negative analog input for internal ADC
V_IOUTP
V_IOUTN
S_IOUTP
S_IOUTN
RSET
14
13
17
16
11
AO
AO
AO
AO
I
positive analog current output of the video output
negative analog current output of the video output
positive analog current output of the SSIF/mono sound output
negative analog current output of the SSIF/mono sound output
External bias setting of the DACs. An external resistor (1 kΩ typical) has to be
connected between RSET and the analog ground of the board. This resistor generates
the current into the DACs and also defines the full scale output current. The total
parasitic capacitance seen externally from the RSET pin has to be lower than 20 pF.
Supplies and grounds
VDDA(DAC1)(3V3) 15
VDDA(DAC2)(3V3) 18
PS
DAC1 (video DAC) and DAC reference module analog supply voltage (3.3 V typical)
DAC2 (sound DAC) analog supply voltage (3.3 V typical)
DAC reference module analog ground supply voltage (0 V typical)
IF ADC analog supply voltage (3.3 V typical)
PS
VSSA(DAC)
12
3
GND
PS
VDDA(ADC)(3V3)
VDDD(ADC)(3V3) 39
PS
IF ADC digital supply voltage (3.3 V typical)
VSSA(ADC)
VDDD1(1V2)
VSSD1
40
4
GND
PS
ADC analog ground supply voltage (0 V typical)
ADC, PLL and DACs digital supply voltage (1.2 V typical)
ADC, PLL and DACs digital ground supply voltage (0 V typical)
crystal oscillator and clock PLL analog supply voltage (1.2 V typical)
crystal oscillator and clock PLL analog ground supply voltage (0 V typical)
core digital supply voltage (1.2 V typical)
5
GND
PS
VDDA(PLL)(1V2)
VSSA(PLL)
VDDD2(1V2)
VSSD2
7
10
25
26
34
35
GND
PS
GND
PS
core digital ground supply voltage (0 V typical)
VDDDR(3V3)
VSSDR
ring digital supply voltage (3.3 V typical)
GND
ring digital ground supply voltage (0 V typical)
Other pins
i.c.
36
38
6
I
I
I
internally connected; connect to ground
internally connected; connect to ground
internally connected; connect to ground
i.c.
i.c.
[1] All digital inputs are 5 V tolerant (except pin XIN).
[2] The pin types are defined in Table 5.
TDA8295_C2_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 27 November 2009
9 of 83
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Table 5.
Pin type description
Description
Type
AI
analog input
AO
GND
I
analog output
ground
digital input
I/O
O
digital input and output
digital output
open-drain output
power supply
3-state
OD
PS
T
8. Functional description
8.1 IF ADC
The low IF spectrum (1 MHz to 10 MHz) from the Silicon Tuner TDA8725A or TDA1827x
is fed symmetrically to the 12-bit IF ADC of the TDA8295, where it is sampled with
54 MHz or 27 MHz. All the anti-aliasing filtering is already done in the Silicon Tuner.
8.2 Filters
The internal filters permit to reduce the sampling rate to 13.5 MHz, and to form a complex
signal to ease the effort of further signal processing. Before this, the DC offset (coming
from the ADC) is removed.
In addition, standard dependent notch filters for the adjacent sound carriers protect the
picture carrier PLL from malfunctioning and avoid disturbances (i.e. moire) becoming
visible in the video output.
8.3 PLL demodulator
The second-order PLL is the core block of the whole IC. It is very robust against adverse
field conditions, like excessive overmodulation, no residual carrier presence or unwanted
phase or frequency modulation of the picture carrier. The PLL output is the synchronously
demodulated channel.
The AFC data is available via the I2C-bus.
8.4 Nyquist filter, video low-pass filter, video and group delay equalizer,
video leveling
The afore-mentioned down-mixed complex signal at the mixer CORDIC output, already
consisting of the demodulated content of the picture carrier together with the sound
carriers (the so-called intercarriers), is running through a Nyquist filter to get a flat video
response and is made real.
Afterwards, a video low-pass filter suppresses the sound carriers and other disturbers.
Next comes the equalizer circuit to remove the transmitter group delay predistortion.
TDA8295_C2_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 27 November 2009
10 of 83
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
A video leveling stage follows, which brings the output within the SCART specification
(±3 dB overall), despite heavy overmodulation. The response time is made very slow.
Finally, a video equalizer allows to compensate the perhaps non-flat frequency response
from the tuner or to change the overall video response according to customer wish (i.e.
peaking or early roll-off).
8.5 Upsampler and video DAC
The filtered and compensated CVBS signal is connected to the oversampled 10-bit video
DAC (fs = 108 MHz) via an interpolation stage. The strong oversampling replaces a
former complicated LCR postfiltering by a simple first-order RC low-pass filter to remove
the DAC image frequencies sufficiently. This holds also for the sound DAC, described in
Section 8.6.
8.6 SSIF/mono sound processing
The complex signal is routed via a band-pass and interpolation filter to the 10-bit sound
DAC for the recovery of the second sound carriers (SSIF). A very sharp band-pass filter at
5.5 MHz is added in the FM Radio mode to remove neighbor channels. This also eases
the dynamic burden on the following ADC in the demodulator/decoder chip. The
afore-mentioned high-selectivity band-pass, which replaces the former ceramic filter, is
located behind a frequency shifter. In there, the incoming wanted FM radio channel from
the Silicon Tuner is changed from 1.25 MHz to 5.5 MHz.
Moreover, the complex signal is demodulated in a linear CORDIC detector and low-pass
filtered to attenuate the video spectrum and the second sound carrier, respectively other
disturbers above the intercarrier. The output of the linear CORDIC (phase information) is
differentiated for getting the demodulated FM audio. The AM demodulation is executed in
a synchronous fashion by using a narrow-band PLL demodulator.
A de-emphasis filter is implemented for FM standards, before the audio is interpolated to
108 MHz as in the CVBS case.
The mono audio is made available in the sound DAC via an I2C-bus controlled selector in
case the intercarrier path is not used for driving an external stereo demodulator.
However, if the mono audio output has to meet the SCART specification, an external
cheap operational amplifier with 12 dB gain becomes necessary, because the low supply
voltage for the TDA8295 doesn’t allow such high levels like 2 V (RMS) maximum.
8.7 Tuner IF AGC
This AGC controls the tuner IF AGC amplifier in the TDA8275A or TDA1827x in such a
way, that the IF ADC is always running with a permanent headroom of 3 dB for the sum of
all signals present at the ADC input. This ensures an always optimal exploitation of the
dynamic range in the IF ADC.
The detection is done in peak Search mode during a field period. The attack time is made
much faster than the decay time in order to avoid transient clipping effects in the IF ADC.
This can happen during channel change or airplane flutter conditions.
TDA8295_C2_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 27 November 2009
11 of 83
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
The above wideband, slowly acting AGC loop (uncorrelated) is of first-order integral
action. It is closed via the continuous tuner IF AGC amplifier in the Silicon Tuner via a
bit stream DAC (PWM signal at 13.5 MHz, 27 MHz or 54 MHz) and an external and
uncritical first-order RC low-pass.
8.8 Digital IF AGC
Common to both IF AGC concepts is the peak search algorithm as long as the H/V PLL is
not locked. This is of advantage for the acquisition by avoiding hang-ups due to excessive
overloading, so being able to leave the saturated condition by reducing the gain.
Two Detection modes are made available in the IC via I2C-bus.
• Black level gated AGC:
The first mode uses an IF AGC detector which is gated with a very robust and
well-proven H/V sync PLL block on board. Gating occurs on the black level (most of
the time on the back porch) of the video signal and the control is delivered after an
error integration and exponential weighting to the internal IF AGC amplifier. This
IF AGC amplifier, in fact a multiplier, has a control range of −20 dB to +48 dB.
• Peak AGC:
A fast attack and slow decay action cares for a good and nearly clip-free transient
behavior. This proved to be more robust for non-standard signals, like sync clipping
along the transmitter/receiver chain.
With respect to the IF AGC speed generally, only the gated black level or peak sync
IF AGC can be made fast. However the peak search one, used for positive
modulation standards (L and L-accent standard), is rather slow because the VITS is
present only once in a field.
The correlated or narrow-band AGC loop, closed via the continuous IF AGC amplifier
in the TDA8295, is of first-order integral action and settles at a constant IF input level
with a permanent headroom of 12 dB (picture carrier). This headroom is needed for
the own sound carriers and the leaking neighbor (N − 1) spectrum.
8.9 Clock generation
Finally, either an external reference frequency (i.e. from the Silicon Tuner) or an own
on-chip crystal oscillator in the TDA8295 feeds the internal PLL synthesizer to generate
the necessary clock signals.
9. I2C-bus control
9.1 Protocol of the I2C-bus serial interface
The TDA8295 internal registers are accessible by means of the I2C-bus serial interface.
The SDA bidirectional pin is used as the data input/output pin and SCL as the clock input
pin. The highest SCL speed is 400 kHz.
TDA8295_C2_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 27 November 2009
12 of 83
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
9.1.1 Write mode
S
BYTE 1
A
BYTE 2
A
BYTE 3
data 1
A
BYTE n
data n
A
P
start
address 0
ack
start index
ack
ack
....
ack
stop
001aad381
Fig 3. I2C-bus Write mode
Table 6.
Address format
6
7
5
4
3
2
1
0
1
0
0
SADDR1
0
1
SADDR0 R/W
Table 7.
Field
S
I2C-bus transfer description
Bit
Description
START condition
device address
SADDR1
-
Byte 1
7 to 5
4
3 and 2
device address
SADDR0
1
0
R/W = 0 for write action
acknowledge
start index
A
-
Byte 2
7 to 0
A
-
acknowledge
data 1
Byte 3
7 to 0
-
A
acknowledge
:
Byte n
7 to 0
data n
A
P
-
-
acknowledge
STOP condition
S
BYTE 1
1000 0100
A
BYTE 2
A
BYTE 3
0000 0010
A
P
start
ack
0000 0001
ack
ack
stop
001aah355
a. Address 84h, write 02h in register 01h
S
BYTE 1
A
BYTE 2
A
BYTE 3
0000 0101
A
BYTE 4
A
P
start
1000 0100
ack
0000 0010
ack
ack
0000 0100
ack
stop
001aah356
b. Address 84h, write 05h in register 02h and 04h in register 03h
Fig 4. Examples I2C-bus Write mode
TDA8295_C2_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 27 November 2009
13 of 83
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
9.1.2 Read mode
S
BYTE 1
A
BYTE 2
A
S
BYTE 3
A
BYTE 4
A
BYTE n
value n
A
P
start
address 0
ack
start index
ack
start
address 1
ack
value 1 ack ....
ack
stop
001aad423
Fig 5. I2C-bus Read mode
Table 8.
Field
S
I2C-bus transfer description
Bit
Description
-
START condition
device address
SADDR1
Byte 1
7 to 5
4
3 and 2
device address
SADDR0
1
0
R/W = 0 for write action
acknowledge
start index
A
-
Byte 2
A
7 to 0
-
acknowledge
S
-
START condition (without stop before)
device address
SADDR1
Byte 3
7 to 5
4
3 and 2
device address
SADDR0
1
0
R/W = 1 for read action
acknowledge
A
-
Byte 4
7 to 0
-
value 1
A
acknowledge
:
Byte n
7 to 0
value n
A
P
-
-
acknowledge
STOP condition
S
BYTE 1
A
BYTE 2
A
S
BYTE 3
A
BYTE 4
A
BYTE 5
0000 0100
A
P
start
1000 0100
ack
0000 0010
ack
start
1000 0101
ack
0000 0101
ack
ack
stop
001aah357
Address 84h, read register 02h with value 05h and read register 03h with value 04h
Fig 6. Example I2C-bus Read mode
TDA8295_C2_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 27 November 2009
14 of 83
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9.2 Register overview
The TDA8295 internal registers are accessible by means of the I2C-bus serial interface as described in Section 9.1. In
Table 9 and Table 10 an overview of all the registers is given, the register description can be found in Section 9.3.
Table 9.
I2C-bus registers
Index Name
7 (MSB)
6
5
4
3
2
1
0 (LSB)
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
STANDARD
STANDARD[7:0]
EASY_PROG
DIV_FUNC
-
-
-
-
-
-
-
-
-
-
-
ACTIVE
AGC_SEL
-
AGC_TRI
-
0
POL_DET
VID_MOD
IF_SWAP
ADC_HEADR
PC_PLL_FUNC
PC_PLL_THRES
PC_PLL_WGT
PC_FLL_FUNC
CARDET_LEVEL
DTO_PC_LOW
DTO_PC_MID
DTO_PC_HIGH
ADC_HEADR[3:0]
PLL_ON
PH_ERR_THRES[3:0]
PC_PLL_BW[4:0]
PULL_IN
CAR_DET
-
-
-
-
PHASE_PER PHASE_GAIN[6:0]
FLL_ON
LIM_ON
-
FLL_LIM[5:0]
-
-
CAR_DET_LVL[4:0]
DTO_PC[7:0]
DTO_PC[15:8]
DTO_PC[23:16]
DTO_SC[7:0]
DTO_SC[15:8]
DTO_SC[23:16]
VID_FILT[2:0]
-
0Ch DTO_SC_LOW
0Dh DTO_SC_MID
0Eh
0Fh
10h
11h
12h
DTO_SC_HIGH
FILTERS_1
NOTCH_FILT[4:0]
FILTERS_2
-
-
-
DC_NOTCH
SBP[3:0]
GRP_DELAY
D_IF_AGC_SET_1
GD_EQ_CTRL -
GRP_DEL[4:0]
D_IF_AGC_
CORR
D_IF_AGC_
MODE
D_IF_AGC_AVG[4:0]
RST_INT
13h
D_IF_AGC_SET_2
D_AGC_ERR_ D_IF_AGC_BW[6:0]
LIM
14h
15h
16h
17h
18h
D_IF_AGC_FORCE D_FORCE
D_FORCE_VAL[6:0]
T_IF_AGC_SET
T_IF_AGC_LIM
POL_TIF
T_IF_AGC_SPEED[6:0]
UP_LIM[3:0]
LOW_LIM[3:0]
- T_IF_AGC_FS[2:0]
T_IF_AGC_FORCE T_FORCE
T_IF_AGC_FS
T_FORCE_VAL[6:0]
-
-
-
-
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Table 9.
I2C-bus registers …continued
Index Name
7 (MSB)
6
5
4
3
2
1
0 (LSB)
19h
to
reserved
reserved
1Bh
1Ch V_SYNC_DEL
1Dh CVBS_SET
VS_WIDTH[1:0]
-
VS_POL
-
VS_DEL[4:0]
-
-
CVBS_EQ_
CTRL
FOR_BLK
AUTO_BLK
VID_LVL
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
CVBS_LEVEL
CVBS_EQ
CVBS_LVL[7:0]
CVBS_EQ[7:0]
SOUNDSET_1
SOUNDSET_2
SOUND_LEVEL
SSIF_LEVEL
ADC_SAT
-
AM_FM_SND[1:0]
DEEMPH[4:0]
HD_DK
-
-
-
-
-
-
-
FOR_MUTE
AUTO_MUTE SSIF_SND[1:0]
-
SND_LVL[4:0]
SSIF_LVL[4:0]
-
ADC_SAT[7:0]
AFC
AFC[7:0]
-
HVPLL_STAT
D_IF_AGC_STAT
T_IF_AGC_STAT
reserved
-
NOISE_DET
MAC_DET
FIDT
V_LOCK
F_H_LOCK
N_H_LOCK
D_IF_AGC_STAT[7:0]
T_IF_AGC_STAT[7:0]
reserved
ANALOG_DEBUG
not used
-
-
-
-
-
-
-
-
-
-
-
-
ADC_TEST
-
DAC_TEST
-
2Bh
to
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
IDENTITY
IDENTITY[7:0]
CLB_STDBY
reserved
-
-
-
-
-
-
-
-
-
STDBY
SLEEP
CLB
-
reserved
reserved
DCIN
-
ANALOG_STAT
ADC_CTL
POR_TEST
LOAD_DACV LOAD_DACS PLL_LOCK
CS[2:0]
GAINSET
TWOS
-
PD_ADC
ADC_CTL_2
VIDEODAC_CTL
AUDIODAC_CTL
-
-
-
-
AD_PLL_BYP AD_SR54M
PD_DA_V
0
0
-
B_DA_V[5:0]
B_DA_S[5:0]
PD_DA_S
DAC_REF_CLK_CT
L
DA_CLK_INV DA_PLL_BYP B_REF[3:0]
PD_DA_REF
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Table 9.
I2C-bus registers …continued
Index Name
7 (MSB)
6
0
-
5
4
0
-
3
0
-
2
0
-
1
0
-
0 (LSB)
38h
PLL_REG00
not used
0
-
PLL_AUTO
-
0
-
39h
to
3Bh
3Ch PLL_REG04
3Dh not used
-
-
-
-
-
0
-
0
-
0
-
-
-
-
-
-
3Eh
3Fh
40h
41h
42h
43h
44h
45h
46h
PLL_REG06
PLL_REG07
PLL_REG08
PLL_REG09
PLL_REG10
XTALOSC_CTL
GPIOREG_0
GPIOREG_1
GPIOREG_2
reserved
0
CLK_EN
0
BYP_PLL
0
DIRECTO
0
DIRECTI
0
0
0
0
0
PD_PLL
0
-
MSEL[7:0]
NSEL[6:0]
0
0
0
0
-
0
-
PSEL[4:0]
-
-
-
HF
0
GP1_CF[3:0]
I2CSW_EN
GP0_CF[3:0]
GP2_CF[3:0]
-
I2CSW_ON
-
-
CLK_INV_GP2 CLK_INV_GP1 CLK_INV_GP0 -
reserved
GP2_VAL
GP1_VAL
GP0_VAL
47h
to
4Ah
4Bh
GD_EQ_SECT1_C1 GD_EQ_SECT1_C1[7:0]
4Ch GD_EQ_SECT1_C2 GD_EQ_SECT1_C2[7:0]
4Dh GD_EQ_SECT2_C1 GD_EQ_SECT2_C1[7:0]
4Eh
4Fh
50h
51h
52h
GD_EQ_SECT2_C2 GD_EQ_SECT2_C2[7:0]
GD_EQ_SECT3_C1 GD_EQ_SECT3_C1[7:0]
GD_EQ_SECT3_C2 GD_EQ_SECT3_C2[7:0]
GD_EQ_SECT4_C1 GD_EQ_SECT4_C1[7:0]
GD_EQ_SECT4_C2 GD_EQ_SECT4_C2[7:0]
53h
to
56h
not used
-
-
-
-
-
-
-
-
-
-
57h
CVBS_EQ_COEF0_ CVBS_EQ_COEF0[7:0]
LOW
58h
CVBS_EQ_COEF0_
HIGH
-
-
CVBS_EQ_COEF0[11:8]
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Table 9.
I2C-bus registers …continued
Index Name
7 (MSB)
6
5
4
3
2
1
0 (LSB)
59h
5Ah
5Bh
CVBS_EQ_COEF1_ CVBS_EQ_COEF1[7:0]
LOW
CVBS_EQ_COEF1_
HIGH
-
-
-
-
CVBS_EQ_COEF1[11:8]
CVBS_EQ_COEF2[11:8]
CVBS_EQ_COEF3[11:8]
CVBS_EQ_COEF4[11:8]
CVBS_EQ_COEF5[11:8]
CVBS_EQ_COEF2_ CVBS_EQ_COEF2[7:0]
LOW
5Ch CVBS_EQ_COEF2_
HIGH
-
-
-
-
-
-
-
-
-
-
5Dh CVBS_EQ_COEF3_ CVBS_EQ_COEF3[7:0]
LOW
5Eh
5Fh
60h
61h
62h
CVBS_EQ_COEF3_
HIGH
-
-
CVBS_EQ_COEF4_ CVBS_EQ_COEF4[7:0]
LOW
CVBS_EQ_COEF4_
HIGH
-
-
CVBS_EQ_COEF5_ CVBS_EQ_COEF5[7:0]
LOW
CVBS_EQ_COEF5_
HIGH
-
-
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Table 10. I2C-bus register reference
Index
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
28h
Name
I2C-bus access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Default value
01h
00h
04h
01h
27h
04h
10h
84h
08h
85h
F6h
92h
55h
55h
55h
21h
11h
01h
A0h
90h
67h
88h
F0h
3Fh
02h
88h
80h
00h
6Fh
01h
73h
08h
21h
02h
08h
04h
-
Reference
Table 11
Table 12
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 21
Table 21
Table 22
Table 22
Table 22
Table 23
Table 24
Table 25
Table 26
Table 27
Table 28
Table 29
Table 30
Table 31
Table 32
-
STANDARD
EASY_PROG
DIV_FUNC
ADC_HEADR
PC_PLL_FUNC
PC_PLL_THRES
PC_PLL_WGT
PC_FLL_FUNC
CARDET_LEVEL
DTO_PC_LOW
DTO_PC_MID
DTO_PC_HIGH
DTO_SC_LOW
DTO_SC_MID
DTO_SC_HIGH
FILTERS_1
FILTERS_2
GRP_DELAY
D_IF_AGC_SET_1
D_IF_AGC_SET_2
D_IF_AGC_FORCE
T_IF_AGC_SET
T_IF_AGC_LIM
T_IF_AGC_FORCE
T_IF_AGC_FS
reserved
reserved
-
reserved
-
V_SYNC_DEL
CVBS_SET
Table 33
Table 34
Table 35
Table 36
Table 37
Table 38
Table 39
Table 40
Table 41
Table 42
Table 44
Table 45
Table 46
CVBS_LEVEL
CVBS_EQ
SOUNDSET_1
SOUNDSET_2
SOUND_LEVEL
SSIF_LEVEL
ADC_SAT
AFC
R
-
HVPLL_STAT
D_IF_AGC_STAT
T_IF_AGC_STAT
R
-
R
-
R
-
TDA8295_C2_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 27 November 2009
19 of 83
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Table 10. I2C-bus register reference …continued
Index
29h
Name
I2C-bus access
Default value
-
Reference
-
reserved
R
2Ah
ANALOG_DEBUG
R/W
-
00h
-
Table 47
-
2Bh to 2Eh not used
2Fh
IDENTITY
R
-
Table 48
Table 49
-
30h
CLB_STDBY
R/W
R/W
R
01h
00h
-
31h
reserved
32h
ANALOG_STAT
ADC_CTL
Table 50
Table 51
Table 52
Table 53
Table 54
Table 55
Table 56
-
33h
R/W
R/W
R/W
R/W
R/W
R/W
-
24h
01h
7Eh
00h
00h
20h
-
34h
ADC_CTL_2
35h
VIDEODAC_CTL
AUDIODAC_CTL
DAC_REF_CLK_CTL
PLL_REG00
36h
37h
38h
39h to 3Bh
3Ch
3Dh
3Eh
not used
PLL_REG04
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
00h
-
Table 57
-
not used
PLL_REG06
61h
00h
1Ah
02h
01h
00h
11h
01h
07h
-
Table 58
Table 60
Table 60
Table 60
Table 60
Table 61
Table 62
Table 63
Table 65
-
3Fh
PLL_REG07
40h
PLL_REG08
41h
PLL_REG09
42h
PLL_REG10
43h
XTALOSC_CTL
GPIOREG_0
44h
45h
GPIOREG_1
46h
GPIOREG_2
47h to 4Ah
4Bh
reserved
GD_EQ_SECT1_C1
GD_EQ_SECT1_C2
GD_EQ_SECT2_C1
GD_EQ_SECT2_C2
GD_EQ_SECT3_C1
GD_EQ_SECT3_C2
GD_EQ_SECT4_C1
GD_EQ_SECT4_C2
not used
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
00h
00h
00h
00h
00h
00h
00h
00h
-
Table 66
Table 66
Table 66
Table 66
Table 66
Table 66
Table 66
Table 66
-
4Ch
4Dh
4Eh
4Fh
50h
51h
52h
53h to 56h
57h
CVBS_EQ_COEF0_LOW
CVBS_EQ_COEF0_HIGH
CVBS_EQ_COEF1_LOW
CVBS_EQ_COEF1_HIGH
CVBS_EQ_COEF2_LOW
CVBS_EQ_COEF2_HIGH
R/W
R/W
R/W
R/W
R/W
R/W
00h
00h
00h
00h
00h
00h
Table 68
Table 68
Table 68
Table 68
Table 68
Table 68
58h
59h
5Ah
5Bh
5Ch
TDA8295_C2_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 27 November 2009
20 of 83
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Table 10. I2C-bus register reference …continued
Index
5Dh
5Eh
5Fh
60h
Name
I2C-bus access
Default value
Reference
Table 68
Table 68
Table 68
Table 68
Table 68
Table 68
CVBS_EQ_COEF3_LOW
CVBS_EQ_COEF3_HIGH
CVBS_EQ_COEF4_LOW
CVBS_EQ_COEF4_HIGH
CVBS_EQ_COEF5_LOW
CVBS_EQ_COEF5_HIGH
R/W
R/W
R/W
R/W
R/W
R/W
00h
00h
00h
00h
00h
00h
61h
62h
9.3 Register description
If registers (or bit groups contained in registers) are programmed with invalid values, i.e.
values different from those described in the tables below, the default behavior is chosen
for the related block.
9.3.1 Standard setting with easy programming
With the implemented ‘easy programming’, only one bit sets the TV or FM radio standard
with recommended register content. If not suitable however, any of these registers can be
written with other settings. With the rising edge of the bit ACTIVE, the registers 02h to 23h
are programmed internally with the standard dependent settings according to Table 13.
The content of registers with address 24h and higher is untouched.
Table 11. STANDARD register (address 00h) bit description
Legend: * = default value.
Bit
Symbol
Access Value
Description
7 to 0 STANDARD[7:0 R/W
]
TV or FM radio standard selection (easy
programming)
0000 0001*
0000 0010
0000 0100
0000 1000
0001 0000
0010 0000
0100 0000
1000 0000
M/N standard
B standard
G/H standard
I standard
D/K standard
L standard
L-accent standard
FM radio
Table 12. EASY_PROG register (address 01h) bit description
Legend: * = default value.
Bit
7 to 1 -
ACTIVE
Symbol
Access Value
Description
R/W
R/W
-
not used
0
With the rising edge of this bit, the registers
02h to 23h are programmed with the standard
dependent settings (see Table 13).
0*
no action
1
no action
0 to 1
activate easy programming
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Digital global standard low IF demodulator for analog TV and FM radio
Example: To set the device to B standard e.g., please do the following steps.
1. Write 02h to register STANDARD, address 00h (set B standard)
2. Write 00h to register EASY_PROG, address 01h (make sure that ACTIVE = 0)
3. Write 01h to register EASY_PROG, address 01h (due to 0 to 1 transition of ACTIVE
the device is set to B standard, i.e. registers 02h to 23h are programmed
automatically according to Table 13)
4. Write 00h to register EASY_PROG, address 01h (reset ACTIVE to logic 0)
TDA8295_C2_2
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Product data sheet
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NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Table 13. Easy programming values
Register
Standard
M/N[1]
04h
Index Name
B
G/H
04h
01h
27h
04h
10h
84h
08h
7Bh
09h
6Dh
DAh
4Bh
68h
44h
12h
02h
A0h
90h
67h
88h
F0h
3Fh
02h
88h
80h
00h
6Fh
01h
73h
08h
22h
02h
04h
04h
I
D/K
04h
01h
27h
04h
10h
84h
08h
7Bh
09h
6Dh
5Fh
42h
7Bh
44h
12h
04h
A0h
90h
67h
88h
F0h
3Fh
02h
88h
80h
00h
6Fh
01h
73h
08h
22h
02h
04h
04h
L
L-accent FM radio
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
DIV_FUNC
04h
01h
27h
04h
10h
84h
08h
00h
00h
80h
DAh
4Bh
68h
42h
12h
02h
A0h
90h
67h
88h
F0h
3Fh
02h
88h
80h
00h
6Fh
01h
73h
08h
22h
02h
04h
04h
04h
01h
27h
04h
10h
84h
08h
7Bh
09h
6Dh
1Dh
C7h
71h
44h
12h
10h
A0h
90h
67h
88h
F0h
3Fh
02h
88h
80h
00h
6Fh
01h
73h
08h
22h
02h
04h
04h
06h
01h
27h
04h
10h
84h
08h
7Bh
09h
6Dh
5Fh
42h
7Bh
44h
12h
08h
A0h
90h
67h
88h
F0h
3Fh
02h
88h
80h
00h
6Fh
01h
6Ch
08h
44h
02h
04h
04h
07h
01h
27h
04h
10h
84h
08h
26h
B4h
17h
5Fh
42h
7Bh
44h
12h
08h
A0h
90h
67h
88h
F0h
3Fh
02h
88h
80h
00h
6Fh
01h
6Ch
08h
44h
02h
04h
04h
00h
01h
22h
04h
10h
04h
08h
00h
00h
80h
DAh
4Bh
68h
90h
14h
10h
A0h
08h
E7h
88h
F0h
3Fh
02h
88h
80h
00h
6Fh
04h
73h
10h
22h
02h
02h
04h
ADC_HEADR
01h
PC_PLL_FUNC
PC_PLL_THRES
PC_PLL_WGT
PC_FLL_FUNC
CARDET_LEVEL
DTO_PC_LOW
DTO_PC_MID
DTO_PC_HIGH
27h
04h
10h
84h
08h
85h
F6h
92h
0Ch DTO_SC_LOW
0Dh DTO_SC_MID
55h
55h
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
DTO_SC_HIGH
FILTERS_1
55h
21h
FILTERS_2
11h
GRP_DELAY
01h
D_IF_AGC_SET_1 A0h
D_IF_AGC_SET_2 90h
D_IF_AGC_FORCE 67h
T_IF_AGC_SET
T_IF_AGC_LIM
88h
F0h
T_IF_AGC_FORCE 3Fh
T_IF_AGC_FS
reserved
02h
88h
80h
00h
6Fh
01h
73h
08h
21h
02h
08h
04h
reserved
reserved
1Ch V_SYNC_DEL
1Dh CVBS_SET
1Eh
1Fh
20h
21h
22h
23h
CVBS_LEVEL
CVBS_EQ
SOUNDSET_1
SOUNDSET_2
SOUND_LEVEL
SSIF_LEVEL
[1] M/N standard settings are equal to the power-on reset (default) values.
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Digital global standard low IF demodulator for analog TV and FM radio
9.3.2 Diverse functions (includes tuner IF AGC Pin mode)
Table 14. DIV_FUNC register (address 02h) bit description
Legend: * = default value.
Bit
Symbol
Access Value Description
7
AGC_SEL R/W
It determines the tuner IF AGC output Pin mode. The
open-drain output can be used in special applications in
need of a higher control voltage.
0*
1
Normal mode
Open-drain mode
6
AGC_TRI R/W
When AGC_TRI is set to logic 1 the tuner IF AGC output
pin is in 3-state mode. This mode is useful for paralleling a
channel decoder for instance.
0*
1
-
Normal mode
3-state mode
5 and 4 -
R/W
R/W
not used
3
2
-
0
reserved, must be set to logic 0
POL_DET R/W
The polarity detector ensures the proper polarity of the
video signal. So, the sync impulses of the video output are
near ground level.
0
polarity detector off
polarity detector on
1*
1
0
VID_MOD R/W
IF_SWAP R/W
Selects video modulation. The only standards with positive
video modulation are L and L-accent.
0*
1
negative video modulation
positive video modulation
When HIGH, the demodulator expects a swapped IF
spectrum. This is the case in L-accent standard. This option
is also built in for flexibility reasons.
0*
1
normal IF spectrum expected
swapped IF spectrum expected
9.3.3 ADC headroom
Table 15. ADC_HEADR register (address 03h) bit description
Legend: * = default value.
Bit
7 to 4 -
3 to 0 ADC_HEADR[3:0] R/W
Symbol
Access Value Description
R/W
-
not used
ADC_HEADR adjusts the needed headroom for the
wanted channel’s own sound carriers and the N − 1
adjacent sound carriers (PC in L-accent standard).
The ADC headroom is related to the sum of all
signals. This function is built in for debugging
purposes.
0001*
0010
0100
1000
ADC headroom 3 dB
ADC headroom 6 dB
ADC headroom 9 dB
ADC headroom 12 dB
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Digital global standard low IF demodulator for analog TV and FM radio
9.3.4 Picture carrier PLL functions
Table 16. PC_PLL_FUNC register (address 04h) bit description
Legend: * = default value.
Bit
Symbol
Access Value
Description
7 to 3 PC_PLL_BW[4:0] R/W
picture carrier PLL loop bandwidth selection
loop bandwidth 15 kHz
loop bandwidth 30 kHz
loop bandwidth 60 kHz
loop bandwidth 130 kHz
0 0001
0 0010
0 0100*
0 1000
1 0000
loop bandwidth 280 kHz (for very bad transmitter
quality)
2
1
0
PLL_ON
PULL_IN
CAR_DET
R/W
R/W
R/W
the picture carrier PLL can be disengaged (e.g. in
FM radio standard)
0
PLL off (FM radio)
PLL on
1*
PULL_IN selects the pull-in range of the picture
carrier PLL/FPLL
0
pull-in range ±1.66 MHz
pull-in range ±830 kHz
1*
The carrier detector freezes the PLL in case of a
picture carrier overmodulation (especially when the
picture carrier is very low or disappears). In
addition, the picture carrier DTO value is forced to
an optimal one to avoid picture carrier phase drift.
To adjust the threshold see CAR_DET_LVL.
0*
1
carrier detector off
carrier detector on
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Digital global standard low IF demodulator for analog TV and FM radio
Table 17. PC_PLL_THRES register (address 05h) bit description
Legend: * = default value.
Bit
7 to 4 -
3 to 0 PH_ERR_THRES[3:0] R/W
Symbol
Access Value Description
R/W
-
not used
When the settable threshold for the linear phase
detector as part of the picture carrier PLL is
passed, the phase detector slope is weighted
according to the settings in PHASE_GAIN. This
feature is of advantage during adverse field
conditions. In case multipath happens like
ghosts, the PC PLL should not follow the sudden
phase jumps. So, the PC PLL is made slow
(lower loop bandwidth) with PC_PLL_THRES
after surpassing the threshold. This threshold is
related to a fraction of FS. There, FS is 90° if
PHASE_PER is logic 0 (default) or 180° when
logic 1. If the ICPM or ICFM is large because of
bad transmitters with oscillator pulling or
modulator imbalance, the PC PLL should follow
as true as possible. This can be done by
increasing the loop bandwidth with overweighting
(see PHASE_GAIN, Table 18).
1
0001
0010
0100*
1000
⁄
32 FS
1
⁄16 FS
1⁄8 FS
1⁄4 FS
Table 18. PC_PLL_WGT register (address 06h) bit description
Legend: * = default value.
Bit
Symbol
Access Value
Description
7
PHASE_PER
R/W
By default, the linear phase detector transfer
function is repetitive in π. This allows a good
picture carrier overmodulation performance,
because the PC PLL doesn’t need to reacquire
the 180° phase modulation, caused by the
excessive AM index above m = 100 % (negative
residual picture carrier).
0*
1
π (needed for overmodulation)
2π
6 to 0 PHASE_GAIN[6:0] R/W
phase error weighting (adaptive loop speed), see
also PH_ERR_THRES in Table 17 for
explanation
000 0001
000 0010
000 0100
000 1000
001 0000*
010 0000
100 0000
× 1⁄16
× 1⁄8
× 1⁄4
× 1⁄2
flat (no weighting)
× 2
× 4
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Digital global standard low IF demodulator for analog TV and FM radio
Table 19. PC_FLL_FUNC register (address 07h) bit description
Legend: * = default value.
Bit
Symbol
Access Value
Description
7
FLL_ON
R/W
The FLL can be switched off for debugging purposes.
In Functional mode, FLL_ON must be logic 1 for all
cases.
0
1*
FLL off (only for debugging)
FLL on
6
LIM_ON
R/W
The default value is logic 0 to have a normal action
FLL. However, some flexibility has been included for
field investigations and debugging purposes.
0*
1
limitation off
limitation on
5 to 0 FLL_LIM[5:0] R/W
With these settings, the FLL action can be reduced. For
better acquisition behavior, a large value should be
chosen. The settings are ‘don’t care’ if LIM_ON is
logic 0.
1
00 0001
00 0010
00 0100*
00 1000
01 0000
10 0000
⁄4096 FS
⁄2048 FS
⁄1024 FS
⁄512 FS
⁄256 FS
⁄128 FS
1
1
1
1
1
Table 20. CARDET_LEVEL register (address 08h) bit description
Legend: * = default value.
Bit
7 to 5 -
4 to 0 CAR_DET_LVL[4:0] R/W
Symbol
Access Value
Description
R/W
-
not used
determines the action threshold of the above
carrier detector; if carrier detector is off,
CAR_DET_LVL settings are irrelevant
0 0001
0 0010
0 0100
0 1000*
1 0000
X XXXX
carrier detector action below 0.5 % residual PC
carrier detector action below 1 % residual PC
carrier detector action below 2 % residual PC
carrier detector action below 4 % residual PC
carrier detector action below 8 % residual PC
don’t care if CAR_DET = 0
TDA8295_C2_2
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Product data sheet
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TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
9.3.5 Picture and sound carrier DTO
Table 21. DTO_PC_LOW, DTO_PC_MID and DTO_PC_HIGH register (address 09h to 0Bh) bit description
Legend: * = default value.
Address Register
Bit
Symbol
Access Value Description
09h
0Ah
0Bh
DTO_PC_LOW 7 to 0 DTO_PC[7:0]
R/W
85h*
F6h*
92h*
With the digitally tuned picture carrier oscillator
(DTO_PC), the IF frequency for the picture carrier
demodulation can be set. This function is
DTO_PC_MID 7 to 0 DTO_PC[15:8] R/W
DTO_PC_HIGH 7 to 0 DTO_PC[23:16] R/W
implemented for general purpose applications which
are different from nominal TV standards. It can also
be used for debugging purposes. The DTO_PC is
part of the picture carrier PLL. To set the DTO_PC
value to a certain PC input frequency (fIF), please
use the following formula:
13.5 MHz – fIF
24
-----------------------------------
DTO_PC =
× 2 . If e.g. the IF
13.5 MHz
picture carrier input frequency is 5.75 MHz
(M/N standard), one gets 92 F685h as result for
DTO_PC.
Table 22. DTO_SC_LOW, DTO_SC_MID and DTO_SC_HIGH register (address 0Ch to 0Eh) bit description
Legend: * = default value.
Address Register
Bit
Symbol
Access Value Description
0Ch
0Dh
0Eh
DTO_SC_LOW 7 to 0 DTO_SC[7:0]
R/W
55h*
55h*
55h*
The DTO_SC is part of the FM/AM mono sound
demodulator. DTO_SC is calculated according to the
following formula, whereas fSC is the sound carrier
DTO_SC_MID 7 to 0 DTO_SC[15:8] R/W
DTO_SC_HIGH 7 to 0 DTO_SC[23:16] R/W
fSC
24
-----------------------
frequency: DTO_SC =
× 2
.
13.5 MHz
In case of M/N standard (sound carrier at 4.5 MHz),
one gets 55 5555h for DTO_SC.
TDA8295_C2_2
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Product data sheet
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TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
9.3.6 Filter settings
Table 23. FILTERS_1 register (address 0Fh) bit description
Legend: * = default value.
Bit
Symbol
Access Value
Description
7 to 5 VID_FILT[2:0]
R/W
video low-pass filter to remove all unwanted
frequencies (own sound carriers) above video
content (see Figure 7)
001*
video low-pass filter 4 MHz
video low-pass filter 5 MHz
video low-pass filter off
010
100
4 to 0 NOTCH_FILT[4:0]
R/W
The notch filter attenuates the adjacent sound
carrier N − 1, which is located differently
dependent on channel spacing 6 MHz, 7 MHz or
8 MHz (see Figure 8).
0 0001*
0 0010
0 0100
1 0000
notch filter for 6 MHz channel spacing
(M/N standard)
notch filter for 7 MHz channel spacing
(B standard)
notch filter for 8 MHz channel spacing (G/H,
D/K, I, L and L-accent standard)
notch/low-pass filter off
001aah358
10
α
resp(f)
(dB)
−10
−30
−50
−70
(1)
(2)
0
1
2
3
4
5
6
7
f (MHz)
(1) M/N standard.
(2) All other standards.
Fig 7. Video low-pass filters for sound carrier suppression
TDA8295_C2_2
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Product data sheet
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TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
001aah359
10
α
resp(f)
(dB)
0
−10
−20
−30
−40
−50
−60
(1)
(2)
(3)
0
2
4
6
8
10
12
14
f (MHz)
Notch filter for NSC (NPC for L-accent standard)
(1) M/N standard.
(2) B standard.
(3) G/H, D/K, I, L and L-accent standard.
Fig 8. Notch filter for adjacent sound carrier suppression
Table 24. FILTERS_2 register (address 10h) bit description
Legend: * = default value.
Bit
7 to 5 -
DC_NOTCH R/W
Symbol
Access Value Description
R/W
-
not used
4
notch filter to remove ADC DC offset
0
off
on
1*
3 to 0 SBP[3:0]
R/W
The SSIF band-pass attenuates unwanted video
frequencies, e.g. color carrier. For FM radio standard it
provides almost channel selectivity (see Figure 9).
0001*
0010
0100
1000
SSIF band-pass 4.5 MHz (M/N standard)
SSIF band-pass 6.2 MHz (all other TV standards)
SSIF band-pass 5.5 MHz high selectivity (FM radio)
SSIF band-pass off
TDA8295_C2_2
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Product data sheet
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TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
001aah360
10
α
resp(f)
(dB)
(1)
(2)
(3)
−10
−30
−50
−70
0
2
4
6
8
10
12
14
f (MHz)
(1) M/N standard.
(2) All other standards.
(3) FM radio.
Fig 9. SSIF and FM radio band-pass filters
9.3.7 Group delay equalization
Table 25. GRP_DELAY register (address 11h) bit description
Legend: * = default value.
Bit
Symbol
Access Value
Description
7
GD_EQ_CTRL R/W
group delay equalizer control; this is the control for
the freely programmable group delay equalizer; for
details see Section 9.3.21
0*
1
-
off (equalizer bypassed)
on (equalizer active)
not used
6 and 5 -
R/W
4 to 0 GRP_DEL[4:0] R/W
group delay equalization to correct the transmitter
predistortion
0 0001*
0 0010
0 0100
0 1000
1 0000
group delay M/N standard
group delay B/G/H standard
group delay D/K standard
group delay L/L-accent standard
group delay I (flat) standard
TDA8295_C2_2
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TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
9.3.8 Digital IF AGC functions
Table 26. D_IF_AGC_SET_1 register (address 12h) bit description
Legend: * = default value.
Bit
Symbol
Access Value
Description
7
D_IF_AGC_CORR
R/W
This determines the condition under which the
digital IF AGC switches to Correlated mode. If
D_IF_AGC_CORR is HIGH, the digital IF AGC
works in a Correlated mode only if N_H_LOCK,
F_H_LOCK and V_LOCK are active (see
H/V PLL read-out in Table 44). If LOW, the
Correlated mode is activated when N_H_LOCK
and V_LOCK are active.
0
1*
H-lock + V-lock
H-lock + fast H-lock + V-lock
6
D_IF_AGC_MODE
R/W
If HIGH, the digital IF AGC detection and gating
is done during the back porch of the video
signal. This Detection mode can be used for all
standards (also L/L-accent standard) without
impact on the IF AGC loop speed.
0*
1
peak sync AGC (slow peak white L/L-accent
standard)
black level AGC detection
5 to 1 D_IF_AGC_AVG[4:0] R/W
With D_IF_AGC_AVG the number of lines for
averaging during the digital IF AGC gating
window is set. This is only valid if the AGC mode
is correlated (H/V PLL locked). With the
averaging, the line noise at low RF levels is
reduced.
0 0001
0 0010
0 0100
0 1000
1 0000*
2 samples
4 samples
8 samples
16 samples
32 samples
0
RST_INT
R/W
The digital IF AGC integrator can be set to zero
(i.e. lowest digital IF AGC gain). This option can
be used for debugging purposes.
0*
1
normal operation
reset IF AGC integrator
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Product data sheet
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TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Table 27. D_IF_AGC_SET_2 register (address 13h) bit description
Legend: * = default value.
Bit
Symbol
Access Value
Description
7
D_AGC_ERR_LIM R/W
With D_AGC_ERR_LIM the digital IF AGC
error slope is limited. This can improve
performance under the presence of e.g.
impulsive noise that can confuse the AGC
detector.
0
limitation off
1*
limitation on
6 to 0 D_IF_AGC_BW[6:0] R/W
digital IF AGC 3 dB-loop bandwidth setting
000 0001
000 0010
000 0100
000 1000
001 0000*
010 0000
100 0000
25 Hz
50 Hz
100 Hz
200 Hz
400 Hz
800 Hz
1.6 kHz
Table 28. D_IF_AGC_FORCE register (address 14h) bit description
Legend: * = default value.
Bit
Symbol
Access Value Description
R/W the IF AGC output voltage can be forced externally
7
D_FORCE
to a fixed voltage, determined by IF_AGC_EXT
0*
1
IF AGC normal operation
IF AGC output voltage determined by
D_FORCE_VAL
6 to 0 D_FORCE_VAL[6:0] R/W
This determines the digital IF AGC forced value
and is a ‘don’t care’ if D_FORCE is LOW. The
format is twos complement. The default is 67h,
which equals 0 dB internal gain. In the following
some possible settings for 6 dB gain steps are
shown.
51h
5Ch
67h*
72h
7Dh
08h
13h
1Eh
29h
34h
3Fh
XXh
−12 dB
−6 dB
0 dB
+6 dB
+12 dB
+18 dB
+24 dB
+30 dB
+36 dB
+42 dB
+48 dB
don’t care if D_FORCE = 0
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Digital global standard low IF demodulator for analog TV and FM radio
9.3.9 Tuner IF AGC functions
Table 29. T_IF_AGC_SET register (address 15h) bit description
Legend: * = default value.
Bit
Symbol
Access Value
Description
7
POL_TIF
R/W
0
tuner IF AGC polarity
inverted tuner IF AGC polarity
1*
normal tuner IF AGC polarity: the higher
the necessary gain, the higher the IF
AGC voltage
6 to 0 T_IF_AGC_SPEED[6:0] R/W
T_IF_AGC_SPEED determines the tuner
IF AGC loop speed
000 0001
000 0010
000 0100
000 1000*
−18 dB nominal
−12 dB nominal
−6 dB nominal
nominal speed (determined by the tuner
IF control slope)
001 0000
010 0000
100 0000
+6 dB nominal
+12 dB nominal
+18 dB nominal
Table 30. T_IF_AGC_LIM register (address 16h) bit description
Legend: * = default value.
Bit
Symbol
Access Value Description
7 to 4 UP_LIM[3:0]
R/W The tuner IF AGC output voltage can be limited to
interface with concepts having power supply < 3.3 V.
UP_LIM determines the upper limit from 1⁄2 FS (= 0h) to
FS (= Fh). The format is straight binary.
1111*
0000*
set upper limit to maximum
3 to 0 LOW_LIM[3:0] R/W
LOW_LIM determines the lower tuner IF AGC output
limit from 0 (= 0h) to 1⁄2 FS (= Fh). The format is straight
binary.
set lower limit to minimum
Table 31. T_IF_AGC_FORCE register (address 17h) bit description
Legend: * = default value.
Bit
Symbol
Access Value Description
R/W the tuner IF AGC output voltage can be forced
7
T_FORCE
externally to a fixed voltage, determined by
T_FORCE_VAL
0*
1
tuner IF AGC normal operation
tuner IF AGC output voltage determined by
T_FORCE_VAL
6 to 0 T_FORCE_VAL[6:0] R/W
T_FORCE_VAL determines the tuner IF AGC
forced value. So the tuner IF AGC can be fixed to
a certain value for debugging purposes. Format is
straight binary.
3Fh*
XXh
0.5 × VDD(3V3), i.e. 1.65 V nominally
don’t care if T_FORCE = 0
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Digital global standard low IF demodulator for analog TV and FM radio
Table 32. T_IF_AGC_FS register (address 18h) bit description
Legend: * = default value.
Bit
7 to 3 -
2 to 0 T_IF_AGC_FS[2:0] R/W
Symbol
Access Value
Description
R/W
-
not used
by increasing the IF AGC noise shaper sampling
rate (fs), the noise shaper in-band disturbance
(line clamping noise) can be heavily reduced
000
010*
100
fs = 13.5 MHz
fs = 27 MHz
fs = 54 MHz
9.3.10 V-sync adjustment
Table 33. V_SYNC_DEL register (address 1Ch) bit description
Legend: * = default value.
Bit
Symbol
Access Value
Description
7 and 6 VS_WIDTH[1:0] R/W
VS_WIDTH determines the width (in horizontal
lines) of the V-sync gating pulse (needed for gating
of tuner RF AGC2)
00
01*
10
11
width 1 line (64 μs)
width 2 lines
width 4 lines
width 16 lines
5
VS_POL
R/W
R/W
VS_POL determines the polarity of the V-sync
pulse: if VS_POL = 1, the first edge of the pulse is
positive, else negative.
0
first edge negative
first edge positive
1*
4 to 0
VS_DEL[4:0]
VS_DEL determines the first edge position of the
output V-sync pulse compared to the beginning of
the vertical blanking interval:
pulse_position = (VS_DEL – 12) lines
0Fh*
first edge 3 lines after beginning of vertical
interval
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Digital global standard low IF demodulator for analog TV and FM radio
9.3.11 CVBS settings
Table 34. CVBS_SET register (address 1Dh) bit description
Legend: * = default value.
Bit
Symbol
Access Value Description
7 to 4 -
R/W
-
not used
3
2
1
0
CVBS_EQ_ R/W
CTRL
video equalizer mode control
0*
1
mode using predefined settings like described in
Table 36
free programmable mode; for details see Section 9.3.21
FOR_BLK
R/W
when active, the video output is always blanked, e.g. for
channel change (forced blank)
0*
1
no action
video blanked
AUTO_BLK R/W
when active, the video output is blanked if the horizontal
line lock flag (N_H_LOCK, see Table 44) is not present
0*
1
auto-blanking off
auto-blanking on
VID_LVL
R/W
the video levelling stage ensures a constant and clipping
free video output level (important for excessive picture
carrier overmodulation)
0
video levelling stage off
video levelling stage on
1*
Table 35. CVBS_LEVEL register (address 1Eh) bit description
Legend: * = default value.
Bit
Symbol
Access Value Description
7 to 0 CVBS_LVL[7:0] R/W
With this byte, the nominal video output level is freely
programmable. The format is unsigned integer (offset
binary). Settings below 40h and above C0h, which
correspond to −5 dB (40h) and +4.5 dB (C0h) related to
the default value, are forbidden. In the following some
possible settings in 1 dB steps are shown.
51h
5Bh
66h
73h*
81h
91h
A2h
−3 dB nominal
−2 dB nominal
−1 dB nominal
nominal: 1 V (p-p) video output level (sync-peak)
+1 dB nominal
+2 dB nominal
+3 dB nominal
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Digital global standard low IF demodulator for analog TV and FM radio
Table 36. CVBS_EQ register (address 1Fh) bit description
Legend: * = default value.
Bit
Symbol
Access Value
Description
7 to 0 CVBS_EQ[7:0] R/W
The video equalizer can be used for the
compensation of a principal tuner tilt or to change
the video frequency according to customer taste.
The figures given are at 5 MHz CVBS with respect
to low frequencies (see Figure 10).
0000 0001
0000 0010
0000 0100
0000 1000*
0001 0000
0010 0000
0100 0000
1000 0000
The video frequency response is −8 dB for
5 MHz.
The video frequency response is −6 dB for
5 MHz.
The video frequency response is −4 dB for
5 MHz.
The video frequency response is −2 dB for
5 MHz.
The video frequency response is made flat in this
mode.
The video frequency response is +2 dB (peaking)
for 5 MHz.
The video frequency response is +4 dB (peaking)
for 5 MHz.
The video frequency response is +6 dB (peaking)
for 5 MHz.
001aah361
10
α
resp(f)
(dB)
6
2
−2
−6
−10
0
1
2
3
4
5
6
7
f (MHz)
Fig 10. Video equalizer curves
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Digital global standard low IF demodulator for analog TV and FM radio
9.3.12 SSIF and mono sound settings
Table 37. SOUNDSET_1 register (address 20h) bit description
Legend: * = default value.
Bit
Symbol
Access Value
Description
7
-
R/W
R/W
-
not used
6 and 5 AM_FM_SND[1:0]
Output mode for inbuilt FM/AM mono sound
demodulator
01*
10
FM sound
AM sound (only L/L-accent standard)
XX
don’t care if SSIF output is chosen
(SSIF_SND[1:0] = 10)
4 to 0
DEEMPH[4:0]
R/W
mono sound de-emphasis adjustment to
compensate transmitter pre-emphasis; or
low-pass filter to remove out of audio band
interferers
0 0001*
0 0010
0 0100
0 1000
1 0000
de-emphasis of 75 μs for M/N standard or
non-European FM radio to compensate the
transmitter pre-emphasis
de-emphasis of 50 μs for B/G/H, D/K and
I standard or European FM radio to
compensate the transmitter pre-emphasis
low-pass filter with 30 kHz −3 dB cut-off
frequency to remove out of audio band
interferers
low-pass filter with 140 kHz −3 dB cut-off
frequency to drive an external BTSC stereo
decoder
The de-emphasis filter is bypassed. This
can be used for debugging or other
purposes.
Table 38. SOUNDSET_2 register (address 21h) bit description
Legend: * = default value.
Bit
7 to 5
4
Symbol
-
Access Value Description
R/W
R/W
-
not used
HD_DK
When active, the internal FM mono sound
demodulator can handle excessive FM deviations up
to 400 kHz. This might happen in D/K standard China.
To activate this mode, it is mandatory to set
D/K standard first. The sound output level has to be
adapted accordingly by the microprocessor to avoid
sound DAC clipping. E.g. for 400 kHz FM deviation,
the −12 dB setting of the sound level register
(see Table 39) is recommended.
0*
1
high Deviation mode off
high Deviation mode on
X
don’t care if SSIF output is chosen
(SSIF_SND[1:0] = 10)
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Digital global standard low IF demodulator for analog TV and FM radio
Table 38. SOUNDSET_2 register (address 21h) bit description …continued
Legend: * = default value.
Bit
Symbol
Access Value Description
R/W When active, the mono sound signal is always muted.
3
FOR_MUTE
This setting only makes sense in case the sound DAC
output is also set to mono sound
(SSIF_SND[1:0] = 01). FOR_MUTE has no function if
SSIF_SND[1:0] = 10.
0*
1
off
on
X
don’t care if SSIF output is chosen
(SSIF_SND[1:0] = 10)
2
AUTO_MUTE R/W
When active, the mono sound signal is muted if the
horizontal lock flag (N_H_LOCK) disappears. This
setting only makes sense in case the sound DAC
output is also set to mono sound
(SSIF_SND[1:0] = 01). FOR_MUTE has no function if
SSIF_SND[1:0] =10.
0*
1
off
on
X
don’t care if SSIF output is chosen
(SSIF_SND[1:0] = 10)
1 and 0 SSIF_SND[1:0] R/W
either mono sound or SSIF can be chosen for the
sound DAC output
01
mono sound
SSIF
10*
Table 39. SOUND_LEVEL register (address 22h) bit description
Legend: * = default value.
Bit
7 to 5 -
4 to 0 SND_LVL[4:0] R/W
Symbol
Access Value
Description
R/W
-
not used
mono sound output level
0 0001
−12 dB nominal; implemented for flexibility reasons.
With this setting, the adaptation to different standard
requirements can be done.
0 0010
0 0100
−6 dB nominal; implemented for flexibility reasons.
With this setting, the adaptation to different standard
requirements can be done. It is chosen for FM radio
because of the large FM deviation involved.
Nominal setting; FM deviations up to 100 kHz can be
processed without sound DAC clipping. The clipping
level is 535 mV (RMS) typically.
0 1000*
1 0000
+6 dB nominal; chosen for M/N standard due to less
nominal frequency deviation
+12 dB nominal; implemented for flexibility reasons.
With this setting, the adaptation to different standard
requirements can be done.
X XXXX
don’t care if SSIF output is chosen
(SSIF_SND[1:0] = 10)
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Digital global standard low IF demodulator for analog TV and FM radio
Table 40. SSIF_LEVEL register (address 23h) bit description
Legend: * = default value.
Bit
7 to 5 -
4 to 0 SSIF_LVL[4:0] R/W
Symbol
Access Value
Description
not used
R/W
-
SSIF output level
0 0001
−12 dB nominal; implemented for flexibility reasons.
With this setting, the adaptation to different standard
requirements can be done.
0 0010
−6 dB nominal; implemented for flexibility reasons.
With this setting, the adaptation to different standard
requirements can be done.
0 0100*
0 1000
Nominal setting; typical output level is 55 mV (RMS)
for PC / SC ratio of 13 dB (see Section 12).
+6 dB nominal; implemented for flexibility reasons.
With this setting, the adaptation to different standard
requirements can be done.
1 0000
+12 dB nominal; implemented for flexibility reasons.
With this setting, the adaptation to different standard
requirements can be done.
X XXXX
don’t care if mono sound output is chosen
(SSIF_SND[1:0] = 01)
9.3.13 Status registers: ADC saturation, AFC, H/V PLL and AGC
Table 41. ADC_SAT register (address 24h) bit description
Bit
Symbol
Access Value
Description
7 to 0 ADC_SAT[7:0]
R
-
With ADC_SAT, the ADC saturation percentage in a
period of 40 ms can be calculated by the following
ADC_SAT
------------------------
formula: saturation =
(%) .
256
Table 42. AFC register (address 25h) bit description
Bit Symbol Access Value Description
7 to 0 AFC[7:0]
This is the readout for AFC[1]. AFC contains the
frequency deviation from nominal IF picture carrier.
The format is twos complement, 13.2 kHz steps are
done per LSB. See Table 43 and Figure 11 for details.
The frequency deviation could also be given by the
R
-
–AFC × 6 750
---------------------------------
(kHz) .
following formula: fIF – fnom
=
512
For a frequency deviation from the nominal IF picture
carrier greater than the FPLL pull-in capability
(−830.6 kHz to +843.8 kHz or −1674.3 kHz to
+1687.5 kHz), the output reading is undefined. The
AFC lock indication can be taken from the N_H_LOCK
information from the H-sync PLL. The lock occurs
inside a frequency window, which is determined by the
pull-in capability of the FPLL.
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Digital global standard low IF demodulator for analog TV and FM radio
[1] Depending on actual frequency of crystal or clock signal it might happen in rare cases that AFC read value
is corrupted. For channel search algorithm it is recommended to read three times the AFC register and
discard the obviously false value.
001aal143
1100
−AFC × 6750
512
(kHz)
700
300
−100
−500
−900
−1000
−600
−200
200
600
− f
1000
at input (kHz)
nom
f
IF
Fig 11. Typical AFC readout versus frequency deviation of picture carrier
Table 43. Calculation of frequency deviation from AFC value
Deviation from nominal AFC[7] AFC[6] AFC[5] AFC[4] AFC[3] AFC[2] AFC[1] AFC[0]
IF frequency[1]
fIF = fnom − 1674.3 kHz
fIF = fnom − 1661.1 kHz
:
0
0
:
1
1
:
1
1
:
1
1
:
1
1
:
1
1
:
1
1
:
1
0
:
fIF = fnom − 830.6 kHz
fIF = fnom − 817.4 kHz
:
0
0
:
0
0
:
1
1
:
1
1
:
1
1
:
1
1
:
1
1
:
1
0
:
fIF = fnom − 13.2 kHz
fIF = fnom
0
0
1
:
0
0
1
:
0
0
1
:
0
0
1
:
0
0
1
:
0
0
1
:
0
0
1
:
1
0
1
:
fIF = fnom + 13.2 kHz
:
fIF = fnom + 830.6 kHz
fIF = fnom + 843.8 kHz
:
1
1
:
1
1
:
0
0
:
0
0
:
0
0
:
0
0
:
0
0
:
1
0
:
fIF = fnom + 1674.3 kHz
fIF = fnom + 1687.5 kHz
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
[1] See Section 12 for nominal IF frequencies.
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Digital global standard low IF demodulator for analog TV and FM radio
Table 44. HVPLL_STAT register (address 26h) bit description
Bit Symbol Access Value Description
7 and 6 -
R
-
-
not used
5
NOISE_DET R
This flag gets HIGH in case the video S/N (weighted)
drops below 30 dB. For proper and noise free video
signals it stays LOW. It can be used for debugging and
other purposes.
4
3
2
1
0
MAC_DET
FIDT
R
R
R
R
R
-
-
-
-
-
This flag indicates the presence of copy-guarded video
content from STBs or VCRs. It can be used for
debugging and other purposes.
This flag indicates the frame rate (50 Hz or 60 Hz).
When active, 60 Hz is detected. It can be used for
debugging and other purposes.
V_LOCK
F_H_LOCK
N_H_LOCK
This flag is active, if a proper frame (50 Hz or 60 Hz) is
detected. It can be used for debugging and other
purposes.
This flag is active, if a proper H-sync (15.625 kHz or
15.734 kHz) is detected (Fast mode). It can be used for
debugging and other purposes.
This flag is active, if a proper H-sync (15.625 kHz or
15.734 kHz) is detected (Normal mode). It can be used
for debugging and other purposes.
Table 45. D_IF_AGC_STAT register (address 27h) bit description
Bit
Symbol
Access Value
Description
7 to 0 D_IF_AGC_STAT[7:0]
R
-
D_IF_AGC_STAT is the digital IF AGC status
readout byte. Contains the digital IF AGC loop
DC information. The format is twos
complement. To get the internal gain in dB, the
following formula can be used:
D_IF_AGC_STAT + 50
--------------------------------------------------------
gain =
(dB) .
3.675
Table 46. T_IF_AGC_STAT register (address 28h) bit description
Bit Symbol Access Value Description
7 to 0 T_IF_AGC_STAT[7:0]
R
-
T_IF_AGC_STAT is the IF AGC status readout
byte. Contains the tuner IF AGC loop DC
information. The format is offset binary.
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Digital global standard low IF demodulator for analog TV and FM radio
9.3.14 Debug register for ADC and DAC test
Table 47. ANALOG_DEBUG register (address 2Ah) bit description
Legend: * = default value.
Bit
Symbol
Access Value Description
7 to 2 -
R/W
-
not used
1
0
ADC_TEST R/W
If ADC_TEST is HIGH, the ADC input signal is interpolated
to 108 MHz and fed to video and sound DAC output; the
main circuitry is bypassed. This feature is intended mainly
for debugging purposes and performance judgment.
0*
1
Normal mode
ADC Test mode
DAC_TEST R/W
DAC Test mode; in this test mode an internally generated
sine wave is given out to video and sound DAC. The
amplitude at DAC output is −1.7 dBFS. The frequency can
be set by DTO_PC. Please use the following formula:
DTO_PC
----------------------
f =
× 13.5 MHz . Due to the sampling theorem
224
only frequencies up to 6.75 MHz can be generated. This
feature is intended mainly for debugging purposes and
performance judgment.
0*
1
Normal mode
DAC Test mode
X
don’t care if ADC_TEST = 1
9.3.15 Chip identification and Standby mode
Table 48. IDENTITY register (address 2Fh) bit description
Bit
Symbol
Access Value
Description
7 to 0 IDENTITY[7:0] R
1000 1010 chip identification, value corresponds to TDA8295
Table 49. CLB_STDBY register (address 30h) bit description
Legend: * = default value.
Bit
Symbol Access Value Description
7 to 2 -
R/W
STDBY R/W
-
not used
1
0
When STDBY is set to logic 1, the chip enters in Standby
mode, and its power consumption is reduced. The IF AGC pin
is set to high-ohmic. The default value is logic 0, which means
that the chip is active.
0*
1
Normal mode
Standby mode
CLB
R/W
This signal clears the TDA8295 through the I2C-bus interface
(software reset). To activate the reset, just write CLB = 0. This
software reset will not affect the content of the registers.
0
activate soft reset
normal operation
1*
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Digital global standard low IF demodulator for analog TV and FM radio
9.3.16 Status of clock PLL and video/sound DAC load
Table 50. ANALOG_STAT register (address 32h) bit description
Bit
Symbol
Access Value Description
7
POR_TEST
R
R
POR block status
0
1
POR test failed
POR test passed
6
5
4
LOAD_DACV
LOAD_DACS
PLL_LOCK
output load identification video DAC
Normal mode
0
1
If active, the video DAC output voltage is above
reference voltage.
R
output load identification sound DAC
Normal mode
0
1
If active, the sound DAC output voltage is above
reference voltage.
R
R
clock PLL lock indicator
clock PLL unlocked
0
1
-
indicates that the clock PLL is locked
reserved
3 to 0 -
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Digital global standard low IF demodulator for analog TV and FM radio
9.3.17 ADC control
In the TDA8295 a 12-bit ADC is implemented sampling with a 54 MHz clock (27 MHz
optional).
Table 51. ADC_CTL register (address 33h) bit description
Legend: * = default value.
Bit
Symbol
Access Value Description
7
GAINSET R/W
The track and hold circuit in the converter has a
programmable gain setting, which is controlled by the
GAINSET parameter. In case the gain of the track and hold is
increased, the input range of the ADC is decreased
accordingly.
0*
1
2.0 V (p-p)
1.0 V (p-p) (6 dB gain)
6 to 4 CS[2:0]
R/W
The current consumption of the ADC has to be programmed
with these three bits.
000
001
010*
011
100
101
110
111
not allowed
not allowed
not allowed
not allowed
1.00 (value to be programmed differing from default value)
1.25
1.50
not allowed
3
DCIN
R/W
The input signal of the ADC can be either AC coupled by
means of two capacitors or connected directly to the inputs
(DC coupled).
0*
1
AC coupling
DC coupling
2
1
TWOS
SLEEP
R/W
R/W
This parameter controls the output format of the ADC.
offset binary format
0
1*
twos complement format
When HIGH, SLEEP sets the ADC into its Sleep mode. Both
bias current and clock are switched off. In this mode, the
current consumption is reduced by a factor of 6. The
reference circuit will remain active in order to guarantee a fast
recovery from Sleep mode.
0*
1
Normal mode
ADC Sleep mode
0
PD_ADC R/W
When HIGH, PD_ADC sets the ADC into its Power-down
mode. All internal currents are switched off. In this mode, the
current consumption is near zero (leakage current only).
0*
1
Normal mode
ADC Power-down mode
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Table 52. ADC_CTL_2 register (address 34h) bit description
Legend: * = default value.
Bit
Symbol
Access Value Description
7 to 2 -
R/W
AD_PLL_BYP R/W
-
not used
1
0
The clock PLL can be bypassed for the ADC sampling
clock. Then the crystal output is directly taken for ADC
sampling.
0*
1
Normal mode
Bypass mode
AD_SR54M
R/W
AD_SR54M sets the ADC sampling rate
0
ADC sampling rate 27 MHz; first decimation filter is
bypassed
1*
ADC sampling rate 54 MHz
9.3.18 Video and sound DAC control
The TDA8295 implements two 10-bit DAC modules (CVBS and sound outputs) which are
sampled by a 108 MHz clock. A reference module derives biasing currents for the two
DACs.
Table 53. VIDEODAC_CTL register (address 35h) bit description
Legend: * = default value.
Bit
Symbol
Access Value
Description
7
-
R/W
0
reserved, must be set to logic 0
6 to 1 B_DA_V[5:0] R/W
B_DA_V is the coarse output level adjustment
parameters of the video DAC. See Section 13.3.
00 0000
11 1111*
minimum current setting
maximum current setting
0
PD_DA_V
R/W
When HIGH, PD_DA_V sets the video DAC into its
Power-down mode.
0*
1
Normal mode
video DAC Power-down mode
Table 54. AUDIODAC_CTL register (address 36h) bit description
Legend: * = default value.
Bit
Symbol
Access Value
Description
7
-
R/W
0
reserved, must be set to logic 0
6 to 1 B_DA_S[5:0] R/W
B_DA_S is the coarse output level adjustment
parameters of the sound DAC. See Section 13.3.
00 0000*
11 1111
minimum current setting
maximum current setting
0
PD_DA_S
R/W
When HIGH, PD_DA_S sets the sound DAC into its
Power-down mode.
0*
1
Normal mode
sound DAC Power-down mode
TDA8295_C2_2
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Product data sheet
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TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Table 55. DAC_REF_CLK_CTL register (address 37h) bit description
Legend: * = default value.
Bit
7
Symbol
Access Value Description
-
R/W
-
not used
6
DA_CLK_INV R/W
For debugging purposes, the DAC clock polarity can be
inverted.
0
inverted polarity
normal polarity
1*
5
DA_PLL_BYP R/W
If active, the clock PLL for DAC sampling can be
bypassed. Then, the crystal output is directly taken for
DAC sampling.
0*
1
Normal mode
Bypass mode
4 to 1 B_REF[3:0]
R/W
For accuracy, one external resistor connected to
pin RSET and board ground controls the bias current.
Moreover, B_REF permits to adjust this bias current from
−7 % to +7 % (see Section 13.3). Format is signed
binary.
1111
minimum fine current
nominal fine current
maximum fine current
0000*
0111
0
PD_DA_REF R/W
When HIGH, PD_DA_REF sets the reference module
into its Power-down mode.
0*
1
Normal mode
Power-down mode
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Product data sheet
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TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
9.3.19 Clock generation (PLL and crystal oscillator)
The TDA8295 implements a crystal oscillator which can be used either in Slave mode or
in Oscillator mode (see Section 13.7), and a multipurpose PLL which receives XIN as
input clock, and delivers the system clock of the IC (108 MHz).
Table 56. PLL_REG00 register (address 38h) bit description
Legend: * = default value.
Bit
Symbol
Access Value
Description
7 and 6 -
R/W
PLL_AUTO R/W
00
reserved, must be set to logic 00
clock PLL mode control
5
0
The sequencing of the programming and monitoring
of the PLL can be made ‘manually’ through CLK_EN,
BYP_PLL, PD_PLL and LOCK, according to the
following set of instructions:
After a hardware reset:
• Set PLL_AUTO to logic 0
• By default, CLK_EN = BYP_PLL = PD_PLL = 1,
LOCK = 0, the PLL is in Power-down mode, is
not locked, and the output clock is the clock of
the quartz oscillator used to resynchronize reset
signals in the TDA8295
Then:
• Set BYP_PLL and CLK_EN to logic 0
• Set MSEL, NSEL and PSEL that are
corresponding to the frequency required value
• Set PD_PLL to logic 0, in order that the PLL
takes those parameters into account and starts
up
• Then, wait for a minimum time of 500 μs (which
is the maximum time the PLL should take to
lock). This time could be used to make the
programming of the other I2C-bus registers.
• Set CLK_EN to logic 1 to enable the sampling
frequency to the rest of the chip
• Optionally, verify that LOCK = 1
1*
The sequencing of the programming and monitoring
of the PLL is handled automatically by the TDA8295
at initialization and each time one of the M, N, P
parameters is changed. Thus, the user has only to
program M, N, P and then once the PLL is locked, its
output clock becomes enabled automatically.
4 to 0
-
R/W
0 0000
reserved, must be set to logic 0 0000
Table 57. PLL_REG04 register (address 3Ch) bit description
Bit
Symbol
Access Value
Description
7 to 3
2 to 0
-
-
R/W
R/W
-
not used
000
reserved, must be set to logic 000
TDA8295_C2_2
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Product data sheet
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TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Table 58. PLL_REG06 register (address 3Eh) bit description
Legend: * = default value.
Bit
7
Symbol
-
Access Value
Description
R/W
R/W
0
reserved, must be set to logic 0
CLK_EN controls the PLL output clock
PLL output clock disable
PLL output clock enable
don’t care if PLL_AUTO = 1
6
CLK_EN
0
1*
X
5
BYP_PLL
R/W
When HIGH, the internal clocks (for logic, ADC, and
DACs) are directly controlled by the pin XIN.
BYP_PLL acts both on external multiplexers and on
internal PLL bypass. When PLL initialization is
automatic (PLL_AUTO = 1), BYP_PLL is not
considered.
0
internal clocks are controlled by PLL clock
internal clocks are controlled by pin XIN
don’t care if PLL_AUTO = 1
1*
X
4
3
DIRECTO
DIRECTI
R/W
R/W
0*
0*
When DIRECTI is set to logic 1, the pre-divider is
bypassed. If DIRECTO is equal to logic 1, then it is
the post-divider, which is bypassed. Please see
Table 59 for further details.
2 and 1 -
PD_PLL
R/W
R/W
00
reserved, must be set to logic 00
0
Put the PLL in Power-down mode if equal to logic 1.
When PLL initialization is automatic
(PLL_AUTO = 1), PD_PLL is not considered.
0
PLL active
1*
X
PLL Power-down mode
don’t care if PLL_AUTO = 1
Table 59. Truth table for PLL output clock frequency
Legend: * = default value.
DIRECTI
DIRECTO
PLL output clock frequency[1]
1
1
1
0
fclk(o)(PLL) = fVCO = fi × 2 × M
fVCO
------------
2 × P
fi × M
-------------
P
fclk(o)(PLL)
=
=
0
1
fi × 2 × M
-----------------------
N
fclk(o)(PLL) = fVCO
=
0*
0*
fVCO
fi × M
-------------
N × P
fclk(o)(PLL)
=
=
------------
2 × P
[1] For description of M, N and P see Table 60.
For optimum performances, the following relations must be respected:
• 275 MHz ≤ fVCO ≤ 550 MHz
• 4 kHz ≤ fi ≤ 150 MHz if DIRECTI = 1, else 4 kHz ≤ fi / N ≤ 150 MHz
TDA8295_C2_2
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Product data sheet
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49 of 83
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Table 60. PLL_REG07, PLL_REG08, PLL_REG09 and PLL_REG10 register (address 3Fh to 42h) bit description
Legend: * = default value.
Address Register
Bit
Symbol
Access Value Description
3Fh
PLL_REG07 7
-
R/W
R/W
-
not used
6 to 0 -
00h
reserved, must be set to 00h
40h
41h
PLL_REG08 7 to 0 MSEL[7:0] R/W
1Ah* It programs the M parameter (M = MSEL + 1). M is the PLL
feedback-divider.
PLL_REG09 7 to 1 NSEL[6:0] R/W
01h*
It programs the N parameter (N = NSEL + 1). N is the PLL
pre-divider.
0
-
R/W
R/W
0
reserved, must be set to logic 0
reserved, must be set to logic 000
42h
PLL_REG10 7 to 5 -
000
01h*
4 to 0 PSEL[4:0] R/W
It programs the P parameter (P = PSEL + 1). P is the PLL
post-divider.
Table 61. XTALOSC_CTL register (address 43h) bit description
Legend: * = default value.
Bit
7 to 3
2
Symbol Access Value Description
-
R/W
R/W
-
not used
HF
With HF, the transconductance of the oscillator gain stage can be set. For
fXIN > 20 MHz, HF should be set to logic 1.
0*
1
recommended for standard application (16 MHz)
recommended if fXIN > 20 MHz
1 and 0 -
R/W
00
reserved, must be set to logic 00
TDA8295_C2_2
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Product data sheet
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9.3.20 GPIOs
Digital global standard low IF demodulator for analog TV and FM radio
In the TDA8295, three general purpose input/outputs are implemented.
Table 62. GPIOREG_0 register (address 44h) bit description
Legend: * = default value.
Bit
Symbol
Access Value Description
7 to 4 GP1_CF[3:0] R/W
It determines how the general purpose pin GPIO1 is
configured.
0000
0001*
0011
The GPIO1 pin is in Input mode. The input value is
stored in GP1_VAL.
The GPIO1 pin is in Open-drain mode. The output
value is determined by GP1_VAL.
The GPIO1 pin is in Output mode. The PLL output
clock divided by two is delivered.
0100
to
1011
The GPIO1 pin is in Output mode. HVPLL signals are
delivered. The output is a one bit signal of
HVPLL_BUS[7:0] according to Table 64.
XXXX
Don’t care if I2CSW_EN = 1. Then the pad is
configured as I2C-bus feed-through like described in
Table 63.
3 to 0 GP0_CF[3:0] R/W
It determines how the general purpose pin GPIO0 is
configured.
0000
0001*
0011
The GPIO0 pin is in Input mode. The input value is
stored in GP0_VAL.
The GPIO0 pin is in Open-drain mode. The output
value is determined by GP0_VAL.
The GPIO0 pin is in Output mode. The PLL output
clock divided by two is delivered.
0100
to
1011
The GPIO0 pin is in Output mode. HVPLL signals are
delivered. The output is a one bit signal of
HVPLL_BUS[7:0] according to Table 64.
Table 63. GPIOREG_1 register (address 45h) bit description
Legend: * = default value.
Bit
7
Symbol
Access Value Description
I2CSW_EN R/W
I2CSW_ON R/W
0*
0*
When I2CSW_EN = 1, GPIO1 and GPIO2 are
configured as an I2C-bus feed-through independently of
the GP1_CF and GP2_CF value. When
6
I2CSW_ON = 0, the feed-through switch is open, and
GPIO1 and GPIO2 are in 3-state. When the switch is
closed (I2CSW_ON = 1), the I2C-bus clock and data
signals (SCL and SDA) are available on the GPIO1 and
GPIO2 pins.
5 and 4 -
R/W
-
not used
TDA8295_C2_2
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Product data sheet
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TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Table 63. GPIOREG_1 register (address 45h) bit description …continued
Legend: * = default value.
Bit
Symbol
Access Value Description
3 to 0
GP2_CF[3:0] R/W
It determines how the general purpose pin GPIO2 is
configured.
0000
0001*
0011
The GPIO2 pin is in Input mode. The input value is
stored in GP2_VAL.
The GPIO2 pin is in Open-drain mode. The output
value is determined by GP2_VAL.
The GPIO2 pin is in Output mode. The PLL output
clock divided by two is delivered.
0100
to
1011
The GPIO2 pin is in Output mode. HVPLL signals are
delivered. The output is a one bit signal of
HVPLL_BUS[7:0] according to Table 64.
XXXX
Don’t care if I2CSW_EN = 1. Then the pad is
configured as I2C-bus feed-through.
Table 64. HVPLL bus mapping
HVPLL_BUS bit
HVPLL_BUS[7]
Signal
V_SYNC
H_SYNC
NOISE_DET
MAC_DET
FIDT
HVPLL_BUS[6]
HVPLL_BUS[5]
HVPLL_BUS[4]
HVPLL_BUS[3]
HVPLL_BUS[2]
V_LOCK
F_H_LOCK
N_H_LOCK
HVPLL_BUS[1]
HVPLL_BUS[0]
Table 65. GPIOREG_2 register (address 46h) bit description
Legend: * = default value.
Bit
7
Symbol
Access Value Description
CLK_INV_GP2 R/W
CLK_INV_GP1 R/W
CLK_INV_GP0 R/W
0*
0*
0*
-
With CLK_INV_GPx, the output clock polarity can be
changed. This is only useful when
GPx_CF[3:0] = 0011.
6
5
4 and 3 -
R/W
R/W
not used
2
1
0
GP2_VAL
1*
GP2_VAL controls the value of the pin GPIO2 when
GP2_CF[3:0] = 0001. When GP2_CF[3:0] = 0000,
GPIO2 is an input pin which value can be read
through the I2C-bus stored in GP2_VAL.
GP1_VAL
GP0_VAL
R/W
R/W
1*
1*
GP1_VAL controls the value of the pin GPIO1 when
GP1_CF[3:0] = 0001. When GP1_CF[3:0] = 0000,
GPIO1 is an input pin which value can be read
through the I2C-bus stored in GP1_VAL.
GP0_VAL controls the value of the pin GPIO0 when
GP0_CF[3:0] = 0001. When GP0_CF[3:0] = 0000,
GPIO0 is an input pin which value can be read
through the I2C-bus stored in GP0_VAL.
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9.3.21 Special equalizer functions for group delay and video (CVBS)
To realize special customer demands or accurate compensation of the tuner influence, the TDA8295 has got freely
programmable equalizers for the group delay and video (CVBS) response.
In Table 66 the programming of the group delay equalizer is explained, in Table 68 the programming of the video equalizer.
For each equalizer type an example is given.
Table 66. GD_EQ_SECTx_C1 and GD_EQ_SECTx_C2 (x = 1 to 4) register (address 4Bh to 52h) bit description
Legend: * = default value[1].
Address Register
Bit
Symbol
Access Value Description
4Bh
4Ch
4Dh
4Eh
4Fh
50h
51h
52h
GD_EQ_SECT1_C1 7 to 0 GD_EQ_SECT1_C1[7:0] R/W
GD_EQ_SECT1_C2 7 to 0 GD_EQ_SECT1_C2[7:0] R/W
GD_EQ_SECT2_C1 7 to 0 GD_EQ_SECT2_C1[7:0] R/W
GD_EQ_SECT2_C2 7 to 0 GD_EQ_SECT2_C2[7:0] R/W
GD_EQ_SECT3_C1 7 to 0 GD_EQ_SECT3_C1[7:0] R/W
GD_EQ_SECT3_C2 7 to 0 GD_EQ_SECT3_C2[7:0] R/W
GD_EQ_SECT4_C1 7 to 0 GD_EQ_SECT4_C1[7:0] R/W
GD_EQ_SECT4_C2 7 to 0 GD_EQ_SECT4_C2[7:0] R/W
00h*
00h*
00h*
00h*
00h*
00h*
00h*
00h*
The group delay equalizer consists of four cascaded all-pass Infinite Impulse
Response (IIR) sections of second order (8th order in sum). The transfer
function H(z) of one section is as follows, while the sampling rate is
b2 + b1 × z–1 + z–2
1 + b1 × z–1 + b2 × z–2
13.5 MHz: H(z) =
-----------------------------------------------------
GD_EQ_SECTx_C1 and GD_EQ_SECTx_C2 (x = 1 to 4) are defining the
linear and square coefficient of each section, i.e. GD_EQ_SECTx_C1 = b1
and GD_EQ_SECTx_C2 = b2. The coefficients are in signed fixed-point
format, the representation is in two’s complement. There is one sign bit, one
magnitude bit and 6 fractional bits. Each fractional bit represents an inverse
power of two, so that the highest value for a coefficient is
20 + 2−1 + ... + 2−6 = 21 − 2−6 = 1.984375. The binary representation for this
value is 01.11 1111 (= 7Fh) and all bits except the sign bit are logic 1. As
two’s complement is chosen, the lowest value for a coefficient is −2, which is
10.00 0000 (= 80h) in the binary representation. So, for the lowest possible
value, only the sign bit is logic 1. The shown default values for
GD_EQ_SECTx_C1 and GD_EQ_SECTx_C2 (x = 1 to 4) implement a flat
equalizer response.
[1] Don’t care if GD_EQ_CTRL = 0; see Table 25.
Example of Table 66: If e.g. a flat group delay response up to 4 MHz and −70 ns from 4.43 MHz to 5 MHz on the CVBS
signal is wanted, one might realize a characteristic like shown in Figure 12.
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
001aaj779
0.65
t
d(grp)
(μs)
0.62
0.59
0.56
0.53
0
1
2
3
4
5
f (MHz)
Fig 12. Example for the programmable group delay equalizer
The coefficients used in the above filter are according to Table 67. To get any other filter
characteristic use a professional filter tool to determine the coefficients.
Table 67. Coefficients used in group delay equalizer example
Symbol
Value
B9h
16h
GD_EQ_SECT1_C1[7:0]
GD_EQ_SECT1_C2[7:0]
GD_EQ_SECT2_C1[7:0]
GD_EQ_SECT2_C2[7:0]
GD_EQ_SECT3_C1[7:0]
GD_EQ_SECT3_C2[7:0]
GD_EQ_SECT4_C1[7:0]
GD_EQ_SECT4_C2[7:0]
DBh
17h
0Eh
19h
47h
1Ch
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Product data sheet
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Table 68. CVBS_EQ_COEFx_LOW and CVBS_EQ_COEFx_HIGH (x = 0 to 5) register (address 57h to 62h) bit description
Legend: * = default value[1].
Address Register
Bit
CVBS_EQ_COEF0_LOW 7 to 0 CVBS_EQ_COEF0[7:0] R/W
CVBS_EQ_COEF0_HIGH 7 to 4 - R/W
Symbol
Access Value Description
57h
58h
00h*
-
The overall video (CVBS) equalizer is a symmetric FIR filter with
11 taps. Due to the symmetry the group delay is constant (linear
phase). The transfer function is as follows, while the sampling rate is
13.5 MHz:
3 to 0 CVBS_EQ_COEF0[11:8] R/W
0h*
00h*
-
59h
5Ah
CVBS_EQ_COEF1_LOW 7 to 0 CVBS_EQ_COEF1[7:0] R/W
H(z) = h0 + h1 × z–1 + h2 × z–2 + h3 × z–3 + h4 × z–4 + ... + h10 × z–10
CVBS_EQ_COEF1_HIGH 7 to 4 -
R/W
Please note that because of the symmetry h0 = h10, h1 = h9, h2 = h8,
h3 = h7 and h4 = h6. The mid coefficient h5 is only present once.
CVBS_EQ_COEFx (x = 0 to 5) are defining the coefficients, i.e.
CVBS_EQ_COEF0 = h0 = h10, CVBS_EQ_COEF1 = h1 = h9,
CVBS_EQ_COEF2 = h2 = h8, CVBS_EQ_COEF3 = h3 = h7,
CVBS_EQ_COEF4 = h4 = h6 CVBS_EQ_COEF5 = h5. Each of the
coefficients h0 to h5 has got 12-bit quantization. The coefficients are in
signed fixed-point format, the representation is in two’s complement.
There is one sign bit, one magnitude bit and 10 fractional bits. Each
fractional bit represents an inverse power of two, so that the highest
3 to 0 CVBS_EQ_COEF1[11:8] R/W
0h*
00h*
-
5Bh
5Ch
CVBS_EQ_COEF2_LOW 7 to 0 CVBS_EQ_COEF2[7:0] R/W
CVBS_EQ_COEF2_HIGH 7 to 4 -
R/W
3 to 0 CVBS_EQ_COEF2[11:8] R/W
0h*
00h*
-
5Dh
5Eh
CVBS_EQ_COEF3_LOW 7 to 0 CVBS_EQ_COEF3[7:0] R/W
CVBS_EQ_COEF3_HIGH 7 to 4 -
R/W
3 to 0 CVBS_EQ_COEF3[11:8] R/W
0h*
00h*
-
5Fh
60h
CVBS_EQ_COEF4_LOW 7 to 0 CVBS_EQ_COEF4[7:0] R/W
CVBS_EQ_COEF4_HIGH 7 to 4 -
R/W
value for a coefficient is 20 + 2−1 + ... + 2−10 = 21 − 2−10
=
3 to 0 CVBS_EQ_COEF4[11:8] R/W
0h*
00h*
-
1.9990234375. The binary representation for this value is
01.11 1111 1111 (= 7FFh) and all bits except the sign bit are logic 1. As
two’s complement is chosen, the lowest value for a coefficient is −2,
which is 10.00 0000 0000 (= 800h) in the binary representation. So, for
the lowest possible value, only the sign bit is logic 1. The shown
default values for CVBS_EQ_COEFx (x = 0 to 5) implement a flat
equalizer response.
61h
62h
CVBS_EQ_COEF5_LOW 7 to 0 CVBS_EQ_COEF5[7:0] R/W
CVBS_EQ_COEF5_HIGH 7 to 4 -
R/W
3 to 0 CVBS_EQ_COEF5[11:8] R/W
4h*
[1] Don’t care if CVBS_EQ_CTRL = 0; see Table 36.
Example of Table 68: If an attenuation of around 1 dB for video frequencies greater than 2 MHz is wanted, the following
figure (see Figure 13) can be implemented.
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
001aaj780
0
α
resp(f)
(dB)
−0.4
−0.8
−1.2
−1.6
−2.0
0
1
2
3
4
5
6
7
f (MHz)
Fig 13. Example for the programmable video equalizer
Table 69. Coefficients used in video equalizer example
Symbol
Value
005h
FFDh
016h
FFFh
018h
39Ch
CVBS_EQ_COEF0[11:0]
CVBS_EQ_COEF1[11:0]
CVBS_EQ_COEF2[11:0]
CVBS_EQ_COEF3[11:0]
CVBS_EQ_COEF4[11:0]
CVBS_EQ_COEF5[11:0]
TDA8295_C2_2
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Product data sheet
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56 of 83
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
10. Limiting values
Table 70. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1][2]
Symbol
Parameter
Conditions
Min
−0.5
−0.5
−0.5
−0.5
−0.5
−0.5
−0.5
-
Max
+1.7
+4.6
+1.7
+1.7
+1.7
+5.1
+1.7
300
Unit
V
VDDDC(1V2)
core digital supply voltage (1.2 V)
VDDA(ADC)(3V3) ADC analog supply voltage (3.3 V)
VDDA(PLL)(1V2) PLL analog supply voltage (1.2 V)
VDDA(OSC)(1V2) oscillator analog supply voltage (1.2 V)
V
V
V
Vi
input voltage
pins IF_POS and IF_NEG
digital input pins (5 V tolerant)
pin XIN
V
V
V
Tlead
Ptot
Tstg
Tj
lead temperature
°C
W
°C
°C
°C
V
total power dissipation
storage temperature
junction temperature
ambient temperature
electrostatic discharge voltage
Tamb = 70 °C
-
0.5
−40
-
+125
125
Tamb
Vesd
−20
-
+85
[3]
[4]
pins SDA, SCL, SADDR0 and
SADDR1; machine model
±150
all other pins; machine model
-
±200
V
[1] Stresses above the absolute maximum ratings may cause permanent damage to the device. Exposure to absolute maximum ratings
conditions for extended periods may affect device reliability.
[2] The maximum allowed ambient temperature Tamb depends on the assembly condition of the package and especially on the design of
the PCB. The application mounting must be done in such a way that the maximum junction temperature Tj(max) is never exceeded.
[3] Class A according to EIA/JESD22-A115.
[4] Class B according to EIA/JESD22-A115.
11. Thermal characteristics
Table 71. Thermal characteristics
Symbol
Parameter
Conditions
Typ
Unit
Rth(j-a)
thermal resistance from junction to
ambient
in still air
33
K/W
The thermal resistance depends strongly on the nature of the PCB used in the application
and on its design. The thermal resistance given in Table 71 corresponds to the value that
can be measured on a multilayer PCB (4 layers) as defined by EIA/JESD51-2. This value
is given for information only.
The junction temperature influences strongly the reliability of an IC. The PCB used in the
application contributes on a large part to the overall thermal characteristic. It must
therefore be designed to insure that the junction temperature of the IC never exceeds
T
j(max) = 125 °C at the maximum ambient temperature.
The IC has to be soldered to ground with its die-attached paddle. Plenty of vias are
recommended to remove the heat.
TDA8295_C2_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 27 November 2009
57 of 83
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
12. Characteristics
Table 72. Characteristics
Power supplies 3.3 V, 1.2 V; Tamb = 25 °C; PC / SC1 for L and M = 10 dB, all others 13 dB; residual picture carrier for L = 3 %,
all others 10 %; FM/AM modulation = 54 %, 1 kHz modulation frequency; measured in application PCB (see Figure 15) with
16 MHz crystal frequency, loaded with 75 Ω (CVBS) and 1 kΩ (SSIF/audio). Values are meant for ‘easy programming’
settings (recommended) except internal mono audio and IF demodulation. The low IF spectrum is delivered by a professional
downconverter.
Symbol
Parameter
Conditions
Min
Typ
Max Unit
Power supply
VDD(1V2)
supply voltage (1.2 V)
supply voltage (3.3 V)
total supply current (1.2 V)
total supply current (3.3 V)
total power dissipation
digital and analog
digital and analog
1.08
1.2
3.3
28
1.32
3.63
33
V
VDD(3V3)
2.97
V
IDD(tot)(1V2)
IDD(tot)(3V3)
Ptot
-
-
-
mA
[1]
[1]
168
575
179 mA
631 mW
default settings; 75 Ω drive;
fs = 54 MHz at ADC; including
DAC loads; RRSET = 1 kΩ
[2]
Power-save mode;
-
465
510 mW
fs = 54 MHz at ADC; including
DAC loads; RRSET = 2 kΩ;
see Section 13.6
Standby mode
-
7
-
10
mW
V
Digital I/Os
VIH
HIGH-level input voltage
LOW-level input voltage
all inputs (except pin XIN);
including voltage on outputs in
3-state mode
0.7 × VDD(3V3)
6.0
VIL
all inputs (except pin XIN);
including voltage on outputs in
3-state mode
-
-
0.8
V
VOH
HIGH-level output voltage
LOW-level output voltage
input capacitance
source current 4 mA
sink current 4 mA
VDD(3V3) − 0.4 -
-
V
VOL
-
-
-
-
0.4
5
V
Ci
pF
Master clock
fclk(o)(PLL)
Δf/fclk
[3]
PLL output clock frequency
-
-
108
-
-
MHz
relative frequency deviation
from clock frequency
±200 10−6
Reference frequency in Slave mode
fclk(ext)
Vi(RMS)
SRr
external clock frequency
RMS input voltage
rising slew rate
-
16
250
-
-
-
-
-
-
MHz
mV
AC coupled
external clock
RMS value
on pin XIN
200
30
-
mV/ns
ps
tjit(cc)
Ci
cycle-to-cycle jitter time
input capacitance
12.5
3
-
pF
Reference frequency in Oscillator mode (with a crystal)
fxtal
crystal frequency
-
-
16
-
-
MHz
Δfxtal/fxtal
relative crystal frequency
variation
temperature, ageing and
spreading
±200 10−6
Tamb(xtal)
crystal ambient temperature
−20
-
+85 °C
TDA8295_C2_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 27 November 2009
58 of 83
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Table 72. Characteristics …continued
Power supplies 3.3 V, 1.2 V; Tamb = 25 °C; PC / SC1 for L and M = 10 dB, all others 13 dB; residual picture carrier for L = 3 %,
all others 10 %; FM/AM modulation = 54 %, 1 kHz modulation frequency; measured in application PCB (see Figure 15) with
16 MHz crystal frequency, loaded with 75 Ω (CVBS) and 1 kΩ (SSIF/audio). Values are meant for ‘easy programming’
settings (recommended) except internal mono audio and IF demodulation. The low IF spectrum is delivered by a professional
downconverter.
Symbol
IF input
Vi(p-p)
Parameter
Conditions
Min
Typ
Max Unit
peak-to-peak input voltage
for full-scale ADC input
(0 dBFS)
1.8
2.0
2.2
V
Ri(dif)
Ci(dif)
Vi
differential input resistance
differential input capacitance
input voltage
10
-
15
2
-
kΩ
3
pF
operational input related to
ADC full scale; all standards;
sum of all signals
−3
−3
−3
dBFS
fi
input frequency
PC / SC1
M/N standard
B standard
-
-
-
-
-
-
-
5.75 / 1.25 -
6.75 / 1.25 -
7.75 / 2.25 -
7.75 / 1.75 -
7.75 / 1.25 -
1.25 / 7.75 -
MHz
MHz
MHz
MHz
MHz
MHz
MHz
G/H standard
I standard
DK and L standard
L-accent standard
FM radio
1.25
-
IF selectivity
αsup(stpb)
stop-band suppression
Hilbert filter stop-band
−60
−40
−40
-
-
-
-
-
-
dB
dB
dB
decimation filter stop-band
[4]
notch for NSC (NPC for
L-accent standard)
Carrier recovery FPLL
B−3dB(cl)
closed-loop −3 dB
bandwidth
ultrawide
superwide
wide
280
130
60
280
130
60
280 kHz
130 kHz
60
30
15
-
kHz
kHz
kHz
kHz
%
medium
narrow
30
30
15
15
[5]
[5]
Δfpullin
pull-in frequency range
see Figure 11
-
±830
117
mover(PC)
picture carrier
overmodulation index
black for L/L-accent standard;
flat field white else
115
-
fstep(AFC)
AFC step frequency
128 steps
13
-
-
kHz
IF demodulation (video equalizer in Flat mode)
BT(tot)
total transition bandwidth
stop-band suppression
Nyquist filter; all standards
Nyquist filter; all standards
1
1
1
-
MHz
dB
αsup(stpb)
−60
-
video low-pass filter (M/N,
B/G/H, I, D/K, L/L-accent
standard)
-
−60
-
dB
TDA8295_C2_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 27 November 2009
59 of 83
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Table 72. Characteristics …continued
Power supplies 3.3 V, 1.2 V; Tamb = 25 °C; PC / SC1 for L and M = 10 dB, all others 13 dB; residual picture carrier for L = 3 %,
all others 10 %; FM/AM modulation = 54 %, 1 kHz modulation frequency; measured in application PCB (see Figure 15) with
16 MHz crystal frequency, loaded with 75 Ω (CVBS) and 1 kΩ (SSIF/audio). Values are meant for ‘easy programming’
settings (recommended) except internal mono audio and IF demodulation. The low IF spectrum is delivered by a professional
downconverter.
Symbol
Parameter
Conditions
Min
Typ
3.9
4.9
Max Unit
Bvideo(−1dB)
−1 dB video bandwidth
M/N standard
-
-
-
-
MHz
MHz
B/G/H, I, D/K, L/L-accent
standard
tripple(GDE)
group delay equalizer ripple peak value for B/G/H half,
-
20
40
ns
time
D/K half, I flat, M (FCC) full,
L/L-accent full standard
Digital IF AGC (internal loop)
[6]
B−3dB(cl)
closed-loop −3 dB
bandwidth
negative modulation (all
standards except L/L-accent)
400
0.2
-
-
-
-
Hz
Hz
positive modulation
(L/L-accent standard)
tresp
response time
±20 dB level change; video
settled within ±3 dB
negative modulation (all
standards except
L/L-accent)
3
3
3
ms
positive modulation
(L/L-accent standard)
100
100
-
100 ms
+48 dB
ΔGAGC
AGC gain range
−20
Tuner IF AGC (external loop)
[7]
tresp
response time
at 60 dBμV (RMS) PC input;
±20 dB level change; video
settled within ±3 dB
with TDA8275A;
positive modulation
-
4000
500
-
ms
ms
ms
ms
kHz
with TDA8275A;
negative modulation
-
-
with TDA1827x;
positive modulation
-
3000
600
-
with TDA1827x;
negative modulation
-
-
f−3dB(lpf)
low-pass filter −3 dB
IF AGC postfilter
0.9
1.0
1.1
frequency
TDA8295_C2_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 27 November 2009
60 of 83
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Table 72. Characteristics …continued
Power supplies 3.3 V, 1.2 V; Tamb = 25 °C; PC / SC1 for L and M = 10 dB, all others 13 dB; residual picture carrier for L = 3 %,
all others 10 %; FM/AM modulation = 54 %, 1 kHz modulation frequency; measured in application PCB (see Figure 15) with
16 MHz crystal frequency, loaded with 75 Ω (CVBS) and 1 kΩ (SSIF/audio). Values are meant for ‘easy programming’
settings (recommended) except internal mono audio and IF demodulation. The low IF spectrum is delivered by a professional
downconverter.
Symbol
Parameter
Conditions
Min
Typ
Max Unit
CVBS output
Vo(p-p)
peak-to-peak output voltage negative PC modulation (all
standards except L/L-accent);
75 Ω DC load; sync-white
modulation
65 %
-
0.7
1.0
1.0
0.9
1.2
1.2
V
V
V
90 % (nominal)
115 %
0.8
-
positive PC modulation
(L/L-accent standard);
75 Ω DC load; sync-white
modulation
65 %
-
0.7
1.0
1.0
1.5
0.9
1.2
1.2
1.8
V
V
V
V
97 % (nominal)
115 %
0.8
-
band limited white noise
0 Hz to 6 MHz; 1 V RMS;
VID_LVL = 0
1.2
Bvideo(−3dB)
−3 dB video bandwidth
overall video response; CVBS
equalizer flat
all standards except M/N
M/N standard
4.8
3.9
−5
4.85
4.05
-
-
-
MHz
MHz
αresp(f)
frequency response
video equalizer; 8 equally
spaced settings; value at
3.9 MHz
+4.5 dB
Gdif
differential gain
“ITU-T J.63 line 330”
“ITU-T J.63 line 330”
-
-
-
1.5
1.5
1
3
3
2
%
ϕdif
differential phase
deg
%
Vstlt/VCVBS(p-p) synchronization tilt voltage
to peak-to-peak CVBS
voltage ratio
Vftlt/VCVBS(p-p) frame tilt voltage to
all standards except
-
-
-
1
1
2
3
5
5
%
%
%
peak-to-peak CVBS voltage L/L-accent
ratio
L/L-accent standard in peak
white AGC detection
[8]
ΔVtro/Vtro
relative transient response
overshoot voltage variation
2T pulse
TDA8295_C2_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 27 November 2009
61 of 83
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Table 72. Characteristics …continued
Power supplies 3.3 V, 1.2 V; Tamb = 25 °C; PC / SC1 for L and M = 10 dB, all others 13 dB; residual picture carrier for L = 3 %,
all others 10 %; FM/AM modulation = 54 %, 1 kHz modulation frequency; measured in application PCB (see Figure 15) with
16 MHz crystal frequency, loaded with 75 Ω (CVBS) and 1 kΩ (SSIF/audio). Values are meant for ‘easy programming’
settings (recommended) except internal mono audio and IF demodulation. The low IF spectrum is delivered by a professional
downconverter.
Symbol
Parameter
Conditions
Min
Typ
Max Unit
αIM(blue)
intermodulation suppression carrier levels related to PC
(blue)
sync; PC = −3.2 dB;
CC = −19.2 dB; SC = −13 dB
1.1 MHz (related to
black-to-white in RMS,
equals CC + 3.6 dB)
-
-
64
75
-
-
dB
dB
3.3 MHz (related to CC)
αIM(yellow)
intermodulation suppression carrier levels related to PC
(yellow)
sync; PC = −10 dB;
CC = −19.2 dB; SC = −13 dB
1.1 MHz (related to
black-to-white in RMS,
equals CC + 3.6 dB)
-
69
-
dB
3.3 MHz (related to CC)
-
81
62
-
-
dB
dB
(S/N)w
weighted signal-to-noise
ratio
all standards; unified
weighting filter (“ITU-T J.61”);
PC at −6 dBFS
58
TDA8295_C2_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 27 November 2009
62 of 83
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Table 72. Characteristics …continued
Power supplies 3.3 V, 1.2 V; Tamb = 25 °C; PC / SC1 for L and M = 10 dB, all others 13 dB; residual picture carrier for L = 3 %,
all others 10 %; FM/AM modulation = 54 %, 1 kHz modulation frequency; measured in application PCB (see Figure 15) with
16 MHz crystal frequency, loaded with 75 Ω (CVBS) and 1 kΩ (SSIF/audio). Values are meant for ‘easy programming’
settings (recommended) except internal mono audio and IF demodulation. The low IF spectrum is delivered by a professional
downconverter.
Symbol
Parameter
Conditions
Min
Typ
Max Unit
PSRR
power supply rejection ratio fripple = 70 Hz; 100 mV (p-p);
video signal: gray; level: 50 %;
TDA8295 stand alone; input
level: 60 dBμV (RMS) PC
positive video modulation;
L standard; 1.2 V
-
-
-
-
52
30
51
30
-
-
-
-
dB
dB
dB
dB
[9]
[9]
positive video modulation;
L standard; 3.3 V
negative video modulation;
B standard; 1.2 V
negative video modulation;
B standard; 3.3 V
fripple = 70 Hz; 100 mV (p-p);
video signal: gray; level: 50 %;
together with TDA8275A;
input level: 60 dBμV (RMS)
PC
positive video modulation;
L standard; 1.2 V
-
-
-
-
26
22
43
32
-
-
-
-
dB
dB
dB
dB
[9]
[9]
positive video modulation;
L standard; 3.3 V
negative video modulation;
B standard; 1.2 V
negative video modulation;
B standard; 3.3 V
fripple = 70 Hz; 100 mV (p-p);
video signal: gray; level: 50 %;
together with TDA1827x; input
level: 60 dBμV (RMS) PC
positive video modulation;
L standard; 1.2 V
-
-
-
-
-
26
22
43
32
56
-
-
-
-
-
dB
dB
dB
dB
dB
[9]
[9]
positive video modulation;
L standard; 3.3 V
negative video modulation;
B standard; 1.2 V
negative video modulation;
B standard; 3.3 V
αsup(f)L(unw)
unwanted leakage
frequency suppression
4.8 MHz video modulation;
related to black-to-white in
10 MHz to 200 MHz band
TDA8295_C2_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 27 November 2009
63 of 83
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Table 72. Characteristics …continued
Power supplies 3.3 V, 1.2 V; Tamb = 25 °C; PC / SC1 for L and M = 10 dB, all others 13 dB; residual picture carrier for L = 3 %,
all others 10 %; FM/AM modulation = 54 %, 1 kHz modulation frequency; measured in application PCB (see Figure 15) with
16 MHz crystal frequency, loaded with 75 Ω (CVBS) and 1 kΩ (SSIF/audio). Values are meant for ‘easy programming’
settings (recommended) except internal mono audio and IF demodulation. The low IF spectrum is delivered by a professional
downconverter.
Symbol
Parameter
Conditions
Min
Typ
Max Unit
SSIF/mono sound output
[10]
fo(SSIF)
SSIF output frequency
SC1 or FM radio carrier
M standard
-
-
-
-
-
4.5
5.5
6.0
6.5
5.5
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
B/G/H standard
I standard
D/K/L/L-accent standard
FM radio
Vo(SSIF)(RMS) RMS SSIF output voltage
1 kΩ DC or AC load;
no modulation;
PC / SC1 = 13 dB; scaled
linearly for all other ratios
all standards except B/G/H
B/G/H standard
30
35
40
37
mV
mV
27
32
FM radio (single carrier)
1 kΩ DC or AC load
460
530
610 mV
Vo(AF)(RMS)
RMS AF output voltage
M standard; 54 %
modulation degree
(±13.5 kHz FM deviation
before pre-emphasis)
125
125
143
143
165 mV
B, G/H, I, D, K standard;
54 % modulation degree
(±27 kHz FM deviation
before pre-emphasis)
165 mV
145 mV
L/L-accent standard; AM;
m = 54 %
110
56
126
65
FM radio; 30 % modulation
degree (±22.5 kHz FM
deviation before
75
mV
pre-emphasis)
high Deviation mode
487
560
644 mV
(D/K standard China);
FM deviation before
pre-emphasis ±400 kHz;
sound level setting: −12 dB
TDA8295_C2_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 27 November 2009
64 of 83
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Table 72. Characteristics …continued
Power supplies 3.3 V, 1.2 V; Tamb = 25 °C; PC / SC1 for L and M = 10 dB, all others 13 dB; residual picture carrier for L = 3 %,
all others 10 %; FM/AM modulation = 54 %, 1 kHz modulation frequency; measured in application PCB (see Figure 15) with
16 MHz crystal frequency, loaded with 75 Ω (CVBS) and 1 kΩ (SSIF/audio). Values are meant for ‘easy programming’
settings (recommended) except internal mono audio and IF demodulation. The low IF spectrum is delivered by a professional
downconverter.
Symbol
Parameter
Conditions
Min
Typ
Max Unit
αhr(AF)
AF headroom
before clipping; 1 kΩ DC or
AC load
M standard; related to
±25 kHz peak deviation
before pre-emphasis
7
7
7
7
7
7
dB
dB
B, G/H, I, D, K standard;
related to ±50 kHz peak
deviation before
pre-emphasis
L/L-accent standard;
PC / SC1 ratio for start of
audio output clipping; AM;
m = 100 %; related to mean
SC1
1
7
1
7
1
7
dB
dB
FM radio; 30 % modulation
degree related to ±22.5 kHz
peak deviation before
pre-emphasis
τdeemp
de-emphasis time constant M/N standard (mono);
FM radio USA
75
50
75
50
75
50
μs
μs
B/G/H, I, D/K standard;
FM radio Europe
B−3dB
THD
−3 dB bandwidth
audio low-pass filter
L/L-accent standard
M-BTSC standard
30
140
-
30
30
kHz
140
0.1
140 kHz
total harmonic distortion
FM; for 50 kHz deviation
before pre-emphasis (25 kHz
for M standard)
0.2
%
AM; m = 80 %
-
0.6
27
50
46
1
-
%
BAF(−3dB)
−3 dB AF bandwidth
AM
FM
20
40
40
kHz
kHz
dB
-
αAM
AM suppression
of FM demodulator;
AM: f = 1 kHz; m = 54 %
referenced to 27 kHz FM
deviation
-
TDA8295_C2_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 27 November 2009
65 of 83
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Table 72. Characteristics …continued
Power supplies 3.3 V, 1.2 V; Tamb = 25 °C; PC / SC1 for L and M = 10 dB, all others 13 dB; residual picture carrier for L = 3 %,
all others 10 %; FM/AM modulation = 54 %, 1 kHz modulation frequency; measured in application PCB (see Figure 15) with
16 MHz crystal frequency, loaded with 75 Ω (CVBS) and 1 kΩ (SSIF/audio). Values are meant for ‘easy programming’
settings (recommended) except internal mono audio and IF demodulation. The low IF spectrum is delivered by a professional
downconverter.
Symbol
Parameter
Conditions
Min
Typ
Max Unit
(S/N)w(AF)
AF weighted signal-to-noise via internal mono sound
ratio
demodulator;
“ITU-R BS.468-4”; FM mode
related to 27 kHz deviation
before pre-emphasis; 10 %
residual PC; SC1
black picture
54
53
52
52
58
57
56
56
-
-
-
-
dB
dB
dB
dB
flat field white picture
6 kHz sine wave picture
250 kHz square wave
picture
crosshatch picture
color bar picture
52
54
56
58
-
-
dB
dB
via internal mono sound
demodulator;
“ITU-R BS.468-4”; AM;
m = 54 %; 3 % residual PC;
SC1
black picture
43
43
43
47
45
46
46
51
-
-
-
-
dB
dB
dB
dB
flat field white picture
color bar picture
via internal mono sound
demodulator;
“ITU-R BS.468-4”;
FM Radio mode
TDA8295_C2_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 27 November 2009
66 of 83
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Table 72. Characteristics …continued
Power supplies 3.3 V, 1.2 V; Tamb = 25 °C; PC / SC1 for L and M = 10 dB, all others 13 dB; residual picture carrier for L = 3 %,
all others 10 %; FM/AM modulation = 54 %, 1 kHz modulation frequency; measured in application PCB (see Figure 15) with
16 MHz crystal frequency, loaded with 75 Ω (CVBS) and 1 kΩ (SSIF/audio). Values are meant for ‘easy programming’
settings (recommended) except internal mono audio and IF demodulation. The low IF spectrum is delivered by a professional
downconverter.
Symbol
Parameter
Conditions
Min
Typ
Max Unit
(S/N)w(SC1)
first sound carrier weighted via external SSIF sound
signal-to-noise ratio
demodulator in Dual mode;
“ITU-R BS.468-4”; FM mode
related to 27 kHz deviation
before pre-emphasis; 10 %
residual PC
black picture
60
60
54
55
64
64
58
59
-
-
-
-
dB
dB
dB
dB
flat field white picture
6 kHz sine wave picture
250 kHz square wave
picture
crosshatch picture
color bar picture
54
59
58
63
-
-
dB
dB
via SSIF sound demodulator;
“ITU-R BS.468-4”; AM;
m = 54 %; 3 % residual PC
black picture
40
40
40
43
43
43
-
-
-
dB
dB
dB
flat field white picture
color bar picture
(S/N)w(SC2)
second sound carrier
weighted signal-to-noise
ratio
via external SSIF sound
demodulator in Dual mode;
“ITU-R BS.468-4”; FM mode
related to 27 kHz deviation
before pre-emphasis; 10 %
residual PC
black picture
58
58
54
46
62
62
58
50
-
-
-
-
dB
dB
dB
dB
flat field white picture
6 kHz sine wave picture
250 kHz square wave
picture
crosshatch picture
color bar picture
56
57
60
60
61
64
-
-
-
dB
dB
dB
(S/N)w
weighted signal-to-noise
ratio
FM radio; via SSIF sound
demodulator in Mono mode;
“ITU-R BS.468-4”
TDA8295_C2_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 27 November 2009
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TDA8295
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Digital global standard low IF demodulator for analog TV and FM radio
Table 72. Characteristics …continued
Power supplies 3.3 V, 1.2 V; Tamb = 25 °C; PC / SC1 for L and M = 10 dB, all others 13 dB; residual picture carrier for L = 3 %,
all others 10 %; FM/AM modulation = 54 %, 1 kHz modulation frequency; measured in application PCB (see Figure 15) with
16 MHz crystal frequency, loaded with 75 Ω (CVBS) and 1 kΩ (SSIF/audio). Values are meant for ‘easy programming’
settings (recommended) except internal mono audio and IF demodulation. The low IF spectrum is delivered by a professional
downconverter.
Symbol
Parameter
Conditions
Min
Typ
Max Unit
PSRR
power supply rejection ratio fripple = 70 Hz; 100 mV (p-p);
video signal: gray; level: 50 %;
TDA8295 stand alone
FM sound; 1.2 V
FM sound; 3.3 V
AM sound; 1.2 V
AM sound; 3.3 V
-
-
-
-
72
33
68
37
-
-
-
-
dB
dB
dB
dB
[9]
[9]
fripple = 70 Hz; 100 mV (p-p);
video signal: gray; level: 50 %;
together with TDA8275A;
input level: 60 dBμV (RMS)
PC
FM sound; 1.2 V
FM sound; 3.3 V
AM sound; 1.2 V
AM sound; 3.3 V
-
-
-
-
72
33
22
22
-
-
-
-
dB
dB
dB
dB
[9]
[9]
fripple = 70 Hz; 100 mV (p-p);
video signal: gray; level: 50 %;
together with TDA1827x; input
level: 60 dBμV (RMS) PC
FM sound; 1.2 V
FM sound; 3.3 V
AM sound; 1.2 V
AM sound; 3.3 V
-
-
-
-
-
72
33
22
22
33
-
-
-
-
-
dB
dB
dB
dB
dB
[9]
[9]
αsup(f)L(unw)
unwanted leakage
related to SSIF (SC1) in
10 MHz to 200 MHz band
frequency suppression
[1] 100 % ADC current; 100 % video DAC current; 50 % sound DAC current.
[2] 100 % ADC current; 50 % video DAC current; 25 % sound DAC current.
[3] See Section 9.3.19 for PLL setting.
[4] Standard dependent located at 7.25 MHz, 8.25 MHz, 9.25 MHz, 9.75 MHz and 10.25 MHz.
[5] The pull-in range can be doubled to ±1660 kHz by I2C-bus register like described in Table 16. Then the AFC read-out has 256 steps.
[6] To counteract a fast IF level reduction, the digital IF AGC loop has a speed-up circuit for positive video modulation.
[7] In the ordinary system application, this slow response is counteracted by the fast digital IF AGC loop. ADC clipping is practically avoided
by fast-attack AGC characteristic.
[8] HAD: 250 ns for M standard, 200 ns for others.
[9] The values given are measured with an IF AGC time constant of 5 Hz. For that, capacitor C7 in Figure 15 must be chosen 220 nF
instead of 2.2 nF. Doing so, the PSRR on 3.3 V together with the tuner can be improved.
[10] SC2 is not listed, but supported for all world standards.
TDA8295_C2_2
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Product data sheet
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Digital global standard low IF demodulator for analog TV and FM radio
13. Application information
13.1 Typical application
2
I C-bus
2
I C-bus
SDA_O
SCL_O
SDA
SCL
V_IOUTN
V_IOUTP
V-sync
CVBS
SSIF
VSYNC
SAA71xx
(AUDIO AND
VIDEO
TDA8275A
TDA1827x
(TUNER ICs)
IF_POS
IF_NEG
low IF signal
TDA8295
DECODER)
S_IOUTP
IF_AGC
XIN
processed
audio and video
tuner IF AGC
S_IOUTN
RSET
reference frequency
001aah420
Fig 14. Typical application of TDA8295
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Product data sheet
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xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x
1.2 V
1.2 V
1.2 V
3.3 V
3.3 V
3.3 V
3.3 V
R6
10 Ω
R5
10 Ω
R8
2.2 Ω
R7
10 Ω
R9
10 Ω
R10
1 Ω
R11
1 Ω
C10
C9
C12
220 nF
F1
C11
C13
470 nF
F2
C14
470 nF
F3
C16
AGND
DGND
DGND
DGND
DGND
AGND
AGND
220 nF
220 nF
470 nF
470 nF
AGND
R12
AGND
AGND DGND
DGND
AGND
1 kΩ
R13
40
7
10
5
4
25
35
26
34
39
3
12
18
15 11
V_IOUTN
V_IOUTP
13
14
AGND
CVBS
XOUT
39 Ω
9
8
C2
reference
frequency
XIN
IF_POS
IF_NEG
R14
75 Ω
C5
470 pF
100 pF
C3
to SCART or
processor
to TDA8275A
or TDA1827x
AGND AGND
S_IOUTP
1
2
IC1
TDA8295
AGND/
DGND
SSIF or
AUDIO
1 nF
C4
17
16
R15
75 Ω
C6
270 pF
low IF
1 nF
AGND AGND
R16
S_IOUTN
R1
IF_AGC
37
29
AGND
150 kΩ
C7
2.2 nF
28
19
20
21
33
32
31
6
38
36
24
30
27
23
22
75 Ω
AGND
DGND DGND DGND DGND DGND DGND DGND
R3
100 Ω
R4
100 Ω
R2
2.2 kΩ
3.3 V supply
3.3 V
1.2 V supply
1.2 V
3.3 V
C8
C15
47 μF
C1
47 μF
100 nF
2
DGND
I C-bus
001aah421
DGND
DGND AGND
AGND
F1, F2, F3: BLM18AG102SN1 ferrite bead
Preferred components: SMD R1 has to be placed near to TDA8295 pin 37 and SMD C7 near to TDA8275A or TDA1827x
Fig 15. Detailed application diagram of TDA8295
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
13.3 DAC connection
This DAC has a differential current output capable of driving a doubly terminated 75 Ω
transmission line without external buffers. But it can also be used in single-ended
applications. In that case both outputs still need proper termination. The off-chip resistive
load must be connected to ground.
With the B_DA_V and B_DA_S coarse output level adjustment registers, the output
current can be increased (linearly) up to two times. However, the maximum output voltage
at both V_IOUTP, V_IOUTN and S_IOUTP, S_IOUTN output nodes still is 1.5 V.
DNL and INL increase when the external biasing resistor is increased. When higher load
resistances are used, distortion will increase linearly. About 12 dB increase in harmonic
distortion is expected at 150 Ω.
Several measures can be taken in order to reach good performance. Decouple the
VDDA(DAC1)(3V3) and the VDDA(DAC2)(3V3) supplies with at least 100 nF. Place the external
bias resistor close to the chip. Do not add decoupling capacitance to pin RSET.
The following relation gives the value of the full-scale current IFS in function of the bias
resistance value, FineControl (B_REF) and CoarseControl (B_DA_V or B_DA_S):
1.216
100
RSET 100 – FineControl
1
5
64 + CoarseControl
------------- -------------------------------------------- -- -----------------------------------------------
IFS
=
×
×
×
× 64
(1)
48
−7 ≤ FineControl ≤ +7
0 ≤ CoarseControl ≤ 63
For programming of FineControl (B_REF) see Table 55, for CoarseControl signals
B_DA_V see Table 53, for B_DA_S see Table 54.
13.4 ADC connection
The input signals of the ADC (IF_POS and IF_NEG) can be either AC coupled by means
of two capacitors or connected directly to the inputs (DC coupled). This selection is done
by programming of DCIN, see Table 51.
In case of AC coupling, DCIN should be set to logic 0, which enables two resistive dividers
between VDDA(ADC)(3V3) and VSSD1 take care of the correct DC biasing of the input signals.
In case only a single-ended input signal is available, this signal should be connected to
the IF_POS input by means of a coupling capacitor whereas the IF_NEG input should be
connected to ground using a similar capacitor.
In case the input signal is DC coupled, the input resistor network can be switched off by
setting the DCIN bit to logic 1. When using the ADC in this mode, the Common mode level
of the input signals should be at 0.5 × VDDA(ADC)(3V3). In case of single-ended operation,
the input signal should be connected directly to the IF_POS input and the IF_NEG input
should be connected to a voltage equal to the Common mode level of the input signal
(0.5 × VDDA(ADC)(3V3)).
The peak-to-peak input range can be set to 1 V (p-p) or 2 V (p-p) by programming of
GAINSET (see Table 51). With a differential input the performances of the ADC are
slightly better with GAINSET = 0 whereas with a single-ended input they are slightly better
with GAINSET = 1.
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Product data sheet
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Digital global standard low IF demodulator for analog TV and FM radio
13.5 Reset operation
13.5.1 Hardware reset
minimum width at LOW is 4 × T
XIN
RST_N
XIN
T
XIN
the TDA8295 enters
immediately in its reset mode
TDA8295 normal operation
starts after 4 falling edges of XIN
001aah362
Fig 16. Hardware reset operation
After a hardware reset, the registers are set to default (power-on reset values) according
to Table 10. M/N standard is the default standard.
CS[2:0] has to be reprogrammed to a value equal or higher than 1.00 (corresponding to
CS[2:0] = 100 or 101 or 110), because the default value is not allowed (full performance is
not guarantied with the default value).
13.5.2 Software reset
A software reset can be done each time something has been programmed. The software
reset does not affect the content of the registers but clears the flip-flops in the design. For
the activation of the software reset see Table 49 bit CLB.
13.6 Application hints
• In case GPIO1 and GPIO2 are configured as I2C-bus feed-through, a capacitor
C = 33 pF to GND must be added at pin 32 (GPIO1/SCL_O). This ensures a reliable
behavior in Read mode.
• The detailed application diagram (see Figure 15) shows the video DAC connection
driving a 75 Ω DC load and the sound DAC driving > 1 kΩ AC/DC load. Power-save
mode: In order to reduce power consumption, the video DAC can be run with half
current and the sound DAC with a quarter current by changing RSET (R12 in
Figure 15) to 2 kΩ. This is possible, if the audio/video processor is rather high-ohmic
(> 1 kΩ). The following components in Figure 15 have to be replaced then:
R13 = 75 Ω; R15 and R16 = 150 Ω; C5 = 220 pF; C6 = 120 pF. A performance
degradation is not expected in the Power-save mode.
The TDA8295 has been designed in such a way, that a simple upgrade of the
predecessor TDA8290 is possible:
1. Change the 1.8 V power supply to 1.2 V. This can be done easily with a variable
voltage regulator, where the sense pin is grounded. This delivers the band gap
voltage of 1.25 V to the output. Or take a fixed regulator.
2. The RSET resistor (R12 in Figure 15) has to be decreased by 20 % in order to make
the DAC output swing higher (1.5 V instead of 1.25 V).
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Product data sheet
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TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
3. Pin 6 and pin 36 (both internally connected pins) can still stay connected to the 1.2 V
power supply, as done in the PCBs for the predecessor TDA8290 without harm.
However, take grounds for new designs, because they are more easily accessible on
a PCB.
13.7 Crystal connection
The typical crystal frequency value is 16 MHz. The values of the passive components
depend on crystal manufacturer. The oscillator can be set in two configurations depending
on the origin of the crystal. Figure 17 describes the case of an crystal shared with the
tuner and the TDA8295 (Slave mode), Figure 18 the case of an crystal dedicated to the
TDA8295 (Oscillator mode).
TDA8295
TDA8295
R
bias
R
bias
XIN
XOUT
C2
XTAL
XIN
XOUT
100 nF
C1
clock signal
from tuner
n.c.
GND
GND
001aah364
001aah363
Slave mode
Oscillator mode
Fig 17. Reference clock application
Fig 18. Oscillator application
In Oscillator mode, only a crystal and the load capacitances C1 and C2 need to be
connected externally since the feedback resistance is integrated on chip. In this mode the
oscillator gain stage can have a normal or large transconductance, determined by the HF
bit (see also Table 61). A large transconductance is required for higher oscillation
frequencies, higher series resistance of the crystal and higher external load capacitors.
For an accurate time reference it is advised to use the load capacitors as specified in
Table 73. CL is the typical load capacitance of the crystal and is usually specified by the
crystal manufacturer.
Table 73. Crystal parameters together with external components
Fundamental
oscillation
frequency
Crystal load
capacitance
CL(xtal) (pF)
Crystal series
resistanceRs(xtal)
(Ω)
External load capacitors
C1 (pF)
C2 (pF)
Bit HF = 0
1 MHz to 5 MHz
10
20
30
< 300
< 300
< 300
< 300
< 200
< 100
< 160
< 60
18
39
56
18
39
56
18
39
18
39
56
18
39
56
18
39
5 MHz to 10 MHz 10
20
30
10 MHz to
15 MHz
10
20
TDA8295_C2_2
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Product data sheet
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TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Table 73. Crystal parameters together with external components …continued
Fundamental
oscillation
frequency
Crystal load
capacitance
CL(xtal) (pF)
Crystal series
resistanceRs(xtal)
(Ω)
External load capacitors
C1 (pF)
C2 (pF)
15 MHz to
20 MHz
10
< 80
18
18
Bit HF = 1
10 MHz to
15 MHz
10
20
10
20
10
20
10
20
10
< 200
< 120
< 180
< 100
< 160
< 80
18
39
18
39
18
39
18
39
18
18
39
18
39
18
39
18
39
18
15 MHz to
20 MHz
20 MHz to
25 MHz
25 MHz to
30 MHz
< 130
< 60
30 MHz to
35 MHz
< 120
35 MHz to
40 MHz
10
10
10
< 100
< 80
< 60
18
18
18
18
18
18
40 MHz to
45 MHz
45 MHz to
50 MHz
14. Test information
14.1 Boundary scan interface (“IEEE Std. 1149.1”)
The TDA8295 implements a boundary scan architecture to allow access to, and control of,
board test support features within integrated circuits through a TAP. The TAP controller is
a synchronous state machine that controls the sequence of operations on the TAP
circuitry when the TMS signal changes. All state transitions occur on the basis of the TMS
value on the rising edge of TCK. The instruction register is a shift register based design. It
decodes the test to be performed and/or the test data register to be accessed. The
instructions are shifted into the register through the TDI and are latched as the current
instruction at the completion of the shifting process. The TDA8295 boundary scan
architecture includes: a TAP controller, a scannable instruction register and three
scannable test data registers: a boundary scan register, a device ID register, and a bypass
register.
The supported instructions are: EXTEST, IDCODE, SAMPLE, INTEST, CLAMP, HIGHZ
and BYPASS.
The boundary scan register is composed of 16 cells (see Table 74). Each cell is
associated either to an input pad, an output pad, a bidirectional pad or to the bidirectional
or 3-state command itself. All cells are of ‘observe and control’ type.
The device ID register is a 32-bit identification register that is included in the scan register
itself and contains the ID number. It is a fixed value that identifies the chip.
TDA8295_C2_2
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Product data sheet
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NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
ID number structure is:
ID version [3:0] = 1h
ID part number [15:0] = 224Ch
ID manufacturer [11:1] = 015h
ID mandatory [0] = 1h
IDCODE [31:0] = 1224 C02Bh
When the boundary scan function is not used, please connect the four dedicated input
pins (TRST_N, TCK, TDI and TMS) to GND.
BOUNDARY
SCAN
REGISTER
DEVICE ID
REGISTER
MUX
BYPASS
REGISTER
control
MUX
TDO
FF
INSTRUCTION
TDI
DECODE
INSTRUCTION
REGISTER
TMS
TEST
select
3-state enable
ACCESS
PORT
CONTROLLER
TCK
TRST_N
001aac078
Fig 19. Boundary scan block diagram
TDA8295_C2_2
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Product data sheet
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Digital global standard low IF demodulator for analog TV and FM radio
Table 74. Boundary scan register list
Pad signal
Chain position
Pad type
Bidir
Ctrl
Scan type
Control signal
U1.vagc_cmd
U1.vagc_cmd
U1.gpio0_cmd
U1.gpio0_cmd
U1.gpio1_cmd
U1.gpio1_cmd
U1.gpio2_cmd
U1.gpio2_cmd
U1.sda_cmd
U1.sda_cmd
-
IF_AGC
[1]
control/observe
control/observe
control/observe
control/observe
control/observe
control/observe
control/observe
control/observe
control/observe
control/observe
control/observe
control/observe
control/observe
control/observe
control/observe
control/observe
[2]
GPIO0
GPIO1
GPIO2
SDA
[3]
Bidir
Ctrl
[4]
[5]
Bidir
Ctrl
[6]
[7]
Bidir
Ctrl
[8]
[9]
Bidir
Ctrl
[10]
[11]
[12]
[13]
[14]
[15]
[16]
SCL
input
input
Ctrl
RST_N
SADDR1
-
U1.saddr1_cmd
U1.saddr1_cmd
U0.saddr1_cmd
U0.saddr1_cmd
Bidir
Ctrl
SADDR0
Bidir
Table 75. Boundary scan electrical characteristics
Symbol Parameter
Conditions
TCK
Min
25
0
Typ
Max
Unit
ns
Tcy
tsu
cycle time
set-up time
hold time
-
-
-
-
-
TDI and TMS
TDI and TMS
-
ns
th
4
-
ns
td(TDO)
delay time on pin TDO on 50 pF
-
12
ns
T
cy
TCK
t
su
t
h
TDI, TMS
TDO
t
d
001aac079
Fig 20. Boundary scan timing diagram
TDA8295_C2_2
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Product data sheet
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TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
15. Package outline
HVQFN40: plastic thermal enhanced very thin quad flat package; no leads;
40 terminals; body 6 x 6 x 0.85 mm
SOT618-1
D
B
A
terminal 1
index area
A
A
E
1
c
detail X
C
e
1
y
y
1/2 e
e
v
M
M
C
b
C
C
A
B
1
11
20
w
L
21
10
e
e
E
h
2
1/2 e
1
30
terminal 1
index area
40
31
D
X
h
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
e
2
y
D
D
E
L
v
w
y
1
1
h
1
h
max.
0.05 0.30
0.00 0.18
6.1
5.9
4.25
3.95
6.1
5.9
4.25
3.95
0.5
0.3
mm
0.05 0.1
1
0.2
0.5
4.5
4.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
01-08-08
02-10-22
SOT618-1
- - -
MO-220
- - -
Fig 21. Package outline SOT618-1 (HVQFN40)
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Product data sheet
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Digital global standard low IF demodulator for analog TV and FM radio
16. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
16.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
16.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
16.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
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Digital global standard low IF demodulator for analog TV and FM radio
16.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 22) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 76 and 77
Table 76. SnPb eutectic process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
235
≥ 350
220
< 2.5
≥ 2.5
220
220
Table 77. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 22.
TDA8295_C2_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 27 November 2009
79 of 83
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 22. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
17. Abbreviations
Table 78. Abbreviations
Acronym
ADC
AFC
Description
Analog-to-Digital Converter
Automatic Frequency Control
Automatic Gain Control
AGC
CC
Color Carrier
CMOS
CORDIC
CVBS
DAC
DTO
DVD
FIR
Complementary Metal-Oxide Semiconductor
COordinate Rotation DIgital Computer
Color Video Blanking Signal
Digital-to-Analog Converter
Digitally Tuned Oscillator
Digital Versatile Disc
Finite Impulse Response
Frequency-Locked Loop
Frequency Phase-Locked Loop
Full Scale
FLL
FPLL
FS
GPIO
H/V
General Purpose Input Output
Horizontal and Vertical
HAD
IC
Half Amplitude Duration
Integrated Circuit
ICFM
Incidental Carrier Frequency Modulation
TDA8295_C2_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 27 November 2009
80 of 83
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
Table 78. Abbreviations …continued
Acronym
Description
ICPM
ID
Incidental Carrier Phase Modulation
IDentification
IF
Intermediate Frequency
Infinite Impulse Response
Neighbor Picture Carrier
Neighbor Sound Carrier
Picture Carrier
IIR
NPC
NSC
PC
PCB
PLL
POR
PWM
QSS
SAW
SC
Printed-Circuit Board
Phase-Locked Loop
Power-On Reset
Pulse Width Modulation
Quasi Split Sound
Surface Acoustic Wave
Sound Carrier
SMD
SSIF
STB
TAP
VCR
VITS
Surface Mounted Device
Second Sound Intermediate Frequency
Set-Top Box
Test Access Port
Video Cassette Recorder
Vertical Interval Test Signal
18. Revision history
Table 79. Revision history
Document ID
TDA8295_C2_2
Modifications:
Release date
20091127
Data sheet status
Change notice
Supersedes
Product data sheet
-
TDA8295_C2_1
• Table 1 and Table 72: values and notes for IDD(tot)(3V3) and Ptot have been adapted
• Table 42: table note has been added
• Figure 11 has been added
• Table 51: CS[2:0] values changed
• Table 72: added CVBS output specification under no signal condition
• Section 13.5.1: added a second paragraph
TDA8295_C2_1
20090721
Product data sheet
-
-
TDA8295_C2_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 27 November 2009
81 of 83
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
19. Legal information
19.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Applications — Applications that are described herein for any of these
19.2 Definitions
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
19.3 Disclaimers
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
19.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
Silicon Tuner — is a trademark of NXP B.V.
20. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
TDA8295_C2_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 27 November 2009
82 of 83
TDA8295
NXP Semiconductors
Digital global standard low IF demodulator for analog TV and FM radio
21. Contents
1
2
3
4
5
6
General description . . . . . . . . . . . . . . . . . . . . . . 1
9.3.18
9.3.19
Video and sound DAC control . . . . . . . . . . . . 46
Clock generation
(PLL and crystal oscillator). . . . . . . . . . . . . . . 48
GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Special equalizer functions for group
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Quick reference data . . . . . . . . . . . . . . . . . . . . . 3
Ordering information. . . . . . . . . . . . . . . . . . . . . 5
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 6
9.3.20
9.3.21
delay and video (CVBS). . . . . . . . . . . . . . . . . 53
10
11
12
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 57
Thermal characteristics . . . . . . . . . . . . . . . . . 57
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 58
7
7.1
7.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 7
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8
13
Application information . . . . . . . . . . . . . . . . . 69
Typical application . . . . . . . . . . . . . . . . . . . . . 69
Detailed application diagram . . . . . . . . . . . . . 70
DAC connection. . . . . . . . . . . . . . . . . . . . . . . 71
ADC connection. . . . . . . . . . . . . . . . . . . . . . . 71
Reset operation . . . . . . . . . . . . . . . . . . . . . . . 72
Hardware reset . . . . . . . . . . . . . . . . . . . . . . . 72
Software reset . . . . . . . . . . . . . . . . . . . . . . . . 72
Application hints. . . . . . . . . . . . . . . . . . . . . . . 72
Crystal connection . . . . . . . . . . . . . . . . . . . . . 73
8
Functional description . . . . . . . . . . . . . . . . . . 10
IF ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
PLL demodulator . . . . . . . . . . . . . . . . . . . . . . 10
Nyquist filter, video low-pass filter, video
and group delay equalizer, video leveling. . . . 10
Upsampler and video DAC . . . . . . . . . . . . . . . 11
SSIF/mono sound processing . . . . . . . . . . . . 11
Tuner IF AGC . . . . . . . . . . . . . . . . . . . . . . . . . 11
Digital IF AGC. . . . . . . . . . . . . . . . . . . . . . . . . 12
Clock generation. . . . . . . . . . . . . . . . . . . . . . . 12
I2C-bus control. . . . . . . . . . . . . . . . . . . . . . . . . 12
Protocol of the I2C-bus serial interface. . . . . . 12
Write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Read mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Register overview. . . . . . . . . . . . . . . . . . . . . . 15
Register description . . . . . . . . . . . . . . . . . . . . 21
Standard setting with easy programming . . . . 21
Diverse functions (includes tuner IF AGC
13.1
13.2
13.3
13.4
13.5
13.5.1
13.5.2
13.6
13.7
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
14
14.1
Test information . . . . . . . . . . . . . . . . . . . . . . . 74
Boundary scan interface
(“IEEE Std. 1149.1”). . . . . . . . . . . . . . . . . . . . 74
9
9.1
9.1.1
9.1.2
9.2
9.3
9.3.1
9.3.2
15
Package outline. . . . . . . . . . . . . . . . . . . . . . . . 77
16
Soldering of SMD packages. . . . . . . . . . . . . . 78
Introduction to soldering. . . . . . . . . . . . . . . . . 78
Wave and reflow soldering. . . . . . . . . . . . . . . 78
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 78
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 79
16.1
16.2
16.3
16.4
Pin mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
ADC headroom. . . . . . . . . . . . . . . . . . . . . . . . 24
Picture carrier PLL functions . . . . . . . . . . . . . 25
Picture and sound carrier DTO. . . . . . . . . . . . 28
Filter settings . . . . . . . . . . . . . . . . . . . . . . . . . 29
Group delay equalization . . . . . . . . . . . . . . . . 31
Digital IF AGC functions . . . . . . . . . . . . . . . . . 32
Tuner IF AGC functions . . . . . . . . . . . . . . . . . 34
V-sync adjustment . . . . . . . . . . . . . . . . . . . . . 35
CVBS settings . . . . . . . . . . . . . . . . . . . . . . . . 36
SSIF and mono sound settings . . . . . . . . . . . 38
Status registers: ADC saturation, AFC,
17
18
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 80
Revision history . . . . . . . . . . . . . . . . . . . . . . . 81
9.3.3
9.3.4
9.3.5
9.3.6
9.3.7
9.3.8
9.3.9
9.3.10
9.3.11
9.3.12
9.3.13
19
Legal information . . . . . . . . . . . . . . . . . . . . . . 82
Data sheet status. . . . . . . . . . . . . . . . . . . . . . 82
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 82
19.1
19.2
19.3
19.4
20
21
Contact information . . . . . . . . . . . . . . . . . . . . 82
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
H/V PLL and AGC . . . . . . . . . . . . . . . . . . . . . 40
Debug register for ADC and DAC test . . . . . . 43
Chip identification and Standby mode . . . . . . 43
Status of clock PLL and video/sound
9.3.14
9.3.15
9.3.16
DAC load . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
ADC control . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.3.17
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 27 November 2009
Document identifier: TDA8295_C2_2
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