TDA8296HN/C1,557_技术文档

TDA8296

Digital global standard low IF demodulator for analog TV and

FM radio

Rev. 1 — 3 March 2011

Product data sheet

1. General description

The TDA8296 is an alignment-free digital multistandard vision and sound low IF signal

PLL demodulator for positive and negative video modulation including AM and FM mono

sound processing. It can be used in all countries worldwide for M/N, B/G/H, I, D/K,

L and L-accent standard. CVBS and SSIF/mono audio are provided via two DACs. FM

radio preprocessing is included for simple interfacing with demodulator/stereo decoder

backends.

The IC is especially suited for the application with the NXP Silicon Tuner TDA1827x.

All the processing is done in the digital domain.

The chip has an ‘easy programming’ mode to make the I²C-bus protocol very simple. In

principle, only one bit sets the proper standard with recommended content. However, if

this is not suitable, free programming is always possible.

Note: Register 06h has to be reprogrammed to new value C4h (see Section 9.2 and

Section 9.3.1).

2. Features and benefits

Digital IF demodulation for all analog TV standards worldwide (M/N, B/G/H, D/K, I,

L and L-accent standard)

Multistandard true synchronous demodulation with active carrier regeneration

Alignment-free

16 MHz typical reference frequency input (from low IF tuner) or operating as crystal

oscillator

Internal PLL synthesizer which allows the use of a low-cost crystal (typically 16 MHz)

Especially suited for the NXP Silicon Tuner TDA1827x

No SAW filter needed

Low application effort and external component count in combination with the

TDA1827x

Simple upgrade of TDA8295 possible

12-bit low power IF ADC on chip running with 54 MHz or 27 MHz

Two 10-bit DACs on chip for CVBS and SSIF or audio

Easy programming for I²C-bus

High flexibility due to various I²C-bus programming registers

I²C-bus interface and I²C-bus feed-through for tuner programming

Four I²C-bus addresses selectable via two external pins

TDA8296

NXP Semiconductors

Digital global standard low IF demodulator for analog TV and FM radio

Gated IF AGC acting on black level by using H/V PLL or peak IF AGC (I²C-bus

selectable)

Internal digital logarithmic IF AGC amplifier with up to 48 dB gain and 68 dB control

range

Peak search tuner IF AGC for optimal adaptive drive of the IF ADC

Switchable IF PLL and IF AGC loop bandwidths

Precise AFC and lock detector

Accurate group delay equalization for all standards

Very robust IF demodulator coping with adverse field conditions

Wide PLL pull-in range up to ±1660 kHz (I²C-bus selectable)

CVBS and SSIF or audio output with simple postfilter (capacitor only)

CVBS gain levelling stage to provide nearly constant signal amplitude during over

modulation

Video equalizer with eight settings

Nyquist filter in video baseband

Excellent video S/N (typically 60 dB weighted)

High selectivity video low-pass filter for all standards

Low video into sound crosstalk

SSIF AGC

Sound performance comparable to QSS single reference concepts

AM/FM mono sound demodulator

Switchable de-emphasis

Excellent FM sound

Good AM sound

High FM Deviation mode for China

Preprocessing of FM radio (mono and stereo) with highly selective digital band-pass

filter

No ceramic filter or external components needed for FM radio

FM radio available in mono

Automatic or forced mute for mono sound

Automatic or forced blank for video

Mostly digital FIR filter implementation (NSC notches and video low-pass filters)

Three GPIO pins

Power-On Reset (POR) block for reliable power-up behavior

Very low total power dissipation (typically 150 mW)

No power sequence requirement

Standby mode (typically 5 mW)

40-pin HVQFN package

CMOS technology (0.090 μm 1.2 V and 3.3 V)

3. Applications

TV applications

Recording

PC TV applications

TDA8296

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 3 March 2011

2 of 87

TDA8296

NXP Semiconductors

Digital global standard low IF demodulator for analog TV and FM radio

4. Quick reference data

Table 1.

Quick reference data

Power supplies 3.3 V, 1.2 V; T_amb= 25 °C; PC/SC1 for L and M = 10 dB, all others 13 dB; nominal residual picture carrier of

3 % for L/L’ , 10 % for M, 10 % for B/G, 12.5 % for D/K, 20 % for I; FM/AM modulation = 54 %, 1 kHz modulation frequency;

measured in application PCB (see Figure 22 and Figure 23) with 16 MHz crystal frequency, terminated with 75 Ω (CVBS) and

1 kΩ (SSIF/audio). Operation mode set via easy programming (Section 9.3.1), otherwise stated. Low IF input signal at -3dB

full scale, input frequencies as defined under row header IF input.

Symbol

Parameter

Conditions

Min

Typ

Max Unit

Power supply

V_DD(1V2)

supply voltage (1.2 V)

supply voltage (3.3 V)

total supply current (1.2 V)

total supply current (3.3 V)

total power dissipation

digital and analog

1.1

1.2

3.3

49

1.3

V

V_DD(3V3)

3.0

3.6

V

I_DD(tot)(1V2)

I_DD(tot)(3V3)

P_tot

-

mA

mW

65

default settings; f_s= 54 MHz at ADC;

DAC application in accordance to

Figure 23

270

f_s= 54 MHz at ADC; DAC application in

accordance to Figure 24

-

150

5

-

mW

Standby mode

8

IF input

V_i(p-p)

V_i

peak-to-peak input voltage for full-scale ADC input (0 dBFS)

0.7

0.8

0.9

V

input voltage

operational input related to ADC full

scale; all standards; sum of all signals

−3

dBFS

f_i

input frequency

PC / SC1

M/N standard

B standard

G/H standard

I standard

-

5.40 / 0.90 -

6.40 / 0.90 -

6.75 / 1.25 -

7.25 / 1.25 -

6.85 / 0.35 -

6.75 / 0.25 -

1.25 / 7.75 -

MHz

D/K standard

L standard

L-accent standard

FM radio

1.25

-

Carrier recovery FPLL

B_−3dB(cl)

closed-loop −3 dB

wide

-

60

-

kHz

bandwidth

[1]

Δf_pullin

pull-in frequency range

-

±830

-

kHz

%

m_over(PC)

picture carrier over

modulation index

black for L/L-accent standard; flat field

white else

115

117

IF demodulation (video equalizer in Flat mode)

α_sup(stpb)

stop-band suppression

video low-pass filter (M/N, B/G/H, I, D/K,

L/L-accent standard)

-

−60

-

dB

ns

t_ripple(GDE)

group delay equalizer

ripple time

peak value for B/G/H half, D/K half,

I flat, M (FCC) full, L/L-accent full

standard

20

40

TDA8296

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Product data sheet

Rev. 1 — 3 March 2011

3 of 87

TDA8296

NXP Semiconductors

Digital global standard low IF demodulator for analog TV and FM radio

Table 1.

Quick reference data …continued

Power supplies 3.3 V, 1.2 V; T_amb= 25 °C; PC/SC1 for L and M = 10 dB, all others 13 dB; nominal residual picture carrier of

3 % for L/L’ , 10 % for M, 10 % for B/G, 12.5 % for D/K, 20 % for I; FM/AM modulation = 54 %, 1 kHz modulation frequency;

measured in application PCB (see Figure 22 and Figure 23) with 16 MHz crystal frequency, terminated with 75 Ω (CVBS) and

1 kΩ (SSIF/audio). Operation mode set via easy programming (Section 9.3.1), otherwise stated. Low IF input signal at -3dB

full scale, input frequencies as defined under row header IF input.

Symbol

Parameter

Conditions

Min

Typ

Max Unit

CVBS output

V_o(p-p)

peak-to-peak output

voltage

negative PC modulation (all standards

except L/L-accent); 75 Ω DC load;

sync-white modulation; 90 % (nominal)

0.9

1.0

1.1

V

positive PC modulation (L/L-accent

standard); 75 Ω DC load; sync-white

modulation; 97 % (nominal)

0.9

1.0

B_{video(−3dB)}

−3 dB video bandwidth

overall video response; CVBS equalizer

flat

all standards except M/N

M/N standard

4.7

3.8

−5

4.85

3.9

-

MHz

α_resp(f)

frequency response

video equalizer; 8 equally spaced

settings; value at 3.9 MHz

+4.5 dB

G_dif

differential gain

“ITU-T J.63 line 330”

-

1.5

1.0

60

5

3

-

%

ϕ_dif

differential phase

-

deg

dB

(S/N)_w

weighted signal-to-noise

ratio

all standards; unified weighting filter

(“ITU-T J.61”); PC at −6 dBFS

57

SSIF/mono sound output

V_o(SSIF)(RMS)RMS SSIF output voltage 1 kΩ DC or AC load; no modulation;

PC / SC1 = 13 dB

M standard

105

97

89

93

89

94

115

104

96

127

116

106

111

106

115

mV

B standard

G/H standard

D/K standard

I standard

100

96

L standard

L-accent standard

FM radio (single carrier)

96

103

V_o(AF)(RMS)

RMS AF output voltage

1 kΩ DC or AC load

M standard; 54 % modulation degree

(±13.5 kHz FM deviation before

pre-emphasis)

98

116

126

135

144

mV

B, G/H, I, D/K standard;

107

54 % modulation degree (±27 kHz

FM deviation before pre-emphasis)

α_hr(AF)

AF headroom

before clipping; 1 kΩ DC or AC load

M standard; related to ±25 kHz peak

deviation before pre-emphasis

-

7

-

dB

B, G/H, I, D/K standard; related to

±50 kHz peak deviation before

pre-emphasis

TDA8296

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Product data sheet

Rev. 1 — 3 March 2011

4 of 87

TDA8296

NXP Semiconductors

Digital global standard low IF demodulator for analog TV and FM radio

Table 1.

Quick reference data …continued

Power supplies 3.3 V, 1.2 V; T_amb= 25 °C; PC/SC1 for L and M = 10 dB, all others 13 dB; nominal residual picture carrier of

3 % for L/L’ , 10 % for M, 10 % for B/G, 12.5 % for D/K, 20 % for I; FM/AM modulation = 54 %, 1 kHz modulation frequency;

measured in application PCB (see Figure 22 and Figure 23) with 16 MHz crystal frequency, terminated with 75 Ω (CVBS) and

1 kΩ (SSIF/audio). Operation mode set via easy programming (Section 9.3.1), otherwise stated. Low IF input signal at -3dB

full scale, input frequencies as defined under row header IF input.

Symbol

Parameter

Conditions

Min

Typ

Max Unit

THD

total harmonic distortion

FM; for 50 kHz deviation before

-

0.15

0.3

%

pre-emphasis (25 kHz for M standard)

AM; m = 80 %

-

0.5

27

50

54

1

-

%

B_AF(−3dB)

−3 dB AF bandwidth

AM

FM

20

40

52

kHz

dB

-

(S/N)_w(AF)

AF weighted

via internal mono sound demodulator;

“ITU-R BS.468-4”; FM mode related to

27 kHz deviation before pre-emphasis;

10 % residual PC; SC1; color bar picture

-

signal-to-noise ratio

[2]

via internal mono sound demodulator;

(audio gain +6 dB) “ITU-R BS.468-4”;

AM; m = 54 %; 3 % residual PC; SC1;

color bar picture

40

44

-

dB

[1] The pull-in range can be doubled to ±1660 kHz by I²C-bus register like described in Table 16. Then the AFC read-out has 256 steps.

[2] To set audio gain to +6 dB for internal sound demodulation, register 22h has to be programmed to 08h.

5. Ordering information

Table 2.

Ordering information

Type number

Package

Name

Description

Version

TDA8296HN

HVQFN40

plastic thermal enhanced very thin quad flat package; no leads;

SOT618-1

40 terminals; body 6 × 6 × 0.85 mm

TDA8296

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Product data sheet

Rev. 1 — 3 March 2011

5 of 87

TDA8296

NXP Semiconductors

Digital global standard low IF demodulator for analog TV and FM radio

7. Pinning information

7.1 Pinning

terminal 1

index area

1

2

30

29

28

27

26

25

24

23

22

21

IF_POS

IF_NEG

TRST_N

SDA

3

V

SCL

DDA(ADC)(1V2)

4

V

TCK

DDD1(1V2)

5

V

SSD1

V

SSD2

TDA8296HN

6

i.c.

DDD2(1V2)

7

V

TMS

TDI

DDA(PLL)(1V2)

XIN

8

9

XOUT

TDO

RST_N

10

V

SSA(PLL)

008aaa139

Transparent top view

Fig 2. Pin configuration for HVQFN40

Table 3.

1

Pin allocation table

Symbol

2

Symbol

IF_POS

IF_NEG

3

V_{DDA(ADC)(1V2)}

V_SSD1

4

V_DDD1(1V2)

i.c.

5

6

7

V_{DDA(PLL)(1V2)}

XOUT

8

XIN

9

10

12

14

16

18

20

22

24

26

28

30

V_SSA(PLL)

V_SSA(DAC)

V_IOUTP

S_IOUTN

V_{DDA(DAC2)(3V3)}

SADDR1

TDO

11

13

15

17

19

21

23

25

27

29

RSET

V_IOUTN

V_{DDA(DAC1)(3V3)}

S_IOUTP

SADDR0

RST_N

TDI

TMS

V_DDD2(1V2)

TCK

V_SSD2

SCL

SDA

TRST_N

TDA8296

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Product data sheet

Rev. 1 — 3 March 2011

7 of 87

TDA8296

NXP Semiconductors

Digital global standard low IF demodulator for analog TV and FM radio

Table 3.

Pin allocation table …continued

31

Symbol

32

34

36

38

40

Symbol

GPIO1/SCL_O

V_DDDR(3V3)

i.c.

GPIO2/SDA_O

33

GPIO0/VSYNC

35

V_SSDR

37

IF_AGC

i.c.

39

n.c.

V_SSA(ADC)

die pad

global ground at backside contact

7.2 Pin description

Table 4.

Symbol

Reset

Pin description

Type^[1]

Description

RST_N

21

I

The RST_N input is asynchronous and active LOW, and clears the TDA8296. When

RST_N goes LOW, the circuit immediately enters its Reset mode and normal

operation will resume four XIN signal falling edges later after RST_N returns HIGH.

Internal register contents are all initialized to their default values. The minimum width

of RST_N at LOW level is four XIN clock periods.

Reference

XIN

8

9

I

Crystal oscillator input pin. In Slave mode (typically), the XIN input simply receives a

16 MHz clock signal (f_REF) from an external device (typically from the TDA1827x). In

Oscillator mode, a fundamental 16 MHz (typically) crystal is connected between

pin XIN and pin XOUT.

XOUT

O

Crystal oscillator output pin. In Slave mode, the XOUT output is not connected. In

Oscillator mode a fundamental 16 MHz (typically) crystal is connected between pin

XIN and pin XOUT.

I²C-bus

SDA

29

28

I/O, OD

I

I²C-bus bidirectional serial data. SDA is an open-drain output and therefore requires

an external pull-up resistor (typically 4.7 kΩ).

I²C-bus clock input. SCL is nominally a square wave with a maximum frequency of

400 kHz. It is generated by the system I²C-bus master.

SCL

SADDR0

SADDR1

19

20

I

These two bits allow to select four possible I²C-bus addresses, and therefore

permits to use several TDA8296 in the same application and/or to avoid conflict with

other ICs. The complete I²C-bus address is: 1, 0, 0, SADDR1, 0, 1, SADDR0, R/W

(see also Section 9.1).

I²C-bus feed-through switch or GPIO

GPIO2/SDA_O 31

I/O, OD

SDA_O is equivalent to SDA but can be 3-stated by I²C-bus programming. It is the

output of a switch controlled by I2CSW_EN parameter. SDA_O is an open-drain

output and therefore requires an external pull-up resistor (see Section 9.3.18).

GPIO1/SCL_O 32

I/O, OD

SCL_O is equivalent to SCL input but can be 3-stated by I²C-bus programming.

SCL_O is an open-drain output and therefore requires an external pull-up resistor

(see Section 9.3.18). For proper functioning of the I²C-bus feed-through, a capacitor

C = 33 pF to GND must be added (see Section 13.6).

V-sync or GPIO

GPIO0/VSYNC 33

I/O, OD

vertical synchronization pulse needed for the NXP Silicon Tuner

(see Section 9.3.18)

Tuner IF AGC

IF_AGC

37

I/O, OD, T tuner IF AGC output

TDA8296

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Product data sheet

Rev. 1 — 3 March 2011

8 of 87

TDA8296

NXP Semiconductors

Digital global standard low IF demodulator for analog TV and FM radio

Table 4.

Pin description …continued

Symbol

Type^[1]

Description

Boundary scan

TMS

24

30

I

Test mode select provides the logic levels needed to change the TAP controller from

state to state during the boundary scan test.

TRST_N

Test reset is used to reset the TAP controller (active LOW). Grounding is mandatory

in Functional mode.

TCK

TDI

27

23

22

I

Test clock is used to drive the TAP controller.

I

Test data input is the serial data input for the test data instruction.

TDO

O

Test data output is the serial test data output pin. The data is provided on the falling

edge of TCK.

ADC

IF_POS

IF_NEG

DAC

1

2

AI

IF positive analog input for internal ADC

IF negative analog input for internal ADC

V_IOUTP

V_IOUTN

S_IOUTP

S_IOUTN

RSET

14

13

17

16

11

AO

I

positive analog current output of the video output

negative analog current output of the video output

positive analog current output of the SSIF/mono sound output

negative analog current output of the SSIF/mono sound output

External bias setting of the DACs. An external resistor (1 kΩ typical) has to be

connected between RSET and the analog ground of the board. This resistor

generates the current into the DACs and also defines the full scale output current.

The total parasitic capacitance seen externally from the RSET pin has to be lower

than 20 pF.

Supplies and grounds

V_{DDA(DAC1)(3V3)}15

V_{DDA(DAC2)(3V3)}18

PS

DAC1 (video DAC) and DAC reference module analog supply voltage (3.3 V typical)

DAC2 (sound DAC) analog supply voltage (3.3 V typical)

DAC reference module analog ground supply voltage (0 V typical)

IF ADC analog supply voltage (1.2 V typical)

PS

V_SSA(DAC)

V_{DDA(ADC)(1V2)}

V_SSA(ADC)

V_DDD1(1V2)

V_SSD1

12

3

GND

PS

40

4

GND

PS

ADC analog ground supply voltage (0 V typical)

ADC, PLL and DACs digital supply voltage (1.2 V typical)

ADC, PLL and DACs digital ground supply voltage (0 V typical)

crystal oscillator and clock PLL analog supply voltage (1.2 V typical)

crystal oscillator and clock PLL analog ground supply voltage (0 V typical)

core digital supply voltage (1.2 V typical)

5

GND

PS

V_{DDA(PLL)(1V2)}

V_SSA(PLL)

V_DDD2(1V2)

V_SSD2

7

10

25

26

34

35

GND

PS

GND

PS

core digital ground supply voltage (0 V typical)

V_DDDR(3V3)

V_SSDR

ring digital supply voltage (3.3 V typical)

GND

ring digital ground supply voltage (0 V typical)

V_SS

die pad GND

Other pins

i.c.

6, 36,

38

I

internally connected; connect to ground

not connected

n.c.

39

[1] The pin types are defined in Table 5.

TDA8296

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Product data sheet

Rev. 1 — 3 March 2011

9 of 87

TDA8296

NXP Semiconductors

Digital global standard low IF demodulator for analog TV and FM radio

Table 5.

Pin type description

Description

Type

AI

analog input

AO

GND

I

analog output

ground

digital input

I/O

O

digital input and output

digital output

open-drain output

power supply

3-state

OD

PS

T

8. Functional description

8.1 IF ADC

The low IF spectrum (1 MHz to 10 MHz) from the Silicon Tuner TDA1827x is fed

symmetrically to the 12-bit IF ADC of the TDA8296, where it is sampled with 54 MHz or

27 MHz. All the anti-aliasing filtering is already done in the Silicon Tuner.

8.2 Filters

The internal filters permit to reduce the sampling rate to 13.5 MHz, and to form a complex

signal to ease the effort of further signal processing. Before this, the DC offset (coming

from the ADC) is removed.

In addition, standard dependent notch filters for the adjacent sound carriers protect the

picture carrier PLL from malfunctioning and avoid disturbances (i.e. moire) becoming

visible in the video output.

8.3 PLL demodulator

The second-order PLL is the core block of the whole IC. It is very robust against adverse

field conditions, like excessive over modulation, no residual carrier presence or unwanted

phase or frequency modulation of the picture carrier. The PLL output is the synchronously

demodulated channel.

The AFC data is available via the I²C-bus.

8.4 Nyquist filter, video low-pass filter, video and group delay equalizer,

video leveling

The afore-mentioned down-mixed complex signal at the mixer CORDIC output, already

consisting of the demodulated content of the picture carrier together with the sound

carriers (the so-called intercarriers), is running through a Nyquist filter to get a flat video

response and is made real.

Afterwards, a video low-pass filter suppresses the sound carriers and other disturbers.

Next comes the equalizer circuit to remove the transmitter group delay predistortion.

TDA8296

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Product data sheet

Rev. 1 — 3 March 2011

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TDA8296

NXP Semiconductors

Digital global standard low IF demodulator for analog TV and FM radio

A video leveling stage follows, which brings the output within the SCART specification

(±3 dB overall), despite heavy over modulation. The response time is made very slow.

Finally, a video equalizer allows to compensate the perhaps non-flat frequency response

from the tuner or to change the overall video response according to customer wish (i.e.

peaking or early roll-off).

8.5 Upsampler and video DAC

The filtered and compensated CVBS signal is connected to the oversampled 10-bit video

DAC (f_s= 108 MHz) via an interpolation stage. The strong oversampling replaces a

former complicated LCR postfiltering by a simple first-order RC low-pass filter to remove

the DAC image frequencies sufficiently. This holds also for the sound DAC, described in

Section 8.6.

8.6 SSIF/mono sound processing

The complex signal is routed via a band-pass, AGC and interpolation filter to the 10-bit

sound DAC for the recovery of the second sound carriers (SSIF). A very sharp band-pass

filter at 5.5 MHz is added in the FM Radio mode to remove neighbor channels. This also

eases the dynamic burden on the following ADC in the demodulator/decoder chip. The

afore-mentioned high-selectivity band-pass, which replaces the former ceramic filter, is

located behind a frequency shifter. In there, the incoming wanted FM radio channel from

the Silicon Tuner is changed from 1.25 MHz to 5.5 MHz.

Moreover, the complex signal is demodulated in a linear CORDIC detector and low-pass

filtered to attenuate the video spectrum and the second sound carrier, respectively other

disturbers above the intercarrier. The output of the linear CORDIC (phase information) is

differentiated for getting the demodulated FM audio. The AM demodulation is executed in

a synchronous fashion by using a narrow-band PLL demodulator.

A de-emphasis filter is implemented for FM standards, before the audio is interpolated to

108 MHz as in the CVBS case.

The mono audio is made available in the sound DAC via an I²C-bus controlled selector in

case the intercarrier path is not used for driving an external stereo demodulator.

However, if the mono audio output has to meet the SCART specification, an external

cheap operational amplifier with 12 dB gain becomes necessary, because the low supply

voltage for the TDA8296 doesn’t allow such high levels like 2 V (RMS) maximum.

8.7 Tuner IF AGC

This AGC controls the tuner IF AGC amplifier in the TDA1827x in such a way, that the

IF ADC is always running with a permanent headroom of 3 dB for the sum of all signals

present at the ADC input. This ensures an always optimal exploitation of the dynamic

range in the IF ADC.

The detection is done in peak Search mode during a field period. The attack time is made

much faster than the decay time in order to avoid transient clipping effects in the IF ADC.

This can happen during channel change or airplane flutter conditions.

TDA8296

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Product data sheet

Rev. 1 — 3 March 2011

11 of 87

TDA8296

NXP Semiconductors

Digital global standard low IF demodulator for analog TV and FM radio

The above wideband, slowly acting AGC loop (uncorrelated) is of first-order integral

action. It is closed via the continuous tuner IF AGC amplifier in the Silicon Tuner via a

bit stream DAC (PWM signal at 13.5 MHz, 27 MHz or 54 MHz) and an external and

uncritical first-order RC low-pass.

8.8 Digital IF AGC

Common to both IF AGC concepts is the peak search algorithm as long as the H/V PLL is

not locked. This is of advantage for the acquisition by avoiding hang-ups due to excessive

overloading, so being able to leave the saturated condition by reducing the gain.

Two Detection modes are made available in the IC via I²C-bus.

• Black level gated AGC:

The first mode uses an IF AGC detector which is gated with a very robust and

well-proven H/V sync PLL block on board. Gating occurs on the black level (most of

the time on the back porch) of the video signal and the control is delivered after an

error integration and exponential weighting to the internal IF AGC amplifier. This

IF AGC amplifier, in fact a multiplier, has a control range of −20 dB to +48 dB.

• Peak AGC:

A fast attack and slow decay action cares for a good and nearly clip-free transient

behavior. This proved to be more robust for non-standard signals, like sync clipping

along the transmitter/receiver chain.

With respect to the IF AGC speed generally, only the gated black level or peak sync

digital IF AGC can be made fast. However the peak search tuner IF AGC, used for

positive modulation standards (L and L-accent standard), is rather slow because the

VITS is present only once in a field.

The correlated or narrow-band AGC loop, closed via the continuous IF AGC amplifier

in the TDA8296, is of first-order integral action and settles at a constant IF input level

with a permanent headroom of 12 dB (picture carrier). This headroom is needed for

the own sound carriers and the leaking neighbor (N − 1) spectrum.

8.9 Clock generation

Finally, either an external reference frequency (i.e. from the Silicon Tuner) or an own

on-chip crystal oscillator in the TDA8296 feeds the internal PLL synthesizer to generate

the necessary clock signals.

9. I²C-bus control

9.1 Protocol of the I²C-bus serial interface

The TDA8296 internal registers are accessible by means of the I²C-bus serial interface.

The SDA bidirectional pin is used as the data input/output pin and SCL as the clock input

pin. The highest SCL speed is 400 kHz.

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Digital global standard low IF demodulator for analog TV and FM radio

9.1.1 Write mode

S

BYTE 1

A

BYTE 2

A

BYTE 3

data 1

A

BYTE n

data n

A

P

start

address 0

ack

start index

ack

....

ack

stop

001aad381

Fig 3. I²C-bus Write mode

Table 6.

Address format

7

6

5

4

3

2

1

0

1

0

SADDR1

0

1

SADDR0 R/W

Table 7.

Field

S

I²C-bus transfer description

Bit

Description

START condition

device address

SADDR1

-

Byte 1

7 to 5

4

3 and 2

device address

SADDR0

1

0

R/W = 0 for write action

acknowledge

start index

A

-

Byte 2

7 to 0

A

-

acknowledge

data 1

Byte 3

7 to 0

-

A

acknowledge

:

Byte n

7 to 0

data n

A

P

-

acknowledge

STOP condition

S

BYTE 1

1000 0100

A

BYTE 2

A

BYTE 3

A

P

start

ack

0000 0001

ack

0000 0010

ack

stop

001aah355

a. Address 84h, write 02h in register 01h

S

BYTE 1

A

BYTE 2

A

BYTE 3

0000 0101

A

BYTE 4

A

P

start

1000 0100

ack

0000 0010

ack

0000 0100

ack

stop

001aah356

b. Address 84h, write 05h in register 02h and 04h in register 03h

Fig 4. Examples I²C-bus Write mode

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9.1.2 Read mode

S

BYTE 1

A

BYTE 2

A

S

BYTE 3

A

BYTE 4

A

BYTE n

value n

A

P

start

address 0

ack

start index

ack

start

address 1

ack

value 1 ack ....

ack

stop

001aad423

Fig 5. I²C-bus Read mode

Table 8.

Field

S

I²C-bus transfer description

Bit

Description

-

START condition

device address

SADDR1

Byte 1

7 to 5

4

3 and 2

device address

SADDR0

1

0

R/W = 0 for write action

acknowledge

start index

A

-

Byte 2

A

7 to 0

-

acknowledge

S

-

START condition (without stop before)

device address

SADDR1

Byte 3

7 to 5

4

3 and 2

device address

SADDR0

1

0

R/W = 1 for read action

acknowledge

A

-

Byte 4

7 to 0

-

value 1

A

acknowledge

:

Byte n

7 to 0

value n

A

P

-

acknowledge

STOP condition

S

BYTE 1

A

BYTE 2

A

S

BYTE 3

A

BYTE 4

A

BYTE 5

0000 0100

A

P

start

1000 0100

ack

0000 0010

ack

start

1000 0101

ack

0000 0101

ack

stop

001aah357

Address 84h, read register 02h with value 05h and read register 03h with value 04h

Fig 6. Example I²C-bus Read mode

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9.2 Register overview

The TDA8296 internal registers are accessible by means of the I²C-bus serial interface as

described in Section 9.1. In Table 10 and Table 9 an overview of all the registers is given,

the register description can be found in Section 9.3.

Table 9.

Index

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

I²C-bus register reference

Name

I²C-bus access

R/W

Default value

01h

Reference

Table 11

Table 12

Table 14

Table 15

Table 16

Table 33

-

STANDARD

EASY_PROG

DIV_FUNC

00h

04h

ADC_HEADR

PC_PLL_FUNC

SSIF_MUTE

reserved

01h

24h

04h

48h^[1]

84h^[1]

08h^[1]

9Ah

reserved

-

reserved

-

DTO_PC_LOW

DTO_PC_MID

DTO_PC_HIGH

DTO_SC_LOW

DTO_SC_MID

DTO_SC_HIGH

FILTERS_1

Table 17

Table 19

Table 21

Table 22

Table 23

Table 24

Table 25

-

99h

3Dh

20h

59h

21h

FILTERS_2

31h

GRP_DELAY

D_IF_AGC_SET_1

D_IF_AGC_SET_2

reserved

01h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

21h

22h

23h

A0h

90h

67h^[1]

T_IF_AGC_SET

T_IF_AGC_LIM

T_IF_AGC_FORCE

reserved

88h

Table 26

Table 27

Table 28

-

F0h

3Fh

02h^[1]

88h^[1]

80h^[1]

00h^[1]

6Fh

reserved

-

reserved

-

reserved

-

V_SYNC_DEL

CVBS_SET

Table 29

Table 30

Table 31

Table 32

Table 34

Table 35

Table 36

Table 37

31h

CVBS_LEVEL

CVBS_EQ

73h

10h

SOUNDSET_1

SOUNDSET_2

SOUND_LEVEL

SSIF_LEVEL

21h

22h

08h

AFh

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Table 9.

I²C-bus register reference …continued

Index

24h

Name

I²C-bus access

Default value

Reference

Table 38

Table 39

Table 41

Table 42

Table 43

-

ADC_SAT

R

-

25h

AFC

R

-

26h

HVPLL_STAT

D_IF_AGC_STAT

T_IF_AGC_STAT

reserved

R

-

27h

R

-

28h

R

-

29h

R

-

2Ah

2Bh

2Ch

2Dh

2Eh

2Fh

30h

reserved

R/W

R

00h^[1]

-

ALT_FILT_COEF

reserved

Table 44

-

SSIF_AGC_STAT_REG

not used

R

-

Table 45

-

R/W

R

00h

-

IDENTITY

Table 46

Table 47

-

CLB_STDBY

reserved

R/W

R

01h

00h^[1]

-

31h

32h

reserved

-

33h

ADC_CTL

R/W

R

24h

05h

7Eh

00h

40h

20h^[1]

00h

00h^[1]

00h

61h^[1]

00h

1Ah

02h

01h

00h^[1]

1Bh

C1h

07h

-

Table 48

Table 49

Table 50

Table 51

Table 52

-

34h

ADC_CTL_2

VIDEODAC_CTL

AUDIODAC_CTL

DAC_REF_CLK_CTL

reserved

35h

36h

37h

38h

39h to 3Bh

3Ch

3Dh

3Eh

3Fh

40h

not used

-

reserved

-

not used

-

reserved

-

PLL_REG07

PLL_REG08

PLL_REG09

PLL_REG10

reserved

Table 53

-

41h

42h

43h

44h

GPIOREG_0

GPIOREG_1

GPIOREG_2

reserved

Table 54

Table 55

Table 57

-

45h

46h

47h to 4Ah

4Bh

4Ch

4Dh

4Eh

4Fh

50h

GD_EQ_SECT1_C1

GD_EQ_SECT1_C2

GD_EQ_SECT2_C1

GD_EQ_SECT2_C2

GD_EQ_SECT3_C1

GD_EQ_SECT3_C2

GD_EQ_SECT4_C1

R/W

00h

Table 58

51h

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Table 9.

I²C-bus register reference …continued

Index

52h

Name

I²C-bus access

R/W

Default value

00h

Reference

GD_EQ_SECT4_C2

not used

Table 58

53h to 56h

57h

00h

-

CVBS_EQ_COEF0_LOW

CVBS_EQ_COEF0_HIGH

CVBS_EQ_COEF1_LOW

CVBS_EQ_COEF1_HIGH

CVBS_EQ_COEF2_LOW

CVBS_EQ_COEF2_HIGH

CVBS_EQ_COEF3_LOW

CVBS_EQ_COEF3_HIGH

CVBS_EQ_COEF4_LOW

CVBS_EQ_COEF4_HIGH

CVBS_EQ_COEF5_LOW

CVBS_EQ_COEF5_HIGH

not used

00h

Table 60

58h

00h

Table 60

59h

00h

Table 60

5Ah

00h

Table 60

5Bh

00h

Table 60

5Ch

00h

Table 60

5Dh

00h

Table 60

5Eh

00h

Table 60

5Fh

00h

Table 60

60h

00h

Table 60

61h

00h

Table 60

62h

04h

Table 60

63h to 66h

67h

00h

-

reserved

FEh^[1]

0Fh^[1]

FAh^[1]

0Fh^[1]

EFh^[1]

0Fh^[1]

DDh^[1]

0Fh^[1]

BEh^[1]

0Fh^[1]

8Ah^[1]

0Fh^[1]

32h^[1]

0Fh^[1]

6Fh^[1]

0Eh^[1]

F4h^[1]

0Ah^[1]

00h

68h

reserved

69h

reserved

6Ah

reserved

6Bh

reserved

6Ch

reserved

6Dh

reserved

6Eh

reserved

6Fh

reserved

70h

reserved

71h

reserved

72h

reserved

73h

reserved

74h

reserved

75h

reserved

76h

reserved

77h

reserved

78h

reserved

79h to 7Bh

7Ch to 9Ch

9Dh to A0h

not used

reserved

00h^[1]

not used

00h

00h^[1]

A1h and A2h reserved

[1] This register must not be written with values other than default.

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9.3 Register description

If registers (or bit groups contained in registers) are programmed with invalid values, i.e.

values different from those described in the tables below, the default behavior is chosen

for the related block. Other settings than described in the tables are not allowed.

9.3.1 Standard setting with easy programming

With the implemented ‘easy programming’, only one bit sets the TV or FM radio standard

with recommended register content. If not suitable however, any of these registers can be

written with other settings. With the rising edge of the bit ACTIVE, some of the registers

02h to 23h are programmed internally with the standard dependent settings according to

Table 13. The content of registers with address 24h and higher is untouched.

Table 11. STANDARD register (address 00h) bit description

Legend: * = default value.

Bit

Symbol

Access Value

Description

7 to 0 STANDARD[7:0 R/W

]

TV or FM radio standard selection (easy

programming)

0000 0001*

0000 0010

0000 0100

0000 1000

0001 0000

0010 0000

0100 0000

1000 0000

M/N standard

B standard

G/H standard

I standard

D/K standard

L standard

L-accent standard

FM radio

In addition to application specific software settings following general recommendation

should be used (deviating from easy programming values):

• Register 06h: new value C4h

• Register 0Ch: new value 00h

• M/N standard:

– Register 10h: use narrow SSIF band-pass filter (SBP[3:0] = 0100)

– Register 0Dh and 0Eh: new value 55h

Remark: When using alternative ADC sampling frequencies the DTO settings have to be

adapted accordingly.

Table 12. EASY_PROG register (address 01h) bit description

Legend: * = default value.

Bit

7 to 1 -

ACTIVE

Symbol

Access Value

Description

R/W

000 0000* not used

0

With the rising edge of this bit, the registers

02h to 23h are programmed with the standard

dependent settings (see Table 13).

0*

no action

1

no action

0 to 1

activate easy programming

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Example: To set the device to B standard e.g., please do the following steps.

1. Write 02h to register STANDARD, address 00h (set B standard)

2. Write 00h to register EASY_PROG, address 01h

3. Write 01h to register EASY_PROG, address 01h (due to 0 to 1 transition of ACTIVE

the device is set to B standard, i.e. registers 02h to 23h are programmed

automatically according to Table 13)

4. Write 00h to register EASY_PROG, address 01h (reset ACTIVE to logic 0)

Table 13. Easy programming values

Register

Standard

M/N^[1]

04h

Index Name

B

G/H

04h

24h

04h

48h

84h

08h

00h

80h

7Bh

09h

6Dh

48h

32h

02h

A0h

90h

67h

31h

73h

10h

22h

04h

AFh

I

D/K

04h

24h

04h

48h

84h

08h

8Ch

1Ah

7Eh

BEh

84h

79h

44h

32h

04h

A0h

90h

67h

31h

75h

10h

22h

04h

AFh

L

L-accent FM radio

02h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

DIV_FUNC

04h

24h

04h

48h

84h

08h

15h

A3h

86h

7Bh

09h

6Dh

42h

32h

02h

A0h

90h

67h

31h

73h

10h

22h

04h

AFh

04h

24h

04h

48h

84h

08h

BEh

84h

76h

BEh

84h

76h

48h

32h

10h

A0h

90h

67h

31h

81h

10h

22h

04h

AFh

06h

24h

04h

48h

84h

08h

00h

80h

D6h

B9h

72h

44h

32h

08h

A0h

90h

67h

31h

6Ch

10h

44h

22h

04h

AFh

07h

24h

04h

48h

84h

08h

26h

B4h

17h

D6h

B9h

72h

48h

32h

08h

A0h

90h

67h

31h

6Ch

10h

44h

22h

04h

AFh

00h

20h

04h

48h

04h

08h

00h

80h

DAh

4Bh

68h

90h

34h

10h

A0h

08h

E7h

04h

73h

10h

22h

02h

AFh

PC_PLL_FUNC

SSIF_MUTE

reserved

24h

04h

48h

reserved

84h

reserved

08h

DTO_PC_LOW

DTO_PC_MID

DTO_PC_HIGH

9Ah

99h

0Ch DTO_SC_LOW

0Dh DTO_SC_MID

3Dh

20h

0Eh

0Fh

10h

11h

12h

13h

14h

DTO_SC_HIGH

FILTERS_1

59h

21h

FILTERS_2

31h

GRP_DELAY

01h

D_IF_AGC_SET_1 A0h

D_IF_AGC_SET_2 90h

reserved

67h

31h

73h

10h

21h

22h

08h

AFh

1Dh CVBS_SET

1Eh

1Fh

20h

21h

22h

23h

CVBS_LEVEL

CVBS_EQ

SOUNDSET_1

SOUNDSET_2

SOUND_LEVEL

SSIF_LEVEL

[1] M/N standard settings are equal to the power-on reset (default) values.

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9.3.2 Diverse functions (includes tuner IF AGC Pin mode)

Table 14. DIV_FUNC register (address 02h) bit description

Legend: * = default value.

Bit

Symbol

Access Value Description

7 and 6 T_IF_SEL[1:0] R/W

It determines the tuner IF AGC output Pin mode. The

open-drain output can be used in special applications

in need of a higher control voltage.

00*

01

10

11

Normal mode

Open-drain mode

3-state mode

not allowed

5 and 4 -

R/W

00*

0*

not used

3

2

-

reserved, must be set to logic 0

POL_DET

The polarity detector ensures the proper polarity of the

video signal. So, the sync impulses of the video output

are near ground level.

0

polarity detector off

polarity detector on

1*

1

0

VID_MOD

IF_SWAP

R/W

Selects video modulation. The only standards with

positive video modulation are L and L-accent.

0*

1

negative video modulation

positive video modulation

When HIGH, the demodulator expects a swapped IF

spectrum. This is the case in L-accent standard. This

option is also built in for flexibility reasons.

0*

1

normal IF spectrum expected

swapped IF spectrum expected

9.3.3 ADC headroom

Table 15. ADC_HEADR register (address 03h) bit description

Legend: * = default value.

Bit

7 to 4 -

3 to 0 ADC_HEADR[3:0] R/W

Symbol

Access Value Description

R/W 0000* not used

ADC_HEADR adjusts the needed headroom for the

wanted channel’s own sound carriers and the N − 1

adjacent sound carriers (PC in L-accent standard).

The ADC headroom is related to the sum of all

signals. This function is built in for debugging

purposes.

0001*

0010

0100

1000

ADC headroom 3 dB

ADC headroom 6 dB

ADC headroom 9 dB

ADC headroom 12 dB

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9.3.4 Picture carrier PLL functions

Table 16. PC_PLL_FUNC register (address 04h) bit description

Legend: * = default value.

Bit

Symbol

Access

Value

Description

7 to 3

PC_PLL_BW[4:0]

R/W

picture carrier PLL loop bandwidth selection

loop bandwidth 15 kHz (not recommanded)

loop bandwidth 30 kHz

0 0001

0 0010

0 0100*

0 1000

1 0000

loop bandwidth 60 kHz

loop bandwidth 130 kHz

loop bandwidth 280 kHz (not recommanded)

2

1

0

PLL_ON

PULL_IN

-

R/W

the picture carrier PLL can be disengaged (e.g. in FM radio

standard)

PLL off (FM radio)^[1]

PLL on^[2]

0

1*

PULL_IN selects the pull-in range of the picture carrier

PLL/FPLL

0*

1

pull-in range ±1.66 MHz

pull-in range ±830 kHz

0*

reserved, must be set to logic 0

[1] The DTO_PC frequency is set via register 09h to 0Bh

[2] The DTO_PC frequency is controlled by VIF_PLL function

9.3.5 Picture and sound carrier DTO

Table 17. DTO_PC_LOW, DTO_PC_MID and DTO_PC_HIGH register (address 09h to 0Bh) bit description

Legend: * = default value.

Address Register

Bit

Symbol

Access Value

Description

09h

0Ah

0Bh

DTO_PC_LOW 7 to 0 DTO_PC[7:0]

R/W

9Ah*

99h*

For picture processing the digital tuned oscillator

(DTO_PC) provides its oscillation signal to the

demodulator part. For demodulation the

DTO_PC_MID 7 to 0 DTO_PC[15:8] R/W

DTO_PC_HIGH 7 to 0 DTO_PC[23:16] R/W

oscillation frequency of the DTO_PC is controlled

by the VIF_PLL. Optional the DTO_PC can

operate at fixed programmed frequency. This will

be the case if PLL_ON register is set to “off”

mode. In case of VIF_PLL mode of the DTO_PC

the register value defines the nominal frequency

of AFC register (seeTable 39). If PLL_ON register

is set to “off” mode the DTO_PC register defines

the fixed oscillation frequency value of the

DTO_PC. The frequency of the DTO_PC is in

relation to the register value by following formula:

f_ADC⁄ 4 – f_PC

24

--------------------------------

DTO_PC =

× 2

.

f_ADC⁄ 4

In case of standard L’ please use the following

4

f_ADC

24

-----------

formula:

DTO_PC = f_PC

×

× 2

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001aan388

10

DTO_PC

frequency

value

8

(MHz)

(2)

6

4

2

0

(1)

0

4

8

12

DTO_PC reg val (dec) (1E6)

(1) relation for L’

(2) relation for systems L; M/N; B/G; I; D/K

Fig 7. TDA8296 DTO_PC characteristic

Table 18. Values of DTO_PC per TV standard at 54 MHz sampling frequency

Standard

DTO_SC[23:16]

DTO_SC[15:8]

DTO_SC[7:0]

9Ah

DTO_PC frequency value

5.40 MHz

M/N

99h

86h

80h

76h

7Eh

80h

17h

99h

A3h

00h

84h

1Ah

00h

B4h

B

15h

6.40 MHz

G

00h

6.75 MHz

I

BEh

7.25 MHz

D/K

8Ch

6.85 MHz

L

00h

6.75 MHz

L-accent

26h

1.25 MHz

Table 19. DTO_SC_LOW, DTO_SC_MID and DTO_SC_HIGH register (address 0Ch to 0Eh) bit description

Legend: * = default value.^[1]

Address Register

Bit

Symbol

Access Value

Description

0Ch

0Dh

0Eh

DTO_SC_LOW 7 to 0 DTO_SC[7:0]

R/W

00h*

20h*

59h*

The DTO_SC is suited for SSIF band-pass filter

tuning. DTO_SC is calculated according to the

following formula, whereas f_SCis the SSIF

band-pass center frequency:

DTO_SC_MID 7 to 0 DTO_SC[15:8] R/W

DTO_SC_HIGH 7 to 0 DTO_SC[23:16] R/W

f_SC

24

------------------

DTO_SC =

× 2

.

f_ADC⁄ 4

[1] Deviating from easy programming values for DTO_SC[23:0] the values from Table 20 should be used.

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TDA8296

NXP Semiconductors

Digital global standard low IF demodulator for analog TV and FM radio

001aam354

10

Fsc

[MHz]

8

6

4

2

0

4

8

12

DTO reg val (dec) (1E6)

Fig 8. TDA8296 DTO_SC characteristic

Table 20. Values for SSIF mode at 54 MHz sampling frequency

Standard

DTO_SC[23:16]

DTO_SC[15:8]

DTO_SC[7:0]

Band-pass center frequency

4.5 MHz

M/N

55h

6Dh

76h

72h

68h

55h

09h

84h

B9h

4Bh

00h

B

5.75 MHz

G/H

5.75 MHz

I

6.25 MHz

D/K

6.25 MHz

L/L-accent

FM radio

6.05 MHz

5.5 MHz

9.3.6 Filter settings

Table 21. FILTERS_1 register (address 0Fh) bit description

Legend: * = default value.

Bit

Symbol

Access

Value

Description

7 to 5

VID_FILT[2:0]

R/W

video low-pass filter to remove all unwanted frequencies

(own sound carriers) above video content (see Figure 9)

001*

010

100

video low-pass filter 4 MHz

video low-pass filter 5 MHz

video low-pass filter off

4 to 0

NOTCH_FILT[4:0]

R/W

The notch filter attenuates the adjacent sound carrier N − 1,

which is located differently dependent on standard

(see Figure 10).

0 0001*

0 0010

0 0100

0 1000

1 0000

notch filter at 6.9 MHz for M/N standard

notch filter at 7.9 MHz for B standard

notch filter at 8.3 MHz for D/K and L standard

notch filter at 9.25 MHz for G/H, I and L-accent standard

notch filter bypass

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TDA8296

NXP Semiconductors

Digital global standard low IF demodulator for analog TV and FM radio

008aaa223

10

α

resp(f)

(dB)

−10

−30

−50

−70

(1)

(2)

0

1

2

3

4

5

6

7

f (MHz)

(1) M/N standard.

(2) All other standards.

Fig 9. Video low-pass filters for sound carrier suppression

008aaa224

10

α

resp(f)

(dB)

(1)

(2)

(3)

(4)

−10

−30

−50

−70

0

2

4

6

8

10

12

14

f (MHz)

Notch filter for NSC (NPC for L-accent standard)

(1) M/N standard.

(2) B standard.

(3) D/K and L standard.

(4) G/H, I and L-accent standard.

Fig 10. Notch filter for adjacent sound carrier suppression

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NXP Semiconductors

Digital global standard low IF demodulator for analog TV and FM radio

Table 22. FILTERS_2 register (address 10h) bit description

Legend: * = default value.

Bit

Symbol

Access Value Description

7 and 6 -

R/W

00*

not used

5

VID_FILT_ R/W

LOW_RIP

video filter characteristic adjust

smooth roll-off

0

1*

low ripple

4

-

R/W

reserved, must be set to logic 1

3 to 0

SBP[3:0]

The SSIF band-pass attenuates unwanted video

frequencies^[1][2], e.g. color carrier. For FM radio standard

it provides almost channel selectivity (see Figure 12).

0001*

0010

SSIF band-pass, wide bandwidth

SSIF band-pass, normal bandwidth (1.1 MHz, all

TV standards)

0100

SSIF band-pass, narrow bandwidth (200 kHz,

FM radio)

[1] SSIF band-pass center frequency is controlled by DTO_SC[23:0]. See Table 20 for recommended DTO

values.

[2] Deviating from easy programming values for FILTERS_2, the narrow SSIF band-pass filter

(SPB[3:0] = 0100) should be used for M/N standard.

001aan681

2

amplitude

response

(dB)

-2

(1)

(2)

(3)

(4)

-6

-10

0

2

4

6

frequency (MHz)

(1) 4 MHz video filter in smooth roll off mode

(2) 4 MHz video filter in low ripple mode

(3) 5 MHz video filter in smooth roll off mode

(4) 5 MHz video filter in low ripple mode

Fig 11. Video low pass frequency response in smooth roll off or low ripple mode

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TDA8296

NXP Semiconductors

Digital global standard low IF demodulator for analog TV and FM radio

008aaa228

10

α

resp(f)

(dB)

(1)

(2)

(3)

−10

−30

−50

−70

0

2

4

6

8

10

12

14

f (MHz)

(1) Wide bandwidth (e.g. for search mode).

(2) All TV standards, normal bandwidth (1.1 MHz).

(3) FM radio, narrow bandwidth (200 kHz).

Fig 12. SSIF and FM radio band-pass filters (center frequency 5.5 MHz chosen)

9.3.7 Group delay equalization

Table 23. GRP_DELAY register (address 11h) bit description

Legend: * = default value.

Bit

Symbol

Access Value

Description

7

GD_EQ_CTRL R/W

group delay equalizer control; this is the control for

the freely programmable group delay equalizer; for

details see Section 9.3.19

0*

1

off (equalizer bypassed)

on (equalizer active)

6 and 5 -

R/W

00*

reserved, must be set to logic 00

4 to 0 GRP_DEL[4:0] R/W

group delay equalization to correct the transmitter

predistortion

0 0001*

0 0010

0 0100

0 1000

1 0000

group delay M/N standard

group delay B/G/H standard

group delay D/K standard

group delay L/L-accent standard

group delay I (flat) standard

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TDA8296

NXP Semiconductors

Digital global standard low IF demodulator for analog TV and FM radio

9.3.8 Digital IF AGC functions

Table 24. D_IF_AGC_SET_1 register (address 12h) bit description

Legend: * = default value.

Bit

7

Symbol

Access Value

Description

-

R/W

1*

reserved, must be set to logic 1

6

D_IF_AGC_MODE R/W

If HIGH, the digital IF AGC detection and gating is

done during the back porch of the video signal.

This Detection mode can be used for all

standards (also L/L-accent standard) without

impact on the IF AGC loop speed.

0*

1

peak sync AGC (slow peak white L/L-accent

standard)

black level AGC detection

5 to 0 -

R/W

10 0000* reserved, must be set to logic 10 0000

Table 25. D_IF_AGC_SET_2 register (address 13h) bit description

Legend: * = default value.

Bit

Symbol

Access Value

Description

7

-

R/W

1*

reserved, must be set to logic 1

6 to 0 D_IF_AGC_BW[6:0] R/W

digital IF AGC 3 dB-loop bandwidth setting

000 0001

000 0010

000 0100

000 1000

001 0000*

010 0000

100 0000

25 Hz

50 Hz

100 Hz

200 Hz

400 Hz

800 Hz

1.6 kHz (not recommended)

9.3.9 Tuner IF AGC functions

Table 26. T_IF_AGC_SET register (address 15h) bit description

Legend: * = default value.

Bit

Symbol

Access Value

Description

7

POL_TIF

R/W

0

tuner IF AGC polarity

inverted tuner IF AGC polarity

1*

normal tuner IF AGC polarity: the higher

the necessary gain, the higher the IF

AGC voltage

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NXP Semiconductors

Digital global standard low IF demodulator for analog TV and FM radio

Table 26. T_IF_AGC_SET register (address 15h) bit description …continued

Legend: * = default value.

Bit

Symbol

Access Value

Description

6 to 0 T_IF_AGC_SPEED[6:0] R/W

T_IF_AGC_SPEED determines the tuner

IF AGC loop speed

000 0001

000 0010

000 0100

000 1000*

−18 dB nominal

−12 dB nominal

−6 dB nominal

nominal speed (determined by the tuner

IF control slope)

001 0000

010 0000

100 0000

+6 dB nominal

+12 dB nominal

+18 dB nominal

Table 27. T_IF_AGC_LIM register (address 16h) bit description

Legend: * = default value.

Bit

Symbol

Access Value Description

7 to 4 UP_LIM[3:0]

R/W The tuner IF AGC output voltage can be limited to

interface with concepts having power supply < 3.3 V.

UP_LIM determines the upper limit from ¹∨₂FS (= 0h)

to FS (= Fh). The format is straight binary.

1111*

0000*

set upper limit to maximum

3 to 0 LOW_LIM[3:0] R/W

LOW_LIM determines the lower tuner IF AGC output

limit from 0 (= 0h) to ¹∨₂FS (= Fh). The format is

straight binary.

set lower limit to minimum

Table 28. T_IF_AGC_FORCE register (address 17h) bit description

Legend: * = default value.

Bit

Symbol

Access Value Description

R/W the tuner IF AGC output voltage can be forced

7

T_FORCE

externally to a fixed voltage, determined by

T_FORCE_VAL

0*

1

tuner IF AGC normal operation

tuner IF AGC output voltage determined by

T_FORCE_VAL

6 to 0 T_FORCE_VAL[6:0] R/W

T_FORCE_VAL determines the tuner IF AGC

forced value. So the tuner IF AGC can be fixed to

a certain value for debugging purposes. Format is

straight binary.

3Fh*

XXh

0.5 × V_DD(3V3), i.e. 1.65 V nominally

don’t care if T_FORCE = 0

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TDA8296

NXP Semiconductors

Digital global standard low IF demodulator for analog TV and FM radio

9.3.10 V-sync adjustment

Table 29. V_SYNC_DEL register (address 1Ch) bit description

Legend: * = default value.

Bit

Symbol

Access Value

Description

7 and 6 VS_WIDTH[1:0] R/W

VS_WIDTH determines the width (in horizontal

lines) of the V-sync gating pulse (needed for gating

of tuner RF AGC2)

00

01*

10

11

width 1 line (64 μs)

width 2 lines

width 4 lines

width 16 lines

5

VS_POL

R/W

VS_POL determines the polarity of the V-sync

pulse: if VS_POL = 1, the first edge of the pulse is

positive, else negative.

0

first edge negative

first edge positive

1*

4 to 0

VS_DEL[4:0]

VS_DEL determines the first edge position of the

output V-sync pulse compared to the beginning of

the vertical blanking interval:

pulse_position = (VS_DEL – 12) lines

0Fh*

first edge 3 lines after beginning of vertical

interval

9.3.11 CVBS settings

Table 30. CVBS_SET register (address 1Dh) bit description

Legend: * = default value.

Bit

Symbol

Access Value Description

7 and 6 -

5 and 4 -

R/W

00*

11*

not used

must be set to logic 11 or in case of L/L-accent to 01

video equalizer mode control

3

CVBS_EQ_ R/W

CTRL

0*

1

mode using predefined settings like described in

Table 32

free programmable mode; for details

see Section 9.3.19

2

1

0

FOR_BLK

R/W

when active, the video output is always blanked, e.g. for

channel change (forced blank)

0*

1

no action

video blanked

AUTO_BLK R/W

when active, the video output is blanked if the horizontal

line lock flag (N_H_LOCK, see Table 41) is not present

0*

1

auto-blanking off

auto-blanking on

-

R/W

1*

reserved, must be set to logic 1

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NXP Semiconductors

Digital global standard low IF demodulator for analog TV and FM radio

Table 31. CVBS_LEVEL register (address 1Eh) bit description

Legend: * = default value.

Bit

Symbol

Access Value Description

7 to 0 CVBS_LVL[7:0] R/W

With this byte, the nominal video output level is freely

programmable. The format is unsigned integer (offset

binary). Settings below 40h and above C0h, which

correspond to −5 dB (40h) and +4.5 dB (C0h) related to

the default value, are forbidden. In the following some

possible settings in 1 dB steps are shown.

51h

5Bh

66h

73h*

81h

91h

A2h

−3 dB nominal

−2 dB nominal

−1 dB nominal

nominal: 1 V (p-p) video output level (sync-peak)

+1 dB nominal

+2 dB nominal

+3 dB nominal

Table 32. CVBS_EQ register (address 1Fh) bit description

Legend: * = default value.

Bit

Symbol

Access Value

Description

7 to 0 CVBS_EQ[7:0] R/W

The video equalizer can be used for the

compensation of a principal tuner tilt or to change

the video frequency according to customer taste.

The figures given are at 5 MHz CVBS with respect

to low frequencies (see Figure 13).

0000 0001

0000 0010

0000 0100

0000 1000

0001 0000*

0010 0000

0100 0000

1000 0000

The video frequency response is −8 dB for

5 MHz.

The video frequency response is −6 dB for

5 MHz.

The video frequency response is −4 dB for

5 MHz.

The video frequency response is −2 dB for

5 MHz.

The video frequency response is made flat in this

mode.

The video frequency response is +2 dB (peaking)

for 5 MHz.

The video frequency response is +4 dB (peaking)

for 5 MHz.

The video frequency response is +6 dB (peaking)

for 5 MHz.

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TDA8296

NXP Semiconductors

Digital global standard low IF demodulator for analog TV and FM radio

001aah361

10

α

resp(f)

(dB)

6

2

−2

−6

−10

0

1

2

3

4

5

6

7

f (MHz)

Fig 13. Video equalizer curves

9.3.12 SSIF and mono sound settings

Table 33. SSIF_MUTE register (address 05h) bit description

Legend: * = default value.

Bit

Symbol

Access Value

Description

7 and 6 -

R/W

00*

not used

5 to 2

SSIF_AFC_WIN[3:0] R/W

SSIF AFC mute window configuration

0001*

0010

0100

1000

±100 kHz

±200 kHz

±400 kHz

±800 kHz

1

0

SSIF_MUTE_TYPE R/W

SSIF_MUTE_CTRL R/W

SSIF auto-mute behavior

0*

1

reduced gain

mute

auto-mute of SSIF output

0*

1

off

on

Table 34. SOUNDSET_1 register (address 20h) bit description

Legend: * = default value.

Bit

Symbol

Access Value

Description

7

-

R/W

0*

reserved, must be set to logic 0

6 and 5 AM_FM_SND[1:0]

Output mode for inbuilt FM/AM mono sound

demodulator

01*

10

FM sound

AM sound (only L/L-accent standard)

XX

don’t care if SSIF output is chosen

(SSIF_SND[1:0] = 10)

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NXP Semiconductors

Digital global standard low IF demodulator for analog TV and FM radio

Table 34. SOUNDSET_1 register (address 20h) bit description …continued

Legend: * = default value.

Bit

Symbol

Access Value

Description

4 to 0

DEEMPH[4:0]

R/W

mono sound de-emphasis adjustment to

compensate transmitter pre-emphasis; or

low-pass filter to remove out of audio band

interferers

0 0001*

0 0010

0 0100

0 1000

1 0000

de-emphasis of 75 μs for M/N standard or

non-European FM radio to compensate the

transmitter pre-emphasis

de-emphasis of 50 μs for B/G/H, D/K and

I standard or European FM radio to

compensate the transmitter pre-emphasis

low-pass filter with 30 kHz −3 dB cut-off

frequency to remove out of audio band

interferers

low-pass filter with 140 kHz −3 dB cut-off

frequency to drive an external BTSC stereo

decoder

The de-emphasis filter is bypassed. This

can be used for debugging or other

purposes.

Table 35. SOUNDSET_2 register (address 21h) bit description

Legend: * = default value.

Bit

7

Symbol

Access Value Description

-

R/W

0*

reserved, must be set to logic 0

6

SSIF_AGC_TC

SSIF AGC time constant for L/L-accent standard

0*

1

slow (normal)

fast

5

4

SSIF_AGC_CTRL R/W

SSIF AGC control

SSIF AGC off

SSIF AGC on

0

1*

HD_DK

R/W

When active, the internal FM mono sound demodulator can handle

excessive FM deviations up to 400 kHz. This might happen in D/K standard

China. To activate this mode, it is mandatory to set D/K standard first. The

sound output level has to be adapted accordingly by the microprocessor to

avoid sound DAC clipping. E.g. for 400 kHz FM deviation, the −12 dB setting

of the sound level register (see Table 36) is recommended.

0*

1

high Deviation mode off

high Deviation mode on

X

don’t care if SSIF output is chosen (SSIF_SND[1:0] = 10)

3

FOR_MUTE

R/W

When active, the mono sound signal is always muted. This setting only

makes sense in case the sound DAC output is also set to mono sound

(SSIF_SND[1:0] = 01). FOR_MUTE has no function if SSIF_SND[1:0] = 10.

0*

1

off

on

X

don’t care if SSIF output is chosen (SSIF_SND[1:0] = 10)

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TDA8296

NXP Semiconductors

Digital global standard low IF demodulator for analog TV and FM radio

Table 35. SOUNDSET_2 register (address 21h) bit description …continued

Legend: * = default value.

Bit

Symbol

Access Value Description

R/W When active, the mono sound signal is muted if the horizontal lock flag

2

AUTO_MUTE

(N_H_LOCK) disappears. This setting only makes sense in case the sound

DAC output is also set to mono sound (SSIF_SND[1:0] = 01). FOR_MUTE

has no function if SSIF_SND[1:0] =10.

0*

1

off

on

X

don’t care if SSIF output is chosen (SSIF_SND[1:0] = 10)

1 and 0 SSIF_SND[1:0]

R/W

either mono sound or SSIF can be chosen for the sound DAC output

01

mono sound^[1]

10*

SSIF

[1] Before activating mono sound, the TV standard needs to be set via easy programming

Table 36. SOUND_LEVEL register (address 22h) bit description

Legend: * = default value.

Bit

Symbol

Access Value

Description

7 to 5 -

R/W

000*

not used

4 to 0 SND_LVL[4:0] R/W

mono sound output level

0 0001

0 0010

−12 dB nominal; implemented for flexibility reasons. With this setting, the

adaptation to different standard requirements can be done.

−6 dB nominal; implemented for flexibility reasons. With this setting, the

adaptation to different standard requirements can be done. It is chosen for FM

radio because of the large FM deviation involved.

0 0100

0 1000*

1 0000

X XXXX

Nominal setting; FM deviations up to 100 kHz can be processed without sound

DAC clipping. The clipping level is 535 mV (RMS) typically.

+6 dB nominal; chosen for M/N standard due to less nominal frequency

deviation

+12 dB nominal; implemented for flexibility reasons. With this setting, the

adaptation to different standard requirements can be done.

don’t care if SSIF output is chosen (SSIF_SND[1:0] = 10)

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NXP Semiconductors

Digital global standard low IF demodulator for analog TV and FM radio

Table 37. SSIF_LEVEL register (address 23h) bit description

Legend: * = default value.

Bit

Symbol

Access Value

Description

7 to 0 SSIF_LVL[7:0] R/W

SSIF output level adjustment; SSIF AGC on

(21h[5] = 1)

1111 1111

+3 dB

:

1010 1111*

:

0 dB

:

0100 0000

to

−8.7 dB

0000 0000

SSIF output level adjustment; SSIF AGC off

(21h[5] = 0)

XXX0 0001

XXX0 0010

XXX0 0100

XXX0 1000

XXX1 0000

XXXX XXXX

−12 dB nominal; implemented for flexibility

reasons. With this setting, the adaptation to

different standard requirements can be done.

−6 dB nominal; implemented for flexibility

reasons. With this setting, the adaptation to

different standard requirements can be done.

Nominal setting; typical output level is

55 mV (RMS) for PC / SC ratio of 13 dB

(see Section 12, SSIF/mono sound output).

+6 dB nominal; implemented for flexibility

reasons. With this setting, the adaptation to

different standard requirements can be done.

+12 dB nominal; implemented for flexibility

reasons. With this setting, the adaptation to

different standard requirements can be done.

don’t care if mono sound output is chosen

(SSIF_SND[1:0] = 01)

Remark: The SSIF level depends also on the used capacitor C_S. Please refer to

Figure 14

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TDA8296

NXP Semiconductors

Digital global standard low IF demodulator for analog TV and FM radio

001aam355

140

SSIFout

(mVrms)

120

100

80

(1)

(2)

(3)

(4)

(5)

4.5

5.0

5.5

6.0

6.5

frequency (MHz)

(1) 150 pF

(2) 180 pF

(3) 220 pF (used for characteristics data)

(4) 270 pF

(5) 330 pF

Fig 14. TDA8296 SSIF characteristic versus C_S(refer to Figure 23) typical values;

termination 75 Ω and 1 kΩ in parallel

9.3.13 Status registers: ADC saturation, AFC, H/V PLL and AGC

Table 38. ADC_SAT register (address 24h) bit description

Bit

Symbol

Access Value

Description

7 to 0 ADC_SAT[7:0]

R

-

With ADC_SAT, the ADC saturation percentage in a

period of 40 ms can be calculated by the following

ADC_SAT

------------------------

formula: saturation =

(%) .

256

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Digital global standard low IF demodulator for analog TV and FM radio

Table 39. AFC register (address 25h) bit description

Bit

Symbol

Access Value

Description

7 to 0 AFC[7:0]

R

-

This is the readout for AFC. AFC contains the

frequency deviation from nominal IF picture carrier.

The format is twos complement, 13.2 kHz steps are

done per LSB. See Table 40 for details. The frequency

deviation could also be given by the following formula:

–AFC × 6 750

---------------------------------

(kHz) . For a frequency

f_IF– f_nom

=

512

deviation from the nominal IF picture carrier greater

than the FPLL pull-in capability (−830.6 kHz to

+843.8 kHz or −1674.3 kHz to +1687.5 kHz), the

output reading is undefined. The AFC lock indication

can be taken from the N_H_LOCK information from the

H-sync PLL. The lock occurs inside a frequency

window, which is determined by the pull-in capability of

the FPLL.

Table 40. Calculation of frequency deviation from AFC value

Deviation from nominal AFC[7] AFC[6] AFC[5] AFC[4] AFC[3] AFC[2] AFC[1] AFC[0]

IF frequency^[1]

f_IF= f_nom− 1674.3 kHz

f_IF= f_nom− 1661.1 kHz

:

0

:

1

:

1

:

1

:

1

:

1

:

1

:

1

0

:

f_IF= f_nom− 830.6 kHz

f_IF= f_nom− 817.4 kHz

:

0

:

0

:

1

:

1

:

1

:

1

:

1

:

1

0

:

f_IF= f_nom− 13.2 kHz

f_IF= f_nom

0

1

:

0

1

:

0

1

:

0

1

:

0

1

:

0

1

:

0

1

:

1

0

1

:

f_IF= f_nom+ 13.2 kHz

:

f_IF= f_nom+ 830.6 kHz

f_IF= f_nom+ 843.8 kHz

:

1

:

1

:

0

:

0

:

0

:

0

:

0

:

1

0

:

f_IF= f_nom+ 1674.3 kHz

f_IF= f_nom+ 1687.5 kHz

1

0

1

0

[1] See Section 12 for nominal IF frequencies.

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Digital global standard low IF demodulator for analog TV and FM radio

001aam356

150

AFC

reg val

50

−50

(1)

(2)

(1)

830 kHz PLL lock mode

1660 kHz PLL lock mode

0

−150

−2000

−1000

1000

2000

Df (MHz)

(1) Undefined area in 1660 kHz mode

(2) Undefined area in 830 kHz mode

Fig 15. TDA8296 AFC characteristic

Table 41. HVPLL_STAT register (address 26h) bit description

Bit Symbol Access Value Description

7 and 6 -

R

-

not used

5

NOISE_DET R

This flag gets HIGH in case the video S/N (weighted)

drops below 30 dB. For proper and noise free video

signals it stays LOW. It can be used for debugging and

other purposes.

4

3

2

1

0

MAC_DET

FIDT

R

-

This flag indicates the presence of copy-guarded video

content from STBs or VCRs. It can be used for

debugging and other purposes.

This flag indicates the frame rate (50 Hz or 60 Hz).

When active, 60 Hz is detected. It can be used for

debugging and other purposes.

V_LOCK

F_H_LOCK

N_H_LOCK

This flag is active, if a proper frame (50 Hz or 60 Hz) is

detected. It can be used for debugging and other

purposes.

This flag is active, if a proper H-sync (15.625 kHz or

15.734 kHz) is detected (Fast mode). It can be used for

debugging and other purposes.

This flag is active, if a proper H-sync (15.625 kHz or

15.734 kHz) is detected (Normal mode). It can be used

for debugging and other purposes.

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Table 42. D_IF_AGC_STAT register (address 27h) bit description

Bit

Symbol

Access Value

Description

7 to 0 D_IF_AGC_STAT[7:0]

R

-

D_IF_AGC_STAT is the digital IF AGC status

readout byte. Contains the digital IF AGC loop

DC information. The format is twos

complement. To get the internal gain in dB, the

following formula can be used:

D_IF_AGC_STAT + 50

--------------------------------------------------------

gain =

(dB) .

3.675

Table 43. T_IF_AGC_STAT register (address 28h) bit description

Bit Symbol Access Value Description

7 to 0 T_IF_AGC_STAT[7:0]

R

-

T_IF_AGC_STAT is the IF AGC status readout

byte. Contains the tuner IF AGC loop DC

information. The format is offset binary.

Table 44. ALT_FILT_COEF register (address 2Bh) bit description

Bit Symbol Access Value Description

Frequency

7 to 2 not used

R/W

0

not used.

1 to 0 ALT_FILT_COEF

00

01

10

internal selection of fixed

coefficients for video low

pass filter using an ADC

sampling frequency of

54.00 MHz

50.75 MHz

57.25 MHz

Table 45. SSIF_AGC_STAT register (address 2Dh) bit description

Bit Symbol Access Value Description

7 to 0 SSIF_AGC_STAT[7:0] R

-

SSIF_AGC_STAT contains the SSIF AGC gain

information. To get the internal gain in dB, the

following formula can be used:

SSIF_AGC_STAT

gain = 20log ------------------------------------------ . The value is

8

10

approximately the PC / SC ratio.

9.3.14 Chip identification and Standby mode

Table 46. IDENTITY register (address 2Fh) bit description

Bit

Symbol

Access Value

Description

7 to 0 IDENTITY[7:0] R

1000 1100* chip identification, value corresponds to TDA8296

Table 47. CLB_STDBY register (address 30h) bit description

Legend: * = default value.

Bit

Symbol Access Value

Description

0000 0* not used

0* reserved, must be set to logic 0

7 to 3 -

R/W

2

-

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Table 47. CLB_STDBY register (address 30h) bit description …continued

Legend: * = default value.

Bit

Symbol Access Value

Description

1

STDBY R/W

When STDBY is set to logic 1, the chip enters in Standby

mode, and its power consumption is reduced. The IF AGC pin

is set to high-ohmic. The default value is logic 0, which means

that the chip is active.

0*

1

Normal mode

Standby mode

0

CLB

R/W

This signal clears the TDA8296 through the I²C-bus interface

(software reset). To activate the reset, just write CLB = 0. This

software reset will not affect the content of the registers.

0

activate soft reset

normal operation

1*

9.3.15 ADC control

In the TDA8296 a 12-bit ADC is implemented sampling with a 54 MHz clock (27 MHz

optional).

Table 48. ADC_CTL register (address 33h) bit description

Legend: * = default value.

Bit

Symbol

Access Value Description

7 to 4 -

R/W

0010* reserved, must be set to logic 0010

3

DCIN

The input signal of the ADC can be either AC coupled by

means of two capacitors or connected directly to the inputs

(DC coupled).

0*

1

AC coupling

DC coupling

2

1

-

R/W

1*

reserved, must be set to logic 1

SLEEP

When HIGH, SLEEP sets the ADC into its Sleep mode. Both

bias current and clock are switched off. In this mode, the

current consumption is reduced by a factor of 6. The

reference circuit will remain active in order to guarantee a fast

recovery from Sleep mode.

0*

1

Normal mode

ADC Sleep mode

0

PD_ADC R/W

When HIGH, PD_ADC sets the ADC into its Power-down

mode. All internal currents are switched off. In this mode, the

current consumption is near zero (leakage current only).

0*

1

Normal mode

ADC Power-down mode

Table 49. ADC_CTL_2 register (address 34h) bit description

Legend: * = default value.

Bit

Symbol

Access Value

Description

7 to 3

-

R/W

0000 0* not used

2 and 1 -

10*

reserved, must be set to logic 10

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Table 49. ADC_CTL_2 register (address 34h) bit description …continued

Legend: * = default value.

Bit

Symbol

Access Value

Description

0

AD_SR54M

R/W

0

AD_SR54M sets the ADC sampling rate

ADC sampling rate 27 MHz; first decimation filter is

bypassed

1*

ADC sampling rate 54 MHz

001aan682

5

amplitude

response

(dB)

0

(1)

(2)

-5

-10

-15

-20

0

2

4

6

8

10

12

14

frequency (MHz)

(1) ADC sample rate 27 MHz

(2) ADC sample rate 54 MHz

ADC sample rate of 54 MHz recommended for optimum aliasing suppression. Internal low IF tilt in

54 MHz mode can be compensated by CVBS_EQ[7:0] set to −2 dB

Fig 16. Internal low IF frequency response in front of the VIF demodulator

9.3.16 Video and sound DAC control

The TDA8296 implements two 10-bit DAC modules (CVBS and sound outputs) which are

sampled by a 108 MHz clock. A reference module derives biasing currents for the two

DACs.

Table 50. VIDEODAC_CTL register (address 35h) bit description

Legend: * = default value.

Bit

Symbol

Access Value

Description

7

-

R/W

0*

reserved, must be set to logic 0

6 to 1 B_DA_V[5:0] R/W

B_DA_V modifies between 50% to 100% the full scale

DAC output current. See Section 13.3.

00 0000

11 1111*

minimum current setting

maximum current setting

0

PD_DA_V

R/W

When HIGH, PD_DA_V sets the video DAC into its

Power-down mode.

0*

1

Normal mode

video DAC Power-down mode

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Table 51. AUDIODAC_CTL register (address 36h) bit description

Legend: * = default value.

Bit

Symbol

Access Value

Description

7

-

R/W

0*

reserved, must be set to logic 0

6 to 1 B_DA_S[5:0] R/W

B_DA_S modifies between 50% to 100% the full scale

DAC output current. See Section 13.3.

00 0000*

11 1111

minimum current setting

maximum current setting

0

PD_DA_S

R/W

When HIGH, PD_DA_S sets the sound DAC into its

Power-down mode.

0*

1

Normal mode

sound DAC Power-down mode

Table 52. DAC_REF_CLK_CTL register (address 37h) bit description

Legend: * = default value.

Bit

Symbol

Access Value

Description

7

-

R/W

0*

not used

6 to 1 -

10 0000* reserved, must be set to logic 10 0000

0

PD_DA_REF R/W

When HIGH, PD_DA_REF sets the reference module

into its Power-down mode.

0*

1

Normal mode

Power-down mode

9.3.17 Clock generation (PLL and crystal oscillator)

The TDA8296 implements a crystal oscillator which can be used either in Slave mode or

in Oscillator mode (see Section 13.7), and a multipurpose PLL which receives XIN as

input clock, and delivers the system clock of the IC (108 MHz).

Table 53. PLL_REG07, PLL_REG08, PLL_REG09 and PLL_REG10 register (address 3Fh to 42h) bit description

Legend: * = default value.

Address Register

Bit

Symbol

-

Access Value Description

3Fh

PLL_REG07 7

R/W

0*

not used

6

NSEL7

It programs bit 7 of the N parameter (N = NSEL + 1). N is the

PLL pre-divider. See below for bits NSEL[6:0].

5 to 0 -

R/W

00h* reserved, must be set to 00h

40h

41h

PLL_REG08 7 to 0 MSEL[7:0] R/W

1Ah* It programs the M parameter (M = MSEL + 1). M is the PLL

feedback-divider.

PLL_REG09 7 to 1 NSEL[6:0] R/W

01h* It programs bits 6 to 0 of the N parameter (N = NSEL + 1).

N is the PLL pre-divider.

0

-

R/W

0*

reserved, must be set to logic 0

42h

PLL_REG10 7 to 5 -

000* reserved, must be set to logic 000

4 to 0 PSEL[4:0] R/W

01h* It programs the P parameter (P = PSEL + 1). P is the PLL

post-divider.

The PLL output frequency (108 MHz) can be calculated with the following formula:

f_VCO

f_clk(o)(PLL)= ------------ = -------------

2 × P N × P

f_i× M

(1)

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Digital global standard low IF demodulator for analog TV and FM radio

For optimum performances, the following relations must be respected:

• 275 MHz ≤ f_VCO≤ 550 MHz

• 4 kHz ≤ f_i/ N ≤ 150 MHz

9.3.18 GPIOs

In the TDA8296, three general purpose input/outputs are implemented.

Table 54. GPIOREG_0 register (address 44h) bit description

Legend: * = default value.

Bit

Symbol

Access Value Description

7 to 4 GP1_CF[3:0] R/W

It determines how the general purpose pin GPIO1 is

configured.

0000

0001*

0011

The GPIO1 pin is in Input mode. The input value is

stored in GP1_VAL.

The GPIO1 pin is in Open-drain mode. The output

value is determined by GP1_VAL.

The GPIO1 pin is in Output mode. The PLL output

clock divided by two is delivered.

0100

to

1011

The GPIO1 pin is in Output mode. HVPLL signals are

delivered. The HVPLL signal is chosen according to

Table 56.

XXXX

Don’t care if I2CSW_EN = 1. Then the pad is

configured as I²C-bus feed-through like described in

Table 55.

3 to 0 GP0_CF[3:0] R/W

It determines how the general purpose pin GPIO0 is

configured.

0000

0001

0011

The GPIO0 pin is in Input mode. The input value is

stored in GP0_VAL.

The GPIO0 pin is in Open-drain mode. The output

value is determined by GP0_VAL.

The GPIO0 pin is in Output mode. The PLL output

clock divided by two is delivered.

0100

to

1011*

The GPIO0 pin is in Output mode. HVPLL signals are

delivered. The HVPLL signal is chosen according to

Table 56.

Table 55. GPIOREG_1 register (address 45h) bit description

Legend: * = default value.

Bit

7

Symbol

Access Value Description

I2CSW_EN R/W

I2CSW_ON R/W

1*

0*

When I2CSW_EN = 1, GPIO1 and GPIO2 are

configured as an I²C-bus feed-through independently of

the GP1_CF and GP2_CF value. When

6

I2CSW_ON = 0, the feed-through switch is open, and

GPIO1 and GPIO2 are in 3-state. When the switch is

closed (I2CSW_ON = 1), the I²C-bus clock and data

signals (SCL and SDA) are available on the GPIO1 and

GPIO2 pins.

5 and 4 -

R/W

00*

not used

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Table 55. GPIOREG_1 register (address 45h) bit description …continued

Legend: * = default value.

Bit

Symbol

Access Value Description

3 to 0

GP2_CF[3:0] R/W

It determines how the general purpose pin GPIO2 is

configured.

0000

0001*

0011

The GPIO2 pin is in Input mode. The input value is

stored in GP2_VAL.

The GPIO2 pin is in Open-drain mode. The output

value is determined by GP2_VAL.

The GPIO2 pin is in Output mode. The PLL output

clock divided by two is delivered.

0100

to

1011

The GPIO2 pin is in Output mode. HVPLL signals are

delivered. The HVPLL signal is chosen according to

Table 56.

XXXX

Don’t care if I2CSW_EN = 1. Then the pad is

configured as I²C-bus feed-through.

Table 56. HVPLL signal configuration

HVPLL_BUS bit

Signal

GPx_CF[3:0] = 1011

GPx_CF[3:0] = 1010

GPx_CF[3:0] = 1001

GPx_CF[3:0] = 1000

GPx_CF[3:0] = 0111

GPx_CF[3:0] = 0110

GPx_CF[3:0] = 0101

GPx_CF[3:0] = 0100

V_SYNC

H_SYNC

NOISE_DET

MAC_DET

FIDT

V_LOCK

F_H_LOCK

N_H_LOCK

Table 57. GPIOREG_2 register (address 46h) bit description

Legend: * = default value.

Bit

Symbol

Access Value Description

7 to 5

-

R/W

000*

00*

1*

reserved, must be set to logic 000

not used

4 and 3 -

2

1

0

GP2_VAL

GP2_VAL controls the value of the pin GPIO2 when

GP2_CF[3:0] = 0001. When GP2_CF[3:0] = 0000,

GPIO2 is an input pin which value can be read

through the I²C-bus stored in GP2_VAL.

GP1_VAL

GP0_VAL

R/W

1*

GP1_VAL controls the value of the pin GPIO1 when

GP1_CF[3:0] = 0001. When GP1_CF[3:0] = 0000,

GPIO1 is an input pin which value can be read

through the I²C-bus stored in GP1_VAL.

GP0_VAL controls the value of the pin GPIO0 when

GP0_CF[3:0] = 0001. When GP0_CF[3:0] = 0000,

GPIO0 is an input pin which value can be read

through the I²C-bus stored in GP0_VAL.

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9.3.19 Special equalizer functions for group delay and video (CVBS)

To realize special customer demands or accurate compensation of the tuner influence,

the TDA8296 has got freely programmable equalizers for the group delay and video

(CVBS) response.

In Table 58 the programming of the group delay equalizer is explained, in Table 60 the

programming of the video equalizer. For each equalizer type an example is given.

Table 58. GD_EQ_SECTx_C1 and GD_EQ_SECTx_C2 (x = 1 to 4) register (address 4Bh to

52h) bit description

Legend: * = default value^[1]

.

Address Register

Bit

Symbol

Access Value

4Bh

4Ch

4Dh

4Eh

4Fh

50h

51h

52h

GD_EQ_SECT1_C1

GD_EQ_SECT1_C2

GD_EQ_SECT2_C1

GD_EQ_SECT2_C2

GD_EQ_SECT3_C1

GD_EQ_SECT3_C2

GD_EQ_SECT4_C1

GD_EQ_SECT4_C2

7 to 0

GD_EQ_SECT1_C1[7:0]

GD_EQ_SECT1_C2[7:0]

GD_EQ_SECT2_C1[7:0]

GD_EQ_SECT2_C2[7:0]

GD_EQ_SECT3_C1[7:0]

GD_EQ_SECT3_C2[7:0]

GD_EQ_SECT4_C1[7:0]

GD_EQ_SECT4_C2[7:0]

R/W

00h*

[1] Don’t care if GD_EQ_CTRL = 0; see Table 23.

Remark: The group delay equalizer consists of four cascaded all-pass Infinite Impulse

Response (IIR) sections of second order (8th order in sum). The transfer function H(z) of

one section is as follows, while the sampling rate is 13.5 MHz:

b₂+ b₁× z^–1+ z^–2

H(z) = -----------------------------------------------------

1 + b₁× z^–1+ b₂× z^–2

GD_EQ_SECTx_C1 and GD_EQ_SECTx_C2 (x = 1 to 4) are defining the linear and

square coefficient of each section, i.e. GD_EQ_SECTx_C1 = b₁and

GD_EQ_SECTx_C2 = b₂. The coefficients are in signed fixed-point format, the

representation is in two’s complement. There is one sign bit, one magnitude bit and

6 fractional bits. Each fractional bit represents an inverse power of two, so that the highest

value for a coefficient is 2⁰+ 2⁻¹+ ... + 2⁻⁶= 2¹− 2⁻⁶= 1.984375. The binary

representation for this value is 01.11 1111 (= 7Fh) and all bits except the sign bit are

logic 1. As two’s complement is chosen, the lowest value for a coefficient is −2, which is

10.00 0000 (= 80h) in the binary representation. So, for the lowest possible value, only the

sign bit is logic 1. The shown default values for GD_EQ_SECTx_C1 and

GD_EQ_SECTx_C2 (x = 1 to 4) implement a flat equalizer response.

Example of Table 58: If e.g. a flat group delay response up to 4 MHz and −70 ns from

4.43 MHz to 5 MHz on the CVBS signal is wanted, one might realize a characteristic like

shown in Figure 17.

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001aaj779

0.65

t

d(grp)

(μs)

0.62

0.59

0.56

0.53

0

1

2

3

4

5

f (MHz)

Fig 17. Example for the programmable group delay equalizer

The coefficients used in the above filter are according to Table 59. To get any other filter

characteristic use a professional filter tool to determine the coefficients.

Table 59. Coefficients used in group delay equalizer example

Symbol

Value

B9h

16h

GD_EQ_SECT1_C1[7:0]

GD_EQ_SECT1_C2[7:0]

GD_EQ_SECT2_C1[7:0]

GD_EQ_SECT2_C2[7:0]

GD_EQ_SECT3_C1[7:0]

GD_EQ_SECT3_C2[7:0]

GD_EQ_SECT4_C1[7:0]

GD_EQ_SECT4_C2[7:0]

DBh

17h

0Eh

19h

47h

1Ch

Table 60. CVBS_EQ_COEFx_LOW and CVBS_EQ_COEFx_HIGH (x = 0 to 5) register

(address 57h to 62h) bit description

Legend: * = default value^[1]

.

Address Register

Bit

Symbol

Access Value

57h

58h

CVBS_EQ_COEF0_LOW 7 to 0

CVBS_EQ_COEF0_HIGH 7 to 4

3 to 0

CVBS_EQ_COEF0[7:0]

-

R/W

00h*

0000*

0h*

CVBS_EQ_COEF0[11:8]

CVBS_EQ_COEF1[7:0]

-

59h

5Ah

CVBS_EQ_COEF1_LOW 7 to 0

CVBS_EQ_COEF1_HIGH 7 to 4

3 to 0

00h*

0000*

0h*

CVBS_EQ_COEF1[11:8]

CVBS_EQ_COEF2[7:0]

-

5Bh

5Ch

CVBS_EQ_COEF2_LOW 7 to 0

CVBS_EQ_COEF2_HIGH 7 to 4

3 to 0

00h*

0000*

0h*

CVBS_EQ_COEF2[11:8]

CVBS_EQ_COEF3[7:0]

5Dh

CVBS_EQ_COEF3_LOW 7 to 0

00h*

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Table 60. CVBS_EQ_COEFx_LOW and CVBS_EQ_COEFx_HIGH (x = 0 to 5) register

(address 57h to 62h) bit description …continued

Legend: * = default value^[1]

.

Address Register

Bit

Symbol

Access Value

5Eh

CVBS_EQ_COEF3_HIGH 7 to 4

3 to 0

-

R/W

0000*

0h*

CVBS_EQ_COEF3[11:8]

CVBS_EQ_COEF4[7:0]

-

5Fh

60h

CVBS_EQ_COEF4_LOW 7 to 0

CVBS_EQ_COEF4_HIGH 7 to 4

3 to 0

00h*

0000*

0h*

CVBS_EQ_COEF4[11:8]

CVBS_EQ_COEF5[7:0]

-

61h

62h

CVBS_EQ_COEF5_LOW 7 to 0

CVBS_EQ_COEF5_HIGH 7 to 4

3 to 0

00h*

0000*

4h*

CVBS_EQ_COEF5[11:8]

[1] Don’t care if CVBS_EQ_CTRL = 0; see Table 32.

Remark: The overall video (CVBS) equalizer is a symmetric FIR filter with 11 taps. Due to

the symmetry the group delay is constant (linear phase). The transfer function is as

follows, while the sampling rate is 13.5 MHz:

H(z) = h₀+ h₁× z^–1+ h₂× z^–2+ h₃× z^–3+ h₄× z^–4+ ... + h₁₀× z^–10

Please note that because of the symmetry h₀= h₁₀, h₁= h₉, h₂= h₈, h₃= h₇and h₄= h₆.

The mid coefficient h₅is only present once. CVBS_EQ_COEFx (x = 0 to 5) are defining

the coefficients, i.e. CVBS_EQ_COEF0 = h₀= h₁₀, CVBS_EQ_COEF1 = h₁= h₉,

CVBS_EQ_COEF2 = h₂= h₈, CVBS_EQ_COEF3 = h₃= h₇,

CVBS_EQ_COEF4 = h₄= h₆and CVBS_EQ_COEF5 = h₅. Each of the coefficients

h₀to h₅has got 12-bit quantization. The coefficients are in signed fixed-point format, the

representation is in two’s complement. There is one sign bit, one magnitude bit and

10 fractional bits. Each fractional bit represents an inverse power of two, so that the

highest value for a coefficient is 2⁰+ 2⁻¹+ ... + 2⁻¹⁰= 2¹− 2⁻¹⁰= 1.9990234375. The

binary representation for this value is 01.11 1111 1111 (= 7FFh) and all bits except the

sign bit are logic 1. As two’s complement is chosen, the lowest value for a coefficient is

−2, which is 10.00 0000 0000 (= 800h) in the binary representation. So, for the lowest

possible value, only the sign bit is logic 1. The shown default values for

CVBS_EQ_COEFx (x = 0 to 5) implement a flat equalizer response.

Example of Table 60: If an attenuation of around 1 dB for video frequencies greater than

2 MHz is wanted, the following figure (see Figure 18) can be implemented.

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001aaj780

0

α

resp(f)

(dB)

−0.4

−0.8

−1.2

−1.6

−2.0

0

1

2

3

4

5

6

7

f (MHz)

Fig 18. Example for the programmable video equalizer

Table 61. Coefficients used in video equalizer example

Symbol

Value

005h

FFDh

016h

FFFh

018h

39Ch

CVBS_EQ_COEF0[11:0]

CVBS_EQ_COEF1[11:0]

CVBS_EQ_COEF2[11:0]

CVBS_EQ_COEF3[11:0]

CVBS_EQ_COEF4[11:0]

CVBS_EQ_COEF5[11:0]

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10. Limiting values

Table 62. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).^[1][2][3]

Symbol

Parameter

Conditions

Min

Max

+1.5

+4.6

+1.5

+4.6

+1.3

Unit

V

V_DDD(1V2)

V_DDDR(3V3)

digital supply voltage (1.2 V)

ring digital supply voltage (3.3 V)

−0.5

V

V_{DDA(ADC)(1V2)}ADC analog supply voltage (1.2 V)

V_{DDA(PLL)(1V2)}PLL analog supply voltage (1.2 V)

V_{DDA(DAC)(3V3)}DAC analog supply voltage (3.3 V)

V

V_i

input voltage

pins XIN, IF_POS and

IF_NEG

V

digital input pins

−0.5

+4.6

300

V

T_lead

P_tot

lead temperature

-

°C

W

°C

total power dissipation

storage temperature

junction temperature

ambient temperature

electrostatic discharge voltage

T_amb= 85 °C

-

0.5

T_stg

T_j

−40

-

+125

+85

T_amb

V_ESD

−20

all pins:

[4]

Field ind. Charge Device

Model (FCDM)

-

±1000

±4000

V

Human Body Model (HBM)

[1] Stresses above the absolute maximum ratings may cause permanent damage to the device. Exposure to absolute maximum ratings

conditions for extended periods may affect device reliability.

[2] T_jdepends on the assembly condition of the package and especially on the design of the PCB. The application mounting must be done

in such a way that the maximum junction temperature T_j(max)is never exceeded.

[3] No power sequence requirement

[4] Class IV according to EIA/JESD22-C101.

11. Thermal characteristics

Table 63. Thermal characteristics

Symbol

Parameter

Conditions

Typ

Unit

R_th(j-a)

thermal resistance from junction to

ambient

in still air

36.8

K/W

The thermal resistance depends strongly on the nature of the PCB used in the application

and on its design. The thermal resistance given in Table 63 corresponds to the value that

can be measured on a multilayer PCB (4 layers) as defined by EIA/JESD51-2. This value

is given for information only.

The junction temperature influences strongly the reliability of an IC. The PCB used in the

application contributes on a large part to the overall thermal characteristic. It must

therefore be designed to insure that the junction temperature of the IC never exceeds

T_j(max)= 125 °C at the maximum ambient temperature.

The IC has to be soldered to ground with its die-attached paddle. Plenty of vias are

recommended to remove the heat.

TDA8296

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Product data sheet

Rev. 1 — 3 March 2011

53 of 87

TDA8296

NXP Semiconductors

Digital global standard low IF demodulator for analog TV and FM radio

12. Characteristics

Table 64. Characteristics

Power supplies 3.3 V, 1.2 V; T_amb= 25 °C; PC/SC1 for L and M = 10 dB, all others 13 dB; nominal residual picture carrier of

3 % for L/L’ , 10 % for M, 10 % for B/G, 12.5 % for D/K, 20 % for I; FM/AM modulation = 54 %, 1 kHz modulation frequency;

measured in application PCB (see Figure 22 and Figure 23) with 16 MHz crystal frequency, terminated with 75 Ω (CVBS) and

1 kΩ (SSIF/audio). Operation mode set via easy programming (Section 9.3.1), otherwise stated. Low IF input signal at -3dB

full scale, input frequencies as defined under row header IF input.

Symbol

Parameter

Conditions

Min

Typ

Max Unit

Power supply

V_DD(1V2)

supply voltage (1.2 V)

supply voltage (3.3 V)

total supply current (1.2 V)

total supply current (3.3 V)

total power dissipation

digital and analog

1.1

1.2

3.3

49

1.3

V

V_DD(3V3)

3.0

3.6

V

I_DD(tot)(1V2)

I_DD(tot)(3V3)

P_tot

-

mA

mW

65

default settings; f_s= 54 MHz

at ADC; DAC application in

accordance to Figure 23

270

f_s= 54 MHz at ADC; DAC

application in accordance to

Figure 24

-

150

-

mW

Standby mode

-

5

-

8

mW

V

Digital I/Os

V_IH

HIGH-level input voltage

LOW-level input voltage

all inputs (except pin XIN);

including voltage on outputs in

3-state mode

0.7 × V_DD(3V3)

6.0

V_IL

all inputs (except pin XIN);

including voltage on outputs in

3-state mode

-

0.8

V

V_OH

HIGH-level output voltage source current 4 mA

V_DD(3V3)− 0.4 -

-

V

V_OL

LOW-level output voltage

input capacitance

sink current 4 mA

-

0.4

5

V

C_i

pF

Master clock

f_clk(o)(PLL)

Δf/f_clk

[1]

PLL output clock frequency

-

108

-

MHz

relative frequency deviation

from clock frequency

±200 10⁻⁶

Reference frequency in Slave mode

f_clk(ext)

V_i(RMS)

SR_r

external clock frequency

RMS input voltage

rising slew rate

-

16

250

-

MHz

mV

AC coupled

external clock

RMS value

on pin XIN

200

30

-

mV/ns

ps

t_jit(cc)

C_i

cycle-to-cycle jitter time

input capacitance

12.5

3

-

pF

TDA8296

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Product data sheet

Rev. 1 — 3 March 2011

54 of 87

TDA8296

NXP Semiconductors

Digital global standard low IF demodulator for analog TV and FM radio

Table 64. Characteristics …continued

Power supplies 3.3 V, 1.2 V; T_amb= 25 °C; PC/SC1 for L and M = 10 dB, all others 13 dB; nominal residual picture carrier of

3 % for L/L’ , 10 % for M, 10 % for B/G, 12.5 % for D/K, 20 % for I; FM/AM modulation = 54 %, 1 kHz modulation frequency;

measured in application PCB (see Figure 22 and Figure 23) with 16 MHz crystal frequency, terminated with 75 Ω (CVBS) and

1 kΩ (SSIF/audio). Operation mode set via easy programming (Section 9.3.1), otherwise stated. Low IF input signal at -3dB

full scale, input frequencies as defined under row header IF input.

Symbol

Parameter

Conditions

Min

Typ

Max Unit

Reference frequency in Oscillator mode (with a crystal)

f_xtal

crystal frequency

-

16

-

MHz

Δf_xtal/f_xtal

relative crystal frequency

variation

temperature, ageing and

spreading

±200 10⁻⁶

IF input

V_i(p-p)

peak-to-peak input voltage for full-scale ADC input

(0 dBFS)

0.7

0.8

0.9

V

R_i(dif)

C_i(dif)

differential input resistance

10

-

15

2

-

kΩ

differential input

capacitance

3

pF

V_i

f_i

input voltage

operational input related to

ADC full scale; all standards;

sum of all signals

−3

dBFS

input frequency

PC / SC1

M/N standard

B standard

-

5.40 / 0.90 -

6.40 / 0.90 -

6.75 / 1.25 -

7.25 / 1.25 -

6.85 / 0.35 -

6.75 / 0.25 -

1.25 / 7.75 -

MHz

G/H standard

I standard

D/K standard

L standard

L-accent standard

FM radio

1.25

-

IF selectivity

α_sup(stpb)

stop-band suppression

Hilbert filter stop-band

−60

−40

-

dB

decimation filter stop-band

[2]

notch for NSC (NPC for

L-accent standard)

Carrier recovery FPLL

B_−3dB(cl)

closed-loop −3 dB

bandwidth

ultrawide

superwide

wide

-

280

130

60

-

kHz

%

-

medium

narrow

-

30

-

15

[3]

Δf_pullin

pull-in frequency range

-

±830

117

m_over(PC)

picture carrier over

modulation index

black for L/L-accent standard;

flat field white else

115

f_step(AFC)

AFC step frequency

128 steps

13

-

kHz

TDA8296

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Product data sheet

Rev. 1 — 3 March 2011

55 of 87

TDA8296

NXP Semiconductors

Digital global standard low IF demodulator for analog TV and FM radio

Table 64. Characteristics …continued

Power supplies 3.3 V, 1.2 V; T_amb= 25 °C; PC/SC1 for L and M = 10 dB, all others 13 dB; nominal residual picture carrier of

3 % for L/L’ , 10 % for M, 10 % for B/G, 12.5 % for D/K, 20 % for I; FM/AM modulation = 54 %, 1 kHz modulation frequency;

measured in application PCB (see Figure 22 and Figure 23) with 16 MHz crystal frequency, terminated with 75 Ω (CVBS) and

1 kΩ (SSIF/audio). Operation mode set via easy programming (Section 9.3.1), otherwise stated. Low IF input signal at -3dB

full scale, input frequencies as defined under row header IF input.

Symbol

Parameter

Conditions

Min

Typ

Max Unit

IF demodulation (video equalizer in Flat mode)

B_T(tot)

total transition bandwidth

stop-band suppression

Nyquist filter; all standards

-

1

-

MHz

dB

α_sup(stpb)

−60

-

video low-pass filter (M/N,

B/G/H, I, D/K, L/L-accent

standard)

-

−60

dB

B_{video(−1dB)}

−1 dB video bandwidth

M/N standard

-

3.8

4.8

-

MHz

B/G/H, I, D/K, L/L-accent

standard

t_ripple(GDE)

group delay equalizer ripple peak value for B/G/H half,

-

20

40

ns

time

D/K half, I flat, M (FCC) full,

L/L-accent full standard

Digital IF AGC (internal loop)

[4]

B_−3dB(cl)

closed-loop −3 dB

bandwidth

negative modulation (all

standards except L/L-accent)

400

0.2

-

Hz

positive modulation

(L/L-accent standard)

t_resp

response time

±20 dB level change; video

settled within ±3 dB

negative modulation (all

standards except

L/L-accent)

-

3

-

ms

positive modulation

(L/L-accent standard)

-

100

-

ms

dB

ΔG_AGC

AGC gain range

−20

+48

Tuner IF AGC (external loop)

[5]

t_resp

response time

at 60 dBμV (RMS) PC input;

±20 dB level change; video

settled within ±3 dB

with TDA1827x;

positive modulation

-

3000

600

1.0

-

ms

kHz

with TDA1827x;

negative modulation

-

f_−3dB(lpf)

low-pass filter −3 dB

IF AGC postfilter

0.9

1.1

frequency

TDA8296

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Product data sheet

Rev. 1 — 3 March 2011

56 of 87

TDA8296

NXP Semiconductors

Digital global standard low IF demodulator for analog TV and FM radio

Table 64. Characteristics …continued

Power supplies 3.3 V, 1.2 V; T_amb= 25 °C; PC/SC1 for L and M = 10 dB, all others 13 dB; nominal residual picture carrier of

3 % for L/L’ , 10 % for M, 10 % for B/G, 12.5 % for D/K, 20 % for I; FM/AM modulation = 54 %, 1 kHz modulation frequency;

measured in application PCB (see Figure 22 and Figure 23) with 16 MHz crystal frequency, terminated with 75 Ω (CVBS) and

1 kΩ (SSIF/audio). Operation mode set via easy programming (Section 9.3.1), otherwise stated. Low IF input signal at -3dB

full scale, input frequencies as defined under row header IF input.

Symbol

Parameter

Conditions

Min

Typ

Max Unit

CVBS output

V_o(p-p)

peak-to-peak output

voltage

negative PC modulation (all

standards except L/L-accent);

75 Ω DC load; sync-white

modulation

65 %

-

0.7

1.0

-

V

nominal

115 %

0.9

-

1.1

-

positive PC modulation

(L/L-accent standard);

75 Ω DC load; sync-white

modulation

65 %

-

0.7

1.0

-

V

nominal

115 %

0.9

-

1.1

-

B_{video(−3dB)}

−3 dB video bandwidth

overall video response; CVBS

equalizer flat

all standards except M/N

M/N standard

4.7

3.8

−5

4.85

3.9

-

MHz

α_resp(f)

frequency response

video equalizer; 8 equally

spaced settings; value at

3.9 MHz

+4.5 dB

[6]

G_dif

differential gain

“ITU-T J.63 line 330”

-

1.5

5

%

ϕ_dif

differential phase

-

1.0

3

deg

V_video/V_sync

video voltage to sync

voltage ratio

video DAC application

according to Figure 23

1.9

2.33

3.0

Vsync

synchronization voltage

video DAC application

according to Figure 23

160

-

200

1

240

2

mV

%

V_stlt/V_CVBS(p-p)synchronization tilt voltage

to peak-to-peak CVBS

voltage ratio

V_ftlt/V_CVBS(p-p)frame tilt voltage to

peak-to-peak CVBS

all standards except

L/L-accent

-

1

2

3

5

%

voltage ratio

L/L-accent standard in peak

white AGC detection

[7]

ΔV_tro/V_tro

relative transient response 2T pulse

overshoot voltage variation

TDA8296

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Product data sheet

Rev. 1 — 3 March 2011

57 of 87

TDA8296

NXP Semiconductors

Digital global standard low IF demodulator for analog TV and FM radio

Table 64. Characteristics …continued

Power supplies 3.3 V, 1.2 V; T_amb= 25 °C; PC/SC1 for L and M = 10 dB, all others 13 dB; nominal residual picture carrier of

3 % for L/L’ , 10 % for M, 10 % for B/G, 12.5 % for D/K, 20 % for I; FM/AM modulation = 54 %, 1 kHz modulation frequency;

measured in application PCB (see Figure 22 and Figure 23) with 16 MHz crystal frequency, terminated with 75 Ω (CVBS) and

1 kΩ (SSIF/audio). Operation mode set via easy programming (Section 9.3.1), otherwise stated. Low IF input signal at -3dB

full scale, input frequencies as defined under row header IF input.

Symbol

Parameter

Conditions

Min

Typ

Max Unit

α_IM(blue)

intermodulation

suppression (blue)

carrier levels related to PC

sync; PC = −3.2 dB;

CC = −19.2 dB; SC = −13 dB

1.1 MHz (related to

black-to-white in RMS,

equals CC + 3.6 dB)

-

67

77

-

dB

3.3 MHz (related to CC)

α_IM(yellow)

intermodulation

suppression (yellow)

carrier levels related to PC

sync; PC = −10 dB;

CC = −19.2 dB; SC = −13 dB

1.1 MHz (related to

black-to-white in RMS,

equals CC + 3.6 dB)

-

70

-

dB

3.3 MHz (related to CC)

-

78

60

-

dB

(S/N)_w

PSRR

weighted signal-to-noise

ratio

all standards; unified

weighting filter (“ITU-T J.61”);

PC at −6 dBFS

57

power supply rejection ratio f_ripple= 70 Hz; 100 mV (p-p);

video signal: gray; level: 50 %;

TDA8296 stand alone; input

positive video modulation;

L standard; 1.2 V

-

39

47

65

37

56

-

dB

[8]

positive video modulation;

L standard; 3.3 V

negative video modulation;

B standard; 1.2 V

negative video modulation;

B standard; 3.3 V

α_sup(f)L(unw)

unwanted leakage

frequency suppression

4.8 MHz video modulation;

related to black-to-white in

10 MHz to 200 MHz band,

wanted signal (peak-to-peak)

and unwanted signal (RMS)

TDA8296

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Product data sheet

Rev. 1 — 3 March 2011

58 of 87

TDA8296

NXP Semiconductors

Digital global standard low IF demodulator for analog TV and FM radio

Table 64. Characteristics …continued

Power supplies 3.3 V, 1.2 V; T_amb= 25 °C; PC/SC1 for L and M = 10 dB, all others 13 dB; nominal residual picture carrier of

3 % for L/L’ , 10 % for M, 10 % for B/G, 12.5 % for D/K, 20 % for I; FM/AM modulation = 54 %, 1 kHz modulation frequency;

measured in application PCB (see Figure 22 and Figure 23) with 16 MHz crystal frequency, terminated with 75 Ω (CVBS) and

1 kΩ (SSIF/audio). Operation mode set via easy programming (Section 9.3.1), otherwise stated. Low IF input signal at -3dB

full scale, input frequencies as defined under row header IF input.

Symbol

Parameter

Conditions

Min

Typ

Max Unit

SSIF/mono sound output

[9]

f_o(SSIF)

SSIF output frequency

SC1 or FM radio carrier

M standard

-

4.5

5.5

6.0

6.5

5.5

-

MHz

B/G/H standard

I standard

D/K/L/L-accent standard

FM radio

V_o(SSIF)(RMS)RMS SSIF output voltage

1 kΩ DC or AC load;

no modulation;

PC / SC1 = 13 dB;

Cs = 220 pF

M standard

105

100

95

120

115

110

115

110

115

135

130

125

130

125

130

mV

B standard

G/H standard

D/K standard

I standard

100

95

L standard

L-accent standard

FM radio (single carrier)

95

100

V_o(AF)(RMS)

RMS AF output voltage

1 kΩ DC or AC load; FM;

gain 0 dB

M standard; 54 %

98

126

133

135

144

mV

modulation degree

(±13.5 kHz FM deviation

before pre-emphasis)

B, G/H, I, D/K standard;

54 % modulation degree

(±27 kHz FM deviation

before pre-emphasis)

107

L/L-accent standard; AM;

m = 54 %; gain +6 dB

158

51

176

54

196

60

mV

FM radio; 30 % modulation

degree (±22.5 kHz FM

deviation before

pre-emphasis)

[10]

high Deviation mode

-

425

-

mV

(D/K standard China);

FM deviation before

pre-emphasis ±400 kHz;

sound level setting: −12 dB

TDA8296

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Product data sheet

Rev. 1 — 3 March 2011

59 of 87

TDA8296

NXP Semiconductors

Digital global standard low IF demodulator for analog TV and FM radio

Table 64. Characteristics …continued

Power supplies 3.3 V, 1.2 V; T_amb= 25 °C; PC/SC1 for L and M = 10 dB, all others 13 dB; nominal residual picture carrier of

3 % for L/L’ , 10 % for M, 10 % for B/G, 12.5 % for D/K, 20 % for I; FM/AM modulation = 54 %, 1 kHz modulation frequency;

measured in application PCB (see Figure 22 and Figure 23) with 16 MHz crystal frequency, terminated with 75 Ω (CVBS) and

1 kΩ (SSIF/audio). Operation mode set via easy programming (Section 9.3.1), otherwise stated. Low IF input signal at -3dB

full scale, input frequencies as defined under row header IF input.

Symbol

Parameter

Conditions

Min

Typ

Max Unit

α_hr(AF)

AF headroom

before clipping; 1 kΩ DC or

AC load

M standard; related to

±25 kHz peak deviation

before pre-emphasis

-

7

-

dB

B, G/H, I, D/K standard;

related to ±50 kHz peak

deviation before

pre-emphasis

L/L-accent standard;

PC / SC1 ratio for start of

audio output clipping; AM;

m = 100 %; related to mean

SC1

-

9

-

dB

FM radio; 30 % modulation

degree related to ±22.5 kHz

peak deviation before

pre-emphasis

τ_deemp

de-emphasis time constant M/N standard (mono);

FM radio USA

-

75

50

-

μs

B/G/H, I, D/K standard;

FM radio Europe

B_−3dB

THD

−3 dB bandwidth

audio low-pass filter

L/L-accent standard

M-BTSC standard

-

30

-

kHz

%

140

0.15

-

total harmonic distortion

FM; for 50 kHz deviation

before pre-emphasis (25 kHz

for M standard)

0.3

AM; m = 80 %

-

0.5

27

50

51

1

-

%

B_AF(−3dB)

−3 dB AF bandwidth

AM

FM

20

40

kHz

dB

-

α_AM

AM suppression

of FM demodulator;

AM: f = 1 kHz; m = 54 %

referenced to 27 kHz FM

deviation

-

TDA8296

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Product data sheet

Rev. 1 — 3 March 2011

60 of 87

TDA8296

NXP Semiconductors

Digital global standard low IF demodulator for analog TV and FM radio

Table 64. Characteristics …continued

Power supplies 3.3 V, 1.2 V; T_amb= 25 °C; PC/SC1 for L and M = 10 dB, all others 13 dB; nominal residual picture carrier of

3 % for L/L’ , 10 % for M, 10 % for B/G, 12.5 % for D/K, 20 % for I; FM/AM modulation = 54 %, 1 kHz modulation frequency;

measured in application PCB (see Figure 22 and Figure 23) with 16 MHz crystal frequency, terminated with 75 Ω (CVBS) and

1 kΩ (SSIF/audio). Operation mode set via easy programming (Section 9.3.1), otherwise stated. Low IF input signal at -3dB

full scale, input frequencies as defined under row header IF input.

Symbol

Parameter

Conditions

Min

Typ

Max Unit

AF weighted

signal-to-noise ratio

via internal mono sound

demodulator;

(S/N)_w(AF)

“ITU-R BS.468-4”; FM mode

related to 27 kHz deviation

before pre-emphasis; 10 %

residual PC; SC1

black picture

52

54

-

dB

flat field white picture

6 kHz sine wave picture

250 kHz square wave

picture

crosshatch picture

color bar picture

52

54

-

dB

[11]

via internal mono sound

demodulator; (audio

gain +6 dB)“ITU-R BS.468-4”;

AM; m = 54 %; 3 % residual

PC; SC1

black picture

40

41

40

-

44

45

-

dB

flat field white picture

color bar picture

via internal mono sound

demodulator;

“ITU-R BS.468-4”;

FM Radio mode;

22.5 kHz deviation

TDA8296

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Product data sheet

Rev. 1 — 3 March 2011

61 of 87

TDA8296

NXP Semiconductors

Digital global standard low IF demodulator for analog TV and FM radio

Table 64. Characteristics …continued

Power supplies 3.3 V, 1.2 V; T_amb= 25 °C; PC/SC1 for L and M = 10 dB, all others 13 dB; nominal residual picture carrier of

3 % for L/L’ , 10 % for M, 10 % for B/G, 12.5 % for D/K, 20 % for I; FM/AM modulation = 54 %, 1 kHz modulation frequency;

measured in application PCB (see Figure 22 and Figure 23) with 16 MHz crystal frequency, terminated with 75 Ω (CVBS) and

1 kΩ (SSIF/audio). Operation mode set via easy programming (Section 9.3.1), otherwise stated. Low IF input signal at -3dB

full scale, input frequencies as defined under row header IF input.

Symbol

Parameter

Conditions

Min

Typ

Max Unit

(S/N)_w(SC1)

first sound carrier weighted via external SSIF sound

signal-to-noise ratio

demodulator in Dual mode;

“ITU-R BS.468-4”; FM mode

related to 27 kHz deviation

before pre-emphasis; 10 %

residual PC

black picture

-

58

57

58

-

dB

flat field white picture

6 kHz sine wave picture

250 kHz square wave

picture

crosshatch picture

color bar picture

-

52

58

-

dB

via SSIF sound demodulator;

“ITU-R BS.468-4”; AM;

m = 54 %; 3 % residual PC

black picture

-

44

-

dB

flat field white picture

color bar picture

(S/N)_w(SC2)

second sound carrier

weighted signal-to-noise

ratio

via external SSIF sound

demodulator in Dual mode;

“ITU-R BS.468-4”; FM mode

related to 27 kHz deviation

before pre-emphasis; 10 %

residual PC

black picture

-

56

55

51

-

dB

flat field white picture

6 kHz sine wave picture

250 kHz square wave

picture

crosshatch picture

color bar picture

-

51

56

55

-

dB

(S/N)_w

weighted signal-to-noise

ratio

FM radio; via SSIF sound

demodulator in Mono mode;

“ITU-R BS.468-4”;

22.5 kHz deviation

TDA8296

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Product data sheet

Rev. 1 — 3 March 2011

62 of 87

TDA8296

NXP Semiconductors

Digital global standard low IF demodulator for analog TV and FM radio

Table 64. Characteristics …continued

Power supplies 3.3 V, 1.2 V; T_amb= 25 °C; PC/SC1 for L and M = 10 dB, all others 13 dB; nominal residual picture carrier of

3 % for L/L’ , 10 % for M, 10 % for B/G, 12.5 % for D/K, 20 % for I; FM/AM modulation = 54 %, 1 kHz modulation frequency;

measured in application PCB (see Figure 22 and Figure 23) with 16 MHz crystal frequency, terminated with 75 Ω (CVBS) and

1 kΩ (SSIF/audio). Operation mode set via easy programming (Section 9.3.1), otherwise stated. Low IF input signal at -3dB

full scale, input frequencies as defined under row header IF input.

Symbol

Parameter

Conditions

Min

Typ

Max Unit

PSRR

power supply rejection ratio f_ripple= 70 Hz; 100 mV (p-p);

video signal: gray; level: 50 %;

TDA8296 stand alone

FM sound; 1.2 V

FM sound; 3.3 V

AM sound; 1.2 V

AM sound; 3.3 V

-

80

39

40

38

51

-

dB

[8]

α_sup(f)L(unw)

unwanted leakage

frequency suppression

related to SSIF (SC1) in

10 MHz to 200 MHz band

wanted signal (peak-to-peak)

and unwanted signal (RMS)

[1] See Section 9.3.17 for PLL setting.

[2] Standard dependent located at 6.9 MHz, 7.9 MHz, 8.3 MHz and 9.25 MHz.

[3] The pull-in range can be doubled to ±1660 kHz by I²C-bus register like described in Table 16. Then the AFC read-out has 256 steps.

[4] To counteract a fast IF level reduction, the digital IF AGC loop has a speed-up circuit for positive video modulation.

[5] In the ordinary system application, this slow response is counteracted by the fast digital IF AGC loop. ADC clipping is practically avoided

by fast-attack AGC characteristic.

[6] Graph differential gain versus temperature.

[7] HAD: 250 ns for M standard, 200 ns for others.

[8] The values given are measured with an IF AGC time constant of 5 Hz. For that, capacitor C7 in Figure 19 must be chosen 220 nF

instead of 2.2 nF. Doing so, the PSRR on 3.3 V together with the tuner can be improved.

[9] SC2 is not listed, but supported for all world standards.

[10] At high deviation mode at D/K standard, IF frequency has to be programmed, that SIF frequency is higher than 500 kHz

(default: 350 kHz).

[11] To set audio gain to +6 dB for internal sound demodulation, register 22h has to be programmed to 08h.

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TDA8296

NXP Semiconductors

Digital global standard low IF demodulator for analog TV and FM radio

13. Application information

13.1 Typical application

2

I C-bus

2

I C-bus

SDA_O

SCL_O

SDA

SCL

V_IOUTN

V_IOUTP

V-sync

CVBS

SSIF

VSYNC

AUDIO

AND

IF_POS

IF_NEG

VIDEO

DECODER

TDA1827x

(TUNER IC)

(1)

TDA8296

S_IOUTP

IF_AGC

XIN

processed

audio and video

tuner IF AGC

S_IOUTN

RSET

reference frequency

008aaa140

(1) Input filter schematics see Figure 20 or Figure 21

Fig 19. Typical application of TDA8296

13.1.1 IF input application

100 nF

47 Ω

82 Ω

39 pF

82 Ω

V

SSA(ADC)

IF_POS

IF_NEG

40

1

2

TDA8296

100 nF

47 Ω

001aam375

Fig 20. IF input application for interlacing TDA1827x

100 nF

22 Ω

82 Ω

V

SSA(ADC)

IF_POS

40

22 nF

82 Ω

1

2

68 pF

TDA8296

IF_NEG

100 nF

22 Ω

001aan141

Fig 21. IF input application

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NXP Semiconductors

Digital global standard low IF demodulator for analog TV and FM radio

13.2 Detailed application diagrams

13.2.1 Main application diagram

GND +3.3 V

+3.3 V

10 Ω

10 kΩ 10 kΩ

IF_AGC

GND

470 nF

GND

470 nF

150 kΩ

(3)

IF_POS

IF_NEG

TRST_N

SDA

1

2

3

4

5

6

7

8

9

30

GND

Low IF in

100 Ω

29

28

27

26

25

24

23

22

21

2.2 Ω

V

SCL

DDA(ADC)(1V2)

+1.2 V

2.2 Ω

V

TCK

DDD1(1V2)

GND

(2)

V

SSD2

SSD1

i.c.

GND

220 nF

2.2 Ω

TDA8296

V

DDD2(1V2)

+1.2 V

10 Ω

V

TMS

TDI

DDA(PLL)(1V2)

+1.2 V

GND

16 MHz

reference

input

100 pF

XIN

(4)

GND

TDO

RST_N

XOUT

(4)

220 nF

2.2 kΩ

V

SSA(PLL)

+3.3 V

10

100 nF

GND

Address select

Pin 19 Address

Pin 20

GND

470 nF

GND

+3.3 V

GND

84h

470 nF

GND

86h

94h

96h

+3.3 V

(1)

1 Ω

GND

V_IOUT

S_IOUT

Address

select

+3.3 V

001aam371

GND

(1) R_RSETdepends on application

(2) PCB layout dependent

(3) use of GPIO function not recommended

(4) for clock/oscillator application refer to Figure 32 and Figure 33

Fig 22. Main application diagram

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NXP Semiconductors

Digital global standard low IF demodulator for analog TV and FM radio

13.2.2 75 Ω application

This is the reference application for the data sheet characteristic.

TDA8296

11

13

14

16

17

SSIF Out

> 1 kΩ

terminated

470

pF

75

Ω

75

Ω

470

pF

75

Ω

(1)

1 kΩ

C

75 Ω

C

75 Ω

s

CVBS Out

75 Ω terminated

001aam372

(1) For C_svalue please refer to Figure 14, for characteristics Cs = 220 pF is used

Set value of B_DA_V[5:0] to 3Fh (part of register 0x35h) and value of B_DA_S[5:0] to 00h (part of

register 0x36h)

Fig 23. 75 Ω load

13.2.3 100 Ω application

TDA8296

11

13

14

16

17

SSIF Out

180

pF

180

pF

150

pF

150

pF

2 kΩ

100 Ω

001aam373

CVBS Out

Set value of B_DA_V[5:0] to 18h (part of register 0x35h) and value of B_DA_S[5:0] to 17h (part of

register 0x36h)

Fig 24. High ohmic load

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NXP Semiconductors

Digital global standard low IF demodulator for analog TV and FM radio

13.2.4 Buffer application

+5 V

47 μF

100 nF

TDA8296

11

13

14

16

17

200 Ω

560 Ω

PBSS4140U

CVBS

68 Ω

75 Ohm

(SCART)

150 Ω

PBSS2515VS

VIDEO

DECODER

150

pF

150 100

220

pF

2 kΩ

33 Ω

100 Ω

33 Ω

150 Ω

pF

Ω

001aam374

SSIF Out

Set value of B_DA_V[5:0] to 18h (part of register 0x35h) and value of B_DA_S[5:0] to 17h (part of register 0x36h)

Fig 25. Buffer application with 75 Ω load

13.2.5 Layout recommendations

18.00

SDA-T

(1)

SCL-T

47 Ω 82 Ω 39 pF

470 nF

47 Ω 82 Ω 39 pF

IF-AGC

Low-IFp

Low-IFn

SDA

SCL

100 Ω

2.2 Ω

n.c.

2.2 Ω

10 Ω

TDA8296HN

2.2 Ω

(2)

18.00

n.c.

16 MHz

470 nF

1.0 Ω

SIFp

CVBSp

001aam882

(1) Bottom layer

(2) Top layer

Fig 26. PCB pattern using circuit diagrams of Figure 20, Figure 22, Figure 23 and 16 MHz

reference from XTAL

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Product data sheet

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TDA8296

NXP Semiconductors

Digital global standard low IF demodulator for analog TV and FM radio

SDA-T

(1)

SCL-T

47 Ω 82 Ω 39 pF

470 nF

IF-AGC

Low-IFp

SDA

SCL

100 Ω

2.2 Ω

Low-IFn

2.2 Ω

10 Ω

470 nF

TDA8296HN

2.2 Ω

(2)

16 MHz-p

16 MHz-n

100 pF

10 pF 220 Ω

2.2 kΩ

470 nF

1.0 Ω

SIFp

CVBSp

001aan108

(1) Bottom layer

(2) Top layer

Fig 27. PCB pattern using circuit diagrams of Figure 20, Figure 22, Figure 23 and 16 MHz

reference from master

13.3 DAC connection

The video and sound output signals are converted from IC internal digital domain to

analog output signal domain by digital controlled current sources. therefore the Digital to

Analog Conversion (DAC) is based on controlled current sources. the current sources of

the video and sound DACs are operating in differential mode. Even though differential

mode can be used, the typical application use case is single ended. Each output of the

differential pair needs to be terminated by the same impedance to ground. The

termination impedance converts the DAC output current to signal voltage. The full scale

DAC current is defined by application resistor R_RSET(connected between pin RSET and

ground). Typical values of R_RSETare 1 kΩ and 2 kΩ. Additionally the full scale DAC

current can be adjusted between 50% and 100% via register 0x35h (bits B_DA_V[5:0])

and via register 0x36h (bits B_DA_S[5:0]).

The full scale current is application dependent and needs to be matched to the termination

(output voltage is product of DAC current and termination impedance value). The nominal

peak-peak signal voltage should not exceed 1V_pp. The sum of AC an DC signal should not

exceed 1.5V single ended.

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Product data sheet

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TDA8296

NXP Semiconductors

Digital global standard low IF demodulator for analog TV and FM radio

The following relation gives the value of the full-scale current I_FSin function of the bias

resistance value and value of B_DA_V[5:0] (part of register 0x35h) and value of

B_DA_S[5:0] (part of register 0x36h) (B_DA_V or B_DA_S):

1.216 V_RSET

----------------------------- -- -------------------------------------

1

5

64 + B_DA_V/S

I_FS

=

×

× 64

(2)

R_RSET

48

0 ≤ B_DA_V/S ≤ 63

For programming of B_DA_V see Table 50, for B_DA_S see Table 51.

001aam357

(1)

45

DAC current

[mA]

35

25

15

(2)

(3)

5

0

10

20

30

40

50

60

DAC reg (dec)

70

(1) I_{V_IOUTP}for R_RSET= 1 kΩ

(2) I_{V_IOUTP}for R_RSET= 1.5 kΩ

(3) I_{V_IOUTP}for R_RSET= 2 kΩ

Fig 28. TDA8296 calculated DAC characteristic

The DAC signal range used for CVBS and sound signal is reduced to provide headroom.

The signal headroom is shown in Figure 29 and Figure 30. The full scale DAC current

corresponds to digital input value of 1034. For the pins VIOUT_P and SIOUT_P the

corresponding signal shapes of CVBS and sound signal can be mapped linear to the full

scale DAC current. For the CVBS signal the sync level is fixed, the white level depends

also on register value CVBS_LVL[7:0]. For the sound signal the DC level is fixed.

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Product data sheet

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TDA8296

NXP Semiconductors

Digital global standard low IF demodulator for analog TV and FM radio

10 bit

DAC

input

relative

numbers

(%)

150

1023

(2)

120

818

100 %

20

136

(1)

time

001aam628

(1) Sync level

(2) White level (also dependent on CVBS_LVL[7:0] at address 1Eh)

Fig 29. Internal CVBS signal in front of video DAC (typical characteristic)

10 bit

relative

DAC

input

numbers

(%)

100

1023

78

50

22

799

512

225

56 %

time

001aam629

Fig 30. Internal SSIF signal in front of sound DAC (typical characteristic, also dependent

on SSIF_LVL[7:0] at address 23h)

Application hints for DAC supply: it is required to use de-coupling capacitors at

V

_{DDA(DAC1)(3V3)}and V_{DDA(DAC2)(3V3)}supplies of > 100nF. A decoupling capacitor at pin

RSET is not allowed. The component R_RSETshould be placed close to the chip.

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TDA8296

NXP Semiconductors

Digital global standard low IF demodulator for analog TV and FM radio

13.4 ADC connection

The input signals of the ADC (IF_POS and IF_NEG) can be either AC coupled by means

of two capacitors or connected directly to the inputs (DC coupled). In case of AC coupling,

the DCIN bit (see Table 48) should be set to logic 0, which enables the internal resistive

dividers between V_{DDA(ADC)(1V2)}and V_SSD1to take care of the correct DC biasing of the

input signals.

In case the input signal is DC coupled, the input resistor network can be switched off by

setting the DCIN bit to logic 1. When using the ADC in this mode, the Common mode level

of the input signal should be at (0.5 / 1.2) × V_{DDA(ADC)(1V2)}± 200 mV.

Please note that during power-down the DC biasing network at the input will be switched

off in order to reduce current consumption. During Sleep mode however the resistor

network will remain active.

13.5 Reset operation

13.5.1 Hardware reset

minimum width at LOW is 4 × T

XIN

RST_N

XIN

T

XIN

the TDA8296 enters

immediately in its reset mode

TDA8296 normal operation

starts after 4 falling edges of XIN

008aaa144

Fig 31. Hardware reset operation

After a hardware reset, the registers are set to default (power-on reset values) according

to Table 9. M/N standard is the default standard.

13.5.2 Software reset

A software reset can be done each time something has been programmed. The software

reset does not affect the content of the registers but clears the flip-flops in the design. For

the activation of the software reset see Table 47 bit CLB.

13.6 Application hints

The DAC application can be adapted to a wide range of application needs. The data sheet

describes 3 different use cases as shown in Figure 23 to Figure 25.

The default application (also used for specification) is shown in Figure 23. This application

supports 75 Ω DC termination for the video CVBS and > 1 kΩ AC/DC termination for the

SSIF or mono audio sound signal. This application is e.g. preferred for device evaluation.

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Product data sheet

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TDA8296

NXP Semiconductors

Digital global standard low IF demodulator for analog TV and FM radio

In applications, where the impedance of the CVBS termination is high (e.g. >1 kΩ), which

is normally the case with audio/video processor, the video and sound DAC can operate

with significant lower current. An application proposal (which leads to reduced power

consumption) is shown in Figure 24.

For application requirements, where both, connections to audio/video processor (with

input impedance >1 kΩ) and 75 Ω termination (e.g. to SCART output), are needed in

parallel, a buffer application can be used as sown in Figure 25).

13.7 Crystal connection

The typical crystal frequency value is 16 MHz. The values of the passive components

depend on crystal manufacturer. The oscillator can be set in two configurations depending

on the origin of the crystal. Figure 32 describes the case of an crystal shared with the

tuner and the TDA8296 (Slave mode), Figure 33 the case of an crystal dedicated to the

TDA8296 (Oscillator mode).

TDA8296

R

bias

R

bias

XIN

XOUT

C2

XTAL

XIN

XOUT

100 nF

C1

clock signal

from tuner

n.c.

GND

008aaa143

008aaa142

Slave mode

Oscillator mode

Fig 32. Reference clock application

Fig 33. Oscillator application

In Oscillator mode, only a crystal and the load capacitances C1 and C2 need to be

connected externally since the feedback resistance is integrated on chip. For an accurate

time reference it is advised to use the load capacitors as specified in Table 65. C_Lis the

typical load capacitance of the crystal and is usually specified by the crystal manufacturer.

Table 65. Crystal parameters together with external components

Fundamental

oscillation

frequency

Crystal load

capacitance

C_L(xtal)(pF)

Crystal series

resistance

R_s(xtal)(Ω)

External load capacitors

C1 (pF)

C2 (pF)

1 MHz to 5 MHz

10

20

30

< 300

< 200

< 100

18

39

56

18

39

56

18

39

56

18

39

56

5 MHz to 10 MHz 10

20

30

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TDA8296

NXP Semiconductors

Digital global standard low IF demodulator for analog TV and FM radio

Table 65. Crystal parameters together with external components …continued

Fundamental

oscillation

frequency

Crystal load

capacitance

C_L(xtal)(pF)

Crystal series

resistance

R_s(xtal)(Ω)

External load capacitors

C1 (pF)

C2 (pF)

10 MHz to

15 MHz

10

20

10

< 160

< 60

< 80

18

39

18

39

18

15 MHz to

20 MHz

13.8 Alternative ADC sampling rates

In combination with a tuner front-end an alternative ADC sampling rates could be

necessary. Please refer to Table 66

The default register setting is adapted to 16 MHz reference frequency (either from crystal

or external source) and a nominal f_ADC= 54 MHz. In case of crosstalk of clock related

signals (e.g. n × 54 MHz) into the RF input of connected tuner circuit, the potential

disturbance of the wanted TV channel can be avoided by switching to the alternative

ADC clock frequencies of 50.75 MHz or 57.25 MHz.

Table 66. Alternative ADC clocks

Frequencies

ADC SR

50.75 MHz

101.50 MHz

16.00 MHz

54.00 MHz

108.00 MHz

16.00 MHz

57.25 MHz

114.50 MHz

16.00 MHz

Clock PLL

Xtal frequency

Divider

M

203

16

2

27

2

229

16

2

N

P

2

Registers

Register 2Bh

Register 38h

Register 3Eh

Register 3Fh

Register 40h

Register 41h

01h

23h

63h

01h

CAh

1Eh

61h

01h

23h

63h

01h

1Ah

02h

61h

02h

23h

63h

01h

E4h

1Eh

61h

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TDA8296

NXP Semiconductors

Digital global standard low IF demodulator for analog TV and FM radio

14. Test information

14.1 Boundary scan interface (“IEEE Std. 1149.1”)

The TDA8296 implements a boundary scan architecture to allow access to, and control of,

board test support features within integrated circuits through a TAP. The TAP controller is

a synchronous state machine that controls the sequence of operations on the TAP

circuitry when the TMS signal changes. All state transitions occur on the basis of the TMS

value on the rising edge of TCK. The instruction register is a shift register based design. It

decodes the test to be performed and/or the test data register to be accessed. The

instructions are shifted into the register through the TDI and are latched as the current

instruction at the completion of the shifting process. The TDA8296 boundary scan

architecture includes: a TAP controller, a scannable instruction register and three

scannable test data registers: a boundary scan register, a device ID register, and a

bypass register.

The supported instructions are: EXTEST, IDCODE, SAMPLE, INTEST, CLAMP, HIGHZ

and BYPASS.

The boundary scan register is composed of 16 cells (see Table 67). Each cell is

associated either to an input pad, an output pad, a bidirectional pad or to the bidirectional

or 3-state command itself. All cells are of ‘observe and control’ type.

The device ID register is a 32-bit identification register that is included in the scan register

itself and contains the ID number. It is a fixed value that identifies the chip.

ID number structure is:

ID version [3:0] = 1h

ID part number [15:0] = 224Ch

ID manufacturer [11:1] = 015h

ID mandatory [0] = 1h

IDCODE [31:0] = 1224 C02Bh

When the boundary scan function is not used, please connect the four dedicated input

pins (TRST_N, TCK, TDI and TMS) to GND.

TDA8296

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TDA8296

NXP Semiconductors

Digital global standard low IF demodulator for analog TV and FM radio

BOUNDARY

SCAN

REGISTER

DEVICE ID

REGISTER

MUX

BYPASS

REGISTER

control

MUX

TDO

FF

INSTRUCTION

DECODE

TDI

INSTRUCTION

REGISTER

TMS

TCK

TEST

ACCESS

PORT

select

3-state enable

CONTROLLER

TRST_N

001aac078

Fig 34. Boundary scan block diagram

Table 67. Boundary scan register list

Pad signal

Chain position

Pad type

Bidir

Ctrl

Scan type

Control signal

U1.vagc_cmd

U1.gpio0_cmd

U1.gpio1_cmd

U1.gpio2_cmd

U1.sda_cmd

-

IF_AGC

[1]

control/observe

[2]

GPIO0

GPIO1

GPIO2

SDA

[3]

Bidir

Ctrl

[4]

[5]

Bidir

Ctrl

[6]

[7]

Bidir

Ctrl

[8]

[9]

Bidir

Ctrl

[10]

[11]

[12]

[13]

[14]

[15]

[16]

SCL

input

Ctrl

RST_N

SADDR1

-

U1.saddr1_cmd

U0.saddr1_cmd

Bidir

Ctrl

SADDR0

Bidir

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Product data sheet

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TDA8296

NXP Semiconductors

Digital global standard low IF demodulator for analog TV and FM radio

Table 68. Boundary scan electrical characteristics

Symbol Parameter

Conditions

TCK

Min

25

0

Typ

Max

Unit

ns

T_cy

t_su

cycle time

set-up time

hold time

-

TDI and TMS

-

ns

t_h

4

-

ns

t_d(TDO)

delay time on pin TDO on 50 pF

-

12

ns

T

cy

TCK

t

su

t

h

TDI, TMS

TDO

t

d

001aac079

Fig 35. Boundary scan timing diagram

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TDA8296

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Digital global standard low IF demodulator for analog TV and FM radio

15. Package outline

HVQFN40: plastic thermal enhanced very thin quad flat package; no leads;

40 terminals; body 6 x 6 x 0.85 mm

SOT618-1

D

B

A

terminal 1

index area

A

E

1

c

detail X

C

e

1

y

1/2 e

e

v

M

C

b

C

A

B

1

11

20

w

L

21

10

e

E

h

2

1/2 e

1

30

terminal 1

index area

40

31

D

X

h

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

A

(1)

UNIT

A

b

c

E

e

2

y

D

E

L

v

w

y

1

h

1

h

max.

0.05 0.30

0.00 0.18

6.1

5.9

4.25

3.95

6.1

5.9

4.25

3.95

0.5

0.3

mm

0.05 0.1

1

0.2

0.5

4.5

0.1

0.05

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

01-08-08

02-10-22

SOT618-1

- - -

MO-220

- - -

Fig 36. Package outline SOT618-1 (HVQFN40)

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TDA8296

NXP Semiconductors

Digital global standard low IF demodulator for analog TV and FM radio

16. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

16.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

16.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

• Board specifications, including the board finish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

16.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath specifications, including temperature and impurities

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Digital global standard low IF demodulator for analog TV and FM radio

16.4 Reflow soldering

Key characteristics in reflow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to

higher minimum peak temperatures (see Figure 37) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accordance with

Table 69 and 70

Table 69. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)

Volume (mm³)

< 350

235

≥ 350

220

< 2.5

≥ 2.5

220

Table 70. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 37.

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Digital global standard low IF demodulator for analog TV and FM radio

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 37. Temperature profiles for large and small components

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

17. Abbreviations

Table 71. Abbreviations

Acronym

ADC

AFC

AGC

CC

Description

Analog-to-Digital Converter

Automatic Frequency Control

Automatic Gain Control

Color Carrier

CMOS

CORDIC

CVBS

DAC

DTO

DVD

FIR

Complementary Metal-Oxide Semiconductor

COordinate Rotation DIgital Computer

Color Video Blanking Signal

Digital-to-Analog Converter

Digitally Tuned Oscillator

Digital Versatile Disc

Finite Impulse Response

Frequency Phase-Locked Loop

Full Scale

FPLL

FS

GPIO

H/V

General Purpose Input Output

Horizontal and Vertical

HAD

IC

Half Amplitude Duration

Integrated Circuit

ID

IDentification

IF

Intermediate Frequency

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Table 71. Abbreviations …continued

Acronym

Description

NPC

NSC

PC

Neighbor Picture Carrier

Neighbor Sound Carrier

Picture Carrier

PCB

PLL

Printed-Circuit Board

Phase-Locked Loop

POR

PWM

QSS

SAW

SC

Power-On Reset

Pulse Width Modulation

Quasi Split Sound

Surface Acoustic Wave

Sound Carrier

SCART

Syndicat des Constructeurs d'Appareils Radiorécepteurs et Téléviseurs

Radio and Television Receiver Manufacturers' Association

Surface Mounted Device

Second Sound Intermediate Frequency

Test Access Port

SMD

SSIF

TAP

VITS

Vertical Interval Test Signal

18. Revision history

Table 72. Revision history

Document ID

Release date

20110303

Data sheet status

Change notice

Supersedes

TDA8296 v.1

Product data sheet

-

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19. Legal information

19.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

malfunction of an NXP Semiconductors product can reasonably be expected

19.2 Definitions

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

19.3 Disclaimers

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

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Digital global standard low IF demodulator for analog TV and FM radio

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

19.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

I²C-bus — logo is a trademark of NXP B.V.

Silicon Tuner — is a trademark of NXP B.V.

20. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

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Digital global standard low IF demodulator for analog TV and FM radio

21. Tables

Table 1. Quick reference data . . . . . . . . . . . . . . . . . . . . .3

Table 2. Ordering information . . . . . . . . . . . . . . . . . . . . .5

Table 3. Pin allocation table . . . . . . . . . . . . . . . . . . . . . . .7

Table 4. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .8

Table 5. Pin type description . . . . . . . . . . . . . . . . . . . . .10

Table 6. Address format . . . . . . . . . . . . . . . . . . . . . . . . .13

Table 7. I²C-bus transfer description . . . . . . . . . . . . . . .13

Table 8. I²C-bus transfer description . . . . . . . . . . . . . . .14

Table 9. I²C-bus register reference . . . . . . . . . . . . . . . .15

Table 10. I²C-bus registers . . . . . . . . . . . . . . . . . . . . . . .18

Table 11. STANDARD register (address 00h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .23

Table 12. EASY_PROG register (address 01h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .23

Table 13. Easy programming values . . . . . . . . . . . . . . . .24

Table 14. DIV_FUNC register (address 02h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .25

Table 15. ADC_HEADR register (address 03h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .25

Table 16. PC_PLL_FUNC register (address 04h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .26

Table 17. DTO_PC_LOW, DTO_PC_MID and

DTO_PC_HIGH register

(address 09h to 0Bh) bit description . . . . . . . .26

Table 18. Values of DTO_PC per TV standard

at 54 MHz sampling frequency . . . . . . . . . . . . .27

Table 19. DTO_SC_LOW, DTO_SC_MID and

DTO_SC_HIGH register (address 0Ch to 0Eh)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .27

Table 20. Values for SSIF mode at 54 MHz sampling

frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Table 21. FILTERS_1 register (address 0Fh)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 30. CVBS_SET register (address 1Dh)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 31. CVBS_LEVEL register (address 1Eh)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 32. CVBS_EQ register (address 1Fh)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 33. SSIF_MUTE register (address 05h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 34. SOUNDSET_1 register (address 20h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 35. SOUNDSET_2 register (address 21h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 36. SOUND_LEVEL register (address 22h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 37. SSIF_LEVEL register (address 23h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 38. ADC_SAT register (address 24h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 39. AFC register (address 25h) bit description . . . 41

Table 40. Calculation of frequency deviation from AFC

value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 41. HVPLL_STAT register (address 26h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 42. D_IF_AGC_STAT register (address 27h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 43. T_IF_AGC_STAT register (address 28h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 44. ALT_FILT_COEF register (address 2Bh)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 45. SSIF_AGC_STAT register (address 2Dh)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 46. IDENTITY register (address 2Fh)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .28

Table 22. FILTERS_2 register (address 10h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 47. CLB_STDBY register (address 30h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 48. ADC_CTL register (address 33h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 49. ADC_CTL_2 register (address 34h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 50. VIDEODAC_CTL register (address 35h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 51. AUDIODAC_CTL register (address 36h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 52. DAC_REF_CLK_CTL register

bit description . . . . . . . . . . . . . . . . . . . . . . . . .30

Table 23. GRP_DELAY register (address 11h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .31

Table 24. D_IF_AGC_SET_1 register (address 12h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .32

Table 25. D_IF_AGC_SET_2 register (address 13h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .32

Table 26. T_IF_AGC_SET register (address 15h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .32

Table 27. T_IF_AGC_LIM register (address 16h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 28. T_IF_AGC_FORCE register (address 17h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 29. V_SYNC_DEL register (address 1Ch)

(address 37h) bit description . . . . . . . . . . . . . . 46

Table 53. PLL_REG07, PLL_REG08, PLL_REG09

and PLL_REG10 register (address 3Fh to 42h)

continued >>

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Digital global standard low IF demodulator for analog TV and FM radio

bit description . . . . . . . . . . . . . . . . . . . . . . . . .46

Table 54. GPIOREG_0 register (address 44h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .47

Table 55. GPIOREG_1 register (address 45h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .47

Table 56. HVPLL signal configuration . . . . . . . . . . . . . . .48

Table 57. GPIOREG_2 register (address 46h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .48

Table 58. GD_EQ_SECTx_C1 and GD_EQ_SECTx_C2

(x = 1 to 4) register (address 4Bh to 52h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . .49

Table 59. Coefficients used in group delay equalizer

example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Table 60. CVBS_EQ_COEFx_LOW and

CVBS_EQ_COEFx_HIGH (x = 0 to 5) register

(address 57h to 62h) bit description . . . . . . . .50

Table 61. Coefficients used in video equalizer

example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Table 62. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .53

Table 63. Thermal characteristics . . . . . . . . . . . . . . . . . .53

Table 64. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .54

Table 65. Crystal parameters together with external

components . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Table 66. Alternative ADC clocks. . . . . . . . . . . . . . . . . . .73

Table 67. Boundary scan register list . . . . . . . . . . . . . . .75

Table 68. Boundary scan electrical characteristics . . . . .76

Table 69. SnPb eutectic process (from J-STD-020C) . . .79

Table 70. Lead-free process (from J-STD-020C) . . . . . .79

Table 71. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .80

Table 72. Revision history . . . . . . . . . . . . . . . . . . . . . . . .81

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22. Figures

Fig 1. Functional diagram of TDA8296 . . . . . . . . . . . . . .6

Fig 2. Pin configuration for HVQFN40 . . . . . . . . . . . . . . .7

Fig 3. I²C-bus Write mode . . . . . . . . . . . . . . . . . . . . . . .13

Fig 4. Examples I²C-bus Write mode. . . . . . . . . . . . . . .13

Fig 5. I²C-bus Read mode . . . . . . . . . . . . . . . . . . . . . . .14

Fig 6. Example I²C-bus Read mode . . . . . . . . . . . . . . .14

Fig 7. TDA8296 DTO_PC characteristic . . . . . . . . . . . .27

Fig 8. TDA8296 DTO_SC characteristic . . . . . . . . . . . .28

Fig 9. Video low-pass filters for sound carrier

suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Fig 10. Notch filter for adjacent sound carrier

suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Fig 11. Video low pass frequency response in

smooth roll off or low ripple mode . . . . . . . . . . . .30

Fig 12. SSIF and FM radio band-pass filters

(center frequency 5.5 MHz chosen). . . . . . . . . . .31

Fig 13. Video equalizer curves. . . . . . . . . . . . . . . . . . . . .36

Fig 14. TDA8296 SSIF characteristic versus C_S

(refer to Figure 23) typical values; termination

75 Ω and 1 kΩ in parallel . . . . . . . . . . . . . . . . . . .40

Fig 15. TDA8296 AFC characteristic . . . . . . . . . . . . . . . .42

Fig 16. Internal low IF frequency response in front

of the VIF demodulator . . . . . . . . . . . . . . . . . . . .45

Fig 17. Example for the programmable group delay

equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Fig 18. Example for the programmable video

equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Fig 19. Typical application of TDA8296 . . . . . . . . . . . . . .64

Fig 20. IF input application for interlacing TDA1827x . . .64

Fig 21. IF input application. . . . . . . . . . . . . . . . . . . . . . . .64

Fig 22. Main application diagram. . . . . . . . . . . . . . . . . . .65

Fig 23. 75 Ω load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Fig 24. High ohmic load. . . . . . . . . . . . . . . . . . . . . . . . . .66

Fig 25. Buffer application with 75 Ω load . . . . . . . . . . . . .67

Fig 26. PCB pattern using circuit diagrams

of Figure 20, Figure 22, Figure 23 and 16 MHz

reference from XTAL . . . . . . . . . . . . . . . . . . . . . .67

Fig 27. PCB pattern using circuit diagrams

of Figure 20, Figure 22, Figure 23

and 16 MHz reference from master. . . . . . . . . . .68

Fig 28. TDA8296 calculated DAC characteristic . . . . . . .69

Fig 29. Internal CVBS signal in front of video DAC

(typical characteristic) . . . . . . . . . . . . . . . . . . . . .70

Fig 30. Internal SSIF signal in front of sound DAC

(typical characteristic, also dependent on

SSIF_LVL[7:0] at address 23h) . . . . . . . . . . . . . .70

Fig 31. Hardware reset operation . . . . . . . . . . . . . . . . . .71

Fig 32. Reference clock application. . . . . . . . . . . . . . . . .72

Fig 33. Oscillator application . . . . . . . . . . . . . . . . . . . . . .72

Fig 34. Boundary scan block diagram . . . . . . . . . . . . . . .75

Fig 35. Boundary scan timing diagram . . . . . . . . . . . . . .76

Fig 36. Package outline SOT618-1 (HVQFN40) . . . . . . .77

Fig 37. Temperature profiles for large and small

components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

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All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 3 March 2011

86 of 87

TDA8296

NXP Semiconductors

Digital global standard low IF demodulator for analog TV and FM radio

23. Contents

1

2

3

4

5

6

General description. . . . . . . . . . . . . . . . . . . . . . 1

9.3.19

Special equalizer functions for group

delay and video (CVBS). . . . . . . . . . . . . . . . . 49

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Quick reference data . . . . . . . . . . . . . . . . . . . . . 3

Ordering information. . . . . . . . . . . . . . . . . . . . . 5

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 6

10

11

12

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 53

Thermal characteristics . . . . . . . . . . . . . . . . . 53

Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 54

13

13.1

13.1.1

13.2

13.2.1

13.2.2

13.2.3

13.2.4

13.2.5

13.3

13.4

13.5

13.5.1

13.5.2

13.6

Application information . . . . . . . . . . . . . . . . . 64

Typical application . . . . . . . . . . . . . . . . . . . . . 64

IF input application. . . . . . . . . . . . . . . . . . . . . 64

Detailed application diagrams . . . . . . . . . . . . 65

Main application diagram. . . . . . . . . . . . . . . . 65

75 W application . . . . . . . . . . . . . . . . . . . . . . 66

100 W application . . . . . . . . . . . . . . . . . . . . . 66

Buffer application . . . . . . . . . . . . . . . . . . . . . . 67

Layout recommendations. . . . . . . . . . . . . . . . 67

DAC connection. . . . . . . . . . . . . . . . . . . . . . . 68

ADC connection. . . . . . . . . . . . . . . . . . . . . . . 71

Reset operation . . . . . . . . . . . . . . . . . . . . . . . 71

Hardware reset . . . . . . . . . . . . . . . . . . . . . . . 71

Software reset . . . . . . . . . . . . . . . . . . . . . . . . 71

Application hints. . . . . . . . . . . . . . . . . . . . . . . 71

Crystal connection . . . . . . . . . . . . . . . . . . . . . 72

Alternative ADC sampling rates. . . . . . . . . . . 73

7

7.1

7.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 7

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8

8

Functional description . . . . . . . . . . . . . . . . . . 10

IF ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

PLL demodulator . . . . . . . . . . . . . . . . . . . . . . 10

Nyquist filter, video low-pass filter, video

and group delay equalizer, video leveling. . . . 10

Upsampler and video DAC . . . . . . . . . . . . . . . 11

SSIF/mono sound processing . . . . . . . . . . . . 11

Tuner IF AGC . . . . . . . . . . . . . . . . . . . . . . . . . 11

Digital IF AGC. . . . . . . . . . . . . . . . . . . . . . . . . 12

Clock generation. . . . . . . . . . . . . . . . . . . . . . . 12

I²C-bus control. . . . . . . . . . . . . . . . . . . . . . . . . 12

Protocol of the I²C-bus serial interface. . . . . . 12

Write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Read mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Register overview. . . . . . . . . . . . . . . . . . . . . . 15

Register description . . . . . . . . . . . . . . . . . . . . 23

Standard setting with easy programming . . . . 23

Diverse functions (includes tuner IF AGC

Pin mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

ADC headroom. . . . . . . . . . . . . . . . . . . . . . . . 25

Picture carrier PLL functions . . . . . . . . . . . . . 26

Picture and sound carrier DTO. . . . . . . . . . . . 26

Filter settings . . . . . . . . . . . . . . . . . . . . . . . . . 28

Group delay equalization . . . . . . . . . . . . . . . . 31

Digital IF AGC functions . . . . . . . . . . . . . . . . . 32

Tuner IF AGC functions . . . . . . . . . . . . . . . . . 32

V-sync adjustment . . . . . . . . . . . . . . . . . . . . . 34

CVBS settings . . . . . . . . . . . . . . . . . . . . . . . . 34

SSIF and mono sound settings . . . . . . . . . . . 36

Status registers: ADC saturation, AFC,

8.1

8.2

8.3

8.4

8.5

8.6

8.7

8.8

8.9

13.7

13.8

9

9.1

9.1.1

9.1.2

9.2

9.3

9.3.1

9.3.2

14

14.1

Test information . . . . . . . . . . . . . . . . . . . . . . . 74

Boundary scan interface

(“IEEE Std. 1149.1”). . . . . . . . . . . . . . . . . . . . 74

15

Package outline. . . . . . . . . . . . . . . . . . . . . . . . 77

16

Soldering of SMD packages. . . . . . . . . . . . . . 78

Introduction to soldering. . . . . . . . . . . . . . . . . 78

Wave and reflow soldering. . . . . . . . . . . . . . . 78

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 78

Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 79

16.1

16.2

16.3

16.4

9.3.3

9.3.4

9.3.5

9.3.6

9.3.7

9.3.8

9.3.9

9.3.10

9.3.11

9.3.12

9.3.13

17

18

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 80

Revision history . . . . . . . . . . . . . . . . . . . . . . . 81

19

Legal information . . . . . . . . . . . . . . . . . . . . . . 82

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 82

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 83

19.1

19.2

19.3

19.4

20

21

22

23

Contact information . . . . . . . . . . . . . . . . . . . . 83

Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

H/V PLL and AGC . . . . . . . . . . . . . . . . . . . . . 40

Chip identification and Standby mode . . . . . . 43

ADC control . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Video and sound DAC control . . . . . . . . . . . . 45

Clock generation (PLL and crystal oscillator) . 46

GPIOs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

9.3.14

9.3.15

9.3.16

9.3.17

9.3.18

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 3 March 2011

Document identifier: TDA8296


型号：	TDA8296HN/C1,557
厂家：	NXP
描述：	暂无描述
文件：	总87页 (文件大小：1016K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TDA8296HN/C1,557 [NXP]

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