TDA8310A [NXP]
PAL/NTSC colour processor for PIP applications; 对于PIP应用PAL / NTSC色彩处理器
| 型号： | TDA8310A |
| 厂家： | 
NXP |
| 描述： | PAL/NTSC colour processor for PIP applications |
| 文件： | 总24页 (文件大小：133K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TDA8310A
PAL/NTSC colour processor
for PIP applications
1996 Jan 25
Product specification
Supersedes data of 1995 Nov 29
File under Integrated Circuits, IC02
Philips Semiconductors
Product specification
PAL/NTSC colour processor
for PIP applications
TDA8310A
FEATURES
GENERAL DESCRIPTION
• Video switch with 2 CVBS inputs. One input can be
switched between CVBS and Y/C and the circuit can
automatically detect whether the incoming signal is
CVBS or Y/C
The TDA8310A is an alignment-free PAL/NTSC colour
processor for Picture-in-Picture (PIP) applications.
The main difference between the TDA8310 and the
TDA8310A is that the vision IF amplifier has been omitted
in the TDA8310A. Therefore, the circuit contains an input
signal selector, a PAL/NTSC colour decoder, horizontal
and vertical synchronization and an RGB/YUV switch.
• Integrated chrominance trap and bandpass filters
(automatically calibrated)
• Integrated luminance delay line
The input signal selector has 2 CVBS inputs. One of the
inputs can be switched between CVBS and Y/C and the
circuit can automatically detect whether the incoming
signal is CVBS or Y/C. The output signals for the PIP
processor are;
• Automatic PAL/NTSC decoder which can decode all
standards available in the world
• Easy interfacing with the TDA8395 (SECAM decoder)
for multistandard applications
• Horizontal PLL with an alignment-free horizontal
oscillator
Luminance signal
Colour difference signals (U and V)
Horizontal and vertical synchronization pulses.
• Vertical count-down circuit
• RGB/YUV and fast blanking switch with 3-state output
The RGB/YUV switch can select between two RGB or
YUV sources, e.g. between the PIP processor and the
SCART input signal.
and active clamping
• Low dissipation (560 mW)
• Small amount of peripheral components compared with
competition ICs.
The supply voltage for the IC is 8 V. It is available in a
52-pin SDIP package.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
DESCRIPTION
plastic shrink dual in-line package; 52 leads (600 mil)
VERSION
TDA8310A
SDIP52
SOT247-1
1996 Jan 25
2
Philips Semiconductors
Product specification
PAL/NTSC colour processor
for PIP applications
TDA8310A
QUICK REFERENCE DATA
SYMBOL
VP
PARAMETER
MIN.
7.2
TYP.
8.0
MAX.
8.8
UNIT
supply voltage (pins 19 and 41)
supply current
V
IP
−
70
1.4
mA
Input voltages
V17,20(p-p)
V16(p-p)
Vi(p-p)
CVBS/Y input voltage (peak-to-peak value)
−
−
−
1.0
0.3
−
−
V
V
V
chrominance input voltage (peak-to-peak value)
−
RGB/YUV input signal voltage amplitude
(peak-to-peak value)
1.3
Output signals
Vo(p-p)
V50(p-p)
V51(p-p)
V39
luminance output voltage (peak-to-peak value)
(B−Y) output voltage (peak-to-peak value)
(R−Y) output voltage (peak-to-peak value)
horizontal sync pulse output voltage
vertical sync pulse output voltage
−
1.4
1.33
1.05
4.0
4.0
0
−
V
1.06
0.84
−
1.6
1.26
−
V
V
V
V36
−
−
V
Gv
voltage gain of the RGB switches
−0.5
+0.5
dB
Control voltage
Vcontrol
control voltage for HUE
0
−
5.0
V
1996 Jan 25
3
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INTB
V
V
P1
19
HOUT VOUT
SAND
40
P2
DEC
21
DEC
35
PH1LF
37
DIG
BG
30
41
39
36
10
VCO
+
CONTROL
COINCIDENCE/
NOISE
DETECTOR
R1
PHASE
DETECTOR
PULSE
SHAPER
SANDCASTLE
GENERATOR
11
12
13
G1
B1
BLANK1
22, 29
33, 34
i.c.
14
VERTICAL
SYNC
SEPARATOR
HORIZONTAL/
VERTICAL
DIVIDER
SYNC
SEPARATOR
CLAMP
n.c.
8
7
6
5
R
RGB/YUV
SWITCH
G
B
DEC
FT
BLANK
15
TDA8310A
1
2
R2
G2
3
B2
52
CHROMINANCE
BANDPASS
CHROMINANCE
TRAP
FILTER
TUNING
BLANK2
4
IDENT
HUE
32
REF
CVBS
SW
28
AUTOMATIC
Y/C
DETECTOR
49
INPUT
SELECTOR
PAL/NTSC
DECODER
LUMINANCE
DELAY LINE
Y
31
20
17
9
16
47
48
46
45
44
43
42
27
26
25
24
23
50
Y
51
18
38
MGD128
PLL
XTAL4 XTAL3 XTAL2 XTAL1
R/W
COLOUR1
CVBS
CHROMA
SECAM
O
COLOUR2
LOGIC2
R Y
EXT
I
GND2
GND1 GND3
CVBS
SYST
CHROMA
B
LOGIC1
INT
SW
ahdnbok,uflapegwidt
Fig.1 Block diagram.
Philips Semiconductors
Product specification
PAL/NTSC colour processor
for PIP applications
TDA8310A
PINNING
SYMBOL PIN
DESCRIPTION
RED input 2 (PIP)
SYMBOL PIN
DESCRIPTION
HUE
28 HUE control input
R2
1
2
3
4
5
6
7
8
9
i.c.
29 internally connected (test purposes)
30 internal bias
G2
GREEN input 2 (PIP)
BLUE input 2 (PIP)
colour standard identification output
blanking output
INTB
GND2
CVBSSW
B2
31 ground 2 (0 V)
IDENT
BLANK
B
32 CVBS positive/negative modulation
control switch input
BLUE output
n.c.
33 not connected
G
GREEN output
n.c.
34 not connected
R
RED output
DECBG
VOUT
PH1LF
GND3
HOUT
SAND
VP2
35 bandgap decoupling
36 vertical sync output pulse
37 phase 1 loop filter
SYSTSW
R1
CVBS/system switch
10 RED input 1
G1
11 GREEN input 1
38 ground 3 (0 V)
B1
12 BLUE input 1
39 horizontal sync output pulse
40 sandcastle pulse output
41 supply voltage 2 (+8 V)
42 4.4336 MHz crystal
BLANK1
CLAMP
DECFT
CHROMAI
CVBSEXT
GND1
VP1
13 blanking input 1
14 clamping pulse input
15 decoupling filter tuning
16 chrominance input
XTAL1
XTAL2
XTAL3
XTAL4
PLL
43 3.5820 MHz crystal for PAL-N
44 3.5756 MHz crystal for PAL-M
45 3.5795 MHz crystal for NTSC
46 PLL colour filter
17 external CVBS/Y input
18 ground 1 (0 V)
19 supply voltage 1 (+8 V)
20 internal CVBS input
CVBSINT
DECDIG
i.c.
CHROMAO 47 chrominance output for TDA8395
21 decoupling digital supply rail
22 internally connected (test purposes)
23 crystal logic 2 input/output
24 crystal logic 1 input/output
25 colour system logic 2 input/output
26 colour system logic 1 input/output
27 read/write selection input
SECAM
Y
48 SECAM reference output
49 Y output
LOGIC2
LOGIC1
COLOUR2
COLOUR1
R/W
B−Y
50 B−Y output
R−Y
51 R−Y output
BLANK2
52 blanking/insertion input 2 (PIP)
1996 Jan 25
5
Philips Semiconductors
Product specification
PAL/NTSC colour processor
for PIP applications
TDA8310A
handbook, halfpage
R2
G2
B2
1
2
3
4
5
6
7
8
9
52 BLANK2
51 R−Y
50 B−Y
IDENT
49 Y
BLANK
48 SECAM
47 CHROMA
46 PLL
B
G
R
O
45 XTAL4
44 XTAL3
43 XTAL2
42 XTAL1
SYST
SW
R1 10
G1 11
B1 12
41 V
P2
BLANK1 13
CLAMP 14
40 SAND
39 HOUT
38 GND3
37 PH1LF
36 VOUT
35 DEC
TDA8310A
DEC
FT
15
CHROMA 16
I
CVBS
17
EXT
GND1 18
BG
V
19
20
21
34 n.c.
P1
CVBS
DEC
33 n.c.
INT
32 CVBS
31 GND2
30 INTB
29 i.c.
DIG
SW
i.c. 22
LOGIC2 23
LOGIC1 24
COLOUR2 25
COLOUR1 26
28 HUE
27 R/W
MGD127
Fig.2 Pin configuration.
6
1996 Jan 25
Philips Semiconductors
Product specification
PAL/NTSC colour processor
for PIP applications
TDA8310A
FUNCTIONAL DESCRIPTION
CVBS switch
Integrated video filters
The circuit contains a chrominance bandpass and trap
circuit. The filters are realised by gyrator circuits that are
automatically tuned by comparing the tuning frequency
with the crystal frequency of the decoder. When a Y/C
signal is supplied to the input the chrominance trap is
automatically switched off by the Y/C detection circuit
however, it is also possible to force the filters in the CVBS
or Y/C position.
The circuit contains a 2 input CVBS switch and one of
the inputs can be switched between CVBS and Y/C.
The circuit contains an identification circuit which can
automatically switch between the CVBS and Y/C signals.
It is also possible to force the switch to CVBS or Y/C.
Synchronization circuit
The luminance delay line is also realised by gyrator
circuits.
The sync separator is preceded by a voltage controlled
amplifier which adjusts the sync pulse amplitude to a fixed
level. The sync pulses are fed to the slicing stage
(separator) which operates at 50% of the amplitude.
Colour decoder
The colour decoder contains an alignment-free crystal
oscillator, a colour killer circuit and colour difference
demodulators. The 90° phase shift for the reference signal
is achieved internally.
The separated sync pulses are fed to the first phase
detector and to the coincidence detector. The coincidence
detector is used to detect whether the line oscillator is
synchronized and for transmitter identification. The first
PLL has a very high static steepness this ensures that the
phase of the picture is independent of the line frequency.
The line oscillator operates at twice the line frequency.
The colour decoder is very flexible. Together with the
SECAM decoder (TDA8395) an automatic multistandard
decoder can be designed but it is also possible to use it for
one standard when only one crystal is connected to the IC.
The decoder can be forced to one of the standards via the
‘forced mode’ pins. The crystal pins which are not used
must be connected to the positive supply line via a 8.2 kΩ
resistor. It is also possible to connect the non-used pins
with one resistor to the positive supply line. In this event
the resistor must have a value of 8.2 kΩ divided by the
number of pins.
The oscillator network is internal. Because of the spread of
internal components an automatic adjustment circuit has
been added to the IC.
The circuit compares the oscillator frequency with that of
the crystal oscillator in the colour decoder. This results in
a free-running frequency which deviates less than 2%
from the typical value.
The chrominance output signal of the video switch is
externally available and must be used as an input signal
for the SECAM decoder.
The horizontal output pulse is derived from the horizontal
oscillator via a pulse shaper. The pulse width of the output
pulse is 5.4 µs, the front edge of this pulse coincides with
the front edge of the sync pulse at the input.
RGB/YUV switch
The vertical output pulse is generated by a count-down
circuit. The pulse width is approximately 380 µs. Both the
horizontal and vertical output pulses will always be
available at the outputs even when no input signal is
available.
The RGB/YUV switch is for switching between two RGB or
YUV video sources. The outputs of the switch can be set
to high-impedance state so that other switches can be
used in parallel.
In addition to the horizontal and vertical sync pulse outputs
the IC has a sandcastle pulse output which contains burst
key and blanking pulses.
The switch is controlled via pins 13 and 52. The details of
switch control are shown in Table 4.
1996 Jan 25
7
Philips Semiconductors
Product specification
PAL/NTSC colour processor
for PIP applications
TDA8310A
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC134).
SYMBOL
VP
PARAMETER
MIN.
MAX.
9.0
UNIT
supply voltage
−
V
Tstg
Tamb
Tsld
Tj
storage temperature
−25
−25
−
+150
+70
260
150
°C
°C
°C
°C
operating ambient temperature
soldering temperature for 5 s
maximum operating junction temperature
−
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
VALUE
UNIT
Rth j-a
thermal resistance from junction to ambient in free air
≤40
K/W
CHARACTERISTICS
VP = 8 V; Tamb = 25 °C; unless otherwise specified.
SYMBOL
Supplies
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VP
supply voltage (pins 19 and 41)
supply current (pin 19)
supply current (pin 41)
total power dissipation
7.2
8.0
8.8
V
IP1
45
3
65
5
80
10
−
mA
mA
mW
kΩ
IP2
Ptot
Rbias
−
560
10
value of resistor to be connected
between pin 30 and the positive
supply line
−
−
CVBS and Y/C switch
INTERNAL CVBS AND EXTERNAL CVBS/Y INPUTS (PINS 20 AND 17)
V20,17(p-p)
CVBS/Y input voltage
(peak-to-peak value)
notes 1 and 3
−
1
1.4
V
I20,17
Vclamp
Iclamp
input current
−
4
6
−
−
µA
V
top sync clamping voltage level
clamping input current
−
3.3
100
80
µA
CHROMINANCE INPUT (PIN 16)
V16(p-p)
chrominance input voltage
(peak-to-peak value)
notes 1, 4 and 11
−
0.3
−
−
V
V
V16(p-p)
input signal amplitude before clipping note 2
occurs (peak-to-peak value)
1.0
−
RI
CI
chrominance input resistance
14
20
26
5
kΩ
chrominance input capacitance
note 1
−
−
pF
1996 Jan 25
8
Philips Semiconductors
Product specification
PAL/NTSC colour processor
for PIP applications
TDA8310A
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
CHROMINANCE OUTPUT (PIN 47)
V47(p-p)
output signal voltage amplitude
0.18
0.20
0.22
V
(peak-to-peak value)
output impedance
DC output voltage
ZO
VO
200
1.2
250
1.4
300
1.6
Ω
open-circuit output
V
SWITCH CONTROL INPUT FOR INTERNAL/EXTERNAL POSITIVE/NEGATIVE MODULATION (PIN 32); note 5
V32
V32
ZI
internal CVBS signal selected
external CVBS or Y/C signal selected
input impedance
−
−
−
−
−
1.0
VP
−
V
3.9
25
50
V
kΩ
dB
ISS
suppression of non-selected video
input signal
note 2
−
SWITCH CONTROL INPUT FOR EXTERNAL CVBS OR Y/C SELECTION (PIN 9)
V9
V9
V9
ZI
filters switched to CVBS condition
filters switched to Y/C condition
automatic selection of CVBS or Y/C
input impedance
−
−
−
−
−
1.0
3.0
VP
−
V
note 6
2.0
3.9
25
V
V
kΩ
Chrominance filters, luminance delay line and luminance output
CHROMINANCE TRAP CIRCUIT
ftrap
QF
SR
trap frequency
−
fosc
2
−
−
−
MHz
dB
trap quality factor
notes 2 and 7
−
colour subcarrier rejection
20
−
CHROMINANCE BANDPASS CIRCUIT
fc
centre frequency
−
−
fosc
3
−
−
MHz
ns
QBP
bandpass quality factor
note 2
Y DELAY LINE
∆td
difference in delay time between the note 2
luminance and the demodulated
chrominance signals
0
50
100
B
bandwidth of internal delay line
note 2
8
−
−
MHz
V
Y OUTPUT (PIN 49)
V49(b-w)
output signal voltage amplitude
note 23
0.8
1.0
1.2
(black-to-white value)
ZO
output impedance
80
100
2.9
0.5
120
3.1
−
Ω
V49(DC)
Ibias
DC output voltage level (top sync)
2.7
0.4
V
internal bias current of NPN emitter
follower output transistor
mA
Isource
maximum source current
−
−
2
mA
1996 Jan 25
9
Philips Semiconductors
Product specification
PAL/NTSC colour processor
for PIP applications
TDA8310A
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Horizontal and vertical synchronization circuits
SYNC VIDEO INPUT (PINS 17 AND 20)
V17,20
SL
sync pulse voltage amplitude
slicing level
note 1
50
300
−
−
mV
note 8
−
50
%
VERTICAL SYNC
tW
width of the vertical sync pulse
without sync instability
note 9
22
−
−
µs
HORIZONTAL OSCILLATOR
ffr
free running frequency
−
−
−
15625
−
−
Hz
%
∆ffr
spread on free running frequency
±2
∆fosc/∆VP
frequency variation with respect to
the supply voltage
VP = 8 V ±10%; note 2
0.2
0.5
%
∆fosc
frequency variation with temperature Tamb = 0 to 70 °C; note 2
−
−
−
−
80
75
Hz
%
∆fosc(max)
maximum frequency deviation at the no calibration
start of the horizontal output
HORIZONTAL PLL (FILTER CONNECTED TO PIN 37); note 18
fHR
fCR
S/N
holding range PLL
catching range PLL
−
±0.9
±0.9
20
±1.2
−
kHz
kHz
dB
note 2
±0.6
14
signal-to-noise ratio of the video
input signal at which the time
constant is switched
26
HYS
hysteresis at the switching point
1
3
6
dB
HORIZONTAL OUTPUT (PIN 39)
VOH
VOL
Isink
Isource
tW
HIGH level output voltage
IO = 2 mA
IO = 2 mA
2.4
−
4.0
0.3
−
−
V
LOW level output voltage
sink current
0.6
2
V
−
mA
mA
µs
µs
source current
pulse width
−
−
2
−
5.4
0
−
td
delay between the positive edge of
the horizontal output pulse and the
start of the horizontal sync pulse at
the input
−
−
1996 Jan 25
10
Philips Semiconductors
Product specification
PAL/NTSC colour processor
for PIP applications
TDA8310A
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VERTICAL OUTPUT (PIN 36); note 10
ffr
free running frequency
locking range
−
50/60
−
Hz
flock
45
−
−
64.5
−
Hz
divider value not locked
locking range
625/525
lines
488
−
722
lines/
frame
VOH
VOL
Isink
Isource
tW
HIGH level output voltage
LOW level output voltage
sink current
IOL = 2 mA
2.4
−
4.0
0.3
−
−
V
IOL = 2 mA
0.6
2
V
−
mA
mA
µs
µs
source current
−
−
2
pulse width
−
380
37.5
−
td
delay between the start of the vertical
sync pulse at the input and the
positive edge of the output pulse
−
−
SANDCASTLE PULSE OUTPUT (PIN 40); note 16
VO
VO
ZO
tW
output voltage during scan
output voltage during burst key
output impedance during blanking
pulse width
IO = 1 mA; note 24
IO = 1 mA; note 24
−
−
−
−
0.9
5.2
−
V
4.1
1.0
V
MΩ
burst key
3.3
8.4
−
3.5
8.7
14
3.7
9.0
−
µs
line blanking
µs
vertical blanking
lines
µs
td
delay of start of burst key to start of
sync
5.2
5.4
5.6
Colour demodulation part
CHROMINANCE AMPLIFIER
ACCcr
ACC control range
note 11
26
−
−
−
dB
dB
∆V
change in amplitude of the output
signals over the ACC range
−
2
THRon
HYSoff
threshold colour killer ON
hysteresis colour killer OFF
strong input signal
−38
−41
−44
dB
note 2
S/N ≥ 40 dB
0
0
+3
+1
+6
+8
dB
dB
noisy input signal
ACL CIRCUIT
chrominance burst ratio at which the
ACL starts to operate
2.3
−
2.7
1996 Jan 25
11
Philips Semiconductors
Product specification
PAL/NTSC colour processor
for PIP applications
TDA8310A
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
REFERENCE PART
Phase-locked loop; note 12
fCR
catching range
300
500
−
Hz
∆ϕ
phase shift for a ±300 Hz deviation of note 2
−
−
2
deg
the oscillator frequency
Oscillator
TCosc
∆fosc
RI
temperature coefficient of fosc
fosc deviation with respect to VP
input resistance (pins 43 to 45)
input resistance (pin 42)
note 2
−
2.0
−
2.5
250
−
Hz/K
Hz
VP = 8 V ±10%; note 2
fi = 3.58 MHz; note 1
fi = 4.43 MHz; note 1
note 1
−
−
1.5
1
kΩ
kΩ
pF
RI
−
−
CI
input capacitance (pins 42 to 45)
−
−
10
8.6
R
required resistance to VP for a crystal note 20
pin which is not used
7.8
8.2
kΩ
HUE CONTROL INPUT (PIN 28); note 21
HUEcr
Vcontrol
HUE control range
see also Fig.3
note 12
±35
±40
−
−
deg
V
control voltage to switch the colour
PLL in the free-running mode
VP − 1
−
RI
input resistance
45
−
−
kΩ
DEMODULATOR OUTPUTS (PINS 50 AND 51)
V50(p-p)
−(B−Y) output signal voltage
amplitude (peak-to-peak value)
note 25
note 25
note 2
1.06
0.84
−1
1.33
1.05
−
1.60
1.26
+1
V
V51(p-p)
−(R−Y) output signal voltage
amplitude (peak-to-peak value)
V
spread of signal amplitude ratio
PAL/NTSC
dB
Ω
ZO
output impedance (R−Y)/(B−Y)
−
−
500
output
B
bandwidth of demodulators
−3 dB; note 19
−
−
−
−
−
−
650
−
−
kHz
mV
mV
mV
mV
mV
V50(p-p)
(B−Y) residual carrier output voltage f = fosc
(peak-to-peak value)
1
f = 2fosc
−
5
V51(p-p)
(R−Y) residual carrier output voltage f = fosc
(peak-to-peak value)
−
1
f = 2fosc
−
5
V51(p-p)
∆VO/∆T
∆VO/∆VP
Ibias
H/2 ripple at (R−Y) output
(peak-to-peak value)
only burst fed to input
−
25
change of output signal amplitude
with temperature
note 2
note 2
−
0.1
−
−
%/K
dB
change of output signal amplitude
with supply voltage
−
±0.1
−
internal bias current of NPN emitter
follower output transistor
0.16
−
0.20
−
mA
mA
Isource
maximum source current
1
1996 Jan 25
12
Philips Semiconductors
Product specification
PAL/NTSC colour processor
for PIP applications
TDA8310A
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
DEMODULATION ANGLE AND GAIN RATIO
demodulation angle
85
90
95
deg
G
gain ratio of both demodulators
1.60
1.78
1.96
G(B−Y) to G(R−Y)
REFERENCE SIGNAL OUTPUT FOR TDA8395 (PIN 48)
fref
reference frequency
note 13
−
4.43
0.25
−
MHz
V
V48(p-p)
output signal amplitude
(peak-to-peak value)
0.2
0.3
VO
VO
output voltage level
output voltage level
PAL/NTSC identified
1.5
4.3
1.6
4.5
1.7
4.7
V
V
no PAL/NTSC; SECAM
(by TDA8395) identified
I48
required current to force the decoder
in SECAM mode
120
−
−
µA
STANDARD IDENTIFICATION AND FORCED SYSTEM SWITCHING (PINS 4 AND 23 TO 27); note 14
VI/O
input/output voltage
in ‘low’ condition
−
−
−
−
−
1.0
5.3
VP
1
V
in ‘high’ condition
4.0
−
V
VI(max)
Iload
II
maximum input voltage
maximum load current (pins 23 to 26)
input current (pins 23 to 26)
in ‘low’ or ‘high’ condition
when connected to VP
input resistance (pin 27)
output voltage (pin 4)
during PAL
note 22
note 22
V
−
mA
−
−
−
−
1
µA
µA
kΩ
−
10
−
RI
80
VO
IO = 0.5 mA;
notes 17 and 24
−
−
−
−
0.9
5.5
−
V
during SECAM
4.1
1
V
ZO
output impedance (pin 4)
during NTSC
note 17
MΩ
Iload
maximum load current (pin 4)
−
−
0.5
mA
RGB switch
RGB INPUTS (PINS 1 TO 3 AND 10 TO 12)
Vi(p-p)
signal voltage amplitude
(peak-to-peak value)
−
−
1.3
V
ZI
input impedance
100
2.6
−
−
−
kΩ
V
Vclamp
ILI
active clamping voltage level
input leakage current
active clamping current
2.8
−
3.0
3
note 2
µA
µA
Iclamp
−200
−
+200
1996 Jan 25
13
Philips Semiconductors
Product specification
PAL/NTSC colour processor
for PIP applications
TDA8310A
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
FAST BLANKING/SWITCH INPUTS (PINS 13 AND 52); note 15
II
input current
−
−0.2
−0.3
mA
VIH
VIL
td
HIGH level input voltage
LOW level input voltage
delay between input and output pulse
0.9
0
−
−
−
−
3.0
0.5
50
V
V
−
ns
ns
td
delay between switch input and RGB
output
−
70
V13
input voltage on pin 13 to make RGB
outputs and the fast blanking output
high-ohmic
4
−
VP
V
CLAMPING PULSE INPUT (PIN 14)
VIH
VIL
ZI
HIGH level input voltage
4.0
−
4.5
−
VP
1
V
LOW level input voltage
input impedance
V
1
−
−
MΩ
RGB OUTPUTS (PINS 6 TO 8)
Gv
voltage gain of the switches
f = 1 MHz
−0.5
−
0
+0.5
0.5
150
−
dB
dB
Ω
Gdiff
ZO
gain difference of the three channels
output impedance
−
−
−
ZO(off)
VO
output impedance in the ‘off’ state
output voltage during blanking
f = 10 MHz
100
1.2
−
−
kΩ
V
open-circuit output
1.4
−
1.6
5
Vos
blanking off-set voltage of the two
sources
mV
Isource(max)
Ibias
maximum source current
−
−
1
mA
mA
internal bias current of NPN emitter
follower output transistor
0.16
0.2
−
ISS
αct
B
input signal suppression when RGB f = 5 MHz; note 2
60
−
−
−
−
−
−
−
−
−
−
−
−
dB
dB
dB
dB
dB
dB
outputs are high-ohmic
f = 10 MHz; note 2
50
f = 22 MHz; note 2
40
crosstalk between the two RGB
channels
f = 5 MHz; note 2
f = 10 MHz; note 2
f = 22 MHz; note 2
CL = 20 pF; note 2
−60
−50
−40
bandwidth of the RGB channels
gain reduction −0.5 dB
5
−
−
−
−
−
MHz
MHz
MHz
ns
gain reduction −1 dB
10
22
−
−
gain reduction −3 dB
−
td
delay from RGB input to output
note 2
20
1996 Jan 25
14
Philips Semiconductors
Product specification
PAL/NTSC colour processor
for PIP applications
TDA8310A
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
FAST BLANKING OUTPUT (PIN 5)
VOH
VOL
ZO
ZO(off)
tr
HIGH level output voltage
2
0
−
−
−
−
−
−
−
−
3
V
LOW level output voltage
output impedance
0.3
300
−
V
Ω
output impedance in the ‘off’ state
rise time of the output pulse
fall time of the output pulse
100
−
kΩ
ns
ns
ns
30
30
30
tf
−
td
delay difference between fast
−
blanking and RGB at the outputs
Iload
maximum load current
−
−
1
mA
Notes
1. This parameter is not tested during production and is just given as application information for the designer of the
television receiver.
2. This parameter is not tested during production but is guaranteed by the design and qualified by means of matrix
batches which are made in the pilot production period.
3. Signal with negative-going sync. Amplitude includes sync pulse amplitude.
4. Burst amplitude; for a colour bar with 75% saturation the chrominance signal amplitude is 660 mV (p-p).
5. The IC has two 3-level switch control inputs for the selection of the video signal for the decoder and synchronization
circuits. The video source for internal or external signal is selected via pin 32, also the polarity of the demodulation
for the internal signal. When the video switch is in the external position the voltage level of pin 9 determines whether
the video filters are switched to CVBS or Y/C. It is also possible via pin 9 to select an automatic detection of the
Y/C signal.
6. This value is internally generated when the pin is left open-circuit (the minimum value of the series resistor is 25 kΩ).
7. The −3 dB bandwidth of the circuit can be calculated by means of the following equation:
1
2Q
f–3 dB = fosc 1 –
-------
8. The slicing level is independent of the sync pulse amplitude.
9. The horizontal and vertical sync are stable while processing Copy Guard signals and signals with phase shifted sync
pulses (stretched tapes). Trick mode conditions of the VCR will also not disturb the synchronization. The value given
is the delay caused by the vertical sync pulse integrator. The integrator has been designed such that the vertical sync
is not disturbed for special anti-copy tapes with vertical sync pulses with an on/off time of 10/22 µs.
10. The timing pulses for the vertical ramp generator are obtained from the horizontal oscillator via a divider circuit.
This divider circuit has 2 search modes of operation:
a) The ‘large window’ mode is switched on when the circuit is not synchronized or, when a non-standard signal is
received (the number of lines per frame in the 50 Hz mode is between 311 and 314 and in the 60 Hz mode
between 261 and 264). In the search mode the divider can be triggered between line 244 and line 361
(approximately 45 to 64.5 Hz).
b) The ‘narrow window’ mode is switched on when more than 15 successive vertical sync pulses are detected in the
narrow window. When the circuit is in the standard mode and a vertical sync pulse is missing the retrace of the
vertical ramp generator is started at the end of the window. Consequently, the disturbance of the picture is very
small. The circuit will switch back to the search window when, for 6 successive vertical periods, no sync pulses
are found within the window.
1996 Jan 25
15
Philips Semiconductors
Product specification
PAL/NTSC colour processor
for PIP applications
TDA8310A
11. At a chrominance input voltage of 660 mV (p-p) (colour bar with 75% saturation i.e. burst signal amplitude
300 mV (p-p)) as given in Characteristics first parameter of Section “Chrominance input (pin 16)” the dynamic range
of the ACC is +6 and −20 dB.
12. All frequency variations are referenced to 3.58/4.43 MHz carrier frequency. All oscillator specifications are measured
with the Philips crystal series 9922 520. If the spurious response of the 4.43 MHz crystal is lower than −3 dB with
respect to the fundamental frequency for a damping resistance of 1 kΩ, oscillation at the fundamental frequency is
guaranteed. The spurious response of the 3.58 MHz crystal must be lower than −3 dB with respect to the
fundamental frequency for a damping resistance of 1.5 kΩ. The catching and detuning range are measured for
nominal crystal parameters. These are:
a) Load resonance frequency f0 (CL = 20 pF) = 4.433619 or 3.579545 MHz
b) Motional capacitance CM = 20.6 fF (4.43 MHz crystal) or 14.7 fF (3.58 MHz crystal)
c) Parallel capacitance C0 = 5.5 pF (4.43 MHz crystal) or 4.5 pF (3.58 MHz crystal).
The actual load capacitance in the application should be CL = 18 pF to account for parasitic capacitances on and
off chip.
The free-running frequency of the oscillator can be checked by the HUE control pin to the positive supply rail. In that
condition the colour killer is not active so that the frequency offset is visible on the screen. When two or more crystals
are connected to the IC the circuit must be forced to one of the crystals during this test to prevent the oscillator
continuously switching between the various frequencies.
13. The reference signal for the TDA8395 is available only when the crystal oscillator is operating at a frequency of
4.43 MHz. When a SECAM signal is identified this signal is only available during the vertical retrace period thus
avoiding crosstalk with the incoming SECAM signal during scan.
14. The identified colour standard can be read from the IC in two ways:
a) From the voltage level of pin 4. The voltage during the demodulation of the various standards is given in the last
three parameters of this section.
b) From the pins 23 to 26 when pin 27 is in the ‘read’ mode.
When pin 27 is in the ‘write’ mode the colour decoder can be forced to one of the colour standards. The levels for the
various standards are given in Tables 1, 2 and 3.
15. The control possibilities of the RGB switch via pins 13 and 52 are shown in Table 4.
16. To obtain a simple interface between the TDA8310A and the PIP processor the sandcastle output has been designed
such that the output is pulled down during scan and pulled up during the burst key pulse. During blanking the output
is high-ohmic and therefore the output voltage is determined by the load.
17. The output of pin 4 is designed similar to the sandcastle output. The output is pulled down during PAL and pulled up
during SECAM. During NTSC the pin is floating so that the output level is determined by the load.
18. To obtain a good performance for both weak signal and VCR playback the time constant of the first control loop is
switched depending on the input signal condition. Therefore the circuit contains a noise detector and the time
constant is switched to ‘slow’ when excessive noise is present in the signal. This occurs when the internal video
signal is selected or for an external CVBS signal when the chrominance input (pin 16) is left open-circuit. The time
constant is always ‘fast’ when the chrominance input pin is connected to ground and the input is switched to the Y/C
mode. In the ‘fast’ mode during the vertical retrace time the phase detector current is increased 50% so that phase
errors due to head-switching of the VCR are corrected as soon as possible.
During weak signal conditions (noise detector active) the phase detector is gated and the width of the gate pulse has
a value of 5.7 µs so that the effect of the noise is reduced to a minimum.
The output current of the phase detector for the various conditions is shown in Table 5.
19. This value indicates the bandwidth of the complete chrominance circuit including the chrominance bandpass filter.
The bandwidth of the demodulator low-pass filter is approximately 1 MHz.
1996 Jan 25
16
Philips Semiconductors
Product specification
PAL/NTSC colour processor
for PIP applications
TDA8310A
20. The crystal pins which are not used must be connected to the positive supply line via an 8.2 kΩ resistor. It is also
possible to connect the non-used pins together and use a resistor with a value of 8.2 kΩ divided by the number of
pins which are not used.
21. When this pin is left open-circuit the HUE control is set to the nominal value.
22. When one or more pins have to be connected to the positive supply line the total current must be limited to 40 µA.
This can be achieved by connecting these pins together and connecting them to a positive supply line via a 100 kΩ
resistor. When separate resistors are used a resistor with a higher value must be used so that the total current is
limited to the required level.
23. This output signal value is obtained when the CVBS or Y input signal at pins 17 and/or 20 has an amplitude of 0.7 V
(black-to-white value).
24. The output buffer consists of a combination of a PMOS and an NMOS. The maximum output impedance in the low
state can be calculated by dividing the maximum output voltage (for this parameter 0.9 V) by the specified current.
For the high state this resistance can be calculated by dividing the difference between the maximum and minimum
output voltage by the specified current. The output impedance is independent of the value of the output current.
25. These output signal values are obtained for a colour bar input signal with 75% saturation.
1996 Jan 25
17
Philips Semiconductors
Product specification
PAL/NTSC colour processor
for PIP applications
TDA8310A
Table 1 Read/write pin input (pin 27)
Table 5 Output current of phase detector
MODE
LEVEL
CURRENTPHASE
DETECTOR
DURING
VERTICAL
RETRACE
SCAN
(µA)
GATED
YES/NO
Decoder automatic
LOW
HIGH
(µA)
Forced decoder mode
Weak signal and
synchronized
30
30
YES
(5.7 µs)
Table 2 Colour system logic (pins 25 and 26)
Strong signal and
synchronized
180
180
270
270
NO
PIN 25
LOW
PIN 26
LOW
STANDARD
auto/no colour
Not synchronized
NO
LOW
HIGH
LOW
PAL
HIGH
HIGH
NTSC
SECAM
MBE018
HIGH
handbook, halfpage
40
Table 3 Crystal logic (pins 23 and 24)
(deg)
20
SELECTED CRYSTAL
(MHz)
PIN 23
PIN 24
LOW
LOW
HIGH
HIGH
LOW
HIGH
LOW
HIGH
4.43
3.579 (NTSC)
3.575 (PAL-M)
3.582 (PAL-N)
0
Table 4 Control logic RGB switch (pins 13 and 52)
20
FAST
RGB
OUTPUT
PIN 13
PIN 52
BLANKING
OUTPUT
LOW
LOW
HIGH
HIGH
LOW
HIGH
LOW
HIGH
black
RGB 2
RGB 1
RGB 2
LOW
HIGH
HIGH
HIGH
40
0
1
2
3
4
5
(V)
Fig.3 HUE control curve.
1996 Jan 25
18
Philips Semiconductors
Product specification
PAL/NTSC colour processor
for PIP applications
TDA8310A
PACKAGE OUTLINE
SDIP52: plastic shrink dual in-line package; 52 leads (600 mil)
SOT247-1
D
M
E
A
2
A
L
A
1
c
e
(e )
1
w M
Z
b
1
M
H
b
52
27
pin 1 index
E
1
26
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
max.
A
A
2
max.
(1)
(1)
Z
1
w
UNIT
b
b
c
D
E
e
e
L
M
M
H
1
1
E
min.
max.
1.3
0.8
0.53
0.40
0.32
0.23
47.9
47.1
14.0
13.7
3.2
2.8
15.80
15.24
17.15
15.90
mm
5.08
0.51
4.0
1.778
15.24
0.18
1.73
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
90-01-22
95-03-11
SOT247-1
1996 Jan 25
19
Philips Semiconductors
Product specification
PAL/NTSC colour processor
for PIP applications
TDA8310A
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
Repairing soldered joints
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
Soldering by dipping or by wave
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1996 Jan 25
20
Philips Semiconductors
Product specification
PAL/NTSC colour processor
for PIP applications
TDA8310A
NOTES
1996 Jan 25
21
Philips Semiconductors
Product specification
PAL/NTSC colour processor
for PIP applications
TDA8310A
NOTES
1996 Jan 25
22
Philips Semiconductors
Product specification
PAL/NTSC colour processor
for PIP applications
TDA8310A
NOTES
1996 Jan 25
23
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Tel. (022)74 8000, Fax. (022)74 8341
Printed in The Netherlands
Pakistan: Philips Electrical Industries of Pakistan Ltd.,
Exchange Bldg. ST-2/A, Block 9, KDA Scheme 5, Clifton,
KARACHI 75600, Tel. (021)587 4641-49,
Fax. (021)577035/5874546
537021/1100/02/pp24
Date of release: 1996 Jan 25
9397 750 00589
Document order number:
相关型号：
TDA8315T/N3
IC COLOR SIGNAL DECODER, PDSO24, 7.50 MM, PLASTIC, MS-013AD, SOT-137-1, SOP-24, Color Signal Converter
NXP
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