TDA8586Q [NXP]
Power amplifier with load detection and auto BTL/SE selection; 功率放大器负载检测和自动BTL / SE选择
| 型号： | TDA8586Q |
| 厂家： | 
NXP |
| 描述： | Power amplifier with load detection and auto BTL/SE selection |
| 文件： | 总24页 (文件大小：142K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TDA8586
Power amplifier with load detection
and auto BTL/SE selection
1999 Apr 08
Preliminary specification
Supersedes data of 1998 May 25
File under Integrated Circuits, IC01
Philips Semiconductors
Preliminary specification
Power amplifier with load detection and
auto BTL/SE selection
TDA8586
FEATURES
General
GENERAL DESCRIPTION
The IC incorporates the following functions:
1. 4 × 6 W SE amplifies without SE capacitor, because of
• Operating voltage from 8 to 18 V
• Low distortion
the availability of 2 half supply voltage power buffers
2. 2 × 20 W BTL amplifiers
• Few external components, fixed gain
3. Automatic switching between 2 and 4 speaker
operation. The mode of operation is determined during
start-up.
• Automatic mode selection (SE or BTL) depending on
connected ‘rear’ loads
• Can be used as a stereo amplifier in Bridge-Tied Load
(BTL) or quad Single-Ended (SE) amplifiers
This amplifier is protected for all general short-circuit
conditions to battery or ground, overvoltage, 45 V load
dump and short-circuits on the speaker outputs.
• Single-ended mode without loudspeaker capacitor
• Soft clipping, to guarantee good clip behaviour with
inductive loads
The IC is contained in a 20-pin power HSOP package, but
is also available in a 17-pin SIL power package. When
packaged in the 20-pin HSOP package additional
functions are available:
• Mute and standby mode with one-pin operation
• Diagnostic information for Dynamic Distortion Detector
(DDD), high temperature (140 °C) mode of operation
and short-circuit
1. DDD level selection between 2 and 10%
2. Overrule pin for changing mode of operation
(from SE to BTL or from BTL to SE).
• No switch-on/off plops when switching between standby
and mute and from mute to on
• Load detection on ‘rear’ channels when switching from
standby to mute
• Fast mute on supply voltage drops (low VP mute).
Protection
• Short-circuit proof to ground, positive supply voltage on
all pins and across load
• ESD protected on all pins
• Thermal protection against temperatures exceeding
150 °C
• Load dump protection
• Overvoltage protection.
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
SOT243-1
SOT418-2
TDA8586Q
DBS17P plastic DIL-bent-SIL power package; 17 leads (lead length 12 mm)
HSOP20 heatsink small outline package; 20 leads; low stand-off
TDA8586TH
1999 Apr 08
2
Philips Semiconductors
Preliminary specification
Power amplifier with load detection and
auto BTL/SE selection
TDA8586
QUICK REFERENCE DATA
SYMBOL
VP
Iq(tot)
Istb
PARAMETER
CONDITIONS
MIN.
8.0
TYP.
MAX.
18
UNIT
operating supply voltage
total quiescent current
standby supply current
voltage gain
−
V
VP = 14.4 V, SE mode
VP = 14.4 V
−
140
1
170
100
27
mA
µA
dB
dB
−
Gv
SE mode
25
31
26
32
BTL mode
33
Bridge-tied load application
Po
output power
VP = 14.4 V; RL = 4 Ω
THD = 0.5%
14
17
−
15
−
W
W
%
THD = 10%
21
−
THD
VOO
total harmonic distortion
DC output offset voltage
fi = 1 kHz; Po = 1 W;
VP = 14.4 V; RL = 4 Ω
0.05
0.15
VP = 14.4 V; RL = 4 Ω;
−
10
20
mV
mute condition
VP = 14.4 V; on condition
−
−
0
100
200
mV
Vn(o)
noise output voltage
Rs = 1 kΩ; VP = 14.4 V
100
µV
Single-ended application
Po
output power
VP = 14.4 V; RL = 4 Ω
THD = 0.5%
4
5
−
4.5
6
−
W
W
%
THD = 10%
−
THD
VOO
total harmonic distortion
DC output offset voltage
fi = 1 kHz; Po = 1 W;
VP = 14.4 V; RL = 4 Ω
0.08
0.15
VP = 14.4 V; RL = 4 Ω;
−
10
20
mV
mute condition
VP = 14.4 V; on condition
−
−
0
100
150
mV
Vn(o)
noise output voltage
Rs = 1 kΩ; VP = 14.4 V
80
µV
1999 Apr 08
3
Philips Semiconductors
Preliminary specification
Power amplifier with load detection and
auto BTL/SE selection
TDA8586
BLOCK DIAGRAM
V
V
P1
P2
16
2
5
IN1
−
+
60
kΩ
V/I
V/I
−
+
1
OUT1
OA
+
−
60
kΩ
TDA8586Q
−
+
3
4
V
Pn
HVP1
OUT2
OA
OA
+
−
6
IN2
+
−
60
kΩ
V/I
V/I
7
IN3
−
+
60
kΩ
−
+
17
OUT3
HVP2
OA
11
ACREF
+
−
V
Pn
60
kΩ
V/I
−
+
15
14
V
Pn
OA
OA
30 kΩ
BUFFER
+
−
8
IN4
OUT4
DIAG
+
−
60
kΩ
V/I
13
12
MSO
INTERFACE
DIAGNOSTIC
9
10
MGR023
PGND2
PGND1
Fig.1 Block diagram SOT243-1.
4
1999 Apr 08
Philips Semiconductors
Preliminary specification
Power amplifier with load detection and
auto BTL/SE selection
TDA8586
V
V
P1
P2
13
18
2
IN1
−
+
60
kΩ
V/I
V/I
−
+
17
OUT1
OA
+
−
60
kΩ
TDA8586TH
−
+
1
3
19
20
V
Pn
n.c.
IN2
HVP1
OUT2
OA
OA
+
−
+
−
60
kΩ
V/I
V/I
4
6
IN3
−
+
60
kΩ
−
+
14
OUT3
HVP2
OA
ACREF
+
−
V
Pn
60
kΩ
V/I
−
+
12
11
V
Pn
OA
OA
30 kΩ
BUFFER
+
−
5
8
IN4
OUT4
DIAG
+
−
60
kΩ
V/I
7
MSO
INTERFACE
DIAGNOSTIC
10
9
15
PGND2
16
MGR024
DDDSEL OVERRULE
PGND1
Fig.2 Block diagram SOT418-2 (HSOP20 heatsink up).
5
1999 Apr 08
Philips Semiconductors
Preliminary specification
Power amplifier with load detection and
auto BTL/SE selection
TDA8586
PINNING
PIN
SOT243
PIN
SOT418
SYMBOL
DESCRIPTION
n.c.
IN1
IN2
IN3
IN4
−
5
1
2
not connected
non-inverting input 1
inverting input 2
6
3
7
4
non inverting input 3
inverting input 4
8
5
ACREF
DIAG
11
12
13
−
6
common signal input
diagnostic output/mode fix
7
MSO
8
mode select mute, standby or on
mode selection overrule
OVERRULE
DDDSEL
OUT4
HVP2
9
−
10
11
12
13
14
15
16
17
18
19
20
2 or 10% dynamic distortion detection
SE output 4 (negative)
14
15
16
17
10
9
buffer output/BTL output 2 (negative)
supply voltage 2
VP2
OUT3
PGND2
PGND1
OUT1
VP1
SE output 3/BTL output 2 (positive)
power ground 2
power ground 1
1
SE output 1/BTL output 1 (positive)
supply voltage 1
2
HVP1
3
buffer output/BTL output 1 (negative)
SE output 2 (negative)
OUT2
4
1999 Apr 08
6
Philips Semiconductors
Preliminary specification
Power amplifier with load detection and
auto BTL/SE selection
TDA8586
handbook, halfpage
OUT1
1
2
V
P1
HVP1
OUT2
IN1
3
handbook, halfpage
4
1
2
20 OUT2
n.c.
IN1
5
19
18
17
HVP1
6
IN2
V
3
IN2
P1
7
IN3
OUT1
4
IN3
8
IN4
16 PGND1
15 PGND2
IN4
5
TDA8586TH
9
PGND1
PGND2
ACREF
DIAG
MSO
TDA8586Q
6
ACREF
DIAG
MSO
10
11
12
13
14
15
16
17
OUT3
7
14
13
12
V
8
P2
HVP2
9
OVERRULE
DDDSEL
10
11 OUT4
OUT4
HVP2
MGR026
V
P2
OUT3
MGR025
Fig.3 Pin configuration (SOT243-1).
Fig.4 Pin configuration (SOT418-2).
1999 Apr 08
7
Philips Semiconductors
Preliminary specification
Power amplifier with load detection and
auto BTL/SE selection
TDA8586
The presence of the load is measured after the transition
between standby and mute. The IC will determine if there
is an acceptable load on both outputs (OUT2 and OUT4).
If both outputs are unloaded, the IC will switch to a
2 speaker mode of operation (BTL mode), unless it is
overruled.
FUNCTIONAL DESCRIPTION
The TDA8586 is a multi-purpose power amplifier with four
amplifiers and 2 buffer stages, which can be connected in
the following configurations with high output power and
low distortion:
• Dual Bridge-Tied Load (BTL) amplifiers
• Quad Single-Ended (SE) amplifiers.
There are two options to overrule:
1. Before transition from mute to on, after a load
detection, pulling the diagnostic output above 9.5 V
will force the IC into 4 speaker mode
In the BTL mode of operation, the 2 buffer amplifiers act as
inverting amplifiers to complete the bridge across the
‘front’ amplifiers (OUT1 and OUT3) and the ‘rear’ outputs
(OUT2 and OUT4) enter a high-impedance state.
2. TDA8586TH: pulling the OVERRULE pin according
pinning table.
In the SE mode of operation, the buffers act as an AC
ground path thereby eliminating the need for series
capacitors on the speaker outputs.
Care should be taken with the OVERRULE function as it
works during the on mode. If there is a 2 or 4 speaker
mode change during the on mode a large ‘plop’ can be
heard on the speakers.
Diagnostics:
• While the IC is in the mute mode, the diagnostic output
will signal the mode of operation when the IC is not
overruled
The ACREF input (common signal input) acts with the four
signal inputs (IN1 to IN4) to provide quasi differential
inputs. A capacitor must be connected to this pin of which
the ground pin should be connected to the ground at the
signal source (usually the ground at the audio signal
processor). This capacitor has a dual function. During the
speaker detection, the signal ground capacitor is used to
set the time constant of the measurement (and thus
determines the minimum required switch-on time).
The capacitor on the MSO pin allows the integrate function
to provide immunity to outside noises during load
detection.
• In the on mode the diagnostic output will signal any fault
in the IC or if the output of any amplifier is clipping with
a distortion of 10% (or 2% depending on selected
clip-mode).
Special attention is given to the dynamic behaviour as
follows:
• Noise suppression during engine start
• No plops when switching from standby to on
• Slow offset change between mute and on (controlled by
MSO pin)
• Low noise levels, which are independent of the supply
voltage.
Protections are included to avoid the IC being damaged at:
• Over temperature: Tj > 150 °C
• Short-circuit of the output pin(s) to ground or supply rail.
When short-circuited, the power dissipation is limited
• ESD protection (Human Body Model 3000 V and
Machine Model 300 V).
1999 Apr 08
8
Philips Semiconductors
Preliminary specification
Power amplifier with load detection and
auto BTL/SE selection
TDA8586
mute
mute
on
on
on
state
standby
condition
load detect
no load detect
no clipping/shorts
clipping
short-circuit
V
P
0
V
P
minimum 1 s
SE detection
9 V
MSO
3 V
0
BTL detection
BTL detected
SE detected
5 V
diagnostic
information
0
10 V
The mode is overruled only from
BTL to SE when the diagnostic pin
is excited with a pulse of 10 V.
diagnostic
overrule
0
5 V
This voltage must remain present.
Whatever the load detection has found the mode of operation will be inverted.
Toggling between the 2 modes is possible.
mode select
0
short-circuit to supply
short-circuit over load
short-circuit to ground
amplifier
output
0.5V
P
0
short-circuit to supply
short-circuit over load
0.5V
buffer/amplifier
output
P
0
short-circuit to ground
MGR027
Fig.5 Timing diagram including diagnostics.
9
1999 Apr 08
Philips Semiconductors
Preliminary specification
Power amplifier with load detection and
auto BTL/SE selection
TDA8586
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VP
PARAMETER
CONDITIONS
operating
MIN.
MAX.
18
UNIT
supply voltage
8
V
V
load dump protected;
see Fig.6
−
45
VDIAG
IOSM
IORM
Vrp
voltage on diagnostic pin
−
−
−
−
−
18
6
V
A
A
V
V
non-repetitive peak output current
repetitive peak output current
reverse polarity voltage
4
note 1
6
Vsc
AC and DC short-circuit voltage of output pins
across loads and to ground or supply pins
18
Ptot
Tj
total power dissipation
junction temperature
−
−
75
W
150
+150
+150
°C
°C
°C
Tstg
Tamb
storage temperature
−55
−40
operating ambient temperature
Note
1. A large reverse current will flow, therefore external protection is needed (fuse and reverse diode).
MGL404
handbook, halfpage
45 V
V
P
14.4 V
t (ms)
t
t
f
r
Fig.6 Load dump voltage waveform.
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
in free air
VALUE
UNIT
K/W
K/W
Rth(j-a)
Rth(j-c)
thermal resistance from junction to ambient
thermal resistance from junction to case
40
2
1999 Apr 08
10
Philips Semiconductors
Preliminary specification
Power amplifier with load detection and
auto BTL/SE selection
TDA8586
CHARACTERISTICS
VP = 14.4 V; Tamb = 25 °C; fi = 1 kHz; RL = ∞; measured in test circuit of Fig.8; unless otherwise specified.
SYMBOL
Supplies
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VP
operating supply voltage
total quiescent current
standby current
8.0
14.4
18
V
Iq(tot)
Istb
SE mode
−
140
1
170
100
−
mA
µA
V
−
VO
DC output voltage
VP = 14.4 V
−
7.0
7.0
VP(mute)
Vo
low supply voltage mute
6.0
8.0
V
single-ended and bridge-tied
load output voltage
VP = 14.4 V; RL = 4 Ω
mute condition
on condition
−
−
−
−
20
100
−
mV
mV
V
−
VI
DC input voltage
VP = 14.4 V
4.0
PIN MSO
VMSO
voltage at pin MSO
standby condition
mute condition; note 1
on condition
0
−
0.8
4
V
2.0
8.0
−
3.0
−
V
10.5
40
V
IMSO
input current
mute pin at standby condition;
VMSO < 0.8 V
5
µA
Diagnostic; output buffer (open-collector); see Figs 7 to 8
VDIAG(L) diagnostic output voltage LOW Isink = 1 mA
ILI
−
0.3
−
0.8
1
V
leakage current
VDIAG = 14.4 V
−
µA
V
VDIAG(or)
diagnostic override voltage
in mute mode after load
detection
10.5
−
18
VDIAG(4ch)
CD2
diagnostic 4 channel indication mute, after load detection with
−
0.3
2
0.8
3.5
13
V
voltage
4 speakers connected
clip detector LOW
THD mode; VDIAG > 3 V;
0.5
7
%
%
R = 10 kΩ
CD10
clip detector HIGH
THD mode (default);
10
V
DIAG > 3 V; R = 10 kΩ
CLIP DETECT CONTROL PIN
VDDDSEL
voltage at DDD select pin to
obtain:
10% DDD
0
−
−
−
1
V
2% DDD
3
6
V
IDDDSEL
Input current DDD select pin
VDDDSEL = 5 V
15
140
µA
1999 Apr 08
11
Philips Semiconductors
Preliminary specification
Power amplifier with load detection and
auto BTL/SE selection
TDA8586
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Stereo BTL application (see Fig.7)
THD
Po
total harmonic distortion
output power
fi = 1 kHz; Po = 1 W; RL = 4 Ω
−
−
0.05
0.15
%
45 Hz < fi < 10 kHz; Po = 1 W;
RL = 4 Ω; filter: f < 30 kHz
0.3
−
%
VP = 14.4 V; RL = 4 Ω; note 2
THD = 0.5%
14
17
31
−0.7
45
−
15
21
32
0
−
W
THD = 10%
−
W
Gv
voltage gain
Vi(rms) = 15 mV
33
+0.7
−
dB
dB
dB
mV
mV
∆Gv
αcs
channel unbalance
channel separation
DC output offset voltage
Vi(rms) = 15 mV
Po = 2 W; fi = 1 kHz; RL = 4 Ω
VP = 14.4 V; on condition
55
0
VOO
100
20
VP = 14.4 V; RL = 4 Ω;
−
10
mute condition
Vn(o)
noise output voltage on
noise output voltage mute
output voltage mute
Rs = 1 kΩ; VP = 14.4 V; note 3
note 3
−
−
−
100
0
150
20
µV
µV
µV
Vn(o)(mute)
Vo(mute)
SVRR
Vi(rms) = 1 V
3
500
supply voltage ripple rejection: Rs = 0 Ω; fi = 1 kHz;
Vripple = 2 V (p-p)
on condition
45
55
40
55
70
60
−
dB
dB
kΩ
mute condition
−
Zi
input impedance
input referenced to ground
90
1999 Apr 08
12
Philips Semiconductors
Preliminary specification
Power amplifier with load detection and
auto BTL/SE selection
TDA8586
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Quad SE application (see Fig.8)
THD
Po
total harmonic distortion
output power
fi = 1 kHz; Po = 1 W; RL = 4 Ω
−
−
0.05
0.15
%
45 Hz < fi < 10 kHz; Po = 1 W;
RL = 4 Ω; filter: f < 30 kHz
0.5
−
%
VP = 14.4 V; RL = 4 Ω; note 2
THD = 0.5%
4
5
4.5
6
−
W
THD = 10%
−
W
Gv
voltage gain
Vi(rms) = 15 mV
25
−0.7
40
−
26
0
27
+0.7
−
dB
dB
dB
mV
mV
∆Gv
αcs
channel unbalance
channel separation
DC output offset voltage
Vi(rms) = 15 mV
Po = 2 W; fi = 1 kHz; RL = 4 Ω
VP = 14.4 V; on condition
50
0
VOO
100
20
VP = 14.4 V; RL = 4 Ω;
−
10
mute condition
Vn(o)
noise output voltage on
noise output voltage mute
output voltage mute
Rs = 1 kΩ; VP = 14.4 V; note 3
note 3
−
−
−
80
0
150
20
µV
µV
µV
Vn(o)(mute)
Vo(mute)
SVRR
Vi(rms) = 1 V
3
500
supply voltage ripple rejection Rs = 0 Ω; fi = 1 kHz;
Vripple = 2 V (p-p)
on condition
43
55
47
70
−
−
dB
dB
mute condition
Notes
1. Tolerances on the mute level is tight because of the usage of this pin for integration during load detection.
2. The output power is measured directly on the pins of the IC.
3. The noise output is measured in a bandwidth of 20 Hz to 20 kHz.
1999 Apr 08
13
Philips Semiconductors
Preliminary specification
Power amplifier with load detection and
auto BTL/SE selection
TDA8586
APPLICATION INFORMATION
V
P
1000 µF
(16/40 V)
100
nF
V
V
P1
P2
16
2
220 nF
IN1
5
−
+
60
kΩ
V/I
V/I
V
front
−
+
INL
OUT1
1
OA
+
−
4 or 8 Ω
+
−
60
kΩ
TDA8586Q
−
+
HVP1
OUT2
3
4
V
Pn
OA
OA
+
−
220 nF
220 nF
IN2
IN3
6
7
+
−
60
kΩ
V/I
V/I
−
+
60
kΩ
V
front
−
+
INR
OUT3
HVP2
17
15
OA
ACREF 11
47 µF
+
−
4 or 8 Ω
(10 V)
+
−
V
Pn
60
kΩ
V/I
−
+
V
Pn
OA
OA
30 kΩ
BUFFER
+
−
220 nF
IN4
8
14 OUT4
+
−
60
kΩ
V/I
switched
+9 V
+5 V
10 kΩ
30 kΩ
MSO
13
12 DIAG
INTERFACE
DIAGNOSTIC
15 kΩ
10
PGND2
9
4.7 µF
(10 V)
MGR028
PGND1
switch
Fig.7 Stereo bridge-tied load application (SOT243-1).
14
1999 Apr 08
Philips Semiconductors
Preliminary specification
Power amplifier with load detection and
auto BTL/SE selection
TDA8586
V
P
1000 µF
(16/40 V)
100
nF
V
V
P1
P2
16
2
220 nF
IN1
5
−
+
60
kΩ
V/I
V/I
V
front
−
+
INL
OUT1
1
OA
+
−
4 or 8 Ω
+
−
60
kΩ
TDA8586Q
−
+
HVP1
OUT2
3
4
V
Pn
OA
OA
+
−
4 or 8 Ω
+
−
220 nF
220 nF
IN2
IN3
6
7
+
−
60
kΩ
V/I
V/I
V
rear
INL
−
+
60
kΩ
V
front
−
+
INR
OUT3
17
OA
ACREF 11
47 µF
+
−
4 or 8 Ω
(10 V)
+
−
V
Pn
60
kΩ
V/I
−
+
HVP2
OUT4
15
14
V
Pn
OA
OA
30 kΩ
+
−
4 or 8 Ω
BUFFER
+
−
220 nF
IN4
8
+
−
60
kΩ
V
rear
V/I
INR
+5 V
10 kΩ
switched
+9 V
30 kΩ
MSO
13
12 DIAG
INTERFACE
DIAGNOSTIC
10
PGND2
9
15 kΩ
MGR029
PGND1
4.7 µF
(10 V)
switch
Fig.8 Quad single-ended application (SOT243-1).
15
1999 Apr 08
Philips Semiconductors
Preliminary specification
Power amplifier with load detection and
auto BTL/SE selection
TDA8586
V
P
1000 µF
(16/40 V)
100
nF
V
V
P1
18
P2
13
220 nF
IN1
2
−
+
60
kΩ
V/I
V/I
V
front
−
+
INL
OUT1
HVP1
17
19
OA
+
−
4 or 8 Ω
+
−
60
kΩ
TDA8586TH
−
+
1
3
n.c.
IN2
V
Pn
OA
OA
+
−
220 nF
220 nF
20 OUT2
+
−
60
kΩ
V/I
V/I
IN3
4
6
−
+
60
kΩ
V
front
−
+
INR
OUT3
HVP2
14
12
OA
ACREF
+
−
47 µF
(10 V)
4 or 8 Ω
+
−
V
Pn
60
kΩ
V/I
−
+
V
Pn
OA
OA
30 kΩ
BUFFER
+
−
220 nF
IN4
5
8
11 OUT4
+
−
60
kΩ
V/I
switched
+9 V
+5 V
10 kΩ
30 kΩ
DIAG
7
MSO
INTERFACE
DIAGNOSTIC
15 kΩ
10
9
15
PGND2
16
4.7 µF
(10 V)
DDDSEL
OVERRULE
PGND1
switch
MGR030
Fig.9 Stereo bridge-tied load application (SOT418-2).
16
1999 Apr 08
Philips Semiconductors
Preliminary specification
Power amplifier with load detection and
auto BTL/SE selection
TDA8586
V
P
1000 µF
(16/40 V)
100
nF
V
V
P1
18
P2
13
220 nF
IN1
2
−
+
60
kΩ
V/I
V/I
V
front
−
+
INL
OUT1
17
OA
+
−
4 or 8 Ω
+
−
60
kΩ
TDA8586TH
−
+
HVP1
OUT2
n.c.
IN2
1
3
19
20
V
Pn
OA
OA
+
−
4 or 8 Ω
+
−
220 nF
220 nF
+
−
60
kΩ
V/I
V/I
V
rear
INL
IN3
4
6
−
+
60
kΩ
V
front
−
+
INR
OUT3
14
12
OA
ACREF
+
−
47 µF
(10 V)
4 or 8 Ω
+
−
V
Pn
60
kΩ
V/I
−
+
HVP2
OUT4
V
Pn
OA
OA
30 kΩ
+
−
4 or 8 Ω
BUFFER
+
−
220 nF
IN4
5
8
11
+
−
60
kΩ
V
rear
V/I
INR
+5 V
switched
+9 V
10 kΩ
DIAG
30 kΩ
MSO
7
INTERFACE
DIAGNOSTIC
10
9
15
PGND2
16
15 kΩ
MGR031
DDDSEL
OVERRULE
PGND1
4.7 µF
(10 V)
switch
Fig.10 Quad single-ended application (SOT418-2).
17
1999 Apr 08
Philips Semiconductors
Preliminary specification
Power amplifier with load detection and
auto BTL/SE selection
TDA8586
INTERNAL PIN CONFIGURATION
PIN
TDA8586TH
NAME
EQUIVALENT CIRCUIT
2, 3, 4, 5 and 6
inputs
V
P
handbook, halfpage
IN
MGE014
11, 12, 14, 17,
19 and 20
outputs
handbook, halfpage
V
P
OUT
0.5 V
MGE015
P
8
mode select
V
P
handbook, halfpage
MGE016
1999 Apr 08
18
Philips Semiconductors
Preliminary specification
Power amplifier with load detection and
auto BTL/SE selection
TDA8586
PACKAGE OUTLINES
DBS17P: plastic DIL-bent-SIL power package; 17 leads (lead length 12 mm)
SOT243-1
non-concave
D
h
x
D
E
h
view B: mounting base side
d
A
2
B
j
E
A
L
3
L
Q
c
2
v
M
1
17
e
e
m
w
M
1
Z
b
p
e
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
(1)
(1)
UNIT
A
A
b
c
D
d
D
E
e
e
e
E
j
L
L
3
m
Q
v
w
x
Z
2
p
h
1
2
h
17.0 4.6 0.75 0.48 24.0 20.0
15.5 4.2 0.60 0.38 23.6 19.6
12.2
11.8
3.4 12.4 2.4
3.1 11.0 1.6
2.00
1.45
2.1
1.8
6
mm
10
2.54 1.27 5.08
0.8
4.3
0.4 0.03
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-03-11
97-12-16
SOT243-1
1999 Apr 08
19
Philips Semiconductors
Preliminary specification
Power amplifier with load detection and
auto BTL/SE selection
TDA8586
HSOP20: heatsink small outline package; 20 leads; low stand-off
SOT418-2
E
A
D
x
X
c
y
E
2
H
v
M
A
E
D
1
D
2
10
1
pin 1 index
Q
A
A
2
(A )
3
E
1
A
4
θ
L
p
detail X
20
11
w M
Z
b
p
e
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
max.
(1)
(2)
(2)
A
A
A
b
c
D
D
D
E
E
1
E
e
H
L
p
Q
v
w
x
y
Z
θ
UNIT
2
3
4
p
1
2
2
E
8°
0°
+0.12 0.53 0.32
−0.02 0.40 0.23
16.0 13.0 1.1 11.1 6.2
15.8 12.6 0.9 10.9 5.8
2.9
2.5
14.5 1.1
13.9 0.8
1.7
1.5
2.5
2.0
3.5
3.2
mm
1.27
3.5
0.35
0.25 0.25 0.03 0.07
Note
1. Limits per individual lead.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
97-10-29
98-02-25
SOT418-2
1999 Apr 08
20
Philips Semiconductors
Preliminary specification
Power amplifier with load detection and
auto BTL/SE selection
TDA8586
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
SOLDERING
Introduction
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
WAVE SOLDERING
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mount components are mixed on
one printed-circuit board. However, wave soldering is not
always suitable for surface mount ICs, or for printed-circuit
boards with high population densities. In these situations
reflow soldering is often used.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
Through-hole mount packages
SOLDERING BY DIPPING OR BY SOLDER WAVE
• For packages with leads on two sides and a pitch (e):
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joints for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg(max)). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
MANUAL SOLDERING
Apply the soldering iron (24 V or less) to the lead(s) of the
package, either below the seating plane or not more than
2 mm above it. If the temperature of the soldering iron bit
is less than 300 °C it may remain in contact for up to
10 seconds. If the bit temperature is between
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
300 and 400 °C, contact may be up to 5 seconds.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Surface mount packages
REFLOW SOLDERING
MANUAL SOLDERING
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
1999 Apr 08
21
Philips Semiconductors
Preliminary specification
Power amplifier with load detection and
auto BTL/SE selection
TDA8586
Suitability of IC packages for wave, reflow and dipping soldering methods
SOLDERING METHOD
WAVE
REFLOW(1) DIPPING
suitable(2)
not suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable(3)
MOUNTING
PACKAGE
Through-hole mount DBS, DIP, HDIP, SDIP, SIL
−
suitable
Surface mount
BGA, SQFP
suitable
suitable
suitable
suitable
suitable
−
−
−
−
−
PLCC(4), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
not recommended(4)(5)
not recommended(6)
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.
3. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is only suitable for LQFP, QFP and TQFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1999 Apr 08
22
Philips Semiconductors
Preliminary specification
Power amplifier with load detection and
auto BTL/SE selection
TDA8586
NOTES
1999 Apr 08
23
Philips Semiconductors – a worldwide company
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5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1999
SCA63
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545002/750/02/pp24
Date of release: 1999 Apr 08
Document order number: 9397 750 05483
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