TDA8703T [NXP]
8-bit high-speed analog-to-digital converter; 8位高速模拟数字转换器
| 型号： | TDA8703T |
| 厂家： | 
NXP |
| 描述： | 8-bit high-speed analog-to-digital converter |
| 文件： | 总18页 (文件大小：144K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TDA8703
8-bit high-speed analog-to-digital
converter
1996 Aug 26
Product specification
Supersedes data of April 1993
File under Integrated Circuits, IC02
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital
converter
TDA8703
FEATURES
APPLICATIONS
• 8-bit resolution
• General purpose high-speed analog-to-digital
conversion
• Sampling rate up to 40 MHz
• Digital TV, IDTV
• High signal-to-noise ratio over a large analog input
frequency range (7.1 effective bits at 4.43 MHz
full-scale input)
• Subscriber TV decoder
• Satellite TV decoders
• Digital VCR.
• Binary or two's complement 3-state TTL outputs
• Overflow/underflow 3-state TTL output
• TTL compatible digital inputs
GENERAL DESCRIPTION
• Low-level AC clock input signal allowed
• Internal reference voltage generator
• Power dissipation only 290 mW (typical)
The TDA8703 is an 8-bit high-speed Analog-to-Digital
Converter (ADC) for video and other applications.
It converts the analog input signal into 8-bit binary-coded
digital words at a maximum sampling rate of 40 MHz.
All digital inputs and outputs are TTL compatible, although
a low-level AC clock input signal is allowed.
• Low analog input capacitance, no buffer amplifier
required
• No sample-and-hold circuit required.
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
SOT101-1
SOT137-1
TDA8703
DIP24
SO24
plastic dual in-line package; 24 leads (600 mil)
TDA8703T
plastic small outline package; 24 leads; body width 7.5 mm
1996 Aug 26
2
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDA8703
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
4.5
TYP.
5.0
MAX.
5.5
UNIT
VCCA
VCCD
VCCO
ICCA
ICCD
ICCO
ILE
analog supply voltage
digital supply voltage
V
4.5
4.2
−
5.0
5.0
28
19
11
−
5.5
5.5
36
25
14
±1
±1/2
±2
−
V
output stages supply voltage
analog supply current
V
mA
mA
mA
LSB
LSB
LSB
MHz
MHz
mW
digital supply current
−
output stages supply current
DC integral linearity error
DC differential linearity error
AC integral linearity error
−3 dB bandwidth
−
−
DLE
AILE
B
−
−
note 1
−
−
note 2; fCLK = 40 MHz
note 3
−
19.5
−
fCLK/fCLK
Ptot
maximum conversion rate
total power dissipation
40
−
−
290
415
Notes
1. Full-scale sinewave (fi = 4.4 MHz; fCLK; fCLK = 27 MHz).
2. The −3 dB bandwidth is determined by the 3 dB reduction in the reconstructed output (full-scale signal at input).
3. The circuit has two clock inputs CLK and CLK. There are four modes of operation:
a) TTL (mode 1); CLK decoupled to DGND by a capacitor. CLK input is TTL threshold voltage of 1.5 V and sampling
on the LOW-to-HIGH transition of the input clock signal.
b) TTL (mode 2); CLK decoupled to DGND by a capacitor. CLK input is TTL threshold voltage of 1.5 V and sampling
on the HIGH-to-LOW transition of the input clock signal.
c) AC drive modes (modes 3 and 4); When driving the CLK input directly and with any AC signal of 0.5 V
(peak-to-peak value) imposed on a DC level of 1.5 V, sampling takes place on the LOW-to-HIGH transition of the
clock signal. When driving the CLK input with such a signal, sampling takes place on the HIGH-to-LOW transition.
d) If one of the clock inputs is not driven, then it is recommended to decouple this input to DGND with a 100 nF
capacitor.
1996 Aug 26
3
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDA8703
BLOCK DIAGRAM
clock inputs
V
7
CLK
16
V
CLK
17
CCA
CCD
18
TC
21
CE
22
STABILIZER
CLOCK DRIVER
DEC
5
9
TDA8703
TDA8703T
V
RT
12 D7
MSB
13 D6
14 D5
15 D4
23 D3
24 D2
VI
8
4
ANALOG - TO - DIGITAL
CONVERTER
analog
voltage input
data outputs
LATCHES
TTL OUTPUTS
1
2
D1
D0
LSB
V
RB
19
11
V
CCO
overflow /
underflow
output
OVERFLOW / UNDERFLOW
LATCH
TTL OUTPUT
20
3
AGND
DGND
MGA015
analog ground
digital ground
Fig.1 Block diagram.
1996 Aug 26
4
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDA8703
PINNING
SYMBOL PIN
DESCRIPTION
data output; bit 1
D1
1
2
3
4
5
D0
data output; bit 0 (LSB)
analog ground
AGND
VRB
DEC
reference voltage bottom (decoupling)
decoupling input (internal stabilization
loop decoupling)
n.c.
6
7
not connected
handbook, halfpage
D1
D0
1
2
24
D2
23 D3
22 CE
21 TC
VCCA
positive supply voltage for analog
circuits (+5 V)
VI
8
9
analog voltage input
AGND
3
VRT
n.c.
O/UF
D7
reference voltage top (decoupling)
V
RB
4
10 not connected
5
20 DGND
V
DEC
n.c.
11 overflow/underflow data output
12 data output; bit 7 (MSB)
13 data output; bit 6
6
19
18
17
CCO
CCD
TDA8703/
TDA8703T
V
V
7
CCA
D6
8
VI
CLK
D5
14 data output; bit 5
V
9
16 CLK
15 D4
14 D5
RT
D4
15 data output; bit 4
CLK
CLK
VCCD
16 clock input
10
n.c.
17 complementary clock input
O/UF 11
12
18 positive supply voltage for digital
circuits (+5 V)
D6
D7
13
MLB034
VCCO
19 positive supply voltage for output
stages (+5 V)
DGND
TC
20 digital ground
21 input for two's complement output (TTL
level input, active LOW)
CE
22 chip enable input (TTL level input,
active LOW)
D3
D2
23 data output; bit 3
24 data output; bit 2
Fig.2 Pin configuration.
1996 Aug 26
5
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDA8703
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VCCA
PARAMETER
analog supply voltage
CONDITIONS
MIN.
−0.3
MAX.
+7.0
UNIT
V
VCCD
VCCO
digital supply voltage
−0.3
−0.3
−1.0
−1.0
−1.0
−0.3
−
+7.0
+7.0
+1.0
+1.0
+1.0
+7.0
2.0
V
V
V
V
V
V
V
output stages supply voltage
VCCA − VCCD supply voltage differences
VCCO − VCCD supply voltage differences
VCCA − VCCO supply voltage differences
VVI
input voltage range
referenced to AGND
VCLK/VCLK
AC input voltage for switching
(peak-to-peak value)
note 1; referenced to DGND
IO
output current
−
+10
mA
°C
°C
°C
Tstg
Tamb
Tj
storage temperature
operating ambient temperature
junction temperature
−55
0
+150
+70
−
+125
Notes
1. The circuit has two clock inputs CLK and CLK. There are four modes of operation:
a) TTL (mode 1); CLK decoupled to DGND by a capacitor. CLK input is TTL threshold voltage of 1.5 V and sampling
on the LOW-to-HIGH transition of the input clock signal.
b) TTL (mode 2); CLK decoupled to DGND by a capacitor. CLK input is TTL threshold voltage of 1.5 V and sampling
on the HIGH-to-LOW transition of the input clock signal.
c) AC drive modes (modes 3 and 4); When driving the CLK input directly and with any AC signal of 0.5 V
(peak-to-peak value) imposed on a DC level of 1.5 V, sampling takes place on the LOW-to-HIGH transition of the
clock signal. When driving the CLK input with such a signal, sampling takes place on the HIGH-to-LOW transition.
d) If one of the clock inputs is not driven, then it is recommended to decouple this input to DGND with a 100 nF
capacitor.
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL RESISTANCE
SYMBOL
Rth j-a
PARAMETER
from junction to ambient in free air
VALUE
UNIT
SOT101-1
SOT137-1
55
75
K/W
K/W
1996 Aug 26
6
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDA8703
CHARACTERISTICS
V
CCA = V7 − V3 = 4.5 V to 5.5 V; VCCD = V18 − V20 = 4.5 V to 5.5 V; VCCO = V19 − V20 = 4.5 V to 5.5 V; AGND and
DGND shorted together; VCCA − VCCD = −0.5 V to +0.5 V; VCCO − VCCD = −0.5 V to +0.5 V;
CCA − VCCD = −0.5 V to +0.5 V; Tamb = 0 °C to +70 °C; unless otherwise specified (typical values measured at
VCCA = VCCD = VCCO = 5 V and Tamb = 25 °C).
V
SYMBOL
Supply
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
VCCA
VCCD
VCCO
ICCA
analog supply voltage
4.5
4.5
4.2
−
5.0
5.0
5.0
28
5.5
5.5
5.5
36
V
digital supply voltage
V
output stages supply voltage
analog supply current
V
mA
mA
mA
ICCD
digital supply current
−
19
25
ICCO
output stage supply current
all outputs LOW
−
11
14
Inputs
CLOCK INPUT CLK AND CLK (note 1; REFERENCED TO DGND)
VIL
VIH
IIL
LOW level input voltage
HIGH level input voltage
LOW level input current
HIGH level input current
0
−
0.8
VCCD
−
V
2.0
−400
−
−
V
VCLK/VCLK = 0.4 V
VCLK/VCLK = 0.4 V
VCLK/VCLK = VCCD
fCLK/fCLK = 10 MHz
fCLK/fCLK = 10 MHz
−
µA
µA
µA
kΩ
pF
V
IIH
−
100
300
−
−
−
Zi
input impedance
input capacitance
−
4
Ci
−
4.5
−
−
VCLK − VCLK AC input voltage for switching
note 1; DC level = 1.5 V 0.5
2.0
(peak-to-peak value)
TC AND CE (REFERENCED TO DGND)
VIL
VIH
IIL
LOW level input voltage
HIGH level input voltage
LOW level input current
HIGH level input current
0
−
−
−
−
0.8
VCCD
−
V
2.0
V
VIL = 0.4 V
VIH = 2.7 V
−400
µA
µA
IIH
−
20
VI (ANALOG INPUT VOLTAGE REFERENCED TO AGND)
VVI(B)
VVI(0)
VOS(B)
VVI(T)
VVI(255)
VOS(T)
VVI(p-p)
IIL
input voltage (bottom)
input voltage
1.33
1.41
1.48
1.635
0.155
3.5
V
output code = 0
1.455 1.55
V
offset voltage (bottom)
input voltage (top)
VVI(0) − VVI(B)
0.125
3.2
−
V
3.36
V
input voltage
output code = 255
VI(T) − VVI(255)
3.115 3.26
3.385
0.115
1.75
−
V
offset voltage (top)
V
0.085
1.66
−
−
V
input voltage amplitude (peak-to-peak value)
LOW level input current
HIGH level input current
input impedance
1.71
0
V
VVI = 1.4 V
VVI = 3.6 V
fi = 1 MHz
fi = 1 MHz
µA
µA
kΩ
pF
IIH
60
−
120
10
14
180
−
Zi
Ci
input capacitance
−
−
1996 Aug 26
7
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDA8703
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Reference resistance
Rref
reference resistance
VRT to VRB
−
220
−
Ω
Outputs
DIGITAL OUTPUTS (D7 - D0) (REFERENCED TO DGND)
VOL
VOH
IOZ
LOW level output voltage
HIGH level output voltage
output current in 3-state mode
IO = 1 mA
0
−
−
−
0.4
V
IO = −0.4 mA
0.4 V < VO < VCCD
2.7
−20
VCCD
+20
V
µA
Switching characteristics (note 2; see Fig.3)
fCLK/fCLK maximum clock frequency
Analog signal processing (fCLK = 40 MHz)
40
−
−
MHz
B
−3 dB bandwidth
note 3
−
−
−
−
−
−
−
19.5
0.6
0.8
−
−
MHz
%
Gd
differential gain
note 4
−
φd
differential phase
note 4
−
deg
dB
f1
fundamental harmonics (full-scale)
harmonics (full-scale), all components
supply voltage ripple rejection
supply voltage ripple rejection
fi = 4.43 MHz
fi = 4.43 MHz
note 5
0
fall
−55
−28
1
−
dB
SVRR1
SVRR2
−25
2.5
dB
note 5
%/V
Transfer function
ILE
DC integral linearity error
−
−
−
−
−
±1
±1/2
±2
−
LSB
LSB
LSB
bits
DLE
AILE
EB
DC differential linearity error
AC integral linearity error
effective bits
−
note 6
−
fi = 4.43 MHz
7.1
Timing (note 7; see Figs 3 to 6; fCLK = 40 MHz)
tdS
sampling delay
−
6
−
−
−
−
−
−
−
2
ns
ns
ns
ns
ns
ns
ns
ns
tHD
output hold time
−
−
tdLH
tdHL
tdZH
tdZL
tdHZ
tdLZ
output delay time
LOW-to-HIGH transition
HIGH-to-LOW transition
enable-to-HIGH
8
10
20
25
20
20
12
output delay time
16
19
16
14
9
3-state output delay times
3-state output delay times
3-state output delay times
3-state output delay times
enable-to-LOW
disable-to-HIGH
disable-to-LOW
1996 Aug 26
8
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDA8703
Notes
1. The circuit has two clock inputs CLK and CLK. There are four modes of operation:
a) TTL (mode 1); CLK decoupled to DGND by a capacitor. CLK input is TTL threshold voltage of 1.5 V and sampling
on the LOW-to-HIGH transition of the input clock signal.
b) TTL (mode 2); CLK decoupled to DGND by a capacitor. CLK input is TTL threshold voltage of 1.5 V and sampling
on the HIGH-to-LOW transition of the input clock signal.
c) AC drive modes (modes 3 and 4); When driving the CLK input directly and with any AC signal of 0.5 V
(peak-to-peak value) imposed on a DC level of 1.5 V, sampling takes place on the LOW-to-HIGH transition of the
clock signal. When driving the CLK input with such a signal, sampling takes place on the HIGH-to-LOW transition.
d) If one of the clock inputs is not driven, then it is recommended to decouple this input to DGND with a 100 nF
capacitor.
2. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must not be less than 2 ns.
3. The −3 dB bandwidth is determined by the 3 dB reduction in the reconstructed output (full-scale signal at the input).
4. Low frequency ramp signal (VVI(p-p) = 1.8 V and fi = 15 kHz) combined with a sinewave input voltage (VVI(p-p) = 0.5 V,
fi = 4.43 MHz) at the input.
5. Supply voltage ripple rejection:
a) SVRR1; variation of the input voltage producing output code 127 for supply voltage variation of 1 V:
SVRR1 = 20 log (∆VVI(127) / ∆VCCA
)
b) SVRR2; relative variation of the full-scale range of analog input for a supply voltage variation of 1 V:
SVR2 = {∆(VVI(0) − VVI(255)) / (VVI(0) − VVI(255))} ÷ ∆VCCA
6. Full-scale sinewave (fi = 4.4 MHz; fCLK; fCLK = 27 MHz).
7. Output data acquisition:
.
a) Output data is available after the maximum delay of tdHL and tdLH
.
1996 Aug 26
9
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDA8703
Table 1 Output coding and input voltage (referenced to AGND; typical values)
BINARY OUTPUT BITS
TWO'S COMPLEMENT OUTPUT BITS
STEP
VVI(p-p)
O/UF D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Underflow <1.55
1
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
1
.
1
1
1
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
1
.
0
1.55
1
−
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
254
255
.
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
3.26
Overflow >3.26
Table 2 Mode selection
TC
X(1)
0
CE
1
D7-D0
O/UF
high impedance
high impedance
active
0
active; two’s complement
active; binary
1
0
active
Note
1. X = don’t care.
CLK
1.3 V
sample N + 1
sample N
sample N + 2
VI
t
HD
t
dS
2.4 V
D0 - D7
data N – 1
1.3 V data N
data N + 1
0.4 V
t
dLH
MEA105
t
dHL
Fig.3 Timing diagram.
10
1996 Aug 26
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDA8703
reference
level
(1.4 V)
CE
input
2.4 V
0.4 V
data
outputs
t
t
dHZ
dZH
dZL
t
t
dLZ
MLB035 - 1
Fig.4 3-state delay timing diagram.
V
CCO
2 kΩ
handbook, halfpage
V
CCO
2 kΩ
S1
handbook, halfpage
D0 to D7
C
5
D0 to D7
kΩ
15 pF
IN916
or
IN3064
IN916
or
IN3064
DGND
S2
MGD691
MBB955
DGND
Fig.6 Load circuit for timing measurement;
3-state outputs (CE: fi = 1 MHz; VVI = 3 V);
see Table 3.
Fig.5 Load circuit for timing measurement; data
outputs (CE = LOW).
1996 Aug 26
11
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDA8703
Table 3 Mode selection
TIMING MEASUREMENT
SWITCH S1
SWITCH S2
CAPACITOR
tdZH
tdZL
tdHZ
tdLZ
open
closed
closed
closed
closed
open
15 pF
15 pF
5 pF
closed
closed
5 pF
INTERNAL PIN CONFIGURATIONS
handbook, halfpage
handbook, halfpage
V
V
CCO
CCA
(x 90)
D7 to D0
O/U
V
I
DGND
AGND
MGD692
MLB037
Fig.7 TTL data and overflow/underflow outputs.
Fig.8 Analog inputs.
handbook, halfpage
V
CCO
handbook, halfpage
V
CCD
CE
TC
DGND
MLB039
DGND
MGD693
Fig.9 CE (3-state) input.
Fig.10 TC (two’s complement) input.
1996 Aug 26
12
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDA8703
V
CCA
V
RT
V
RB
DEC
AGND
MCD188
Fig.11 VRB, VRT and DEC.
V
CCD
V
CLK
ref
30 kΩ
30 kΩ
DGND
MCD189 - 1
Fig.12 CLK and CLK inputs.
1996 Aug 26
13
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDA8703
APPLICATION INFORMATION
Additional application information will be supplied upon request (please quote number FTV/8901).
1
2
3
4
5
6
7
8
9
D1
D0
D2
D3
CE
24
23
22
21
20
AGND
V
RB
TC
DGND
DEC
n.c.
22 nF
V
CCO
5 V
19
18
17
16
15
14
13
47 pF
(1)
TDA8703
TDA8703T
22 Ω
V
V
CCA
CCD
22 nF
4.7 µF
VI
CLK
100 pF
V
RT
CLK
D4
4.7 µF
22 nF
DGND
n.c. 10
O / UF 11
D7 12
D5
AGND
D6
MGA014 - 1
CLK should be decoupled to the DGND with a 100 nF capacitor, if a TTL signal is used on CLK (see Chapter “Characteristics”, note 1).
CLK and CLK can be used in a differential mode (see Chapter “Characteristics”, note 1).
VRB and VRT are decoupling pins for the internal reference ladder; do not draw current from these pins in order to achieve good linearity.
If it is required to use the TDA8703 in a parallel system configuration, the references (VRB and VRT) of each TDA8703 can be connected together.
Code 0 will be identical and code 255 will remain in the 1 LSB variation for each TDA8703.
Analog and digital supplies should be separated and decoupled.
Pins 6 and 10 should be connected to AGND in order to prevent noise influence.
(1) It is recommended to decouple VCCO through a 22 Ω resistor especially when the output data of the TDA8703 interfaces with a capacitive CMOS
load device.
Fig.13 Application diagram.
1996 Aug 26
14
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDA8703
PACKAGE OUTLINES
DIP24: plastic dual in-line package; 24 leads (600 mil)
SOT101-1
D
M
E
A
2
A
L
A
1
c
e
w M
Z
b
1
(e )
1
b
M
H
24
13
pin 1 index
E
1
12
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
Z
A
A
A
2
(1)
(1)
1
UNIT
mm
b
b
c
D
E
e
e
L
M
M
H
w
1
1
E
max.
min.
max.
max.
1.7
1.3
0.53
0.38
0.32
0.23
32.0
31.4
14.1
13.7
3.9
3.4
15.80
15.24
17.15
15.90
5.1
0.51
4.0
2.54
0.10
15.24
0.60
0.25
0.01
2.2
0.066
0.051
0.021
0.015
0.013
0.009
1.26
1.24
0.56
0.54
0.15
0.13
0.62
0.60
0.68
0.63
inches
0.20
0.020
0.16
0.087
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-11-17
95-01-23
SOT101-1
051G02
MO-015AD
1996 Aug 26
15
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDA8703
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
D
E
A
X
c
H
v
M
A
E
y
Z
24
13
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
12
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.30
0.10
2.45
2.25
0.49
0.36
0.32
0.23
15.6
15.2
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
mm
2.65
0.25
0.01
1.27
0.050
1.4
0.25 0.25
0.01
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.61
0.014 0.009 0.60
0.30
0.29
0.42
0.39
0.043 0.043
0.016 0.039
0.035
0.016
inches 0.10
0.055
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-11-17
95-01-24
SOT137-1
075E05
MS-013AD
1996 Aug 26
16
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDA8703
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
WAVE SOLDERING
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
Wave soldering techniques can be used for all SO
packages if the following conditions are observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
DIP
SOLDERING BY DIPPING OR BY WAVE
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
• The package footprint must incorporate solder thieves at
the downstream end.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
REPAIRING SOLDERED JOINTS
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
REPAIRING SOLDERED JOINTS
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
SO
REFLOW SOLDERING
Reflow soldering techniques are suitable for all SO
packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
1996 Aug 26
17
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDA8703
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1996 Aug 26
18
相关型号：
TDA8703T/C4
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