TDA8705A [NXP]
6-bit high-speed dual Analog-to-Digital Converter ADC; 6位高速双模拟数字转换器ADC
| 型号： | TDA8705A |
| 厂家： | 
NXP |
| 描述： | 6-bit high-speed dual Analog-to-Digital Converter ADC |
| 文件： | 总16页 (文件大小：114K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TDA8705A
6-bit high-speed dual
Analog-to-Digital Converter (ADC)
1996 Jan 12
Product specification
Supersedes data of November 1994
File under Integrated Circuits, IC02
Philips Semiconductors
Product specification
6-bit high-speed dual Analog-to-Digital
Converter (ADC)
TDA8705A
FEATURES
APPLICATIONS
High-speed analog-to-digital conversion for:
• 2 times 6-bit resolution
• Sampling rate up to 80 MHz
• DBS (Digital Broadcast Satellite)
• QPSK (Quadrature Phase Shift Keying) demodulation
• Video.
• High signal-to-noise ratio over a large analog input
frequency range (5.5 effective bits at 20 MHz full-scale
input at fclk = 80 MHz)
• TTL output
GENERAL DESCRIPTION
• Two separated inputs (AC-coupling)
• TTL compatible digital inputs
• Low-level AC clock input signal allowed
The TDA8705A is a 6-bit high-speed dual analog-to-digital
converter (ADC) for satellite video and other applications.
It converts the two analog input signals into two 6-bit
binary-coded digital words at a maximum sampling rate of
80 MHz. All digital inputs and outputs are TTL compatible,
although a low-level sine wave clock input signal is
allowed.
• Internal reference voltage regulator
(external reference regulation possible)
• Power dissipation only 250 mW (typical)
• Low analog input capacitance, no buffer amplifier
required
• No sample-and-hold circuit required.
QUICK REFERENCE DATA
SYMBOL
VCCA
PARAMETER
CONDITIONS
MIN.
4.75
TYP.
5.0
MAX.
5.25
UNIT
analog supply voltage
V
V
V
VCCD
VCCO
ICCA
digital supply voltage
4.75
4.75
20
10
10
−
5.0
5.0
27
5.25
5.25
32
output stages supply voltage
analog supply current
mA
ICCD
ICCO
ILE
digital supply current
14
18
mA
output stages supply current
DC integral linear error
DC differential linearity error
AC integral linearity error
maximum clock frequency
total power dissipation
14
18
mA
±0.25
±0.25
±0.5
−
±0.5
±0.5
±1.0
−
LSB
LSB
LSB
MHz
mW
DLE
AILE
fclk(max)
Ptot
−
note 1
−
80
−
250
−
Note
1. Full-scale sine wave (fi = 20 MHz; fclk = 80 MHz).
ORDERING INFORMATION
TYPE
PACKAGE
DESCRIPTION
plastic small outline package; 28 leads; body width 7.5 mm
NUMBER
NAME
VERSION
TDA8705AT
SO28
SOT136-1
1996 Jan 12
2
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V
V
V
DEC
10
CCA
8
CCD
2
CCO
21
REGULATOR
reference
voltage TOP
A
5
6
28 D5A
27 D4A
26 D3A
25 D2A
24 D1A
23 D0A
V
MSB
RTA
analog
voltage input
A
V
6
ANALOG -TO-DIGITAL
IA
data
outputs
LATCHES
TTL OUTPUTS
CONVERTER
A
R
INTA
reference
voltage BOTTOM
A
4
V
LSB
RBA
reference
voltage MIDDLE
A
9
V
RMA
reference
voltage TOP
B
TDA8705A
12
14
V
RTB
V
RMB
reference
voltage MIDDLE
B
R
INTB
20 D5B
19 D4B
18 D3B
17 D2B
16 D1B
15 D0B
MSB
analog
voltage input
11
13
V
6
ANALOG -TO-DIGITAL
IB
data
outputs
LATCHES
TTL OUTPUTS
CONVERTER
B
B
reference
voltage BOTTOM
B
V
LSB
RBB
CLOCK DRIVER
1
22
7
3
OGND
AGND
DGND
MLC374
CLK
output ground
analog ground
digital ground
ahdnbok,uflapegwidt
Fig.1 Block diagram.
Philips Semiconductors
Product specification
6-bit high-speed dual Analog-to-Digital
Converter (ADC)
TDA8705A
PINNING
SYMBOL PIN
DESCRIPTION
CLK
1
2
3
4
clock input
VCCD
DGND
VRBA
digital supply voltage (+5 V)
digital ground
reference voltage BOTTOM for
ADC A (decoupling)
VRTA
5
reference voltage TOP for ADC A
(decoupling)
VIA
6
7
8
9
analog input voltage for ADC A
analog ground
handbook, halfpage
CLK
1
2
3
4
5
6
7
8
9
D5A
27 D4A
28
AGND
VCCA
VRMA
V
CCD
analog supply voltage (+5 V)
D3A
D2A
DGND
26
25
reference voltage MIDDLE for ADC A
(decoupling)
V
RBA
DEC
VIB
10 decoupling input
V
24 D1A
23 D0A
22 OGND
RTA
11 analog input voltage for ADC B
V
IA
VRTB
12 reference voltage TOP for ADC B
(decoupling)
AGND
TDA8705A
V
V
21
VRBB
VRMB
13 reference voltage BOTTOM for
ADC B (decoupling)
CCO
CCA
V
20 D5B
19 D4B
RMA
14 reference voltage MIDDLE for ADC B
(decoupling)
DEC 10
V
D3B
D2B
D1B
11
18
17
16
IB
D0B
D1B
D2B
D3B
D4B
D5B
VCCO
15 data output; bit 0 (LSB), ADC B
16 data output; bit 1, ADC B
17 data output; bit 2, ADC B
18 data output; bit 3, ADC B
19 data output; bit 4, ADC B
20 data output; bit 5 (MSB), ADC B
V
V
RTB 12
13
14
RBB
V
15 D0B
RMB
MLC375
21 supply voltage for output stages
(+5 V)
OGND
D0A
D1A
D2A
D3A
D4A
D5A
22 output ground
23 data output; bit 0 (LSB), ADC A
24 data output; bit 1, ADC A
25 data output; bit 2, ADC A
26 data output; bit 3, ADC A
27 data output; bit 4, ADC A
28 data output; bit 5 (MSB), ADC A
Fig.2 Pin configuration.
1996 Jan 12
4
Philips Semiconductors
Product specification
6-bit high-speed dual Analog-to-Digital
Converter (ADC)
TDA8705A
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VCCA
PARAMETER
analog supply voltage
CONDITIONS
note 1
MIN.
−0.3
MAX.
+7.0
UNIT
V
V
V
V
VCCD
VCCO
∆VCC
digital supply voltage
note 1
note 1
−0.3
−0.3
−1.0
+7.0
+7.0
+1.0
output stages supply voltage
supply voltage differences between VCCA
and VCCD
∆VCC
∆VCC
supply voltage differences between VCCO
and VCCD
−1.0
−1.0
+1.0
+1.0
V
V
supply voltage differences between VCCA
and VCCO
VI
input voltage
referenced to AGND
referenced to DGND
−0.3
+7.0
V
V
Vclk(p-p)
AC input voltage for switching
(peak-to-peak value)
−
VCCD
IO
output current
−
10
mA
°C
°C
°C
Tstg
Tamb
Tj
storage temperature
operating ambient temperature
junction temperature
−55
0
+150
+70
+150
−
Note
1. The supply voltages VCCA, VCCO and VCCD may have any value between −0.3 V and +7 V provided the difference
between VCCA, VCCO and VCCD is between −1 V and +1 V.
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
PARAMETER
VALUE
UNIT
thermal resistance from junction to ambient in free air
70
K/W
1996 Jan 12
5
Philips Semiconductors
Product specification
6-bit high-speed dual Analog-to-Digital
Converter (ADC)
TDA8705A
CHARACTERISTICS
V
CCA = V8 to V7 = 4.75 to 5.25 V; VCCD = V2 to V3 = 4.75 to 5.25 V; VCCO = V21 to V22 = 4.75 to 5.25 V; AGND, OGND
and DGND shorted together; VCCA to VCCD = −0.25 to +0.25 V; VCCO to VCCD = −0.25 to +0.25 V;
CCA to VCCO = −0.25 to +0.25 V; Tamb = 0 to +70 °C; typical values measured at VCCA = VCCD = VCCO = 5 V and
Tamb = 25 °C; CL = 15 pF; unless otherwise specified.
V
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VCCA
VCCD
VCCO
ICCA
analog supply voltage
4.75
4.75
4.75
20
5.0
5.25
5.25
5.25
32
V
V
V
digital supply voltage
5.0
5.0
27
14
14
output stages supply voltage
analog supply current
mA
mA
mA
ICCD
digital supply current
10
18
ICCO
output stages supply current
10
18
Inputs
CLOCK INPUT CLK; REFERENCED TO DGND; note 1
VIL
VIH
IIL
LOW level input voltage
HIGH level input voltage
LOW level input current
HIGH level input current
input impedance
0
−
−
−
−
2
2
0.8
VCCD
+1
20
−
V
2.0
−1
−
V
Vclk = 0.4 V
µA
µA
kΩ
pF
IIH
ZI
Vclk = 2.7 V
fclk = 80 MHz
fclk = 80 MHz
−
CI
input capacitance
−
−
VI ANALOG INPUT VOLTAGE FOR A AND B; REFERENCED TO AGND
RI
DC parallel input resistance
parallel input capacitance
crosstalk between VIA and VIB
20
−
−
−
−
−
kΩ
pF
dB
CI
fi = 20 MHz
fi = 20 MHz
1.5
−
αCT
40
Reference voltages for the resistor ladder (A and B); see Table 1
VRB
reference voltage BOTTOM
reference voltage TOP
1.9
2.8
0.85
−
2.0
2.1
3.0
0.95
−
V
VRT
2.9
V
Vdiff
differential reference voltage VRT − VRB
reference current
0.90
2
V
Iref
mA
Ω
RLAD
TCRLAD
VosB
VosT
Vi(p-p)
resistor ladder
−
450
3280
200
200
0.50
−
temperature coefficient of the resistor ladder
offset voltage BOTTOM
−
−
ppm
mV
mV
V
note 2
note 2
−
−
offset voltage TOP
−
−
input voltage amplitude (peak-to-peak value)
0.45
0.55
Outputs (A and B)
DIGITAL OUTPUTS D5 TO D0 (REFERENCED TO DGND)
VOL
VOH
LOW level output voltage
HIGH level output voltage
IO = 1 mA
0
−
−
0.4
V
V
IO = −1 mA
2.4
VCCD
1996 Jan 12
6
Philips Semiconductors
Product specification
6-bit high-speed dual Analog-to-Digital
Converter (ADC)
TDA8705A
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Switching characteristics
CLOCK INPUT CLK; note 1; see Fig.3
fclk(max)
tCPH
maximum clock frequency
clock pulse width HIGH
clock pulse width LOW
80
−
−
MHz
5.5
5.5
−
−
−
−
ns
ns
tCPL
Analog signal processing
LINEARITY
ILE
DC integral linearity error
−
±0.25 ±0.5
±0.25 ±0.5
LSB
LSB
LSB
LSB
DLE
AILE
OFE
DC differential linearity error
AC integral linearity error
offset error between A and B
−
note 3
fi = 10 MHz;
clk = 40 MHz; note 4
−
±0.5
±1.0
±2
±1
−
f
GE
gain error between A and B
fi = 10 MHz;
fclk = 40 MHz; note 4
±1
−
−
±2
LSB
MID
middle scale output code (A and B)
31
32
BANDWIDTH; fclk = 80 MHz
B
−0.5 dB analog bandwidth
full-scale sine
wave; note 5
−
−
−
50
8
−
−
−
MHz
ns
tSTLH
tSTHL
analog input settling time LOW-to-HIGH
analog input settling time HIGH-to-LOW
full-scale square
wave; Fig.4; note 6
full-scale square
5
ns
wave; Fig.4; note 6
HARMONICS; fclk = 40 MHZ; see Fig.5
h1
fundamental harmonics (full scale)
fi = 20 MHz
fi = 20 MHz
−
−
0
dB
hall
harmonics (full scale);
all components
second harmonics
third harmonics
−
−
−
−45
−41
−39
−
dB
dB
dB
−
THD
total harmonic distortion
fi = 20 MHz
−34
SIGNAL-TO-NOISE RATIO; note 7; see Fig.5
S/N signal-to-noise ratio (full scale)
without harmonics;
33
36
−
dB
fclk = 80 MHz;
fi = 20 MHz
EFFECTIVE BITS; note 7; see Fig.5
EB
effective bits
f
clk = 80 MHz
fi = 10 MHz
fi = 20 MHz
fi = 30 MHz
−
−
−
5.7
5.5
5.1
−
−
−
bits
bits
bits
1996 Jan 12
7
Philips Semiconductors
Product specification
6-bit high-speed dual Analog-to-Digital
Converter (ADC)
TDA8705A
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
TWO-TONE; note 8
TTIR
two-tone intermodulation rejection
fclk = 80 MHz
−
48
−
dB
BIT ERROR RATE
BER
bit error rate
fclk = 80 MHz;
fi = 20 MHz;
VI = ±16 LSB at
code 32
−
10−12
−
times/
samples
Timing (fclk = 80 MHz; CL = 15 pF); note 9; see Fig.3
tds
th
sampling delay time
output hold time
−
5
−
−
−
−
2
ns
ns
ns
−
td
output delay time
11
Notes
1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must not be less than 1 ns.
2. Analog input voltages producing code 00 up to and including 3F:
a) VosB (voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00 and
the reference voltage BOTTOM (VRB) at Tamb = 25 °C.
b) VosT (voltage offset TOP) is the difference between VRT (reference voltage TOP) and the analog input which
produces data outputs equal to 3F at Tamb = 25 °C.
3. Full-scale sine wave (fi = 20 MHz; fclk = 80 MHz).
4. The Offset Error (OFE) and Gain Error (GE) are determined by taking results from a simultaneous acquisition on both
ADCs of a sine wave greater than full-scale. The occurrences of code 0 and 63 are used to calculate the OFE
(mid-scale-to-mid-scale) and the GE (amplitude difference) between the two converters A and B.
5. The −0.5 dB analog bandwidth is determined by the 0.5 dB reduction in the reconstructed output, the input being a
full-scale sine wave. It is determined with a beat frequency method; no glitches occurrence.
6. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale
input (square-wave signal) in order to sample the signal and obtain correct output data.
7. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8K acquisition points per period.
The calculation takes into account all harmonics and noise up to half of the clock frequency (NYQUIST frequency).
Conversion to signal-to-noise ratio: S/N = EB × 6.02 + 1.76 dB.
8. Intermodulation measured relative to either tone with analog input frequencies of 20.0 MHz and 20.1 MHz. The two
input signals have the same amplitude and the total amplitude of both signals provides full scale to the converter.
9. Output data acquisition: the output data is available after the maximum delay time of td.
1996 Jan 12
8
Philips Semiconductors
Product specification
6-bit high-speed dual Analog-to-Digital
Converter (ADC)
TDA8705A
Table 1 Output coding and input voltage (typical values; referenced to AGND)
BINARY OUTPUT BITS
STEP
VI(p-p) A or B (V)
D5
D4
D3
D2
D1
D0
Underflow
<2.2
2.2
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
1
.
0
1
2.208
.
.
.
62
.
.
.
.
.
.
.
2.692
2.7
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
63
Overflow
>2.7
t
CPL
t
CPH
1.4 V
CLK
sample N
sample N + 1
sample N + 2
V
l(n)
t
t
ds
h
2.4 V
1.4 V
0.4 V
DATA
D0 to D5
DATA
N - 2
DATA
N - 1
DATA
N
DATA
N + 1
t
d
MLC115
Fig.3 Timing diagram for data output.
t
t
STLH
STHL
50 %
code 63
V
I(n)
50 %
code 0
2 ns
2 ns
CLK
50 %
50 %
MLC116
0.5 ns
0.5 ns
Fig.4 Analog input settling-time diagram.
9
1996 Jan 12
Philips Semiconductors
Product specification
6-bit high-speed dual Analog-to-Digital
Converter (ADC)
TDA8705A
MLC376
0
amplitude
(dB)
20
40
60
80
100
120
40.2
45.2
50.2
55.2
60.3
65.3
70.3
75.3
80.4
f (MHz)
Effective bits: 5.54; THD = −39.89 dB;
Harmonic levels (dB): 2nd = −46.51; 3rd = −41.21; 4th = −80.65; 5th = −60.16; 6th = −54.51.
Fig.5 Typical Fast Fourier Transform (fclk = 80 MHz; fi = 20 MHz).
1996 Jan 12
10
Philips Semiconductors
Product specification
6-bit high-speed dual Analog-to-Digital
Converter (ADC)
TDA8705A
APPLICATION INFORMATION
100 nF
CLK
D5A
D4A
D3A
D2A
D1A
D0A
OGND
1
2
3
4
5
6
7
28
27
26
25
24
23
22
21
20
19
18
17
16
V
CCD
5 V
DGND
V
100 nF
RBA
V
100 nF
(1)
RTA
C
V
LA
IA
input A
AGND
5 V
TDA8705A
8
V
V
CCO
CCA
5 V
100 nF
100 nF
V
D5B
D4B
D3B
D2B
D1B
D0B
RMA
9
(2)
1 nF
DEC
100 nF
10
11
12
13
14
(1)
C
V
LB
IB
input B
V
100 nF
100 nF
100 nF
RTB
V
RBB
V
RMB
15
MLC377
The analog and digital supplies should be separated and decoupled.
VRT(n), VRM(n) and VRB(n) and DEC inputs are decoupled to AGND.
(1) In the event of AC-coupling, CLA and CLB values are chosen in accordance with the classical low frequencies cut-off formulae
1
fCL
=
where input resistance R is the value measured under DC conditions.
I
-------------------------------------
2 × π × RI × CL
In the event of DC-coupling, CLA and CLB capacitors are omitted. The DC biassing and AC modulation signal directly applied to inputs (pin 6 and 11),
must be in the range of VRT(n) − VRB(n)
.
(2) When pin 10 (DEC) is short-circuited to AGND, an external regulator can be connected to VRT(n) and VRB(n)
.
Fig.6 Application diagram.
1996 Jan 12
11
Philips Semiconductors
Product specification
6-bit high-speed dual Analog-to-Digital
Converter (ADC)
TDA8705A
PACKAGE OUTLINE
SO28: plastic small outline package; 28 leads; body width 7.5 mm
SOT136-1
D
E
A
X
c
y
H
v
M
A
E
Z
28
15
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
14
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.30
0.10
2.45
2.25
0.49
0.36
0.32
0.23
18.1
17.7
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
mm
2.65
1.27
0.050
1.4
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.71
0.014 0.009 0.69
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches 0.10
0.055
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-01-24
97-05-22
SOT136-1
075E06
MS-013AE
1996 Jan 12
12
Philips Semiconductors
Product specification
6-bit high-speed dual Analog-to-Digital
Converter (ADC)
TDA8705A
SOLDERING
Introduction
Wave soldering
Wave soldering techniques can be used for all SO
packages if the following conditions are observed:
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
• The package footprint must incorporate solder thieves at
the downstream end.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Reflow soldering
Reflow soldering techniques are suitable for all SO
packages.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Repairing soldered joints
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
1996 Jan 12
13
Philips Semiconductors
Product specification
6-bit high-speed dual Analog-to-Digital
Converter (ADC)
TDA8705A
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1996 Jan 12
14
Philips Semiconductors
Product specification
6-bit high-speed dual Analog-to-Digital
Converter (ADC)
TDA8705A
NOTES
1996 Jan 12
15
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Telex 35000 phtcnl, Fax. +31-40-2724825
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SCDS47
© Philips Electronics N.V. 1996
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All rights are reserved. Reproduction in whole or in part is prohibited without the
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Fax. (021)577035/5874546
537021/1100/02/pp16
Date of release: 1996 Jan 12
9397 750 00569
Document order number:
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