TDA8741 [NXP]
Satellite sound circuit with noise reduction; 卫星音响电路降噪
| 型号： | TDA8741 |
| 厂家： | 
NXP |
| 描述： | Satellite sound circuit with noise reduction |
| 文件： | 总24页 (文件大小：438K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TDA8741; TDA8741H
Satellite sound circuit with noise
reduction
October 1994
Product specification
Supersedes data of November 1992
File under Integrated Circuits, IC02
Philips Semiconductors
Philips Semiconductors
Product specification
Satellite sound circuit with noise reduction
TDA8741; TDA8741H
FEATURES
APPLICATIONS
• Demodulation of main audio signal using wide band PLL
(lock range selectable)
• Satellite receivers
• TV sets
• Demodulation of secondary audio signals using wide
band PLL
• Video recorders.
• Noise reduction of the secondary audio signals
GENERAL DESCRIPTION
• Output selection: stereo, language 1, language 2, main
The TDA8741; TDA8741H is a multi-function sound IC for
use in satellite receivers, television sets and video
recorders. The pin numbers given in parenthesis
throughout this document refer to the QFP44 package.
audio and external
• Mute control
• Line outputs (SCART level).
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS MIN.
TYP. MAX. UNIT
Supply
VP
supply voltage
8
12
13.2
2.0
V
Main channel
VIN3(rms)
input sensitivity pin 18 (14) (RMS value)
lock range PLL demodulator
either
S/N(A) = 40 dB
−
1.0
mV
∆fOM
5.5
10.0
−9
−
7.5
11.5
−4
MHz
MHz
dBV
dB
or
−
VOM
output voltage pin 23 (19)
signal-to-noise ratio
−6
70
S/N(A)
A-weighted
62
−
Secondary channels
VIN1,IN2(rms) input sensitivity pins 8 and 16 (3 and 11) (RMS value) S/N(A) = 40 dB
−
0.8
−
1.5
11.5
−4
mV
∆fOS1,2
VOR,OL
S/N(A)
lock range PLL demodulators
output voltage pins 24 and 25 (20 and 21)
signal-to-noise ratio
10.0
−8
72
MHz
dBV
dB
−6
80
A-weighted
−
Crosstalk
αS/M
crosstalk from secondary to main channel
crosstalk from main to secondary channel
crosstalk between secondary channels
−
−
−
74
74
74
−
−
−
dB
dB
dB
αM/S
αS/S
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
TDA8741
SDIP42
QFP44(1)
plastic shrink dual in-line package; 42 leads (600 mil)
SOT270-1
SOT307-2
TDA8741H
plastic quad flat package; 44 leads (lead length 1.3 mm);
body 10 × 10 × 1.75 mm
Note
1. When using IR reflow soldering it is recommended that the Drypack instructions in the “Quality Reference Handbook”
(order number 9398 510 63011) are followed.
October 1994
2
Philips Semiconductors
Product specification
Satellite sound circuit with noise reduction
TDA8741; TDA8741H
BLOCK DIAGRAM
The pin numbers in parenthesis refer to the QFP44 package.
Fig.1 Block diagram.
October 1994
3
Philips Semiconductors
Product specification
Satellite sound circuit with noise reduction
TDA8741; TDA8741H
PINNING
PIN
SDIP42
PIN
QFP44
SYMBOL
DESCRIPTION
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
1
1
not connected
not connected
not connected
not connected
not connected
not connected
2
5
3
7
4
9
5
12
39
2
6
MCS
IN-1
7
main channel PLL lock-in range select/disable
intercarrier input for secondary Channel 1 (left)
ground for HF section
8
3
HFGND
n.c.
9
4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
6
not connected
SCD
secondary channels PLLs disable
not connected
n.c.
41
8
MUTE
n.c.
mute switch
42
10
11
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
not connected
Osel L
IN-2
output select switch bit 1 (left)
intercarrier input for secondary Channel 2 (right)
output select switch bit 2 (right)
intercarrier input for main channel
decoupling capacitor for reference voltage
de-emphasis capacitor for main channel
audio pass-through capacitor input for main channel
positive supply voltage
Osel R
IN-3
VREF
CD M
CC M
VP
OM
main channel output
OR
right channel output
OL
left channel output
EXT/INT
EXTR
EXTL
CATT/REC R
RECTR
CNR D R
CD R
output switch bit 3 (external/internal)
external audio input (right)
external audio input (left)
attack/recovery capacitor (right)
rectifier DC decoupling (right)
noise reduction de-emphasis capacitor (right)
fixed de-emphasis capacitor (right)
audio pass-through capacitor input for right channel
ground for AF section
CC R
AFGND
CC L
audio pass-through capacitor input for left channel
fixed de-emphasis capacitor (left)
noise reduction de-emphasis capacitor (left)
rectifier DC decoupling (left)
CD L
CNR D L
RECTL
CATT/REC L
attack/recovery capacitor (left)
October 1994
4
Philips Semiconductors
Product specification
Satellite sound circuit with noise reduction
TDA8741; TDA8741H
PIN
SDIP42
PIN
QFP44
SYMBOL
CDC L
DESCRIPTION
DC decoupling capacitor (left)
40
41
42
−
36
37
38
43
44
CDC M
CDC R
n.c.
DC decoupling capacitor (main)
DC decoupling capacitor (right)
not connected
n.c.
−
not connected
Fig.2 Pin configuration (SDIP42).
5
October 1994
Philips Semiconductors
Product specification
Satellite sound circuit with noise reduction
TDA8741; TDA8741H
Fig.3 Pin configuration (QFP44).
October 1994
6
Philips Semiconductors
Product specification
Satellite sound circuit with noise reduction
TDA8741; TDA8741H
external mixer and oscillator-frequency synthesizer. In this
event the lock-in range of the PLL should be switched to
10.0 to 11.5 MHz. The IF signal is applied to the main
channel input, pin 18 (14) via a 10.7 MHz ceramic
bandpass filter.
FUNCTIONAL DESCRIPTION
Satellite sound
The baseband signal coming from a satellite tuner
contains the demodulated video signal plus a number of
sound carriers to facilitate reception of a
The filtered signal is AC-coupled to a limiter/amplifier and
then to a PLL demodulator. The PLL FM demodulator
ensures that the demodulator is alignment-free. High gain
and DC error signals from the PLL, which are
superimposed on the demodulator output, require DC
decoupling. A buffer amplifier is used to amplify the signal
to the same level as the secondary channels and
decouples DC using an electrolytic capacitor connected to
pin 41 (37). The demodulator output signal is fed to pin 20
(16) via an internal resistor. The output signal can be
de-emphasized by means of this resistor and an external
capacitor connected to ground.
PAL/NTSC/SECAM satellite signal.
Nearest to the video signal is the main sound carrier which
carries the single channel sound related to the video. This
is an FM modulated carrier with a fixed pre-emphasis. The
carrier frequency can be in the range of 5.8 to 6.8 MHz.
Additionally, a number of optional secondary sound
carriers may be present which can be used for stereo or
multi-language sound related to the video, or for unrelated
radio sound. These carriers are also FM modulated, but for
better sound quality (improved signal-to-noise
performance) broadcast satellites (e.g. ‘ASTRA’) use a
noise reduction system (adaptive pre-emphasis circuit,
combined with a fixed pre-emphasis).
Capacitor value = de-emphasis time constant per 1500
(for 50 µs: 33 nF).
From here the signal is fed to the output selectors. The
signal is amplified to 500 mV (RMS) (i.e. −6 dBV) in the
output amplifiers.
These secondary carrier frequencies can be in the range
of 6.30 to 8.28 MHz. For accurate tuning to the many
sound carriers an external frequency synthesizer and
mixer is used to transpose the sound carriers to
intermediate frequencies of 10.7 and 10.52 MHz.
Secondary channels
An external mixer and oscillator frequency synthesizer
transfers the secondary sound carriers to fixed
intermediate frequencies e.g. 10.7 and 10.52 MHz. Two
secondary channel inputs are available at pins 8 and 16 (3
and 11). The signals are routed to the inputs via external
ceramic bandpass filters which are tuned to the required
intermediate frequencies.
The TDA8741; H contains all circuitry for processing the
main channel and for two secondary channels, from IF
signal to line (SCART) output drivers. The desired
frequencies can be routed to the TDA8741; H via
bandpass filters.
Main channel (see Fig.1)
For stereo applications the TDA8741; TDA8741H contains
two identical secondary sound processing channels.
Secondary Channel 1 will also be referred to as ‘LEFT’ or
‘LANGUAGE 1’ and secondary Channel 2 will also be
referred to as ‘RIGHT’ or ‘LANGUAGE 2’.
The lock-in range of the main channel PLL can be
switched between 5.5 to 7.5 MHz, PLL off and 10.0 to
11.5 MHz using the MCS signal at pin 7 (2) [when pin 7 (2)
is at logic 0, being a voltage from 0 to 1.2 V, the lock-in
range = 5.5 to 7.5 MHz; when pin 7 (2) is at logic 1, being
a voltage from 3.5 V until VP, the lock-in range = 10.0 to
11.5 MHz; when pin 7 (2) is in the mid voltage position,
being a voltage from 1.8 to 2.8 V, the main channel PLL is
switched off]. The voltage is then determined by the
resistor divider at this pin between VP and ground.
From the inputs the signals are coupled to
limiter/amplifiers and then to the PLL demodulators.
Processing is similar to the main channel. The
demodulator output signal is amplified in a buffer amplifier
and DC decoupled using electrolytic capacitors connected
to pins 40 (36) (left) and 42 (38) (right). The output level is
set with a resistor connected in series with the capacitor.
If only one fixed carrier frequency for the main channel is
to be demodulated (e.g. 6.5 MHz), the lock-in range of the
PLL should be switched to 5.5 to 7.5 MHz. The baseband
signal is applied to the main channel input, pin 18 (14) via
a 6.5 MHz ceramic bandpass filter. Alternatively, if there is
a requirement to demodulate different main channel
frequencies, these frequencies can be transferred to a
fixed intermediate frequency (e.g. 10.7 MHz) using an
High frequency components in the amplified PLL output
signal are filtered out in the audio LPF block (4th order
Butterworth low-pass filter) to prevent unwanted influence
on the noise reduction.
October 1994
7
Philips Semiconductors
Product specification
Satellite sound circuit with noise reduction
TDA8741; TDA8741H
NOISE REDUCTION (NR)
ABBREVIATIONS
fMOD = modulating frequency.
The noise reduction can be regarded as an input
level-dependent low-pass filter (adaptive de-emphasis
system) followed by a fixed de-emphasis. With maximum
input level (0 dB) the frequency response of the first part
(i.e. without the fixed de-emphasis) is virtually flat. As the
input level is lowered by x-dB, the higher output
frequencies will be reduced an extra x-dB with respect to
the lower frequencies (1 : 2 expansion).
∆fM = frequency deviation of the main Channel.
∆fS1 = frequency deviation of secondary Channel 1 (left).
∆fS2 = frequency deviation of secondary Channel 2 (right).
fOM = carrier frequency of main Channel.
fOS1 = carrier frequency of secondary Channel 1.
fOS2 = carrier frequency of secondary Channel 2.
LPF = Low-Pass Filter.
The NR output signal is fed to pin 36 (32) (left) and pin 32
(28) (right) via an internal resistor.
Fixed de-emphasis is achieved by these resistors and
external capacitors connected to ground. The signals are
DC decoupled via pins 36/35 (32/31) and 32/33 (28/29)
and then routed to the output selectors.
NR = Noise Reduction.
PLL = Phase-Locked-Loop.
OUTPUT SELECTION
With the output selector (see Table 1) the outputs at
pins 25 and 24 (21 and 20) can be switched to the different
channels. Both outputs can be switched to both secondary
channels, to the main channel and to the external inputs at
pin 28 and 27 (24 and 23) for IC chaining purposes.
Pin 23 (19) is a separate output which delivers the main
channel only, thereby creating the possibility of having
three different output channels simultaneously e.g. for use
in hi-fi VCRs.
The outputs at pins 25 and 24 (21 and 20) can be muted
by setting the MUTE signal at pin 13 (8) to logic 1 (switch
positions 6 and 7).
The output at pin 23 (19) can be muted by setting the
MUTE signal and the EXT/INT signal at pin 26 (22) both
logic 1 (switch position 7).
All outputs at pins 23, 24 and 25 (19, 20 and 21) are line
drivers with SCART level capability and are short-circuit
protected by 125 Ω output resistors.
Output level of all channels = −6 dBV typical when
frequency deviation of FM signal is 54% of maximum
frequency deviation (i.e. 0.54 × 85 kHz = 46 kHz for the
main channel and 0.54 × 50 kHz = 27 kHz for the
secondary channels) at 1 kHz modulation frequency
(reference level).
October 1994
8
Philips Semiconductors
Product specification
Satellite sound circuit with noise reduction
TDA8741; TDA8741H
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VP
PARAMETER
supply voltage
CONDITIONS
note 1
MIN.
MAX.
13.2
UNIT
0
0
V
V
VI
input voltage level on pins 8 and 16
(3 and 11)
note 2
1
Vn
voltage on pins 11, 13, 15, 17, 20, 21,
23 to 26, 31, 33, 35, 37, 40, 41, and 42
(6, 8, 10, 13, 16, 17, 19, 20 to 22, 27, 29,
31, 33, 36, 37 and 38)
note 2
0
9
V
Vn
voltage on pins 7, 18, 19, 27 to 30, 32,
36, 38 and 39 (2, 14, 15, 23 to 26, 28,
32, 34 and 35)
note 1
0
VP
V
Tstg
storage temperature
−55
−20
+150
+70
°C
°C
Tamb
operating ambient temperature
Notes
1. All voltages referenced to ground pins 9 and 34 (4 and 30).
2. All voltages referenced to ground pins 9 and 34 (4 and 30). These voltages must not exceed VP or maximum value
at any time.
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
PARAMETER
VALUE
UNIT
thermal resistance from junction to ambient in free air
SDIP42
QFP44
53
69
K/W
K/W
DC CHARACTERISTICS
All voltages referenced to ground at pins 9 and 34 (4 and 30). Measured in test circuit Fig.4; VP = 12 V; Tamb = 25 °C;
∆fM = ∆fS1 = ∆fS2 = 0 kHz (no modulation); fOM = 6.5 MHz; fOS1 = 10.7 MHz; fOS2 = 10.52 MHz; HF level at pin 18 (14):
40 mV (RMS); HF level at pins 8 and 16 (3 and 11): 20 mV (RMS); MCS = logic 0 [V7 (V2) = 0 V];
SCD = logic 0 [V11 (V6) = 0 V]; unless otherwise specified.
SYMBOL
VP
PARAMETER
MIN.
8.0
TYP.
12
MAX.
13.2
UNIT
supply voltage
V
IP
supply current
−
−
−
38
−
45
600
−
mA
mW
V
Ptot
Vn
total power dissipation
voltage on pins 20, 21, 23, 24, 25, 27, 28, 30, 32, 33, 35, 36
and 38 (16, 17, 19, 20, 21, 23, 24, 26, 28, 29, 31, 32 and 34)
3.8
VREF
input reference voltage on pin 19 (15)
voltage on pins 8 and 16 (3 and 11)
voltage on pins 40 and 42 (36 and 38)
voltage on pin 41 (37)
3.7
−
3.8
0
3.9
−
V
VIN1,IN2
VCDCL,CDCR
VCDCM
IIN3
V
−
3.0
2.8
−
−
V
−
−
V
input current at pin 18 (14)
−
1
µA
October 1994
9
Philips Semiconductors
Product specification
Satellite sound circuit with noise reduction
TDA8741; TDA8741H
AC CHARACTERISTICS
All voltages referenced to ground at pins 9 and 34 (4 and 30). Measured in test circuit Fig.4; VP = 12 V; Tamb = 25 °C;
fMOD = 1 kHz; fOM = 6.5 MHz; ∆fM = 46 kHz; ∆fS1 = ∆fS2 = 27 kHz (reference levels); fOS1 = 10.7 MHz;
fOS2 = 10.52 MHz; HF level at pin 18 (14): 40 mV (RMS); HF level at pins 8 and 16 (3 and 11): 20 mV (RMS);
MCS = logic 0 [V7 (V2) = 0 V]; SCD = logic 0 [V11 (V6) = 0 V]; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Main channel - HF input pin 18 (14) and limiter
VIN3(rms)
VIN3(rms)
RIN3
input sensitivity (RMS value)
input signal level (RMS value)
input resistance
S/N(A) = 40 dB
−
−
−
1.0
−
2.0
200
−
mV
mV
kΩ
15
Main channel - PLL FM demodulator and DC decoupling amplifier
fCCO
free-running frequency
−
6.5
10.7
−
−
MHz
MHz
MHz
MCS = logic 1
note 1
−
−
∆fOM
lock range of PLL
5.5
10.0
7.5
MCS = logic 1; note 1
−
11.5 MHz
1.7 kΩ
RCDM
output resistance for 50 µs
1.24 1.5
de-emphasis pin 20 (16)
VCDM
output voltage pin 20 (16)
−18.5 −16.0 −14.5 dBV
∆VCDM
spread of PLL output voltage
over lock range pin 20 (16)
−
−
±1
dB
RCCM
input resistance of output
amplifier pin 21 (17)
95
150
200
kΩ
Main channel - overall performance (output selector in position 4)
VOM,OR,OL
output voltage pins 23, 24 and
25 (19, 20 and 21)
all PLLs locked
−9
−6
−4
dBV
THD
total harmonic distortion
signal-to-noise ratio
all PLLs locked
−
0.1
70
0.5
%
S/N(A)
A-weighted;
62
−
dB
all PLLs locked
15 kHz frequency response
with respect to 1 kHz pin 23 (19) connected
no de-emphasis
−0.5
0
+0.5 dB
VOM (15 kHz)
-------------------------------
VOM (1 kHz)
ROM,OR,OL
output resistance pins 23, 24
and 25 (19, 20 and 21)
92
−
125
74
−
150
−
Ω
αS/M
crosstalk attenuation from
secondary channels to main
note 2
dB
dB
dB
MUTEatt
SVRR
mute attenuation
output selector in
position 7
74
−
−
supply voltage ripple rejection
VRR = 100 mV; fi = 70 Hz
35
−
Secondary channels 1 and 2 - HF inputs pins 8 and 16 (3 and 11) and limiters
VIN1,IN2(rms)
Vi(rms)
input sensitivity (RMS value)
input signal level (RMS value)
input resistance
S/N(A) = 40 dB
−
0.8
−
1.5
mV
mV
Ω
−
200
380
RIN1,IN2
280
330
October 1994
10
Philips Semiconductors
Product specification
Satellite sound circuit with noise reduction
TDA8741; TDA8741H
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Secondary channels 1 and 2 - PLL FM demodulators
fCCO1
free running frequency PLL1
free running frequency PLL2
lock range of PLLs
−
10.7
10.52
−
−
−
MHz
MHz
fCCO2
−
∆fOS1/2
RS1,S2
note 3
10
0
11.5 MHz
series resistance for optimum
frequency response adjustment
0.68 2.2
kΩ
mV
dB
VCDCL,CDCR(rms)
PLL output voltage pins 40 and pins to be left open-circuit −
42 (36 and 38) (RMS value)
9
−
∆VCDCL,CDCR
spread of PLL output voltage
over lock range
−
−
±1
Secondary channels - overall performance of LPF and NR (output selectors in position 1)
RO
output resistance for 75 µs
de-emphasis pins 36 and 32 (32
and 28)
1.9
2.3
2.6
kΩ
kΩ
Ri
input resistance of output
amplifiers pins 35 and 33
(31 and 29)
95
150
200
VOL,OR
UBS
output voltage level pins 25 and note 4
24 (21 and 20)
−8
−1
−6
−4
dBV
dB
unbalance voltage outputs
pins 25 and 24 (21 and 20)
note 4
−
+1
THD
S/N(A)
Ro
total harmonic distortion
signal-to-noise ratio
note 4
−
0.1
80
0.5
−
%
dB
Ω
A-weighted; note 4
72
92
output resistance pins 25 and 24 note 4
(21 and 20)
125
150
MUTEatt
αS/S
mute attenuation
output selector in
position 6; note 4
74
−
−
−
dB
dB
dB
mV
crosstalk attenuation between
secondary channels
note 5
74
74
16
−
αM/S
crosstalk attenuation from main note 6
channel to secondary
−
−
Voffset(DC)
DC offset voltage on
attack/recovery capacitors
pins 29, 39 (25, 35)
all PLLs locked; ∆f = 0
14
20
SVRR
supply voltage ripple rejection
V
RR = 100 mV; fi = 70 Hz
−
25
−
dB
dB
Secondary channels - low-pass filter pins 38 and 30 (34 and 26)
50 kHz frequency response
with respect to 1 kHz
note 7
−25
−16
−9
VRECTL, RECTR (50 kHz)
----------------------------------------------------------
VRECTL, RECTR (1 kHz)
October 1994
11
Philips Semiconductors
Product specification
Satellite sound circuit with noise reduction
TDA8741; TDA8741H
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Secondary channels - noise reduction pins 25 and 24 (21 and 20); note 4
VOL,OR
output voltage at 0 dB noise
reduction input level
∆fS1 = ∆fS2 = 50 kHz;
no fixed de-emphasis
connected
−1
+1
0
+3
dBV
dB
15 kHz frequency response
with respect to 1 kHz at 0 dB
noise reduction input level
∆fS1 = ∆fS2 = 50 kHz;
no fixed de-emphasis
connected
−2
+2
VOL, OR (15 kHz)
---------------------------------------
VOL, OR (1 kHz)
VOL, OR
output voltage at −20 dB noise
reduction input level
∆fS1 = ∆fS2 = 5 kHz;
no fixed de-emphasis
connected
−29
−13
−26
−23
dBV
dB
15 kHz frequency response
with respect to 1 kHz at −20 dB no fixed de-emphasis
noise reduction input level connected
∆fS1 = ∆fS2 = 5 kHz;
−11.5 −10
V OL, OR (15 kHz)
---------------------------------------
VOL, OR (1 kHz)
External inputs - pin 28 (24) (left) and pin 27 (23) (right) - overall performance (output selector in position 5)
VEXTR,EXTL
Ri
input signal level
input resistance
output level
−
−
6
dBV
95
150
200
kΩ
VOL,OR
THD
VEXTR, EXTL = −6 dBV
−6.5 −6.0 −5.5 dBV
total harmonic distortion
VEXTR, EXTL = −6 dBV;
−
−
0.1
%
fi = 1 kHz
S/N(A)
signal-to-noise ratio
A-weighted;
80
−
−
−
dB
dB
VEXTR, EXTL = −6 dBV
αL/R,αR/L
crosstalk
fi = 1 kHz
80
−
Secondary channels PLLs disable [SCD pin 11 (6)]; pin 11 (6) left open-circuit = logic HIGH
VIL
VIH
Ri
LOW level input voltage
HIGH level input voltage
input resistance
0
−
1.2
9
V
3.5
65
−
V
connected to VP
100
130
kΩ
Output selector control circuit (see also Table 1) and main channel PLL lock-in select [MCS pin 7 (2)]; pins 15,
17, 26, 13 and 7 (10, 13, 22, 8 and 2) MOS inputs and should not be left open-circuit
VIL
LOW level input voltage limits
0
−
−
1.2
2.8
V
V
VIM
MID level input voltage limits for
MCS pin only
1.8
VIMF
MID level input voltage on MCS VP must be 1.8 to 13.2 V 17
pin if MCS pin is floating
19
21
%VP
VIH
RIL
HIGH level input voltage limits
3.5
12
−
VP
26
V
low input resistance MCS pin to
ground
19
kΩ
RIH
IIL
high input resistance MCS pin to
VP
52
−
80
108
−
kΩ
µA
µA
LOW level input current
(not MCS pin)
VIL = 0 V
VIH = 5 V
<−1
<1
IIH
HIGH level input current
(not MCS pin)
−
−
October 1994
12
Philips Semiconductors
Product specification
Satellite sound circuit with noise reduction
TDA8741; TDA8741H
Notes to the AC characteristics
1. At pin 20 (16) the demodulated 1 kHz signal should be present with a typical level of 158 mV (RMS) (−16 dBV), and
THD of maximum 0.5%; VP = 8 to 13.2 V; Tamb = −20 to +70 °C.
2. Modulation of main channel is OFF; modulation of secondary channels is ON.
3. The electrolytic capacitors at pins 40 and 42 (36 and 38) are removed and 1500 pF capacitors between pin 40 (36)
and ground and between pin 42 (38) and ground are connected. At pins 40 and 42 (36 and 38) the demodulated
1 kHz signals should be present with typical levels of 9 mV (RMS) and THD of maximum 0.5%; VP = 8 to 3.2 V;
Tamb = −20 to +70 °C.
4. All PLLs locked; RS1 = RS2 = 0.68 kΩ.
5. Modulation of secondary channel being measured and main channel is OFF; modulation of other secondary channel
is ON.
6. Modulation of main channel is ON; modulation of secondary channels is OFF.
7. Measured at pins 38 (34) (left) and 30 (26) (right) and no electrolytic capacitors connected to these pins.
Table 1 Truth table for output selection (note 1)
PIN 15 (10)
PIN 17 (13)
PIN 26 (22)
PIN 13 (8)
SWITCH
POSITION
STATE
stereo
OUTSEL L
OUTSEL R
EXT/INT
MUTE
1
2
3
4
5
6
7
1
1
0
0
X
X
X
1
0
1
0
X
X
X
0
0
0
0
1
0
1
0
0
0
0
0
1
1
left
right
main
external
mute secondary
mute all
Note
1. X = don’t care.
October 1994
13
Philips Semiconductors
Product specification
Satellite sound circuit with noise reduction
TDA8741; TDA8741H
October 1994
14
Philips Semiconductors
Product specification
Satellite sound circuit with noise reduction
TDA8741; TDA8741H
If simultaneous demodulation of main- and secondary
sound carriers is not required, a low cost solution as given
in Fig.6 can be considered. One mixer and frequency
synthesizer are used to transfer all sound carriers to
intermediate frequencies of 10.7 and 10.52 MHz. When
the bandwidth of the main channel is larger than the
secondary channel bandwidth, a separate (e.g. 10.7 MHz)
ceramic filter plus resistors are required for the main
channel.
APPLICATION INFORMATION
General
The satellite baseband signal is routed to a mixer to
transfer the various secondary channels to fixed
intermediate frequencies of 10.7 and 10.52 MHz. Tuning
to the required carrier frequencies can be achieved by
varying the oscillator frequency e.g. tuning to 7.02 and
7.20 MHz carrier frequencies requires an oscillator
frequency of 17.72 MHz and tuning to 7.38 and 7.56 MHz
requires an oscillator frequency of 18.08 MHz. The IF
signals are routed to the inputs pin 8 and 16 (3 and 11) via
10.7 and 10.52 MHz ceramic bandpass filters. For the
secondary channels the bandpass filter terminating
resistor is integrated on-chip (330 Ω typical) thus no
external resistors are required.
The secondary sound carriers can be demodulated as
described above. If e.g. a 6.65 MHz main sound carrier is
to be demodulated, this frequency is mixed to 10.7 MHz by
tuning the frequency synthesizer to 17.35 MHz. If the
synthesizer is tuned to 17.20 MHz a 6.5 MHz main sound
carrier can be demodulated. When main sound is to be
demodulated and this IF signal is also available on the
secondary Channel 1 input the PLLs of the secondary
channels can be disabled by making SCD pin 11 (6) HIGH.
The output selector should be in position 4 (main sound on
all outputs) if output pins 25 and 24 (21 and 20) are used.
MCS pin 7 (2) = logic 0; (see Fig.5)
The lock-in range of the main channel PLL is 5.5 to
7.5 MHz. For the main channel a ceramic bandpass filter
(e.g. 6.5 MHz) is used to filter out the main sound carrier
directly from the baseband signal. Simultaneous
demodulation of one main channel and various secondary
channels is now possible with a minimum of external
components. As no bandpass filter terminating resistor for
the main channel pin 18 (14) is integrated on-chip, an
external resistor is required.
For high-end applications the input level of the NR can be
adjusted to give optimum performance. 0 dB is the
maximum input level which corresponds to the maximum
frequency deviation of the incoming FM signal (50 kHz for
secondary channels). If the NR input signal is too low
(HIGH) the NR will attenuate (favour) the higher audio
frequencies too much due to the expansion character. In
general: 1 dB error in NR input level will give a 1 dB
difference between low (50 Hz) and high (15 kHz) audio
frequencies. With RS1 (RS2) the input level and so the
frequency response of the NR can be adjusted: at 0 dB
input level (which corresponds to a frequency deviation of
50 kHz) the output level of a 15 kHz modulated signal
should be 0.25 dB lower than that of an 50 Hz modulated
signal.
MCS pin 7 (2) = logic 1; (see Fig.6)
The lock-in range of the main channel PLL is now 10.0 to
11.5 MHz. The carrier frequency of the main channel is
also transferred to a fixed intermediate frequency. In this
event the main audio output level should be adjusted to
−6 dBV by inserting a 470 Ω resistor in series with the
electrolytic capacitor on pin 41 (37).
MCS pin 7 (2) = MID position
The main channel PLL is off if the voltage is between 1.8
and 2.8 V on pin 7 (2). This situation can be obtained by a
floating MCS pin if VP is between 10.8 and 13.2 V or by
forcing this MCS pin to the desired voltage by an external
voltage source. In that event VP can be in the full range of
8 to 13.2 V. This feature can be used to slightly improve
the signal-to-noise ratio of the secondary channels if the
main channel is not used.
October 1994
15
Philips Semiconductors
Product specification
Satellite sound circuit with noise reduction
TDA8741; TDA8741H
October 1994
16
Philips Semiconductors
Product specification
Satellite sound circuit with noise reduction
TDA8741; TDA8741H
October 1994
17
Philips Semiconductors
Product specification
Satellite sound circuit with noise reduction
TDA8741; TDA8741H
PACKAGE OUTLINES
39.0
38.4
15.80
15.24
4.57
max
5.08
max
3.2
2.9
0.51
min
0.32 max
15.24
M
0.18
1.73
max
0.53
max
1.778
(40x)
17.15
15.90
1.3 max
MSA268 - 1
22
42
14.1
13.7
1
21
Dimensions in mm.
Fig.7 Plastic shrink dual in-line package; 42 leads (600 mil); SDIP42; SOT270-1.
October 1994
18
Philips Semiconductors
Product specification
Satellite sound circuit with noise reduction
TDA8741; TDA8741H
seating
plane
S
0.1 S
12.9
12.3
1.2
0.8
(4x)
44
34
B
33
1
pin 1 index
0.8
10.1 12.9
9.9 12.3
0.40
0.20
11
23
12
22
1.2
0.8
(4x)
0.40
0.20
0.15 M
A
X
0.8
10.1
9.9
A
0.85
0.75
1.85
1.65
2.10
1.70
0.25
0.14
0.25
0.05
o
0 to 10
0.95
0.55
detail X
MBB944 - 2
Dimensions in mm.
Fig.8 Plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 × 10 × 1.75 mm (QFP44; SOT307-2).
October 1994
19
Philips Semiconductors
Product specification
Satellite sound circuit with noise reduction
TDA8741; TDA8741H
SOLDERING
BY SOLDER PASTE REFLOW
Reflow soldering requires the solder paste (a suspension
of fine solder particles, flux and binding agent) to be
applied to the substrate by screen printing, stencilling or
pressure-syringe dispensing before device placement.
Plastic dual in-line packages
BY DIP OR WAVE
The maximum permissible temperature of the solder is
260 °C; this temperature must not be in contact with the
joint for more than 5 s. The total contact time of successive
solder waves must not exceed 5 s.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt, infrared, and
vapour-phase reflow. Dwell times vary between 50 and
300 s according to method. Typical reflow temperatures
range from 215 to 250 °C.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified storage maximum. If the printed-circuit board has
been pre-heated, forced cooling may be necessary
immediately after soldering to keep the temperature within
the permissible limit.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 min at 45 °C.
REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING
IRON OR PULSE-HEATED SOLDER TOOL)
REPAIRING SOLDERED JOINTS
Fix the component by first soldering two, diagonally
opposite, end pins. Apply the heating tool to the flat part of
the pin only. Contact time must be limited to 10 s at up to
300 °C. When using proper tools, all other pins can be
soldered in one operation within 2 to 5 s at between 270
and 320 °C. (Pulse-heated soldering is not recommended
for SO packages.)
Apply the soldering iron below the seating plane (or not
more than 2 mm above it). If its temperature is below
300 °C, it must not be in contact for more than 10 s; if
between 300 and 400 °C, for not more than 5 s.
Plastic quad flat packages
BY WAVE
For pulse-heated solder tool (resistance) soldering of VSO
packages, solder is applied to the substrate by dipping or
by an extra thick tin/lead plating before package
placement.
During placement and before soldering, the component
must be fixed with a droplet of adhesive. After curing the
adhesive, the component can be soldered. The adhesive
can be applied by screen printing, pin transfer or syringe
dispensing.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder bath is
10 s, if allowed to cool to less than 150 °C within 6 s.
Typical dwell time is 4 s at 250 °C.
A modified wave soldering technique is recommended
using two solder waves (dual-wave), in which a turbulent
wave with high upward pressure is followed by a smooth
laminar wave. Using a mildly-activated flux eliminates the
need for removal of corrosive residues in most
applications.
October 1994
20
Philips Semiconductors
Product specification
Satellite sound circuit with noise reduction
TDA8741; TDA8741H
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
October 1994
21
Philips Semiconductors
Product specification
Satellite sound circuit with noise reduction
TDA8741; TDA8741H
NOTES
October 1994
22
Philips Semiconductors
Product specification
Satellite sound circuit with noise reduction
TDA8741; TDA8741H
NOTES
October 1994
23
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Date of release: October 1994
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